lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // (outs Result), (ins Imm, OpCmode)
  19 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  20
  21 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  22
  23 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  24
  25 // (outs Result), (ins Imm)
  26 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  27                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  28
  29 // (outs Result), (ins LHS, RHS, CondCode)
  30 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  31                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  32
  33 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  34 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  35                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  36
  37 // (outs Result), (ins LHS, RHS)
  38 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  39                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  40
  41 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  42                                      SDTCisVT<2, i32>]>;
  43 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  44 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  45
  46 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  47                                SDTCisSameAs<0, 2>]>;
  48 def Neon_uzp1    : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
  49 def Neon_uzp2    : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
  50 def Neon_zip1    : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
  51 def Neon_zip2    : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
  52 def Neon_trn1    : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
  53 def Neon_trn2    : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
  54
  55 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
  56 def Neon_rev64    : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
  57 def Neon_rev32    : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
  58 def Neon_rev16    : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
  59 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  60                        [SDTCisVec<0>]>>;
  61 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  62                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  63 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
  64                            [SDTCisVec<0>,  SDTCisSameAs<0, 1>,
  65                            SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
  66
  67 def SDT_assertext : SDTypeProfile<1, 1,
  68   [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
  69 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
  70 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
  71
  72 //===----------------------------------------------------------------------===//
  73 // Addressing-mode instantiations
  74 //===----------------------------------------------------------------------===//
  75
  76 multiclass ls_64_pats<dag address, dag Base, dag Offset, ValueType Ty> {
  77 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
  78                       !foreach(decls.pattern, Offset,
  79                                !subst(OFFSET, dword_uimm12, decls.pattern)),
  80                       !foreach(decls.pattern, address,
  81                                !subst(OFFSET, dword_uimm12,
  82                                !subst(ALIGN, min_align8, decls.pattern))),
  83                       Ty>;
  84 }
  85
  86 multiclass ls_128_pats<dag address, dag Base, dag Offset, ValueType Ty> {
  87 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
  88                        !foreach(decls.pattern, Offset,
  89                                 !subst(OFFSET, qword_uimm12, decls.pattern)),
  90                        !foreach(decls.pattern, address,
  91                                 !subst(OFFSET, qword_uimm12,
  92                                 !subst(ALIGN, min_align16, decls.pattern))),
  93                       Ty>;
  94 }
  95
  96 multiclass uimm12_neon_pats<dag address, dag Base, dag Offset> {
  97   defm : ls_64_pats<address, Base, Offset, v8i8>;
  98   defm : ls_64_pats<address, Base, Offset, v4i16>;
  99   defm : ls_64_pats<address, Base, Offset, v2i32>;
 100   defm : ls_64_pats<address, Base, Offset, v1i64>;
 101   defm : ls_64_pats<address, Base, Offset, v2f32>;
 102   defm : ls_64_pats<address, Base, Offset, v1f64>;
 103
 104   defm : ls_128_pats<address, Base, Offset, v16i8>;
 105   defm : ls_128_pats<address, Base, Offset, v8i16>;
 106   defm : ls_128_pats<address, Base, Offset, v4i32>;
 107   defm : ls_128_pats<address, Base, Offset, v2i64>;
 108   defm : ls_128_pats<address, Base, Offset, v4f32>;
 109   defm : ls_128_pats<address, Base, Offset, v2f64>;
 110 }
 111
 112 defm : uimm12_neon_pats<(A64WrapperSmall
 113                           tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
 114                         (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
 115
 116 //===----------------------------------------------------------------------===//
 117 // Multiclasses
 118 //===----------------------------------------------------------------------===//
 119
 120 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
 121                                 string asmop, SDPatternOperator opnode8B,
 122                                 SDPatternOperator opnode16B,
 123                                 bit Commutable = 0> {
 124   let isCommutable = Commutable in {
 125     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
 126                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 127                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 128                [(set (v8i8 VPR64:$Rd),
 129                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 130                NoItinerary>;
 131
 132     def _16B : NeonI_3VSame<0b1, u, size, opcode,
 133                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 134                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 135                [(set (v16i8 VPR128:$Rd),
 136                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 137                NoItinerary>;
 138   }
 139
 140 }
 141
 142 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
 143                                   string asmop, SDPatternOperator opnode,
 144                                   bit Commutable = 0> {
 145   let isCommutable = Commutable in {
 146     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
 147               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 148               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
 149               [(set (v4i16 VPR64:$Rd),
 150                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
 151               NoItinerary>;
 152
 153     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
 154               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 155               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
 156               [(set (v8i16 VPR128:$Rd),
 157                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
 158               NoItinerary>;
 159
 160     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 161               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 162               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 163               [(set (v2i32 VPR64:$Rd),
 164                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 165               NoItinerary>;
 166
 167     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 168               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 169               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 170               [(set (v4i32 VPR128:$Rd),
 171                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 172               NoItinerary>;
 173   }
 174 }
 175 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 176                                   string asmop, SDPatternOperator opnode,
 177                                   bit Commutable = 0>
 178    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable> {
 179   let isCommutable = Commutable in {
 180     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 181                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 182                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 183                [(set (v8i8 VPR64:$Rd),
 184                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 185                NoItinerary>;
 186
 187     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 188                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 189                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 190                [(set (v16i8 VPR128:$Rd),
 191                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 192                NoItinerary>;
 193   }
 194 }
 195
 196 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 197                                    string asmop, SDPatternOperator opnode,
 198                                    bit Commutable = 0>
 199    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable> {
 200   let isCommutable = Commutable in {
 201     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 202               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 203               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 204               [(set (v2i64 VPR128:$Rd),
 205                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 206               NoItinerary>;
 207   }
 208 }
 209
 210 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 211 // but Result types can be integer or floating point types.
 212 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 213                                  string asmop, SDPatternOperator opnode2S,
 214                                  SDPatternOperator opnode4S,
 215                                  SDPatternOperator opnode2D,
 216                                  ValueType ResTy2S, ValueType ResTy4S,
 217                                  ValueType ResTy2D, bit Commutable = 0> {
 218   let isCommutable = Commutable in {
 219     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 220               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 221               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 222               [(set (ResTy2S VPR64:$Rd),
 223                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 224               NoItinerary>;
 225
 226     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 227               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 228               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 229               [(set (ResTy4S VPR128:$Rd),
 230                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 231               NoItinerary>;
 232
 233     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 234               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 235               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 236               [(set (ResTy2D VPR128:$Rd),
 237                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 238                NoItinerary>;
 239   }
 240 }
 241
 242 //===----------------------------------------------------------------------===//
 243 // Instruction Definitions
 244 //===----------------------------------------------------------------------===//
 245
 246 // Vector Arithmetic Instructions
 247
 248 // Vector Add (Integer and Floating-Point)
 249
 250 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 251 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 252                                      v2f32, v4f32, v2f64, 1>;
 253
 254 // Vector Sub (Integer and Floating-Point)
 255
 256 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 257 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 258                                      v2f32, v4f32, v2f64, 0>;
 259
 260 // Vector Multiply (Integer and Floating-Point)
 261
 262 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 263 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 264                                      v2f32, v4f32, v2f64, 1>;
 265
 266 // Vector Multiply (Polynomial)
 267
 268 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 269                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 270
 271 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 272
 273 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 274 // two operands constraints.
 275 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 276   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 277   bits<5> opcode, SDPatternOperator opnode>
 278   : NeonI_3VSame<q, u, size, opcode,
 279     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 280     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 281     [(set (OpTy VPRC:$Rd),
 282        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 283     NoItinerary> {
 284   let Constraints = "$src = $Rd";
 285 }
 286
 287 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 288                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 289
 290 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 291                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 292
 293
 294 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 295                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 296 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 297                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 298 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 299                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 300 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 301                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 302 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 303                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 304 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 305                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 306
 307 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 308                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 309 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 310                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 311 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 312                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 313 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 314                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 315 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 316                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 317 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 318                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 319
 320 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 321
 322 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 323                         (fadd node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
 324
 325 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 326                         (fsub node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
 327
 328 let Predicates = [HasNEON, UseFusedMAC] in {
 329 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 330                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 331 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 332                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 333 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 334                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 335
 336 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 337                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 338 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 339                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 340 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 341                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 342 }
 343
 344 // We're also allowed to match the fma instruction regardless of compile
 345 // options.
 346 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 347           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 348 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 349           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 350 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 351           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 352
 353 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 354           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 355 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 356           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 357 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 358           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 359
 360 // Vector Divide (Floating-Point)
 361
 362 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 363                                      v2f32, v4f32, v2f64, 0>;
 364
 365 // Vector Bitwise Operations
 366
 367 // Vector Bitwise AND
 368
 369 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 370
 371 // Vector Bitwise Exclusive OR
 372
 373 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 374
 375 // Vector Bitwise OR
 376
 377 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 378
 379 // ORR disassembled as MOV if Vn==Vm
 380
 381 // Vector Move - register
 382 // Alias for ORR if Vn=Vm.
 383 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 384 // custom printing of aliases.
 385 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 386                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 387 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 388                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 389
 390 // The MOVI instruction takes two immediate operands.  The first is the
 391 // immediate encoding, while the second is the cmode.  A cmode of 14, or
 392 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
 393 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
 394 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
 395
 396 def Neon_not8B  : PatFrag<(ops node:$in),
 397                           (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
 398 def Neon_not16B : PatFrag<(ops node:$in),
 399                           (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
 400
 401 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 402                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 403
 404 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 405                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 406
 407 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 408                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 409
 410 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 411                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 412
 413
 414 // Vector Bitwise OR NOT - register
 415
 416 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 417                                    Neon_orn8B, Neon_orn16B, 0>;
 418
 419 // Vector Bitwise Bit Clear (AND NOT) - register
 420
 421 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 422                                    Neon_bic8B, Neon_bic16B, 0>;
 423
 424 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 425                                    SDPatternOperator opnode16B,
 426                                    Instruction INST8B,
 427                                    Instruction INST16B> {
 428   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 429             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 430   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 431             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 432   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 433             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 434   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 435             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 436   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 437             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 438   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 439             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 440 }
 441
 442 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 443 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 444 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 445 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 446 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 447 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 448
 449 //   Vector Bitwise Select
 450 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 451                                               0b0, 0b1, 0b01, 0b00011, vselect>;
 452
 453 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 454                                               0b1, 0b1, 0b01, 0b00011, vselect>;
 455
 456 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 457                                    Instruction INST8B,
 458                                    Instruction INST16B> {
 459   // Disassociate type from instruction definition
 460   def : Pat<(v8i8 (opnode (v8i8 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 461             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 462   def : Pat<(v2i32 (opnode (v2i32 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 463             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 464   def : Pat<(v4i16 (opnode (v4i16 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 465             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 466   def : Pat<(v1i64 (opnode (v1i64 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 467             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 468   def : Pat<(v16i8 (opnode (v16i8 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 469             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 470   def : Pat<(v4i32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 471             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 472   def : Pat<(v8i16 (opnode (v8i16 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 473             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 474   def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 475             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 476   def : Pat<(v2f64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 477             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 478   def : Pat<(v4f32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 479             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 480
 481   // Allow to match BSL instruction pattern with non-constant operand
 482   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 483                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 484           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 485   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 486                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 487           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 488   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 489                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 490           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 491   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 492                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 493           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 494   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 495                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 496           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 497   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 498                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 499           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 500   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 501                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 502           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 503   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 504                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 505           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 506
 507   // Allow to match llvm.arm.* intrinsics.
 508   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 509                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 510             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 511   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 512                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 513             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 514   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 515                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 516             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 517   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 518                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 519             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 520   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 521                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 522             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 523   def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
 524                     (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
 525             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 526   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 527                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 528             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 529   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 530                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 531             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 532   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 533                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 534             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 535   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 536                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 537             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 538   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 539                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 540             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 541   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 542                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 543             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 544 }
 545
 546 // Additional patterns for bitwise instruction BSL
 547 defm: Neon_bitwise3V_patterns<vselect, BSLvvv_8B, BSLvvv_16B>;
 548
 549 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 550                            (vselect node:$src, node:$Rn, node:$Rm),
 551                            [{ (void)N; return false; }]>;
 552
 553 // Vector Bitwise Insert if True
 554
 555 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 556                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 557 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 558                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 559
 560 // Vector Bitwise Insert if False
 561
 562 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 563                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 564 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 565                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 566
 567 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 568
 569 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 570                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 571 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 572                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 573
 574 // Vector Absolute Difference and Accumulate (Unsigned)
 575 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 576                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 577 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 578                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 579 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 580                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 581 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 582                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 583 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 584                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 585 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 586                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 587
 588 // Vector Absolute Difference and Accumulate (Signed)
 589 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 590                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 591 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 592                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 593 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 594                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 595 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 596                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 597 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 598                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 599 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 600                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 601
 602
 603 // Vector Absolute Difference (Signed, Unsigned)
 604 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 605 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 606
 607 // Vector Absolute Difference (Floating Point)
 608 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 609                                     int_arm_neon_vabds, int_arm_neon_vabds,
 610                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 611
 612 // Vector Reciprocal Step (Floating Point)
 613 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 614                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 615                                        int_arm_neon_vrecps,
 616                                        v2f32, v4f32, v2f64, 0>;
 617
 618 // Vector Reciprocal Square Root Step (Floating Point)
 619 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 620                                         int_arm_neon_vrsqrts,
 621                                         int_arm_neon_vrsqrts,
 622                                         int_arm_neon_vrsqrts,
 623                                         v2f32, v4f32, v2f64, 0>;
 624
 625 // Vector Comparisons
 626
 627 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 628                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 629 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 630                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 631 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 632                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 633 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 634                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 635 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 636                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 637
 638 // NeonI_compare_aliases class: swaps register operands to implement
 639 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 640 class NeonI_compare_aliases<string asmop, string asmlane,
 641                             Instruction inst, RegisterOperand VPRC>
 642   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 643                     ", $Rm" # asmlane,
 644                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 645
 646 // Vector Comparisons (Integer)
 647
 648 // Vector Compare Mask Equal (Integer)
 649 let isCommutable =1 in {
 650 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 651 }
 652
 653 // Vector Compare Mask Higher or Same (Unsigned Integer)
 654 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 655
 656 // Vector Compare Mask Greater Than or Equal (Integer)
 657 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 658
 659 // Vector Compare Mask Higher (Unsigned Integer)
 660 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 661
 662 // Vector Compare Mask Greater Than (Integer)
 663 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 664
 665 // Vector Compare Mask Bitwise Test (Integer)
 666 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 667
 668 // Vector Compare Mask Less or Same (Unsigned Integer)
 669 // CMLS is alias for CMHS with operands reversed.
 670 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 671 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 672 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 673 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 674 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 675 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 676 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 677
 678 // Vector Compare Mask Less Than or Equal (Integer)
 679 // CMLE is alias for CMGE with operands reversed.
 680 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 681 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 682 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 683 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 684 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 685 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 686 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 687
 688 // Vector Compare Mask Lower (Unsigned Integer)
 689 // CMLO is alias for CMHI with operands reversed.
 690 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 691 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 692 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 693 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 694 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 695 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 696 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 697
 698 // Vector Compare Mask Less Than (Integer)
 699 // CMLT is alias for CMGT with operands reversed.
 700 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 701 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 702 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 703 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 704 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 705 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 706 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 707
 708
 709 def neon_uimm0_asmoperand : AsmOperandClass
 710 {
 711   let Name = "UImm0";
 712   let PredicateMethod = "isUImm<0>";
 713   let RenderMethod = "addImmOperands";
 714 }
 715
 716 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 717   let ParserMatchClass = neon_uimm0_asmoperand;
 718   let PrintMethod = "printNeonUImm0Operand";
 719
 720 }
 721
 722 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 723 {
 724   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 725              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 726              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 727              [(set (v8i8 VPR64:$Rd),
 728                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 729              NoItinerary>;
 730
 731   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 732              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 733              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 734              [(set (v16i8 VPR128:$Rd),
 735                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 736              NoItinerary>;
 737
 738   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 739             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 740             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 741             [(set (v4i16 VPR64:$Rd),
 742                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 743             NoItinerary>;
 744
 745   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 746             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 747             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 748             [(set (v8i16 VPR128:$Rd),
 749                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 750             NoItinerary>;
 751
 752   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 753             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 754             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 755             [(set (v2i32 VPR64:$Rd),
 756                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 757             NoItinerary>;
 758
 759   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 760             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 761             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 762             [(set (v4i32 VPR128:$Rd),
 763                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 764             NoItinerary>;
 765
 766   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 767             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 768             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 769             [(set (v2i64 VPR128:$Rd),
 770                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 771             NoItinerary>;
 772 }
 773
 774 // Vector Compare Mask Equal to Zero (Integer)
 775 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 776
 777 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 778 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 779
 780 // Vector Compare Mask Greater Than Zero (Signed Integer)
 781 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 782
 783 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 784 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 785
 786 // Vector Compare Mask Less Than Zero (Signed Integer)
 787 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 788
 789 // Vector Comparisons (Floating Point)
 790
 791 // Vector Compare Mask Equal (Floating Point)
 792 let isCommutable =1 in {
 793 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 794                                       Neon_cmeq, Neon_cmeq,
 795                                       v2i32, v4i32, v2i64, 0>;
 796 }
 797
 798 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 799 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 800                                       Neon_cmge, Neon_cmge,
 801                                       v2i32, v4i32, v2i64, 0>;
 802
 803 // Vector Compare Mask Greater Than (Floating Point)
 804 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 805                                       Neon_cmgt, Neon_cmgt,
 806                                       v2i32, v4i32, v2i64, 0>;
 807
 808 // Vector Compare Mask Less Than Or Equal (Floating Point)
 809 // FCMLE is alias for FCMGE with operands reversed.
 810 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 811 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 812 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 813
 814 // Vector Compare Mask Less Than (Floating Point)
 815 // FCMLT is alias for FCMGT with operands reversed.
 816 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 817 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 818 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 819
 820 def fpzero_izero_asmoperand : AsmOperandClass {
 821   let Name = "FPZeroIZero";
 822   let ParserMethod = "ParseFPImm0AndImm0Operand";
 823   let DiagnosticType = "FPZero";
 824 }
 825
 826 def fpzz32 : Operand<f32>,
 827              ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
 828   let ParserMatchClass = fpzero_izero_asmoperand;
 829   let PrintMethod = "printFPZeroOperand";
 830   let DecoderMethod = "DecodeFPZeroOperand";
 831 }
 832
 833 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 834                               string asmop, CondCode CC>
 835 {
 836   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 837             (outs VPR64:$Rd), (ins VPR64:$Rn, fpzz32:$FPImm),
 838             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 839             [(set (v2i32 VPR64:$Rd),
 840                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpzz32:$FPImm), CC)))],
 841             NoItinerary>;
 842
 843   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 844             (outs VPR128:$Rd), (ins VPR128:$Rn, fpzz32:$FPImm),
 845             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 846             [(set (v4i32 VPR128:$Rd),
 847                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpzz32:$FPImm), CC)))],
 848             NoItinerary>;
 849
 850   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 851             (outs VPR128:$Rd), (ins VPR128:$Rn, fpzz32:$FPImm),
 852             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 853             [(set (v2i64 VPR128:$Rd),
 854                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpzz32:$FPImm), CC)))],
 855             NoItinerary>;
 856 }
 857
 858 // Vector Compare Mask Equal to Zero (Floating Point)
 859 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 860
 861 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 862 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 863
 864 // Vector Compare Mask Greater Than Zero (Floating Point)
 865 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 866
 867 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 868 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 869
 870 // Vector Compare Mask Less Than Zero (Floating Point)
 871 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 872
 873 // Vector Absolute Comparisons (Floating Point)
 874
 875 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 876 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 877                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 878                                       int_aarch64_neon_vacgeq,
 879                                       v2i32, v4i32, v2i64, 0>;
 880
 881 // Vector Absolute Compare Mask Greater Than (Floating Point)
 882 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 883                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 884                                       int_aarch64_neon_vacgtq,
 885                                       v2i32, v4i32, v2i64, 0>;
 886
 887 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 888 // FACLE is alias for FACGE with operands reversed.
 889 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 890 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 891 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 892
 893 // Vector Absolute Compare Mask Less Than (Floating Point)
 894 // FACLT is alias for FACGT with operands reversed.
 895 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 896 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 897 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 898
 899 // Vector halving add (Integer Signed, Unsigned)
 900 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 901                                         int_arm_neon_vhadds, 1>;
 902 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 903                                         int_arm_neon_vhaddu, 1>;
 904
 905 // Vector halving sub (Integer Signed, Unsigned)
 906 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 907                                         int_arm_neon_vhsubs, 0>;
 908 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 909                                         int_arm_neon_vhsubu, 0>;
 910
 911 // Vector rouding halving add (Integer Signed, Unsigned)
 912 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 913                                          int_arm_neon_vrhadds, 1>;
 914 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 915                                          int_arm_neon_vrhaddu, 1>;
 916
 917 // Vector Saturating add (Integer Signed, Unsigned)
 918 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 919                    int_arm_neon_vqadds, 1>;
 920 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 921                    int_arm_neon_vqaddu, 1>;
 922
 923 // Vector Saturating sub (Integer Signed, Unsigned)
 924 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 925                    int_arm_neon_vqsubs, 1>;
 926 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 927                    int_arm_neon_vqsubu, 1>;
 928
 929 // Vector Shift Left (Signed and Unsigned Integer)
 930 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 931                  int_arm_neon_vshifts, 1>;
 932 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 933                  int_arm_neon_vshiftu, 1>;
 934
 935 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 936 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 937                   int_arm_neon_vqshifts, 1>;
 938 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 939                   int_arm_neon_vqshiftu, 1>;
 940
 941 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 942 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 943                   int_arm_neon_vrshifts, 1>;
 944 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 945                   int_arm_neon_vrshiftu, 1>;
 946
 947 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 948 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 949                    int_arm_neon_vqrshifts, 1>;
 950 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 951                    int_arm_neon_vqrshiftu, 1>;
 952
 953 // Vector Maximum (Signed and Unsigned Integer)
 954 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 955 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 956
 957 // Vector Minimum (Signed and Unsigned Integer)
 958 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 959 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 960
 961 // Vector Maximum (Floating Point)
 962 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 963                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 964                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 965
 966 // Vector Minimum (Floating Point)
 967 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 968                                      int_arm_neon_vmins, int_arm_neon_vmins,
 969                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 970
 971 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 972 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 973                                        int_aarch64_neon_vmaxnm,
 974                                        int_aarch64_neon_vmaxnm,
 975                                        int_aarch64_neon_vmaxnm,
 976                                        v2f32, v4f32, v2f64, 1>;
 977
 978 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 979 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 980                                        int_aarch64_neon_vminnm,
 981                                        int_aarch64_neon_vminnm,
 982                                        int_aarch64_neon_vminnm,
 983                                        v2f32, v4f32, v2f64, 1>;
 984
 985 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 986 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 987 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 988
 989 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 990 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 991 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 992
 993 // Vector Maximum Pairwise (Floating Point)
 994 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 995                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 996                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 997
 998 // Vector Minimum Pairwise (Floating Point)
 999 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
1000                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
1001                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
1002
1003 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
1004 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
1005                                        int_aarch64_neon_vpmaxnm,
1006                                        int_aarch64_neon_vpmaxnm,
1007                                        int_aarch64_neon_vpmaxnm,
1008                                        v2f32, v4f32, v2f64, 1>;
1009
1010 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
1011 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
1012                                        int_aarch64_neon_vpminnm,
1013                                        int_aarch64_neon_vpminnm,
1014                                        int_aarch64_neon_vpminnm,
1015                                        v2f32, v4f32, v2f64, 1>;
1016
1017 // Vector Addition Pairwise (Integer)
1018 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
1019
1020 // Vector Addition Pairwise (Floating Point)
1021 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
1022                                        int_arm_neon_vpadd,
1023                                        int_arm_neon_vpadd,
1024                                        int_arm_neon_vpadd,
1025                                        v2f32, v4f32, v2f64, 1>;
1026
1027 // Vector Saturating Doubling Multiply High
1028 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
1029                     int_arm_neon_vqdmulh, 1>;
1030
1031 // Vector Saturating Rouding Doubling Multiply High
1032 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
1033                      int_arm_neon_vqrdmulh, 1>;
1034
1035 // Vector Multiply Extended (Floating Point)
1036 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
1037                                       int_aarch64_neon_vmulx,
1038                                       int_aarch64_neon_vmulx,
1039                                       int_aarch64_neon_vmulx,
1040                                       v2f32, v4f32, v2f64, 1>;
1041
1042 // Patterns to match llvm.aarch64.* intrinsic for
1043 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
1044 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
1045   : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
1046         (EXTRACT_SUBREG
1047              (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
1048              sub_32)>;
1049
1050 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
1051 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
1052 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
1053 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
1054 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
1055
1056 // Vector Immediate Instructions
1057
1058 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
1059 {
1060   def _asmoperand : AsmOperandClass
1061     {
1062       let Name = "NeonMovImmShift" # PREFIX;
1063       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1064       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1065     }
1066 }
1067
1068 // Definition of vector immediates shift operands
1069
1070 // The selectable use-cases extract the shift operation
1071 // information from the OpCmode fields encoded in the immediate.
1072 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1073   uint64_t OpCmode = N->getZExtValue();
1074   unsigned ShiftImm;
1075   unsigned ShiftOnesIn;
1076   unsigned HasShift =
1077     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1078   if (!HasShift) return SDValue();
1079   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1080 }]>;
1081
1082 // Vector immediates shift operands which accept LSL and MSL
1083 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1084 // or 0, 8 (LSLH) or 8, 16 (MSL).
1085 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1086 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1087 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
1088 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1089
1090 multiclass neon_mov_imm_shift_operands<string PREFIX,
1091                                        string HALF, string ISHALF, code pred>
1092 {
1093    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1094     {
1095       let PrintMethod =
1096         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1097       let DecoderMethod =
1098         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1099       let ParserMatchClass =
1100         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1101     }
1102 }
1103
1104 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1105   unsigned ShiftImm;
1106   unsigned ShiftOnesIn;
1107   unsigned HasShift =
1108     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1109   return (HasShift && !ShiftOnesIn);
1110 }]>;
1111
1112 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1113   unsigned ShiftImm;
1114   unsigned ShiftOnesIn;
1115   unsigned HasShift =
1116     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1117   return (HasShift && ShiftOnesIn);
1118 }]>;
1119
1120 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1121   unsigned ShiftImm;
1122   unsigned ShiftOnesIn;
1123   unsigned HasShift =
1124     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1125   return (HasShift && !ShiftOnesIn);
1126 }]>;
1127
1128 def neon_uimm1_asmoperand : AsmOperandClass
1129 {
1130   let Name = "UImm1";
1131   let PredicateMethod = "isUImm<1>";
1132   let RenderMethod = "addImmOperands";
1133 }
1134
1135 def neon_uimm2_asmoperand : AsmOperandClass
1136 {
1137   let Name = "UImm2";
1138   let PredicateMethod = "isUImm<2>";
1139   let RenderMethod = "addImmOperands";
1140 }
1141
1142 def neon_uimm8_asmoperand : AsmOperandClass
1143 {
1144   let Name = "UImm8";
1145   let PredicateMethod = "isUImm<8>";
1146   let RenderMethod = "addImmOperands";
1147 }
1148
1149 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1150   let ParserMatchClass = neon_uimm8_asmoperand;
1151   let PrintMethod = "printUImmHexOperand";
1152 }
1153
1154 def neon_uimm64_mask_asmoperand : AsmOperandClass
1155 {
1156   let Name = "NeonUImm64Mask";
1157   let PredicateMethod = "isNeonUImm64Mask";
1158   let RenderMethod = "addNeonUImm64MaskOperands";
1159 }
1160
1161 // MCOperand for 64-bit bytemask with each byte having only the
1162 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1163 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1164   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1165   let PrintMethod = "printNeonUImm64MaskOperand";
1166 }
1167
1168 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1169                                    SDPatternOperator opnode>
1170 {
1171     // shift zeros, per word
1172     def _2S  : NeonI_1VModImm<0b0, op,
1173                               (outs VPR64:$Rd),
1174                               (ins neon_uimm8:$Imm,
1175                                 neon_mov_imm_LSL_operand:$Simm),
1176                               !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1177                               [(set (v2i32 VPR64:$Rd),
1178                                  (v2i32 (opnode (timm:$Imm),
1179                                    (neon_mov_imm_LSL_operand:$Simm))))],
1180                               NoItinerary> {
1181        bits<2> Simm;
1182        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1183      }
1184
1185     def _4S  : NeonI_1VModImm<0b1, op,
1186                               (outs VPR128:$Rd),
1187                               (ins neon_uimm8:$Imm,
1188                                 neon_mov_imm_LSL_operand:$Simm),
1189                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1190                               [(set (v4i32 VPR128:$Rd),
1191                                  (v4i32 (opnode (timm:$Imm),
1192                                    (neon_mov_imm_LSL_operand:$Simm))))],
1193                               NoItinerary> {
1194       bits<2> Simm;
1195       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1196     }
1197
1198     // shift zeros, per halfword
1199     def _4H  : NeonI_1VModImm<0b0, op,
1200                               (outs VPR64:$Rd),
1201                               (ins neon_uimm8:$Imm,
1202                                 neon_mov_imm_LSLH_operand:$Simm),
1203                               !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1204                               [(set (v4i16 VPR64:$Rd),
1205                                  (v4i16 (opnode (timm:$Imm),
1206                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1207                               NoItinerary> {
1208       bit  Simm;
1209       let cmode = {0b1, 0b0, Simm, 0b0};
1210     }
1211
1212     def _8H  : NeonI_1VModImm<0b1, op,
1213                               (outs VPR128:$Rd),
1214                               (ins neon_uimm8:$Imm,
1215                                 neon_mov_imm_LSLH_operand:$Simm),
1216                               !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1217                               [(set (v8i16 VPR128:$Rd),
1218                                  (v8i16 (opnode (timm:$Imm),
1219                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1220                               NoItinerary> {
1221       bit Simm;
1222       let cmode = {0b1, 0b0, Simm, 0b0};
1223      }
1224 }
1225
1226 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1227                                                    SDPatternOperator opnode,
1228                                                    SDPatternOperator neonopnode>
1229 {
1230   let Constraints = "$src = $Rd" in {
1231     // shift zeros, per word
1232     def _2S  : NeonI_1VModImm<0b0, op,
1233                  (outs VPR64:$Rd),
1234                  (ins VPR64:$src, neon_uimm8:$Imm,
1235                    neon_mov_imm_LSL_operand:$Simm),
1236                  !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1237                  [(set (v2i32 VPR64:$Rd),
1238                     (v2i32 (opnode (v2i32 VPR64:$src),
1239                       (v2i32 (neonopnode timm:$Imm,
1240                         neon_mov_imm_LSL_operand:$Simm)))))],
1241                  NoItinerary> {
1242       bits<2> Simm;
1243       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1244     }
1245
1246     def _4S  : NeonI_1VModImm<0b1, op,
1247                  (outs VPR128:$Rd),
1248                  (ins VPR128:$src, neon_uimm8:$Imm,
1249                    neon_mov_imm_LSL_operand:$Simm),
1250                  !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1251                  [(set (v4i32 VPR128:$Rd),
1252                     (v4i32 (opnode (v4i32 VPR128:$src),
1253                       (v4i32 (neonopnode timm:$Imm,
1254                         neon_mov_imm_LSL_operand:$Simm)))))],
1255                  NoItinerary> {
1256       bits<2> Simm;
1257       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1258     }
1259
1260     // shift zeros, per halfword
1261     def _4H  : NeonI_1VModImm<0b0, op,
1262                  (outs VPR64:$Rd),
1263                  (ins VPR64:$src, neon_uimm8:$Imm,
1264                    neon_mov_imm_LSLH_operand:$Simm),
1265                  !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1266                  [(set (v4i16 VPR64:$Rd),
1267                     (v4i16 (opnode (v4i16 VPR64:$src),
1268                        (v4i16 (neonopnode timm:$Imm,
1269                           neon_mov_imm_LSL_operand:$Simm)))))],
1270                  NoItinerary> {
1271       bit  Simm;
1272       let cmode = {0b1, 0b0, Simm, 0b1};
1273     }
1274
1275     def _8H  : NeonI_1VModImm<0b1, op,
1276                  (outs VPR128:$Rd),
1277                  (ins VPR128:$src, neon_uimm8:$Imm,
1278                    neon_mov_imm_LSLH_operand:$Simm),
1279                  !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1280                  [(set (v8i16 VPR128:$Rd),
1281                     (v8i16 (opnode (v8i16 VPR128:$src),
1282                       (v8i16 (neonopnode timm:$Imm,
1283                         neon_mov_imm_LSL_operand:$Simm)))))],
1284                  NoItinerary> {
1285       bit Simm;
1286       let cmode = {0b1, 0b0, Simm, 0b1};
1287     }
1288   }
1289 }
1290
1291 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1292                                    SDPatternOperator opnode>
1293 {
1294     // shift ones, per word
1295     def _2S  : NeonI_1VModImm<0b0, op,
1296                              (outs VPR64:$Rd),
1297                              (ins neon_uimm8:$Imm,
1298                                neon_mov_imm_MSL_operand:$Simm),
1299                              !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1300                               [(set (v2i32 VPR64:$Rd),
1301                                  (v2i32 (opnode (timm:$Imm),
1302                                    (neon_mov_imm_MSL_operand:$Simm))))],
1303                              NoItinerary> {
1304        bit Simm;
1305        let cmode = {0b1, 0b1, 0b0, Simm};
1306      }
1307
1308    def _4S  : NeonI_1VModImm<0b1, op,
1309                               (outs VPR128:$Rd),
1310                               (ins neon_uimm8:$Imm,
1311                                 neon_mov_imm_MSL_operand:$Simm),
1312                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1313                               [(set (v4i32 VPR128:$Rd),
1314                                  (v4i32 (opnode (timm:$Imm),
1315                                    (neon_mov_imm_MSL_operand:$Simm))))],
1316                               NoItinerary> {
1317      bit Simm;
1318      let cmode = {0b1, 0b1, 0b0, Simm};
1319    }
1320 }
1321
1322 // Vector Move Immediate Shifted
1323 let isReMaterializable = 1 in {
1324 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1325 }
1326
1327 // Vector Move Inverted Immediate Shifted
1328 let isReMaterializable = 1 in {
1329 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1330 }
1331
1332 // Vector Bitwise Bit Clear (AND NOT) - immediate
1333 let isReMaterializable = 1 in {
1334 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1335                                                          and, Neon_mvni>;
1336 }
1337
1338 // Vector Bitwise OR - immedidate
1339
1340 let isReMaterializable = 1 in {
1341 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1342                                                            or, Neon_movi>;
1343 }
1344
1345 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1346 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1347 // BIC immediate instructions selection requires additional patterns to
1348 // transform Neon_movi operands into BIC immediate operands
1349
1350 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1351   uint64_t OpCmode = N->getZExtValue();
1352   unsigned ShiftImm;
1353   unsigned ShiftOnesIn;
1354   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1355   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1356   // Transform encoded shift amount 0 to 1 and 1 to 0.
1357   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1358 }]>;
1359
1360 def neon_mov_imm_LSLH_transform_operand
1361   : ImmLeaf<i32, [{
1362     unsigned ShiftImm;
1363     unsigned ShiftOnesIn;
1364     unsigned HasShift =
1365       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1366     return (HasShift && !ShiftOnesIn); }],
1367   neon_mov_imm_LSLH_transform_XFORM>;
1368
1369 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0xff, LSL 8)
1370 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0xff)
1371 def : Pat<(v4i16 (and VPR64:$src,
1372             (v4i16 (Neon_movi 255,
1373               neon_mov_imm_LSLH_transform_operand:$Simm)))),
1374           (BICvi_lsl_4H VPR64:$src, 255,
1375             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1376
1377 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0xff, LSL 8)
1378 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0xff)
1379 def : Pat<(v8i16 (and VPR128:$src,
1380             (v8i16 (Neon_movi 255,
1381               neon_mov_imm_LSLH_transform_operand:$Simm)))),
1382           (BICvi_lsl_8H VPR128:$src, 255,
1383             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1384
1385 def : Pat<(v8i8 (and VPR64:$src,
1386                   (bitconvert(v4i16 (Neon_movi 255,
1387                     neon_mov_imm_LSLH_transform_operand:$Simm))))),
1388           (BICvi_lsl_4H VPR64:$src, 255,
1389             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1390 def : Pat<(v2i32 (and VPR64:$src,
1391                  (bitconvert(v4i16 (Neon_movi 255,
1392                    neon_mov_imm_LSLH_transform_operand:$Simm))))),
1393           (BICvi_lsl_4H VPR64:$src, 255,
1394             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1395 def : Pat<(v1i64 (and VPR64:$src,
1396                 (bitconvert(v4i16 (Neon_movi 255,
1397                   neon_mov_imm_LSLH_transform_operand:$Simm))))),
1398         (BICvi_lsl_4H VPR64:$src, 255,
1399           neon_mov_imm_LSLH_transform_operand:$Simm)>;
1400
1401 def : Pat<(v16i8 (and VPR128:$src,
1402                  (bitconvert(v8i16 (Neon_movi 255,
1403                    neon_mov_imm_LSLH_transform_operand:$Simm))))),
1404         (BICvi_lsl_8H VPR128:$src, 255,
1405           neon_mov_imm_LSLH_transform_operand:$Simm)>;
1406 def : Pat<(v4i32 (and VPR128:$src,
1407                  (bitconvert(v8i16 (Neon_movi 255,
1408                    neon_mov_imm_LSLH_transform_operand:$Simm))))),
1409         (BICvi_lsl_8H VPR128:$src, 255,
1410           neon_mov_imm_LSLH_transform_operand:$Simm)>;
1411 def : Pat<(v2i64 (and VPR128:$src,
1412                  (bitconvert(v8i16 (Neon_movi 255,
1413                    neon_mov_imm_LSLH_transform_operand:$Simm))))),
1414         (BICvi_lsl_8H VPR128:$src, 255,
1415           neon_mov_imm_LSLH_transform_operand:$Simm)>;
1416
1417 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1418                                    SDPatternOperator neonopnode,
1419                                    Instruction INST4H,
1420                                    Instruction INST8H,
1421                                    Instruction INST2S,
1422                                    Instruction INST4S> {
1423   def : Pat<(v8i8 (opnode VPR64:$src,
1424                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1425                       neon_mov_imm_LSLH_operand:$Simm))))),
1426             (INST4H VPR64:$src, neon_uimm8:$Imm,
1427               neon_mov_imm_LSLH_operand:$Simm)>;
1428   def : Pat<(v2i32 (opnode VPR64:$src,
1429                    (bitconvert(v4i16 (neonopnode timm:$Imm,
1430                      neon_mov_imm_LSLH_operand:$Simm))))),
1431             (INST4H VPR64:$src, neon_uimm8:$Imm,
1432               neon_mov_imm_LSLH_operand:$Simm)>;
1433   def : Pat<(v1i64 (opnode VPR64:$src,
1434                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1435                     neon_mov_imm_LSLH_operand:$Simm))))),
1436           (INST4H VPR64:$src, neon_uimm8:$Imm,
1437             neon_mov_imm_LSLH_operand:$Simm)>;
1438
1439   def : Pat<(v16i8 (opnode VPR128:$src,
1440                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1441                      neon_mov_imm_LSLH_operand:$Simm))))),
1442           (INST8H VPR128:$src, neon_uimm8:$Imm,
1443             neon_mov_imm_LSLH_operand:$Simm)>;
1444   def : Pat<(v4i32 (opnode VPR128:$src,
1445                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1446                      neon_mov_imm_LSLH_operand:$Simm))))),
1447           (INST8H VPR128:$src, neon_uimm8:$Imm,
1448             neon_mov_imm_LSLH_operand:$Simm)>;
1449   def : Pat<(v2i64 (opnode VPR128:$src,
1450                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1451                      neon_mov_imm_LSLH_operand:$Simm))))),
1452           (INST8H VPR128:$src, neon_uimm8:$Imm,
1453             neon_mov_imm_LSLH_operand:$Simm)>;
1454
1455   def : Pat<(v8i8 (opnode VPR64:$src,
1456                     (bitconvert(v2i32 (neonopnode timm:$Imm,
1457                       neon_mov_imm_LSLH_operand:$Simm))))),
1458             (INST2S VPR64:$src, neon_uimm8:$Imm,
1459               neon_mov_imm_LSLH_operand:$Simm)>;
1460   def : Pat<(v4i16 (opnode VPR64:$src,
1461                    (bitconvert(v2i32 (neonopnode timm:$Imm,
1462                      neon_mov_imm_LSLH_operand:$Simm))))),
1463             (INST2S VPR64:$src, neon_uimm8:$Imm,
1464               neon_mov_imm_LSLH_operand:$Simm)>;
1465   def : Pat<(v1i64 (opnode VPR64:$src,
1466                   (bitconvert(v2i32 (neonopnode timm:$Imm,
1467                     neon_mov_imm_LSLH_operand:$Simm))))),
1468           (INST2S VPR64:$src, neon_uimm8:$Imm,
1469             neon_mov_imm_LSLH_operand:$Simm)>;
1470
1471   def : Pat<(v16i8 (opnode VPR128:$src,
1472                    (bitconvert(v4i32 (neonopnode timm:$Imm,
1473                      neon_mov_imm_LSLH_operand:$Simm))))),
1474           (INST4S VPR128:$src, neon_uimm8:$Imm,
1475             neon_mov_imm_LSLH_operand:$Simm)>;
1476   def : Pat<(v8i16 (opnode VPR128:$src,
1477                    (bitconvert(v4i32 (neonopnode timm:$Imm,
1478                      neon_mov_imm_LSLH_operand:$Simm))))),
1479           (INST4S VPR128:$src, neon_uimm8:$Imm,
1480             neon_mov_imm_LSLH_operand:$Simm)>;
1481   def : Pat<(v2i64 (opnode VPR128:$src,
1482                    (bitconvert(v4i32 (neonopnode timm:$Imm,
1483                      neon_mov_imm_LSLH_operand:$Simm))))),
1484           (INST4S VPR128:$src, neon_uimm8:$Imm,
1485             neon_mov_imm_LSLH_operand:$Simm)>;
1486 }
1487
1488 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1489 defm : Neon_bitwiseVi_patterns<and, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H,
1490                                BICvi_lsl_2S, BICvi_lsl_4S>;
1491
1492 // Additional patterns for Vector Bitwise OR - immedidate
1493 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H,
1494                                ORRvi_lsl_2S, ORRvi_lsl_4S>;
1495
1496
1497 // Vector Move Immediate Masked
1498 let isReMaterializable = 1 in {
1499 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1500 }
1501
1502 // Vector Move Inverted Immediate Masked
1503 let isReMaterializable = 1 in {
1504 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1505 }
1506
1507 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1508                                 Instruction inst, RegisterOperand VPRC>
1509   : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1510                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1511
1512 // Aliases for Vector Move Immediate Shifted
1513 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1514 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1515 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1516 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1517
1518 // Aliases for Vector Move Inverted Immediate Shifted
1519 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1520 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1521 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1522 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1523
1524 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1525 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1526 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1527 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1528 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1529
1530 // Aliases for Vector Bitwise OR - immedidate
1531 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1532 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1533 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1534 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1535
1536 //  Vector Move Immediate - per byte
1537 let isReMaterializable = 1 in {
1538 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1539                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1540                                "movi\t$Rd.8b, $Imm",
1541                                [(set (v8i8 VPR64:$Rd),
1542                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1543                                 NoItinerary> {
1544   let cmode = 0b1110;
1545 }
1546
1547 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1548                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1549                                 "movi\t$Rd.16b, $Imm",
1550                                 [(set (v16i8 VPR128:$Rd),
1551                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1552                                  NoItinerary> {
1553   let cmode = 0b1110;
1554 }
1555 }
1556
1557 // Vector Move Immediate - bytemask, per double word
1558 let isReMaterializable = 1 in {
1559 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1560                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1561                                "movi\t $Rd.2d, $Imm",
1562                                [(set (v2i64 VPR128:$Rd),
1563                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1564                                NoItinerary> {
1565   let cmode = 0b1110;
1566 }
1567 }
1568
1569 // Vector Move Immediate - bytemask, one doubleword
1570
1571 let isReMaterializable = 1 in {
1572 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1573                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1574                            "movi\t $Rd, $Imm",
1575                            [(set (v1i64 FPR64:$Rd),
1576                              (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1577                            NoItinerary> {
1578   let cmode = 0b1110;
1579 }
1580 }
1581
1582 // Vector Floating Point Move Immediate
1583
1584 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1585                       Operand immOpType, bit q, bit op>
1586   : NeonI_1VModImm<q, op,
1587                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1588                    "fmov\t$Rd" # asmlane # ", $Imm",
1589                    [(set (OpTy VPRC:$Rd),
1590                       (OpTy (Neon_fmovi (timm:$Imm))))],
1591                    NoItinerary> {
1592      let cmode = 0b1111;
1593    }
1594
1595 let isReMaterializable = 1 in {
1596 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1597 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1598 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1599 }
1600
1601 // Vector Shift (Immediate)
1602 // Immediate in [0, 63]
1603 def imm0_63 : Operand<i32> {
1604   let ParserMatchClass = uimm6_asmoperand;
1605 }
1606
1607 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1608 // as follows:
1609 //
1610 //    Offset    Encoding
1611 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1612 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1613 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1614 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1615 //
1616 // The shift right immediate amount, in the range 1 to element bits, is computed
1617 // as Offset - UInt(immh:immb).  The shift left immediate amount, in the range 0
1618 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1619
1620 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1621   let Name = "ShrImm" # OFFSET;
1622   let RenderMethod = "addImmOperands";
1623   let DiagnosticType = "ShrImm" # OFFSET;
1624 }
1625
1626 class shr_imm<string OFFSET> : Operand<i32> {
1627   let EncoderMethod = "getShiftRightImm" # OFFSET;
1628   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1629   let ParserMatchClass =
1630     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1631 }
1632
1633 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1634 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1635 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1636 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1637
1638 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1639 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1640 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1641 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1642
1643 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1644   let Name = "ShlImm" # OFFSET;
1645   let RenderMethod = "addImmOperands";
1646   let DiagnosticType = "ShlImm" # OFFSET;
1647 }
1648
1649 class shl_imm<string OFFSET> : Operand<i32> {
1650   let EncoderMethod = "getShiftLeftImm" # OFFSET;
1651   let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1652   let ParserMatchClass =
1653     !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1654 }
1655
1656 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1657 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1658 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1659 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1660
1661 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1662 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1663 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1664 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1665
1666 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1667                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1668   : NeonI_2VShiftImm<q, u, opcode,
1669                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1670                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1671                      [(set (Ty VPRC:$Rd),
1672                         (Ty (OpNode (Ty VPRC:$Rn),
1673                           (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1674                      NoItinerary>;
1675
1676 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1677   // 64-bit vector types.
1678   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1679     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1680   }
1681
1682   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1683     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1684   }
1685
1686   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1687     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1688   }
1689
1690   // 128-bit vector types.
1691   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1692     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1693   }
1694
1695   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1696     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1697   }
1698
1699   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1700     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1701   }
1702
1703   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1704     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1705   }
1706 }
1707
1708 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1709   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1710                      OpNode> {
1711     let Inst{22-19} = 0b0001;
1712   }
1713
1714   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1715                      OpNode> {
1716     let Inst{22-20} = 0b001;
1717   }
1718
1719   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1720                      OpNode> {
1721      let Inst{22-21} = 0b01;
1722   }
1723
1724   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1725                       OpNode> {
1726                       let Inst{22-19} = 0b0001;
1727                     }
1728
1729   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1730                      OpNode> {
1731                      let Inst{22-20} = 0b001;
1732                     }
1733
1734   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1735                      OpNode> {
1736                       let Inst{22-21} = 0b01;
1737                     }
1738
1739   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1740                      OpNode> {
1741                       let Inst{22} = 0b1;
1742                     }
1743 }
1744
1745 // Shift left
1746 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1747
1748 // Shift right
1749 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1750 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1751
1752 def Neon_High16B : PatFrag<(ops node:$in),
1753                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1754 def Neon_High8H  : PatFrag<(ops node:$in),
1755                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1756 def Neon_High4S  : PatFrag<(ops node:$in),
1757                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1758 def Neon_High2D  : PatFrag<(ops node:$in),
1759                            (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1760 def Neon_High4float : PatFrag<(ops node:$in),
1761                                (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1762 def Neon_High2double : PatFrag<(ops node:$in),
1763                                (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1764
1765 def Neon_Low16B : PatFrag<(ops node:$in),
1766                           (v8i8 (extract_subvector (v16i8 node:$in),
1767                                                    (iPTR 0)))>;
1768 def Neon_Low8H : PatFrag<(ops node:$in),
1769                          (v4i16 (extract_subvector (v8i16 node:$in),
1770                                                    (iPTR 0)))>;
1771 def Neon_Low4S : PatFrag<(ops node:$in),
1772                          (v2i32 (extract_subvector (v4i32 node:$in),
1773                                                    (iPTR 0)))>;
1774 def Neon_Low2D : PatFrag<(ops node:$in),
1775                          (v1i64 (extract_subvector (v2i64 node:$in),
1776                                                    (iPTR 0)))>;
1777 def Neon_Low4float : PatFrag<(ops node:$in),
1778                              (v2f32 (extract_subvector (v4f32 node:$in),
1779                                                        (iPTR 0)))>;
1780 def Neon_Low2double : PatFrag<(ops node:$in),
1781                               (v1f64 (extract_subvector (v2f64 node:$in),
1782                                                         (iPTR 0)))>;
1783
1784 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1785                    string SrcT, ValueType DestTy, ValueType SrcTy,
1786                    Operand ImmTy, SDPatternOperator ExtOp>
1787   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1788                      (ins VPR64:$Rn, ImmTy:$Imm),
1789                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1790                      [(set (DestTy VPR128:$Rd),
1791                         (DestTy (shl
1792                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1793                             (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1794                      NoItinerary>;
1795
1796 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1797                        string SrcT, ValueType DestTy, ValueType SrcTy,
1798                        int StartIndex, Operand ImmTy,
1799                        SDPatternOperator ExtOp, PatFrag getTop>
1800   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1801                      (ins VPR128:$Rn, ImmTy:$Imm),
1802                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1803                      [(set (DestTy VPR128:$Rd),
1804                         (DestTy (shl
1805                           (DestTy (ExtOp
1806                             (SrcTy (getTop VPR128:$Rn)))),
1807                               (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1808                      NoItinerary>;
1809
1810 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1811                          SDNode ExtOp> {
1812   // 64-bit vector types.
1813   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1814                          shl_imm8, ExtOp> {
1815     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1816   }
1817
1818   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1819                          shl_imm16, ExtOp> {
1820     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1821   }
1822
1823   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1824                          shl_imm32, ExtOp> {
1825     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1826   }
1827
1828   // 128-bit vector types
1829   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1830                               8, shl_imm8, ExtOp, Neon_High16B> {
1831     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1832   }
1833
1834   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1835                              4, shl_imm16, ExtOp, Neon_High8H> {
1836     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1837   }
1838
1839   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1840                              2, shl_imm32, ExtOp, Neon_High4S> {
1841     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1842   }
1843
1844   // Use other patterns to match when the immediate is 0.
1845   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1846             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1847
1848   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1849             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1850
1851   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1852             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1853
1854   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1855             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1856
1857   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1858             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1859
1860   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1861             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1862 }
1863
1864 // Shift left long
1865 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1866 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1867
1868 class NeonI_ext_len_alias<string asmop, string lane, string laneOp,
1869                        Instruction inst, RegisterOperand VPRC,
1870                        RegisterOperand VPRCOp>
1871   : NeonInstAlias<asmop # "\t$Rd" # lane #", $Rn" # laneOp,
1872                   (inst VPRC:$Rd, VPRCOp:$Rn, 0), 0b0>;
1873
1874 // Signed integer lengthen (vector) is alias for SSHLL Vd, Vn, #0
1875 // Signed integer lengthen (vector, second part) is alias for SSHLL2 Vd, Vn, #0
1876 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1877 // custom printing of aliases.
1878 def SXTLvv_8B  : NeonI_ext_len_alias<"sxtl", ".8h", ".8b",  SSHLLvvi_8B, VPR128, VPR64>;
1879 def SXTLvv_4H  : NeonI_ext_len_alias<"sxtl", ".4s", ".4h",  SSHLLvvi_4H, VPR128, VPR64>;
1880 def SXTLvv_2S  : NeonI_ext_len_alias<"sxtl", ".2d", ".2s",  SSHLLvvi_2S, VPR128, VPR64>;
1881 def SXTL2vv_16B : NeonI_ext_len_alias<"sxtl2", ".8h", ".16b",  SSHLLvvi_16B, VPR128, VPR128>;
1882 def SXTL2vv_8H  : NeonI_ext_len_alias<"sxtl2", ".4s", ".8h",  SSHLLvvi_8H, VPR128, VPR128>;
1883 def SXTL2vv_4S  : NeonI_ext_len_alias<"sxtl2", ".2d", ".4s",  SSHLLvvi_4S, VPR128, VPR128>;
1884
1885 // Unsigned integer lengthen (vector) is alias for USHLL Vd, Vn, #0
1886 // Unsigned integer lengthen (vector, second part) is alias for USHLL2 Vd, Vn, #0
1887 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1888 // custom printing of aliases.
1889 def UXTLvv_8B  : NeonI_ext_len_alias<"uxtl", ".8h", ".8b",  USHLLvvi_8B, VPR128, VPR64>;
1890 def UXTLvv_4H  : NeonI_ext_len_alias<"uxtl", ".4s", ".4h",  USHLLvvi_4H, VPR128, VPR64>;
1891 def UXTLvv_2S  : NeonI_ext_len_alias<"uxtl", ".2d", ".2s",  USHLLvvi_2S, VPR128, VPR64>;
1892 def UXTL2vv_16B : NeonI_ext_len_alias<"uxtl2", ".8h", ".16b",  USHLLvvi_16B, VPR128, VPR128>;
1893 def UXTL2vv_8H  : NeonI_ext_len_alias<"uxtl2", ".4s", ".8h",  USHLLvvi_8H, VPR128, VPR128>;
1894 def UXTL2vv_4S  : NeonI_ext_len_alias<"uxtl2", ".2d", ".4s",  USHLLvvi_4S, VPR128, VPR128>;
1895
1896 def : Pat<(v8i16 (anyext (v8i8 VPR64:$Rn))), (USHLLvvi_8B VPR64:$Rn, 0)>;
1897 def : Pat<(v4i32 (anyext (v4i16 VPR64:$Rn))), (USHLLvvi_4H VPR64:$Rn, 0)>;
1898 def : Pat<(v2i64 (anyext (v2i32 VPR64:$Rn))), (USHLLvvi_2S VPR64:$Rn, 0)>;
1899
1900 // Rounding/Saturating shift
1901 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1902                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1903                   SDPatternOperator OpNode>
1904   : NeonI_2VShiftImm<q, u, opcode,
1905                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1906                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1907                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1908                         (i32 ImmTy:$Imm))))],
1909                      NoItinerary>;
1910
1911 // shift right (vector by immediate)
1912 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1913                            SDPatternOperator OpNode> {
1914   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1915                          OpNode> {
1916     let Inst{22-19} = 0b0001;
1917   }
1918
1919   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1920                          OpNode> {
1921     let Inst{22-20} = 0b001;
1922   }
1923
1924   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1925                          OpNode> {
1926     let Inst{22-21} = 0b01;
1927   }
1928
1929   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1930                          OpNode> {
1931     let Inst{22-19} = 0b0001;
1932   }
1933
1934   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1935                         OpNode> {
1936     let Inst{22-20} = 0b001;
1937   }
1938
1939   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1940                         OpNode> {
1941     let Inst{22-21} = 0b01;
1942   }
1943
1944   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1945                         OpNode> {
1946     let Inst{22} = 0b1;
1947   }
1948 }
1949
1950 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1951                           SDPatternOperator OpNode> {
1952   // 64-bit vector types.
1953   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1954                         OpNode> {
1955     let Inst{22-19} = 0b0001;
1956   }
1957
1958   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1959                         OpNode> {
1960     let Inst{22-20} = 0b001;
1961   }
1962
1963   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1964                         OpNode> {
1965     let Inst{22-21} = 0b01;
1966   }
1967
1968   // 128-bit vector types.
1969   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1970                          OpNode> {
1971     let Inst{22-19} = 0b0001;
1972   }
1973
1974   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1975                         OpNode> {
1976     let Inst{22-20} = 0b001;
1977   }
1978
1979   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1980                         OpNode> {
1981     let Inst{22-21} = 0b01;
1982   }
1983
1984   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1985                         OpNode> {
1986     let Inst{22} = 0b1;
1987   }
1988 }
1989
1990 // Rounding shift right
1991 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1992                                 int_aarch64_neon_vsrshr>;
1993 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1994                                 int_aarch64_neon_vurshr>;
1995
1996 // Saturating shift left unsigned
1997 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1998
1999 // Saturating shift left
2000 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
2001 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
2002
2003 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
2004                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2005                   SDNode OpNode>
2006   : NeonI_2VShiftImm<q, u, opcode,
2007            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2008            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2009            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
2010               (Ty (OpNode (Ty VPRC:$Rn),
2011                 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
2012            NoItinerary> {
2013   let Constraints = "$src = $Rd";
2014 }
2015
2016 // Shift Right accumulate
2017 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
2018   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2019                         OpNode> {
2020     let Inst{22-19} = 0b0001;
2021   }
2022
2023   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2024                         OpNode> {
2025     let Inst{22-20} = 0b001;
2026   }
2027
2028   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2029                         OpNode> {
2030     let Inst{22-21} = 0b01;
2031   }
2032
2033   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2034                          OpNode> {
2035     let Inst{22-19} = 0b0001;
2036   }
2037
2038   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2039                         OpNode> {
2040     let Inst{22-20} = 0b001;
2041   }
2042
2043   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2044                         OpNode> {
2045     let Inst{22-21} = 0b01;
2046   }
2047
2048   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2049                         OpNode> {
2050     let Inst{22} = 0b1;
2051   }
2052 }
2053
2054 // Shift right and accumulate
2055 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
2056 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
2057
2058 // Rounding shift accumulate
2059 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
2060                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2061                     SDPatternOperator OpNode>
2062   : NeonI_2VShiftImm<q, u, opcode,
2063                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2064                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2065                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
2066                         (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
2067                      NoItinerary> {
2068   let Constraints = "$src = $Rd";
2069 }
2070
2071 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
2072                              SDPatternOperator OpNode> {
2073   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2074                           OpNode> {
2075     let Inst{22-19} = 0b0001;
2076   }
2077
2078   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2079                           OpNode> {
2080     let Inst{22-20} = 0b001;
2081   }
2082
2083   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2084                           OpNode> {
2085     let Inst{22-21} = 0b01;
2086   }
2087
2088   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2089                            OpNode> {
2090     let Inst{22-19} = 0b0001;
2091   }
2092
2093   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2094                           OpNode> {
2095     let Inst{22-20} = 0b001;
2096   }
2097
2098   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2099                           OpNode> {
2100     let Inst{22-21} = 0b01;
2101   }
2102
2103   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2104                           OpNode> {
2105     let Inst{22} = 0b1;
2106   }
2107 }
2108
2109 // Rounding shift right and accumulate
2110 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
2111 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
2112
2113 // Shift insert by immediate
2114 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
2115                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2116                   SDPatternOperator OpNode>
2117     : NeonI_2VShiftImm<q, u, opcode,
2118            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2119            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2120            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
2121              (i32 ImmTy:$Imm))))],
2122            NoItinerary> {
2123   let Constraints = "$src = $Rd";
2124 }
2125
2126 // shift left insert (vector by immediate)
2127 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
2128   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
2129                         int_aarch64_neon_vsli> {
2130     let Inst{22-19} = 0b0001;
2131   }
2132
2133   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
2134                         int_aarch64_neon_vsli> {
2135     let Inst{22-20} = 0b001;
2136   }
2137
2138   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
2139                         int_aarch64_neon_vsli> {
2140     let Inst{22-21} = 0b01;
2141   }
2142
2143     // 128-bit vector types
2144   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
2145                          int_aarch64_neon_vsli> {
2146     let Inst{22-19} = 0b0001;
2147   }
2148
2149   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
2150                         int_aarch64_neon_vsli> {
2151     let Inst{22-20} = 0b001;
2152   }
2153
2154   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
2155                         int_aarch64_neon_vsli> {
2156     let Inst{22-21} = 0b01;
2157   }
2158
2159   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
2160                         int_aarch64_neon_vsli> {
2161     let Inst{22} = 0b1;
2162   }
2163 }
2164
2165 // shift right insert (vector by immediate)
2166 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2167     // 64-bit vector types.
2168   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2169                         int_aarch64_neon_vsri> {
2170     let Inst{22-19} = 0b0001;
2171   }
2172
2173   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2174                         int_aarch64_neon_vsri> {
2175     let Inst{22-20} = 0b001;
2176   }
2177
2178   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2179                         int_aarch64_neon_vsri> {
2180     let Inst{22-21} = 0b01;
2181   }
2182
2183     // 128-bit vector types
2184   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2185                          int_aarch64_neon_vsri> {
2186     let Inst{22-19} = 0b0001;
2187   }
2188
2189   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2190                         int_aarch64_neon_vsri> {
2191     let Inst{22-20} = 0b001;
2192   }
2193
2194   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2195                         int_aarch64_neon_vsri> {
2196     let Inst{22-21} = 0b01;
2197   }
2198
2199   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2200                         int_aarch64_neon_vsri> {
2201     let Inst{22} = 0b1;
2202   }
2203 }
2204
2205 // Shift left and insert
2206 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2207
2208 // Shift right and insert
2209 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2210
2211 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2212                     string SrcT, Operand ImmTy>
2213   : NeonI_2VShiftImm<q, u, opcode,
2214                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2215                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2216                      [], NoItinerary>;
2217
2218 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2219                        string SrcT, Operand ImmTy>
2220   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2221                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2222                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2223                      [], NoItinerary> {
2224   let Constraints = "$src = $Rd";
2225 }
2226
2227 // left long shift by immediate
2228 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2229   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2230     let Inst{22-19} = 0b0001;
2231   }
2232
2233   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2234     let Inst{22-20} = 0b001;
2235   }
2236
2237   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2238     let Inst{22-21} = 0b01;
2239   }
2240
2241   // Shift Narrow High
2242   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2243                               shr_imm8> {
2244     let Inst{22-19} = 0b0001;
2245   }
2246
2247   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2248                              shr_imm16> {
2249     let Inst{22-20} = 0b001;
2250   }
2251
2252   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2253                              shr_imm32> {
2254     let Inst{22-21} = 0b01;
2255   }
2256 }
2257
2258 // Shift right narrow
2259 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2260
2261 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2262 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2263 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2264 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2265 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2266 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2267 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2268 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2269
2270 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2271                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2272                                                      (v1i64 node:$Rn)))>;
2273 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2274                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2275                                                      (v4i16 node:$Rn)))>;
2276 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2277                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2278                                                      (v2i32 node:$Rn)))>;
2279 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2280                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2281                                                      (v2f32 node:$Rn)))>;
2282 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2283                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2284                                                      (v1f64 node:$Rn)))>;
2285
2286 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2287                              (v8i16 (srl (v8i16 node:$lhs),
2288                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2289 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2290                              (v4i32 (srl (v4i32 node:$lhs),
2291                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2292 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2293                              (v2i64 (srl (v2i64 node:$lhs),
2294                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2295 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2296                              (v8i16 (sra (v8i16 node:$lhs),
2297                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2298 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2299                              (v4i32 (sra (v4i32 node:$lhs),
2300                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2301 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2302                              (v2i64 (sra (v2i64 node:$lhs),
2303                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2304
2305 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2306 multiclass Neon_shiftNarrow_patterns<string shr> {
2307   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2308               (i32 shr_imm8:$Imm)))),
2309             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2310   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2311               (i32 shr_imm16:$Imm)))),
2312             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2313   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2314               (i32 shr_imm32:$Imm)))),
2315             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2316
2317   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2318               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2319                 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2320             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2321                          VPR128:$Rn, imm:$Imm)>;
2322   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2323               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2324                 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2325             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2326                         VPR128:$Rn, imm:$Imm)>;
2327   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2328               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2329                 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2330             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2331                         VPR128:$Rn, imm:$Imm)>;
2332 }
2333
2334 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2335   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2336             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2337   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2338             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2339   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2340             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2341
2342   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2343                 (v1i64 (bitconvert (v8i8
2344                     (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2345             (!cast<Instruction>(prefix # "_16B")
2346                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2347                 VPR128:$Rn, imm:$Imm)>;
2348   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2349                 (v1i64 (bitconvert (v4i16
2350                     (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2351             (!cast<Instruction>(prefix # "_8H")
2352                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2353                 VPR128:$Rn, imm:$Imm)>;
2354   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2355                 (v1i64 (bitconvert (v2i32
2356                     (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2357             (!cast<Instruction>(prefix # "_4S")
2358                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2359                   VPR128:$Rn, imm:$Imm)>;
2360 }
2361
2362 defm : Neon_shiftNarrow_patterns<"lshr">;
2363 defm : Neon_shiftNarrow_patterns<"ashr">;
2364
2365 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2366 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2367 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2368 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2369 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2370 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2371 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2372
2373 // Convert fix-point and float-pointing
2374 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2375                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2376                 Operand ImmTy, SDPatternOperator IntOp>
2377   : NeonI_2VShiftImm<q, u, opcode,
2378                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2379                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2380                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2381                        (i32 ImmTy:$Imm))))],
2382                      NoItinerary>;
2383
2384 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2385                               SDPatternOperator IntOp> {
2386   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2387                       shr_imm32, IntOp> {
2388     let Inst{22-21} = 0b01;
2389   }
2390
2391   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2392                       shr_imm32, IntOp> {
2393     let Inst{22-21} = 0b01;
2394   }
2395
2396   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2397                       shr_imm64, IntOp> {
2398     let Inst{22} = 0b1;
2399   }
2400 }
2401
2402 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2403                               SDPatternOperator IntOp> {
2404   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2405                       shr_imm32, IntOp> {
2406     let Inst{22-21} = 0b01;
2407   }
2408
2409   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2410                       shr_imm32, IntOp> {
2411     let Inst{22-21} = 0b01;
2412   }
2413
2414   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2415                       shr_imm64, IntOp> {
2416     let Inst{22} = 0b1;
2417   }
2418 }
2419
2420 // Convert fixed-point to floating-point
2421 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2422                                    int_arm_neon_vcvtfxs2fp>;
2423 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2424                                    int_arm_neon_vcvtfxu2fp>;
2425
2426 // Convert floating-point to fixed-point
2427 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2428                                    int_arm_neon_vcvtfp2fxs>;
2429 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2430                                    int_arm_neon_vcvtfp2fxu>;
2431
2432 multiclass Neon_sshll2_0<SDNode ext>
2433 {
2434   def _v8i8  : PatFrag<(ops node:$Rn),
2435                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2436   def _v4i16 : PatFrag<(ops node:$Rn),
2437                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2438   def _v2i32 : PatFrag<(ops node:$Rn),
2439                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2440 }
2441
2442 defm NI_sext_high : Neon_sshll2_0<sext>;
2443 defm NI_zext_high : Neon_sshll2_0<zext>;
2444
2445
2446 //===----------------------------------------------------------------------===//
2447 // Multiclasses for NeonI_Across
2448 //===----------------------------------------------------------------------===//
2449
2450 // Variant 1
2451
2452 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2453                             string asmop, SDPatternOperator opnode>
2454 {
2455     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2456                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2457                 asmop # "\t$Rd, $Rn.8b",
2458                 [(set (v1i16 FPR16:$Rd),
2459                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2460                 NoItinerary>;
2461
2462     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2463                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2464                 asmop # "\t$Rd, $Rn.16b",
2465                 [(set (v1i16 FPR16:$Rd),
2466                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2467                 NoItinerary>;
2468
2469     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2470                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2471                 asmop # "\t$Rd, $Rn.4h",
2472                 [(set (v1i32 FPR32:$Rd),
2473                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2474                 NoItinerary>;
2475
2476     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2477                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2478                 asmop # "\t$Rd, $Rn.8h",
2479                 [(set (v1i32 FPR32:$Rd),
2480                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2481                 NoItinerary>;
2482
2483     // _1d2s doesn't exist!
2484
2485     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2486                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2487                 asmop # "\t$Rd, $Rn.4s",
2488                 [(set (v1i64 FPR64:$Rd),
2489                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2490                 NoItinerary>;
2491 }
2492
2493 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2494 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2495
2496 // Variant 2
2497
2498 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2499                             string asmop, SDPatternOperator opnode>
2500 {
2501     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2502                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2503                 asmop # "\t$Rd, $Rn.8b",
2504                 [(set (v1i8 FPR8:$Rd),
2505                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2506                 NoItinerary>;
2507
2508     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2509                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2510                 asmop # "\t$Rd, $Rn.16b",
2511                 [(set (v1i8 FPR8:$Rd),
2512                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2513                 NoItinerary>;
2514
2515     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2516                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2517                 asmop # "\t$Rd, $Rn.4h",
2518                 [(set (v1i16 FPR16:$Rd),
2519                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2520                 NoItinerary>;
2521
2522     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2523                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2524                 asmop # "\t$Rd, $Rn.8h",
2525                 [(set (v1i16 FPR16:$Rd),
2526                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2527                 NoItinerary>;
2528
2529     // _1s2s doesn't exist!
2530
2531     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2532                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2533                 asmop # "\t$Rd, $Rn.4s",
2534                 [(set (v1i32 FPR32:$Rd),
2535                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2536                 NoItinerary>;
2537 }
2538
2539 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2540 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2541
2542 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2543 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2544
2545 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2546
2547 // Variant 3
2548
2549 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2550                             string asmop, SDPatternOperator opnode> {
2551     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2552                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2553                 asmop # "\t$Rd, $Rn.4s",
2554                 [(set (f32 FPR32:$Rd),
2555                     (f32 (opnode (v4f32 VPR128:$Rn))))],
2556                 NoItinerary>;
2557 }
2558
2559 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2560                                 int_aarch64_neon_vmaxnmv>;
2561 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2562                                 int_aarch64_neon_vminnmv>;
2563
2564 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2565                               int_aarch64_neon_vmaxv>;
2566 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2567                               int_aarch64_neon_vminv>;
2568
2569 // The followings are for instruction class (Perm)
2570
2571 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2572                     string asmop, RegisterOperand OpVPR, string OpS,
2573                     SDPatternOperator opnode, ValueType Ty>
2574   : NeonI_Perm<q, size, opcode,
2575                (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2576                asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2577                [(set (Ty OpVPR:$Rd),
2578                   (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2579                NoItinerary>;
2580
2581 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2582                           SDPatternOperator opnode> {
2583   def _8b  : NeonI_Permute<0b0, 0b00, opcode, asmop,
2584                            VPR64, "8b", opnode, v8i8>;
2585   def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2586                            VPR128, "16b",opnode, v16i8>;
2587   def _4h  : NeonI_Permute<0b0, 0b01, opcode, asmop,
2588                            VPR64, "4h", opnode, v4i16>;
2589   def _8h  : NeonI_Permute<0b1, 0b01, opcode, asmop,
2590                            VPR128, "8h", opnode, v8i16>;
2591   def _2s  : NeonI_Permute<0b0, 0b10, opcode, asmop,
2592                            VPR64, "2s", opnode, v2i32>;
2593   def _4s  : NeonI_Permute<0b1, 0b10, opcode, asmop,
2594                            VPR128, "4s", opnode, v4i32>;
2595   def _2d  : NeonI_Permute<0b1, 0b11, opcode, asmop,
2596                            VPR128, "2d", opnode, v2i64>;
2597 }
2598
2599 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2600 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2601 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2602 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2603 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2604 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2605
2606 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2607   def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2608             (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2609
2610   def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2611             (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2612
2613   def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2614             (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2615 }
2616
2617 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2618 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2619 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2620 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2621 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2622 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2623
2624 // The followings are for instruction class (3V Diff)
2625
2626 // normal long/long2 pattern
2627 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2628                  string asmop, string ResS, string OpS,
2629                  SDPatternOperator opnode, SDPatternOperator ext,
2630                  RegisterOperand OpVPR,
2631                  ValueType ResTy, ValueType OpTy>
2632   : NeonI_3VDiff<q, u, size, opcode,
2633                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2634                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2635                  [(set (ResTy VPR128:$Rd),
2636                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2637                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2638                  NoItinerary>;
2639
2640 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2641                         string asmop, SDPatternOperator opnode,
2642                         bit Commutable = 0> {
2643   let isCommutable = Commutable in {
2644     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2645                            opnode, sext, VPR64, v8i16, v8i8>;
2646     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2647                            opnode, sext, VPR64, v4i32, v4i16>;
2648     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2649                            opnode, sext, VPR64, v2i64, v2i32>;
2650   }
2651 }
2652
2653 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2654                          SDPatternOperator opnode, bit Commutable = 0> {
2655   let isCommutable = Commutable in {
2656     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2657                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2658     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2659                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2660     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2661                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2662   }
2663 }
2664
2665 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2666                         SDPatternOperator opnode, bit Commutable = 0> {
2667   let isCommutable = Commutable in {
2668     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2669                            opnode, zext, VPR64, v8i16, v8i8>;
2670     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2671                            opnode, zext, VPR64, v4i32, v4i16>;
2672     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2673                            opnode, zext, VPR64, v2i64, v2i32>;
2674   }
2675 }
2676
2677 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2678                          SDPatternOperator opnode, bit Commutable = 0> {
2679   let isCommutable = Commutable in {
2680     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2681                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2682     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2683                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2684     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2685                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2686   }
2687 }
2688
2689 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2690 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2691
2692 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2693 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2694
2695 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2696 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2697
2698 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2699 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2700
2701 // normal wide/wide2 pattern
2702 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2703                  string asmop, string ResS, string OpS,
2704                  SDPatternOperator opnode, SDPatternOperator ext,
2705                  RegisterOperand OpVPR,
2706                  ValueType ResTy, ValueType OpTy>
2707   : NeonI_3VDiff<q, u, size, opcode,
2708                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2709                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2710                  [(set (ResTy VPR128:$Rd),
2711                     (ResTy (opnode (ResTy VPR128:$Rn),
2712                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2713                  NoItinerary>;
2714
2715 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2716                         SDPatternOperator opnode> {
2717   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2718                          opnode, sext, VPR64, v8i16, v8i8>;
2719   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2720                          opnode, sext, VPR64, v4i32, v4i16>;
2721   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2722                          opnode, sext, VPR64, v2i64, v2i32>;
2723 }
2724
2725 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2726 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2727
2728 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2729                          SDPatternOperator opnode> {
2730   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2731                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2732   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2733                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2734   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2735                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2736 }
2737
2738 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2739 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2740
2741 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2742                         SDPatternOperator opnode> {
2743   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2744                          opnode, zext, VPR64, v8i16, v8i8>;
2745   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2746                          opnode, zext, VPR64, v4i32, v4i16>;
2747   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2748                          opnode, zext, VPR64, v2i64, v2i32>;
2749 }
2750
2751 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2752 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2753
2754 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2755                          SDPatternOperator opnode> {
2756   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2757                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2758   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2759                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2760   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2761                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2762 }
2763
2764 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2765 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2766
2767 // Get the high half part of the vector element.
2768 multiclass NeonI_get_high {
2769   def _8h : PatFrag<(ops node:$Rn),
2770                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2771                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2772   def _4s : PatFrag<(ops node:$Rn),
2773                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2774                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2775   def _2d : PatFrag<(ops node:$Rn),
2776                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2777                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2778 }
2779
2780 defm NI_get_hi : NeonI_get_high;
2781
2782 // pattern for addhn/subhn with 2 operands
2783 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2784                            string asmop, string ResS, string OpS,
2785                            SDPatternOperator opnode, SDPatternOperator get_hi,
2786                            ValueType ResTy, ValueType OpTy>
2787   : NeonI_3VDiff<q, u, size, opcode,
2788                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2789                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2790                  [(set (ResTy VPR64:$Rd),
2791                     (ResTy (get_hi
2792                       (OpTy (opnode (OpTy VPR128:$Rn),
2793                                     (OpTy VPR128:$Rm))))))],
2794                  NoItinerary>;
2795
2796 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2797                                 SDPatternOperator opnode, bit Commutable = 0> {
2798   let isCommutable = Commutable in {
2799     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2800                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2801     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2802                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2803     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2804                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2805   }
2806 }
2807
2808 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2809 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2810
2811 // pattern for operation with 2 operands
2812 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2813                     string asmop, string ResS, string OpS,
2814                     SDPatternOperator opnode,
2815                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2816                     ValueType ResTy, ValueType OpTy>
2817   : NeonI_3VDiff<q, u, size, opcode,
2818                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2819                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2820                  [(set (ResTy ResVPR:$Rd),
2821                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2822                  NoItinerary>;
2823
2824 // normal narrow pattern
2825 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2826                           SDPatternOperator opnode, bit Commutable = 0> {
2827   let isCommutable = Commutable in {
2828     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2829                               opnode, VPR64, VPR128, v8i8, v8i16>;
2830     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2831                               opnode, VPR64, VPR128, v4i16, v4i32>;
2832     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2833                               opnode, VPR64, VPR128, v2i32, v2i64>;
2834   }
2835 }
2836
2837 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2838 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2839
2840 // pattern for acle intrinsic with 3 operands
2841 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2842                      string asmop, string ResS, string OpS>
2843   : NeonI_3VDiff<q, u, size, opcode,
2844                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2845                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2846                  [], NoItinerary> {
2847   let Constraints = "$src = $Rd";
2848   let neverHasSideEffects = 1;
2849 }
2850
2851 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2852   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2853   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2854   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2855 }
2856
2857 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2858 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2859
2860 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2861 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2862
2863 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2864 // part.
2865 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2866                         SDPatternOperator coreop>
2867   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2868                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2869                                                         (SrcTy VPR128:$Rm)))))),
2870         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2871               VPR128:$Rn, VPR128:$Rm)>;
2872
2873 // addhn2 patterns
2874 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2875           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2876 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2877           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2878 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2879           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2880
2881 // subhn2 patterns
2882 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2883           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2884 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2885           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2886 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2887           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2888
2889 // raddhn2 patterns
2890 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2891 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2892 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2893
2894 // rsubhn2 patterns
2895 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2896 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2897 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2898
2899 // pattern that need to extend result
2900 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2901                      string asmop, string ResS, string OpS,
2902                      SDPatternOperator opnode,
2903                      RegisterOperand OpVPR,
2904                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2905   : NeonI_3VDiff<q, u, size, opcode,
2906                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2907                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2908                  [(set (ResTy VPR128:$Rd),
2909                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2910                                                 (OpTy OpVPR:$Rm))))))],
2911                  NoItinerary>;
2912
2913 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2914                            SDPatternOperator opnode, bit Commutable = 0> {
2915   let isCommutable = Commutable in {
2916     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2917                                opnode, VPR64, v8i16, v8i8, v8i8>;
2918     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2919                                opnode, VPR64, v4i32, v4i16, v4i16>;
2920     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2921                                opnode, VPR64, v2i64, v2i32, v2i32>;
2922   }
2923 }
2924
2925 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2926 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2927
2928 multiclass NeonI_Op_High<SDPatternOperator op> {
2929   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2930                      (op (v8i8 (Neon_High16B node:$Rn)),
2931                          (v8i8 (Neon_High16B node:$Rm)))>;
2932   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
2933                      (op (v4i16 (Neon_High8H node:$Rn)),
2934                          (v4i16 (Neon_High8H node:$Rm)))>;
2935   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
2936                      (op (v2i32 (Neon_High4S node:$Rn)),
2937                          (v2i32 (Neon_High4S node:$Rm)))>;
2938 }
2939
2940 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2941 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2942 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2943 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2944 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2945 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2946
2947 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2948                             bit Commutable = 0> {
2949   let isCommutable = Commutable in {
2950     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2951                                 !cast<PatFrag>(opnode # "_16B"),
2952                                 VPR128, v8i16, v16i8, v8i8>;
2953     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2954                                 !cast<PatFrag>(opnode # "_8H"),
2955                                 VPR128, v4i32, v8i16, v4i16>;
2956     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2957                                 !cast<PatFrag>(opnode # "_4S"),
2958                                 VPR128, v2i64, v4i32, v2i32>;
2959   }
2960 }
2961
2962 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2963 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2964
2965 // For pattern that need two operators being chained.
2966 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2967                      string asmop, string ResS, string OpS,
2968                      SDPatternOperator opnode, SDPatternOperator subop,
2969                      RegisterOperand OpVPR,
2970                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2971   : NeonI_3VDiff<q, u, size, opcode,
2972                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2973                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2974                  [(set (ResTy VPR128:$Rd),
2975                     (ResTy (opnode
2976                       (ResTy VPR128:$src),
2977                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2978                                                  (OpTy OpVPR:$Rm))))))))],
2979                  NoItinerary> {
2980   let Constraints = "$src = $Rd";
2981 }
2982
2983 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2984                              SDPatternOperator opnode, SDPatternOperator subop>{
2985   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2986                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2987   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2988                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2989   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2990                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2991 }
2992
2993 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2994                                    add, int_arm_neon_vabds>;
2995 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2996                                    add, int_arm_neon_vabdu>;
2997
2998 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2999                               SDPatternOperator opnode, string subop> {
3000   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3001                              opnode, !cast<PatFrag>(subop # "_16B"),
3002                              VPR128, v8i16, v16i8, v8i8>;
3003   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3004                              opnode, !cast<PatFrag>(subop # "_8H"),
3005                              VPR128, v4i32, v8i16, v4i16>;
3006   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3007                              opnode, !cast<PatFrag>(subop # "_4S"),
3008                              VPR128, v2i64, v4i32, v2i32>;
3009 }
3010
3011 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
3012                                      "NI_sabdl_hi">;
3013 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
3014                                      "NI_uabdl_hi">;
3015
3016 // Long pattern with 2 operands
3017 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
3018                           SDPatternOperator opnode, bit Commutable = 0> {
3019   let isCommutable = Commutable in {
3020     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3021                               opnode, VPR128, VPR64, v8i16, v8i8>;
3022     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3023                               opnode, VPR128, VPR64, v4i32, v4i16>;
3024     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3025                               opnode, VPR128, VPR64, v2i64, v2i32>;
3026   }
3027 }
3028
3029 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
3030 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
3031
3032 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
3033                            string asmop, string ResS, string OpS,
3034                            SDPatternOperator opnode,
3035                            ValueType ResTy, ValueType OpTy>
3036   : NeonI_3VDiff<q, u, size, opcode,
3037                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3038                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3039                  [(set (ResTy VPR128:$Rd),
3040                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
3041                  NoItinerary>;
3042
3043 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
3044                                    string opnode, bit Commutable = 0> {
3045   let isCommutable = Commutable in {
3046     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3047                                       !cast<PatFrag>(opnode # "_16B"),
3048                                       v8i16, v16i8>;
3049     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3050                                      !cast<PatFrag>(opnode # "_8H"),
3051                                      v4i32, v8i16>;
3052     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3053                                      !cast<PatFrag>(opnode # "_4S"),
3054                                      v2i64, v4i32>;
3055   }
3056 }
3057
3058 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
3059                                          "NI_smull_hi", 1>;
3060 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
3061                                          "NI_umull_hi", 1>;
3062
3063 // Long pattern with 3 operands
3064 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
3065                      string asmop, string ResS, string OpS,
3066                      SDPatternOperator opnode,
3067                      ValueType ResTy, ValueType OpTy>
3068   : NeonI_3VDiff<q, u, size, opcode,
3069                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
3070                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3071                  [(set (ResTy VPR128:$Rd),
3072                     (ResTy (opnode
3073                       (ResTy VPR128:$src),
3074                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
3075                NoItinerary> {
3076   let Constraints = "$src = $Rd";
3077 }
3078
3079 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
3080                              SDPatternOperator opnode> {
3081   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3082                              opnode, v8i16, v8i8>;
3083   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3084                              opnode, v4i32, v4i16>;
3085   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3086                              opnode, v2i64, v2i32>;
3087 }
3088
3089 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3090                          (add node:$Rd,
3091                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3092
3093 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3094                          (add node:$Rd,
3095                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3096
3097 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3098                          (sub node:$Rd,
3099                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3100
3101 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3102                          (sub node:$Rd,
3103                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3104
3105 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
3106 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
3107
3108 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
3109 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
3110
3111 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
3112                            string asmop, string ResS, string OpS,
3113                            SDPatternOperator subop, SDPatternOperator opnode,
3114                            RegisterOperand OpVPR,
3115                            ValueType ResTy, ValueType OpTy>
3116   : NeonI_3VDiff<q, u, size, opcode,
3117                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3118                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3119                [(set (ResTy VPR128:$Rd),
3120                   (ResTy (subop
3121                     (ResTy VPR128:$src),
3122                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
3123                NoItinerary> {
3124   let Constraints = "$src = $Rd";
3125 }
3126
3127 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
3128                                    SDPatternOperator subop, string opnode> {
3129   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3130                                     subop, !cast<PatFrag>(opnode # "_16B"),
3131                                     VPR128, v8i16, v16i8>;
3132   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3133                                    subop, !cast<PatFrag>(opnode # "_8H"),
3134                                    VPR128, v4i32, v8i16>;
3135   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3136                                    subop, !cast<PatFrag>(opnode # "_4S"),
3137                                    VPR128, v2i64, v4i32>;
3138 }
3139
3140 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
3141                                           add, "NI_smull_hi">;
3142 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
3143                                           add, "NI_umull_hi">;
3144
3145 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
3146                                           sub, "NI_smull_hi">;
3147 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
3148                                           sub, "NI_umull_hi">;
3149
3150 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
3151                                     SDPatternOperator opnode> {
3152   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3153                                    opnode, int_arm_neon_vqdmull,
3154                                    VPR64, v4i32, v4i16>;
3155   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3156                                    opnode, int_arm_neon_vqdmull,
3157                                    VPR64, v2i64, v2i32>;
3158 }
3159
3160 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
3161                                            int_arm_neon_vqadds>;
3162 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
3163                                            int_arm_neon_vqsubs>;
3164
3165 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3166                          SDPatternOperator opnode, bit Commutable = 0> {
3167   let isCommutable = Commutable in {
3168     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3169                               opnode, VPR128, VPR64, v4i32, v4i16>;
3170     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3171                               opnode, VPR128, VPR64, v2i64, v2i32>;
3172   }
3173 }
3174
3175 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3176                                 int_arm_neon_vqdmull, 1>;
3177
3178 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3179                                    string opnode, bit Commutable = 0> {
3180   let isCommutable = Commutable in {
3181     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3182                                      !cast<PatFrag>(opnode # "_8H"),
3183                                      v4i32, v8i16>;
3184     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3185                                      !cast<PatFrag>(opnode # "_4S"),
3186                                      v2i64, v4i32>;
3187   }
3188 }
3189
3190 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3191                                            "NI_qdmull_hi", 1>;
3192
3193 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3194                                      SDPatternOperator opnode> {
3195   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3196                                    opnode, NI_qdmull_hi_8H,
3197                                    VPR128, v4i32, v8i16>;
3198   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3199                                    opnode, NI_qdmull_hi_4S,
3200                                    VPR128, v2i64, v4i32>;
3201 }
3202
3203 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3204                                              int_arm_neon_vqadds>;
3205 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3206                                              int_arm_neon_vqsubs>;
3207
3208 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3209                          SDPatternOperator opnode_8h8b,
3210                          SDPatternOperator opnode_1q1d, bit Commutable = 0> {
3211   let isCommutable = Commutable in {
3212     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3213                               opnode_8h8b, VPR128, VPR64, v8i16, v8i8>;
3214
3215     def _1q1d : NeonI_3VD_2Op<0b0, u, 0b11, opcode, asmop, "1q", "1d",
3216                               opnode_1q1d, VPR128, VPR64, v16i8, v1i64>;
3217   }
3218 }
3219
3220 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
3221                               int_aarch64_neon_vmull_p64, 1>;
3222
3223 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3224                                    string opnode, bit Commutable = 0> {
3225   let isCommutable = Commutable in {
3226     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3227                                       !cast<PatFrag>(opnode # "_16B"),
3228                                       v8i16, v16i8>;
3229
3230     def _1q2d :
3231       NeonI_3VDiff<0b1, u, 0b11, opcode,
3232                    (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3233                    asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3234                    [(set (v16i8 VPR128:$Rd),
3235                       (v16i8 (int_aarch64_neon_vmull_p64
3236                         (v1i64 (scalar_to_vector
3237                           (i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
3238                         (v1i64 (scalar_to_vector
3239                           (i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
3240                    NoItinerary>;
3241   }
3242 }
3243
3244 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3245                                          1>;
3246
3247 // End of implementation for instruction class (3V Diff)
3248
3249 // The followings are vector load/store multiple N-element structure
3250 // (class SIMD lselem).
3251
3252 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
3253 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3254 //              The structure consists of a sequence of sets of N values.
3255 //              The first element of the structure is placed in the first lane
3256 //              of the first first vector, the second element in the first lane
3257 //              of the second vector, and so on.
3258 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3259 // the three 64-bit vectors list {BA, DC, FE}.
3260 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3261 // 64-bit vectors list {DA, EB, FC}.
3262 // Store instructions store multiple structure to N registers like load.
3263
3264
3265 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3266                     RegisterOperand VecList, string asmop>
3267   : NeonI_LdStMult<q, 1, opcode, size,
3268                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3269                  asmop # "\t$Rt, [$Rn]",
3270                  [],
3271                  NoItinerary> {
3272   let mayLoad = 1;
3273   let neverHasSideEffects = 1;
3274 }
3275
3276 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3277   def _8B : NeonI_LDVList<0, opcode, 0b00,
3278                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3279
3280   def _4H : NeonI_LDVList<0, opcode, 0b01,
3281                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3282
3283   def _2S : NeonI_LDVList<0, opcode, 0b10,
3284                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3285
3286   def _16B : NeonI_LDVList<1, opcode, 0b00,
3287                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3288
3289   def _8H : NeonI_LDVList<1, opcode, 0b01,
3290                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3291
3292   def _4S : NeonI_LDVList<1, opcode, 0b10,
3293                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3294
3295   def _2D : NeonI_LDVList<1, opcode, 0b11,
3296                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3297 }
3298
3299 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3300 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3301 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3302
3303 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3304
3305 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3306
3307 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3308
3309 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3310 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3311 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3312
3313 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3314 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3315
3316 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3317 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3318
3319 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3320                     RegisterOperand VecList, string asmop>
3321   : NeonI_LdStMult<q, 0, opcode, size,
3322                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3323                  asmop # "\t$Rt, [$Rn]",
3324                  [],
3325                  NoItinerary> {
3326   let mayStore = 1;
3327   let neverHasSideEffects = 1;
3328 }
3329
3330 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3331   def _8B : NeonI_STVList<0, opcode, 0b00,
3332                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3333
3334   def _4H : NeonI_STVList<0, opcode, 0b01,
3335                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3336
3337   def _2S : NeonI_STVList<0, opcode, 0b10,
3338                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3339
3340   def _16B : NeonI_STVList<1, opcode, 0b00,
3341                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3342
3343   def _8H : NeonI_STVList<1, opcode, 0b01,
3344                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3345
3346   def _4S : NeonI_STVList<1, opcode, 0b10,
3347                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3348
3349   def _2D : NeonI_STVList<1, opcode, 0b11,
3350                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3351 }
3352
3353 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3354 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3355 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3356
3357 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3358
3359 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3360
3361 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3362
3363 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3364 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3365 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3366
3367 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3368 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3369
3370 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3371 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3372
3373 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3374 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3375
3376 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3377 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3378
3379 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3380 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3381
3382 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3383 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3384
3385 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3386 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3387
3388 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3389 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3390
3391 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3392           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3393 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3394           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3395
3396 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3397           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3398 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3399           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3400
3401 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3402           (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3403 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3404           (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3405
3406 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3407           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3408 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3409           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3410
3411 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3412           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3413 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3414           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3415
3416 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3417           (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3418 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3419           (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3420
3421 // Match load/store of v1i8/v1i16/v1i32 type to FPR8/FPR16/FPR32 load/store.
3422 // FIXME: for now we have v1i8, v1i16, v1i32 legal types, if they are illegal,
3423 // these patterns are not needed any more.
3424 def : Pat<(v1i8 (load GPR64xsp:$addr)), (LSFP8_LDR $addr, 0)>;
3425 def : Pat<(v1i16 (load GPR64xsp:$addr)), (LSFP16_LDR $addr, 0)>;
3426 def : Pat<(v1i32 (load GPR64xsp:$addr)), (LSFP32_LDR $addr, 0)>;
3427
3428 def : Pat<(store (v1i8 FPR8:$value), GPR64xsp:$addr),
3429           (LSFP8_STR $value, $addr, 0)>;
3430 def : Pat<(store (v1i16 FPR16:$value), GPR64xsp:$addr),
3431           (LSFP16_STR $value, $addr, 0)>;
3432 def : Pat<(store (v1i32 FPR32:$value), GPR64xsp:$addr),
3433           (LSFP32_STR $value, $addr, 0)>;
3434
3435
3436 // End of vector load/store multiple N-element structure(class SIMD lselem)
3437
3438 // The followings are post-index vector load/store multiple N-element
3439 // structure(class SIMD lselem-post)
3440 def exact1_asmoperand : AsmOperandClass {
3441   let Name = "Exact1";
3442   let PredicateMethod = "isExactImm<1>";
3443   let RenderMethod = "addImmOperands";
3444 }
3445 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3446   let ParserMatchClass = exact1_asmoperand;
3447 }
3448
3449 def exact2_asmoperand : AsmOperandClass {
3450   let Name = "Exact2";
3451   let PredicateMethod = "isExactImm<2>";
3452   let RenderMethod = "addImmOperands";
3453 }
3454 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3455   let ParserMatchClass = exact2_asmoperand;
3456 }
3457
3458 def exact3_asmoperand : AsmOperandClass {
3459   let Name = "Exact3";
3460   let PredicateMethod = "isExactImm<3>";
3461   let RenderMethod = "addImmOperands";
3462 }
3463 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3464   let ParserMatchClass = exact3_asmoperand;
3465 }
3466
3467 def exact4_asmoperand : AsmOperandClass {
3468   let Name = "Exact4";
3469   let PredicateMethod = "isExactImm<4>";
3470   let RenderMethod = "addImmOperands";
3471 }
3472 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3473   let ParserMatchClass = exact4_asmoperand;
3474 }
3475
3476 def exact6_asmoperand : AsmOperandClass {
3477   let Name = "Exact6";
3478   let PredicateMethod = "isExactImm<6>";
3479   let RenderMethod = "addImmOperands";
3480 }
3481 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3482   let ParserMatchClass = exact6_asmoperand;
3483 }
3484
3485 def exact8_asmoperand : AsmOperandClass {
3486   let Name = "Exact8";
3487   let PredicateMethod = "isExactImm<8>";
3488   let RenderMethod = "addImmOperands";
3489 }
3490 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3491   let ParserMatchClass = exact8_asmoperand;
3492 }
3493
3494 def exact12_asmoperand : AsmOperandClass {
3495   let Name = "Exact12";
3496   let PredicateMethod = "isExactImm<12>";
3497   let RenderMethod = "addImmOperands";
3498 }
3499 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3500   let ParserMatchClass = exact12_asmoperand;
3501 }
3502
3503 def exact16_asmoperand : AsmOperandClass {
3504   let Name = "Exact16";
3505   let PredicateMethod = "isExactImm<16>";
3506   let RenderMethod = "addImmOperands";
3507 }
3508 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3509   let ParserMatchClass = exact16_asmoperand;
3510 }
3511
3512 def exact24_asmoperand : AsmOperandClass {
3513   let Name = "Exact24";
3514   let PredicateMethod = "isExactImm<24>";
3515   let RenderMethod = "addImmOperands";
3516 }
3517 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3518   let ParserMatchClass = exact24_asmoperand;
3519 }
3520
3521 def exact32_asmoperand : AsmOperandClass {
3522   let Name = "Exact32";
3523   let PredicateMethod = "isExactImm<32>";
3524   let RenderMethod = "addImmOperands";
3525 }
3526 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3527   let ParserMatchClass = exact32_asmoperand;
3528 }
3529
3530 def exact48_asmoperand : AsmOperandClass {
3531   let Name = "Exact48";
3532   let PredicateMethod = "isExactImm<48>";
3533   let RenderMethod = "addImmOperands";
3534 }
3535 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3536   let ParserMatchClass = exact48_asmoperand;
3537 }
3538
3539 def exact64_asmoperand : AsmOperandClass {
3540   let Name = "Exact64";
3541   let PredicateMethod = "isExactImm<64>";
3542   let RenderMethod = "addImmOperands";
3543 }
3544 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3545   let ParserMatchClass = exact64_asmoperand;
3546 }
3547
3548 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3549                            RegisterOperand VecList, Operand ImmTy,
3550                            string asmop> {
3551   let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3552       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3553     def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3554                      (outs VecList:$Rt, GPR64xsp:$wb),
3555                      (ins GPR64xsp:$Rn, ImmTy:$amt),
3556                      asmop # "\t$Rt, [$Rn], $amt",
3557                      [],
3558                      NoItinerary> {
3559       let Rm = 0b11111;
3560     }
3561
3562     def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3563                         (outs VecList:$Rt, GPR64xsp:$wb),
3564                         (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3565                         asmop # "\t$Rt, [$Rn], $Rm",
3566                         [],
3567                         NoItinerary>;
3568   }
3569 }
3570
3571 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3572     Operand ImmTy2, string asmop> {
3573   defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3574                               !cast<RegisterOperand>(List # "8B_operand"),
3575                               ImmTy, asmop>;
3576
3577   defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3578                               !cast<RegisterOperand>(List # "4H_operand"),
3579                               ImmTy, asmop>;
3580
3581   defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3582                               !cast<RegisterOperand>(List # "2S_operand"),
3583                               ImmTy, asmop>;
3584
3585   defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3586                                !cast<RegisterOperand>(List # "16B_operand"),
3587                                ImmTy2, asmop>;
3588
3589   defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3590                               !cast<RegisterOperand>(List # "8H_operand"),
3591                               ImmTy2, asmop>;
3592
3593   defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3594                               !cast<RegisterOperand>(List # "4S_operand"),
3595                               ImmTy2, asmop>;
3596
3597   defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3598                               !cast<RegisterOperand>(List # "2D_operand"),
3599                               ImmTy2, asmop>;
3600 }
3601
3602 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3603 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3604 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3605                                  "ld1">;
3606
3607 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3608
3609 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3610                              "ld3">;
3611
3612 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3613
3614 // Post-index load multiple 1-element structures from N consecutive registers
3615 // (N = 2,3,4)
3616 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3617                                "ld1">;
3618 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3619                                    uimm_exact16, "ld1">;
3620
3621 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3622                                "ld1">;
3623 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3624                                    uimm_exact24, "ld1">;
3625
3626 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3627                                 "ld1">;
3628 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3629                                    uimm_exact32, "ld1">;
3630
3631 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3632                             RegisterOperand VecList, Operand ImmTy,
3633                             string asmop> {
3634   let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3635       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3636     def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3637                      (outs GPR64xsp:$wb),
3638                      (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3639                      asmop # "\t$Rt, [$Rn], $amt",
3640                      [],
3641                      NoItinerary> {
3642       let Rm = 0b11111;
3643     }
3644
3645     def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3646                       (outs GPR64xsp:$wb),
3647                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3648                       asmop # "\t$Rt, [$Rn], $Rm",
3649                       [],
3650                       NoItinerary>;
3651   }
3652 }
3653
3654 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3655                            Operand ImmTy2, string asmop> {
3656   defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3657                  !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3658
3659   defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3660                               !cast<RegisterOperand>(List # "4H_operand"),
3661                               ImmTy, asmop>;
3662
3663   defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3664                               !cast<RegisterOperand>(List # "2S_operand"),
3665                               ImmTy, asmop>;
3666
3667   defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3668                                !cast<RegisterOperand>(List # "16B_operand"),
3669                                ImmTy2, asmop>;
3670
3671   defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3672                               !cast<RegisterOperand>(List # "8H_operand"),
3673                               ImmTy2, asmop>;
3674
3675   defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3676                               !cast<RegisterOperand>(List # "4S_operand"),
3677                               ImmTy2, asmop>;
3678
3679   defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3680                               !cast<RegisterOperand>(List # "2D_operand"),
3681                               ImmTy2, asmop>;
3682 }
3683
3684 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3685 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3686 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3687                                  "st1">;
3688
3689 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3690
3691 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3692                              "st3">;
3693
3694 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3695
3696 // Post-index load multiple 1-element structures from N consecutive registers
3697 // (N = 2,3,4)
3698 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3699                                "st1">;
3700 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3701                                    uimm_exact16, "st1">;
3702
3703 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3704                                "st1">;
3705 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3706                                    uimm_exact24, "st1">;
3707
3708 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3709                                "st1">;
3710 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3711                                    uimm_exact32, "st1">;
3712
3713 // End of post-index vector load/store multiple N-element structure
3714 // (class SIMD lselem-post)
3715
3716 // The followings are vector load/store single N-element structure
3717 // (class SIMD lsone).
3718 def neon_uimm0_bare : Operand<i64>,
3719                         ImmLeaf<i64, [{return Imm == 0;}]> {
3720   let ParserMatchClass = neon_uimm0_asmoperand;
3721   let PrintMethod = "printUImmBareOperand";
3722 }
3723
3724 def neon_uimm1_bare : Operand<i64>,
3725                         ImmLeaf<i64, [{return Imm < 2;}]> {
3726   let ParserMatchClass = neon_uimm1_asmoperand;
3727   let PrintMethod = "printUImmBareOperand";
3728 }
3729
3730 def neon_uimm2_bare : Operand<i64>,
3731                         ImmLeaf<i64, [{return Imm < 4;}]> {
3732   let ParserMatchClass = neon_uimm2_asmoperand;
3733   let PrintMethod = "printUImmBareOperand";
3734 }
3735
3736 def neon_uimm3_bare : Operand<i64>,
3737                         ImmLeaf<i64, [{return Imm < 8;}]> {
3738   let ParserMatchClass = uimm3_asmoperand;
3739   let PrintMethod = "printUImmBareOperand";
3740 }
3741
3742 def neon_uimm4_bare : Operand<i64>,
3743                         ImmLeaf<i64, [{return Imm < 16;}]> {
3744   let ParserMatchClass = uimm4_asmoperand;
3745   let PrintMethod = "printUImmBareOperand";
3746 }
3747
3748 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3749                     RegisterOperand VecList, string asmop>
3750     : NeonI_LdOne_Dup<q, r, opcode, size,
3751                       (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3752                       asmop # "\t$Rt, [$Rn]",
3753                       [],
3754                       NoItinerary> {
3755   let mayLoad = 1;
3756   let neverHasSideEffects = 1;
3757 }
3758
3759 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3760   def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3761                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3762
3763   def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3764                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3765
3766   def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3767                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3768
3769   def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3770                           !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3771
3772   def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3773                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3774
3775   def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3776                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3777
3778   def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3779                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3780
3781   def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3782                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3783 }
3784
3785 // Load single 1-element structure to all lanes of 1 register
3786 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3787
3788 // Load single N-element structure to all lanes of N consecutive
3789 // registers (N = 2,3,4)
3790 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3791 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3792 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3793
3794
3795 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3796                     Instruction INST>
3797     : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3798           (VTy (INST GPR64xsp:$Rn))>;
3799
3800 // Match all LD1R instructions
3801 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3802
3803 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3804
3805 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3806
3807 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3808
3809 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3810 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3811
3812 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3813 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3814
3815 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3816 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3817
3818 class LD1R_pattern_v1 <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3819                        Instruction INST>
3820   : Pat<(VTy (scalar_to_vector (DTy (LoadOp GPR64xsp:$Rn)))),
3821         (VTy (INST GPR64xsp:$Rn))>;
3822
3823 def : LD1R_pattern_v1<v1i64, i64, load, LD1R_1D>;
3824 def : LD1R_pattern_v1<v1f64, f64, load, LD1R_1D>;
3825
3826 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3827                                 RegisterClass RegList> {
3828   defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3829   defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3830   defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3831   defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3832 }
3833
3834 // Special vector list operand of 128-bit vectors with bare layout.
3835 // i.e. only show ".b", ".h", ".s", ".d"
3836 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3837 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3838 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3839 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3840
3841 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3842                      Operand ImmOp, string asmop>
3843     : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3844                          (outs VList:$Rt),
3845                          (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3846                          asmop # "\t$Rt[$lane], [$Rn]",
3847                          [],
3848                          NoItinerary> {
3849   let mayLoad = 1;
3850   let neverHasSideEffects = 1;
3851   let hasExtraDefRegAllocReq = 1;
3852   let Constraints = "$src = $Rt";
3853 }
3854
3855 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3856   def _B : NeonI_LDN_Lane<r, 0b00, op0,
3857                           !cast<RegisterOperand>(List # "B_operand"),
3858                           neon_uimm4_bare, asmop> {
3859     let Inst{12-10} = lane{2-0};
3860     let Inst{30} = lane{3};
3861   }
3862
3863   def _H : NeonI_LDN_Lane<r, 0b01, op0,
3864                           !cast<RegisterOperand>(List # "H_operand"),
3865                           neon_uimm3_bare, asmop> {
3866     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3867     let Inst{30} = lane{2};
3868   }
3869
3870   def _S : NeonI_LDN_Lane<r, 0b10, op0,
3871                           !cast<RegisterOperand>(List # "S_operand"),
3872                           neon_uimm2_bare, asmop> {
3873     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3874     let Inst{30} = lane{1};
3875   }
3876
3877   def _D : NeonI_LDN_Lane<r, 0b10, op0,
3878                           !cast<RegisterOperand>(List # "D_operand"),
3879                           neon_uimm1_bare, asmop> {
3880     let Inst{12-10} = 0b001;
3881     let Inst{30} = lane{0};
3882   }
3883 }
3884
3885 // Load single 1-element structure to one lane of 1 register.
3886 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3887
3888 // Load single N-element structure to one lane of N consecutive registers
3889 // (N = 2,3,4)
3890 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3891 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3892 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3893
3894 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3895                           Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3896                           Instruction INST> {
3897   def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3898                      (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3899             (VTy (EXTRACT_SUBREG
3900                      (INST GPR64xsp:$Rn,
3901                            (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3902                            ImmOp:$lane),
3903                      sub_64))>;
3904
3905   def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3906                       (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3907             (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3908 }
3909
3910 // Match all LD1LN instructions
3911 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3912                       extloadi8, LD1LN_B>;
3913
3914 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3915                       extloadi16, LD1LN_H>;
3916
3917 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3918                       load, LD1LN_S>;
3919 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3920                       load, LD1LN_S>;
3921
3922 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3923                       load, LD1LN_D>;
3924 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3925                       load, LD1LN_D>;
3926
3927 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3928                      Operand ImmOp, string asmop>
3929     : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3930                          (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3931                          asmop # "\t$Rt[$lane], [$Rn]",
3932                          [],
3933                          NoItinerary> {
3934   let mayStore = 1;
3935   let neverHasSideEffects = 1;
3936   let hasExtraDefRegAllocReq = 1;
3937 }
3938
3939 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3940   def _B : NeonI_STN_Lane<r, 0b00, op0,
3941                           !cast<RegisterOperand>(List # "B_operand"),
3942                           neon_uimm4_bare, asmop> {
3943     let Inst{12-10} = lane{2-0};
3944     let Inst{30} = lane{3};
3945   }
3946
3947   def _H : NeonI_STN_Lane<r, 0b01, op0,
3948                           !cast<RegisterOperand>(List # "H_operand"),
3949                           neon_uimm3_bare, asmop> {
3950     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3951     let Inst{30} = lane{2};
3952   }
3953
3954   def _S : NeonI_STN_Lane<r, 0b10, op0,
3955                           !cast<RegisterOperand>(List # "S_operand"),
3956                            neon_uimm2_bare, asmop> {
3957     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3958     let Inst{30} = lane{1};
3959   }
3960
3961   def _D : NeonI_STN_Lane<r, 0b10, op0,
3962                           !cast<RegisterOperand>(List # "D_operand"),
3963                           neon_uimm1_bare, asmop>{
3964     let Inst{12-10} = 0b001;
3965     let Inst{30} = lane{0};
3966   }
3967 }
3968
3969 // Store single 1-element structure from one lane of 1 register.
3970 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3971
3972 // Store single N-element structure from one lane of N consecutive registers
3973 // (N = 2,3,4)
3974 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3975 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3976 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3977
3978 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3979                           Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3980                           Instruction INST> {
3981   def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3982                      GPR64xsp:$Rn),
3983             (INST GPR64xsp:$Rn,
3984                   (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3985                   ImmOp:$lane)>;
3986
3987   def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3988                      GPR64xsp:$Rn),
3989             (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3990 }
3991
3992 // Match all ST1LN instructions
3993 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3994                       truncstorei8, ST1LN_B>;
3995
3996 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3997                       truncstorei16, ST1LN_H>;
3998
3999 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
4000                       store, ST1LN_S>;
4001 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
4002                       store, ST1LN_S>;
4003
4004 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
4005                       store, ST1LN_D>;
4006 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
4007                       store, ST1LN_D>;
4008
4009 // End of vector load/store single N-element structure (class SIMD lsone).
4010
4011
4012 // The following are post-index load/store single N-element instructions
4013 // (class SIMD lsone-post)
4014
4015 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
4016                             RegisterOperand VecList, Operand ImmTy,
4017                             string asmop> {
4018   let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
4019   DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4020     def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4021                       (outs VecList:$Rt, GPR64xsp:$wb),
4022                       (ins GPR64xsp:$Rn, ImmTy:$amt),
4023                       asmop # "\t$Rt, [$Rn], $amt",
4024                       [],
4025                       NoItinerary> {
4026                         let Rm = 0b11111;
4027                       }
4028
4029     def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4030                       (outs VecList:$Rt, GPR64xsp:$wb),
4031                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
4032                       asmop # "\t$Rt, [$Rn], $Rm",
4033                       [],
4034                       NoItinerary>;
4035   }
4036 }
4037
4038 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
4039                          Operand uimm_b, Operand uimm_h,
4040                          Operand uimm_s, Operand uimm_d> {
4041   defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
4042                               !cast<RegisterOperand>(List # "8B_operand"),
4043                               uimm_b, asmop>;
4044
4045   defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
4046                               !cast<RegisterOperand>(List # "4H_operand"),
4047                               uimm_h, asmop>;
4048
4049   defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
4050                               !cast<RegisterOperand>(List # "2S_operand"),
4051                               uimm_s, asmop>;
4052
4053   defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
4054                               !cast<RegisterOperand>(List # "1D_operand"),
4055                               uimm_d, asmop>;
4056
4057   defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
4058                                !cast<RegisterOperand>(List # "16B_operand"),
4059                                uimm_b, asmop>;
4060
4061   defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
4062                               !cast<RegisterOperand>(List # "8H_operand"),
4063                               uimm_h, asmop>;
4064
4065   defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
4066                               !cast<RegisterOperand>(List # "4S_operand"),
4067                               uimm_s, asmop>;
4068
4069   defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
4070                               !cast<RegisterOperand>(List # "2D_operand"),
4071                               uimm_d, asmop>;
4072 }
4073
4074 // Post-index load single 1-element structure to all lanes of 1 register
4075 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
4076                              uimm_exact2, uimm_exact4, uimm_exact8>;
4077
4078 // Post-index load single N-element structure to all lanes of N consecutive
4079 // registers (N = 2,3,4)
4080 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
4081                              uimm_exact4, uimm_exact8, uimm_exact16>;
4082 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
4083                              uimm_exact6, uimm_exact12, uimm_exact24>;
4084 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
4085                              uimm_exact8, uimm_exact16, uimm_exact32>;
4086
4087 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
4088     Constraints = "$Rn = $wb, $Rt = $src",
4089     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4090   class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4091                                 Operand ImmTy, Operand ImmOp, string asmop>
4092       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4093                                 (outs VList:$Rt, GPR64xsp:$wb),
4094                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
4095                                     VList:$src, ImmOp:$lane),
4096                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
4097                                 [],
4098                                 NoItinerary> {
4099     let Rm = 0b11111;
4100   }
4101
4102   class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4103                                  Operand ImmTy, Operand ImmOp, string asmop>
4104       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4105                                 (outs VList:$Rt, GPR64xsp:$wb),
4106                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
4107                                     VList:$src, ImmOp:$lane),
4108                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4109                                 [],
4110                                 NoItinerary>;
4111 }
4112
4113 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4114                            Operand uimm_b, Operand uimm_h,
4115                            Operand uimm_s, Operand uimm_d> {
4116   def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
4117                                !cast<RegisterOperand>(List # "B_operand"),
4118                                uimm_b, neon_uimm4_bare, asmop> {
4119     let Inst{12-10} = lane{2-0};
4120     let Inst{30} = lane{3};
4121   }
4122
4123   def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
4124                                    !cast<RegisterOperand>(List # "B_operand"),
4125                                    uimm_b, neon_uimm4_bare, asmop> {
4126     let Inst{12-10} = lane{2-0};
4127     let Inst{30} = lane{3};
4128   }
4129
4130   def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
4131                                !cast<RegisterOperand>(List # "H_operand"),
4132                                uimm_h, neon_uimm3_bare, asmop> {
4133     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4134     let Inst{30} = lane{2};
4135   }
4136
4137   def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
4138                                    !cast<RegisterOperand>(List # "H_operand"),
4139                                    uimm_h, neon_uimm3_bare, asmop> {
4140     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4141     let Inst{30} = lane{2};
4142   }
4143
4144   def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4145                                !cast<RegisterOperand>(List # "S_operand"),
4146                                uimm_s, neon_uimm2_bare, asmop> {
4147     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4148     let Inst{30} = lane{1};
4149   }
4150
4151   def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
4152                                    !cast<RegisterOperand>(List # "S_operand"),
4153                                    uimm_s, neon_uimm2_bare, asmop> {
4154     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4155     let Inst{30} = lane{1};
4156   }
4157
4158   def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4159                                !cast<RegisterOperand>(List # "D_operand"),
4160                                uimm_d, neon_uimm1_bare, asmop> {
4161     let Inst{12-10} = 0b001;
4162     let Inst{30} = lane{0};
4163   }
4164
4165   def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
4166                                    !cast<RegisterOperand>(List # "D_operand"),
4167                                    uimm_d, neon_uimm1_bare, asmop> {
4168     let Inst{12-10} = 0b001;
4169     let Inst{30} = lane{0};
4170   }
4171 }
4172
4173 // Post-index load single 1-element structure to one lane of 1 register.
4174 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
4175                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4176
4177 // Post-index load single N-element structure to one lane of N consecutive
4178 // registers
4179 // (N = 2,3,4)
4180 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
4181                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4182 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
4183                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4184 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4185                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4186
4187 let mayStore = 1, neverHasSideEffects = 1,
4188     hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4189     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4190   class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4191                       Operand ImmTy, Operand ImmOp, string asmop>
4192       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4193                                 (outs GPR64xsp:$wb),
4194                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
4195                                     VList:$Rt, ImmOp:$lane),
4196                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
4197                                 [],
4198                                 NoItinerary> {
4199     let Rm = 0b11111;
4200   }
4201
4202   class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4203                        Operand ImmTy, Operand ImmOp, string asmop>
4204       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4205                                 (outs GPR64xsp:$wb),
4206                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4207                                     ImmOp:$lane),
4208                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4209                                 [],
4210                                 NoItinerary>;
4211 }
4212
4213 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4214                            Operand uimm_b, Operand uimm_h,
4215                            Operand uimm_s, Operand uimm_d> {
4216   def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4217                                !cast<RegisterOperand>(List # "B_operand"),
4218                                uimm_b, neon_uimm4_bare, asmop> {
4219     let Inst{12-10} = lane{2-0};
4220     let Inst{30} = lane{3};
4221   }
4222
4223   def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4224                                    !cast<RegisterOperand>(List # "B_operand"),
4225                                    uimm_b, neon_uimm4_bare, asmop> {
4226     let Inst{12-10} = lane{2-0};
4227     let Inst{30} = lane{3};
4228   }
4229
4230   def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4231                                !cast<RegisterOperand>(List # "H_operand"),
4232                                uimm_h, neon_uimm3_bare, asmop> {
4233     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4234     let Inst{30} = lane{2};
4235   }
4236
4237   def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4238                                    !cast<RegisterOperand>(List # "H_operand"),
4239                                    uimm_h, neon_uimm3_bare, asmop> {
4240     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4241     let Inst{30} = lane{2};
4242   }
4243
4244   def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4245                                !cast<RegisterOperand>(List # "S_operand"),
4246                                uimm_s, neon_uimm2_bare, asmop> {
4247     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4248     let Inst{30} = lane{1};
4249   }
4250
4251   def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4252                                    !cast<RegisterOperand>(List # "S_operand"),
4253                                    uimm_s, neon_uimm2_bare, asmop> {
4254     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4255     let Inst{30} = lane{1};
4256   }
4257
4258   def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4259                                !cast<RegisterOperand>(List # "D_operand"),
4260                                uimm_d, neon_uimm1_bare, asmop> {
4261     let Inst{12-10} = 0b001;
4262     let Inst{30} = lane{0};
4263   }
4264
4265   def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4266                                    !cast<RegisterOperand>(List # "D_operand"),
4267                                    uimm_d, neon_uimm1_bare, asmop> {
4268     let Inst{12-10} = 0b001;
4269     let Inst{30} = lane{0};
4270   }
4271 }
4272
4273 // Post-index store single 1-element structure from one lane of 1 register.
4274 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4275                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4276
4277 // Post-index store single N-element structure from one lane of N consecutive
4278 // registers (N = 2,3,4)
4279 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4280                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4281 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4282                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4283 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4284                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4285
4286 // End of post-index load/store single N-element instructions
4287 // (class SIMD lsone-post)
4288
4289 // Neon Scalar instructions implementation
4290 // Scalar Three Same
4291
4292 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4293                              RegisterClass FPRC>
4294   : NeonI_Scalar3Same<u, size, opcode,
4295                       (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4296                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4297                       [],
4298                       NoItinerary>;
4299
4300 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4301   : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4302
4303 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4304                                       bit Commutable = 0> {
4305   let isCommutable = Commutable in {
4306     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4307     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4308   }
4309 }
4310
4311 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4312                                       string asmop, bit Commutable = 0> {
4313   let isCommutable = Commutable in {
4314     def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4315     def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4316   }
4317 }
4318
4319 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4320                                         string asmop, bit Commutable = 0> {
4321   let isCommutable = Commutable in {
4322     def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4323     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4324     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4325     def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4326   }
4327 }
4328
4329 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4330                                             Instruction INSTD> {
4331   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4332             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4333 }
4334
4335 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4336                                                Instruction INSTB,
4337                                                Instruction INSTH,
4338                                                Instruction INSTS,
4339                                                Instruction INSTD>
4340   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4341   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4342            (INSTB FPR8:$Rn, FPR8:$Rm)>;
4343   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4344            (INSTH FPR16:$Rn, FPR16:$Rm)>;
4345   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4346            (INSTS FPR32:$Rn, FPR32:$Rm)>;
4347 }
4348
4349 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4350                                              Instruction INSTH,
4351                                              Instruction INSTS> {
4352   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4353             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4354   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4355             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4356 }
4357
4358 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4359                                              ValueType SResTy, ValueType STy,
4360                                              Instruction INSTS, ValueType DResTy,
4361                                              ValueType DTy, Instruction INSTD> {
4362   def : Pat<(SResTy (opnode (STy FPR32:$Rn), (STy FPR32:$Rm))),
4363             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4364   def : Pat<(DResTy (opnode (DTy FPR64:$Rn), (DTy FPR64:$Rm))),
4365             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4366 }
4367
4368 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4369                                               Instruction INSTD>
4370   : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4371         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4372
4373 // Scalar Three Different
4374
4375 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4376                              RegisterClass FPRCD, RegisterClass FPRCS>
4377   : NeonI_Scalar3Diff<u, size, opcode,
4378                       (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4379                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4380                       [],
4381                       NoItinerary>;
4382
4383 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4384   def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4385   def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4386 }
4387
4388 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4389   let Constraints = "$Src = $Rd" in {
4390     def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4391                        (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4392                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4393                        [],
4394                        NoItinerary>;
4395     def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4396                        (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4397                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4398                        [],
4399                        NoItinerary>;
4400   }
4401 }
4402
4403 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4404                                              Instruction INSTH,
4405                                              Instruction INSTS> {
4406   def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4407             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4408   def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4409             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4410 }
4411
4412 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4413                                              Instruction INSTH,
4414                                              Instruction INSTS> {
4415   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4416             (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4417   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4418             (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4419 }
4420
4421 // Scalar Two Registers Miscellaneous
4422
4423 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4424                              RegisterClass FPRCD, RegisterClass FPRCS>
4425   : NeonI_Scalar2SameMisc<u, size, opcode,
4426                           (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4427                           !strconcat(asmop, "\t$Rd, $Rn"),
4428                           [],
4429                           NoItinerary>;
4430
4431 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4432                                          string asmop> {
4433   def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4434                                       FPR32>;
4435   def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4436                                       FPR64>;
4437 }
4438
4439 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4440   def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4441 }
4442
4443 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4444   : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4445   def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4446   def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4447   def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4448 }
4449
4450 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4451   : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4452
4453 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4454                                                  string asmop> {
4455   def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4456   def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4457   def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4458 }
4459
4460 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4461                                        string asmop, RegisterClass FPRC>
4462   : NeonI_Scalar2SameMisc<u, size, opcode,
4463                           (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4464                           !strconcat(asmop, "\t$Rd, $Rn"),
4465                           [],
4466                           NoItinerary>;
4467
4468 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4469                                                  string asmop> {
4470
4471   let Constraints = "$Src = $Rd" in {
4472     def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4473     def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4474     def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4475     def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4476   }
4477 }
4478
4479 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4480                                                   Instruction INSTD>
4481   : Pat<(f32 (opnode (f64 FPR64:$Rn))),
4482         (INSTD FPR64:$Rn)>;
4483
4484 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4485                                                       Instruction INSTS,
4486                                                       Instruction INSTD> {
4487   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn))),
4488             (INSTS FPR32:$Rn)>;
4489   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn))),
4490             (INSTD FPR64:$Rn)>;
4491 }
4492
4493 class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
4494                                                 Instruction INSTD>
4495   : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4496             (INSTD FPR64:$Rn)>;
4497
4498 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
4499                                                      Instruction INSTS,
4500                                                      Instruction INSTD> {
4501   def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
4502             (INSTS FPR32:$Rn)>;
4503   def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
4504             (INSTD FPR64:$Rn)>;
4505 }
4506
4507 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4508                                                  Instruction INSTS,
4509                                                  Instruction INSTD> {
4510   def : Pat<(f32 (opnode (f32 FPR32:$Rn))),
4511             (INSTS FPR32:$Rn)>;
4512   def : Pat<(f64 (opnode (f64 FPR64:$Rn))),
4513             (INSTD FPR64:$Rn)>;
4514 }
4515
4516 class Neon_Scalar2SameMisc_V1_D_size_patterns<SDPatternOperator opnode,
4517                                               Instruction INSTD>
4518   : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4519         (INSTD FPR64:$Rn)>;
4520
4521 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4522   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4523                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4524                           !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4525                           [],
4526                           NoItinerary>;
4527
4528 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4529                                               string asmop> {
4530   def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4531                            (outs FPR32:$Rd), (ins FPR32:$Rn, fpzz32:$FPImm),
4532                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4533                            [],
4534                            NoItinerary>;
4535   def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4536                            (outs FPR64:$Rd), (ins FPR64:$Rn, fpzz32:$FPImm),
4537                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4538                            [],
4539                            NoItinerary>;
4540 }
4541
4542 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4543                                                 Instruction INSTD>
4544   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4545                        (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4546         (INSTD FPR64:$Rn, 0)>;
4547
4548 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4549                                                    Instruction INSTD>
4550   : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4551                           (i32 neon_uimm0:$Imm), CC)),
4552         (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4553
4554 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4555                                                       CondCode CC,
4556                                                       Instruction INSTS,
4557                                                       Instruction INSTD> {
4558   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 fpzz32:$FPImm))),
4559             (INSTS FPR32:$Rn, fpzz32:$FPImm)>;
4560   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f32 fpzz32:$FPImm))),
4561             (INSTD FPR64:$Rn, fpzz32:$FPImm)>;
4562   def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpzz32:$FPImm), CC)),
4563             (INSTD FPR64:$Rn, fpzz32:$FPImm)>;
4564 }
4565
4566 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4567                                                 Instruction INSTD> {
4568   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4569             (INSTD FPR64:$Rn)>;
4570 }
4571
4572 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4573                                                    Instruction INSTB,
4574                                                    Instruction INSTH,
4575                                                    Instruction INSTS,
4576                                                    Instruction INSTD>
4577   : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4578   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4579             (INSTB FPR8:$Rn)>;
4580   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4581             (INSTH FPR16:$Rn)>;
4582   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4583             (INSTS FPR32:$Rn)>;
4584 }
4585
4586 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4587                                                        SDPatternOperator opnode,
4588                                                        Instruction INSTH,
4589                                                        Instruction INSTS,
4590                                                        Instruction INSTD> {
4591   def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4592             (INSTH FPR16:$Rn)>;
4593   def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4594             (INSTS FPR32:$Rn)>;
4595   def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4596             (INSTD FPR64:$Rn)>;
4597
4598 }
4599
4600 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4601                                                        SDPatternOperator opnode,
4602                                                        Instruction INSTB,
4603                                                        Instruction INSTH,
4604                                                        Instruction INSTS,
4605                                                        Instruction INSTD> {
4606   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4607             (INSTB FPR8:$Src, FPR8:$Rn)>;
4608   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4609             (INSTH FPR16:$Src, FPR16:$Rn)>;
4610   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4611             (INSTS FPR32:$Src, FPR32:$Rn)>;
4612   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4613             (INSTD FPR64:$Src, FPR64:$Rn)>;
4614 }
4615
4616 // Scalar Shift By Immediate
4617
4618 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4619                                 RegisterClass FPRC, Operand ImmTy>
4620   : NeonI_ScalarShiftImm<u, opcode,
4621                          (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4622                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4623                          [], NoItinerary>;
4624
4625 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4626                                             string asmop> {
4627   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4628     bits<6> Imm;
4629     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4630     let Inst{21-16} = Imm;
4631   }
4632 }
4633
4634 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4635                                                string asmop>
4636   : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4637   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4638     bits<3> Imm;
4639     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4640     let Inst{18-16} = Imm;
4641   }
4642   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4643     bits<4> Imm;
4644     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4645     let Inst{19-16} = Imm;
4646   }
4647   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4648     bits<5> Imm;
4649     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4650     let Inst{20-16} = Imm;
4651   }
4652 }
4653
4654 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4655                                             string asmop> {
4656   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4657     bits<6> Imm;
4658     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4659     let Inst{21-16} = Imm;
4660   }
4661 }
4662
4663 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4664                                               string asmop>
4665   : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4666   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4667     bits<3> Imm;
4668     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4669     let Inst{18-16} = Imm;
4670   }
4671   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4672     bits<4> Imm;
4673     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4674     let Inst{19-16} = Imm;
4675   }
4676   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4677     bits<5> Imm;
4678     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4679     let Inst{20-16} = Imm;
4680   }
4681 }
4682
4683 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4684   : NeonI_ScalarShiftImm<u, opcode,
4685                          (outs FPR64:$Rd),
4686                          (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4687                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4688                          [], NoItinerary> {
4689     bits<6> Imm;
4690     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4691     let Inst{21-16} = Imm;
4692     let Constraints = "$Src = $Rd";
4693 }
4694
4695 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4696   : NeonI_ScalarShiftImm<u, opcode,
4697                          (outs FPR64:$Rd),
4698                          (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4699                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4700                          [], NoItinerary> {
4701     bits<6> Imm;
4702     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4703     let Inst{21-16} = Imm;
4704     let Constraints = "$Src = $Rd";
4705 }
4706
4707 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4708                                        RegisterClass FPRCD, RegisterClass FPRCS,
4709                                        Operand ImmTy>
4710   : NeonI_ScalarShiftImm<u, opcode,
4711                          (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4712                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4713                          [], NoItinerary>;
4714
4715 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4716                                                 string asmop> {
4717   def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4718                                              shr_imm8> {
4719     bits<3> Imm;
4720     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4721     let Inst{18-16} = Imm;
4722   }
4723   def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4724                                              shr_imm16> {
4725     bits<4> Imm;
4726     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4727     let Inst{19-16} = Imm;
4728   }
4729   def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4730                                              shr_imm32> {
4731     bits<5> Imm;
4732     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4733     let Inst{20-16} = Imm;
4734   }
4735 }
4736
4737 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4738   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4739     bits<5> Imm;
4740     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4741     let Inst{20-16} = Imm;
4742   }
4743   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4744     bits<6> Imm;
4745     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4746     let Inst{21-16} = Imm;
4747   }
4748 }
4749
4750 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4751                                                Instruction INSTD> {
4752   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4753                 (INSTD FPR64:$Rn, imm:$Imm)>;
4754 }
4755
4756 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4757                                                Instruction INSTD> {
4758   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4759                 (INSTD FPR64:$Rn, imm:$Imm)>;
4760 }
4761
4762 class Neon_ScalarShiftLImm_V1_D_size_patterns<SDPatternOperator opnode,
4763                                              Instruction INSTD>
4764   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4765             (v1i64 (Neon_vdup (i32 shl_imm64:$Imm))))),
4766         (INSTD FPR64:$Rn, imm:$Imm)>;
4767
4768 class Neon_ScalarShiftRImm_V1_D_size_patterns<SDPatternOperator opnode,
4769                                              Instruction INSTD>
4770   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4771             (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4772         (INSTD FPR64:$Rn, imm:$Imm)>;
4773
4774 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4775                                                    Instruction INSTB,
4776                                                    Instruction INSTH,
4777                                                    Instruction INSTS,
4778                                                    Instruction INSTD>
4779   : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4780   def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4781                 (INSTB FPR8:$Rn, imm:$Imm)>;
4782   def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4783                 (INSTH FPR16:$Rn, imm:$Imm)>;
4784   def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4785                 (INSTS FPR32:$Rn, imm:$Imm)>;
4786 }
4787
4788 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4789                                                 Instruction INSTD>
4790   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4791             (i32 shl_imm64:$Imm))),
4792         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4793
4794 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4795                                                 Instruction INSTD>
4796   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4797             (i32 shr_imm64:$Imm))),
4798         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4799
4800 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4801                                                        SDPatternOperator opnode,
4802                                                        Instruction INSTH,
4803                                                        Instruction INSTS,
4804                                                        Instruction INSTD> {
4805   def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4806                 (INSTH FPR16:$Rn, imm:$Imm)>;
4807   def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4808                 (INSTS FPR32:$Rn, imm:$Imm)>;
4809   def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4810                 (INSTD FPR64:$Rn, imm:$Imm)>;
4811 }
4812
4813 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
4814                                                       Instruction INSTS,
4815                                                       Instruction INSTD> {
4816   def ssi : Pat<(f32 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4817                 (INSTS FPR32:$Rn, imm:$Imm)>;
4818   def ddi : Pat<(f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4819                 (INSTD FPR64:$Rn, imm:$Imm)>;
4820 }
4821
4822 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
4823                                                       Instruction INSTS,
4824                                                       Instruction INSTD> {
4825   def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4826                 (INSTS FPR32:$Rn, imm:$Imm)>;
4827   def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4828                 (INSTD FPR64:$Rn, imm:$Imm)>;
4829 }
4830
4831 // Scalar Signed Shift Right (Immediate)
4832 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4833 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4834 // Pattern to match llvm.arm.* intrinsic.
4835 def : Neon_ScalarShiftRImm_V1_D_size_patterns<sra, SSHRddi>;
4836
4837 // Scalar Unsigned Shift Right (Immediate)
4838 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4839 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4840 // Pattern to match llvm.arm.* intrinsic.
4841 def : Neon_ScalarShiftRImm_V1_D_size_patterns<srl, USHRddi>;
4842
4843 // Scalar Signed Rounding Shift Right (Immediate)
4844 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4845 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4846
4847 // Scalar Unigned Rounding Shift Right (Immediate)
4848 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4849 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4850
4851 // Scalar Signed Shift Right and Accumulate (Immediate)
4852 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4853 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4854           <int_aarch64_neon_vsrads_n, SSRA>;
4855
4856 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4857 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4858 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4859           <int_aarch64_neon_vsradu_n, USRA>;
4860
4861 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4862 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4863 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4864           <int_aarch64_neon_vrsrads_n, SRSRA>;
4865
4866 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4867 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4868 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4869           <int_aarch64_neon_vrsradu_n, URSRA>;
4870
4871 // Scalar Shift Left (Immediate)
4872 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4873 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4874 // Pattern to match llvm.arm.* intrinsic.
4875 def : Neon_ScalarShiftLImm_V1_D_size_patterns<shl, SHLddi>;
4876
4877 // Signed Saturating Shift Left (Immediate)
4878 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4879 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4880                                                SQSHLbbi, SQSHLhhi,
4881                                                SQSHLssi, SQSHLddi>;
4882 // Pattern to match llvm.arm.* intrinsic.
4883 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4884
4885 // Unsigned Saturating Shift Left (Immediate)
4886 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4887 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4888                                                UQSHLbbi, UQSHLhhi,
4889                                                UQSHLssi, UQSHLddi>;
4890 // Pattern to match llvm.arm.* intrinsic.
4891 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4892
4893 // Signed Saturating Shift Left Unsigned (Immediate)
4894 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4895 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4896                                                SQSHLUbbi, SQSHLUhhi,
4897                                                SQSHLUssi, SQSHLUddi>;
4898
4899 // Shift Right And Insert (Immediate)
4900 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4901 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4902           <int_aarch64_neon_vsri, SRI>;
4903
4904 // Shift Left And Insert (Immediate)
4905 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4906 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4907           <int_aarch64_neon_vsli, SLI>;
4908
4909 // Signed Saturating Shift Right Narrow (Immediate)
4910 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4911 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4912                                                     SQSHRNbhi, SQSHRNhsi,
4913                                                     SQSHRNsdi>;
4914
4915 // Unsigned Saturating Shift Right Narrow (Immediate)
4916 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4917 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4918                                                     UQSHRNbhi, UQSHRNhsi,
4919                                                     UQSHRNsdi>;
4920
4921 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4922 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4923 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4924                                                     SQRSHRNbhi, SQRSHRNhsi,
4925                                                     SQRSHRNsdi>;
4926
4927 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4928 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4929 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4930                                                     UQRSHRNbhi, UQRSHRNhsi,
4931                                                     UQRSHRNsdi>;
4932
4933 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4934 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4935 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4936                                                     SQSHRUNbhi, SQSHRUNhsi,
4937                                                     SQSHRUNsdi>;
4938
4939 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4940 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4941 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4942                                                     SQRSHRUNbhi, SQRSHRUNhsi,
4943                                                     SQRSHRUNsdi>;
4944
4945 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4946 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4947 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxs2fp_n,
4948                                                   SCVTF_Nssi, SCVTF_Nddi>;
4949
4950 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4951 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4952 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxu2fp_n,
4953                                                   UCVTF_Nssi, UCVTF_Nddi>;
4954
4955 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4956 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4957 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxs_n,
4958                                                   FCVTZS_Nssi, FCVTZS_Nddi>;
4959
4960 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4961 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4962 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxu_n,
4963                                                   FCVTZU_Nssi, FCVTZU_Nddi>;
4964
4965 // Patterns For Convert Instructions Between v1f64 and v1i64
4966 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4967                                              Instruction INST>
4968     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4969           (INST FPR64:$Rn, imm:$Imm)>;
4970
4971 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4972                                              Instruction INST>
4973     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4974           (INST FPR64:$Rn, imm:$Imm)>;
4975
4976 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4977                                              SCVTF_Nddi>;
4978
4979 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4980                                              UCVTF_Nddi>;
4981
4982 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4983                                              FCVTZS_Nddi>;
4984
4985 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4986                                              FCVTZU_Nddi>;
4987
4988 // Scalar Integer Add
4989 let isCommutable = 1 in {
4990 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4991 }
4992
4993 // Scalar Integer Sub
4994 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4995
4996 // Pattern for Scalar Integer Add and Sub with D register only
4997 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4998 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4999
5000 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
5001 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
5002 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
5003 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
5004 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
5005
5006 // Scalar Integer Saturating Add (Signed, Unsigned)
5007 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
5008 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
5009
5010 // Scalar Integer Saturating Sub (Signed, Unsigned)
5011 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
5012 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
5013
5014
5015 // Patterns to match llvm.aarch64.* intrinsic for
5016 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
5017 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
5018                                            SQADDhhh, SQADDsss, SQADDddd>;
5019 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
5020                                            UQADDhhh, UQADDsss, UQADDddd>;
5021 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
5022                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
5023 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
5024                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
5025
5026 // Scalar Integer Saturating Doubling Multiply Half High
5027 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
5028
5029 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5030 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
5031
5032 // Patterns to match llvm.arm.* intrinsic for
5033 // Scalar Integer Saturating Doubling Multiply Half High and
5034 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5035 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
5036                                                                SQDMULHsss>;
5037 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
5038                                                                 SQRDMULHsss>;
5039
5040 // Scalar Floating-point Multiply Extended
5041 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
5042
5043 // Scalar Floating-point Reciprocal Step
5044 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
5045 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrecps, f32, f32,
5046                                          FRECPSsss, f64, f64, FRECPSddd>;
5047 def : Pat<(v1f64 (int_arm_neon_vrecps (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5048           (FRECPSddd FPR64:$Rn, FPR64:$Rm)>;
5049
5050 // Scalar Floating-point Reciprocal Square Root Step
5051 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
5052 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrsqrts, f32, f32,
5053                                          FRSQRTSsss, f64, f64, FRSQRTSddd>;
5054 def : Pat<(v1f64 (int_arm_neon_vrsqrts (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5055           (FRSQRTSddd FPR64:$Rn, FPR64:$Rm)>;
5056 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
5057
5058 // Patterns to match llvm.aarch64.* intrinsic for
5059 // Scalar Floating-point Multiply Extended,
5060 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
5061                                                   Instruction INSTS,
5062                                                   Instruction INSTD> {
5063   def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
5064             (INSTS FPR32:$Rn, FPR32:$Rm)>;
5065   def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
5066             (INSTD FPR64:$Rn, FPR64:$Rm)>;
5067 }
5068
5069 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
5070                                               FMULXsss, FMULXddd>;
5071 def : Pat<(v1f64 (int_aarch64_neon_vmulx (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5072           (FMULXddd FPR64:$Rn, FPR64:$Rm)>;
5073
5074 // Scalar Integer Shift Left (Signed, Unsigned)
5075 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
5076 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
5077
5078 // Patterns to match llvm.arm.* intrinsic for
5079 // Scalar Integer Shift Left (Signed, Unsigned)
5080 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
5081 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
5082
5083 // Patterns to match llvm.aarch64.* intrinsic for
5084 // Scalar Integer Shift Left (Signed, Unsigned)
5085 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
5086 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
5087
5088 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
5089 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
5090 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
5091
5092 // Patterns to match llvm.aarch64.* intrinsic for
5093 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
5094 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
5095                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
5096 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
5097                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
5098
5099 // Patterns to match llvm.arm.* intrinsic for
5100 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
5101 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
5102 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
5103
5104 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5105 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
5106 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
5107
5108 // Patterns to match llvm.aarch64.* intrinsic for
5109 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5110 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
5111 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
5112
5113 // Patterns to match llvm.arm.* intrinsic for
5114 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5115 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
5116 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
5117
5118 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5119 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
5120 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
5121
5122 // Patterns to match llvm.aarch64.* intrinsic for
5123 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5124 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
5125                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
5126 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
5127                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
5128
5129 // Patterns to match llvm.arm.* intrinsic for
5130 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5131 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
5132 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
5133
5134 // Signed Saturating Doubling Multiply-Add Long
5135 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
5136 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
5137                                             SQDMLALshh, SQDMLALdss>;
5138
5139 // Signed Saturating Doubling Multiply-Subtract Long
5140 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
5141 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
5142                                             SQDMLSLshh, SQDMLSLdss>;
5143
5144 // Signed Saturating Doubling Multiply Long
5145 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
5146 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
5147                                          SQDMULLshh, SQDMULLdss>;
5148
5149 // Scalar Signed Integer Convert To Floating-point
5150 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
5151 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
5152                                                  SCVTFss, SCVTFdd>;
5153
5154 // Scalar Unsigned Integer Convert To Floating-point
5155 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
5156 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
5157                                                  UCVTFss, UCVTFdd>;
5158
5159 // Scalar Floating-point Converts
5160 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
5161 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
5162                                                   FCVTXN>;
5163
5164 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
5165 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
5166                                                   FCVTNSss, FCVTNSdd>;
5167 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtns, FCVTNSdd>;
5168
5169 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
5170 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
5171                                                   FCVTNUss, FCVTNUdd>;
5172 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtnu, FCVTNUdd>;
5173
5174 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
5175 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
5176                                                   FCVTMSss, FCVTMSdd>;
5177 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtms, FCVTMSdd>;
5178
5179 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
5180 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
5181                                                   FCVTMUss, FCVTMUdd>;
5182 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtmu, FCVTMUdd>;
5183
5184 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
5185 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
5186                                                   FCVTASss, FCVTASdd>;
5187 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtas, FCVTASdd>;
5188
5189 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
5190 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
5191                                                   FCVTAUss, FCVTAUdd>;
5192 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtau, FCVTAUdd>;
5193
5194 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5195 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5196                                                   FCVTPSss, FCVTPSdd>;
5197 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtps, FCVTPSdd>;
5198
5199 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5200 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5201                                                   FCVTPUss, FCVTPUdd>;
5202 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtpu, FCVTPUdd>;
5203
5204 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5205 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5206                                                   FCVTZSss, FCVTZSdd>;
5207 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzs,
5208                                                 FCVTZSdd>;
5209
5210 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5211 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5212                                                   FCVTZUss, FCVTZUdd>;
5213 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzu,
5214                                                 FCVTZUdd>;
5215
5216 // Patterns For Convert Instructions Between v1f64 and v1i64
5217 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5218                                               Instruction INST>
5219     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5220
5221 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5222                                               Instruction INST>
5223     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5224
5225 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5226 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5227
5228 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5229 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5230
5231 // Scalar Floating-point Reciprocal Estimate
5232 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5233 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpe,
5234                                              FRECPEss, FRECPEdd>;
5235 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrecpe,
5236                                               FRECPEdd>;
5237
5238 // Scalar Floating-point Reciprocal Exponent
5239 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5240 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5241                                              FRECPXss, FRECPXdd>;
5242
5243 // Scalar Floating-point Reciprocal Square Root Estimate
5244 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5245 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrsqrte,
5246                                                  FRSQRTEss, FRSQRTEdd>;
5247 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrsqrte,
5248                                               FRSQRTEdd>;
5249
5250 // Scalar Floating-point Round
5251 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5252     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5253
5254 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5255 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5256 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5257 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5258 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5259 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5260 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5261
5262 // Scalar Integer Compare
5263
5264 // Scalar Compare Bitwise Equal
5265 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5266 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5267
5268 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5269                                               Instruction INSTD,
5270                                               CondCode CC>
5271   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5272         (INSTD FPR64:$Rn, FPR64:$Rm)>;
5273
5274 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5275
5276 // Scalar Compare Signed Greather Than Or Equal
5277 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5278 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5279 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5280
5281 // Scalar Compare Unsigned Higher Or Same
5282 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5283 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5284 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5285
5286 // Scalar Compare Unsigned Higher
5287 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5288 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5289 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5290
5291 // Scalar Compare Signed Greater Than
5292 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5293 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5294 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5295
5296 // Scalar Compare Bitwise Test Bits
5297 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5298 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5299 defm : Neon_Scalar3Same_D_size_patterns<Neon_tst, CMTSTddd>;
5300
5301 // Scalar Compare Bitwise Equal To Zero
5302 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5303 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5304                                                 CMEQddi>;
5305 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5306
5307 // Scalar Compare Signed Greather Than Or Equal To Zero
5308 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5309 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5310                                                 CMGEddi>;
5311 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5312
5313 // Scalar Compare Signed Greater Than Zero
5314 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5315 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5316                                                 CMGTddi>;
5317 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5318
5319 // Scalar Compare Signed Less Than Or Equal To Zero
5320 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5321 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5322                                                 CMLEddi>;
5323 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5324
5325 // Scalar Compare Less Than Zero
5326 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5327 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5328                                                 CMLTddi>;
5329 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5330
5331 // Scalar Floating-point Compare
5332
5333 // Scalar Floating-point Compare Mask Equal
5334 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5335 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fceq, v1i32, f32,
5336                                          FCMEQsss, v1i64, f64, FCMEQddd>;
5337 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5338
5339 // Scalar Floating-point Compare Mask Equal To Zero
5340 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5341 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fceq, SETEQ,
5342                                                   FCMEQZssi, FCMEQZddi>;
5343
5344 // Scalar Floating-point Compare Mask Greater Than Or Equal
5345 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5346 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcge, v1i32, f32,
5347                                          FCMGEsss, v1i64, f64, FCMGEddd>;
5348 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5349
5350 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5351 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5352 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcge, SETGE,
5353                                                   FCMGEZssi, FCMGEZddi>;
5354
5355 // Scalar Floating-point Compare Mask Greather Than
5356 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5357 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcgt, v1i32, f32,
5358                                          FCMGTsss, v1i64, f64, FCMGTddd>;
5359 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5360
5361 // Scalar Floating-point Compare Mask Greather Than Zero
5362 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5363 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcgt, SETGT,
5364                                                   FCMGTZssi, FCMGTZddi>;
5365
5366 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5367 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5368 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fclez, SETLE,
5369                                                   FCMLEZssi, FCMLEZddi>;
5370
5371 // Scalar Floating-point Compare Mask Less Than Zero
5372 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5373 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz, SETLT,
5374                                                   FCMLTZssi, FCMLTZddi>;
5375
5376 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5377 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5378 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcage, v1i32, f32,
5379                                          FACGEsss, v1i64, f64, FACGEddd>;
5380 def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5381           (FACGEddd FPR64:$Rn, FPR64:$Rm)>;
5382
5383 // Scalar Floating-point Absolute Compare Mask Greater Than
5384 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5385 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcagt, v1i32, f32,
5386                                          FACGTsss, v1i64, f64, FACGTddd>;
5387 def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5388           (FACGTddd FPR64:$Rn, FPR64:$Rm)>;
5389
5390 // Scalar Floating-point Absolute Difference
5391 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5392 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd, f32, f32,
5393                                          FABDsss, f64, f64, FABDddd>;
5394
5395 // Scalar Absolute Value
5396 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5397 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5398
5399 // Scalar Signed Saturating Absolute Value
5400 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5401 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5402                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
5403
5404 // Scalar Negate
5405 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5406 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5407
5408 // Scalar Signed Saturating Negate
5409 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5410 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5411                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5412
5413 // Scalar Signed Saturating Accumulated of Unsigned Value
5414 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5415 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5416                                                      SUQADDbb, SUQADDhh,
5417                                                      SUQADDss, SUQADDdd>;
5418
5419 // Scalar Unsigned Saturating Accumulated of Signed Value
5420 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5421 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5422                                                      USQADDbb, USQADDhh,
5423                                                      USQADDss, USQADDdd>;
5424
5425 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5426                                           (v1i64 FPR64:$Rn))),
5427           (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5428
5429 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5430                                           (v1i64 FPR64:$Rn))),
5431           (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5432
5433 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5434           (ABSdd FPR64:$Rn)>;
5435
5436 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5437           (SQABSdd FPR64:$Rn)>;
5438
5439 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5440           (SQNEGdd FPR64:$Rn)>;
5441
5442 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5443                       (v1i64 FPR64:$Rn))),
5444           (NEGdd FPR64:$Rn)>;
5445
5446 // Scalar Signed Saturating Extract Unsigned Narrow
5447 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5448 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5449                                                      SQXTUNbh, SQXTUNhs,
5450                                                      SQXTUNsd>;
5451
5452 // Scalar Signed Saturating Extract Narrow
5453 defm SQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5454 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5455                                                      SQXTNbh, SQXTNhs,
5456                                                      SQXTNsd>;
5457
5458 // Scalar Unsigned Saturating Extract Narrow
5459 defm UQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5460 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5461                                                      UQXTNbh, UQXTNhs,
5462                                                      UQXTNsd>;
5463
5464 // Scalar Reduce Pairwise
5465
5466 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5467                                      string asmop, bit Commutable = 0> {
5468   let isCommutable = Commutable in {
5469     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5470                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
5471                                 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5472                                 [],
5473                                 NoItinerary>;
5474   }
5475 }
5476
5477 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5478                                      string asmop, bit Commutable = 0>
5479   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5480   let isCommutable = Commutable in {
5481     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5482                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
5483                                 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5484                                 [],
5485                                 NoItinerary>;
5486   }
5487 }
5488
5489 // Scalar Reduce Addition Pairwise (Integer) with
5490 // Pattern to match llvm.arm.* intrinsic
5491 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5492
5493 // Pattern to match llvm.aarch64.* intrinsic for
5494 // Scalar Reduce Addition Pairwise (Integer)
5495 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5496           (ADDPvv_D_2D VPR128:$Rn)>;
5497 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5498           (ADDPvv_D_2D VPR128:$Rn)>;
5499
5500 // Scalar Reduce Addition Pairwise (Floating Point)
5501 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5502
5503 // Scalar Reduce Maximum Pairwise (Floating Point)
5504 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5505
5506 // Scalar Reduce Minimum Pairwise (Floating Point)
5507 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5508
5509 // Scalar Reduce maxNum Pairwise (Floating Point)
5510 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5511
5512 // Scalar Reduce minNum Pairwise (Floating Point)
5513 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5514
5515 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5516                                             Instruction INSTS,
5517                                             Instruction INSTD> {
5518   def : Pat<(f32 (opnode (v2f32 VPR64:$Rn))),
5519             (INSTS VPR64:$Rn)>;
5520   def : Pat<(f64 (opnode (v2f64 VPR128:$Rn))),
5521             (INSTD VPR128:$Rn)>;
5522 }
5523
5524 // Patterns to match llvm.aarch64.* intrinsic for
5525 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5526 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5527                                         FADDPvv_S_2S, FADDPvv_D_2D>;
5528
5529 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5530                                         FMAXPvv_S_2S, FMAXPvv_D_2D>;
5531
5532 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5533                                         FMINPvv_S_2S, FMINPvv_D_2D>;
5534
5535 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5536                                         FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5537
5538 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5539                                         FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5540
5541 def : Pat<(f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5542           (FADDPvv_S_2S (v2f32
5543                (EXTRACT_SUBREG
5544                    (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5545                    sub_64)))>;
5546
5547 // Scalar by element Arithmetic
5548
5549 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5550                                     string rmlane, bit u, bit szhi, bit szlo,
5551                                     RegisterClass ResFPR, RegisterClass OpFPR,
5552                                     RegisterOperand OpVPR, Operand OpImm>
5553   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5554                              (outs ResFPR:$Rd),
5555                              (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5556                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5557                              [],
5558                              NoItinerary> {
5559   bits<3> Imm;
5560   bits<5> MRm;
5561 }
5562
5563 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5564                                                     string rmlane,
5565                                                     bit u, bit szhi, bit szlo,
5566                                                     RegisterClass ResFPR,
5567                                                     RegisterClass OpFPR,
5568                                                     RegisterOperand OpVPR,
5569                                                     Operand OpImm>
5570   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5571                              (outs ResFPR:$Rd),
5572                              (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5573                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5574                              [],
5575                              NoItinerary> {
5576   let Constraints = "$src = $Rd";
5577   bits<3> Imm;
5578   bits<5> MRm;
5579 }
5580
5581 // Scalar Floating Point  multiply (scalar, by element)
5582 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5583   0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5584   let Inst{11} = Imm{1}; // h
5585   let Inst{21} = Imm{0}; // l
5586   let Inst{20-16} = MRm;
5587 }
5588 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5589   0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5590   let Inst{11} = Imm{0}; // h
5591   let Inst{21} = 0b0;    // l
5592   let Inst{20-16} = MRm;
5593 }
5594
5595 // Scalar Floating Point  multiply extended (scalar, by element)
5596 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5597   0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5598   let Inst{11} = Imm{1}; // h
5599   let Inst{21} = Imm{0}; // l
5600   let Inst{20-16} = MRm;
5601 }
5602 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5603   0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5604   let Inst{11} = Imm{0}; // h
5605   let Inst{21} = 0b0;    // l
5606   let Inst{20-16} = MRm;
5607 }
5608
5609 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5610   SDPatternOperator opnode,
5611   Instruction INST,
5612   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5613   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5614
5615   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5616                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5617              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5618
5619   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5620                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5621              (ResTy (INST (ResTy FPRC:$Rn),
5622                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5623                OpNImm:$Imm))>;
5624
5625   // swapped operands
5626   def  : Pat<(ResTy (opnode
5627                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5628                (ResTy FPRC:$Rn))),
5629              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5630
5631   def  : Pat<(ResTy (opnode
5632                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5633                (ResTy FPRC:$Rn))),
5634              (ResTy (INST (ResTy FPRC:$Rn),
5635                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5636                OpNImm:$Imm))>;
5637 }
5638
5639 // Patterns for Scalar Floating Point  multiply (scalar, by element)
5640 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5641   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5642 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5643   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5644
5645 // Patterns for Scalar Floating Point  multiply extended (scalar, by element)
5646 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5647   FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5648   v2f32, v4f32, neon_uimm1_bare>;
5649 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5650   FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5651   v1f64, v2f64, neon_uimm0_bare>;
5652
5653 // Scalar Floating Point fused multiply-add (scalar, by element)
5654 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5655   0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5656   let Inst{11} = Imm{1}; // h
5657   let Inst{21} = Imm{0}; // l
5658   let Inst{20-16} = MRm;
5659 }
5660 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5661   0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5662   let Inst{11} = Imm{0}; // h
5663   let Inst{21} = 0b0;    // l
5664   let Inst{20-16} = MRm;
5665 }
5666
5667 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5668 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5669   0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5670   let Inst{11} = Imm{1}; // h
5671   let Inst{21} = Imm{0}; // l
5672   let Inst{20-16} = MRm;
5673 }
5674 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5675   0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5676   let Inst{11} = Imm{0}; // h
5677   let Inst{21} = 0b0;    // l
5678   let Inst{20-16} = MRm;
5679 }
5680 // We are allowed to match the fma instruction regardless of compile options.
5681 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5682   Instruction FMLAI, Instruction FMLSI,
5683   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5684   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5685   // fmla
5686   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5687                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5688                (ResTy FPRC:$Ra))),
5689              (ResTy (FMLAI (ResTy FPRC:$Ra),
5690                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5691
5692   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5693                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5694                (ResTy FPRC:$Ra))),
5695              (ResTy (FMLAI (ResTy FPRC:$Ra),
5696                (ResTy FPRC:$Rn),
5697                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5698                OpNImm:$Imm))>;
5699
5700   // swapped fmla operands
5701   def  : Pat<(ResTy (fma
5702                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5703                (ResTy FPRC:$Rn),
5704                (ResTy FPRC:$Ra))),
5705              (ResTy (FMLAI (ResTy FPRC:$Ra),
5706                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5707
5708   def  : Pat<(ResTy (fma
5709                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5710                (ResTy FPRC:$Rn),
5711                (ResTy FPRC:$Ra))),
5712              (ResTy (FMLAI (ResTy FPRC:$Ra),
5713                (ResTy FPRC:$Rn),
5714                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5715                OpNImm:$Imm))>;
5716
5717   // fmls
5718   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5719                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5720                (ResTy FPRC:$Ra))),
5721              (ResTy (FMLSI (ResTy FPRC:$Ra),
5722                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5723
5724   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5725                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5726                (ResTy FPRC:$Ra))),
5727              (ResTy (FMLSI (ResTy FPRC:$Ra),
5728                (ResTy FPRC:$Rn),
5729                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5730                OpNImm:$Imm))>;
5731
5732   // swapped fmls operands
5733   def  : Pat<(ResTy (fma
5734                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5735                (ResTy FPRC:$Rn),
5736                (ResTy FPRC:$Ra))),
5737              (ResTy (FMLSI (ResTy FPRC:$Ra),
5738                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5739
5740   def  : Pat<(ResTy (fma
5741                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5742                (ResTy FPRC:$Rn),
5743                (ResTy FPRC:$Ra))),
5744              (ResTy (FMLSI (ResTy FPRC:$Ra),
5745                (ResTy FPRC:$Rn),
5746                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5747                OpNImm:$Imm))>;
5748 }
5749
5750 // Scalar Floating Point fused multiply-add and
5751 // multiply-subtract (scalar, by element)
5752 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5753   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5754 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5755   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5756 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5757   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5758
5759 // Scalar Signed saturating doubling multiply long (scalar, by element)
5760 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5761   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5762   let Inst{11} = 0b0; // h
5763   let Inst{21} = Imm{1}; // l
5764   let Inst{20} = Imm{0}; // m
5765   let Inst{19-16} = MRm{3-0};
5766 }
5767 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5768   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5769   let Inst{11} = Imm{2}; // h
5770   let Inst{21} = Imm{1}; // l
5771   let Inst{20} = Imm{0}; // m
5772   let Inst{19-16} = MRm{3-0};
5773 }
5774 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5775   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5776   let Inst{11} = 0b0;    // h
5777   let Inst{21} = Imm{0}; // l
5778   let Inst{20-16} = MRm;
5779 }
5780 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5781   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5782   let Inst{11} = Imm{1};    // h
5783   let Inst{21} = Imm{0};    // l
5784   let Inst{20-16} = MRm;
5785 }
5786
5787 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5788   SDPatternOperator opnode,
5789   Instruction INST,
5790   ValueType ResTy, RegisterClass FPRC,
5791   ValueType OpVTy, ValueType OpTy,
5792   ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5793
5794   def  : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5795                (OpVTy (scalar_to_vector
5796                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5797              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5798
5799   //swapped operands
5800   def  : Pat<(ResTy (opnode
5801                (OpVTy (scalar_to_vector
5802                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5803                  (OpVTy FPRC:$Rn))),
5804              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5805 }
5806
5807
5808 // Patterns for Scalar Signed saturating doubling
5809 // multiply long (scalar, by element)
5810 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5811   SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5812   i32, VPR64Lo, neon_uimm2_bare>;
5813 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5814   SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5815   i32, VPR128Lo, neon_uimm3_bare>;
5816 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5817   SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5818   i32, VPR64Lo, neon_uimm1_bare>;
5819 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5820   SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5821   i32, VPR128Lo, neon_uimm2_bare>;
5822
5823 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5824 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5825   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5826   let Inst{11} = 0b0; // h
5827   let Inst{21} = Imm{1}; // l
5828   let Inst{20} = Imm{0}; // m
5829   let Inst{19-16} = MRm{3-0};
5830 }
5831 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5832   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5833   let Inst{11} = Imm{2}; // h
5834   let Inst{21} = Imm{1}; // l
5835   let Inst{20} = Imm{0}; // m
5836   let Inst{19-16} = MRm{3-0};
5837 }
5838 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5839   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5840   let Inst{11} = 0b0;    // h
5841   let Inst{21} = Imm{0}; // l
5842   let Inst{20-16} = MRm;
5843 }
5844 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5845   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5846   let Inst{11} = Imm{1};    // h
5847   let Inst{21} = Imm{0};    // l
5848   let Inst{20-16} = MRm;
5849 }
5850
5851 // Scalar Signed saturating doubling
5852 // multiply-subtract long (scalar, by element)
5853 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5854   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5855   let Inst{11} = 0b0; // h
5856   let Inst{21} = Imm{1}; // l
5857   let Inst{20} = Imm{0}; // m
5858   let Inst{19-16} = MRm{3-0};
5859 }
5860 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5861   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5862   let Inst{11} = Imm{2}; // h
5863   let Inst{21} = Imm{1}; // l
5864   let Inst{20} = Imm{0}; // m
5865   let Inst{19-16} = MRm{3-0};
5866 }
5867 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5868   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5869   let Inst{11} = 0b0;    // h
5870   let Inst{21} = Imm{0}; // l
5871   let Inst{20-16} = MRm;
5872 }
5873 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5874   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5875   let Inst{11} = Imm{1};    // h
5876   let Inst{21} = Imm{0};    // l
5877   let Inst{20-16} = MRm;
5878 }
5879
5880 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5881   SDPatternOperator opnode,
5882   SDPatternOperator coreopnode,
5883   Instruction INST,
5884   ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5885   ValueType OpTy,
5886   ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5887
5888   def  : Pat<(ResTy (opnode
5889                (ResTy ResFPRC:$Ra),
5890                (ResTy (coreopnode (OpTy FPRC:$Rn),
5891                  (OpTy (scalar_to_vector
5892                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5893              (ResTy (INST (ResTy ResFPRC:$Ra),
5894                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5895
5896   // swapped operands
5897   def  : Pat<(ResTy (opnode
5898                (ResTy ResFPRC:$Ra),
5899                (ResTy (coreopnode
5900                  (OpTy (scalar_to_vector
5901                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5902                  (OpTy FPRC:$Rn))))),
5903              (ResTy (INST (ResTy ResFPRC:$Ra),
5904                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5905 }
5906
5907 // Patterns for Scalar Signed saturating
5908 // doubling multiply-add long (scalar, by element)
5909 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5910   int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5911   i32, VPR64Lo, neon_uimm2_bare>;
5912 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5913   int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5914   i32, VPR128Lo, neon_uimm3_bare>;
5915 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5916   int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5917   i32, VPR64Lo, neon_uimm1_bare>;
5918 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5919   int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5920   i32, VPR128Lo, neon_uimm2_bare>;
5921
5922 // Patterns for Scalar Signed saturating
5923 // doubling multiply-sub long (scalar, by element)
5924 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5925   int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5926   i32, VPR64Lo, neon_uimm2_bare>;
5927 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5928   int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5929   i32, VPR128Lo, neon_uimm3_bare>;
5930 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5931   int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5932   i32, VPR64Lo, neon_uimm1_bare>;
5933 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5934   int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5935   i32, VPR128Lo, neon_uimm2_bare>;
5936
5937 // Scalar Signed saturating doubling multiply returning
5938 // high half (scalar, by element)
5939 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5940   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5941   let Inst{11} = 0b0; // h
5942   let Inst{21} = Imm{1}; // l
5943   let Inst{20} = Imm{0}; // m
5944   let Inst{19-16} = MRm{3-0};
5945 }
5946 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5947   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5948   let Inst{11} = Imm{2}; // h
5949   let Inst{21} = Imm{1}; // l
5950   let Inst{20} = Imm{0}; // m
5951   let Inst{19-16} = MRm{3-0};
5952 }
5953 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5954   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5955   let Inst{11} = 0b0;    // h
5956   let Inst{21} = Imm{0}; // l
5957   let Inst{20-16} = MRm;
5958 }
5959 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5960   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5961   let Inst{11} = Imm{1};    // h
5962   let Inst{21} = Imm{0};    // l
5963   let Inst{20-16} = MRm;
5964 }
5965
5966 // Patterns for Scalar Signed saturating doubling multiply returning
5967 // high half (scalar, by element)
5968 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5969   SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5970   i32, VPR64Lo, neon_uimm2_bare>;
5971 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5972   SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5973   i32, VPR128Lo, neon_uimm3_bare>;
5974 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5975   SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5976   i32, VPR64Lo, neon_uimm1_bare>;
5977 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5978   SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5979   i32, VPR128Lo, neon_uimm2_bare>;
5980
5981 // Scalar Signed saturating rounding doubling multiply
5982 // returning high half (scalar, by element)
5983 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5984   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5985   let Inst{11} = 0b0; // h
5986   let Inst{21} = Imm{1}; // l
5987   let Inst{20} = Imm{0}; // m
5988   let Inst{19-16} = MRm{3-0};
5989 }
5990 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5991   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5992   let Inst{11} = Imm{2}; // h
5993   let Inst{21} = Imm{1}; // l
5994   let Inst{20} = Imm{0}; // m
5995   let Inst{19-16} = MRm{3-0};
5996 }
5997 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5998   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5999   let Inst{11} = 0b0;    // h
6000   let Inst{21} = Imm{0}; // l
6001   let Inst{20-16} = MRm;
6002 }
6003 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
6004   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
6005   let Inst{11} = Imm{1};    // h
6006   let Inst{21} = Imm{0};    // l
6007   let Inst{20-16} = MRm;
6008 }
6009
6010 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6011   SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
6012   VPR64Lo, neon_uimm2_bare>;
6013 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6014   SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
6015   VPR128Lo, neon_uimm3_bare>;
6016 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6017   SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
6018   VPR64Lo, neon_uimm1_bare>;
6019 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6020   SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
6021   VPR128Lo, neon_uimm2_bare>;
6022
6023 // Scalar general arithmetic operation
6024 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
6025                                         Instruction INST>
6026     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
6027
6028 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
6029                                         Instruction INST>
6030     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
6031           (INST FPR64:$Rn, FPR64:$Rm)>;
6032
6033 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
6034                                         Instruction INST>
6035     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
6036               (v1f64 FPR64:$Ra))),
6037           (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
6038
6039 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
6040 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
6041 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
6042 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
6043 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
6044 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
6045 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
6046 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
6047 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
6048
6049 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
6050 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
6051
6052 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
6053 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
6054
6055 // Scalar Copy - DUP element to scalar
6056 class NeonI_Scalar_DUP<string asmop, string asmlane,
6057                        RegisterClass ResRC, RegisterOperand VPRC,
6058                        Operand OpImm>
6059   : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
6060                      asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
6061                      [],
6062                      NoItinerary> {
6063   bits<4> Imm;
6064 }
6065
6066 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
6067   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6068 }
6069 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
6070   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6071 }
6072 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
6073   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6074 }
6075 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
6076   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6077 }
6078
6079 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 0)),
6080           (f32 (EXTRACT_SUBREG (v4f32 VPR128:$Rn), sub_32))>;
6081 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 1)),
6082           (f32 (DUPsv_S (v4f32 VPR128:$Rn), 1))>;
6083 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 2)),
6084           (f32 (DUPsv_S (v4f32 VPR128:$Rn), 2))>;
6085 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 3)),
6086           (f32 (DUPsv_S (v4f32 VPR128:$Rn), 3))>;
6087
6088 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 0)),
6089           (f64 (EXTRACT_SUBREG (v2f64 VPR128:$Rn), sub_64))>;
6090 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 1)),
6091           (f64 (DUPdv_D (v2f64 VPR128:$Rn), 1))>;
6092
6093 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 0)),
6094           (f32 (EXTRACT_SUBREG (v2f32 VPR64:$Rn), sub_32))>;
6095 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 1)),
6096           (f32 (DUPsv_S (v4f32 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6097             1))>;
6098
6099 def : Pat<(f64 (vector_extract (v1f64 VPR64:$Rn), 0)),
6100           (f64 (EXTRACT_SUBREG (v1f64 VPR64:$Rn), sub_64))>;
6101
6102 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
6103   ValueType ResTy, ValueType OpTy,Operand OpLImm,
6104   ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
6105
6106   def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
6107             (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
6108
6109   def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
6110             (ResTy (DUPI
6111               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6112                 OpNImm:$Imm))>;
6113 }
6114
6115 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
6116 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
6117                                         v8i8, v16i8, neon_uimm3_bare>;
6118 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
6119                                         v4i16, v8i16, neon_uimm2_bare>;
6120 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
6121                                         v2i32, v4i32, neon_uimm1_bare>;
6122
6123 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
6124                                           ValueType OpTy, ValueType ElemTy,
6125                                           Operand OpImm, ValueType OpNTy,
6126                                           ValueType ExTy, Operand OpNImm> {
6127
6128   def : Pat<(ResTy (vector_insert (ResTy undef),
6129               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
6130               (neon_uimm0_bare:$Imm))),
6131             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6132
6133   def : Pat<(ResTy (vector_insert (ResTy undef),
6134               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
6135               (OpNImm:$Imm))),
6136             (ResTy (DUPI
6137               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6138               OpNImm:$Imm))>;
6139 }
6140
6141 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
6142                                           ValueType OpTy, ValueType ElemTy,
6143                                           Operand OpImm, ValueType OpNTy,
6144                                           ValueType ExTy, Operand OpNImm> {
6145
6146   def : Pat<(ResTy (scalar_to_vector
6147               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
6148             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6149
6150   def : Pat<(ResTy (scalar_to_vector
6151               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
6152             (ResTy (DUPI
6153               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6154               OpNImm:$Imm))>;
6155 }
6156
6157 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
6158 // instructions.
6159 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
6160   v1i64, v2i64, i64, neon_uimm1_bare,
6161   v1i64, v2i64, neon_uimm0_bare>;
6162 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
6163   v1i32, v4i32, i32, neon_uimm2_bare,
6164   v2i32, v4i32, neon_uimm1_bare>;
6165 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
6166   v1i16, v8i16, i32, neon_uimm3_bare,
6167   v4i16, v8i16, neon_uimm2_bare>;
6168 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
6169   v1i8, v16i8, i32, neon_uimm4_bare,
6170   v8i8, v16i8, neon_uimm3_bare>;
6171 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
6172   v1i64, v2i64, i64, neon_uimm1_bare,
6173   v1i64, v2i64, neon_uimm0_bare>;
6174 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
6175   v1i32, v4i32, i32, neon_uimm2_bare,
6176   v2i32, v4i32, neon_uimm1_bare>;
6177 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
6178   v1i16, v8i16, i32, neon_uimm3_bare,
6179   v4i16, v8i16, neon_uimm2_bare>;
6180 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
6181   v1i8, v16i8, i32, neon_uimm4_bare,
6182   v8i8, v16i8, neon_uimm3_bare>;
6183
6184 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
6185                                   Instruction DUPI, Operand OpImm,
6186                                   RegisterClass ResRC> {
6187   def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
6188           (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
6189 }
6190
6191 // Aliases for Scalar copy - DUP element (scalar)
6192 // FIXME: This is actually the preferred syntax but TableGen can't deal with
6193 // custom printing of aliases.
6194 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
6195 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
6196 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6197 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6198
6199 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6200                       ValueType OpTy> {
6201   def : Pat<(ResTy (GetLow VPR128:$Rn)),
6202             (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6203   def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6204             (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6205 }
6206
6207 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6208 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6209 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6210 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6211 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6212 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6213
6214 //===----------------------------------------------------------------------===//
6215 // Non-Instruction Patterns
6216 //===----------------------------------------------------------------------===//
6217
6218 // 64-bit vector bitcasts...
6219
6220 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
6221 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
6222 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
6223 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
6224
6225 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
6226 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
6227 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
6228 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
6229
6230 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
6231 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
6232 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
6233 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
6234
6235 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
6236 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
6237 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
6238 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
6239
6240 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
6241 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6242 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6243 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6244
6245 def : Pat<(v1i64 (bitconvert (v1f64  VPR64:$src))), (v1i64 VPR64:$src)>;
6246 def : Pat<(v2f32 (bitconvert (v1f64  VPR64:$src))), (v2f32 VPR64:$src)>;
6247 def : Pat<(v2i32 (bitconvert (v1f64  VPR64:$src))), (v2i32 VPR64:$src)>;
6248 def : Pat<(v4i16 (bitconvert (v1f64  VPR64:$src))), (v4i16 VPR64:$src)>;
6249 def : Pat<(v8i8 (bitconvert (v1f64  VPR64:$src))), (v8i8 VPR64:$src)>;
6250 def : Pat<(f64   (bitconvert (v1f64  VPR64:$src))), (f64 VPR64:$src)>;
6251
6252 def : Pat<(v1f64 (bitconvert (v1i64  VPR64:$src))), (v1f64 VPR64:$src)>;
6253 def : Pat<(v1f64 (bitconvert (v2f32  VPR64:$src))), (v1f64 VPR64:$src)>;
6254 def : Pat<(v1f64 (bitconvert (v2i32  VPR64:$src))), (v1f64 VPR64:$src)>;
6255 def : Pat<(v1f64 (bitconvert (v4i16  VPR64:$src))), (v1f64 VPR64:$src)>;
6256 def : Pat<(v1f64 (bitconvert (v8i8  VPR64:$src))), (v1f64 VPR64:$src)>;
6257 def : Pat<(v1f64 (bitconvert (f64  VPR64:$src))), (v1f64 VPR64:$src)>;
6258
6259 // ..and 128-bit vector bitcasts...
6260
6261 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
6262 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
6263 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
6264 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
6265 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
6266
6267 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
6268 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
6269 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
6270 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
6271 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
6272
6273 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
6274 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
6275 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
6276 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
6277 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
6278
6279 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
6280 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
6281 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
6282 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
6283 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
6284
6285 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
6286 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
6287 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
6288 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
6289 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
6290
6291 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
6292 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
6293 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
6294 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
6295 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
6296
6297 // ...and scalar bitcasts...
6298 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
6299 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
6300 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
6301 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
6302
6303 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
6304 def : Pat<(i64 (bitconvert (v1f64  FPR64:$src))), (FMOVxd $src)>;
6305 def : Pat<(i64 (bitconvert (v2i32  FPR64:$src))), (FMOVxd $src)>;
6306 def : Pat<(i64 (bitconvert (v2f32  FPR64:$src))), (FMOVxd $src)>;
6307 def : Pat<(i64 (bitconvert (v4i16  FPR64:$src))), (FMOVxd $src)>;
6308 def : Pat<(i64 (bitconvert (v8i8  FPR64:$src))), (FMOVxd $src)>;
6309
6310 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
6311
6312 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6313 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6314 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6315
6316 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
6317 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
6318 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
6319 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
6320 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
6321
6322 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
6323 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
6324 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
6325 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
6326 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
6327 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
6328
6329 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
6330 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
6331 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
6332 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
6333
6334 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6335 def : Pat<(v1f64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6336 def : Pat<(v2i32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6337 def : Pat<(v2f32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6338 def : Pat<(v4i16 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6339 def : Pat<(v8i8 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6340
6341 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
6342
6343 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
6344 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
6345 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
6346 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
6347 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
6348
6349 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
6350 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
6351 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
6352 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
6353 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
6354 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
6355
6356 // Scalar Three Same
6357
6358 def neon_uimm3 : Operand<i64>,
6359                    ImmLeaf<i64, [{return Imm < 8;}]> {
6360   let ParserMatchClass = uimm3_asmoperand;
6361   let PrintMethod = "printUImmHexOperand";
6362 }
6363
6364 def neon_uimm4 : Operand<i64>,
6365                    ImmLeaf<i64, [{return Imm < 16;}]> {
6366   let ParserMatchClass = uimm4_asmoperand;
6367   let PrintMethod = "printUImmHexOperand";
6368 }
6369
6370 // Bitwise Extract
6371 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6372                     string OpS, RegisterOperand OpVPR, Operand OpImm>
6373   : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6374                      (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6375                      asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6376                      ", $Rm." # OpS # ", $Index",
6377                      [],
6378                      NoItinerary>{
6379   bits<4> Index;
6380 }
6381
6382 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6383                                VPR64, neon_uimm3> {
6384   let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6385 }
6386
6387 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6388                                VPR128, neon_uimm4> {
6389   let Inst{14-11} = Index;
6390 }
6391
6392 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6393                  Operand OpImm>
6394   : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6395                                  (i64 OpImm:$Imm))),
6396               (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6397
6398 def : NI_Extract<v8i8,  VPR64,  EXTvvvi_8b,  neon_uimm3>;
6399 def : NI_Extract<v4i16, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6400 def : NI_Extract<v2i32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6401 def : NI_Extract<v1i64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6402 def : NI_Extract<v2f32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6403 def : NI_Extract<v1f64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6404 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6405 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6406 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6407 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6408 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6409 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6410
6411 // Table lookup
6412 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6413              string asmop, string OpS, RegisterOperand OpVPR,
6414              RegisterOperand VecList>
6415   : NeonI_TBL<q, op2, len, op,
6416               (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6417               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6418               [],
6419               NoItinerary>;
6420
6421 // The vectors in look up table are always 16b
6422 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6423   def _8b  : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6424                     !cast<RegisterOperand>(List # "16B_operand")>;
6425
6426   def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6427                     !cast<RegisterOperand>(List # "16B_operand")>;
6428 }
6429
6430 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6431 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6432 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6433 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6434
6435 // Table lookup extension
6436 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6437              string asmop, string OpS, RegisterOperand OpVPR,
6438              RegisterOperand VecList>
6439   : NeonI_TBL<q, op2, len, op,
6440               (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6441               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6442               [],
6443               NoItinerary> {
6444   let Constraints = "$src = $Rd";
6445 }
6446
6447 // The vectors in look up table are always 16b
6448 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6449   def _8b  : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6450                     !cast<RegisterOperand>(List # "16B_operand")>;
6451
6452   def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6453                     !cast<RegisterOperand>(List # "16B_operand")>;
6454 }
6455
6456 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6457 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6458 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6459 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6460
6461 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6462                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6463   : NeonI_copy<0b1, 0b0, 0b0011,
6464                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6465                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6466                [(set (ResTy VPR128:$Rd),
6467                  (ResTy (vector_insert
6468                    (ResTy VPR128:$src),
6469                    (OpTy OpGPR:$Rn),
6470                    (OpImm:$Imm))))],
6471                NoItinerary> {
6472   bits<4> Imm;
6473   let Constraints = "$src = $Rd";
6474 }
6475
6476 //Insert element (vector, from main)
6477 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6478                            neon_uimm4_bare> {
6479   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6480 }
6481 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6482                            neon_uimm3_bare> {
6483   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6484 }
6485 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6486                            neon_uimm2_bare> {
6487   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6488 }
6489 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6490                            neon_uimm1_bare> {
6491   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6492 }
6493
6494 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6495                     (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6496 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6497                     (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6498 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6499                     (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6500 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6501                     (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6502
6503 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6504                              RegisterClass OpGPR, ValueType OpTy,
6505                              Operand OpImm, Instruction INS>
6506   : Pat<(ResTy (vector_insert
6507               (ResTy VPR64:$src),
6508               (OpTy OpGPR:$Rn),
6509               (OpImm:$Imm))),
6510         (ResTy (EXTRACT_SUBREG
6511           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6512             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6513
6514 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6515                                           neon_uimm3_bare, INSbw>;
6516 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6517                                           neon_uimm2_bare, INShw>;
6518 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6519                                           neon_uimm1_bare, INSsw>;
6520 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6521                                           neon_uimm0_bare, INSdx>;
6522
6523 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6524   : NeonI_insert<0b1, 0b1,
6525                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6526                  ResImm:$Immd, ResImm:$Immn),
6527                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6528                  [],
6529                  NoItinerary> {
6530   let Constraints = "$src = $Rd";
6531   bits<4> Immd;
6532   bits<4> Immn;
6533 }
6534
6535 //Insert element (vector, from element)
6536 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6537   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6538   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6539 }
6540 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6541   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6542   let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6543   // bit 11 is unspecified, but should be set to zero.
6544 }
6545 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6546   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6547   let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6548   // bits 11-12 are unspecified, but should be set to zero.
6549 }
6550 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6551   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6552   let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6553   // bits 11-13 are unspecified, but should be set to zero.
6554 }
6555
6556 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6557                     (INSELb VPR128:$Rd, VPR128:$Rn,
6558                       neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6559 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6560                     (INSELh VPR128:$Rd, VPR128:$Rn,
6561                       neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6562 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6563                     (INSELs VPR128:$Rd, VPR128:$Rn,
6564                       neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6565 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6566                     (INSELd VPR128:$Rd, VPR128:$Rn,
6567                       neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6568
6569 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6570                                 ValueType MidTy, Operand StImm, Operand NaImm,
6571                                 Instruction INS> {
6572 def : Pat<(ResTy (vector_insert
6573             (ResTy VPR128:$src),
6574             (MidTy (vector_extract
6575               (ResTy VPR128:$Rn),
6576               (StImm:$Immn))),
6577             (StImm:$Immd))),
6578           (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6579               StImm:$Immd, StImm:$Immn)>;
6580
6581 def : Pat <(ResTy (vector_insert
6582              (ResTy VPR128:$src),
6583              (MidTy (vector_extract
6584                (NaTy VPR64:$Rn),
6585                (NaImm:$Immn))),
6586              (StImm:$Immd))),
6587            (INS (ResTy VPR128:$src),
6588              (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6589              StImm:$Immd, NaImm:$Immn)>;
6590
6591 def : Pat <(NaTy (vector_insert
6592              (NaTy VPR64:$src),
6593              (MidTy (vector_extract
6594                (ResTy VPR128:$Rn),
6595                (StImm:$Immn))),
6596              (NaImm:$Immd))),
6597            (NaTy (EXTRACT_SUBREG
6598              (ResTy (INS
6599                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6600                (ResTy VPR128:$Rn),
6601                NaImm:$Immd, StImm:$Immn)),
6602              sub_64))>;
6603
6604 def : Pat <(NaTy (vector_insert
6605              (NaTy VPR64:$src),
6606              (MidTy (vector_extract
6607                (NaTy VPR64:$Rn),
6608                (NaImm:$Immn))),
6609              (NaImm:$Immd))),
6610            (NaTy (EXTRACT_SUBREG
6611              (ResTy (INS
6612                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6613                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6614                NaImm:$Immd, NaImm:$Immn)),
6615              sub_64))>;
6616 }
6617
6618 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6619                             neon_uimm1_bare, INSELs>;
6620 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6621                             neon_uimm0_bare, INSELd>;
6622 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6623                             neon_uimm3_bare, INSELb>;
6624 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6625                             neon_uimm2_bare, INSELh>;
6626 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6627                             neon_uimm1_bare, INSELs>;
6628 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6629                             neon_uimm0_bare, INSELd>;
6630
6631 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6632                                       ValueType MidTy,
6633                                       RegisterClass OpFPR, Operand ResImm,
6634                                       SubRegIndex SubIndex, Instruction INS> {
6635 def : Pat <(ResTy (vector_insert
6636              (ResTy VPR128:$src),
6637              (MidTy OpFPR:$Rn),
6638              (ResImm:$Imm))),
6639            (INS (ResTy VPR128:$src),
6640              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6641              ResImm:$Imm,
6642              (i64 0))>;
6643
6644 def : Pat <(NaTy (vector_insert
6645              (NaTy VPR64:$src),
6646              (MidTy OpFPR:$Rn),
6647              (ResImm:$Imm))),
6648            (NaTy (EXTRACT_SUBREG
6649              (ResTy (INS
6650                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6651                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6652                ResImm:$Imm,
6653                (i64 0))),
6654              sub_64))>;
6655 }
6656
6657 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6658                                   sub_32, INSELs>;
6659 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6660                                   sub_64, INSELd>;
6661
6662 class NeonI_SMOV<string asmop, string Res, bit Q,
6663                  ValueType OpTy, ValueType eleTy,
6664                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6665   : NeonI_copy<Q, 0b0, 0b0101,
6666                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6667                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6668                [(set (ResTy ResGPR:$Rd),
6669                  (ResTy (sext_inreg
6670                    (ResTy (vector_extract
6671                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
6672                    eleTy)))],
6673                NoItinerary> {
6674   bits<4> Imm;
6675 }
6676
6677 //Signed integer move (main, from element)
6678 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6679                         GPR32, i32> {
6680   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6681 }
6682 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6683                         GPR32, i32> {
6684   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6685 }
6686 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6687                         GPR64, i64> {
6688   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6689 }
6690 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6691                         GPR64, i64> {
6692   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6693 }
6694 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6695                         GPR64, i64> {
6696   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6697 }
6698
6699 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6700                                ValueType eleTy, Operand StImm,  Operand NaImm,
6701                                Instruction SMOVI> {
6702   def : Pat<(i64 (sext_inreg
6703               (i64 (anyext
6704                 (i32 (vector_extract
6705                   (StTy VPR128:$Rn), (StImm:$Imm))))),
6706               eleTy)),
6707             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6708
6709   def : Pat<(i64 (sext
6710               (i32 (vector_extract
6711                 (StTy VPR128:$Rn), (StImm:$Imm))))),
6712             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6713
6714   def : Pat<(i64 (sext_inreg
6715               (i64 (vector_extract
6716                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6717               eleTy)),
6718             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6719               NaImm:$Imm)>;
6720
6721   def : Pat<(i64 (sext_inreg
6722               (i64 (anyext
6723                 (i32 (vector_extract
6724                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6725               eleTy)),
6726             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6727               NaImm:$Imm)>;
6728
6729   def : Pat<(i64 (sext
6730               (i32 (vector_extract
6731                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6732             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6733               NaImm:$Imm)>;
6734 }
6735
6736 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6737                           neon_uimm3_bare, SMOVxb>;
6738 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6739                           neon_uimm2_bare, SMOVxh>;
6740 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6741                           neon_uimm1_bare, SMOVxs>;
6742
6743 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6744                           ValueType eleTy, Operand StImm,  Operand NaImm,
6745                           Instruction SMOVI>
6746   : Pat<(i32 (sext_inreg
6747           (i32 (vector_extract
6748             (NaTy VPR64:$Rn), (NaImm:$Imm))),
6749           eleTy)),
6750         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6751           NaImm:$Imm)>;
6752
6753 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6754                          neon_uimm3_bare, SMOVwb>;
6755 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6756                          neon_uimm2_bare, SMOVwh>;
6757
6758 class NeonI_UMOV<string asmop, string Res, bit Q,
6759                  ValueType OpTy, Operand OpImm,
6760                  RegisterClass ResGPR, ValueType ResTy>
6761   : NeonI_copy<Q, 0b0, 0b0111,
6762                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6763                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6764                [(set (ResTy ResGPR:$Rd),
6765                   (ResTy (vector_extract
6766                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6767                NoItinerary> {
6768   bits<4> Imm;
6769 }
6770
6771 //Unsigned integer move (main, from element)
6772 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6773                          GPR32, i32> {
6774   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6775 }
6776 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6777                          GPR32, i32> {
6778   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6779 }
6780 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6781                          GPR32, i32> {
6782   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6783 }
6784 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6785                          GPR64, i64> {
6786   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6787 }
6788
6789 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6790                     (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6791 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6792                     (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6793
6794 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6795                          Operand StImm,  Operand NaImm,
6796                          Instruction SMOVI>
6797   : Pat<(ResTy (vector_extract
6798           (NaTy VPR64:$Rn), NaImm:$Imm)),
6799         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6800           NaImm:$Imm)>;
6801
6802 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6803                         neon_uimm3_bare, UMOVwb>;
6804 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6805                         neon_uimm2_bare, UMOVwh>;
6806 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6807                         neon_uimm1_bare, UMOVws>;
6808
6809 def : Pat<(i32 (and
6810             (i32 (vector_extract
6811               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6812             255)),
6813           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6814
6815 def : Pat<(i32 (and
6816             (i32 (vector_extract
6817               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6818             65535)),
6819           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6820
6821 def : Pat<(i64 (zext
6822             (i32 (vector_extract
6823               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6824           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6825
6826 def : Pat<(i32 (and
6827             (i32 (vector_extract
6828               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6829             255)),
6830           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6831             neon_uimm3_bare:$Imm)>;
6832
6833 def : Pat<(i32 (and
6834             (i32 (vector_extract
6835               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6836             65535)),
6837           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6838             neon_uimm2_bare:$Imm)>;
6839
6840 def : Pat<(i64 (zext
6841             (i32 (vector_extract
6842               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6843           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6844             neon_uimm0_bare:$Imm)>;
6845
6846 // Additional copy patterns for scalar types
6847 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6848           (UMOVwb (v16i8
6849             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6850
6851 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6852           (UMOVwh (v8i16
6853             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6854
6855 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6856           (FMOVws FPR32:$Rn)>;
6857
6858 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6859           (FMOVxd FPR64:$Rn)>;
6860
6861 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6862           (f64 FPR64:$Rn)>;
6863
6864 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6865           (v1i8 (EXTRACT_SUBREG (v16i8
6866             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6867             sub_8))>;
6868
6869 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6870           (v1i16 (EXTRACT_SUBREG (v8i16
6871             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6872             sub_16))>;
6873
6874 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6875           (FMOVsw $src)>;
6876
6877 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6878           (FMOVdx $src)>;
6879
6880 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
6881           (v8i8 (EXTRACT_SUBREG (v16i8
6882             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6883             sub_64))>;
6884
6885 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
6886           (v4i16 (EXTRACT_SUBREG (v8i16
6887             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6888             sub_64))>;
6889
6890 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6891           (v2i32 (EXTRACT_SUBREG (v16i8
6892             (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6893             sub_64))>;
6894
6895 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
6896           (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6897
6898 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
6899           (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6900
6901 def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)),
6902           (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6903
6904 def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)),
6905           (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6906
6907 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
6908           (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>;
6909 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
6910           (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>;
6911
6912 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6913           (v1f64 FPR64:$Rn)>;
6914
6915 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6916           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6917                          (f64 FPR64:$src), sub_64)>;
6918
6919 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
6920                     RegisterOperand ResVPR, Operand OpImm>
6921   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6922                (ins VPR128:$Rn, OpImm:$Imm),
6923                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6924                [],
6925                NoItinerary> {
6926   bits<4> Imm;
6927 }
6928
6929 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6930                               neon_uimm4_bare> {
6931   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6932 }
6933
6934 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6935                               neon_uimm3_bare> {
6936   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6937 }
6938
6939 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6940                               neon_uimm2_bare> {
6941   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6942 }
6943
6944 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6945                               neon_uimm1_bare> {
6946   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6947 }
6948
6949 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6950                               neon_uimm4_bare> {
6951   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6952 }
6953
6954 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6955                               neon_uimm3_bare> {
6956   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6957 }
6958
6959 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6960                               neon_uimm2_bare> {
6961   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6962 }
6963
6964 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6965                                        ValueType OpTy,ValueType NaTy,
6966                                        ValueType ExTy, Operand OpLImm,
6967                                        Operand OpNImm> {
6968 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6969         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6970
6971 def : Pat<(ResTy (Neon_vduplane
6972             (NaTy VPR64:$Rn), OpNImm:$Imm)),
6973           (ResTy (DUPELT
6974             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6975 }
6976 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6977                              neon_uimm4_bare, neon_uimm3_bare>;
6978 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6979                              neon_uimm4_bare, neon_uimm3_bare>;
6980 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6981                              neon_uimm3_bare, neon_uimm2_bare>;
6982 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6983                              neon_uimm3_bare, neon_uimm2_bare>;
6984 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6985                              neon_uimm2_bare, neon_uimm1_bare>;
6986 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6987                              neon_uimm2_bare, neon_uimm1_bare>;
6988 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6989                              neon_uimm1_bare, neon_uimm0_bare>;
6990 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6991                              neon_uimm2_bare, neon_uimm1_bare>;
6992 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6993                              neon_uimm2_bare, neon_uimm1_bare>;
6994 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6995                              neon_uimm1_bare, neon_uimm0_bare>;
6996
6997 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6998           (v2f32 (DUPELT2s
6999             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7000             (i64 0)))>;
7001 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
7002           (v4f32 (DUPELT4s
7003             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7004             (i64 0)))>;
7005 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
7006           (v2f64 (DUPELT2d
7007             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
7008             (i64 0)))>;
7009
7010 class NeonI_DUP<bit Q, string asmop, string rdlane,
7011                 RegisterOperand ResVPR, ValueType ResTy,
7012                 RegisterClass OpGPR, ValueType OpTy>
7013   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
7014                asmop # "\t$Rd" # rdlane # ", $Rn",
7015                [(set (ResTy ResVPR:$Rd),
7016                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
7017                NoItinerary>;
7018
7019 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
7020   let Inst{20-16} = 0b00001;
7021   // bits 17-20 are unspecified, but should be set to zero.
7022 }
7023
7024 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
7025   let Inst{20-16} = 0b00010;
7026   // bits 18-20 are unspecified, but should be set to zero.
7027 }
7028
7029 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
7030   let Inst{20-16} = 0b00100;
7031   // bits 19-20 are unspecified, but should be set to zero.
7032 }
7033
7034 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
7035   let Inst{20-16} = 0b01000;
7036   // bit 20 is unspecified, but should be set to zero.
7037 }
7038
7039 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
7040   let Inst{20-16} = 0b00001;
7041   // bits 17-20 are unspecified, but should be set to zero.
7042 }
7043
7044 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
7045   let Inst{20-16} = 0b00010;
7046   // bits 18-20 are unspecified, but should be set to zero.
7047 }
7048
7049 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
7050   let Inst{20-16} = 0b00100;
7051   // bits 19-20 are unspecified, but should be set to zero.
7052 }
7053
7054 // patterns for CONCAT_VECTORS
7055 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
7056 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
7057           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
7058 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
7059           (INSELd
7060             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7061             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
7062             (i64 1),
7063             (i64 0))>;
7064 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
7065           (DUPELT2d
7066             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7067             (i64 0))> ;
7068 }
7069
7070 defm : Concat_Vector_Pattern<v16i8, v8i8>;
7071 defm : Concat_Vector_Pattern<v8i16, v4i16>;
7072 defm : Concat_Vector_Pattern<v4i32, v2i32>;
7073 defm : Concat_Vector_Pattern<v2i64, v1i64>;
7074 defm : Concat_Vector_Pattern<v4f32, v2f32>;
7075 defm : Concat_Vector_Pattern<v2f64, v1f64>;
7076
7077 def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), undef)),
7078           (v2i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32))>;
7079 def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
7080           (EXTRACT_SUBREG
7081             (v4i32 (INSELs
7082               (v4i32 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)),
7083               (v4i32 (SUBREG_TO_REG (i64 0), FPR32:$Rm, sub_32)),
7084               (i64 1),
7085               (i64 0))),
7086             sub_64)>;
7087 def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rn))),
7088           (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
7089
7090 //patterns for EXTRACT_SUBVECTOR
7091 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
7092           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7093 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
7094           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7095 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
7096           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7097 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
7098           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7099 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
7100           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7101 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
7102           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7103
7104 // The followings are for instruction class (3V Elem)
7105
7106 // Variant 1
7107
7108 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
7109              string asmop, string ResS, string OpS, string EleOpS,
7110              Operand OpImm, RegisterOperand ResVPR,
7111              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7112   : NeonI_2VElem<q, u, size, opcode,
7113                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
7114                                          EleOpVPR:$Re, OpImm:$Index),
7115                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7116                  ", $Re." # EleOpS # "[$Index]",
7117                  [],
7118                  NoItinerary> {
7119   bits<3> Index;
7120   bits<5> Re;
7121
7122   let Constraints = "$src = $Rd";
7123 }
7124
7125 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
7126   // vector register class for element is always 128-bit to cover the max index
7127   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7128                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
7129     let Inst{11} = {Index{1}};
7130     let Inst{21} = {Index{0}};
7131     let Inst{20-16} = Re;
7132   }
7133
7134   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7135                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7136     let Inst{11} = {Index{1}};
7137     let Inst{21} = {Index{0}};
7138     let Inst{20-16} = Re;
7139   }
7140
7141   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7142   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7143                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7144     let Inst{11} = {Index{2}};
7145     let Inst{21} = {Index{1}};
7146     let Inst{20} = {Index{0}};
7147     let Inst{19-16} = Re{3-0};
7148   }
7149
7150   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7151                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7152     let Inst{11} = {Index{2}};
7153     let Inst{21} = {Index{1}};
7154     let Inst{20} = {Index{0}};
7155     let Inst{19-16} = Re{3-0};
7156   }
7157 }
7158
7159 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
7160 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
7161
7162 // Pattern for lane in 128-bit vector
7163 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7164                    RegisterOperand ResVPR, RegisterOperand OpVPR,
7165                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7166                    ValueType EleOpTy>
7167   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7168           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7169         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7170
7171 // Pattern for lane in 64-bit vector
7172 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7173                   RegisterOperand ResVPR, RegisterOperand OpVPR,
7174                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7175                   ValueType EleOpTy>
7176   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7177           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7178         (INST ResVPR:$src, OpVPR:$Rn,
7179           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7180
7181 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
7182 {
7183   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7184                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
7185
7186   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7187                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
7188
7189   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7190                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7191
7192   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7193                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7194
7195   // Index can only be half of the max value for lane in 64-bit vector
7196
7197   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7198                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
7199
7200   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7201                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7202 }
7203
7204 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
7205 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
7206
7207 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
7208                  string asmop, string ResS, string OpS, string EleOpS,
7209                  Operand OpImm, RegisterOperand ResVPR,
7210                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7211   : NeonI_2VElem<q, u, size, opcode,
7212                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
7213                                          EleOpVPR:$Re, OpImm:$Index),
7214                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7215                  ", $Re." # EleOpS # "[$Index]",
7216                  [],
7217                  NoItinerary> {
7218   bits<3> Index;
7219   bits<5> Re;
7220 }
7221
7222 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
7223   // vector register class for element is always 128-bit to cover the max index
7224   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7225                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
7226     let Inst{11} = {Index{1}};
7227     let Inst{21} = {Index{0}};
7228     let Inst{20-16} = Re;
7229   }
7230
7231   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7232                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7233     let Inst{11} = {Index{1}};
7234     let Inst{21} = {Index{0}};
7235     let Inst{20-16} = Re;
7236   }
7237
7238   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7239   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7240                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7241     let Inst{11} = {Index{2}};
7242     let Inst{21} = {Index{1}};
7243     let Inst{20} = {Index{0}};
7244     let Inst{19-16} = Re{3-0};
7245   }
7246
7247   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7248                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7249     let Inst{11} = {Index{2}};
7250     let Inst{21} = {Index{1}};
7251     let Inst{20} = {Index{0}};
7252     let Inst{19-16} = Re{3-0};
7253   }
7254 }
7255
7256 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7257 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7258 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7259
7260 // Pattern for lane in 128-bit vector
7261 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7262                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7263                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7264   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7265           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7266         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7267
7268 // Pattern for lane in 64-bit vector
7269 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7270                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7271                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7272   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7273           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7274         (INST OpVPR:$Rn,
7275           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7276
7277 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7278   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7279                          op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7280
7281   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7282                          op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7283
7284   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7285                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7286
7287   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7288                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7289
7290   // Index can only be half of the max value for lane in 64-bit vector
7291
7292   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7293                         op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7294
7295   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7296                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7297 }
7298
7299 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7300 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7301 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7302
7303 // Variant 2
7304
7305 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7306   // vector register class for element is always 128-bit to cover the max index
7307   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7308                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
7309     let Inst{11} = {Index{1}};
7310     let Inst{21} = {Index{0}};
7311     let Inst{20-16} = Re;
7312   }
7313
7314   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7315                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7316     let Inst{11} = {Index{1}};
7317     let Inst{21} = {Index{0}};
7318     let Inst{20-16} = Re;
7319   }
7320
7321   // _1d2d doesn't exist!
7322
7323   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7324                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
7325     let Inst{11} = {Index{0}};
7326     let Inst{21} = 0b0;
7327     let Inst{20-16} = Re;
7328   }
7329 }
7330
7331 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7332 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7333
7334 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7335                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7336                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7337                          SDPatternOperator coreop>
7338   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7339           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7340         (INST OpVPR:$Rn,
7341           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7342
7343 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7344   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7345                          op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7346
7347   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7348                          op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7349
7350   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7351                          op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7352
7353   // Index can only be half of the max value for lane in 64-bit vector
7354
7355   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7356                         op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7357
7358   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7359                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
7360                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7361 }
7362
7363 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7364 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7365
7366 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7367                        (v2f32 VPR64:$Rn))),
7368           (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7369
7370 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7371                        (v4f32 VPR128:$Rn))),
7372           (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7373
7374 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7375                        (v2f64 VPR128:$Rn))),
7376           (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7377
7378 // The followings are patterns using fma
7379 // -ffp-contract=fast generates fma
7380
7381 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7382   // vector register class for element is always 128-bit to cover the max index
7383   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7384                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
7385     let Inst{11} = {Index{1}};
7386     let Inst{21} = {Index{0}};
7387     let Inst{20-16} = Re;
7388   }
7389
7390   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7391                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7392     let Inst{11} = {Index{1}};
7393     let Inst{21} = {Index{0}};
7394     let Inst{20-16} = Re;
7395   }
7396
7397   // _1d2d doesn't exist!
7398
7399   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7400                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
7401     let Inst{11} = {Index{0}};
7402     let Inst{21} = 0b0;
7403     let Inst{20-16} = Re;
7404   }
7405 }
7406
7407 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7408 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7409
7410 // Pattern for lane in 128-bit vector
7411 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7412                        RegisterOperand ResVPR, RegisterOperand OpVPR,
7413                        ValueType ResTy, ValueType OpTy,
7414                        SDPatternOperator coreop>
7415   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7416                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7417         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7418
7419 // Pattern for lane 0
7420 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7421                       RegisterOperand ResVPR, ValueType ResTy>
7422   : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7423                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7424                    (ResTy ResVPR:$src))),
7425         (INST ResVPR:$src, ResVPR:$Rn,
7426               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7427
7428 // Pattern for lane in 64-bit vector
7429 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7430                       RegisterOperand ResVPR, RegisterOperand OpVPR,
7431                       ValueType ResTy, ValueType OpTy,
7432                       SDPatternOperator coreop>
7433   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7434                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7435         (INST ResVPR:$src, ResVPR:$Rn,
7436           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7437
7438 // Pattern for lane in 64-bit vector
7439 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7440                            SDPatternOperator op,
7441                            RegisterOperand ResVPR, RegisterOperand OpVPR,
7442                            ValueType ResTy, ValueType OpTy,
7443                            SDPatternOperator coreop>
7444   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7445                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7446         (INST ResVPR:$src, ResVPR:$Rn,
7447           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7448
7449
7450 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7451   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7452                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7453                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7454
7455   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7456                         op, VPR64, v2f32>;
7457
7458   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7459                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7460                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7461
7462   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7463                         op, VPR128, v4f32>;
7464
7465   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7466                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7467                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7468
7469   // Index can only be half of the max value for lane in 64-bit vector
7470
7471   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7472                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7473                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7474
7475   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7476                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7477                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7478 }
7479
7480 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7481
7482 // Pattern for lane 0
7483 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7484                       RegisterOperand ResVPR, ValueType ResTy>
7485   : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7486                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7487                    (ResTy ResVPR:$src))),
7488         (INST ResVPR:$src, ResVPR:$Rn,
7489               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7490
7491 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7492 {
7493   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7494                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7495                          BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7496
7497   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7498                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7499                          BinOpFrag<(Neon_vduplane
7500                                      (fneg node:$LHS), node:$RHS)>>;
7501
7502   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7503                         op, VPR64, v2f32>;
7504
7505   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7506                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7507                          BinOpFrag<(fneg (Neon_vduplane
7508                                      node:$LHS, node:$RHS))>>;
7509
7510   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7511                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7512                          BinOpFrag<(Neon_vduplane
7513                                      (fneg node:$LHS), node:$RHS)>>;
7514
7515   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7516                         op, VPR128, v4f32>;
7517
7518   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7519                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7520                          BinOpFrag<(fneg (Neon_vduplane
7521                                      node:$LHS, node:$RHS))>>;
7522
7523   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7524                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7525                          BinOpFrag<(Neon_vduplane
7526                                      (fneg node:$LHS), node:$RHS)>>;
7527
7528   // Index can only be half of the max value for lane in 64-bit vector
7529
7530   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7531                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7532                         BinOpFrag<(fneg (Neon_vduplane
7533                                     node:$LHS, node:$RHS))>>;
7534
7535   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7536                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7537                         BinOpFrag<(Neon_vduplane
7538                                     (fneg node:$LHS), node:$RHS)>>;
7539
7540   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7541                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7542                         BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7543
7544   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7545                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7546                         BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7547
7548   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7549                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7550                              BinOpFrag<(fneg (Neon_combine_2d
7551                                          node:$LHS, node:$RHS))>>;
7552
7553   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7554                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7555                              BinOpFrag<(Neon_combine_2d
7556                                          (fneg node:$LHS), (fneg node:$RHS))>>;
7557 }
7558
7559 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7560
7561 // Variant 3: Long type
7562 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7563 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7564
7565 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7566   // vector register class for element is always 128-bit to cover the max index
7567   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7568                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
7569     let Inst{11} = {Index{1}};
7570     let Inst{21} = {Index{0}};
7571     let Inst{20-16} = Re;
7572   }
7573
7574   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7575                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7576     let Inst{11} = {Index{1}};
7577     let Inst{21} = {Index{0}};
7578     let Inst{20-16} = Re;
7579   }
7580
7581   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7582   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7583                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7584     let Inst{11} = {Index{2}};
7585     let Inst{21} = {Index{1}};
7586     let Inst{20} = {Index{0}};
7587     let Inst{19-16} = Re{3-0};
7588   }
7589
7590   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7591                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7592     let Inst{11} = {Index{2}};
7593     let Inst{21} = {Index{1}};
7594     let Inst{20} = {Index{0}};
7595     let Inst{19-16} = Re{3-0};
7596   }
7597 }
7598
7599 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7600 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7601 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7602 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7603 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7604 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7605
7606 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7607   // vector register class for element is always 128-bit to cover the max index
7608   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7609                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
7610     let Inst{11} = {Index{1}};
7611     let Inst{21} = {Index{0}};
7612     let Inst{20-16} = Re;
7613   }
7614
7615   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7616                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7617     let Inst{11} = {Index{1}};
7618     let Inst{21} = {Index{0}};
7619     let Inst{20-16} = Re;
7620   }
7621
7622   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7623   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7624                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7625     let Inst{11} = {Index{2}};
7626     let Inst{21} = {Index{1}};
7627     let Inst{20} = {Index{0}};
7628     let Inst{19-16} = Re{3-0};
7629   }
7630
7631   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7632                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7633     let Inst{11} = {Index{2}};
7634     let Inst{21} = {Index{1}};
7635     let Inst{20} = {Index{0}};
7636     let Inst{19-16} = Re{3-0};
7637   }
7638 }
7639
7640 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7641 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7642 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7643
7644 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7645           (FMOVdd $src)>;
7646
7647 // Pattern for lane in 128-bit vector
7648 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7649                      RegisterOperand EleOpVPR, ValueType ResTy,
7650                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7651                      SDPatternOperator hiop>
7652   : Pat<(ResTy (op (ResTy VPR128:$src),
7653           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7654           (HalfOpTy (Neon_vduplane
7655                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7656         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7657
7658 // Pattern for lane in 64-bit vector
7659 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7660                     RegisterOperand EleOpVPR, ValueType ResTy,
7661                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7662                     SDPatternOperator hiop>
7663   : Pat<(ResTy (op (ResTy VPR128:$src),
7664           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7665           (HalfOpTy (Neon_vduplane
7666                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7667         (INST VPR128:$src, VPR128:$Rn,
7668           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7669
7670 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7671                      ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7672                      SDPatternOperator hiop, Instruction DupInst>
7673   : Pat<(ResTy (op (ResTy VPR128:$src),
7674           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7675           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7676         (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7677
7678 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7679   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7680                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7681
7682   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7683                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7684
7685   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7686                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7687
7688   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7689                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7690
7691   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7692                        op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7693
7694   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7695                        op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7696
7697   // Index can only be half of the max value for lane in 64-bit vector
7698
7699   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7700                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7701
7702   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7703                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7704
7705   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7706                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7707
7708   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7709                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7710 }
7711
7712 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7713 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7714 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7715 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7716
7717 // Pattern for lane in 128-bit vector
7718 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7719                          RegisterOperand EleOpVPR, ValueType ResTy,
7720                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7721                          SDPatternOperator hiop>
7722   : Pat<(ResTy (op
7723           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7724           (HalfOpTy (Neon_vduplane
7725                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7726         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7727
7728 // Pattern for lane in 64-bit vector
7729 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7730                         RegisterOperand EleOpVPR, ValueType ResTy,
7731                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7732                         SDPatternOperator hiop>
7733   : Pat<(ResTy (op
7734           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7735           (HalfOpTy (Neon_vduplane
7736                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7737         (INST VPR128:$Rn,
7738           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7739
7740 // Pattern for fixed lane 0
7741 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7742                          ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7743                          SDPatternOperator hiop, Instruction DupInst>
7744   : Pat<(ResTy (op
7745           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7746           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7747         (INST VPR128:$Rn, (DupInst $Re), 0)>;
7748
7749 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7750   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7751                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7752
7753   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7754                          op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7755
7756   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7757                          op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7758
7759   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7760                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7761
7762   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7763                            op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7764
7765   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7766                            op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7767
7768   // Index can only be half of the max value for lane in 64-bit vector
7769
7770   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7771                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7772
7773   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7774                         op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7775
7776   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7777                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7778
7779   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7780                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7781 }
7782
7783 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7784 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7785 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7786
7787 multiclass NI_qdma<SDPatternOperator op> {
7788   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7789                     (op node:$Ra,
7790                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7791
7792   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7793                     (op node:$Ra,
7794                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7795 }
7796
7797 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7798 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7799
7800 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7801   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7802                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7803                      v4i32, v4i16, v8i16>;
7804
7805   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7806                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7807                      v2i64, v2i32, v4i32>;
7808
7809   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7810                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
7811                        v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7812
7813   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7814                        !cast<PatFrag>(op # "_2d"), VPR128,
7815                        v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7816
7817   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7818                        !cast<PatFrag>(op # "_4s"),
7819                        v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7820
7821   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7822                        !cast<PatFrag>(op # "_2d"),
7823                        v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7824
7825   // Index can only be half of the max value for lane in 64-bit vector
7826
7827   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7828                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7829                     v4i32, v4i16, v4i16>;
7830
7831   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7832                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7833                     v2i64, v2i32, v2i32>;
7834
7835   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7836                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
7837                       v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7838
7839   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7840                       !cast<PatFrag>(op # "_2d"), VPR64,
7841                       v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7842 }
7843
7844 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7845 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7846
7847 // End of implementation for instruction class (3V Elem)
7848
7849 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7850                 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7851                 SDPatternOperator Neon_Rev>
7852   : NeonI_2VMisc<Q, U, size, opcode,
7853                (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7854                asmop # "\t$Rd." # Res # ", $Rn." # Res,
7855                [(set (ResTy ResVPR:$Rd),
7856                   (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7857                NoItinerary> ;
7858
7859 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7860                           v16i8, Neon_rev64>;
7861 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7862                          v8i16, Neon_rev64>;
7863 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7864                          v4i32, Neon_rev64>;
7865 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7866                          v8i8, Neon_rev64>;
7867 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7868                          v4i16, Neon_rev64>;
7869 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7870                          v2i32, Neon_rev64>;
7871
7872 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7873 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7874
7875 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7876                           v16i8, Neon_rev32>;
7877 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7878                           v8i16, Neon_rev32>;
7879 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7880                          v8i8, Neon_rev32>;
7881 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7882                          v4i16, Neon_rev32>;
7883
7884 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7885                           v16i8, Neon_rev16>;
7886 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7887                          v8i8, Neon_rev16>;
7888
7889 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7890                              SDPatternOperator Neon_Padd> {
7891   def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7892                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7893                            asmop # "\t$Rd.8h, $Rn.16b",
7894                            [(set (v8i16 VPR128:$Rd),
7895                               (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7896                            NoItinerary>;
7897
7898   def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7899                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7900                           asmop # "\t$Rd.4h, $Rn.8b",
7901                           [(set (v4i16 VPR64:$Rd),
7902                              (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7903                           NoItinerary>;
7904
7905   def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7906                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7907                            asmop # "\t$Rd.4s, $Rn.8h",
7908                            [(set (v4i32 VPR128:$Rd),
7909                               (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7910                            NoItinerary>;
7911
7912   def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7913                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7914                           asmop # "\t$Rd.2s, $Rn.4h",
7915                           [(set (v2i32 VPR64:$Rd),
7916                              (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7917                           NoItinerary>;
7918
7919   def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7920                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7921                            asmop # "\t$Rd.2d, $Rn.4s",
7922                            [(set (v2i64 VPR128:$Rd),
7923                               (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7924                            NoItinerary>;
7925
7926   def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7927                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7928                           asmop # "\t$Rd.1d, $Rn.2s",
7929                           [(set (v1i64 VPR64:$Rd),
7930                              (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7931                           NoItinerary>;
7932 }
7933
7934 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7935                                 int_arm_neon_vpaddls>;
7936 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7937                                 int_arm_neon_vpaddlu>;
7938
7939 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7940           (SADDLP2s1d $Rn)>;
7941 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7942           (UADDLP2s1d $Rn)>;
7943
7944 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7945                              SDPatternOperator Neon_Padd> {
7946   let Constraints = "$src = $Rd" in {
7947     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7948                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7949                              asmop # "\t$Rd.8h, $Rn.16b",
7950                              [(set (v8i16 VPR128:$Rd),
7951                                 (v8i16 (Neon_Padd
7952                                   (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7953                              NoItinerary>;
7954
7955     def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7956                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7957                             asmop # "\t$Rd.4h, $Rn.8b",
7958                             [(set (v4i16 VPR64:$Rd),
7959                                (v4i16 (Neon_Padd
7960                                  (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7961                             NoItinerary>;
7962
7963     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7964                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7965                             asmop # "\t$Rd.4s, $Rn.8h",
7966                             [(set (v4i32 VPR128:$Rd),
7967                                (v4i32 (Neon_Padd
7968                                  (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7969                             NoItinerary>;
7970
7971     def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7972                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7973                             asmop # "\t$Rd.2s, $Rn.4h",
7974                             [(set (v2i32 VPR64:$Rd),
7975                                (v2i32 (Neon_Padd
7976                                  (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7977                             NoItinerary>;
7978
7979     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7980                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7981                             asmop # "\t$Rd.2d, $Rn.4s",
7982                             [(set (v2i64 VPR128:$Rd),
7983                                (v2i64 (Neon_Padd
7984                                  (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7985                             NoItinerary>;
7986
7987     def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7988                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7989                             asmop # "\t$Rd.1d, $Rn.2s",
7990                             [(set (v1i64 VPR64:$Rd),
7991                                (v1i64 (Neon_Padd
7992                                  (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7993                             NoItinerary>;
7994   }
7995 }
7996
7997 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7998                                    int_arm_neon_vpadals>;
7999 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
8000                                    int_arm_neon_vpadalu>;
8001
8002 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
8003   def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8004                          (outs VPR128:$Rd), (ins VPR128:$Rn),
8005                          asmop # "\t$Rd.16b, $Rn.16b",
8006                          [], NoItinerary>;
8007
8008   def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8009                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8010                         asmop # "\t$Rd.8h, $Rn.8h",
8011                         [], NoItinerary>;
8012
8013   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8014                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8015                         asmop # "\t$Rd.4s, $Rn.4s",
8016                         [], NoItinerary>;
8017
8018   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8019                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8020                         asmop # "\t$Rd.2d, $Rn.2d",
8021                         [], NoItinerary>;
8022
8023   def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8024                          (outs VPR64:$Rd), (ins VPR64:$Rn),
8025                          asmop # "\t$Rd.8b, $Rn.8b",
8026                          [], NoItinerary>;
8027
8028   def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8029                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8030                         asmop # "\t$Rd.4h, $Rn.4h",
8031                         [], NoItinerary>;
8032
8033   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8034                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8035                         asmop # "\t$Rd.2s, $Rn.2s",
8036                         [], NoItinerary>;
8037 }
8038
8039 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
8040 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
8041 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
8042 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
8043
8044 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
8045                                           SDPatternOperator Neon_Op> {
8046   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
8047             (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
8048
8049   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
8050             (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
8051
8052   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
8053             (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
8054
8055   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
8056             (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
8057
8058   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
8059             (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
8060
8061   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
8062             (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
8063
8064   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
8065             (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
8066 }
8067
8068 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
8069 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
8070 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
8071
8072 def : Pat<(v16i8 (sub
8073             (v16i8 Neon_AllZero),
8074             (v16i8 VPR128:$Rn))),
8075           (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
8076 def : Pat<(v8i8 (sub
8077             (v8i8 Neon_AllZero),
8078             (v8i8 VPR64:$Rn))),
8079           (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
8080 def : Pat<(v8i16 (sub
8081             (v8i16 (bitconvert (v16i8 Neon_AllZero))),
8082             (v8i16 VPR128:$Rn))),
8083           (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
8084 def : Pat<(v4i16 (sub
8085             (v4i16 (bitconvert (v8i8 Neon_AllZero))),
8086             (v4i16 VPR64:$Rn))),
8087           (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
8088 def : Pat<(v4i32 (sub
8089             (v4i32 (bitconvert (v16i8 Neon_AllZero))),
8090             (v4i32 VPR128:$Rn))),
8091           (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
8092 def : Pat<(v2i32 (sub
8093             (v2i32 (bitconvert (v8i8 Neon_AllZero))),
8094             (v2i32 VPR64:$Rn))),
8095           (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
8096 def : Pat<(v2i64 (sub
8097             (v2i64 (bitconvert (v16i8 Neon_AllZero))),
8098             (v2i64 VPR128:$Rn))),
8099           (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
8100
8101 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
8102   let Constraints = "$src = $Rd" in {
8103     def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8104                            (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8105                            asmop # "\t$Rd.16b, $Rn.16b",
8106                            [], NoItinerary>;
8107
8108     def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8109                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8110                           asmop # "\t$Rd.8h, $Rn.8h",
8111                           [], NoItinerary>;
8112
8113     def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8114                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8115                           asmop # "\t$Rd.4s, $Rn.4s",
8116                           [], NoItinerary>;
8117
8118     def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8119                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8120                           asmop # "\t$Rd.2d, $Rn.2d",
8121                           [], NoItinerary>;
8122
8123     def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8124                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8125                           asmop # "\t$Rd.8b, $Rn.8b",
8126                           [], NoItinerary>;
8127
8128     def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8129                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8130                           asmop # "\t$Rd.4h, $Rn.4h",
8131                           [], NoItinerary>;
8132
8133     def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8134                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8135                           asmop # "\t$Rd.2s, $Rn.2s",
8136                           [], NoItinerary>;
8137   }
8138 }
8139
8140 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
8141 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
8142
8143 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
8144                                            SDPatternOperator Neon_Op> {
8145   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
8146             (v16i8 (!cast<Instruction>(Prefix # 16b)
8147               (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
8148
8149   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
8150             (v8i16 (!cast<Instruction>(Prefix # 8h)
8151               (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
8152
8153   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
8154             (v4i32 (!cast<Instruction>(Prefix # 4s)
8155               (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
8156
8157   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
8158             (v2i64 (!cast<Instruction>(Prefix # 2d)
8159               (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
8160
8161   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
8162             (v8i8 (!cast<Instruction>(Prefix # 8b)
8163               (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
8164
8165   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
8166             (v4i16 (!cast<Instruction>(Prefix # 4h)
8167               (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
8168
8169   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
8170             (v2i32 (!cast<Instruction>(Prefix # 2s)
8171               (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
8172 }
8173
8174 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
8175 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
8176
8177 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
8178                           SDPatternOperator Neon_Op> {
8179   def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
8180                          (outs VPR128:$Rd), (ins VPR128:$Rn),
8181                          asmop # "\t$Rd.16b, $Rn.16b",
8182                          [(set (v16i8 VPR128:$Rd),
8183                             (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
8184                          NoItinerary>;
8185
8186   def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
8187                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8188                         asmop # "\t$Rd.8h, $Rn.8h",
8189                         [(set (v8i16 VPR128:$Rd),
8190                            (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
8191                         NoItinerary>;
8192
8193   def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
8194                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8195                         asmop # "\t$Rd.4s, $Rn.4s",
8196                         [(set (v4i32 VPR128:$Rd),
8197                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8198                         NoItinerary>;
8199
8200   def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
8201                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8202                         asmop # "\t$Rd.8b, $Rn.8b",
8203                         [(set (v8i8 VPR64:$Rd),
8204                            (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
8205                         NoItinerary>;
8206
8207   def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
8208                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8209                         asmop # "\t$Rd.4h, $Rn.4h",
8210                         [(set (v4i16 VPR64:$Rd),
8211                            (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
8212                         NoItinerary>;
8213
8214   def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
8215                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8216                         asmop # "\t$Rd.2s, $Rn.2s",
8217                         [(set (v2i32 VPR64:$Rd),
8218                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8219                         NoItinerary>;
8220 }
8221
8222 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
8223 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
8224
8225 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
8226                               bits<5> Opcode> {
8227   def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
8228                          (outs VPR128:$Rd), (ins VPR128:$Rn),
8229                          asmop # "\t$Rd.16b, $Rn.16b",
8230                          [], NoItinerary>;
8231
8232   def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
8233                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8234                         asmop # "\t$Rd.8b, $Rn.8b",
8235                         [], NoItinerary>;
8236 }
8237
8238 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
8239 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
8240 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
8241
8242 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
8243                     (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8244 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8245                     (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8246
8247 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8248           (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8249 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8250           (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8251
8252 def : Pat<(v16i8 (xor
8253             (v16i8 VPR128:$Rn),
8254             (v16i8 Neon_AllOne))),
8255           (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8256 def : Pat<(v8i8 (xor
8257             (v8i8 VPR64:$Rn),
8258             (v8i8 Neon_AllOne))),
8259           (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8260 def : Pat<(v8i16 (xor
8261             (v8i16 VPR128:$Rn),
8262             (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8263           (NOT16b VPR128:$Rn)>;
8264 def : Pat<(v4i16 (xor
8265             (v4i16 VPR64:$Rn),
8266             (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8267           (NOT8b VPR64:$Rn)>;
8268 def : Pat<(v4i32 (xor
8269             (v4i32 VPR128:$Rn),
8270             (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8271           (NOT16b VPR128:$Rn)>;
8272 def : Pat<(v2i32 (xor
8273             (v2i32 VPR64:$Rn),
8274             (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8275           (NOT8b VPR64:$Rn)>;
8276 def : Pat<(v2i64 (xor
8277             (v2i64 VPR128:$Rn),
8278             (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8279           (NOT16b VPR128:$Rn)>;
8280
8281 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8282           (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8283 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8284           (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8285
8286 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8287                                 SDPatternOperator Neon_Op> {
8288   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8289                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8290                         asmop # "\t$Rd.4s, $Rn.4s",
8291                         [(set (v4f32 VPR128:$Rd),
8292                            (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8293                         NoItinerary>;
8294
8295   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8296                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8297                         asmop # "\t$Rd.2d, $Rn.2d",
8298                         [(set (v2f64 VPR128:$Rd),
8299                            (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8300                         NoItinerary>;
8301
8302   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8303                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8304                         asmop # "\t$Rd.2s, $Rn.2s",
8305                         [(set (v2f32 VPR64:$Rd),
8306                            (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8307                         NoItinerary>;
8308 }
8309
8310 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8311 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8312
8313 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8314   def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8315                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8316                           asmop # "\t$Rd.8b, $Rn.8h",
8317                           [], NoItinerary>;
8318
8319   def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8320                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8321                           asmop # "\t$Rd.4h, $Rn.4s",
8322                           [], NoItinerary>;
8323
8324   def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8325                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8326                           asmop # "\t$Rd.2s, $Rn.2d",
8327                           [], NoItinerary>;
8328
8329   let Constraints = "$Rd = $src" in {
8330     def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8331                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8332                              asmop # "2\t$Rd.16b, $Rn.8h",
8333                              [], NoItinerary>;
8334
8335     def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8336                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8337                             asmop # "2\t$Rd.8h, $Rn.4s",
8338                             [], NoItinerary>;
8339
8340     def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8341                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8342                             asmop # "2\t$Rd.4s, $Rn.2d",
8343                             [], NoItinerary>;
8344   }
8345 }
8346
8347 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8348 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8349 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8350 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8351
8352 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8353                                         SDPatternOperator Neon_Op> {
8354   def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8355             (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8356
8357   def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8358             (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8359
8360   def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8361             (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8362
8363   def : Pat<(v16i8 (concat_vectors
8364               (v8i8 VPR64:$src),
8365               (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8366             (!cast<Instruction>(Prefix # 8h16b)
8367               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8368               VPR128:$Rn)>;
8369
8370   def : Pat<(v8i16 (concat_vectors
8371               (v4i16 VPR64:$src),
8372               (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8373             (!cast<Instruction>(Prefix # 4s8h)
8374               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8375               VPR128:$Rn)>;
8376
8377   def : Pat<(v4i32 (concat_vectors
8378               (v2i32 VPR64:$src),
8379               (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8380             (!cast<Instruction>(Prefix # 2d4s)
8381               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8382               VPR128:$Rn)>;
8383 }
8384
8385 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8386 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8387 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8388 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8389
8390 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8391   let DecoderMethod = "DecodeSHLLInstruction" in {
8392     def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8393                             (outs VPR128:$Rd),
8394                             (ins VPR64:$Rn, uimm_exact8:$Imm),
8395                             asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8396                             [], NoItinerary>;
8397
8398     def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8399                             (outs VPR128:$Rd),
8400                             (ins VPR64:$Rn, uimm_exact16:$Imm),
8401                             asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8402                             [], NoItinerary>;
8403
8404     def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8405                             (outs VPR128:$Rd),
8406                             (ins VPR64:$Rn, uimm_exact32:$Imm),
8407                             asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8408                             [], NoItinerary>;
8409
8410     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8411                             (outs VPR128:$Rd),
8412                             (ins VPR128:$Rn, uimm_exact8:$Imm),
8413                             asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8414                             [], NoItinerary>;
8415
8416     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8417                             (outs VPR128:$Rd),
8418                             (ins VPR128:$Rn, uimm_exact16:$Imm),
8419                             asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8420                             [], NoItinerary>;
8421
8422     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8423                             (outs VPR128:$Rd),
8424                             (ins VPR128:$Rn, uimm_exact32:$Imm),
8425                             asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8426                             [], NoItinerary>;
8427   }
8428 }
8429
8430 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8431
8432 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8433                           SDPatternOperator ExtOp, Operand Neon_Imm,
8434                           string suffix>
8435   : Pat<(DesTy (shl
8436           (DesTy (ExtOp (OpTy VPR64:$Rn))),
8437             (DesTy (Neon_vdup
8438               (i32 Neon_Imm:$Imm))))),
8439         (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8440
8441 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8442                                SDPatternOperator ExtOp, Operand Neon_Imm,
8443                                string suffix, PatFrag GetHigh>
8444   : Pat<(DesTy (shl
8445           (DesTy (ExtOp
8446             (OpTy (GetHigh VPR128:$Rn)))),
8447               (DesTy (Neon_vdup
8448                 (i32 Neon_Imm:$Imm))))),
8449         (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8450
8451 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8452 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8453 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8454 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8455 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8456 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8457 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8458                                Neon_High16B>;
8459 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8460                                Neon_High16B>;
8461 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8462                                Neon_High8H>;
8463 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8464                                Neon_High8H>;
8465 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8466                                Neon_High4S>;
8467 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8468                                Neon_High4S>;
8469
8470 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8471   def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8472                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8473                           asmop # "\t$Rd.4h, $Rn.4s",
8474                           [], NoItinerary>;
8475
8476   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8477                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8478                           asmop # "\t$Rd.2s, $Rn.2d",
8479                           [], NoItinerary>;
8480
8481   let Constraints = "$src = $Rd" in {
8482     def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8483                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8484                             asmop # "2\t$Rd.8h, $Rn.4s",
8485                             [], NoItinerary>;
8486
8487     def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8488                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8489                             asmop # "2\t$Rd.4s, $Rn.2d",
8490                             [], NoItinerary>;
8491   }
8492 }
8493
8494 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8495
8496 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8497                                        SDPatternOperator f32_to_f16_Op,
8498                                        SDPatternOperator f64_to_f32_Op> {
8499
8500   def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8501               (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8502
8503   def : Pat<(v8i16 (concat_vectors
8504                 (v4i16 VPR64:$src),
8505                 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8506                   (!cast<Instruction>(prefix # "4s8h")
8507                     (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8508                     (v4f32 VPR128:$Rn))>;
8509
8510   def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8511             (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8512
8513   def : Pat<(v4f32 (concat_vectors
8514               (v2f32 VPR64:$src),
8515               (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8516                 (!cast<Instruction>(prefix # "2d4s")
8517                   (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8518                   (v2f64 VPR128:$Rn))>;
8519 }
8520
8521 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8522
8523 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8524                                  bits<5> opcode> {
8525   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8526                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8527                           asmop # "\t$Rd.2s, $Rn.2d",
8528                           [], NoItinerary>;
8529
8530   def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8531                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8532                           asmop # "2\t$Rd.4s, $Rn.2d",
8533                           [], NoItinerary> {
8534     let Constraints = "$src = $Rd";
8535   }
8536
8537   def : Pat<(v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))),
8538             (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8539
8540   def : Pat<(v4f32 (concat_vectors
8541               (v2f32 VPR64:$src),
8542               (v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))))),
8543             (!cast<Instruction>(prefix # "2d4s")
8544                (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8545                VPR128:$Rn)>;
8546 }
8547
8548 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8549
8550 def Neon_High4Float : PatFrag<(ops node:$in),
8551                               (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8552
8553 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8554   def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8555                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8556                           asmop # "\t$Rd.4s, $Rn.4h",
8557                           [], NoItinerary>;
8558
8559   def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8560                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8561                           asmop # "\t$Rd.2d, $Rn.2s",
8562                           [], NoItinerary>;
8563
8564   def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8565                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8566                           asmop # "2\t$Rd.4s, $Rn.8h",
8567                           [], NoItinerary>;
8568
8569   def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8570                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8571                           asmop # "2\t$Rd.2d, $Rn.4s",
8572                           [], NoItinerary>;
8573 }
8574
8575 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8576
8577 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8578   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8579             (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8580
8581   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8582               (v4i16 (Neon_High8H
8583                 (v8i16 VPR128:$Rn))))),
8584             (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8585
8586   def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8587             (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8588
8589   def : Pat<(v2f64 (fextend
8590               (v2f32 (Neon_High4Float
8591                 (v4f32 VPR128:$Rn))))),
8592             (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8593 }
8594
8595 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8596
8597 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8598                                 ValueType ResTy4s, ValueType OpTy4s,
8599                                 ValueType ResTy2d, ValueType OpTy2d,
8600                                 ValueType ResTy2s, ValueType OpTy2s,
8601                                 SDPatternOperator Neon_Op> {
8602
8603   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8604                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8605                         asmop # "\t$Rd.4s, $Rn.4s",
8606                         [(set (ResTy4s VPR128:$Rd),
8607                            (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8608                         NoItinerary>;
8609
8610   def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8611                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8612                         asmop # "\t$Rd.2d, $Rn.2d",
8613                         [(set (ResTy2d VPR128:$Rd),
8614                            (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8615                         NoItinerary>;
8616
8617   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8618                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8619                         asmop # "\t$Rd.2s, $Rn.2s",
8620                         [(set (ResTy2s VPR64:$Rd),
8621                            (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8622                         NoItinerary>;
8623 }
8624
8625 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8626                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8627   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8628                                 v2f64, v2i32, v2f32, Neon_Op>;
8629 }
8630
8631 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8632                                      int_arm_neon_vcvtns>;
8633 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8634                                      int_arm_neon_vcvtnu>;
8635 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8636                                      int_arm_neon_vcvtps>;
8637 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8638                                      int_arm_neon_vcvtpu>;
8639 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8640                                      int_arm_neon_vcvtms>;
8641 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8642                                      int_arm_neon_vcvtmu>;
8643 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8644 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8645 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8646                                      int_arm_neon_vcvtas>;
8647 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8648                                      int_arm_neon_vcvtau>;
8649
8650 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8651                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8652   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8653                                 v2i64, v2f32, v2i32, Neon_Op>;
8654 }
8655
8656 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8657 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8658
8659 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8660                                  bits<5> opcode, SDPatternOperator Neon_Op> {
8661   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8662                                 v2f64, v2f32, v2f32, Neon_Op>;
8663 }
8664
8665 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8666                                      int_aarch64_neon_frintn>;
8667 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8668 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8669 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8670 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8671 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8672 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8673 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8674                                     int_arm_neon_vrecpe>;
8675 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8676                                      int_arm_neon_vrsqrte>;
8677 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8678
8679 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8680                                bits<5> opcode, SDPatternOperator Neon_Op> {
8681   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8682                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8683                         asmop # "\t$Rd.4s, $Rn.4s",
8684                         [(set (v4i32 VPR128:$Rd),
8685                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8686                         NoItinerary>;
8687
8688   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8689                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8690                         asmop # "\t$Rd.2s, $Rn.2s",
8691                         [(set (v2i32 VPR64:$Rd),
8692                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8693                         NoItinerary>;
8694 }
8695
8696 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8697                                   int_arm_neon_vrecpe>;
8698 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8699                                    int_arm_neon_vrsqrte>;
8700
8701 // Crypto Class
8702 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8703                          string asmop, SDPatternOperator opnode>
8704   : NeonI_Crypto_AES<size, opcode,
8705                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8706                      asmop # "\t$Rd.16b, $Rn.16b",
8707                      [(set (v16i8 VPR128:$Rd),
8708                         (v16i8 (opnode (v16i8 VPR128:$src),
8709                                        (v16i8 VPR128:$Rn))))],
8710                      NoItinerary>{
8711   let Constraints = "$src = $Rd";
8712   let Predicates = [HasNEON, HasCrypto];
8713 }
8714
8715 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8716 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8717
8718 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8719                       string asmop, SDPatternOperator opnode>
8720   : NeonI_Crypto_AES<size, opcode,
8721                      (outs VPR128:$Rd), (ins VPR128:$Rn),
8722                      asmop # "\t$Rd.16b, $Rn.16b",
8723                      [(set (v16i8 VPR128:$Rd),
8724                         (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8725                      NoItinerary>;
8726
8727 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8728 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8729
8730 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8731                          string asmop, SDPatternOperator opnode>
8732   : NeonI_Crypto_SHA<size, opcode,
8733                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8734                      asmop # "\t$Rd.4s, $Rn.4s",
8735                      [(set (v4i32 VPR128:$Rd),
8736                         (v4i32 (opnode (v4i32 VPR128:$src),
8737                                        (v4i32 VPR128:$Rn))))],
8738                      NoItinerary> {
8739   let Constraints = "$src = $Rd";
8740   let Predicates = [HasNEON, HasCrypto];
8741 }
8742
8743 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8744                                  int_arm_neon_sha1su1>;
8745 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8746                                    int_arm_neon_sha256su0>;
8747
8748 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8749                          string asmop, SDPatternOperator opnode>
8750   : NeonI_Crypto_SHA<size, opcode,
8751                      (outs FPR32:$Rd), (ins FPR32:$Rn),
8752                      asmop # "\t$Rd, $Rn",
8753                      [(set (v1i32 FPR32:$Rd),
8754                         (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8755                      NoItinerary> {
8756   let Predicates = [HasNEON, HasCrypto];
8757 }
8758
8759 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8760
8761 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8762                            SDPatternOperator opnode>
8763   : NeonI_Crypto_3VSHA<size, opcode,
8764                        (outs VPR128:$Rd),
8765                        (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8766                        asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8767                        [(set (v4i32 VPR128:$Rd),
8768                           (v4i32 (opnode (v4i32 VPR128:$src),
8769                                          (v4i32 VPR128:$Rn),
8770                                          (v4i32 VPR128:$Rm))))],
8771                        NoItinerary> {
8772   let Constraints = "$src = $Rd";
8773   let Predicates = [HasNEON, HasCrypto];
8774 }
8775
8776 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8777                                    int_arm_neon_sha1su0>;
8778 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8779                                      int_arm_neon_sha256su1>;
8780
8781 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8782                            SDPatternOperator opnode>
8783   : NeonI_Crypto_3VSHA<size, opcode,
8784                        (outs FPR128:$Rd),
8785                        (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8786                        asmop # "\t$Rd, $Rn, $Rm.4s",
8787                        [(set (v4i32 FPR128:$Rd),
8788                           (v4i32 (opnode (v4i32 FPR128:$src),
8789                                          (v4i32 FPR128:$Rn),
8790                                          (v4i32 VPR128:$Rm))))],
8791                        NoItinerary> {
8792   let Constraints = "$src = $Rd";
8793   let Predicates = [HasNEON, HasCrypto];
8794 }
8795
8796 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8797                                    int_arm_neon_sha256h>;
8798 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8799                                     int_arm_neon_sha256h2>;
8800
8801 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8802                            SDPatternOperator opnode>
8803   : NeonI_Crypto_3VSHA<size, opcode,
8804                        (outs FPR128:$Rd),
8805                        (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8806                        asmop # "\t$Rd, $Rn, $Rm.4s",
8807                        [(set (v4i32 FPR128:$Rd),
8808                           (v4i32 (opnode (v4i32 FPR128:$src),
8809                                          (v1i32 FPR32:$Rn),
8810                                          (v4i32 VPR128:$Rm))))],
8811                        NoItinerary> {
8812   let Constraints = "$src = $Rd";
8813   let Predicates = [HasNEON, HasCrypto];
8814 }
8815
8816 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8817 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8818 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8819
8820 // Additional patterns to match shl to USHL.
8821 def : Pat<(v8i8 (shl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8822           (USHLvvv_8B $Rn, $Rm)>;
8823 def : Pat<(v4i16 (shl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8824           (USHLvvv_4H $Rn, $Rm)>;
8825 def : Pat<(v2i32 (shl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8826           (USHLvvv_2S $Rn, $Rm)>;
8827 def : Pat<(v1i64 (shl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8828           (USHLddd $Rn, $Rm)>;
8829 def : Pat<(v16i8 (shl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8830           (USHLvvv_16B $Rn, $Rm)>;
8831 def : Pat<(v8i16 (shl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8832           (USHLvvv_8H $Rn, $Rm)>;
8833 def : Pat<(v4i32 (shl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8834           (USHLvvv_4S $Rn, $Rm)>;
8835 def : Pat<(v2i64 (shl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8836           (USHLvvv_2D $Rn, $Rm)>;
8837
8838 // Additional patterns to match sra, srl.
8839 // For a vector right shift by vector, the shift amounts of SSHL/USHL are
8840 // negative. Negate the vector of shift amount first.
8841 def : Pat<(v8i8 (srl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8842           (USHLvvv_8B $Rn, (NEG8b $Rm))>;
8843 def : Pat<(v4i16 (srl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8844           (USHLvvv_4H $Rn, (NEG4h $Rm))>;
8845 def : Pat<(v2i32 (srl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8846           (USHLvvv_2S $Rn, (NEG2s $Rm))>;
8847 def : Pat<(v1i64 (srl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8848           (USHLddd $Rn, (NEGdd $Rm))>;
8849 def : Pat<(v16i8 (srl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8850           (USHLvvv_16B $Rn, (NEG16b $Rm))>;
8851 def : Pat<(v8i16 (srl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8852           (USHLvvv_8H $Rn, (NEG8h $Rm))>;
8853 def : Pat<(v4i32 (srl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8854           (USHLvvv_4S $Rn, (NEG4s $Rm))>;
8855 def : Pat<(v2i64 (srl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8856           (USHLvvv_2D $Rn, (NEG2d $Rm))>;
8857
8858 def : Pat<(v8i8 (sra (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8859           (SSHLvvv_8B $Rn, (NEG8b $Rm))>;
8860 def : Pat<(v4i16 (sra (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8861           (SSHLvvv_4H $Rn, (NEG4h $Rm))>;
8862 def : Pat<(v2i32 (sra (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8863           (SSHLvvv_2S $Rn, (NEG2s $Rm))>;
8864 def : Pat<(v1i64 (sra (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8865           (SSHLddd $Rn, (NEGdd $Rm))>;
8866 def : Pat<(v16i8 (sra (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8867           (SSHLvvv_16B $Rn, (NEG16b $Rm))>;
8868 def : Pat<(v8i16 (sra (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8869           (SSHLvvv_8H $Rn, (NEG8h $Rm))>;
8870 def : Pat<(v4i32 (sra (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8871           (SSHLvvv_4S $Rn, (NEG4s $Rm))>;
8872 def : Pat<(v2i64 (sra (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8873           (SSHLvvv_2D $Rn, (NEG2d $Rm))>;
8874
8875 //
8876 // Patterns for handling half-precision values
8877 //
8878
8879 // Convert between f16 value and f32 value
8880 def : Pat<(f32 (f16_to_f32 (i32 GPR32:$Rn))),
8881           (FCVTsh (EXTRACT_SUBREG (FMOVsw $Rn), sub_16))>;
8882 def : Pat<(i32 (f32_to_f16 (f32 FPR32:$Rn))),
8883           (FMOVws (SUBREG_TO_REG (i64 0), (f16 (FCVThs $Rn)), sub_16))>;
8884
8885 // Convert f16 value coming in as i16 value to f32
8886 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8887           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8888 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8889           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8890
8891 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8892             f32_to_f16 (f32 FPR32:$Rn))))))),
8893           (f32 FPR32:$Rn)>;
8894
8895 // Patterns for vector extract of half-precision FP value in i16 storage type
8896 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8897             (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8898           (FCVTsh (f16 (DUPhv_H
8899             (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8900             neon_uimm2_bare:$Imm)))>;
8901
8902 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8903             (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8904           (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8905
8906 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8907 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8908             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8909             (neon_uimm3_bare:$Imm))),
8910           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8911             (v8i16 (SUBREG_TO_REG (i64 0),
8912               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8913               sub_16)),
8914             neon_uimm3_bare:$Imm, 0))>;
8915
8916 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8917             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8918             (neon_uimm2_bare:$Imm))),
8919           (v4i16 (EXTRACT_SUBREG
8920             (v8i16 (INSELh
8921               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8922               (v8i16 (SUBREG_TO_REG (i64 0),
8923                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8924                 sub_16)),
8925               neon_uimm2_bare:$Imm, 0)),
8926             sub_64))>;
8927
8928 // Patterns for vector insert of half-precision FP value in i16 storage type
8929 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8930             (i32 (assertsext (i32 (fp_to_sint
8931               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8932             (neon_uimm3_bare:$Imm))),
8933           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8934             (v8i16 (SUBREG_TO_REG (i64 0),
8935               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8936               sub_16)),
8937             neon_uimm3_bare:$Imm, 0))>;
8938
8939 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8940             (i32 (assertsext (i32 (fp_to_sint
8941               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8942             (neon_uimm2_bare:$Imm))),
8943           (v4i16 (EXTRACT_SUBREG
8944             (v8i16 (INSELh
8945               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8946               (v8i16 (SUBREG_TO_REG (i64 0),
8947                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8948                 sub_16)),
8949               neon_uimm2_bare:$Imm, 0)),
8950             sub_64))>;
8951
8952 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8953             (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8954               (neon_uimm3_bare:$Imm1))),
8955           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8956             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8957
8958 // Patterns for vector copy of half-precision FP value in i16 storage type
8959 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8960             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8961               (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8962               65535)))))))),
8963             (neon_uimm3_bare:$Imm1))),
8964           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8965             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8966
8967 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8968             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8969               (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8970               65535)))))))),
8971             (neon_uimm3_bare:$Imm1))),
8972           (v4i16 (EXTRACT_SUBREG
8973             (v8i16 (INSELh
8974               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8975               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8976               neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),
8977             sub_64))>;
8978
8979