1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
17 def Neon_bsl : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
18 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
19 SDTCisSameAs<0, 3>]>>;
21 // (outs Result), (ins Imm, OpCmode)
22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
24 def Neon_movi : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
26 def Neon_mvni : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
28 // (outs Result), (ins Imm)
29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
30 [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
32 // (outs Result), (ins LHS, RHS, CondCode)
33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
34 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
38 [SDTCisVec<0>, SDTCisVec<1>]>>;
40 // (outs Result), (ins LHS, RHS)
41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
42 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
46 def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
47 def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
49 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
51 def Neon_uzp1 : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
52 def Neon_uzp2 : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
53 def Neon_zip1 : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
54 def Neon_zip2 : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
55 def Neon_trn1 : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
56 def Neon_trn2 : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
58 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
59 def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
60 def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
61 def Neon_rev16 : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
62 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
64 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
65 [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
66 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
67 [SDTCisVec<0>, SDTCisSameAs<0, 1>,
68 SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
70 //===----------------------------------------------------------------------===//
72 //===----------------------------------------------------------------------===//
74 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size, bits<5> opcode,
75 string asmop, SDPatternOperator opnode8B,
76 SDPatternOperator opnode16B,
78 let isCommutable = Commutable in {
79 def _8B : NeonI_3VSame<0b0, u, size, opcode,
80 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
81 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
82 [(set (v8i8 VPR64:$Rd),
83 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
86 def _16B : NeonI_3VSame<0b1, u, size, opcode,
87 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
88 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
89 [(set (v16i8 VPR128:$Rd),
90 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
96 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
97 string asmop, SDPatternOperator opnode,
99 let isCommutable = Commutable in {
100 def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
101 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
102 asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
103 [(set (v4i16 VPR64:$Rd),
104 (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
107 def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
108 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
109 asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
110 [(set (v8i16 VPR128:$Rd),
111 (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
114 def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
115 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
116 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
117 [(set (v2i32 VPR64:$Rd),
118 (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
121 def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
122 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
123 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
124 [(set (v4i32 VPR128:$Rd),
125 (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
129 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
130 string asmop, SDPatternOperator opnode,
132 : NeonI_3VSame_HS_sizes<u, opcode, asmop, opnode, Commutable> {
133 let isCommutable = Commutable in {
134 def _8B : NeonI_3VSame<0b0, u, 0b00, opcode,
135 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
136 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
137 [(set (v8i8 VPR64:$Rd),
138 (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
141 def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
142 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
143 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
144 [(set (v16i8 VPR128:$Rd),
145 (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
150 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
151 string asmop, SDPatternOperator opnode,
153 : NeonI_3VSame_BHS_sizes<u, opcode, asmop, opnode, Commutable> {
154 let isCommutable = Commutable in {
155 def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
156 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
157 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
158 [(set (v2i64 VPR128:$Rd),
159 (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
164 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
165 // but Result types can be integer or floating point types.
166 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
167 string asmop, SDPatternOperator opnode2S,
168 SDPatternOperator opnode4S,
169 SDPatternOperator opnode2D,
170 ValueType ResTy2S, ValueType ResTy4S,
171 ValueType ResTy2D, bit Commutable = 0> {
172 let isCommutable = Commutable in {
173 def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
174 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
175 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
176 [(set (ResTy2S VPR64:$Rd),
177 (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
180 def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
181 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
182 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
183 [(set (ResTy4S VPR128:$Rd),
184 (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
187 def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
188 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
189 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
190 [(set (ResTy2D VPR128:$Rd),
191 (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
196 //===----------------------------------------------------------------------===//
197 // Instruction Definitions
198 //===----------------------------------------------------------------------===//
200 // Vector Arithmetic Instructions
202 // Vector Add (Integer and Floating-Point)
204 defm ADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
205 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
206 v2f32, v4f32, v2f64, 1>;
208 // Vector Sub (Integer and Floating-Point)
210 defm SUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
211 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
212 v2f32, v4f32, v2f64, 0>;
214 // Vector Multiply (Integer and Floating-Point)
216 defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
217 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
218 v2f32, v4f32, v2f64, 1>;
220 // Vector Multiply (Polynomial)
222 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
223 int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
225 // Vector Multiply-accumulate and Multiply-subtract (Integer)
227 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
228 // two operands constraints.
229 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
230 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
231 bits<5> opcode, SDPatternOperator opnode>
232 : NeonI_3VSame<q, u, size, opcode,
233 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
234 asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
235 [(set (OpTy VPRC:$Rd),
236 (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
238 let Constraints = "$src = $Rd";
241 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
242 (add node:$Ra, (mul node:$Rn, node:$Rm))>;
244 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
245 (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
248 def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
249 0b0, 0b0, 0b00, 0b10010, Neon_mla>;
250 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
251 0b1, 0b0, 0b00, 0b10010, Neon_mla>;
252 def MLAvvv_4H: NeonI_3VSame_Constraint_impl<"mla", ".4h", VPR64, v4i16,
253 0b0, 0b0, 0b01, 0b10010, Neon_mla>;
254 def MLAvvv_8H: NeonI_3VSame_Constraint_impl<"mla", ".8h", VPR128, v8i16,
255 0b1, 0b0, 0b01, 0b10010, Neon_mla>;
256 def MLAvvv_2S: NeonI_3VSame_Constraint_impl<"mla", ".2s", VPR64, v2i32,
257 0b0, 0b0, 0b10, 0b10010, Neon_mla>;
258 def MLAvvv_4S: NeonI_3VSame_Constraint_impl<"mla", ".4s", VPR128, v4i32,
259 0b1, 0b0, 0b10, 0b10010, Neon_mla>;
261 def MLSvvv_8B: NeonI_3VSame_Constraint_impl<"mls", ".8b", VPR64, v8i8,
262 0b0, 0b1, 0b00, 0b10010, Neon_mls>;
263 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
264 0b1, 0b1, 0b00, 0b10010, Neon_mls>;
265 def MLSvvv_4H: NeonI_3VSame_Constraint_impl<"mls", ".4h", VPR64, v4i16,
266 0b0, 0b1, 0b01, 0b10010, Neon_mls>;
267 def MLSvvv_8H: NeonI_3VSame_Constraint_impl<"mls", ".8h", VPR128, v8i16,
268 0b1, 0b1, 0b01, 0b10010, Neon_mls>;
269 def MLSvvv_2S: NeonI_3VSame_Constraint_impl<"mls", ".2s", VPR64, v2i32,
270 0b0, 0b1, 0b10, 0b10010, Neon_mls>;
271 def MLSvvv_4S: NeonI_3VSame_Constraint_impl<"mls", ".4s", VPR128, v4i32,
272 0b1, 0b1, 0b10, 0b10010, Neon_mls>;
274 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
276 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
277 (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
279 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
280 (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
282 let Predicates = [HasNEON, UseFusedMAC] in {
283 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
284 0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
285 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
286 0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
287 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d", VPR128, v2f64,
288 0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
290 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s", VPR64, v2f32,
291 0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
292 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s", VPR128, v4f32,
293 0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
294 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d", VPR128, v2f64,
295 0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
298 // We're also allowed to match the fma instruction regardless of compile
300 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
301 (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
302 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
303 (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
304 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
305 (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
307 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
308 (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
309 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
310 (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
311 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
312 (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
314 // Vector Divide (Floating-Point)
316 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
317 v2f32, v4f32, v2f64, 0>;
319 // Vector Bitwise Operations
321 // Vector Bitwise AND
323 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
325 // Vector Bitwise Exclusive OR
327 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
331 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
333 // ORR disassembled as MOV if Vn==Vm
335 // Vector Move - register
336 // Alias for ORR if Vn=Vm.
337 // FIXME: This is actually the preferred syntax but TableGen can't deal with
338 // custom printing of aliases.
339 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
340 (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
341 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
342 (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
344 // The MOVI instruction takes two immediate operands. The first is the
345 // immediate encoding, while the second is the cmode. A cmode of 14, or
346 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
347 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
348 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
350 def Neon_not8B : PatFrag<(ops node:$in),
351 (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
352 def Neon_not16B : PatFrag<(ops node:$in),
353 (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
355 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
356 (or node:$Rn, (Neon_not8B node:$Rm))>;
358 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
359 (or node:$Rn, (Neon_not16B node:$Rm))>;
361 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
362 (and node:$Rn, (Neon_not8B node:$Rm))>;
364 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
365 (and node:$Rn, (Neon_not16B node:$Rm))>;
368 // Vector Bitwise OR NOT - register
370 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
371 Neon_orn8B, Neon_orn16B, 0>;
373 // Vector Bitwise Bit Clear (AND NOT) - register
375 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
376 Neon_bic8B, Neon_bic16B, 0>;
378 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
379 SDPatternOperator opnode16B,
381 Instruction INST16B> {
382 def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
383 (INST8B VPR64:$Rn, VPR64:$Rm)>;
384 def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
385 (INST8B VPR64:$Rn, VPR64:$Rm)>;
386 def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
387 (INST8B VPR64:$Rn, VPR64:$Rm)>;
388 def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
389 (INST16B VPR128:$Rn, VPR128:$Rm)>;
390 def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
391 (INST16B VPR128:$Rn, VPR128:$Rm)>;
392 def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
393 (INST16B VPR128:$Rn, VPR128:$Rm)>;
396 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
397 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
398 defm : Neon_bitwise2V_patterns<or, or, ORRvvv_8B, ORRvvv_16B>;
399 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
400 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
401 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
403 // Vector Bitwise Select
404 def BSLvvv_8B : NeonI_3VSame_Constraint_impl<"bsl", ".8b", VPR64, v8i8,
405 0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
407 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
408 0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
410 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
412 Instruction INST16B> {
413 // Disassociate type from instruction definition
414 def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
415 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
416 def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
417 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
418 def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
419 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
420 def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
421 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
422 def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
423 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
424 def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
425 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
427 // Allow to match BSL instruction pattern with non-constant operand
428 def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
429 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
430 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
431 def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
432 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
433 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
434 def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
435 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
436 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
437 def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
438 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
439 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
440 def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
441 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
442 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
443 def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
444 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
445 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
446 def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
447 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
448 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
449 def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
450 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
451 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
453 // Allow to match llvm.arm.* intrinsics.
454 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
455 (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
456 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
457 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
458 (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
459 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
460 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
461 (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
462 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
463 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
464 (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
465 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
466 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
467 (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
468 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
469 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
470 (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
471 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
472 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
473 (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
474 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
475 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
476 (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
477 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
478 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
479 (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
480 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
481 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
482 (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
483 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
484 def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
485 (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
486 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
489 // Additional patterns for bitwise instruction BSL
490 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
492 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
493 (Neon_bsl node:$src, node:$Rn, node:$Rm),
494 [{ (void)N; return false; }]>;
496 // Vector Bitwise Insert if True
498 def BITvvv_8B : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64, v8i8,
499 0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
500 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
501 0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
503 // Vector Bitwise Insert if False
505 def BIFvvv_8B : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64, v8i8,
506 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
507 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
508 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
510 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
512 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
513 (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
514 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
515 (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
517 // Vector Absolute Difference and Accumulate (Unsigned)
518 def UABAvvv_8B : NeonI_3VSame_Constraint_impl<"uaba", ".8b", VPR64, v8i8,
519 0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
520 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
521 0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
522 def UABAvvv_4H : NeonI_3VSame_Constraint_impl<"uaba", ".4h", VPR64, v4i16,
523 0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
524 def UABAvvv_8H : NeonI_3VSame_Constraint_impl<"uaba", ".8h", VPR128, v8i16,
525 0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
526 def UABAvvv_2S : NeonI_3VSame_Constraint_impl<"uaba", ".2s", VPR64, v2i32,
527 0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
528 def UABAvvv_4S : NeonI_3VSame_Constraint_impl<"uaba", ".4s", VPR128, v4i32,
529 0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
531 // Vector Absolute Difference and Accumulate (Signed)
532 def SABAvvv_8B : NeonI_3VSame_Constraint_impl<"saba", ".8b", VPR64, v8i8,
533 0b0, 0b0, 0b00, 0b01111, Neon_saba>;
534 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
535 0b1, 0b0, 0b00, 0b01111, Neon_saba>;
536 def SABAvvv_4H : NeonI_3VSame_Constraint_impl<"saba", ".4h", VPR64, v4i16,
537 0b0, 0b0, 0b01, 0b01111, Neon_saba>;
538 def SABAvvv_8H : NeonI_3VSame_Constraint_impl<"saba", ".8h", VPR128, v8i16,
539 0b1, 0b0, 0b01, 0b01111, Neon_saba>;
540 def SABAvvv_2S : NeonI_3VSame_Constraint_impl<"saba", ".2s", VPR64, v2i32,
541 0b0, 0b0, 0b10, 0b01111, Neon_saba>;
542 def SABAvvv_4S : NeonI_3VSame_Constraint_impl<"saba", ".4s", VPR128, v4i32,
543 0b1, 0b0, 0b10, 0b01111, Neon_saba>;
546 // Vector Absolute Difference (Signed, Unsigned)
547 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
548 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
550 // Vector Absolute Difference (Floating Point)
551 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
552 int_arm_neon_vabds, int_arm_neon_vabds,
553 int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
555 // Vector Reciprocal Step (Floating Point)
556 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
557 int_arm_neon_vrecps, int_arm_neon_vrecps,
559 v2f32, v4f32, v2f64, 0>;
561 // Vector Reciprocal Square Root Step (Floating Point)
562 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
563 int_arm_neon_vrsqrts,
564 int_arm_neon_vrsqrts,
565 int_arm_neon_vrsqrts,
566 v2f32, v4f32, v2f64, 0>;
568 // Vector Comparisons
570 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
571 (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
572 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
573 (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
574 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
575 (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
576 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
577 (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
578 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
579 (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
581 // NeonI_compare_aliases class: swaps register operands to implement
582 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
583 class NeonI_compare_aliases<string asmop, string asmlane,
584 Instruction inst, RegisterOperand VPRC>
585 : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
587 (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
589 // Vector Comparisons (Integer)
591 // Vector Compare Mask Equal (Integer)
592 let isCommutable =1 in {
593 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
596 // Vector Compare Mask Higher or Same (Unsigned Integer)
597 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
599 // Vector Compare Mask Greater Than or Equal (Integer)
600 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
602 // Vector Compare Mask Higher (Unsigned Integer)
603 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
605 // Vector Compare Mask Greater Than (Integer)
606 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
608 // Vector Compare Mask Bitwise Test (Integer)
609 defm CMTSTvvv: NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
611 // Vector Compare Mask Less or Same (Unsigned Integer)
612 // CMLS is alias for CMHS with operands reversed.
613 def CMLSvvv_8B : NeonI_compare_aliases<"cmls", ".8b", CMHSvvv_8B, VPR64>;
614 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
615 def CMLSvvv_4H : NeonI_compare_aliases<"cmls", ".4h", CMHSvvv_4H, VPR64>;
616 def CMLSvvv_8H : NeonI_compare_aliases<"cmls", ".8h", CMHSvvv_8H, VPR128>;
617 def CMLSvvv_2S : NeonI_compare_aliases<"cmls", ".2s", CMHSvvv_2S, VPR64>;
618 def CMLSvvv_4S : NeonI_compare_aliases<"cmls", ".4s", CMHSvvv_4S, VPR128>;
619 def CMLSvvv_2D : NeonI_compare_aliases<"cmls", ".2d", CMHSvvv_2D, VPR128>;
621 // Vector Compare Mask Less Than or Equal (Integer)
622 // CMLE is alias for CMGE with operands reversed.
623 def CMLEvvv_8B : NeonI_compare_aliases<"cmle", ".8b", CMGEvvv_8B, VPR64>;
624 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
625 def CMLEvvv_4H : NeonI_compare_aliases<"cmle", ".4h", CMGEvvv_4H, VPR64>;
626 def CMLEvvv_8H : NeonI_compare_aliases<"cmle", ".8h", CMGEvvv_8H, VPR128>;
627 def CMLEvvv_2S : NeonI_compare_aliases<"cmle", ".2s", CMGEvvv_2S, VPR64>;
628 def CMLEvvv_4S : NeonI_compare_aliases<"cmle", ".4s", CMGEvvv_4S, VPR128>;
629 def CMLEvvv_2D : NeonI_compare_aliases<"cmle", ".2d", CMGEvvv_2D, VPR128>;
631 // Vector Compare Mask Lower (Unsigned Integer)
632 // CMLO is alias for CMHI with operands reversed.
633 def CMLOvvv_8B : NeonI_compare_aliases<"cmlo", ".8b", CMHIvvv_8B, VPR64>;
634 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
635 def CMLOvvv_4H : NeonI_compare_aliases<"cmlo", ".4h", CMHIvvv_4H, VPR64>;
636 def CMLOvvv_8H : NeonI_compare_aliases<"cmlo", ".8h", CMHIvvv_8H, VPR128>;
637 def CMLOvvv_2S : NeonI_compare_aliases<"cmlo", ".2s", CMHIvvv_2S, VPR64>;
638 def CMLOvvv_4S : NeonI_compare_aliases<"cmlo", ".4s", CMHIvvv_4S, VPR128>;
639 def CMLOvvv_2D : NeonI_compare_aliases<"cmlo", ".2d", CMHIvvv_2D, VPR128>;
641 // Vector Compare Mask Less Than (Integer)
642 // CMLT is alias for CMGT with operands reversed.
643 def CMLTvvv_8B : NeonI_compare_aliases<"cmlt", ".8b", CMGTvvv_8B, VPR64>;
644 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
645 def CMLTvvv_4H : NeonI_compare_aliases<"cmlt", ".4h", CMGTvvv_4H, VPR64>;
646 def CMLTvvv_8H : NeonI_compare_aliases<"cmlt", ".8h", CMGTvvv_8H, VPR128>;
647 def CMLTvvv_2S : NeonI_compare_aliases<"cmlt", ".2s", CMGTvvv_2S, VPR64>;
648 def CMLTvvv_4S : NeonI_compare_aliases<"cmlt", ".4s", CMGTvvv_4S, VPR128>;
649 def CMLTvvv_2D : NeonI_compare_aliases<"cmlt", ".2d", CMGTvvv_2D, VPR128>;
652 def neon_uimm0_asmoperand : AsmOperandClass
655 let PredicateMethod = "isUImm<0>";
656 let RenderMethod = "addImmOperands";
659 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
660 let ParserMatchClass = neon_uimm0_asmoperand;
661 let PrintMethod = "printNeonUImm0Operand";
665 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
667 def _8B : NeonI_2VMisc<0b0, u, 0b00, opcode,
668 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
669 asmop # "\t$Rd.8b, $Rn.8b, $Imm",
670 [(set (v8i8 VPR64:$Rd),
671 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
674 def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
675 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
676 asmop # "\t$Rd.16b, $Rn.16b, $Imm",
677 [(set (v16i8 VPR128:$Rd),
678 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
681 def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
682 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
683 asmop # "\t$Rd.4h, $Rn.4h, $Imm",
684 [(set (v4i16 VPR64:$Rd),
685 (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
688 def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
689 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
690 asmop # "\t$Rd.8h, $Rn.8h, $Imm",
691 [(set (v8i16 VPR128:$Rd),
692 (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
695 def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
696 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
697 asmop # "\t$Rd.2s, $Rn.2s, $Imm",
698 [(set (v2i32 VPR64:$Rd),
699 (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
702 def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
703 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
704 asmop # "\t$Rd.4s, $Rn.4s, $Imm",
705 [(set (v4i32 VPR128:$Rd),
706 (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
709 def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
710 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
711 asmop # "\t$Rd.2d, $Rn.2d, $Imm",
712 [(set (v2i64 VPR128:$Rd),
713 (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
717 // Vector Compare Mask Equal to Zero (Integer)
718 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
720 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
721 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
723 // Vector Compare Mask Greater Than Zero (Signed Integer)
724 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
726 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
727 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
729 // Vector Compare Mask Less Than Zero (Signed Integer)
730 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
732 // Vector Comparisons (Floating Point)
734 // Vector Compare Mask Equal (Floating Point)
735 let isCommutable =1 in {
736 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
737 Neon_cmeq, Neon_cmeq,
738 v2i32, v4i32, v2i64, 0>;
741 // Vector Compare Mask Greater Than Or Equal (Floating Point)
742 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
743 Neon_cmge, Neon_cmge,
744 v2i32, v4i32, v2i64, 0>;
746 // Vector Compare Mask Greater Than (Floating Point)
747 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
748 Neon_cmgt, Neon_cmgt,
749 v2i32, v4i32, v2i64, 0>;
751 // Vector Compare Mask Less Than Or Equal (Floating Point)
752 // FCMLE is alias for FCMGE with operands reversed.
753 def FCMLEvvv_2S : NeonI_compare_aliases<"fcmle", ".2s", FCMGEvvv_2S, VPR64>;
754 def FCMLEvvv_4S : NeonI_compare_aliases<"fcmle", ".4s", FCMGEvvv_4S, VPR128>;
755 def FCMLEvvv_2D : NeonI_compare_aliases<"fcmle", ".2d", FCMGEvvv_2D, VPR128>;
757 // Vector Compare Mask Less Than (Floating Point)
758 // FCMLT is alias for FCMGT with operands reversed.
759 def FCMLTvvv_2S : NeonI_compare_aliases<"fcmlt", ".2s", FCMGTvvv_2S, VPR64>;
760 def FCMLTvvv_4S : NeonI_compare_aliases<"fcmlt", ".4s", FCMGTvvv_4S, VPR128>;
761 def FCMLTvvv_2D : NeonI_compare_aliases<"fcmlt", ".2d", FCMGTvvv_2D, VPR128>;
764 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
765 string asmop, CondCode CC>
767 def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
768 (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
769 asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
770 [(set (v2i32 VPR64:$Rd),
771 (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpimm:$FPImm), CC)))],
774 def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
775 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
776 asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
777 [(set (v4i32 VPR128:$Rd),
778 (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
781 def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
782 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
783 asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
784 [(set (v2i64 VPR128:$Rd),
785 (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
789 // Vector Compare Mask Equal to Zero (Floating Point)
790 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
792 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
793 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
795 // Vector Compare Mask Greater Than Zero (Floating Point)
796 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
798 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
799 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
801 // Vector Compare Mask Less Than Zero (Floating Point)
802 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
804 // Vector Absolute Comparisons (Floating Point)
806 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
807 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
808 int_arm_neon_vacged, int_arm_neon_vacgeq,
809 int_aarch64_neon_vacgeq,
810 v2i32, v4i32, v2i64, 0>;
812 // Vector Absolute Compare Mask Greater Than (Floating Point)
813 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
814 int_arm_neon_vacgtd, int_arm_neon_vacgtq,
815 int_aarch64_neon_vacgtq,
816 v2i32, v4i32, v2i64, 0>;
818 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
819 // FACLE is alias for FACGE with operands reversed.
820 def FACLEvvv_2S : NeonI_compare_aliases<"facle", ".2s", FACGEvvv_2S, VPR64>;
821 def FACLEvvv_4S : NeonI_compare_aliases<"facle", ".4s", FACGEvvv_4S, VPR128>;
822 def FACLEvvv_2D : NeonI_compare_aliases<"facle", ".2d", FACGEvvv_2D, VPR128>;
824 // Vector Absolute Compare Mask Less Than (Floating Point)
825 // FACLT is alias for FACGT with operands reversed.
826 def FACLTvvv_2S : NeonI_compare_aliases<"faclt", ".2s", FACGTvvv_2S, VPR64>;
827 def FACLTvvv_4S : NeonI_compare_aliases<"faclt", ".4s", FACGTvvv_4S, VPR128>;
828 def FACLTvvv_2D : NeonI_compare_aliases<"faclt", ".2d", FACGTvvv_2D, VPR128>;
830 // Vector halving add (Integer Signed, Unsigned)
831 defm SHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
832 int_arm_neon_vhadds, 1>;
833 defm UHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
834 int_arm_neon_vhaddu, 1>;
836 // Vector halving sub (Integer Signed, Unsigned)
837 defm SHSUBvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
838 int_arm_neon_vhsubs, 0>;
839 defm UHSUBvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
840 int_arm_neon_vhsubu, 0>;
842 // Vector rouding halving add (Integer Signed, Unsigned)
843 defm SRHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
844 int_arm_neon_vrhadds, 1>;
845 defm URHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
846 int_arm_neon_vrhaddu, 1>;
848 // Vector Saturating add (Integer Signed, Unsigned)
849 defm SQADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
850 int_arm_neon_vqadds, 1>;
851 defm UQADDvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
852 int_arm_neon_vqaddu, 1>;
854 // Vector Saturating sub (Integer Signed, Unsigned)
855 defm SQSUBvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
856 int_arm_neon_vqsubs, 1>;
857 defm UQSUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
858 int_arm_neon_vqsubu, 1>;
860 // Vector Shift Left (Signed and Unsigned Integer)
861 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
862 int_arm_neon_vshifts, 1>;
863 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
864 int_arm_neon_vshiftu, 1>;
866 // Vector Saturating Shift Left (Signed and Unsigned Integer)
867 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
868 int_arm_neon_vqshifts, 1>;
869 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
870 int_arm_neon_vqshiftu, 1>;
872 // Vector Rouding Shift Left (Signed and Unsigned Integer)
873 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
874 int_arm_neon_vrshifts, 1>;
875 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
876 int_arm_neon_vrshiftu, 1>;
878 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
879 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
880 int_arm_neon_vqrshifts, 1>;
881 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
882 int_arm_neon_vqrshiftu, 1>;
884 // Vector Maximum (Signed and Unsigned Integer)
885 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
886 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
888 // Vector Minimum (Signed and Unsigned Integer)
889 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
890 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
892 // Vector Maximum (Floating Point)
893 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
894 int_arm_neon_vmaxs, int_arm_neon_vmaxs,
895 int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
897 // Vector Minimum (Floating Point)
898 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
899 int_arm_neon_vmins, int_arm_neon_vmins,
900 int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
902 // Vector maxNum (Floating Point) - prefer a number over a quiet NaN)
903 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
904 int_aarch64_neon_vmaxnm,
905 int_aarch64_neon_vmaxnm,
906 int_aarch64_neon_vmaxnm,
907 v2f32, v4f32, v2f64, 1>;
909 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
910 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
911 int_aarch64_neon_vminnm,
912 int_aarch64_neon_vminnm,
913 int_aarch64_neon_vminnm,
914 v2f32, v4f32, v2f64, 1>;
916 // Vector Maximum Pairwise (Signed and Unsigned Integer)
917 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
918 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
920 // Vector Minimum Pairwise (Signed and Unsigned Integer)
921 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
922 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
924 // Vector Maximum Pairwise (Floating Point)
925 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
926 int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
927 int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
929 // Vector Minimum Pairwise (Floating Point)
930 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
931 int_arm_neon_vpmins, int_arm_neon_vpmins,
932 int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
934 // Vector maxNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
935 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
936 int_aarch64_neon_vpmaxnm,
937 int_aarch64_neon_vpmaxnm,
938 int_aarch64_neon_vpmaxnm,
939 v2f32, v4f32, v2f64, 1>;
941 // Vector minNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
942 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
943 int_aarch64_neon_vpminnm,
944 int_aarch64_neon_vpminnm,
945 int_aarch64_neon_vpminnm,
946 v2f32, v4f32, v2f64, 1>;
948 // Vector Addition Pairwise (Integer)
949 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
951 // Vector Addition Pairwise (Floating Point)
952 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
956 v2f32, v4f32, v2f64, 1>;
958 // Vector Saturating Doubling Multiply High
959 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
960 int_arm_neon_vqdmulh, 1>;
962 // Vector Saturating Rouding Doubling Multiply High
963 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
964 int_arm_neon_vqrdmulh, 1>;
966 // Vector Multiply Extended (Floating Point)
967 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
968 int_aarch64_neon_vmulx,
969 int_aarch64_neon_vmulx,
970 int_aarch64_neon_vmulx,
971 v2f32, v4f32, v2f64, 1>;
973 // Vector Immediate Instructions
975 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
977 def _asmoperand : AsmOperandClass
979 let Name = "NeonMovImmShift" # PREFIX;
980 let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
981 let PredicateMethod = "isNeonMovImmShift" # PREFIX;
985 // Definition of vector immediates shift operands
987 // The selectable use-cases extract the shift operation
988 // information from the OpCmode fields encoded in the immediate.
989 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
990 uint64_t OpCmode = N->getZExtValue();
992 unsigned ShiftOnesIn;
994 A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
995 if (!HasShift) return SDValue();
996 return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
999 // Vector immediates shift operands which accept LSL and MSL
1000 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1001 // or 0, 8 (LSLH) or 8, 16 (MSL).
1002 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1003 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1004 // LSLH restricts shift amount to 0, 8 out of 0, 8, 16, 24
1005 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1007 multiclass neon_mov_imm_shift_operands<string PREFIX,
1008 string HALF, string ISHALF, code pred>
1010 def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1013 "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1015 "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1016 let ParserMatchClass =
1017 !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1021 defm neon_mov_imm_LSL : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1023 unsigned ShiftOnesIn;
1025 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1026 return (HasShift && !ShiftOnesIn);
1029 defm neon_mov_imm_MSL : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1031 unsigned ShiftOnesIn;
1033 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1034 return (HasShift && ShiftOnesIn);
1037 defm neon_mov_imm_LSLH : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1039 unsigned ShiftOnesIn;
1041 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1042 return (HasShift && !ShiftOnesIn);
1045 def neon_uimm1_asmoperand : AsmOperandClass
1048 let PredicateMethod = "isUImm<1>";
1049 let RenderMethod = "addImmOperands";
1052 def neon_uimm2_asmoperand : AsmOperandClass
1055 let PredicateMethod = "isUImm<2>";
1056 let RenderMethod = "addImmOperands";
1059 def neon_uimm8_asmoperand : AsmOperandClass
1062 let PredicateMethod = "isUImm<8>";
1063 let RenderMethod = "addImmOperands";
1066 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1067 let ParserMatchClass = neon_uimm8_asmoperand;
1068 let PrintMethod = "printUImmHexOperand";
1071 def neon_uimm64_mask_asmoperand : AsmOperandClass
1073 let Name = "NeonUImm64Mask";
1074 let PredicateMethod = "isNeonUImm64Mask";
1075 let RenderMethod = "addNeonUImm64MaskOperands";
1078 // MCOperand for 64-bit bytemask with each byte having only the
1079 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1080 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1081 let ParserMatchClass = neon_uimm64_mask_asmoperand;
1082 let PrintMethod = "printNeonUImm64MaskOperand";
1085 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1086 SDPatternOperator opnode>
1088 // shift zeros, per word
1089 def _2S : NeonI_1VModImm<0b0, op,
1091 (ins neon_uimm8:$Imm,
1092 neon_mov_imm_LSL_operand:$Simm),
1093 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1094 [(set (v2i32 VPR64:$Rd),
1095 (v2i32 (opnode (timm:$Imm),
1096 (neon_mov_imm_LSL_operand:$Simm))))],
1099 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1102 def _4S : NeonI_1VModImm<0b1, op,
1104 (ins neon_uimm8:$Imm,
1105 neon_mov_imm_LSL_operand:$Simm),
1106 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1107 [(set (v4i32 VPR128:$Rd),
1108 (v4i32 (opnode (timm:$Imm),
1109 (neon_mov_imm_LSL_operand:$Simm))))],
1112 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1115 // shift zeros, per halfword
1116 def _4H : NeonI_1VModImm<0b0, op,
1118 (ins neon_uimm8:$Imm,
1119 neon_mov_imm_LSLH_operand:$Simm),
1120 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1121 [(set (v4i16 VPR64:$Rd),
1122 (v4i16 (opnode (timm:$Imm),
1123 (neon_mov_imm_LSLH_operand:$Simm))))],
1126 let cmode = {0b1, 0b0, Simm, 0b0};
1129 def _8H : NeonI_1VModImm<0b1, op,
1131 (ins neon_uimm8:$Imm,
1132 neon_mov_imm_LSLH_operand:$Simm),
1133 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1134 [(set (v8i16 VPR128:$Rd),
1135 (v8i16 (opnode (timm:$Imm),
1136 (neon_mov_imm_LSLH_operand:$Simm))))],
1139 let cmode = {0b1, 0b0, Simm, 0b0};
1143 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1144 SDPatternOperator opnode,
1145 SDPatternOperator neonopnode>
1147 let Constraints = "$src = $Rd" in {
1148 // shift zeros, per word
1149 def _2S : NeonI_1VModImm<0b0, op,
1151 (ins VPR64:$src, neon_uimm8:$Imm,
1152 neon_mov_imm_LSL_operand:$Simm),
1153 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1154 [(set (v2i32 VPR64:$Rd),
1155 (v2i32 (opnode (v2i32 VPR64:$src),
1156 (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1157 neon_mov_imm_LSL_operand:$Simm)))))))],
1160 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1163 def _4S : NeonI_1VModImm<0b1, op,
1165 (ins VPR128:$src, neon_uimm8:$Imm,
1166 neon_mov_imm_LSL_operand:$Simm),
1167 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1168 [(set (v4i32 VPR128:$Rd),
1169 (v4i32 (opnode (v4i32 VPR128:$src),
1170 (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1171 neon_mov_imm_LSL_operand:$Simm)))))))],
1174 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1177 // shift zeros, per halfword
1178 def _4H : NeonI_1VModImm<0b0, op,
1180 (ins VPR64:$src, neon_uimm8:$Imm,
1181 neon_mov_imm_LSLH_operand:$Simm),
1182 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1183 [(set (v4i16 VPR64:$Rd),
1184 (v4i16 (opnode (v4i16 VPR64:$src),
1185 (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1186 neon_mov_imm_LSL_operand:$Simm)))))))],
1189 let cmode = {0b1, 0b0, Simm, 0b1};
1192 def _8H : NeonI_1VModImm<0b1, op,
1194 (ins VPR128:$src, neon_uimm8:$Imm,
1195 neon_mov_imm_LSLH_operand:$Simm),
1196 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1197 [(set (v8i16 VPR128:$Rd),
1198 (v8i16 (opnode (v8i16 VPR128:$src),
1199 (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1200 neon_mov_imm_LSL_operand:$Simm)))))))],
1203 let cmode = {0b1, 0b0, Simm, 0b1};
1208 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1209 SDPatternOperator opnode>
1211 // shift ones, per word
1212 def _2S : NeonI_1VModImm<0b0, op,
1214 (ins neon_uimm8:$Imm,
1215 neon_mov_imm_MSL_operand:$Simm),
1216 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1217 [(set (v2i32 VPR64:$Rd),
1218 (v2i32 (opnode (timm:$Imm),
1219 (neon_mov_imm_MSL_operand:$Simm))))],
1222 let cmode = {0b1, 0b1, 0b0, Simm};
1225 def _4S : NeonI_1VModImm<0b1, op,
1227 (ins neon_uimm8:$Imm,
1228 neon_mov_imm_MSL_operand:$Simm),
1229 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1230 [(set (v4i32 VPR128:$Rd),
1231 (v4i32 (opnode (timm:$Imm),
1232 (neon_mov_imm_MSL_operand:$Simm))))],
1235 let cmode = {0b1, 0b1, 0b0, Simm};
1239 // Vector Move Immediate Shifted
1240 let isReMaterializable = 1 in {
1241 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1244 // Vector Move Inverted Immediate Shifted
1245 let isReMaterializable = 1 in {
1246 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1249 // Vector Bitwise Bit Clear (AND NOT) - immediate
1250 let isReMaterializable = 1 in {
1251 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1255 // Vector Bitwise OR - immedidate
1257 let isReMaterializable = 1 in {
1258 defm ORRvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1262 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1263 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1264 // BIC immediate instructions selection requires additional patterns to
1265 // transform Neon_movi operands into BIC immediate operands
1267 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1268 uint64_t OpCmode = N->getZExtValue();
1270 unsigned ShiftOnesIn;
1271 (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1272 // LSLH restricts shift amount to 0, 8 which are encoded as 0 and 1
1273 // Transform encoded shift amount 0 to 1 and 1 to 0.
1274 return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1277 def neon_mov_imm_LSLH_transform_operand
1280 unsigned ShiftOnesIn;
1282 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1283 return (HasShift && !ShiftOnesIn); }],
1284 neon_mov_imm_LSLH_transform_XFORM>;
1286 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1287 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1288 def : Pat<(v4i16 (and VPR64:$src,
1289 (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1290 (BICvi_lsl_4H VPR64:$src, 0,
1291 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1293 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1294 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1295 def : Pat<(v8i16 (and VPR128:$src,
1296 (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1297 (BICvi_lsl_8H VPR128:$src, 0,
1298 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1301 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1302 SDPatternOperator neonopnode,
1304 Instruction INST8H> {
1305 def : Pat<(v8i8 (opnode VPR64:$src,
1306 (bitconvert(v4i16 (neonopnode timm:$Imm,
1307 neon_mov_imm_LSLH_operand:$Simm))))),
1308 (INST4H VPR64:$src, neon_uimm8:$Imm,
1309 neon_mov_imm_LSLH_operand:$Simm)>;
1310 def : Pat<(v1i64 (opnode VPR64:$src,
1311 (bitconvert(v4i16 (neonopnode timm:$Imm,
1312 neon_mov_imm_LSLH_operand:$Simm))))),
1313 (INST4H VPR64:$src, neon_uimm8:$Imm,
1314 neon_mov_imm_LSLH_operand:$Simm)>;
1316 def : Pat<(v16i8 (opnode VPR128:$src,
1317 (bitconvert(v8i16 (neonopnode timm:$Imm,
1318 neon_mov_imm_LSLH_operand:$Simm))))),
1319 (INST8H VPR128:$src, neon_uimm8:$Imm,
1320 neon_mov_imm_LSLH_operand:$Simm)>;
1321 def : Pat<(v4i32 (opnode VPR128:$src,
1322 (bitconvert(v8i16 (neonopnode timm:$Imm,
1323 neon_mov_imm_LSLH_operand:$Simm))))),
1324 (INST8H VPR128:$src, neon_uimm8:$Imm,
1325 neon_mov_imm_LSLH_operand:$Simm)>;
1326 def : Pat<(v2i64 (opnode VPR128:$src,
1327 (bitconvert(v8i16 (neonopnode timm:$Imm,
1328 neon_mov_imm_LSLH_operand:$Simm))))),
1329 (INST8H VPR128:$src, neon_uimm8:$Imm,
1330 neon_mov_imm_LSLH_operand:$Simm)>;
1333 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1334 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1336 // Additional patterns for Vector Bitwise OR - immedidate
1337 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1340 // Vector Move Immediate Masked
1341 let isReMaterializable = 1 in {
1342 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1345 // Vector Move Inverted Immediate Masked
1346 let isReMaterializable = 1 in {
1347 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1350 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1351 Instruction inst, RegisterOperand VPRC>
1352 : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1353 (inst VPRC:$Rd, neon_uimm8:$Imm, 0), 0b0>;
1355 // Aliases for Vector Move Immediate Shifted
1356 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1357 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1358 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1359 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1361 // Aliases for Vector Move Inverted Immediate Shifted
1362 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1363 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1364 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1365 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1367 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1368 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1369 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1370 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1371 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1373 // Aliases for Vector Bitwise OR - immedidate
1374 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1375 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1376 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1377 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1379 // Vector Move Immediate - per byte
1380 let isReMaterializable = 1 in {
1381 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1382 (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1383 "movi\t$Rd.8b, $Imm",
1384 [(set (v8i8 VPR64:$Rd),
1385 (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1390 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1391 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1392 "movi\t$Rd.16b, $Imm",
1393 [(set (v16i8 VPR128:$Rd),
1394 (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1400 // Vector Move Immediate - bytemask, per double word
1401 let isReMaterializable = 1 in {
1402 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1403 (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1404 "movi\t $Rd.2d, $Imm",
1405 [(set (v2i64 VPR128:$Rd),
1406 (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1412 // Vector Move Immediate - bytemask, one doubleword
1414 let isReMaterializable = 1 in {
1415 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1416 (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1418 [(set (f64 FPR64:$Rd),
1420 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
1426 // Vector Floating Point Move Immediate
1428 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1429 Operand immOpType, bit q, bit op>
1430 : NeonI_1VModImm<q, op,
1431 (outs VPRC:$Rd), (ins immOpType:$Imm),
1432 "fmov\t$Rd" # asmlane # ", $Imm",
1433 [(set (OpTy VPRC:$Rd),
1434 (OpTy (Neon_fmovi (timm:$Imm))))],
1439 let isReMaterializable = 1 in {
1440 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64, v2f32, fmov32_operand, 0b0, 0b0>;
1441 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1442 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1445 // Vector Shift (Immediate)
1446 // Immediate in [0, 63]
1447 def imm0_63 : Operand<i32> {
1448 let ParserMatchClass = uimm6_asmoperand;
1451 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1455 // 8 immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1456 // 16 immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1457 // 32 immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1458 // 64 immh:immb<6> = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1460 // The shift right immediate amount, in the range 1 to element bits, is computed
1461 // as Offset - UInt(immh:immb). The shift left immediate amount, in the range 0
1462 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1464 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1465 let Name = "ShrImm" # OFFSET;
1466 let RenderMethod = "addImmOperands";
1467 let DiagnosticType = "ShrImm" # OFFSET;
1470 class shr_imm<string OFFSET> : Operand<i32> {
1471 let EncoderMethod = "getShiftRightImm" # OFFSET;
1472 let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1473 let ParserMatchClass =
1474 !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1477 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1478 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1479 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1480 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1482 def shr_imm8 : shr_imm<"8">;
1483 def shr_imm16 : shr_imm<"16">;
1484 def shr_imm32 : shr_imm<"32">;
1485 def shr_imm64 : shr_imm<"64">;
1487 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1488 let Name = "ShlImm" # OFFSET;
1489 let RenderMethod = "addImmOperands";
1490 let DiagnosticType = "ShlImm" # OFFSET;
1493 class shl_imm<string OFFSET> : Operand<i32> {
1494 let EncoderMethod = "getShiftLeftImm" # OFFSET;
1495 let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1496 let ParserMatchClass =
1497 !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1500 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1501 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1502 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1503 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1505 def shl_imm8 : shl_imm<"8">;
1506 def shl_imm16 : shl_imm<"16">;
1507 def shl_imm32 : shl_imm<"32">;
1508 def shl_imm64 : shl_imm<"64">;
1510 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1511 RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1512 : NeonI_2VShiftImm<q, u, opcode,
1513 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1514 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1515 [(set (Ty VPRC:$Rd),
1516 (Ty (OpNode (Ty VPRC:$Rn),
1517 (Ty (Neon_vdup (i32 imm:$Imm))))))],
1520 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1521 // 64-bit vector types.
1522 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3, shl> {
1523 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1526 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4, shl> {
1527 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1530 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5, shl> {
1531 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1534 // 128-bit vector types.
1535 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3, shl> {
1536 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1539 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4, shl> {
1540 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1543 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5, shl> {
1544 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1547 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63, shl> {
1548 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
1552 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1553 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1555 let Inst{22-19} = 0b0001;
1558 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1560 let Inst{22-20} = 0b001;
1563 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1565 let Inst{22-21} = 0b01;
1568 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1570 let Inst{22-19} = 0b0001;
1573 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1575 let Inst{22-20} = 0b001;
1578 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1580 let Inst{22-21} = 0b01;
1583 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1590 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1593 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1594 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1596 def Neon_High16B : PatFrag<(ops node:$in),
1597 (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1598 def Neon_High8H : PatFrag<(ops node:$in),
1599 (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1600 def Neon_High4S : PatFrag<(ops node:$in),
1601 (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1602 def Neon_High2D : PatFrag<(ops node:$in),
1603 (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1604 def Neon_High4float : PatFrag<(ops node:$in),
1605 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1606 def Neon_High2double : PatFrag<(ops node:$in),
1607 (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1609 def Neon_Low16B : PatFrag<(ops node:$in),
1610 (v8i8 (extract_subvector (v16i8 node:$in),
1612 def Neon_Low8H : PatFrag<(ops node:$in),
1613 (v4i16 (extract_subvector (v8i16 node:$in),
1615 def Neon_Low4S : PatFrag<(ops node:$in),
1616 (v2i32 (extract_subvector (v4i32 node:$in),
1618 def Neon_Low2D : PatFrag<(ops node:$in),
1619 (v1i64 (extract_subvector (v2i64 node:$in),
1621 def Neon_Low4float : PatFrag<(ops node:$in),
1622 (v2f32 (extract_subvector (v4f32 node:$in),
1624 def Neon_Low2double : PatFrag<(ops node:$in),
1625 (v1f64 (extract_subvector (v2f64 node:$in),
1628 def neon_uimm3_shift : Operand<i32>,
1629 ImmLeaf<i32, [{return Imm < 8;}]> {
1630 let ParserMatchClass = uimm3_asmoperand;
1633 def neon_uimm4_shift : Operand<i32>,
1634 ImmLeaf<i32, [{return Imm < 16;}]> {
1635 let ParserMatchClass = uimm4_asmoperand;
1638 def neon_uimm5_shift : Operand<i32>,
1639 ImmLeaf<i32, [{return Imm < 32;}]> {
1640 let ParserMatchClass = uimm5_asmoperand;
1643 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1644 string SrcT, ValueType DestTy, ValueType SrcTy,
1645 Operand ImmTy, SDPatternOperator ExtOp>
1646 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1647 (ins VPR64:$Rn, ImmTy:$Imm),
1648 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1649 [(set (DestTy VPR128:$Rd),
1651 (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1652 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1655 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1656 string SrcT, ValueType DestTy, ValueType SrcTy,
1657 int StartIndex, Operand ImmTy,
1658 SDPatternOperator ExtOp, PatFrag getTop>
1659 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1660 (ins VPR128:$Rn, ImmTy:$Imm),
1661 asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1662 [(set (DestTy VPR128:$Rd),
1665 (SrcTy (getTop VPR128:$Rn)))),
1666 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1669 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1671 // 64-bit vector types.
1672 def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1673 neon_uimm3_shift, ExtOp> {
1674 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1677 def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1678 neon_uimm4_shift, ExtOp> {
1679 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1682 def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1683 neon_uimm5_shift, ExtOp> {
1684 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1687 // 128-bit vector types
1688 def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1689 8, neon_uimm3_shift, ExtOp, Neon_High16B> {
1690 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1693 def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1694 4, neon_uimm4_shift, ExtOp, Neon_High8H> {
1695 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1698 def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1699 2, neon_uimm5_shift, ExtOp, Neon_High4S> {
1700 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1703 // Use other patterns to match when the immediate is 0.
1704 def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1705 (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1707 def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1708 (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1710 def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1711 (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1713 def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1714 (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1716 def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1717 (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1719 def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1720 (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1724 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1725 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1727 // Rounding/Saturating shift
1728 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1729 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1730 SDPatternOperator OpNode>
1731 : NeonI_2VShiftImm<q, u, opcode,
1732 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1733 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1734 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1738 // shift right (vector by immediate)
1739 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1740 SDPatternOperator OpNode> {
1741 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1743 let Inst{22-19} = 0b0001;
1746 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1748 let Inst{22-20} = 0b001;
1751 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1753 let Inst{22-21} = 0b01;
1756 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1758 let Inst{22-19} = 0b0001;
1761 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1763 let Inst{22-20} = 0b001;
1766 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1768 let Inst{22-21} = 0b01;
1771 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1777 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1778 SDPatternOperator OpNode> {
1779 // 64-bit vector types.
1780 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1782 let Inst{22-19} = 0b0001;
1785 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1787 let Inst{22-20} = 0b001;
1790 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1792 let Inst{22-21} = 0b01;
1795 // 128-bit vector types.
1796 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1798 let Inst{22-19} = 0b0001;
1801 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1803 let Inst{22-20} = 0b001;
1806 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1808 let Inst{22-21} = 0b01;
1811 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1817 // Rounding shift right
1818 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1819 int_aarch64_neon_vsrshr>;
1820 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1821 int_aarch64_neon_vurshr>;
1823 // Saturating shift left unsigned
1824 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1826 // Saturating shift left
1827 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1828 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1830 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1831 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1833 : NeonI_2VShiftImm<q, u, opcode,
1834 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1835 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1836 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1837 (Ty (OpNode (Ty VPRC:$Rn),
1838 (Ty (Neon_vdup (i32 imm:$Imm))))))))],
1840 let Constraints = "$src = $Rd";
1843 // Shift Right accumulate
1844 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1845 def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1847 let Inst{22-19} = 0b0001;
1850 def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1852 let Inst{22-20} = 0b001;
1855 def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1857 let Inst{22-21} = 0b01;
1860 def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1862 let Inst{22-19} = 0b0001;
1865 def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1867 let Inst{22-20} = 0b001;
1870 def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1872 let Inst{22-21} = 0b01;
1875 def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1881 // Shift right and accumulate
1882 defm SSRAvvi : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1883 defm USRAvvi : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1885 // Rounding shift accumulate
1886 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1887 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1888 SDPatternOperator OpNode>
1889 : NeonI_2VShiftImm<q, u, opcode,
1890 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1891 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1892 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1893 (Ty (OpNode (Ty VPRC:$Rn), (i32 imm:$Imm))))))],
1895 let Constraints = "$src = $Rd";
1898 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1899 SDPatternOperator OpNode> {
1900 def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1902 let Inst{22-19} = 0b0001;
1905 def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1907 let Inst{22-20} = 0b001;
1910 def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1912 let Inst{22-21} = 0b01;
1915 def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1917 let Inst{22-19} = 0b0001;
1920 def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1922 let Inst{22-20} = 0b001;
1925 def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1927 let Inst{22-21} = 0b01;
1930 def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1936 // Rounding shift right and accumulate
1937 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1938 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1940 // Shift insert by immediate
1941 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1942 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1943 SDPatternOperator OpNode>
1944 : NeonI_2VShiftImm<q, u, opcode,
1945 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1946 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1947 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1950 let Constraints = "$src = $Rd";
1953 // shift left insert (vector by immediate)
1954 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1955 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1956 int_aarch64_neon_vsli> {
1957 let Inst{22-19} = 0b0001;
1960 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1961 int_aarch64_neon_vsli> {
1962 let Inst{22-20} = 0b001;
1965 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1966 int_aarch64_neon_vsli> {
1967 let Inst{22-21} = 0b01;
1970 // 128-bit vector types
1971 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1972 int_aarch64_neon_vsli> {
1973 let Inst{22-19} = 0b0001;
1976 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1977 int_aarch64_neon_vsli> {
1978 let Inst{22-20} = 0b001;
1981 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1982 int_aarch64_neon_vsli> {
1983 let Inst{22-21} = 0b01;
1986 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1987 int_aarch64_neon_vsli> {
1992 // shift right insert (vector by immediate)
1993 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
1994 // 64-bit vector types.
1995 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1996 int_aarch64_neon_vsri> {
1997 let Inst{22-19} = 0b0001;
2000 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2001 int_aarch64_neon_vsri> {
2002 let Inst{22-20} = 0b001;
2005 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2006 int_aarch64_neon_vsri> {
2007 let Inst{22-21} = 0b01;
2010 // 128-bit vector types
2011 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2012 int_aarch64_neon_vsri> {
2013 let Inst{22-19} = 0b0001;
2016 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2017 int_aarch64_neon_vsri> {
2018 let Inst{22-20} = 0b001;
2021 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2022 int_aarch64_neon_vsri> {
2023 let Inst{22-21} = 0b01;
2026 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2027 int_aarch64_neon_vsri> {
2032 // Shift left and insert
2033 defm SLIvvi : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2035 // Shift right and insert
2036 defm SRIvvi : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2038 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2039 string SrcT, Operand ImmTy>
2040 : NeonI_2VShiftImm<q, u, opcode,
2041 (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2042 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2045 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2046 string SrcT, Operand ImmTy>
2047 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2048 (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2049 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2051 let Constraints = "$src = $Rd";
2054 // left long shift by immediate
2055 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2056 def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2057 let Inst{22-19} = 0b0001;
2060 def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2061 let Inst{22-20} = 0b001;
2064 def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2065 let Inst{22-21} = 0b01;
2068 // Shift Narrow High
2069 def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2071 let Inst{22-19} = 0b0001;
2074 def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2076 let Inst{22-20} = 0b001;
2079 def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2081 let Inst{22-21} = 0b01;
2085 // Shift right narrow
2086 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2088 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2089 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2090 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2091 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2092 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2093 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2094 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2095 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2097 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2098 (v2i64 (concat_vectors (v1i64 node:$Rm),
2099 (v1i64 node:$Rn)))>;
2100 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2101 (v8i16 (concat_vectors (v4i16 node:$Rm),
2102 (v4i16 node:$Rn)))>;
2103 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2104 (v4i32 (concat_vectors (v2i32 node:$Rm),
2105 (v2i32 node:$Rn)))>;
2106 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2107 (v4f32 (concat_vectors (v2f32 node:$Rm),
2108 (v2f32 node:$Rn)))>;
2109 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2110 (v2f64 (concat_vectors (v1f64 node:$Rm),
2111 (v1f64 node:$Rn)))>;
2113 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2114 (v8i16 (srl (v8i16 node:$lhs),
2115 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2116 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2117 (v4i32 (srl (v4i32 node:$lhs),
2118 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2119 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2120 (v2i64 (srl (v2i64 node:$lhs),
2121 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2122 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2123 (v8i16 (sra (v8i16 node:$lhs),
2124 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2125 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2126 (v4i32 (sra (v4i32 node:$lhs),
2127 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2128 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2129 (v2i64 (sra (v2i64 node:$lhs),
2130 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2132 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2133 multiclass Neon_shiftNarrow_patterns<string shr> {
2134 def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2136 (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2137 def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2139 (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2140 def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2142 (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2144 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2145 (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2146 VPR128:$Rn, (i32 imm:$Imm))))))),
2147 (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2148 VPR128:$Rn, imm:$Imm)>;
2149 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2150 (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2151 VPR128:$Rn, (i32 imm:$Imm))))))),
2152 (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2153 VPR128:$Rn, imm:$Imm)>;
2154 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2155 (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2156 VPR128:$Rn, (i32 imm:$Imm))))))),
2157 (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2158 VPR128:$Rn, imm:$Imm)>;
2161 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2162 def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm)),
2163 (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2164 def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm)),
2165 (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2166 def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm)),
2167 (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2169 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2170 (v1i64 (bitconvert (v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm))))),
2171 (!cast<Instruction>(prefix # "_16B")
2172 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2173 VPR128:$Rn, imm:$Imm)>;
2174 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2175 (v1i64 (bitconvert (v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm))))),
2176 (!cast<Instruction>(prefix # "_8H")
2177 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2178 VPR128:$Rn, imm:$Imm)>;
2179 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2180 (v1i64 (bitconvert (v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm))))),
2181 (!cast<Instruction>(prefix # "_4S")
2182 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2183 VPR128:$Rn, imm:$Imm)>;
2186 defm : Neon_shiftNarrow_patterns<"lshr">;
2187 defm : Neon_shiftNarrow_patterns<"ashr">;
2189 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2190 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2191 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2192 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2193 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2194 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2195 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2197 // Convert fix-point and float-pointing
2198 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2199 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2200 Operand ImmTy, SDPatternOperator IntOp>
2201 : NeonI_2VShiftImm<q, u, opcode,
2202 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2203 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2204 [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2208 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2209 SDPatternOperator IntOp> {
2210 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2212 let Inst{22-21} = 0b01;
2215 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2217 let Inst{22-21} = 0b01;
2220 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2226 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2227 SDPatternOperator IntOp> {
2228 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2230 let Inst{22-21} = 0b01;
2233 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2235 let Inst{22-21} = 0b01;
2238 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2244 // Convert fixed-point to floating-point
2245 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2246 int_arm_neon_vcvtfxs2fp>;
2247 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2248 int_arm_neon_vcvtfxu2fp>;
2250 // Convert floating-point to fixed-point
2251 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2252 int_arm_neon_vcvtfp2fxs>;
2253 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2254 int_arm_neon_vcvtfp2fxu>;
2256 multiclass Neon_sshll2_0<SDNode ext>
2258 def _v8i8 : PatFrag<(ops node:$Rn),
2259 (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2260 def _v4i16 : PatFrag<(ops node:$Rn),
2261 (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2262 def _v2i32 : PatFrag<(ops node:$Rn),
2263 (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2266 defm NI_sext_high : Neon_sshll2_0<sext>;
2267 defm NI_zext_high : Neon_sshll2_0<zext>;
2270 //===----------------------------------------------------------------------===//
2271 // Multiclasses for NeonI_Across
2272 //===----------------------------------------------------------------------===//
2276 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2277 string asmop, SDPatternOperator opnode>
2279 def _1h8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2280 (outs FPR16:$Rd), (ins VPR64:$Rn),
2281 asmop # "\t$Rd, $Rn.8b",
2282 [(set (v1i16 FPR16:$Rd),
2283 (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2286 def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2287 (outs FPR16:$Rd), (ins VPR128:$Rn),
2288 asmop # "\t$Rd, $Rn.16b",
2289 [(set (v1i16 FPR16:$Rd),
2290 (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2293 def _1s4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2294 (outs FPR32:$Rd), (ins VPR64:$Rn),
2295 asmop # "\t$Rd, $Rn.4h",
2296 [(set (v1i32 FPR32:$Rd),
2297 (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2300 def _1s8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2301 (outs FPR32:$Rd), (ins VPR128:$Rn),
2302 asmop # "\t$Rd, $Rn.8h",
2303 [(set (v1i32 FPR32:$Rd),
2304 (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2307 // _1d2s doesn't exist!
2309 def _1d4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2310 (outs FPR64:$Rd), (ins VPR128:$Rn),
2311 asmop # "\t$Rd, $Rn.4s",
2312 [(set (v1i64 FPR64:$Rd),
2313 (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2317 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2318 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2322 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2323 string asmop, SDPatternOperator opnode>
2325 def _1b8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2326 (outs FPR8:$Rd), (ins VPR64:$Rn),
2327 asmop # "\t$Rd, $Rn.8b",
2328 [(set (v1i8 FPR8:$Rd),
2329 (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2332 def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2333 (outs FPR8:$Rd), (ins VPR128:$Rn),
2334 asmop # "\t$Rd, $Rn.16b",
2335 [(set (v1i8 FPR8:$Rd),
2336 (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2339 def _1h4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2340 (outs FPR16:$Rd), (ins VPR64:$Rn),
2341 asmop # "\t$Rd, $Rn.4h",
2342 [(set (v1i16 FPR16:$Rd),
2343 (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2346 def _1h8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2347 (outs FPR16:$Rd), (ins VPR128:$Rn),
2348 asmop # "\t$Rd, $Rn.8h",
2349 [(set (v1i16 FPR16:$Rd),
2350 (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2353 // _1s2s doesn't exist!
2355 def _1s4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2356 (outs FPR32:$Rd), (ins VPR128:$Rn),
2357 asmop # "\t$Rd, $Rn.4s",
2358 [(set (v1i32 FPR32:$Rd),
2359 (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2363 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2364 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2366 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2367 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2369 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2373 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2374 string asmop, SDPatternOperator opnode> {
2375 def _1s4s: NeonI_2VAcross<0b1, u, size, opcode,
2376 (outs FPR32:$Rd), (ins VPR128:$Rn),
2377 asmop # "\t$Rd, $Rn.4s",
2378 [(set (v1f32 FPR32:$Rd),
2379 (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2383 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2384 int_aarch64_neon_vmaxnmv>;
2385 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2386 int_aarch64_neon_vminnmv>;
2388 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2389 int_aarch64_neon_vmaxv>;
2390 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2391 int_aarch64_neon_vminv>;
2393 // The followings are for instruction class (Perm)
2395 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2396 string asmop, RegisterOperand OpVPR, string OpS,
2397 SDPatternOperator opnode, ValueType Ty>
2398 : NeonI_Perm<q, size, opcode,
2399 (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2400 asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2401 [(set (Ty OpVPR:$Rd),
2402 (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2405 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2406 SDPatternOperator opnode> {
2407 def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop,
2408 VPR64, "8b", opnode, v8i8>;
2409 def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2410 VPR128, "16b",opnode, v16i8>;
2411 def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop,
2412 VPR64, "4h", opnode, v4i16>;
2413 def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop,
2414 VPR128, "8h", opnode, v8i16>;
2415 def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop,
2416 VPR64, "2s", opnode, v2i32>;
2417 def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop,
2418 VPR128, "4s", opnode, v4i32>;
2419 def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop,
2420 VPR128, "2d", opnode, v2i64>;
2423 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2424 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2425 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2426 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2427 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2428 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2430 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2431 def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2432 (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2434 def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2435 (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2437 def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2438 (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2441 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2442 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2443 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2444 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2445 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2446 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2448 // The followings are for instruction class (3V Diff)
2450 // normal long/long2 pattern
2451 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2452 string asmop, string ResS, string OpS,
2453 SDPatternOperator opnode, SDPatternOperator ext,
2454 RegisterOperand OpVPR,
2455 ValueType ResTy, ValueType OpTy>
2456 : NeonI_3VDiff<q, u, size, opcode,
2457 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2458 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2459 [(set (ResTy VPR128:$Rd),
2460 (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2461 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2464 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2465 string asmop, SDPatternOperator opnode,
2466 bit Commutable = 0> {
2467 let isCommutable = Commutable in {
2468 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2469 opnode, sext, VPR64, v8i16, v8i8>;
2470 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2471 opnode, sext, VPR64, v4i32, v4i16>;
2472 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2473 opnode, sext, VPR64, v2i64, v2i32>;
2477 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2478 SDPatternOperator opnode, bit Commutable = 0> {
2479 let isCommutable = Commutable in {
2480 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2481 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2482 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2483 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2484 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2485 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2489 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2490 SDPatternOperator opnode, bit Commutable = 0> {
2491 let isCommutable = Commutable in {
2492 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2493 opnode, zext, VPR64, v8i16, v8i8>;
2494 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2495 opnode, zext, VPR64, v4i32, v4i16>;
2496 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2497 opnode, zext, VPR64, v2i64, v2i32>;
2501 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2502 SDPatternOperator opnode, bit Commutable = 0> {
2503 let isCommutable = Commutable in {
2504 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2505 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2506 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2507 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2508 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2509 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2513 defm SADDLvvv : NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2514 defm UADDLvvv : NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2516 defm SADDL2vvv : NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2517 defm UADDL2vvv : NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2519 defm SSUBLvvv : NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2520 defm USUBLvvv : NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2522 defm SSUBL2vvv : NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2523 defm USUBL2vvv : NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2525 // normal wide/wide2 pattern
2526 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2527 string asmop, string ResS, string OpS,
2528 SDPatternOperator opnode, SDPatternOperator ext,
2529 RegisterOperand OpVPR,
2530 ValueType ResTy, ValueType OpTy>
2531 : NeonI_3VDiff<q, u, size, opcode,
2532 (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2533 asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2534 [(set (ResTy VPR128:$Rd),
2535 (ResTy (opnode (ResTy VPR128:$Rn),
2536 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2539 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2540 SDPatternOperator opnode> {
2541 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2542 opnode, sext, VPR64, v8i16, v8i8>;
2543 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2544 opnode, sext, VPR64, v4i32, v4i16>;
2545 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2546 opnode, sext, VPR64, v2i64, v2i32>;
2549 defm SADDWvvv : NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2550 defm SSUBWvvv : NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2552 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2553 SDPatternOperator opnode> {
2554 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2555 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2556 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2557 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2558 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2559 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2562 defm SADDW2vvv : NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2563 defm SSUBW2vvv : NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2565 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2566 SDPatternOperator opnode> {
2567 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2568 opnode, zext, VPR64, v8i16, v8i8>;
2569 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2570 opnode, zext, VPR64, v4i32, v4i16>;
2571 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2572 opnode, zext, VPR64, v2i64, v2i32>;
2575 defm UADDWvvv : NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2576 defm USUBWvvv : NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2578 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2579 SDPatternOperator opnode> {
2580 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2581 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2582 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2583 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2584 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2585 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2588 defm UADDW2vvv : NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2589 defm USUBW2vvv : NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2591 // Get the high half part of the vector element.
2592 multiclass NeonI_get_high {
2593 def _8h : PatFrag<(ops node:$Rn),
2594 (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2595 (v8i16 (Neon_vdup (i32 8)))))))>;
2596 def _4s : PatFrag<(ops node:$Rn),
2597 (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2598 (v4i32 (Neon_vdup (i32 16)))))))>;
2599 def _2d : PatFrag<(ops node:$Rn),
2600 (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2601 (v2i64 (Neon_vdup (i32 32)))))))>;
2604 defm NI_get_hi : NeonI_get_high;
2606 // pattern for addhn/subhn with 2 operands
2607 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2608 string asmop, string ResS, string OpS,
2609 SDPatternOperator opnode, SDPatternOperator get_hi,
2610 ValueType ResTy, ValueType OpTy>
2611 : NeonI_3VDiff<q, u, size, opcode,
2612 (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2613 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2614 [(set (ResTy VPR64:$Rd),
2616 (OpTy (opnode (OpTy VPR128:$Rn),
2617 (OpTy VPR128:$Rm))))))],
2620 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2621 SDPatternOperator opnode, bit Commutable = 0> {
2622 let isCommutable = Commutable in {
2623 def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2624 opnode, NI_get_hi_8h, v8i8, v8i16>;
2625 def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2626 opnode, NI_get_hi_4s, v4i16, v4i32>;
2627 def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2628 opnode, NI_get_hi_2d, v2i32, v2i64>;
2632 defm ADDHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2633 defm SUBHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2635 // pattern for operation with 2 operands
2636 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2637 string asmop, string ResS, string OpS,
2638 SDPatternOperator opnode,
2639 RegisterOperand ResVPR, RegisterOperand OpVPR,
2640 ValueType ResTy, ValueType OpTy>
2641 : NeonI_3VDiff<q, u, size, opcode,
2642 (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2643 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2644 [(set (ResTy ResVPR:$Rd),
2645 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2648 // normal narrow pattern
2649 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2650 SDPatternOperator opnode, bit Commutable = 0> {
2651 let isCommutable = Commutable in {
2652 def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2653 opnode, VPR64, VPR128, v8i8, v8i16>;
2654 def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2655 opnode, VPR64, VPR128, v4i16, v4i32>;
2656 def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2657 opnode, VPR64, VPR128, v2i32, v2i64>;
2661 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2662 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2664 // pattern for acle intrinsic with 3 operands
2665 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2666 string asmop, string ResS, string OpS>
2667 : NeonI_3VDiff<q, u, size, opcode,
2668 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2669 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2671 let Constraints = "$src = $Rd";
2672 let neverHasSideEffects = 1;
2675 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2676 def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2677 def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2678 def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2681 defm ADDHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2682 defm SUBHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2684 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2685 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2687 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2689 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2690 SDPatternOperator coreop>
2691 : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2692 (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2693 (SrcTy VPR128:$Rm)))))),
2694 (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2695 VPR128:$Rn, VPR128:$Rm)>;
2698 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8, v8i16,
2699 BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2700 def : NarrowHighHalfPat<ADDHN2vvv_8h4s, v4i16, v4i32,
2701 BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2702 def : NarrowHighHalfPat<ADDHN2vvv_4s2d, v2i32, v2i64,
2703 BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2706 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8, v8i16,
2707 BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2708 def : NarrowHighHalfPat<SUBHN2vvv_8h4s, v4i16, v4i32,
2709 BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2710 def : NarrowHighHalfPat<SUBHN2vvv_4s2d, v2i32, v2i64,
2711 BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2714 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vraddhn>;
2715 def : NarrowHighHalfPat<RADDHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vraddhn>;
2716 def : NarrowHighHalfPat<RADDHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vraddhn>;
2719 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vrsubhn>;
2720 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vrsubhn>;
2721 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vrsubhn>;
2723 // pattern that need to extend result
2724 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2725 string asmop, string ResS, string OpS,
2726 SDPatternOperator opnode,
2727 RegisterOperand OpVPR,
2728 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2729 : NeonI_3VDiff<q, u, size, opcode,
2730 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2731 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2732 [(set (ResTy VPR128:$Rd),
2733 (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2734 (OpTy OpVPR:$Rm))))))],
2737 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2738 SDPatternOperator opnode, bit Commutable = 0> {
2739 let isCommutable = Commutable in {
2740 def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2741 opnode, VPR64, v8i16, v8i8, v8i8>;
2742 def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2743 opnode, VPR64, v4i32, v4i16, v4i16>;
2744 def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2745 opnode, VPR64, v2i64, v2i32, v2i32>;
2749 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2750 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2752 multiclass NeonI_Op_High<SDPatternOperator op> {
2753 def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2754 (op (v8i8 (Neon_High16B node:$Rn)),
2755 (v8i8 (Neon_High16B node:$Rm)))>;
2756 def _8H : PatFrag<(ops node:$Rn, node:$Rm),
2757 (op (v4i16 (Neon_High8H node:$Rn)),
2758 (v4i16 (Neon_High8H node:$Rm)))>;
2759 def _4S : PatFrag<(ops node:$Rn, node:$Rm),
2760 (op (v2i32 (Neon_High4S node:$Rn)),
2761 (v2i32 (Neon_High4S node:$Rm)))>;
2764 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2765 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2766 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2767 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2768 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2769 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2771 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2772 bit Commutable = 0> {
2773 let isCommutable = Commutable in {
2774 def _8h8b : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2775 !cast<PatFrag>(opnode # "_16B"),
2776 VPR128, v8i16, v16i8, v8i8>;
2777 def _4s4h : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2778 !cast<PatFrag>(opnode # "_8H"),
2779 VPR128, v4i32, v8i16, v4i16>;
2780 def _2d2s : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2781 !cast<PatFrag>(opnode # "_4S"),
2782 VPR128, v2i64, v4i32, v2i32>;
2786 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2787 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2789 // For pattern that need two operators being chained.
2790 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2791 string asmop, string ResS, string OpS,
2792 SDPatternOperator opnode, SDPatternOperator subop,
2793 RegisterOperand OpVPR,
2794 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2795 : NeonI_3VDiff<q, u, size, opcode,
2796 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2797 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2798 [(set (ResTy VPR128:$Rd),
2800 (ResTy VPR128:$src),
2801 (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2802 (OpTy OpVPR:$Rm))))))))],
2804 let Constraints = "$src = $Rd";
2807 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2808 SDPatternOperator opnode, SDPatternOperator subop>{
2809 def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2810 opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2811 def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2812 opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2813 def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2814 opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2817 defm SABALvvv : NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2818 add, int_arm_neon_vabds>;
2819 defm UABALvvv : NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2820 add, int_arm_neon_vabdu>;
2822 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2823 SDPatternOperator opnode, string subop> {
2824 def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2825 opnode, !cast<PatFrag>(subop # "_16B"),
2826 VPR128, v8i16, v16i8, v8i8>;
2827 def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2828 opnode, !cast<PatFrag>(subop # "_8H"),
2829 VPR128, v4i32, v8i16, v4i16>;
2830 def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2831 opnode, !cast<PatFrag>(subop # "_4S"),
2832 VPR128, v2i64, v4i32, v2i32>;
2835 defm SABAL2vvv : NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2837 defm UABAL2vvv : NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2840 // Long pattern with 2 operands
2841 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2842 SDPatternOperator opnode, bit Commutable = 0> {
2843 let isCommutable = Commutable in {
2844 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2845 opnode, VPR128, VPR64, v8i16, v8i8>;
2846 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2847 opnode, VPR128, VPR64, v4i32, v4i16>;
2848 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2849 opnode, VPR128, VPR64, v2i64, v2i32>;
2853 defm SMULLvvv : NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2854 defm UMULLvvv : NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2856 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2857 string asmop, string ResS, string OpS,
2858 SDPatternOperator opnode,
2859 ValueType ResTy, ValueType OpTy>
2860 : NeonI_3VDiff<q, u, size, opcode,
2861 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2862 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2863 [(set (ResTy VPR128:$Rd),
2864 (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2867 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
2868 string opnode, bit Commutable = 0> {
2869 let isCommutable = Commutable in {
2870 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2871 !cast<PatFrag>(opnode # "_16B"),
2873 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2874 !cast<PatFrag>(opnode # "_8H"),
2876 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2877 !cast<PatFrag>(opnode # "_4S"),
2882 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2884 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2887 // Long pattern with 3 operands
2888 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2889 string asmop, string ResS, string OpS,
2890 SDPatternOperator opnode,
2891 ValueType ResTy, ValueType OpTy>
2892 : NeonI_3VDiff<q, u, size, opcode,
2893 (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2894 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2895 [(set (ResTy VPR128:$Rd),
2897 (ResTy VPR128:$src),
2898 (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2900 let Constraints = "$src = $Rd";
2903 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
2904 SDPatternOperator opnode> {
2905 def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2906 opnode, v8i16, v8i8>;
2907 def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2908 opnode, v4i32, v4i16>;
2909 def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2910 opnode, v2i64, v2i32>;
2913 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2915 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2917 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2919 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2921 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2923 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2925 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2927 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2929 defm SMLALvvv : NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2930 defm UMLALvvv : NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2932 defm SMLSLvvv : NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2933 defm UMLSLvvv : NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2935 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2936 string asmop, string ResS, string OpS,
2937 SDPatternOperator subop, SDPatternOperator opnode,
2938 RegisterOperand OpVPR,
2939 ValueType ResTy, ValueType OpTy>
2940 : NeonI_3VDiff<q, u, size, opcode,
2941 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2942 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2943 [(set (ResTy VPR128:$Rd),
2945 (ResTy VPR128:$src),
2946 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2948 let Constraints = "$src = $Rd";
2951 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
2952 SDPatternOperator subop, string opnode> {
2953 def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2954 subop, !cast<PatFrag>(opnode # "_16B"),
2955 VPR128, v8i16, v16i8>;
2956 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2957 subop, !cast<PatFrag>(opnode # "_8H"),
2958 VPR128, v4i32, v8i16>;
2959 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2960 subop, !cast<PatFrag>(opnode # "_4S"),
2961 VPR128, v2i64, v4i32>;
2964 defm SMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2965 add, "NI_smull_hi">;
2966 defm UMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2967 add, "NI_umull_hi">;
2969 defm SMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2970 sub, "NI_smull_hi">;
2971 defm UMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2972 sub, "NI_umull_hi">;
2974 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
2975 SDPatternOperator opnode> {
2976 def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2977 opnode, int_arm_neon_vqdmull,
2978 VPR64, v4i32, v4i16>;
2979 def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2980 opnode, int_arm_neon_vqdmull,
2981 VPR64, v2i64, v2i32>;
2984 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2985 int_arm_neon_vqadds>;
2986 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2987 int_arm_neon_vqsubs>;
2989 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
2990 SDPatternOperator opnode, bit Commutable = 0> {
2991 let isCommutable = Commutable in {
2992 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2993 opnode, VPR128, VPR64, v4i32, v4i16>;
2994 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2995 opnode, VPR128, VPR64, v2i64, v2i32>;
2999 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3000 int_arm_neon_vqdmull, 1>;
3002 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3003 string opnode, bit Commutable = 0> {
3004 let isCommutable = Commutable in {
3005 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3006 !cast<PatFrag>(opnode # "_8H"),
3008 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3009 !cast<PatFrag>(opnode # "_4S"),
3014 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3017 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3018 SDPatternOperator opnode> {
3019 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3020 opnode, NI_qdmull_hi_8H,
3021 VPR128, v4i32, v8i16>;
3022 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3023 opnode, NI_qdmull_hi_4S,
3024 VPR128, v2i64, v4i32>;
3027 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3028 int_arm_neon_vqadds>;
3029 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3030 int_arm_neon_vqsubs>;
3032 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3033 SDPatternOperator opnode, bit Commutable = 0> {
3034 let isCommutable = Commutable in {
3035 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3036 opnode, VPR128, VPR64, v8i16, v8i8>;
3038 def _1q1d : NeonI_3VDiff<0b0, u, 0b11, opcode,
3039 (outs VPR128:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
3040 asmop # "\t$Rd.1q, $Rn.1d, $Rm.1d",
3045 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
3047 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3048 string opnode, bit Commutable = 0> {
3049 let isCommutable = Commutable in {
3050 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3051 !cast<PatFrag>(opnode # "_16B"),
3054 def _1q2d : NeonI_3VDiff<0b1, u, 0b11, opcode,
3055 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3056 asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3061 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3064 // End of implementation for instruction class (3V Diff)
3066 // The followings are vector load/store multiple N-element structure
3067 // (class SIMD lselem).
3069 // ld1: load multiple 1-element structure to 1/2/3/4 registers.
3070 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3071 // The structure consists of a sequence of sets of N values.
3072 // The first element of the structure is placed in the first lane
3073 // of the first first vector, the second element in the first lane
3074 // of the second vector, and so on.
3075 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3076 // the three 64-bit vectors list {BA, DC, FE}.
3077 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3078 // 64-bit vectors list {DA, EB, FC}.
3079 // Store instructions store multiple structure to N registers like load.
3082 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3083 RegisterOperand VecList, string asmop>
3084 : NeonI_LdStMult<q, 1, opcode, size,
3085 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3086 asmop # "\t$Rt, [$Rn]",
3090 let neverHasSideEffects = 1;
3093 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3094 def _8B : NeonI_LDVList<0, opcode, 0b00,
3095 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3097 def _4H : NeonI_LDVList<0, opcode, 0b01,
3098 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3100 def _2S : NeonI_LDVList<0, opcode, 0b10,
3101 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3103 def _16B : NeonI_LDVList<1, opcode, 0b00,
3104 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3106 def _8H : NeonI_LDVList<1, opcode, 0b01,
3107 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3109 def _4S : NeonI_LDVList<1, opcode, 0b10,
3110 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3112 def _2D : NeonI_LDVList<1, opcode, 0b11,
3113 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3116 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3117 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3118 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3120 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3122 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3124 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3126 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3127 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3128 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3130 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3131 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3133 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3134 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3136 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3137 RegisterOperand VecList, string asmop>
3138 : NeonI_LdStMult<q, 0, opcode, size,
3139 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3140 asmop # "\t$Rt, [$Rn]",
3144 let neverHasSideEffects = 1;
3147 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3148 def _8B : NeonI_STVList<0, opcode, 0b00,
3149 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3151 def _4H : NeonI_STVList<0, opcode, 0b01,
3152 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3154 def _2S : NeonI_STVList<0, opcode, 0b10,
3155 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3157 def _16B : NeonI_STVList<1, opcode, 0b00,
3158 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3160 def _8H : NeonI_STVList<1, opcode, 0b01,
3161 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3163 def _4S : NeonI_STVList<1, opcode, 0b10,
3164 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3166 def _2D : NeonI_STVList<1, opcode, 0b11,
3167 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3170 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3171 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3172 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3174 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3176 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3178 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3180 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3181 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3182 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3184 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3185 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3187 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3188 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3190 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3191 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3193 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3194 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3196 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3197 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3199 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3200 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3202 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3203 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3205 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3206 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3208 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3209 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3210 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3211 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3213 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3214 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3215 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3216 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3218 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3219 (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3220 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3221 (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3223 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3224 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3225 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3226 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3228 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3229 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3230 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3231 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3233 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3234 (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3235 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3236 (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3238 // End of vector load/store multiple N-element structure(class SIMD lselem)
3240 // The followings are post-index vector load/store multiple N-element
3241 // structure(class SIMD lselem-post)
3242 def exact1_asmoperand : AsmOperandClass {
3243 let Name = "Exact1";
3244 let PredicateMethod = "isExactImm<1>";
3245 let RenderMethod = "addImmOperands";
3247 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3248 let ParserMatchClass = exact1_asmoperand;
3251 def exact2_asmoperand : AsmOperandClass {
3252 let Name = "Exact2";
3253 let PredicateMethod = "isExactImm<2>";
3254 let RenderMethod = "addImmOperands";
3256 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3257 let ParserMatchClass = exact2_asmoperand;
3260 def exact3_asmoperand : AsmOperandClass {
3261 let Name = "Exact3";
3262 let PredicateMethod = "isExactImm<3>";
3263 let RenderMethod = "addImmOperands";
3265 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3266 let ParserMatchClass = exact3_asmoperand;
3269 def exact4_asmoperand : AsmOperandClass {
3270 let Name = "Exact4";
3271 let PredicateMethod = "isExactImm<4>";
3272 let RenderMethod = "addImmOperands";
3274 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3275 let ParserMatchClass = exact4_asmoperand;
3278 def exact6_asmoperand : AsmOperandClass {
3279 let Name = "Exact6";
3280 let PredicateMethod = "isExactImm<6>";
3281 let RenderMethod = "addImmOperands";
3283 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3284 let ParserMatchClass = exact6_asmoperand;
3287 def exact8_asmoperand : AsmOperandClass {
3288 let Name = "Exact8";
3289 let PredicateMethod = "isExactImm<8>";
3290 let RenderMethod = "addImmOperands";
3292 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3293 let ParserMatchClass = exact8_asmoperand;
3296 def exact12_asmoperand : AsmOperandClass {
3297 let Name = "Exact12";
3298 let PredicateMethod = "isExactImm<12>";
3299 let RenderMethod = "addImmOperands";
3301 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3302 let ParserMatchClass = exact12_asmoperand;
3305 def exact16_asmoperand : AsmOperandClass {
3306 let Name = "Exact16";
3307 let PredicateMethod = "isExactImm<16>";
3308 let RenderMethod = "addImmOperands";
3310 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3311 let ParserMatchClass = exact16_asmoperand;
3314 def exact24_asmoperand : AsmOperandClass {
3315 let Name = "Exact24";
3316 let PredicateMethod = "isExactImm<24>";
3317 let RenderMethod = "addImmOperands";
3319 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3320 let ParserMatchClass = exact24_asmoperand;
3323 def exact32_asmoperand : AsmOperandClass {
3324 let Name = "Exact32";
3325 let PredicateMethod = "isExactImm<32>";
3326 let RenderMethod = "addImmOperands";
3328 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3329 let ParserMatchClass = exact32_asmoperand;
3332 def exact48_asmoperand : AsmOperandClass {
3333 let Name = "Exact48";
3334 let PredicateMethod = "isExactImm<48>";
3335 let RenderMethod = "addImmOperands";
3337 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3338 let ParserMatchClass = exact48_asmoperand;
3341 def exact64_asmoperand : AsmOperandClass {
3342 let Name = "Exact64";
3343 let PredicateMethod = "isExactImm<64>";
3344 let RenderMethod = "addImmOperands";
3346 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3347 let ParserMatchClass = exact64_asmoperand;
3350 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3351 RegisterOperand VecList, Operand ImmTy,
3353 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3354 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3355 def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3356 (outs VecList:$Rt, GPR64xsp:$wb),
3357 (ins GPR64xsp:$Rn, ImmTy:$amt),
3358 asmop # "\t$Rt, [$Rn], $amt",
3364 def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3365 (outs VecList:$Rt, GPR64xsp:$wb),
3366 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3367 asmop # "\t$Rt, [$Rn], $Rm",
3373 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3374 Operand ImmTy2, string asmop> {
3375 defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3376 !cast<RegisterOperand>(List # "8B_operand"),
3379 defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3380 !cast<RegisterOperand>(List # "4H_operand"),
3383 defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3384 !cast<RegisterOperand>(List # "2S_operand"),
3387 defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3388 !cast<RegisterOperand>(List # "16B_operand"),
3391 defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3392 !cast<RegisterOperand>(List # "8H_operand"),
3395 defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3396 !cast<RegisterOperand>(List # "4S_operand"),
3399 defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3400 !cast<RegisterOperand>(List # "2D_operand"),
3404 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3405 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3406 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3409 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3411 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3414 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3416 // Post-index load multiple 1-element structures from N consecutive registers
3418 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3420 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3421 uimm_exact16, "ld1">;
3423 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3425 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3426 uimm_exact24, "ld1">;
3428 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3430 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3431 uimm_exact32, "ld1">;
3433 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3434 RegisterOperand VecList, Operand ImmTy,
3436 let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3437 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3438 def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3439 (outs GPR64xsp:$wb),
3440 (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3441 asmop # "\t$Rt, [$Rn], $amt",
3447 def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3448 (outs GPR64xsp:$wb),
3449 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3450 asmop # "\t$Rt, [$Rn], $Rm",
3456 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3457 Operand ImmTy2, string asmop> {
3458 defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3459 !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3461 defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3462 !cast<RegisterOperand>(List # "4H_operand"),
3465 defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3466 !cast<RegisterOperand>(List # "2S_operand"),
3469 defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3470 !cast<RegisterOperand>(List # "16B_operand"),
3473 defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3474 !cast<RegisterOperand>(List # "8H_operand"),
3477 defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3478 !cast<RegisterOperand>(List # "4S_operand"),
3481 defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3482 !cast<RegisterOperand>(List # "2D_operand"),
3486 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3487 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3488 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3491 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3493 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3496 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3498 // Post-index load multiple 1-element structures from N consecutive registers
3500 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3502 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3503 uimm_exact16, "st1">;
3505 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3507 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3508 uimm_exact24, "st1">;
3510 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3512 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3513 uimm_exact32, "st1">;
3515 // End of post-index vector load/store multiple N-element structure
3516 // (class SIMD lselem-post)
3518 // The followings are vector load/store single N-element structure
3519 // (class SIMD lsone).
3520 def neon_uimm0_bare : Operand<i64>,
3521 ImmLeaf<i64, [{return Imm == 0;}]> {
3522 let ParserMatchClass = neon_uimm0_asmoperand;
3523 let PrintMethod = "printUImmBareOperand";
3526 def neon_uimm1_bare : Operand<i64>,
3527 ImmLeaf<i64, [{return Imm < 2;}]> {
3528 let ParserMatchClass = neon_uimm1_asmoperand;
3529 let PrintMethod = "printUImmBareOperand";
3532 def neon_uimm2_bare : Operand<i64>,
3533 ImmLeaf<i64, [{return Imm < 4;}]> {
3534 let ParserMatchClass = neon_uimm2_asmoperand;
3535 let PrintMethod = "printUImmBareOperand";
3538 def neon_uimm3_bare : Operand<i64>,
3539 ImmLeaf<i64, [{return Imm < 8;}]> {
3540 let ParserMatchClass = uimm3_asmoperand;
3541 let PrintMethod = "printUImmBareOperand";
3544 def neon_uimm4_bare : Operand<i64>,
3545 ImmLeaf<i64, [{return Imm < 16;}]> {
3546 let ParserMatchClass = uimm4_asmoperand;
3547 let PrintMethod = "printUImmBareOperand";
3550 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3551 RegisterOperand VecList, string asmop>
3552 : NeonI_LdOne_Dup<q, r, opcode, size,
3553 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3554 asmop # "\t$Rt, [$Rn]",
3558 let neverHasSideEffects = 1;
3561 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3562 def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3563 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3565 def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3566 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3568 def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3569 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3571 def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3572 !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3574 def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3575 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3577 def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3578 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3580 def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3581 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3583 def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3584 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3587 // Load single 1-element structure to all lanes of 1 register
3588 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3590 // Load single N-element structure to all lanes of N consecutive
3591 // registers (N = 2,3,4)
3592 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3593 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3594 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3597 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3599 : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3600 (VTy (INST GPR64xsp:$Rn))>;
3602 // Match all LD1R instructions
3603 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3605 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3607 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3609 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3611 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3612 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3614 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3615 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3617 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3618 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3620 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3621 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3624 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3625 RegisterClass RegList> {
3626 defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3627 defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3628 defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3629 defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3632 // Special vector list operand of 128-bit vectors with bare layout.
3633 // i.e. only show ".b", ".h", ".s", ".d"
3634 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3635 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3636 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3637 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3639 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3640 Operand ImmOp, string asmop>
3641 : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3643 (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3644 asmop # "\t$Rt[$lane], [$Rn]",
3648 let neverHasSideEffects = 1;
3649 let hasExtraDefRegAllocReq = 1;
3650 let Constraints = "$src = $Rt";
3653 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3654 def _B : NeonI_LDN_Lane<r, 0b00, op0,
3655 !cast<RegisterOperand>(List # "B_operand"),
3656 neon_uimm4_bare, asmop> {
3657 let Inst{12-10} = lane{2-0};
3658 let Inst{30} = lane{3};
3661 def _H : NeonI_LDN_Lane<r, 0b01, op0,
3662 !cast<RegisterOperand>(List # "H_operand"),
3663 neon_uimm3_bare, asmop> {
3664 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3665 let Inst{30} = lane{2};
3668 def _S : NeonI_LDN_Lane<r, 0b10, op0,
3669 !cast<RegisterOperand>(List # "S_operand"),
3670 neon_uimm2_bare, asmop> {
3671 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3672 let Inst{30} = lane{1};
3675 def _D : NeonI_LDN_Lane<r, 0b10, op0,
3676 !cast<RegisterOperand>(List # "D_operand"),
3677 neon_uimm1_bare, asmop> {
3678 let Inst{12-10} = 0b001;
3679 let Inst{30} = lane{0};
3683 // Load single 1-element structure to one lane of 1 register.
3684 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3686 // Load single N-element structure to one lane of N consecutive registers
3688 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3689 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3690 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3692 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3693 Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3695 def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3696 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3697 (VTy (EXTRACT_SUBREG
3699 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3703 def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3704 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3705 (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3708 // Match all LD1LN instructions
3709 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3710 extloadi8, LD1LN_B>;
3712 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3713 extloadi16, LD1LN_H>;
3715 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3717 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3720 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3722 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3725 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3726 Operand ImmOp, string asmop>
3727 : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3728 (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3729 asmop # "\t$Rt[$lane], [$Rn]",
3733 let neverHasSideEffects = 1;
3734 let hasExtraDefRegAllocReq = 1;
3737 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3738 def _B : NeonI_STN_Lane<r, 0b00, op0,
3739 !cast<RegisterOperand>(List # "B_operand"),
3740 neon_uimm4_bare, asmop> {
3741 let Inst{12-10} = lane{2-0};
3742 let Inst{30} = lane{3};
3745 def _H : NeonI_STN_Lane<r, 0b01, op0,
3746 !cast<RegisterOperand>(List # "H_operand"),
3747 neon_uimm3_bare, asmop> {
3748 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3749 let Inst{30} = lane{2};
3752 def _S : NeonI_STN_Lane<r, 0b10, op0,
3753 !cast<RegisterOperand>(List # "S_operand"),
3754 neon_uimm2_bare, asmop> {
3755 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3756 let Inst{30} = lane{1};
3759 def _D : NeonI_STN_Lane<r, 0b10, op0,
3760 !cast<RegisterOperand>(List # "D_operand"),
3761 neon_uimm1_bare, asmop>{
3762 let Inst{12-10} = 0b001;
3763 let Inst{30} = lane{0};
3767 // Store single 1-element structure from one lane of 1 register.
3768 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3770 // Store single N-element structure from one lane of N consecutive registers
3772 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3773 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3774 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3776 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3777 Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3779 def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3782 (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3785 def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3787 (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3790 // Match all ST1LN instructions
3791 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3792 truncstorei8, ST1LN_B>;
3794 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3795 truncstorei16, ST1LN_H>;
3797 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3799 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3802 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3804 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3807 // End of vector load/store single N-element structure (class SIMD lsone).
3810 // The following are post-index load/store single N-element instructions
3811 // (class SIMD lsone-post)
3813 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3814 RegisterOperand VecList, Operand ImmTy,
3816 let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
3817 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3818 def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3819 (outs VecList:$Rt, GPR64xsp:$wb),
3820 (ins GPR64xsp:$Rn, ImmTy:$amt),
3821 asmop # "\t$Rt, [$Rn], $amt",
3827 def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3828 (outs VecList:$Rt, GPR64xsp:$wb),
3829 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3830 asmop # "\t$Rt, [$Rn], $Rm",
3836 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
3837 Operand uimm_b, Operand uimm_h,
3838 Operand uimm_s, Operand uimm_d> {
3839 defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
3840 !cast<RegisterOperand>(List # "8B_operand"),
3843 defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
3844 !cast<RegisterOperand>(List # "4H_operand"),
3847 defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
3848 !cast<RegisterOperand>(List # "2S_operand"),
3851 defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
3852 !cast<RegisterOperand>(List # "1D_operand"),
3855 defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
3856 !cast<RegisterOperand>(List # "16B_operand"),
3859 defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
3860 !cast<RegisterOperand>(List # "8H_operand"),
3863 defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
3864 !cast<RegisterOperand>(List # "4S_operand"),
3867 defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
3868 !cast<RegisterOperand>(List # "2D_operand"),
3872 // Post-index load single 1-element structure to all lanes of 1 register
3873 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
3874 uimm_exact2, uimm_exact4, uimm_exact8>;
3876 // Post-index load single N-element structure to all lanes of N consecutive
3877 // registers (N = 2,3,4)
3878 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
3879 uimm_exact4, uimm_exact8, uimm_exact16>;
3880 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
3881 uimm_exact6, uimm_exact12, uimm_exact24>;
3882 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
3883 uimm_exact8, uimm_exact16, uimm_exact32>;
3885 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
3886 Constraints = "$Rn = $wb, $Rt = $src",
3887 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3888 class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3889 Operand ImmTy, Operand ImmOp, string asmop>
3890 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3891 (outs VList:$Rt, GPR64xsp:$wb),
3892 (ins GPR64xsp:$Rn, ImmTy:$amt,
3893 VList:$src, ImmOp:$lane),
3894 asmop # "\t$Rt[$lane], [$Rn], $amt",
3900 class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3901 Operand ImmTy, Operand ImmOp, string asmop>
3902 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3903 (outs VList:$Rt, GPR64xsp:$wb),
3904 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
3905 VList:$src, ImmOp:$lane),
3906 asmop # "\t$Rt[$lane], [$Rn], $Rm",
3911 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
3912 Operand uimm_b, Operand uimm_h,
3913 Operand uimm_s, Operand uimm_d> {
3914 def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
3915 !cast<RegisterOperand>(List # "B_operand"),
3916 uimm_b, neon_uimm4_bare, asmop> {
3917 let Inst{12-10} = lane{2-0};
3918 let Inst{30} = lane{3};
3921 def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
3922 !cast<RegisterOperand>(List # "B_operand"),
3923 uimm_b, neon_uimm4_bare, asmop> {
3924 let Inst{12-10} = lane{2-0};
3925 let Inst{30} = lane{3};
3928 def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
3929 !cast<RegisterOperand>(List # "H_operand"),
3930 uimm_h, neon_uimm3_bare, asmop> {
3931 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3932 let Inst{30} = lane{2};
3935 def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
3936 !cast<RegisterOperand>(List # "H_operand"),
3937 uimm_h, neon_uimm3_bare, asmop> {
3938 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3939 let Inst{30} = lane{2};
3942 def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3943 !cast<RegisterOperand>(List # "S_operand"),
3944 uimm_s, neon_uimm2_bare, asmop> {
3945 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3946 let Inst{30} = lane{1};
3949 def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
3950 !cast<RegisterOperand>(List # "S_operand"),
3951 uimm_s, neon_uimm2_bare, asmop> {
3952 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3953 let Inst{30} = lane{1};
3956 def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3957 !cast<RegisterOperand>(List # "D_operand"),
3958 uimm_d, neon_uimm1_bare, asmop> {
3959 let Inst{12-10} = 0b001;
3960 let Inst{30} = lane{0};
3963 def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
3964 !cast<RegisterOperand>(List # "D_operand"),
3965 uimm_d, neon_uimm1_bare, asmop> {
3966 let Inst{12-10} = 0b001;
3967 let Inst{30} = lane{0};
3971 // Post-index load single 1-element structure to one lane of 1 register.
3972 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
3973 uimm_exact2, uimm_exact4, uimm_exact8>;
3975 // Post-index load single N-element structure to one lane of N consecutive
3978 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
3979 uimm_exact4, uimm_exact8, uimm_exact16>;
3980 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
3981 uimm_exact6, uimm_exact12, uimm_exact24>;
3982 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
3983 uimm_exact8, uimm_exact16, uimm_exact32>;
3985 let mayStore = 1, neverHasSideEffects = 1,
3986 hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
3987 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3988 class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3989 Operand ImmTy, Operand ImmOp, string asmop>
3990 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
3991 (outs GPR64xsp:$wb),
3992 (ins GPR64xsp:$Rn, ImmTy:$amt,
3993 VList:$Rt, ImmOp:$lane),
3994 asmop # "\t$Rt[$lane], [$Rn], $amt",
4000 class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4001 Operand ImmTy, Operand ImmOp, string asmop>
4002 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4003 (outs GPR64xsp:$wb),
4004 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4006 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4011 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4012 Operand uimm_b, Operand uimm_h,
4013 Operand uimm_s, Operand uimm_d> {
4014 def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4015 !cast<RegisterOperand>(List # "B_operand"),
4016 uimm_b, neon_uimm4_bare, asmop> {
4017 let Inst{12-10} = lane{2-0};
4018 let Inst{30} = lane{3};
4021 def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4022 !cast<RegisterOperand>(List # "B_operand"),
4023 uimm_b, neon_uimm4_bare, asmop> {
4024 let Inst{12-10} = lane{2-0};
4025 let Inst{30} = lane{3};
4028 def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4029 !cast<RegisterOperand>(List # "H_operand"),
4030 uimm_h, neon_uimm3_bare, asmop> {
4031 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4032 let Inst{30} = lane{2};
4035 def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4036 !cast<RegisterOperand>(List # "H_operand"),
4037 uimm_h, neon_uimm3_bare, asmop> {
4038 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4039 let Inst{30} = lane{2};
4042 def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4043 !cast<RegisterOperand>(List # "S_operand"),
4044 uimm_s, neon_uimm2_bare, asmop> {
4045 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4046 let Inst{30} = lane{1};
4049 def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4050 !cast<RegisterOperand>(List # "S_operand"),
4051 uimm_s, neon_uimm2_bare, asmop> {
4052 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4053 let Inst{30} = lane{1};
4056 def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4057 !cast<RegisterOperand>(List # "D_operand"),
4058 uimm_d, neon_uimm1_bare, asmop> {
4059 let Inst{12-10} = 0b001;
4060 let Inst{30} = lane{0};
4063 def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4064 !cast<RegisterOperand>(List # "D_operand"),
4065 uimm_d, neon_uimm1_bare, asmop> {
4066 let Inst{12-10} = 0b001;
4067 let Inst{30} = lane{0};
4071 // Post-index store single 1-element structure from one lane of 1 register.
4072 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4073 uimm_exact2, uimm_exact4, uimm_exact8>;
4075 // Post-index store single N-element structure from one lane of N consecutive
4076 // registers (N = 2,3,4)
4077 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4078 uimm_exact4, uimm_exact8, uimm_exact16>;
4079 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4080 uimm_exact6, uimm_exact12, uimm_exact24>;
4081 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4082 uimm_exact8, uimm_exact16, uimm_exact32>;
4084 // End of post-index load/store single N-element instructions
4085 // (class SIMD lsone-post)
4087 // Neon Scalar instructions implementation
4088 // Scalar Three Same
4090 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4092 : NeonI_Scalar3Same<u, size, opcode,
4093 (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4094 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4098 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4099 : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4101 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4102 bit Commutable = 0> {
4103 let isCommutable = Commutable in {
4104 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4105 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4109 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4110 string asmop, bit Commutable = 0> {
4111 let isCommutable = Commutable in {
4112 def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4113 def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4117 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4118 string asmop, bit Commutable = 0> {
4119 let isCommutable = Commutable in {
4120 def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4121 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4122 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4123 def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4127 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4128 Instruction INSTD> {
4129 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4130 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4133 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4138 : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4139 def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4140 (INSTB FPR8:$Rn, FPR8:$Rm)>;
4142 def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4143 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4145 def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4146 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4149 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
4151 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4152 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4154 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4156 Instruction INSTS> {
4157 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4158 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4159 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4160 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4163 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4165 Instruction INSTD> {
4166 def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4167 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4168 def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4169 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4172 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
4174 Instruction INSTD> {
4175 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4176 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4177 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4178 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4181 // Scalar Three Different
4183 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4184 RegisterClass FPRCD, RegisterClass FPRCS>
4185 : NeonI_Scalar3Diff<u, size, opcode,
4186 (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4187 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4191 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4192 def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4193 def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4196 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4197 let Constraints = "$Src = $Rd" in {
4198 def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4199 (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4200 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4203 def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4204 (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4205 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4211 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4213 Instruction INSTS> {
4214 def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4215 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4216 def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4217 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4220 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4222 Instruction INSTS> {
4223 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4224 (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4225 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4226 (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4229 // Scalar Two Registers Miscellaneous
4231 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4232 RegisterClass FPRCD, RegisterClass FPRCS>
4233 : NeonI_Scalar2SameMisc<u, size, opcode,
4234 (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4235 !strconcat(asmop, "\t$Rd, $Rn"),
4239 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4241 def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4243 def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4247 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4248 def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4251 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4252 : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4253 def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4254 def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4255 def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4258 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4259 : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4261 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4263 def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4264 def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4265 def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4268 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4269 string asmop, RegisterClass FPRC>
4270 : NeonI_Scalar2SameMisc<u, size, opcode,
4271 (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4272 !strconcat(asmop, "\t$Rd, $Rn"),
4276 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4279 let Constraints = "$Src = $Rd" in {
4280 def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4281 def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4282 def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4283 def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4287 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4289 : Pat<(v1f32 (opnode (v1f64 FPR64:$Rn))),
4292 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4294 Instruction INSTD> {
4295 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn))),
4297 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4301 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
4302 SDPatternOperator Dopnode,
4304 Instruction INSTD> {
4305 def : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn))),
4307 def : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn))),
4311 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4313 Instruction INSTD> {
4314 def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
4316 def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4320 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4321 : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4322 (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4323 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4327 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4329 def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4330 (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4331 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4334 def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4335 (outs FPR64:$Rd), (ins FPR64:$Rn, fpz64movi:$FPImm),
4336 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4341 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4343 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4344 (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4345 (INSTD FPR64:$Rn, 0)>;
4347 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4349 Instruction INSTD> {
4350 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
4351 (v1f32 (scalar_to_vector (f32 fpimm:$FPImm))))),
4352 (INSTS FPR32:$Rn, fpimm:$FPImm)>;
4353 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
4354 (v1f64 (bitconvert (v8i8 Neon_AllZero))))),
4355 (INSTD FPR64:$Rn, 0)>;
4358 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4359 Instruction INSTD> {
4360 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4364 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4369 : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4370 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4372 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4374 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4378 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4379 SDPatternOperator opnode,
4382 Instruction INSTD> {
4383 def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4385 def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4387 def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4392 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4393 SDPatternOperator opnode,
4397 Instruction INSTD> {
4398 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4399 (INSTB FPR8:$Src, FPR8:$Rn)>;
4400 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4401 (INSTH FPR16:$Src, FPR16:$Rn)>;
4402 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4403 (INSTS FPR32:$Src, FPR32:$Rn)>;
4404 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4405 (INSTD FPR64:$Src, FPR64:$Rn)>;
4408 // Scalar Shift By Immediate
4410 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4411 RegisterClass FPRC, Operand ImmTy>
4412 : NeonI_ScalarShiftImm<u, opcode,
4413 (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4414 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4417 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4419 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4421 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4422 let Inst{21-16} = Imm;
4426 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4428 : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4429 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4431 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4432 let Inst{18-16} = Imm;
4434 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4436 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4437 let Inst{19-16} = Imm;
4439 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4441 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4442 let Inst{20-16} = Imm;
4446 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4448 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4450 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4451 let Inst{21-16} = Imm;
4455 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4457 : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4458 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4460 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4461 let Inst{18-16} = Imm;
4463 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4465 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4466 let Inst{19-16} = Imm;
4468 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4470 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4471 let Inst{20-16} = Imm;
4475 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4476 : NeonI_ScalarShiftImm<u, opcode,
4477 (outs FPR64:$Rd), (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4478 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4481 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4482 let Inst{21-16} = Imm;
4483 let Constraints = "$Src = $Rd";
4486 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4487 : NeonI_ScalarShiftImm<u, opcode,
4488 (outs FPR64:$Rd), (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4489 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4492 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4493 let Inst{21-16} = Imm;
4494 let Constraints = "$Src = $Rd";
4497 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4498 RegisterClass FPRCD, RegisterClass FPRCS,
4500 : NeonI_ScalarShiftImm<u, opcode,
4501 (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4502 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4505 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4507 def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4510 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4511 let Inst{18-16} = Imm;
4513 def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4516 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4517 let Inst{19-16} = Imm;
4519 def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4522 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4523 let Inst{20-16} = Imm;
4527 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4528 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4530 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4531 let Inst{20-16} = Imm;
4533 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4535 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4536 let Inst{21-16} = Imm;
4540 multiclass Neon_ScalarShiftImm_D_size_patterns<SDPatternOperator opnode,
4541 Instruction INSTD> {
4542 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4543 (INSTD FPR64:$Rn, imm:$Imm)>;
4546 class Neon_ScalarShiftImm_arm_D_size_patterns<SDPatternOperator opnode,
4548 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 (Neon_vdup (i32 imm:$Imm))))),
4549 (INSTD FPR64:$Rn, imm:$Imm)>;
4551 multiclass Neon_ScalarShiftImm_BHSD_size_patterns<SDPatternOperator opnode,
4556 : Neon_ScalarShiftImm_D_size_patterns<opnode, INSTD> {
4557 def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 imm:$Imm))),
4558 (INSTB FPR8:$Rn, imm:$Imm)>;
4559 def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
4560 (INSTH FPR16:$Rn, imm:$Imm)>;
4561 def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4562 (INSTS FPR32:$Rn, imm:$Imm)>;
4565 class Neon_ScalarShiftImm_accum_D_size_patterns<SDPatternOperator opnode,
4567 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4568 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4570 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4571 SDPatternOperator opnode,
4574 Instruction INSTD> {
4575 def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
4576 (INSTH FPR16:$Rn, imm:$Imm)>;
4577 def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4578 (INSTS FPR32:$Rn, imm:$Imm)>;
4579 def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4580 (INSTD FPR64:$Rn, imm:$Imm)>;
4583 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
4584 SDPatternOperator Dopnode,
4586 Instruction INSTD> {
4587 def ssi : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4588 (INSTS FPR32:$Rn, imm:$Imm)>;
4589 def ddi : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4590 (INSTD FPR64:$Rn, imm:$Imm)>;
4593 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator Sopnode,
4594 SDPatternOperator Dopnode,
4596 Instruction INSTD> {
4597 def ssi : Pat<(v1i32 (Sopnode (v1f32 FPR32:$Rn), (i32 imm:$Imm))),
4598 (INSTS FPR32:$Rn, imm:$Imm)>;
4599 def ddi : Pat<(v1i64 (Dopnode (v1f64 FPR64:$Rn), (i32 imm:$Imm))),
4600 (INSTD FPR64:$Rn, imm:$Imm)>;
4603 // Scalar Signed Shift Right (Immediate)
4604 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4605 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4606 // Pattern to match llvm.arm.* intrinsic.
4607 def : Neon_ScalarShiftImm_arm_D_size_patterns<sra, SSHRddi>;
4609 // Scalar Unsigned Shift Right (Immediate)
4610 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4611 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4612 // Pattern to match llvm.arm.* intrinsic.
4613 def : Neon_ScalarShiftImm_arm_D_size_patterns<srl, USHRddi>;
4615 // Scalar Signed Rounding Shift Right (Immediate)
4616 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4617 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4619 // Scalar Unigned Rounding Shift Right (Immediate)
4620 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4621 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4623 // Scalar Signed Shift Right and Accumulate (Immediate)
4624 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4625 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsrads_n, SSRA>;
4627 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4628 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4629 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsradu_n, USRA>;
4631 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4632 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4633 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsrads_n, SRSRA>;
4635 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4636 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4637 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsradu_n, URSRA>;
4639 // Scalar Shift Left (Immediate)
4640 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4641 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4642 // Pattern to match llvm.arm.* intrinsic.
4643 def : Neon_ScalarShiftImm_arm_D_size_patterns<shl, SHLddi>;
4645 // Signed Saturating Shift Left (Immediate)
4646 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4647 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4649 SQSHLssi, SQSHLddi>;
4650 // Pattern to match llvm.arm.* intrinsic.
4651 defm : Neon_ScalarShiftImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4653 // Unsigned Saturating Shift Left (Immediate)
4654 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4655 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4657 UQSHLssi, UQSHLddi>;
4658 // Pattern to match llvm.arm.* intrinsic.
4659 defm : Neon_ScalarShiftImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4661 // Signed Saturating Shift Left Unsigned (Immediate)
4662 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4663 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4664 SQSHLUbbi, SQSHLUhhi,
4665 SQSHLUssi, SQSHLUddi>;
4667 // Shift Right And Insert (Immediate)
4668 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4669 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsri, SRI>;
4671 // Shift Left And Insert (Immediate)
4672 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4673 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsli, SLI>;
4675 // Signed Saturating Shift Right Narrow (Immediate)
4676 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4677 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4678 SQSHRNbhi, SQSHRNhsi,
4681 // Unsigned Saturating Shift Right Narrow (Immediate)
4682 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4683 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4684 UQSHRNbhi, UQSHRNhsi,
4687 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4688 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4689 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4690 SQRSHRNbhi, SQRSHRNhsi,
4693 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4694 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4695 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4696 UQRSHRNbhi, UQRSHRNhsi,
4699 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4700 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4701 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4702 SQSHRUNbhi, SQSHRUNhsi,
4705 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4706 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4707 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4708 SQRSHRUNbhi, SQRSHRUNhsi,
4711 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4712 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4713 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
4714 int_aarch64_neon_vcvtf64_n_s64,
4715 SCVTF_Nssi, SCVTF_Nddi>;
4717 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4718 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4719 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
4720 int_aarch64_neon_vcvtf64_n_u64,
4721 UCVTF_Nssi, UCVTF_Nddi>;
4723 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4724 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4725 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_s32_f32,
4726 int_aarch64_neon_vcvtd_n_s64_f64,
4727 FCVTZS_Nssi, FCVTZS_Nddi>;
4729 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4730 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4731 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_u32_f32,
4732 int_aarch64_neon_vcvtd_n_u64_f64,
4733 FCVTZU_Nssi, FCVTZU_Nddi>;
4735 // Scalar Integer Add
4736 let isCommutable = 1 in {
4737 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4740 // Scalar Integer Sub
4741 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4743 // Pattern for Scalar Integer Add and Sub with D register only
4744 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4745 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4747 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4748 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4749 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4750 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4751 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4753 // Scalar Integer Saturating Add (Signed, Unsigned)
4754 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4755 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4757 // Scalar Integer Saturating Sub (Signed, Unsigned)
4758 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4759 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4762 // Patterns to match llvm.aarch64.* intrinsic for
4763 // Scalar Integer Saturating Add, Sub (Signed, Unsigned)
4764 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4765 SQADDhhh, SQADDsss, SQADDddd>;
4766 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
4767 UQADDhhh, UQADDsss, UQADDddd>;
4768 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
4769 SQSUBhhh, SQSUBsss, SQSUBddd>;
4770 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
4771 UQSUBhhh, UQSUBsss, UQSUBddd>;
4773 // Scalar Integer Saturating Doubling Multiply Half High
4774 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4776 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4777 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4779 // Patterns to match llvm.arm.* intrinsic for
4780 // Scalar Integer Saturating Doubling Multiply Half High and
4781 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4782 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4784 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4787 // Scalar Floating-point Multiply Extended
4788 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4790 // Scalar Floating-point Reciprocal Step
4791 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4793 // Scalar Floating-point Reciprocal Square Root Step
4794 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4796 // Patterns to match llvm.arm.* intrinsic for
4797 // Scalar Floating-point Reciprocal Step and
4798 // Scalar Floating-point Reciprocal Square Root Step
4799 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
4801 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
4804 // Patterns to match llvm.aarch64.* intrinsic for
4805 // Scalar Floating-point Multiply Extended,
4806 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
4808 Instruction INSTD> {
4809 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4810 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4811 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4812 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4815 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
4818 // Scalar Integer Shift Left (Signed, Unsigned)
4819 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
4820 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
4822 // Patterns to match llvm.arm.* intrinsic for
4823 // Scalar Integer Shift Left (Signed, Unsigned)
4824 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
4825 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
4827 // Patterns to match llvm.aarch64.* intrinsic for
4828 // Scalar Integer Shift Left (Signed, Unsigned)
4829 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
4830 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
4832 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
4833 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
4834 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4836 // Patterns to match llvm.aarch64.* intrinsic for
4837 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
4838 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4839 SQSHLhhh, SQSHLsss, SQSHLddd>;
4840 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4841 UQSHLhhh, UQSHLsss, UQSHLddd>;
4843 // Patterns to match llvm.arm.* intrinsic for
4844 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
4845 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4846 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4848 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4849 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4850 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4852 // Patterns to match llvm.aarch64.* intrinsic for
4853 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4854 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4855 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4857 // Patterns to match llvm.arm.* intrinsic for
4858 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4859 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4860 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4862 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4863 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4864 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4866 // Patterns to match llvm.aarch64.* intrinsic for
4867 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4868 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4869 SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4870 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4871 UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4873 // Patterns to match llvm.arm.* intrinsic for
4874 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4875 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4876 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4878 // Signed Saturating Doubling Multiply-Add Long
4879 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4880 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4881 SQDMLALshh, SQDMLALdss>;
4883 // Signed Saturating Doubling Multiply-Subtract Long
4884 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4885 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4886 SQDMLSLshh, SQDMLSLdss>;
4888 // Signed Saturating Doubling Multiply Long
4889 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4890 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
4891 SQDMULLshh, SQDMULLdss>;
4893 // Scalar Signed Integer Convert To Floating-point
4894 defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4895 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
4896 int_aarch64_neon_vcvtf64_s64,
4899 // Scalar Unsigned Integer Convert To Floating-point
4900 defm UCVTF : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4901 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
4902 int_aarch64_neon_vcvtf64_u64,
4905 // Scalar Floating-point Converts
4906 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
4907 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
4910 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
4911 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
4912 FCVTNSss, FCVTNSdd>;
4914 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
4915 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
4916 FCVTNUss, FCVTNUdd>;
4918 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
4919 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
4920 FCVTMSss, FCVTMSdd>;
4922 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
4923 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
4924 FCVTMUss, FCVTMUdd>;
4926 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
4927 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
4928 FCVTASss, FCVTASdd>;
4930 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
4931 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
4932 FCVTAUss, FCVTAUdd>;
4934 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
4935 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
4936 FCVTPSss, FCVTPSdd>;
4938 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
4939 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
4940 FCVTPUss, FCVTPUdd>;
4942 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
4943 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
4944 FCVTZSss, FCVTZSdd>;
4946 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
4947 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
4948 FCVTZUss, FCVTZUdd>;
4950 // Scalar Floating-point Reciprocal Estimate
4951 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
4952 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
4953 FRECPEss, FRECPEdd>;
4955 // Scalar Floating-point Reciprocal Exponent
4956 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
4957 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
4958 FRECPXss, FRECPXdd>;
4960 // Scalar Floating-point Reciprocal Square Root Estimate
4961 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
4962 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
4963 FRSQRTEss, FRSQRTEdd>;
4965 // Scalar Integer Compare
4967 // Scalar Compare Bitwise Equal
4968 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
4969 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
4971 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
4974 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
4975 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4977 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
4979 // Scalar Compare Signed Greather Than Or Equal
4980 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
4981 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
4983 // Scalar Compare Unsigned Higher Or Same
4984 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
4985 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
4987 // Scalar Compare Unsigned Higher
4988 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
4989 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
4991 // Scalar Compare Signed Greater Than
4992 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
4993 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
4995 // Scalar Compare Bitwise Test Bits
4996 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
4997 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
4998 def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
5000 // Scalar Compare Bitwise Equal To Zero
5001 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5002 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5005 // Scalar Compare Signed Greather Than Or Equal To Zero
5006 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5007 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5010 // Scalar Compare Signed Greater Than Zero
5011 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5012 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5015 // Scalar Compare Signed Less Than Or Equal To Zero
5016 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5017 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5020 // Scalar Compare Less Than Zero
5021 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5022 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5025 // Scalar Floating-point Compare
5027 // Scalar Floating-point Compare Mask Equal
5028 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5029 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
5030 FCMEQsss, FCMEQddd>;
5032 // Scalar Floating-point Compare Mask Equal To Zero
5033 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5034 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
5035 FCMEQZssi, FCMEQZddi>;
5037 // Scalar Floating-point Compare Mask Greater Than Or Equal
5038 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5039 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
5040 FCMGEsss, FCMGEddd>;
5042 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5043 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5044 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
5045 FCMGEZssi, FCMGEZddi>;
5047 // Scalar Floating-point Compare Mask Greather Than
5048 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5049 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
5050 FCMGTsss, FCMGTddd>;
5052 // Scalar Floating-point Compare Mask Greather Than Zero
5053 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5054 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
5055 FCMGTZssi, FCMGTZddi>;
5057 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5058 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5059 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
5060 FCMLEZssi, FCMLEZddi>;
5062 // Scalar Floating-point Compare Mask Less Than Zero
5063 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5064 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
5065 FCMLTZssi, FCMLTZddi>;
5067 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5068 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5069 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
5070 FACGEsss, FACGEddd>;
5072 // Scalar Floating-point Absolute Compare Mask Greater Than
5073 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5074 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
5075 FACGTsss, FACGTddd>;
5077 // Scalar Absolute Value
5078 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5079 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5081 // Scalar Signed Saturating Absolute Value
5082 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5083 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5084 SQABSbb, SQABShh, SQABSss, SQABSdd>;
5087 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5088 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5090 // Scalar Signed Saturating Negate
5091 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5092 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5093 SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5095 // Scalar Signed Saturating Accumulated of Unsigned Value
5096 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5097 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5099 SUQADDss, SUQADDdd>;
5101 // Scalar Unsigned Saturating Accumulated of Signed Value
5102 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5103 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5105 USQADDss, USQADDdd>;
5107 // Scalar Signed Saturating Extract Unsigned Narrow
5108 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5109 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5113 // Scalar Signed Saturating Extract Narrow
5114 defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5115 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5119 // Scalar Unsigned Saturating Extract Narrow
5120 defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5121 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5125 // Scalar Reduce Pairwise
5127 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5128 string asmop, bit Commutable = 0> {
5129 let isCommutable = Commutable in {
5130 def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5131 (outs FPR64:$Rd), (ins VPR128:$Rn),
5132 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5138 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5139 string asmop, bit Commutable = 0>
5140 : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5141 let isCommutable = Commutable in {
5142 def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5143 (outs FPR32:$Rd), (ins VPR64:$Rn),
5144 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5150 // Scalar Reduce Addition Pairwise (Integer) with
5151 // Pattern to match llvm.arm.* intrinsic
5152 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5154 // Pattern to match llvm.aarch64.* intrinsic for
5155 // Scalar Reduce Addition Pairwise (Integer)
5156 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5157 (ADDPvv_D_2D VPR128:$Rn)>;
5159 // Scalar Reduce Addition Pairwise (Floating Point)
5160 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5162 // Scalar Reduce Maximum Pairwise (Floating Point)
5163 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5165 // Scalar Reduce Minimum Pairwise (Floating Point)
5166 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5168 // Scalar Reduce maxNum Pairwise (Floating Point)
5169 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5171 // Scalar Reduce minNum Pairwise (Floating Point)
5172 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5174 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnodeS,
5175 SDPatternOperator opnodeD,
5177 Instruction INSTD> {
5178 def : Pat<(v1f32 (opnodeS (v2f32 VPR64:$Rn))),
5180 def : Pat<(v1f64 (opnodeD (v2f64 VPR128:$Rn))),
5181 (INSTD VPR128:$Rn)>;
5184 // Patterns to match llvm.aarch64.* intrinsic for
5185 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5186 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5187 int_aarch64_neon_vpfaddq, FADDPvv_S_2S, FADDPvv_D_2D>;
5189 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5190 int_aarch64_neon_vpmaxq, FMAXPvv_S_2S, FMAXPvv_D_2D>;
5192 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5193 int_aarch64_neon_vpminq, FMINPvv_S_2S, FMINPvv_D_2D>;
5195 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5196 int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5198 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5199 int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5202 // Scalar by element Arithmetic
5204 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5205 string rmlane, bit u, bit szhi, bit szlo,
5206 RegisterClass ResFPR, RegisterClass OpFPR,
5207 RegisterOperand OpVPR, Operand OpImm>
5208 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5210 (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5211 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5218 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5220 bit u, bit szhi, bit szlo,
5221 RegisterClass ResFPR,
5222 RegisterClass OpFPR,
5223 RegisterOperand OpVPR,
5225 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5227 (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5228 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5231 let Constraints = "$src = $Rd";
5236 // Scalar Floating Point multiply (scalar, by element)
5237 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5238 0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5239 let Inst{11} = Imm{1}; // h
5240 let Inst{21} = Imm{0}; // l
5241 let Inst{20-16} = MRm;
5243 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5244 0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5245 let Inst{11} = Imm{0}; // h
5246 let Inst{21} = 0b0; // l
5247 let Inst{20-16} = MRm;
5250 // Scalar Floating Point multiply extended (scalar, by element)
5251 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5252 0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5253 let Inst{11} = Imm{1}; // h
5254 let Inst{21} = Imm{0}; // l
5255 let Inst{20-16} = MRm;
5257 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5258 0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5259 let Inst{11} = Imm{0}; // h
5260 let Inst{21} = 0b0; // l
5261 let Inst{20-16} = MRm;
5264 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5265 SDPatternOperator opnode,
5267 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5268 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5270 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5271 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5272 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5274 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5275 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5276 (ResTy (INST (ResTy FPRC:$Rn),
5277 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5281 def : Pat<(ResTy (opnode
5282 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5284 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5286 def : Pat<(ResTy (opnode
5287 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5289 (ResTy (INST (ResTy FPRC:$Rn),
5290 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5294 // Patterns for Scalar Floating Point multiply (scalar, by element)
5295 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5296 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5297 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5298 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5300 // Patterns for Scalar Floating Point multiply extended (scalar, by element)
5301 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5302 FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5303 v2f32, v4f32, neon_uimm1_bare>;
5304 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5305 FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5306 v1f64, v2f64, neon_uimm0_bare>;
5309 // Scalar Floating Point fused multiply-add (scalar, by element)
5310 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5311 0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5312 let Inst{11} = Imm{1}; // h
5313 let Inst{21} = Imm{0}; // l
5314 let Inst{20-16} = MRm;
5316 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5317 0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5318 let Inst{11} = Imm{0}; // h
5319 let Inst{21} = 0b0; // l
5320 let Inst{20-16} = MRm;
5323 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5324 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5325 0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5326 let Inst{11} = Imm{1}; // h
5327 let Inst{21} = Imm{0}; // l
5328 let Inst{20-16} = MRm;
5330 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5331 0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5332 let Inst{11} = Imm{0}; // h
5333 let Inst{21} = 0b0; // l
5334 let Inst{20-16} = MRm;
5336 // We are allowed to match the fma instruction regardless of compile options.
5337 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5338 Instruction FMLAI, Instruction FMLSI,
5339 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5340 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5342 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5343 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5345 (ResTy (FMLAI (ResTy FPRC:$Ra),
5346 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5348 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5349 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5351 (ResTy (FMLAI (ResTy FPRC:$Ra),
5353 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5356 // swapped fmla operands
5357 def : Pat<(ResTy (fma
5358 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5361 (ResTy (FMLAI (ResTy FPRC:$Ra),
5362 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5364 def : Pat<(ResTy (fma
5365 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5368 (ResTy (FMLAI (ResTy FPRC:$Ra),
5370 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5374 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5375 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5377 (ResTy (FMLSI (ResTy FPRC:$Ra),
5378 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5380 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5381 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5383 (ResTy (FMLSI (ResTy FPRC:$Ra),
5385 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5388 // swapped fmls operands
5389 def : Pat<(ResTy (fma
5390 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5393 (ResTy (FMLSI (ResTy FPRC:$Ra),
5394 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5396 def : Pat<(ResTy (fma
5397 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5400 (ResTy (FMLSI (ResTy FPRC:$Ra),
5402 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5406 // Scalar Floating Point fused multiply-add and
5407 // multiply-subtract (scalar, by element)
5408 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5409 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5410 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5411 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5412 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5413 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5415 // Scalar Signed saturating doubling multiply long (scalar, by element)
5416 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5417 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5418 let Inst{11} = 0b0; // h
5419 let Inst{21} = Imm{1}; // l
5420 let Inst{20} = Imm{0}; // m
5421 let Inst{19-16} = MRm{3-0};
5423 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5424 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5425 let Inst{11} = Imm{2}; // h
5426 let Inst{21} = Imm{1}; // l
5427 let Inst{20} = Imm{0}; // m
5428 let Inst{19-16} = MRm{3-0};
5430 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5431 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5432 let Inst{11} = 0b0; // h
5433 let Inst{21} = Imm{0}; // l
5434 let Inst{20-16} = MRm;
5436 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5437 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5438 let Inst{11} = Imm{1}; // h
5439 let Inst{21} = Imm{0}; // l
5440 let Inst{20-16} = MRm;
5443 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5444 SDPatternOperator opnode,
5446 ValueType ResTy, RegisterClass FPRC,
5447 ValueType OpVTy, ValueType OpTy,
5448 ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5450 def : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5451 (OpVTy (scalar_to_vector
5452 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5453 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5456 def : Pat<(ResTy (opnode
5457 (OpVTy (scalar_to_vector
5458 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5460 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5464 // Patterns for Scalar Signed saturating doubling
5465 // multiply long (scalar, by element)
5466 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5467 SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5468 i32, VPR64Lo, neon_uimm2_bare>;
5469 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5470 SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5471 i32, VPR128Lo, neon_uimm3_bare>;
5472 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5473 SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5474 i32, VPR64Lo, neon_uimm1_bare>;
5475 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5476 SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5477 i32, VPR128Lo, neon_uimm2_bare>;
5479 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5480 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5481 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5482 let Inst{11} = 0b0; // h
5483 let Inst{21} = Imm{1}; // l
5484 let Inst{20} = Imm{0}; // m
5485 let Inst{19-16} = MRm{3-0};
5487 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5488 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5489 let Inst{11} = Imm{2}; // h
5490 let Inst{21} = Imm{1}; // l
5491 let Inst{20} = Imm{0}; // m
5492 let Inst{19-16} = MRm{3-0};
5494 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5495 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5496 let Inst{11} = 0b0; // h
5497 let Inst{21} = Imm{0}; // l
5498 let Inst{20-16} = MRm;
5500 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5501 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5502 let Inst{11} = Imm{1}; // h
5503 let Inst{21} = Imm{0}; // l
5504 let Inst{20-16} = MRm;
5507 // Scalar Signed saturating doubling
5508 // multiply-subtract long (scalar, by element)
5509 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5510 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5511 let Inst{11} = 0b0; // h
5512 let Inst{21} = Imm{1}; // l
5513 let Inst{20} = Imm{0}; // m
5514 let Inst{19-16} = MRm{3-0};
5516 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5517 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5518 let Inst{11} = Imm{2}; // h
5519 let Inst{21} = Imm{1}; // l
5520 let Inst{20} = Imm{0}; // m
5521 let Inst{19-16} = MRm{3-0};
5523 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5524 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5525 let Inst{11} = 0b0; // h
5526 let Inst{21} = Imm{0}; // l
5527 let Inst{20-16} = MRm;
5529 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5530 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5531 let Inst{11} = Imm{1}; // h
5532 let Inst{21} = Imm{0}; // l
5533 let Inst{20-16} = MRm;
5536 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5537 SDPatternOperator opnode,
5538 SDPatternOperator coreopnode,
5540 ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5542 ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5544 def : Pat<(ResTy (opnode
5545 (ResTy ResFPRC:$Ra),
5546 (ResTy (coreopnode (OpTy FPRC:$Rn),
5547 (OpTy (scalar_to_vector
5548 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5549 (ResTy (INST (ResTy ResFPRC:$Ra),
5550 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5553 def : Pat<(ResTy (opnode
5554 (ResTy ResFPRC:$Ra),
5556 (OpTy (scalar_to_vector
5557 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5558 (OpTy FPRC:$Rn))))),
5559 (ResTy (INST (ResTy ResFPRC:$Ra),
5560 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5563 // Patterns for Scalar Signed saturating
5564 // doubling multiply-add long (scalar, by element)
5565 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5566 int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5567 i32, VPR64Lo, neon_uimm2_bare>;
5568 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5569 int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5570 i32, VPR128Lo, neon_uimm3_bare>;
5571 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5572 int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5573 i32, VPR64Lo, neon_uimm1_bare>;
5574 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5575 int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5576 i32, VPR128Lo, neon_uimm2_bare>;
5578 // Patterns for Scalar Signed saturating
5579 // doubling multiply-sub long (scalar, by element)
5580 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5581 int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5582 i32, VPR64Lo, neon_uimm2_bare>;
5583 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5584 int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5585 i32, VPR128Lo, neon_uimm3_bare>;
5586 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5587 int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5588 i32, VPR64Lo, neon_uimm1_bare>;
5589 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5590 int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5591 i32, VPR128Lo, neon_uimm2_bare>;
5594 // Scalar Signed saturating doubling multiply returning
5595 // high half (scalar, by element)
5596 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5597 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5598 let Inst{11} = 0b0; // h
5599 let Inst{21} = Imm{1}; // l
5600 let Inst{20} = Imm{0}; // m
5601 let Inst{19-16} = MRm{3-0};
5603 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5604 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5605 let Inst{11} = Imm{2}; // h
5606 let Inst{21} = Imm{1}; // l
5607 let Inst{20} = Imm{0}; // m
5608 let Inst{19-16} = MRm{3-0};
5610 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5611 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5612 let Inst{11} = 0b0; // h
5613 let Inst{21} = Imm{0}; // l
5614 let Inst{20-16} = MRm;
5616 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5617 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5618 let Inst{11} = Imm{1}; // h
5619 let Inst{21} = Imm{0}; // l
5620 let Inst{20-16} = MRm;
5623 // Patterns for Scalar Signed saturating doubling multiply returning
5624 // high half (scalar, by element)
5625 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5626 SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5627 i32, VPR64Lo, neon_uimm2_bare>;
5628 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5629 SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5630 i32, VPR128Lo, neon_uimm3_bare>;
5631 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5632 SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5633 i32, VPR64Lo, neon_uimm1_bare>;
5634 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5635 SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5636 i32, VPR128Lo, neon_uimm2_bare>;
5638 // Scalar Signed saturating rounding doubling multiply
5639 // returning high half (scalar, by element)
5640 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5641 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5642 let Inst{11} = 0b0; // h
5643 let Inst{21} = Imm{1}; // l
5644 let Inst{20} = Imm{0}; // m
5645 let Inst{19-16} = MRm{3-0};
5647 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5648 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5649 let Inst{11} = Imm{2}; // h
5650 let Inst{21} = Imm{1}; // l
5651 let Inst{20} = Imm{0}; // m
5652 let Inst{19-16} = MRm{3-0};
5654 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5655 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5656 let Inst{11} = 0b0; // h
5657 let Inst{21} = Imm{0}; // l
5658 let Inst{20-16} = MRm;
5660 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5661 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5662 let Inst{11} = Imm{1}; // h
5663 let Inst{21} = Imm{0}; // l
5664 let Inst{20-16} = MRm;
5667 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5668 SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5669 VPR64Lo, neon_uimm2_bare>;
5670 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5671 SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5672 VPR128Lo, neon_uimm3_bare>;
5673 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5674 SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5675 VPR64Lo, neon_uimm1_bare>;
5676 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5677 SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
5678 VPR128Lo, neon_uimm2_bare>;
5680 // Scalar Copy - DUP element to scalar
5681 class NeonI_Scalar_DUP<string asmop, string asmlane,
5682 RegisterClass ResRC, RegisterOperand VPRC,
5684 : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5685 asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5691 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5692 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5694 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5695 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5697 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5698 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5700 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5701 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5704 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5705 ValueType OpTy, Operand OpImm,
5706 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5707 def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5708 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5710 def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5712 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5716 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh,
5717 ValueType ResTy, ValueType OpTy> {
5718 def : Pat<(ResTy (GetLow VPR128:$Rn)),
5719 (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
5720 def : Pat<(ResTy (GetHigh VPR128:$Rn)),
5721 (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
5724 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
5725 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
5726 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
5727 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
5728 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
5729 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
5731 // Patterns for vector extract of FP data using scalar DUP instructions
5732 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5733 v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5734 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5735 v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5737 multiclass NeonI_Scalar_DUP_Vec_pattern<Instruction DUPI,
5738 ValueType ResTy, ValueType OpTy,Operand OpLImm,
5739 ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
5741 def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
5742 (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
5744 def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
5746 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5749 // Patterns for extract subvectors of v1ix data using scalar DUP instructions
5750 defm : NeonI_Scalar_DUP_Vec_pattern<DUPbv_B,
5751 v1i8, v16i8, neon_uimm4_bare, v8i8, v16i8, neon_uimm3_bare>;
5752 defm : NeonI_Scalar_DUP_Vec_pattern<DUPhv_H,
5753 v1i16, v8i16, neon_uimm3_bare, v4i16, v8i16, neon_uimm2_bare>;
5754 defm : NeonI_Scalar_DUP_Vec_pattern<DUPsv_S,
5755 v1i32, v4i32, neon_uimm2_bare, v2i32, v4i32, neon_uimm1_bare>;
5758 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
5759 Instruction DUPI, Operand OpImm,
5760 RegisterClass ResRC> {
5761 def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
5762 (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
5765 // Aliases for Scalar copy - DUP element (scalar)
5766 // FIXME: This is actually the preferred syntax but TableGen can't deal with
5767 // custom printing of aliases.
5768 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
5769 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
5770 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
5771 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
5774 //===----------------------------------------------------------------------===//
5775 // Non-Instruction Patterns
5776 //===----------------------------------------------------------------------===//
5778 // 64-bit vector bitcasts...
5780 def : Pat<(v1i64 (bitconvert (v8i8 VPR64:$src))), (v1i64 VPR64:$src)>;
5781 def : Pat<(v2f32 (bitconvert (v8i8 VPR64:$src))), (v2f32 VPR64:$src)>;
5782 def : Pat<(v2i32 (bitconvert (v8i8 VPR64:$src))), (v2i32 VPR64:$src)>;
5783 def : Pat<(v4i16 (bitconvert (v8i8 VPR64:$src))), (v4i16 VPR64:$src)>;
5785 def : Pat<(v1i64 (bitconvert (v4i16 VPR64:$src))), (v1i64 VPR64:$src)>;
5786 def : Pat<(v2i32 (bitconvert (v4i16 VPR64:$src))), (v2i32 VPR64:$src)>;
5787 def : Pat<(v2f32 (bitconvert (v4i16 VPR64:$src))), (v2f32 VPR64:$src)>;
5788 def : Pat<(v8i8 (bitconvert (v4i16 VPR64:$src))), (v8i8 VPR64:$src)>;
5790 def : Pat<(v1i64 (bitconvert (v2i32 VPR64:$src))), (v1i64 VPR64:$src)>;
5791 def : Pat<(v2f32 (bitconvert (v2i32 VPR64:$src))), (v2f32 VPR64:$src)>;
5792 def : Pat<(v4i16 (bitconvert (v2i32 VPR64:$src))), (v4i16 VPR64:$src)>;
5793 def : Pat<(v8i8 (bitconvert (v2i32 VPR64:$src))), (v8i8 VPR64:$src)>;
5795 def : Pat<(v1i64 (bitconvert (v2f32 VPR64:$src))), (v1i64 VPR64:$src)>;
5796 def : Pat<(v2i32 (bitconvert (v2f32 VPR64:$src))), (v2i32 VPR64:$src)>;
5797 def : Pat<(v4i16 (bitconvert (v2f32 VPR64:$src))), (v4i16 VPR64:$src)>;
5798 def : Pat<(v8i8 (bitconvert (v2f32 VPR64:$src))), (v8i8 VPR64:$src)>;
5800 def : Pat<(v2f32 (bitconvert (v1i64 VPR64:$src))), (v2f32 VPR64:$src)>;
5801 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
5802 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
5803 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
5805 // ..and 128-bit vector bitcasts...
5807 def : Pat<(v2f64 (bitconvert (v16i8 VPR128:$src))), (v2f64 VPR128:$src)>;
5808 def : Pat<(v2i64 (bitconvert (v16i8 VPR128:$src))), (v2i64 VPR128:$src)>;
5809 def : Pat<(v4f32 (bitconvert (v16i8 VPR128:$src))), (v4f32 VPR128:$src)>;
5810 def : Pat<(v4i32 (bitconvert (v16i8 VPR128:$src))), (v4i32 VPR128:$src)>;
5811 def : Pat<(v8i16 (bitconvert (v16i8 VPR128:$src))), (v8i16 VPR128:$src)>;
5813 def : Pat<(v2f64 (bitconvert (v8i16 VPR128:$src))), (v2f64 VPR128:$src)>;
5814 def : Pat<(v2i64 (bitconvert (v8i16 VPR128:$src))), (v2i64 VPR128:$src)>;
5815 def : Pat<(v4i32 (bitconvert (v8i16 VPR128:$src))), (v4i32 VPR128:$src)>;
5816 def : Pat<(v4f32 (bitconvert (v8i16 VPR128:$src))), (v4f32 VPR128:$src)>;
5817 def : Pat<(v16i8 (bitconvert (v8i16 VPR128:$src))), (v16i8 VPR128:$src)>;
5819 def : Pat<(v2f64 (bitconvert (v4i32 VPR128:$src))), (v2f64 VPR128:$src)>;
5820 def : Pat<(v2i64 (bitconvert (v4i32 VPR128:$src))), (v2i64 VPR128:$src)>;
5821 def : Pat<(v4f32 (bitconvert (v4i32 VPR128:$src))), (v4f32 VPR128:$src)>;
5822 def : Pat<(v8i16 (bitconvert (v4i32 VPR128:$src))), (v8i16 VPR128:$src)>;
5823 def : Pat<(v16i8 (bitconvert (v4i32 VPR128:$src))), (v16i8 VPR128:$src)>;
5825 def : Pat<(v2f64 (bitconvert (v4f32 VPR128:$src))), (v2f64 VPR128:$src)>;
5826 def : Pat<(v2i64 (bitconvert (v4f32 VPR128:$src))), (v2i64 VPR128:$src)>;
5827 def : Pat<(v4i32 (bitconvert (v4f32 VPR128:$src))), (v4i32 VPR128:$src)>;
5828 def : Pat<(v8i16 (bitconvert (v4f32 VPR128:$src))), (v8i16 VPR128:$src)>;
5829 def : Pat<(v16i8 (bitconvert (v4f32 VPR128:$src))), (v16i8 VPR128:$src)>;
5831 def : Pat<(v2f64 (bitconvert (v2i64 VPR128:$src))), (v2f64 VPR128:$src)>;
5832 def : Pat<(v4f32 (bitconvert (v2i64 VPR128:$src))), (v4f32 VPR128:$src)>;
5833 def : Pat<(v4i32 (bitconvert (v2i64 VPR128:$src))), (v4i32 VPR128:$src)>;
5834 def : Pat<(v8i16 (bitconvert (v2i64 VPR128:$src))), (v8i16 VPR128:$src)>;
5835 def : Pat<(v16i8 (bitconvert (v2i64 VPR128:$src))), (v16i8 VPR128:$src)>;
5837 def : Pat<(v2i64 (bitconvert (v2f64 VPR128:$src))), (v2i64 VPR128:$src)>;
5838 def : Pat<(v4f32 (bitconvert (v2f64 VPR128:$src))), (v4f32 VPR128:$src)>;
5839 def : Pat<(v4i32 (bitconvert (v2f64 VPR128:$src))), (v4i32 VPR128:$src)>;
5840 def : Pat<(v8i16 (bitconvert (v2f64 VPR128:$src))), (v8i16 VPR128:$src)>;
5841 def : Pat<(v16i8 (bitconvert (v2f64 VPR128:$src))), (v16i8 VPR128:$src)>;
5844 // ...and scalar bitcasts...
5845 def : Pat<(f16 (bitconvert (v1i16 FPR16:$src))), (f16 FPR16:$src)>;
5846 def : Pat<(f32 (bitconvert (v1i32 FPR32:$src))), (f32 FPR32:$src)>;
5847 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5848 def : Pat<(f32 (bitconvert (v1f32 FPR32:$src))), (f32 FPR32:$src)>;
5849 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5851 def : Pat<(i64 (bitconvert (v1i64 FPR64:$src))), (FMOVxd $src)>;
5852 def : Pat<(i64 (bitconvert (v1f64 FPR64:$src))), (FMOVxd $src)>;
5853 def : Pat<(i64 (bitconvert (v2i32 FPR64:$src))), (FMOVxd $src)>;
5854 def : Pat<(i64 (bitconvert (v2f32 FPR64:$src))), (FMOVxd $src)>;
5855 def : Pat<(i64 (bitconvert (v4i16 FPR64:$src))), (FMOVxd $src)>;
5856 def : Pat<(i64 (bitconvert (v8i8 FPR64:$src))), (FMOVxd $src)>;
5858 def : Pat<(i32 (bitconvert (v1i32 FPR32:$src))), (FMOVws $src)>;
5860 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
5861 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
5862 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
5864 def : Pat<(f64 (bitconvert (v8i8 VPR64:$src))), (f64 VPR64:$src)>;
5865 def : Pat<(f64 (bitconvert (v4i16 VPR64:$src))), (f64 VPR64:$src)>;
5866 def : Pat<(f64 (bitconvert (v2i32 VPR64:$src))), (f64 VPR64:$src)>;
5867 def : Pat<(f64 (bitconvert (v2f32 VPR64:$src))), (f64 VPR64:$src)>;
5868 def : Pat<(f64 (bitconvert (v1i64 VPR64:$src))), (f64 VPR64:$src)>;
5870 def : Pat<(f128 (bitconvert (v16i8 VPR128:$src))), (f128 VPR128:$src)>;
5871 def : Pat<(f128 (bitconvert (v8i16 VPR128:$src))), (f128 VPR128:$src)>;
5872 def : Pat<(f128 (bitconvert (v4i32 VPR128:$src))), (f128 VPR128:$src)>;
5873 def : Pat<(f128 (bitconvert (v2i64 VPR128:$src))), (f128 VPR128:$src)>;
5874 def : Pat<(f128 (bitconvert (v4f32 VPR128:$src))), (f128 VPR128:$src)>;
5875 def : Pat<(f128 (bitconvert (v2f64 VPR128:$src))), (f128 VPR128:$src)>;
5877 def : Pat<(v1i16 (bitconvert (f16 FPR16:$src))), (v1i16 FPR16:$src)>;
5878 def : Pat<(v1i32 (bitconvert (f32 FPR32:$src))), (v1i32 FPR32:$src)>;
5879 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5880 def : Pat<(v1f32 (bitconvert (f32 FPR32:$src))), (v1f32 FPR32:$src)>;
5881 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5883 def : Pat<(v1i64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
5884 def : Pat<(v1f64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
5885 def : Pat<(v2i32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
5886 def : Pat<(v2f32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
5887 def : Pat<(v4i16 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
5888 def : Pat<(v8i8 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
5890 def : Pat<(v1i32 (bitconvert (i32 GPR32:$src))), (FMOVsw $src)>;
5892 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5893 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5894 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5895 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5896 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5898 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5899 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5900 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5901 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5902 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5903 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5905 // Scalar Three Same
5907 def neon_uimm3 : Operand<i64>,
5908 ImmLeaf<i64, [{return Imm < 8;}]> {
5909 let ParserMatchClass = uimm3_asmoperand;
5910 let PrintMethod = "printUImmHexOperand";
5913 def neon_uimm4 : Operand<i64>,
5914 ImmLeaf<i64, [{return Imm < 16;}]> {
5915 let ParserMatchClass = uimm4_asmoperand;
5916 let PrintMethod = "printUImmHexOperand";
5920 class NeonI_Extract<bit q, bits<2> op2, string asmop,
5921 string OpS, RegisterOperand OpVPR, Operand OpImm>
5922 : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
5923 (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
5924 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
5925 ", $Rm." # OpS # ", $Index",
5931 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
5932 VPR64, neon_uimm3> {
5933 let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
5936 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
5937 VPR128, neon_uimm4> {
5938 let Inst{14-11} = Index;
5941 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
5943 : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
5945 (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
5947 def : NI_Extract<v8i8, VPR64, EXTvvvi_8b, neon_uimm3>;
5948 def : NI_Extract<v4i16, VPR64, EXTvvvi_8b, neon_uimm3>;
5949 def : NI_Extract<v2i32, VPR64, EXTvvvi_8b, neon_uimm3>;
5950 def : NI_Extract<v1i64, VPR64, EXTvvvi_8b, neon_uimm3>;
5951 def : NI_Extract<v2f32, VPR64, EXTvvvi_8b, neon_uimm3>;
5952 def : NI_Extract<v1f64, VPR64, EXTvvvi_8b, neon_uimm3>;
5953 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
5954 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
5955 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
5956 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
5957 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
5958 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
5961 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
5962 string asmop, string OpS, RegisterOperand OpVPR,
5963 RegisterOperand VecList>
5964 : NeonI_TBL<q, op2, len, op,
5965 (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
5966 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
5970 // The vectors in look up table are always 16b
5971 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
5972 def _8b : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
5973 !cast<RegisterOperand>(List # "16B_operand")>;
5975 def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
5976 !cast<RegisterOperand>(List # "16B_operand")>;
5979 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
5980 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
5981 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
5982 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
5984 // Table lookup extention
5985 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
5986 string asmop, string OpS, RegisterOperand OpVPR,
5987 RegisterOperand VecList>
5988 : NeonI_TBL<q, op2, len, op,
5989 (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
5990 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
5993 let Constraints = "$src = $Rd";
5996 // The vectors in look up table are always 16b
5997 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
5998 def _8b : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
5999 !cast<RegisterOperand>(List # "16B_operand")>;
6001 def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6002 !cast<RegisterOperand>(List # "16B_operand")>;
6005 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6006 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6007 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6008 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6010 // The followings are for instruction class (3V Elem)
6014 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6015 string asmop, string ResS, string OpS, string EleOpS,
6016 Operand OpImm, RegisterOperand ResVPR,
6017 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6018 : NeonI_2VElem<q, u, size, opcode,
6019 (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6020 EleOpVPR:$Re, OpImm:$Index),
6021 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6022 ", $Re." # EleOpS # "[$Index]",
6028 let Constraints = "$src = $Rd";
6031 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6032 // vector register class for element is always 128-bit to cover the max index
6033 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6034 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6035 let Inst{11} = {Index{1}};
6036 let Inst{21} = {Index{0}};
6037 let Inst{20-16} = Re;
6040 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6041 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6042 let Inst{11} = {Index{1}};
6043 let Inst{21} = {Index{0}};
6044 let Inst{20-16} = Re;
6047 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6048 def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6049 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6050 let Inst{11} = {Index{2}};
6051 let Inst{21} = {Index{1}};
6052 let Inst{20} = {Index{0}};
6053 let Inst{19-16} = Re{3-0};
6056 def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6057 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6058 let Inst{11} = {Index{2}};
6059 let Inst{21} = {Index{1}};
6060 let Inst{20} = {Index{0}};
6061 let Inst{19-16} = Re{3-0};
6065 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6066 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6068 // Pattern for lane in 128-bit vector
6069 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6070 RegisterOperand ResVPR, RegisterOperand OpVPR,
6071 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6072 ValueType EleOpTy, SDPatternOperator coreop>
6073 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6074 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6075 (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6077 // Pattern for lane in 64-bit vector
6078 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6079 RegisterOperand ResVPR, RegisterOperand OpVPR,
6080 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6081 ValueType EleOpTy, SDPatternOperator coreop>
6082 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6083 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6084 (INST ResVPR:$src, OpVPR:$Rn,
6085 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6087 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6089 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6090 op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32,
6091 BinOpFrag<(Neon_vduplane
6092 (Neon_Low4S node:$LHS), node:$RHS)>>;
6094 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6095 op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32,
6096 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6098 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6099 op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
6100 BinOpFrag<(Neon_vduplane
6101 (Neon_Low8H node:$LHS), node:$RHS)>>;
6103 def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6104 op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
6105 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6107 // Index can only be half of the max value for lane in 64-bit vector
6109 def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6110 op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32,
6111 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6113 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
6114 op, VPR128, VPR128, VPR64, v4i32, v4i32, v2i32,
6115 BinOpFrag<(Neon_vduplane
6116 (Neon_combine_4S node:$LHS, undef),
6119 def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6120 op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
6121 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6123 def : NI_2VE_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
6124 op, VPR128, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
6125 BinOpFrag<(Neon_vduplane
6126 (Neon_combine_8H node:$LHS, undef),
6130 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
6131 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
6133 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
6134 string asmop, string ResS, string OpS, string EleOpS,
6135 Operand OpImm, RegisterOperand ResVPR,
6136 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6137 : NeonI_2VElem<q, u, size, opcode,
6138 (outs ResVPR:$Rd), (ins OpVPR:$Rn,
6139 EleOpVPR:$Re, OpImm:$Index),
6140 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6141 ", $Re." # EleOpS # "[$Index]",
6148 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
6149 // vector register class for element is always 128-bit to cover the max index
6150 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6151 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6152 let Inst{11} = {Index{1}};
6153 let Inst{21} = {Index{0}};
6154 let Inst{20-16} = Re;
6157 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6158 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6159 let Inst{11} = {Index{1}};
6160 let Inst{21} = {Index{0}};
6161 let Inst{20-16} = Re;
6164 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6165 def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6166 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6167 let Inst{11} = {Index{2}};
6168 let Inst{21} = {Index{1}};
6169 let Inst{20} = {Index{0}};
6170 let Inst{19-16} = Re{3-0};
6173 def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6174 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6175 let Inst{11} = {Index{2}};
6176 let Inst{21} = {Index{1}};
6177 let Inst{20} = {Index{0}};
6178 let Inst{19-16} = Re{3-0};
6182 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
6183 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
6184 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
6186 // Pattern for lane in 128-bit vector
6187 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6188 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6189 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6190 SDPatternOperator coreop>
6191 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6192 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6193 (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6195 // Pattern for lane in 64-bit vector
6196 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6197 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6198 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6199 SDPatternOperator coreop>
6200 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6201 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6203 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6205 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
6206 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6207 op, VPR64, VPR128, v2i32, v2i32, v4i32,
6208 BinOpFrag<(Neon_vduplane
6209 (Neon_Low4S node:$LHS), node:$RHS)>>;
6211 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6212 op, VPR128, VPR128, v4i32, v4i32, v4i32,
6213 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6215 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6216 op, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
6217 BinOpFrag<(Neon_vduplane
6218 (Neon_Low8H node:$LHS), node:$RHS)>>;
6220 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6221 op, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
6222 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6224 // Index can only be half of the max value for lane in 64-bit vector
6226 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6227 op, VPR64, VPR64, v2i32, v2i32, v2i32,
6228 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6230 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
6231 op, VPR128, VPR64, v4i32, v4i32, v2i32,
6232 BinOpFrag<(Neon_vduplane
6233 (Neon_combine_4S node:$LHS, undef),
6236 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6237 op, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
6238 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6240 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
6241 op, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
6242 BinOpFrag<(Neon_vduplane
6243 (Neon_combine_8H node:$LHS, undef),
6247 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
6248 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
6249 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
6253 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
6254 // vector register class for element is always 128-bit to cover the max index
6255 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6256 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6257 let Inst{11} = {Index{1}};
6258 let Inst{21} = {Index{0}};
6259 let Inst{20-16} = Re;
6262 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6263 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6264 let Inst{11} = {Index{1}};
6265 let Inst{21} = {Index{0}};
6266 let Inst{20-16} = Re;
6269 // _1d2d doesn't exist!
6271 def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
6272 neon_uimm1_bare, VPR128, VPR128, VPR128> {
6273 let Inst{11} = {Index{0}};
6275 let Inst{20-16} = Re;
6279 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
6280 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
6282 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
6283 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6284 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6285 SDPatternOperator coreop>
6286 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6287 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
6289 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
6291 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
6292 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6293 op, VPR64, VPR128, v2f32, v2f32, v4f32,
6294 BinOpFrag<(Neon_vduplane
6295 (Neon_Low4float node:$LHS), node:$RHS)>>;
6297 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6298 op, VPR128, VPR128, v4f32, v4f32, v4f32,
6299 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6301 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
6302 op, VPR128, VPR128, v2f64, v2f64, v2f64,
6303 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6305 // Index can only be half of the max value for lane in 64-bit vector
6307 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6308 op, VPR64, VPR64, v2f32, v2f32, v2f32,
6309 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6311 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
6312 op, VPR128, VPR64, v4f32, v4f32, v2f32,
6313 BinOpFrag<(Neon_vduplane
6314 (Neon_combine_4f node:$LHS, undef),
6317 def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
6318 op, VPR128, VPR64, v2f64, v2f64, v1f64,
6319 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
6322 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
6323 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
6325 // The followings are patterns using fma
6326 // -ffp-contract=fast generates fma
6328 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
6329 // vector register class for element is always 128-bit to cover the max index
6330 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6331 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6332 let Inst{11} = {Index{1}};
6333 let Inst{21} = {Index{0}};
6334 let Inst{20-16} = Re;
6337 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6338 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6339 let Inst{11} = {Index{1}};
6340 let Inst{21} = {Index{0}};
6341 let Inst{20-16} = Re;
6344 // _1d2d doesn't exist!
6346 def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
6347 neon_uimm1_bare, VPR128, VPR128, VPR128> {
6348 let Inst{11} = {Index{0}};
6350 let Inst{20-16} = Re;
6354 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
6355 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
6357 // Pattern for lane in 128-bit vector
6358 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6359 RegisterOperand ResVPR, RegisterOperand OpVPR,
6360 ValueType ResTy, ValueType OpTy,
6361 SDPatternOperator coreop>
6362 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
6363 (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
6364 (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
6366 // Pattern for lane in 64-bit vector
6367 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6368 RegisterOperand ResVPR, RegisterOperand OpVPR,
6369 ValueType ResTy, ValueType OpTy,
6370 SDPatternOperator coreop>
6371 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
6372 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
6373 (INST ResVPR:$src, ResVPR:$Rn,
6374 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
6376 // Pattern for lane in 64-bit vector
6377 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
6378 SDPatternOperator op,
6379 RegisterOperand ResVPR, RegisterOperand OpVPR,
6380 ValueType ResTy, ValueType OpTy,
6381 SDPatternOperator coreop>
6382 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
6383 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
6384 (INST ResVPR:$src, ResVPR:$Rn,
6385 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
6388 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
6389 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
6390 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
6391 BinOpFrag<(Neon_vduplane
6392 (Neon_Low4float node:$LHS), node:$RHS)>>;
6394 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
6395 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
6396 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6398 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
6399 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
6400 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6402 // Index can only be half of the max value for lane in 64-bit vector
6404 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
6405 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
6406 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6408 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
6409 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
6410 BinOpFrag<(Neon_vduplane
6411 (Neon_combine_4f node:$LHS, undef),
6414 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
6415 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
6416 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
6419 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
6421 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
6423 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
6424 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
6425 BinOpFrag<(fneg (Neon_vduplane
6426 (Neon_Low4float node:$LHS), node:$RHS))>>;
6428 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
6429 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
6430 BinOpFrag<(Neon_vduplane
6431 (Neon_Low4float (fneg node:$LHS)),
6434 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
6435 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
6436 BinOpFrag<(fneg (Neon_vduplane
6437 node:$LHS, node:$RHS))>>;
6439 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
6440 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
6441 BinOpFrag<(Neon_vduplane
6442 (fneg node:$LHS), node:$RHS)>>;
6444 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
6445 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
6446 BinOpFrag<(fneg (Neon_vduplane
6447 node:$LHS, node:$RHS))>>;
6449 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
6450 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
6451 BinOpFrag<(Neon_vduplane
6452 (fneg node:$LHS), node:$RHS)>>;
6454 // Index can only be half of the max value for lane in 64-bit vector
6456 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
6457 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
6458 BinOpFrag<(fneg (Neon_vduplane
6459 node:$LHS, node:$RHS))>>;
6461 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
6462 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
6463 BinOpFrag<(Neon_vduplane
6464 (fneg node:$LHS), node:$RHS)>>;
6466 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
6467 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
6468 BinOpFrag<(fneg (Neon_vduplane
6469 (Neon_combine_4f node:$LHS, undef),
6472 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
6473 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
6474 BinOpFrag<(Neon_vduplane
6475 (Neon_combine_4f (fneg node:$LHS), undef),
6478 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
6479 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
6480 BinOpFrag<(fneg (Neon_combine_2d
6481 node:$LHS, node:$RHS))>>;
6483 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
6484 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
6485 BinOpFrag<(Neon_combine_2d
6486 (fneg node:$LHS), (fneg node:$RHS))>>;
6489 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
6491 // Variant 3: Long type
6492 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
6493 // SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
6495 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
6496 // vector register class for element is always 128-bit to cover the max index
6497 def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
6498 neon_uimm2_bare, VPR128, VPR64, VPR128> {
6499 let Inst{11} = {Index{1}};
6500 let Inst{21} = {Index{0}};
6501 let Inst{20-16} = Re;
6504 def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
6505 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6506 let Inst{11} = {Index{1}};
6507 let Inst{21} = {Index{0}};
6508 let Inst{20-16} = Re;
6511 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6512 def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
6513 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6514 let Inst{11} = {Index{2}};
6515 let Inst{21} = {Index{1}};
6516 let Inst{20} = {Index{0}};
6517 let Inst{19-16} = Re{3-0};
6520 def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
6521 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
6522 let Inst{11} = {Index{2}};
6523 let Inst{21} = {Index{1}};
6524 let Inst{20} = {Index{0}};
6525 let Inst{19-16} = Re{3-0};
6529 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
6530 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
6531 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
6532 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
6533 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
6534 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
6536 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
6537 // vector register class for element is always 128-bit to cover the max index
6538 def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
6539 neon_uimm2_bare, VPR128, VPR64, VPR128> {
6540 let Inst{11} = {Index{1}};
6541 let Inst{21} = {Index{0}};
6542 let Inst{20-16} = Re;
6545 def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
6546 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6547 let Inst{11} = {Index{1}};
6548 let Inst{21} = {Index{0}};
6549 let Inst{20-16} = Re;
6552 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6553 def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
6554 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6555 let Inst{11} = {Index{2}};
6556 let Inst{21} = {Index{1}};
6557 let Inst{20} = {Index{0}};
6558 let Inst{19-16} = Re{3-0};
6561 def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
6562 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
6563 let Inst{11} = {Index{2}};
6564 let Inst{21} = {Index{1}};
6565 let Inst{20} = {Index{0}};
6566 let Inst{19-16} = Re{3-0};
6570 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
6571 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
6572 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
6574 // Pattern for lane in 128-bit vector
6575 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6576 RegisterOperand EleOpVPR, ValueType ResTy,
6577 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6578 SDPatternOperator hiop, SDPatternOperator coreop>
6579 : Pat<(ResTy (op (ResTy VPR128:$src),
6580 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6581 (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6582 (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6584 // Pattern for lane in 64-bit vector
6585 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6586 RegisterOperand EleOpVPR, ValueType ResTy,
6587 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6588 SDPatternOperator hiop, SDPatternOperator coreop>
6589 : Pat<(ResTy (op (ResTy VPR128:$src),
6590 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6591 (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6592 (INST VPR128:$src, VPR128:$Rn,
6593 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6595 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
6596 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
6597 op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
6598 BinOpFrag<(Neon_vduplane
6599 (Neon_Low8H node:$LHS), node:$RHS)>>;
6601 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
6602 op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32,
6603 BinOpFrag<(Neon_vduplane
6604 (Neon_Low4S node:$LHS), node:$RHS)>>;
6606 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
6607 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H,
6608 BinOpFrag<(Neon_vduplane
6609 (Neon_Low8H node:$LHS), node:$RHS)>>;
6611 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
6612 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
6613 BinOpFrag<(Neon_vduplane
6614 (Neon_Low4S node:$LHS), node:$RHS)>>;
6616 // Index can only be half of the max value for lane in 64-bit vector
6618 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
6619 op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
6620 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6622 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
6623 op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32,
6624 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6626 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
6627 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
6628 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6630 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
6631 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
6632 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6635 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
6636 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
6637 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
6638 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
6640 // Pattern for lane in 128-bit vector
6641 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6642 RegisterOperand EleOpVPR, ValueType ResTy,
6643 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6644 SDPatternOperator hiop, SDPatternOperator coreop>
6646 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6647 (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6648 (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6650 // Pattern for lane in 64-bit vector
6651 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6652 RegisterOperand EleOpVPR, ValueType ResTy,
6653 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6654 SDPatternOperator hiop, SDPatternOperator coreop>
6656 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6657 (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6659 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6661 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
6662 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
6663 op, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
6664 BinOpFrag<(Neon_vduplane
6665 (Neon_Low8H node:$LHS), node:$RHS)>>;
6667 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
6668 op, VPR64, VPR128, v2i64, v2i32, v4i32,
6669 BinOpFrag<(Neon_vduplane
6670 (Neon_Low4S node:$LHS), node:$RHS)>>;
6672 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
6673 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16,
6675 BinOpFrag<(Neon_vduplane
6676 (Neon_Low8H node:$LHS), node:$RHS)>>;
6678 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
6679 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
6680 BinOpFrag<(Neon_vduplane
6681 (Neon_Low4S node:$LHS), node:$RHS)>>;
6683 // Index can only be half of the max value for lane in 64-bit vector
6685 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
6686 op, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
6687 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6689 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
6690 op, VPR64, VPR64, v2i64, v2i32, v2i32,
6691 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6693 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
6694 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
6695 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6697 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
6698 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
6699 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6702 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
6703 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
6704 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
6706 multiclass NI_qdma<SDPatternOperator op> {
6707 def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
6709 (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
6711 def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
6713 (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
6716 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
6717 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
6719 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
6720 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
6721 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
6722 v4i32, v4i16, v8i16,
6723 BinOpFrag<(Neon_vduplane
6724 (Neon_Low8H node:$LHS), node:$RHS)>>;
6726 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
6727 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
6728 v2i64, v2i32, v4i32,
6729 BinOpFrag<(Neon_vduplane
6730 (Neon_Low4S node:$LHS), node:$RHS)>>;
6732 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
6733 !cast<PatFrag>(op # "_4s"), VPR128Lo,
6734 v4i32, v8i16, v8i16, v4i16, Neon_High8H,
6735 BinOpFrag<(Neon_vduplane
6736 (Neon_Low8H node:$LHS), node:$RHS)>>;
6738 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
6739 !cast<PatFrag>(op # "_2d"), VPR128,
6740 v2i64, v4i32, v4i32, v2i32, Neon_High4S,
6741 BinOpFrag<(Neon_vduplane
6742 (Neon_Low4S node:$LHS), node:$RHS)>>;
6744 // Index can only be half of the max value for lane in 64-bit vector
6746 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
6747 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
6748 v4i32, v4i16, v4i16,
6749 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6751 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
6752 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
6753 v2i64, v2i32, v2i32,
6754 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6756 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
6757 !cast<PatFrag>(op # "_4s"), VPR64Lo,
6758 v4i32, v8i16, v4i16, v4i16, Neon_High8H,
6759 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6761 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
6762 !cast<PatFrag>(op # "_2d"), VPR64,
6763 v2i64, v4i32, v2i32, v2i32, Neon_High4S,
6764 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6767 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
6768 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
6770 // End of implementation for instruction class (3V Elem)
6772 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6773 RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6774 : NeonI_copy<0b1, 0b0, 0b0011,
6775 (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6776 asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6777 [(set (ResTy VPR128:$Rd),
6778 (ResTy (vector_insert
6779 (ResTy VPR128:$src),
6784 let Constraints = "$src = $Rd";
6787 //Insert element (vector, from main)
6788 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6790 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6792 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6794 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6796 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6798 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6800 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6802 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6805 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6806 (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6807 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6808 (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6809 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6810 (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6811 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6812 (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6814 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6815 RegisterClass OpGPR, ValueType OpTy,
6816 Operand OpImm, Instruction INS>
6817 : Pat<(ResTy (vector_insert
6821 (ResTy (EXTRACT_SUBREG
6822 (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6823 OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6825 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6826 neon_uimm3_bare, INSbw>;
6827 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6828 neon_uimm2_bare, INShw>;
6829 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6830 neon_uimm1_bare, INSsw>;
6831 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6832 neon_uimm0_bare, INSdx>;
6834 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6835 : NeonI_insert<0b1, 0b1,
6836 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6837 ResImm:$Immd, ResImm:$Immn),
6838 asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6841 let Constraints = "$src = $Rd";
6846 //Insert element (vector, from element)
6847 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6848 let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6849 let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6851 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6852 let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6853 let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6854 // bit 11 is unspecified, but should be set to zero.
6856 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6857 let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6858 let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6859 // bits 11-12 are unspecified, but should be set to zero.
6861 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6862 let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6863 let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6864 // bits 11-13 are unspecified, but should be set to zero.
6867 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6868 (INSELb VPR128:$Rd, VPR128:$Rn,
6869 neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6870 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6871 (INSELh VPR128:$Rd, VPR128:$Rn,
6872 neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6873 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6874 (INSELs VPR128:$Rd, VPR128:$Rn,
6875 neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6876 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6877 (INSELd VPR128:$Rd, VPR128:$Rn,
6878 neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6880 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6881 ValueType MidTy, Operand StImm, Operand NaImm,
6883 def : Pat<(ResTy (vector_insert
6884 (ResTy VPR128:$src),
6885 (MidTy (vector_extract
6889 (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6890 StImm:$Immd, StImm:$Immn)>;
6892 def : Pat <(ResTy (vector_insert
6893 (ResTy VPR128:$src),
6894 (MidTy (vector_extract
6898 (INS (ResTy VPR128:$src),
6899 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6900 StImm:$Immd, NaImm:$Immn)>;
6902 def : Pat <(NaTy (vector_insert
6904 (MidTy (vector_extract
6908 (NaTy (EXTRACT_SUBREG
6910 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6912 NaImm:$Immd, StImm:$Immn)),
6915 def : Pat <(NaTy (vector_insert
6917 (MidTy (vector_extract
6921 (NaTy (EXTRACT_SUBREG
6923 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6924 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6925 NaImm:$Immd, NaImm:$Immn)),
6929 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6930 neon_uimm1_bare, INSELs>;
6931 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6932 neon_uimm0_bare, INSELd>;
6933 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6934 neon_uimm3_bare, INSELb>;
6935 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6936 neon_uimm2_bare, INSELh>;
6937 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6938 neon_uimm1_bare, INSELs>;
6939 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6940 neon_uimm0_bare, INSELd>;
6942 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6944 RegisterClass OpFPR, Operand ResImm,
6945 SubRegIndex SubIndex, Instruction INS> {
6946 def : Pat <(ResTy (vector_insert
6947 (ResTy VPR128:$src),
6950 (INS (ResTy VPR128:$src),
6951 (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6955 def : Pat <(NaTy (vector_insert
6959 (NaTy (EXTRACT_SUBREG
6961 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6962 (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6968 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6970 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6973 class NeonI_SMOV<string asmop, string Res, bit Q,
6974 ValueType OpTy, ValueType eleTy,
6975 Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6976 : NeonI_copy<Q, 0b0, 0b0101,
6977 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6978 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6979 [(set (ResTy ResGPR:$Rd),
6981 (ResTy (vector_extract
6982 (OpTy VPR128:$Rn), (OpImm:$Imm))),
6988 //Signed integer move (main, from element)
6989 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6991 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6993 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6995 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6997 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6999 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7001 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
7003 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7005 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
7007 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7010 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
7011 ValueType eleTy, Operand StImm, Operand NaImm,
7012 Instruction SMOVI> {
7013 def : Pat<(i64 (sext_inreg
7015 (i32 (vector_extract
7016 (StTy VPR128:$Rn), (StImm:$Imm))))),
7018 (SMOVI VPR128:$Rn, StImm:$Imm)>;
7020 def : Pat<(i64 (sext
7021 (i32 (vector_extract
7022 (StTy VPR128:$Rn), (StImm:$Imm))))),
7023 (SMOVI VPR128:$Rn, StImm:$Imm)>;
7025 def : Pat<(i64 (sext_inreg
7026 (i64 (vector_extract
7027 (NaTy VPR64:$Rn), (NaImm:$Imm))),
7029 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7032 def : Pat<(i64 (sext_inreg
7034 (i32 (vector_extract
7035 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
7037 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7040 def : Pat<(i64 (sext
7041 (i32 (vector_extract
7042 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
7043 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7047 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
7048 neon_uimm3_bare, SMOVxb>;
7049 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
7050 neon_uimm2_bare, SMOVxh>;
7051 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
7052 neon_uimm1_bare, SMOVxs>;
7054 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
7055 ValueType eleTy, Operand StImm, Operand NaImm,
7057 : Pat<(i32 (sext_inreg
7058 (i32 (vector_extract
7059 (NaTy VPR64:$Rn), (NaImm:$Imm))),
7061 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7064 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
7065 neon_uimm3_bare, SMOVwb>;
7066 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
7067 neon_uimm2_bare, SMOVwh>;
7069 class NeonI_UMOV<string asmop, string Res, bit Q,
7070 ValueType OpTy, Operand OpImm,
7071 RegisterClass ResGPR, ValueType ResTy>
7072 : NeonI_copy<Q, 0b0, 0b0111,
7073 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
7074 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
7075 [(set (ResTy ResGPR:$Rd),
7076 (ResTy (vector_extract
7077 (OpTy VPR128:$Rn), (OpImm:$Imm))))],
7082 //Unsigned integer move (main, from element)
7083 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
7085 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7087 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
7089 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7091 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
7093 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7095 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
7097 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
7100 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
7101 (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
7102 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
7103 (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
7105 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
7106 Operand StImm, Operand NaImm,
7108 : Pat<(ResTy (vector_extract
7109 (NaTy VPR64:$Rn), NaImm:$Imm)),
7110 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7113 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
7114 neon_uimm3_bare, UMOVwb>;
7115 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
7116 neon_uimm2_bare, UMOVwh>;
7117 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
7118 neon_uimm1_bare, UMOVws>;
7121 (i32 (vector_extract
7122 (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
7124 (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
7127 (i32 (vector_extract
7128 (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
7130 (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
7132 def : Pat<(i64 (zext
7133 (i32 (vector_extract
7134 (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
7135 (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
7138 (i32 (vector_extract
7139 (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
7141 (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
7142 neon_uimm3_bare:$Imm)>;
7145 (i32 (vector_extract
7146 (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
7148 (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
7149 neon_uimm2_bare:$Imm)>;
7151 def : Pat<(i64 (zext
7152 (i32 (vector_extract
7153 (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
7154 (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
7155 neon_uimm0_bare:$Imm)>;
7157 // Additional copy patterns for scalar types
7158 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
7160 (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
7162 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
7164 (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
7166 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
7167 (FMOVws FPR32:$Rn)>;
7169 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
7170 (FMOVxd FPR64:$Rn)>;
7172 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
7175 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
7178 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
7179 (v1i8 (EXTRACT_SUBREG (v16i8
7180 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
7183 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
7184 (v1i16 (EXTRACT_SUBREG (v8i16
7185 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
7188 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
7191 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
7194 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
7196 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
7199 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7202 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
7203 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
7204 (f64 FPR64:$src), sub_64)>;
7206 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
7207 RegisterOperand ResVPR, Operand OpImm>
7208 : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
7209 (ins VPR128:$Rn, OpImm:$Imm),
7210 asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
7216 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
7218 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7221 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
7223 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7226 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
7228 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7231 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
7233 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
7236 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
7238 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7241 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
7243 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7246 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
7248 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7251 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
7252 ValueType OpTy,ValueType NaTy,
7253 ValueType ExTy, Operand OpLImm,
7255 def : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
7256 (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
7258 def : Pat<(ResTy (Neon_vduplane
7259 (NaTy VPR64:$Rn), OpNImm:$Imm)),
7261 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
7263 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
7264 neon_uimm4_bare, neon_uimm3_bare>;
7265 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
7266 neon_uimm4_bare, neon_uimm3_bare>;
7267 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
7268 neon_uimm3_bare, neon_uimm2_bare>;
7269 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
7270 neon_uimm3_bare, neon_uimm2_bare>;
7271 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
7272 neon_uimm2_bare, neon_uimm1_bare>;
7273 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
7274 neon_uimm2_bare, neon_uimm1_bare>;
7275 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
7276 neon_uimm1_bare, neon_uimm0_bare>;
7277 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
7278 neon_uimm2_bare, neon_uimm1_bare>;
7279 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
7280 neon_uimm2_bare, neon_uimm1_bare>;
7281 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
7282 neon_uimm1_bare, neon_uimm0_bare>;
7284 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
7286 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7288 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
7290 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7292 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
7294 (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
7297 class NeonI_DUP<bit Q, string asmop, string rdlane,
7298 RegisterOperand ResVPR, ValueType ResTy,
7299 RegisterClass OpGPR, ValueType OpTy>
7300 : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
7301 asmop # "\t$Rd" # rdlane # ", $Rn",
7302 [(set (ResTy ResVPR:$Rd),
7303 (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
7306 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
7307 let Inst{20-16} = 0b00001;
7308 // bits 17-20 are unspecified, but should be set to zero.
7311 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
7312 let Inst{20-16} = 0b00010;
7313 // bits 18-20 are unspecified, but should be set to zero.
7316 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
7317 let Inst{20-16} = 0b00100;
7318 // bits 19-20 are unspecified, but should be set to zero.
7321 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
7322 let Inst{20-16} = 0b01000;
7323 // bit 20 is unspecified, but should be set to zero.
7326 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
7327 let Inst{20-16} = 0b00001;
7328 // bits 17-20 are unspecified, but should be set to zero.
7331 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
7332 let Inst{20-16} = 0b00010;
7333 // bits 18-20 are unspecified, but should be set to zero.
7336 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
7337 let Inst{20-16} = 0b00100;
7338 // bits 19-20 are unspecified, but should be set to zero.
7341 // patterns for CONCAT_VECTORS
7342 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
7343 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
7344 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
7345 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
7347 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7348 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
7351 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
7353 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7357 defm : Concat_Vector_Pattern<v16i8, v8i8>;
7358 defm : Concat_Vector_Pattern<v8i16, v4i16>;
7359 defm : Concat_Vector_Pattern<v4i32, v2i32>;
7360 defm : Concat_Vector_Pattern<v2i64, v1i64>;
7361 defm : Concat_Vector_Pattern<v4f32, v2f32>;
7362 defm : Concat_Vector_Pattern<v2f64, v1f64>;
7364 //patterns for EXTRACT_SUBVECTOR
7365 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
7366 (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7367 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
7368 (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7369 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
7370 (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7371 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
7372 (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7373 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
7374 (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7375 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
7376 (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7378 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7379 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7380 SDPatternOperator Neon_Rev>
7381 : NeonI_2VMisc<Q, U, size, opcode,
7382 (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7383 asmop # "\t$Rd." # Res # ", $Rn." # Res,
7384 [(set (ResTy ResVPR:$Rd),
7385 (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7388 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7390 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7392 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7394 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7396 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7398 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7401 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7402 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7404 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7406 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7408 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7410 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7413 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7415 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7418 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7419 SDPatternOperator Neon_Padd> {
7420 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7421 (outs VPR128:$Rd), (ins VPR128:$Rn),
7422 asmop # "\t$Rd.8h, $Rn.16b",
7423 [(set (v8i16 VPR128:$Rd),
7424 (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7427 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7428 (outs VPR64:$Rd), (ins VPR64:$Rn),
7429 asmop # "\t$Rd.4h, $Rn.8b",
7430 [(set (v4i16 VPR64:$Rd),
7431 (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7434 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7435 (outs VPR128:$Rd), (ins VPR128:$Rn),
7436 asmop # "\t$Rd.4s, $Rn.8h",
7437 [(set (v4i32 VPR128:$Rd),
7438 (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7441 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7442 (outs VPR64:$Rd), (ins VPR64:$Rn),
7443 asmop # "\t$Rd.2s, $Rn.4h",
7444 [(set (v2i32 VPR64:$Rd),
7445 (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7448 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7449 (outs VPR128:$Rd), (ins VPR128:$Rn),
7450 asmop # "\t$Rd.2d, $Rn.4s",
7451 [(set (v2i64 VPR128:$Rd),
7452 (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7455 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7456 (outs VPR64:$Rd), (ins VPR64:$Rn),
7457 asmop # "\t$Rd.1d, $Rn.2s",
7458 [(set (v1i64 VPR64:$Rd),
7459 (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7463 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7464 int_arm_neon_vpaddls>;
7465 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7466 int_arm_neon_vpaddlu>;
7468 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7469 SDPatternOperator Neon_Padd> {
7470 let Constraints = "$src = $Rd" in {
7471 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7472 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7473 asmop # "\t$Rd.8h, $Rn.16b",
7474 [(set (v8i16 VPR128:$Rd),
7476 (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7479 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7480 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7481 asmop # "\t$Rd.4h, $Rn.8b",
7482 [(set (v4i16 VPR64:$Rd),
7484 (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7487 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7488 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7489 asmop # "\t$Rd.4s, $Rn.8h",
7490 [(set (v4i32 VPR128:$Rd),
7492 (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7495 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7496 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7497 asmop # "\t$Rd.2s, $Rn.4h",
7498 [(set (v2i32 VPR64:$Rd),
7500 (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7503 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7504 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7505 asmop # "\t$Rd.2d, $Rn.4s",
7506 [(set (v2i64 VPR128:$Rd),
7508 (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7511 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7512 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7513 asmop # "\t$Rd.1d, $Rn.2s",
7514 [(set (v1i64 VPR64:$Rd),
7516 (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7521 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7522 int_arm_neon_vpadals>;
7523 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7524 int_arm_neon_vpadalu>;
7526 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7527 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7528 (outs VPR128:$Rd), (ins VPR128:$Rn),
7529 asmop # "\t$Rd.16b, $Rn.16b",
7532 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7533 (outs VPR128:$Rd), (ins VPR128:$Rn),
7534 asmop # "\t$Rd.8h, $Rn.8h",
7537 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7538 (outs VPR128:$Rd), (ins VPR128:$Rn),
7539 asmop # "\t$Rd.4s, $Rn.4s",
7542 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7543 (outs VPR128:$Rd), (ins VPR128:$Rn),
7544 asmop # "\t$Rd.2d, $Rn.2d",
7547 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7548 (outs VPR64:$Rd), (ins VPR64:$Rn),
7549 asmop # "\t$Rd.8b, $Rn.8b",
7552 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7553 (outs VPR64:$Rd), (ins VPR64:$Rn),
7554 asmop # "\t$Rd.4h, $Rn.4h",
7557 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7558 (outs VPR64:$Rd), (ins VPR64:$Rn),
7559 asmop # "\t$Rd.2s, $Rn.2s",
7563 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7564 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7565 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7566 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7568 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7569 SDPatternOperator Neon_Op> {
7570 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7571 (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7573 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7574 (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7576 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7577 (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7579 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7580 (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7582 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7583 (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7585 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7586 (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7588 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7589 (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7592 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7593 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7594 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7596 def : Pat<(v16i8 (sub
7597 (v16i8 Neon_AllZero),
7598 (v16i8 VPR128:$Rn))),
7599 (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7600 def : Pat<(v8i8 (sub
7601 (v8i8 Neon_AllZero),
7603 (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7604 def : Pat<(v8i16 (sub
7605 (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7606 (v8i16 VPR128:$Rn))),
7607 (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7608 def : Pat<(v4i16 (sub
7609 (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7610 (v4i16 VPR64:$Rn))),
7611 (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7612 def : Pat<(v4i32 (sub
7613 (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7614 (v4i32 VPR128:$Rn))),
7615 (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7616 def : Pat<(v2i32 (sub
7617 (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7618 (v2i32 VPR64:$Rn))),
7619 (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7620 def : Pat<(v2i64 (sub
7621 (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7622 (v2i64 VPR128:$Rn))),
7623 (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7625 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7626 let Constraints = "$src = $Rd" in {
7627 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7628 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7629 asmop # "\t$Rd.16b, $Rn.16b",
7632 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7633 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7634 asmop # "\t$Rd.8h, $Rn.8h",
7637 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7638 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7639 asmop # "\t$Rd.4s, $Rn.4s",
7642 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7643 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7644 asmop # "\t$Rd.2d, $Rn.2d",
7647 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7648 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7649 asmop # "\t$Rd.8b, $Rn.8b",
7652 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7653 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7654 asmop # "\t$Rd.4h, $Rn.4h",
7657 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7658 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7659 asmop # "\t$Rd.2s, $Rn.2s",
7664 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7665 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7667 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7668 SDPatternOperator Neon_Op> {
7669 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7670 (v16i8 (!cast<Instruction>(Prefix # 16b)
7671 (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7673 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7674 (v8i16 (!cast<Instruction>(Prefix # 8h)
7675 (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7677 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7678 (v4i32 (!cast<Instruction>(Prefix # 4s)
7679 (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7681 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7682 (v2i64 (!cast<Instruction>(Prefix # 2d)
7683 (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7685 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7686 (v8i8 (!cast<Instruction>(Prefix # 8b)
7687 (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7689 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7690 (v4i16 (!cast<Instruction>(Prefix # 4h)
7691 (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7693 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7694 (v2i32 (!cast<Instruction>(Prefix # 2s)
7695 (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7698 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7699 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7701 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7702 SDPatternOperator Neon_Op> {
7703 def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7704 (outs VPR128:$Rd), (ins VPR128:$Rn),
7705 asmop # "\t$Rd.16b, $Rn.16b",
7706 [(set (v16i8 VPR128:$Rd),
7707 (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7710 def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7711 (outs VPR128:$Rd), (ins VPR128:$Rn),
7712 asmop # "\t$Rd.8h, $Rn.8h",
7713 [(set (v8i16 VPR128:$Rd),
7714 (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7717 def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7718 (outs VPR128:$Rd), (ins VPR128:$Rn),
7719 asmop # "\t$Rd.4s, $Rn.4s",
7720 [(set (v4i32 VPR128:$Rd),
7721 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
7724 def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
7725 (outs VPR64:$Rd), (ins VPR64:$Rn),
7726 asmop # "\t$Rd.8b, $Rn.8b",
7727 [(set (v8i8 VPR64:$Rd),
7728 (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
7731 def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
7732 (outs VPR64:$Rd), (ins VPR64:$Rn),
7733 asmop # "\t$Rd.4h, $Rn.4h",
7734 [(set (v4i16 VPR64:$Rd),
7735 (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
7738 def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
7739 (outs VPR64:$Rd), (ins VPR64:$Rn),
7740 asmop # "\t$Rd.2s, $Rn.2s",
7741 [(set (v2i32 VPR64:$Rd),
7742 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
7746 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
7747 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
7749 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
7751 def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
7752 (outs VPR128:$Rd), (ins VPR128:$Rn),
7753 asmop # "\t$Rd.16b, $Rn.16b",
7756 def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
7757 (outs VPR64:$Rd), (ins VPR64:$Rn),
7758 asmop # "\t$Rd.8b, $Rn.8b",
7762 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
7763 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
7764 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
7766 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
7767 (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
7768 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
7769 (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
7771 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
7772 (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
7773 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
7774 (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
7776 def : Pat<(v16i8 (xor
7778 (v16i8 Neon_AllOne))),
7779 (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
7780 def : Pat<(v8i8 (xor
7782 (v8i8 Neon_AllOne))),
7783 (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
7784 def : Pat<(v8i16 (xor
7786 (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
7787 (NOT16b VPR128:$Rn)>;
7788 def : Pat<(v4i16 (xor
7790 (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
7792 def : Pat<(v4i32 (xor
7794 (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
7795 (NOT16b VPR128:$Rn)>;
7796 def : Pat<(v2i32 (xor
7798 (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
7800 def : Pat<(v2i64 (xor
7802 (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
7803 (NOT16b VPR128:$Rn)>;
7805 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
7806 (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
7807 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
7808 (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
7810 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
7811 SDPatternOperator Neon_Op> {
7812 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7813 (outs VPR128:$Rd), (ins VPR128:$Rn),
7814 asmop # "\t$Rd.4s, $Rn.4s",
7815 [(set (v4f32 VPR128:$Rd),
7816 (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
7819 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7820 (outs VPR128:$Rd), (ins VPR128:$Rn),
7821 asmop # "\t$Rd.2d, $Rn.2d",
7822 [(set (v2f64 VPR128:$Rd),
7823 (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
7826 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7827 (outs VPR64:$Rd), (ins VPR64:$Rn),
7828 asmop # "\t$Rd.2s, $Rn.2s",
7829 [(set (v2f32 VPR64:$Rd),
7830 (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
7834 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
7835 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
7837 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
7838 def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7839 (outs VPR64:$Rd), (ins VPR128:$Rn),
7840 asmop # "\t$Rd.8b, $Rn.8h",
7843 def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7844 (outs VPR64:$Rd), (ins VPR128:$Rn),
7845 asmop # "\t$Rd.4h, $Rn.4s",
7848 def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7849 (outs VPR64:$Rd), (ins VPR128:$Rn),
7850 asmop # "\t$Rd.2s, $Rn.2d",
7853 let Constraints = "$Rd = $src" in {
7854 def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7855 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7856 asmop # "2\t$Rd.16b, $Rn.8h",
7859 def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7860 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7861 asmop # "2\t$Rd.8h, $Rn.4s",
7864 def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7865 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7866 asmop # "2\t$Rd.4s, $Rn.2d",
7871 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
7872 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
7873 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
7874 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
7876 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
7877 SDPatternOperator Neon_Op> {
7878 def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
7879 (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
7881 def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
7882 (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
7884 def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
7885 (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
7887 def : Pat<(v16i8 (concat_vectors
7889 (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
7890 (!cast<Instruction>(Prefix # 8h16b)
7891 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
7894 def : Pat<(v8i16 (concat_vectors
7896 (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
7897 (!cast<Instruction>(Prefix # 4s8h)
7898 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
7901 def : Pat<(v4i32 (concat_vectors
7903 (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
7904 (!cast<Instruction>(Prefix # 2d4s)
7905 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
7909 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
7910 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
7911 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
7912 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
7914 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
7915 def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7917 (ins VPR64:$Rn, uimm_exact8:$Imm),
7918 asmop # "\t$Rd.8h, $Rn.8b, $Imm",
7921 def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7923 (ins VPR64:$Rn, uimm_exact16:$Imm),
7924 asmop # "\t$Rd.4s, $Rn.4h, $Imm",
7927 def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7929 (ins VPR64:$Rn, uimm_exact32:$Imm),
7930 asmop # "\t$Rd.2d, $Rn.2s, $Imm",
7933 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7935 (ins VPR128:$Rn, uimm_exact8:$Imm),
7936 asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
7939 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7941 (ins VPR128:$Rn, uimm_exact16:$Imm),
7942 asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
7945 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7947 (ins VPR128:$Rn, uimm_exact32:$Imm),
7948 asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
7952 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
7954 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
7955 SDPatternOperator ExtOp, Operand Neon_Imm,
7958 (DesTy (ExtOp (OpTy VPR64:$Rn))),
7960 (i32 Neon_Imm:$Imm))))),
7961 (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
7963 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
7964 SDPatternOperator ExtOp, Operand Neon_Imm,
7965 string suffix, PatFrag GetHigh>
7968 (OpTy (GetHigh VPR128:$Rn)))),
7970 (i32 Neon_Imm:$Imm))))),
7971 (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
7973 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
7974 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
7975 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
7976 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
7977 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
7978 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
7979 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
7981 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
7983 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
7985 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
7987 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
7989 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
7992 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
7993 def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7994 (outs VPR64:$Rd), (ins VPR128:$Rn),
7995 asmop # "\t$Rd.4h, $Rn.4s",
7998 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7999 (outs VPR64:$Rd), (ins VPR128:$Rn),
8000 asmop # "\t$Rd.2s, $Rn.2d",
8003 let Constraints = "$src = $Rd" in {
8004 def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8005 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8006 asmop # "2\t$Rd.8h, $Rn.4s",
8009 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8010 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8011 asmop # "2\t$Rd.4s, $Rn.2d",
8016 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8018 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8019 SDPatternOperator f32_to_f16_Op,
8020 SDPatternOperator f64_to_f32_Op> {
8022 def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8023 (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8025 def : Pat<(v8i16 (concat_vectors
8027 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8028 (!cast<Instruction>(prefix # "4s8h")
8029 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8030 (v4f32 VPR128:$Rn))>;
8032 def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8033 (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8035 def : Pat<(v4f32 (concat_vectors
8037 (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8038 (!cast<Instruction>(prefix # "2d4s")
8039 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8040 (v2f64 VPR128:$Rn))>;
8043 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8045 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8047 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8048 (outs VPR64:$Rd), (ins VPR128:$Rn),
8049 asmop # "\t$Rd.2s, $Rn.2d",
8052 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8053 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8054 asmop # "2\t$Rd.4s, $Rn.2d",
8056 let Constraints = "$src = $Rd";
8059 def : Pat<(v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))),
8060 (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8062 def : Pat<(v4f32 (concat_vectors
8064 (v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))))),
8065 (!cast<Instruction>(prefix # "2d4s")
8066 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8070 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8072 def Neon_High4Float : PatFrag<(ops node:$in),
8073 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8075 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8076 def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8077 (outs VPR128:$Rd), (ins VPR64:$Rn),
8078 asmop # "\t$Rd.4s, $Rn.4h",
8081 def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8082 (outs VPR128:$Rd), (ins VPR64:$Rn),
8083 asmop # "\t$Rd.2d, $Rn.2s",
8086 def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8087 (outs VPR128:$Rd), (ins VPR128:$Rn),
8088 asmop # "2\t$Rd.4s, $Rn.8h",
8091 def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8092 (outs VPR128:$Rd), (ins VPR128:$Rn),
8093 asmop # "2\t$Rd.2d, $Rn.4s",
8097 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8099 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8100 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8101 (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8103 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8105 (v8i16 VPR128:$Rn))))),
8106 (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8108 def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8109 (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8111 def : Pat<(v2f64 (fextend
8112 (v2f32 (Neon_High4Float
8113 (v4f32 VPR128:$Rn))))),
8114 (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8117 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8119 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8120 ValueType ResTy4s, ValueType OpTy4s,
8121 ValueType ResTy2d, ValueType OpTy2d,
8122 ValueType ResTy2s, ValueType OpTy2s,
8123 SDPatternOperator Neon_Op> {
8125 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8126 (outs VPR128:$Rd), (ins VPR128:$Rn),
8127 asmop # "\t$Rd.4s, $Rn.4s",
8128 [(set (ResTy4s VPR128:$Rd),
8129 (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8132 def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8133 (outs VPR128:$Rd), (ins VPR128:$Rn),
8134 asmop # "\t$Rd.2d, $Rn.2d",
8135 [(set (ResTy2d VPR128:$Rd),
8136 (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8139 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8140 (outs VPR64:$Rd), (ins VPR64:$Rn),
8141 asmop # "\t$Rd.2s, $Rn.2s",
8142 [(set (ResTy2s VPR64:$Rd),
8143 (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8147 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8148 bits<5> opcode, SDPatternOperator Neon_Op> {
8149 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8150 v2f64, v2i32, v2f32, Neon_Op>;
8153 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8154 int_aarch64_neon_fcvtns>;
8155 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8156 int_aarch64_neon_fcvtnu>;
8157 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8158 int_aarch64_neon_fcvtps>;
8159 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8160 int_aarch64_neon_fcvtpu>;
8161 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8162 int_aarch64_neon_fcvtms>;
8163 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8164 int_aarch64_neon_fcvtmu>;
8165 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8166 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8167 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8168 int_aarch64_neon_fcvtas>;
8169 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8170 int_aarch64_neon_fcvtau>;
8172 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8173 bits<5> opcode, SDPatternOperator Neon_Op> {
8174 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8175 v2i64, v2f32, v2i32, Neon_Op>;
8178 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8179 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8181 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8182 bits<5> opcode, SDPatternOperator Neon_Op> {
8183 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8184 v2f64, v2f32, v2f32, Neon_Op>;
8187 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8188 int_aarch64_neon_frintn>;
8189 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8190 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8191 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8192 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8193 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8194 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8195 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8196 int_arm_neon_vrecpe>;
8197 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8198 int_arm_neon_vrsqrte>;
8199 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111,
8200 int_aarch64_neon_fsqrt>;
8202 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8203 bits<5> opcode, SDPatternOperator Neon_Op> {
8204 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8205 (outs VPR128:$Rd), (ins VPR128:$Rn),
8206 asmop # "\t$Rd.4s, $Rn.4s",
8207 [(set (v4i32 VPR128:$Rd),
8208 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8211 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8212 (outs VPR64:$Rd), (ins VPR64:$Rn),
8213 asmop # "\t$Rd.2s, $Rn.2s",
8214 [(set (v2i32 VPR64:$Rd),
8215 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8219 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8220 int_arm_neon_vrecpe>;
8221 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8222 int_arm_neon_vrsqrte>;
8225 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8226 string asmop, SDPatternOperator opnode>
8227 : NeonI_Crypto_AES<size, opcode,
8228 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8229 asmop # "\t$Rd.16b, $Rn.16b",
8230 [(set (v16i8 VPR128:$Rd),
8231 (v16i8 (opnode (v16i8 VPR128:$src),
8232 (v16i8 VPR128:$Rn))))],
8234 let Constraints = "$src = $Rd";
8235 let Predicates = [HasNEON, HasCrypto];
8238 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8239 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8241 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8242 string asmop, SDPatternOperator opnode>
8243 : NeonI_Crypto_AES<size, opcode,
8244 (outs VPR128:$Rd), (ins VPR128:$Rn),
8245 asmop # "\t$Rd.16b, $Rn.16b",
8246 [(set (v16i8 VPR128:$Rd),
8247 (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8250 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8251 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8253 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8254 string asmop, SDPatternOperator opnode>
8255 : NeonI_Crypto_SHA<size, opcode,
8256 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8257 asmop # "\t$Rd.4s, $Rn.4s",
8258 [(set (v4i32 VPR128:$Rd),
8259 (v4i32 (opnode (v4i32 VPR128:$src),
8260 (v4i32 VPR128:$Rn))))],
8262 let Constraints = "$src = $Rd";
8263 let Predicates = [HasNEON, HasCrypto];
8266 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8267 int_arm_neon_sha1su1>;
8268 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8269 int_arm_neon_sha256su0>;
8271 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8272 string asmop, SDPatternOperator opnode>
8273 : NeonI_Crypto_SHA<size, opcode,
8274 (outs FPR32:$Rd), (ins FPR32:$Rn),
8275 asmop # "\t$Rd, $Rn",
8276 [(set (v1i32 FPR32:$Rd),
8277 (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8279 let Predicates = [HasNEON, HasCrypto];
8282 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8284 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8285 SDPatternOperator opnode>
8286 : NeonI_Crypto_3VSHA<size, opcode,
8288 (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8289 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8290 [(set (v4i32 VPR128:$Rd),
8291 (v4i32 (opnode (v4i32 VPR128:$src),
8293 (v4i32 VPR128:$Rm))))],
8295 let Constraints = "$src = $Rd";
8296 let Predicates = [HasNEON, HasCrypto];
8299 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8300 int_arm_neon_sha1su0>;
8301 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8302 int_arm_neon_sha256su1>;
8304 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8305 SDPatternOperator opnode>
8306 : NeonI_Crypto_3VSHA<size, opcode,
8308 (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8309 asmop # "\t$Rd, $Rn, $Rm.4s",
8310 [(set (v4i32 FPR128:$Rd),
8311 (v4i32 (opnode (v4i32 FPR128:$src),
8313 (v4i32 VPR128:$Rm))))],
8315 let Constraints = "$src = $Rd";
8316 let Predicates = [HasNEON, HasCrypto];
8319 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8320 int_arm_neon_sha256h>;
8321 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8322 int_arm_neon_sha256h2>;
8324 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8325 SDPatternOperator opnode>
8326 : NeonI_Crypto_3VSHA<size, opcode,
8328 (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8329 asmop # "\t$Rd, $Rn, $Rm.4s",
8330 [(set (v4i32 FPR128:$Rd),
8331 (v4i32 (opnode (v4i32 FPR128:$src),
8333 (v4i32 VPR128:$Rm))))],
8335 let Constraints = "$src = $Rd";
8336 let Predicates = [HasNEON, HasCrypto];
8339 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8340 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8341 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;