1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
20 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
21 def HasNEON : Predicate<"Subtarget->hasNEON()">,
22 AssemblerPredicate<"FeatureNEON", "neon">;
23 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
24 AssemblerPredicate<"FeatureCrypto", "crypto">;
25 def HasCRC : Predicate<"Subtarget->hasCRC()">,
26 AssemblerPredicate<"FeatureCRC", "crc">;
27 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
28 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
29 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
31 //===----------------------------------------------------------------------===//
32 // AArch64-specific DAG Nodes.
35 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
36 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
39 SDTCisInt<0>, SDTCisVT<1, i32>]>;
41 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
42 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
48 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
49 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
56 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
59 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
60 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
61 SDTCisVT<2, OtherVT>]>;
64 def SDT_AArch64CSel : SDTypeProfile<1, 4,
69 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
72 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
73 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
74 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
77 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
78 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
79 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
80 SDTCisInt<2>, SDTCisInt<3>]>;
81 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
82 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
83 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
84 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
86 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
87 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
88 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
89 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
94 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
95 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
97 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
99 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
102 // Generates the general dynamic sequences, i.e.
103 // adrp x0, :tlsdesc:var
104 // ldr x1, [x0, #:tlsdesc_lo12:var]
105 // add x0, x0, #:tlsdesc_lo12:var
109 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
110 // number of operands (the variable)
111 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
114 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
115 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
116 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
117 SDTCisSameAs<1, 4>]>;
121 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
122 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
123 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
124 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
125 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
128 SDCallSeqEnd<[ SDTCisVT<0, i32>,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
131 def AArch64call : SDNode<"AArch64ISD::CALL",
132 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
135 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
137 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
139 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
141 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
143 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
147 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
148 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
149 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
150 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
151 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
153 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
154 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
155 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
157 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
158 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
160 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
161 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
163 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
165 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
167 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
168 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
170 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
171 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
172 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
173 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
174 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
176 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
177 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
178 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
179 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
180 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
181 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
183 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
184 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
185 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
186 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
187 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
188 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
189 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
191 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
192 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
193 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
194 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
196 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
197 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
198 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
199 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
200 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
201 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
202 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
203 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
205 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
206 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
207 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
209 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
210 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
211 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
212 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
213 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
215 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
216 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
217 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
219 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
220 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
221 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
222 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
223 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
224 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
225 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
227 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
228 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
229 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
230 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
231 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
233 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
234 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
236 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
238 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
239 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
241 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
242 [SDNPHasChain, SDNPSideEffect]>;
244 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
245 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
247 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
248 SDT_AArch64TLSDescCallSeq,
249 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
253 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
254 SDT_AArch64WrapperLarge>;
256 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
258 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
259 SDTCisSameAs<1, 2>]>;
260 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
261 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
263 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
264 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
265 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
266 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
267 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
268 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
270 //===----------------------------------------------------------------------===//
272 //===----------------------------------------------------------------------===//
274 // AArch64 Instruction Predicate Definitions.
276 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
277 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
278 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
279 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
280 def ForCodeSize : Predicate<"ForCodeSize">;
281 def NotForCodeSize : Predicate<"!ForCodeSize">;
283 include "AArch64InstrFormats.td"
285 //===----------------------------------------------------------------------===//
287 //===----------------------------------------------------------------------===//
288 // Miscellaneous instructions.
289 //===----------------------------------------------------------------------===//
291 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
292 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
293 [(AArch64callseq_start timm:$amt)]>;
294 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
295 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
296 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
298 let isReMaterializable = 1, isCodeGenOnly = 1 in {
299 // FIXME: The following pseudo instructions are only needed because remat
300 // cannot handle multiple instructions. When that changes, they can be
301 // removed, along with the AArch64Wrapper node.
303 let AddedComplexity = 10 in
304 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
305 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
308 // The MOVaddr instruction should match only when the add is not folded
309 // into a load or store address.
311 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
312 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
313 tglobaladdr:$low))]>,
314 Sched<[WriteAdrAdr]>;
316 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
317 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
319 Sched<[WriteAdrAdr]>;
321 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
322 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
324 Sched<[WriteAdrAdr]>;
326 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
327 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
328 tblockaddress:$low))]>,
329 Sched<[WriteAdrAdr]>;
331 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
332 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
333 tglobaltlsaddr:$low))]>,
334 Sched<[WriteAdrAdr]>;
336 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
337 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
338 texternalsym:$low))]>,
339 Sched<[WriteAdrAdr]>;
341 } // isReMaterializable, isCodeGenOnly
343 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
344 (LOADgot tglobaltlsaddr:$addr)>;
346 def : Pat<(AArch64LOADgot texternalsym:$addr),
347 (LOADgot texternalsym:$addr)>;
349 def : Pat<(AArch64LOADgot tconstpool:$addr),
350 (LOADgot tconstpool:$addr)>;
352 //===----------------------------------------------------------------------===//
353 // System instructions.
354 //===----------------------------------------------------------------------===//
356 def HINT : HintI<"hint">;
357 def : InstAlias<"nop", (HINT 0b000)>;
358 def : InstAlias<"yield",(HINT 0b001)>;
359 def : InstAlias<"wfe", (HINT 0b010)>;
360 def : InstAlias<"wfi", (HINT 0b011)>;
361 def : InstAlias<"sev", (HINT 0b100)>;
362 def : InstAlias<"sevl", (HINT 0b101)>;
364 // As far as LLVM is concerned this writes to the system's exclusive monitors.
365 let mayLoad = 1, mayStore = 1 in
366 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
368 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
369 // model patterns with sufficiently fine granularity.
370 let mayLoad = ?, mayStore = ? in {
371 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
372 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
374 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
375 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
377 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
378 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
381 def : InstAlias<"clrex", (CLREX 0xf)>;
382 def : InstAlias<"isb", (ISB 0xf)>;
386 def MSRpstate: MSRpstateI;
388 // The thread pointer (on Linux, at least, where this has been implemented) is
390 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
392 // Generic system instructions
393 def SYSxt : SystemXtI<0, "sys">;
394 def SYSLxt : SystemLXtI<1, "sysl">;
396 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
397 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
398 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
400 //===----------------------------------------------------------------------===//
401 // Move immediate instructions.
402 //===----------------------------------------------------------------------===//
404 defm MOVK : InsertImmediate<0b11, "movk">;
405 defm MOVN : MoveImmediate<0b00, "movn">;
407 let PostEncoderMethod = "fixMOVZ" in
408 defm MOVZ : MoveImmediate<0b10, "movz">;
410 // First group of aliases covers an implicit "lsl #0".
411 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
412 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
413 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
414 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
415 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
416 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
418 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
419 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
420 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
421 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
422 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
424 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
425 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
426 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
427 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
429 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
430 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
431 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
432 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
434 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
435 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
437 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
438 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
440 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
441 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
443 // Final group of aliases covers true "mov $Rd, $imm" cases.
444 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
445 int width, int shift> {
446 def _asmoperand : AsmOperandClass {
447 let Name = basename # width # "_lsl" # shift # "MovAlias";
448 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
450 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
453 def _movimm : Operand<i32> {
454 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
457 def : InstAlias<"mov $Rd, $imm",
458 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
461 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
462 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
464 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
465 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
466 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
467 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
469 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
470 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
472 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
473 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
474 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
475 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
477 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
478 isAsCheapAsAMove = 1 in {
479 // FIXME: The following pseudo instructions are only needed because remat
480 // cannot handle multiple instructions. When that changes, we can select
481 // directly to the real instructions and get rid of these pseudos.
484 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
485 [(set GPR32:$dst, imm:$src)]>,
488 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
489 [(set GPR64:$dst, imm:$src)]>,
491 } // isReMaterializable, isCodeGenOnly
493 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
494 // eventual expansion code fewer bits to worry about getting right. Marshalling
495 // the types is a little tricky though:
496 def i64imm_32bit : ImmLeaf<i64, [{
497 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
500 def trunc_imm : SDNodeXForm<imm, [{
501 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
504 def : Pat<(i64 i64imm_32bit:$src),
505 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
507 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
508 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
509 return CurDAG->getTargetConstant(
510 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
513 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
514 return CurDAG->getTargetConstant(
515 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
519 def : Pat<(f32 fpimm:$in),
520 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
521 def : Pat<(f64 fpimm:$in),
522 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
525 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
527 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
528 tglobaladdr:$g1, tglobaladdr:$g0),
529 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
530 tglobaladdr:$g2, 32),
531 tglobaladdr:$g1, 16),
532 tglobaladdr:$g0, 0)>;
534 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
535 tblockaddress:$g1, tblockaddress:$g0),
536 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
537 tblockaddress:$g2, 32),
538 tblockaddress:$g1, 16),
539 tblockaddress:$g0, 0)>;
541 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
542 tconstpool:$g1, tconstpool:$g0),
543 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
548 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
549 tjumptable:$g1, tjumptable:$g0),
550 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
556 //===----------------------------------------------------------------------===//
557 // Arithmetic instructions.
558 //===----------------------------------------------------------------------===//
560 // Add/subtract with carry.
561 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
562 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
564 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
565 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
566 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
567 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
570 defm ADD : AddSub<0, "add", "sub", add>;
571 defm SUB : AddSub<1, "sub", "add">;
573 def : InstAlias<"mov $dst, $src",
574 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
575 def : InstAlias<"mov $dst, $src",
576 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
577 def : InstAlias<"mov $dst, $src",
578 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
579 def : InstAlias<"mov $dst, $src",
580 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
582 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
583 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
585 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
586 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
587 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
588 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
589 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
590 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
591 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
592 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
593 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
594 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
595 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
596 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
597 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
598 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
599 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
600 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
601 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
603 // Because of the immediate format for add/sub-imm instructions, the
604 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
605 // These patterns capture that transformation.
606 let AddedComplexity = 1 in {
607 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
608 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
609 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
610 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
611 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
612 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
613 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
614 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
617 // Because of the immediate format for add/sub-imm instructions, the
618 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
619 // These patterns capture that transformation.
620 let AddedComplexity = 1 in {
621 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
622 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
623 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
624 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
625 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
626 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
627 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
628 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
631 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
632 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
633 def : InstAlias<"neg $dst, $src$shift",
634 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
635 def : InstAlias<"neg $dst, $src$shift",
636 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
638 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
639 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
640 def : InstAlias<"negs $dst, $src$shift",
641 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
642 def : InstAlias<"negs $dst, $src$shift",
643 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
646 // Unsigned/Signed divide
647 defm UDIV : Div<0, "udiv", udiv>;
648 defm SDIV : Div<1, "sdiv", sdiv>;
649 let isCodeGenOnly = 1 in {
650 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
651 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
655 defm ASRV : Shift<0b10, "asr", sra>;
656 defm LSLV : Shift<0b00, "lsl", shl>;
657 defm LSRV : Shift<0b01, "lsr", srl>;
658 defm RORV : Shift<0b11, "ror", rotr>;
660 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
661 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
662 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
663 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
664 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
665 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
666 def : ShiftAlias<"rorv", RORVWr, GPR32>;
667 def : ShiftAlias<"rorv", RORVXr, GPR64>;
670 let AddedComplexity = 7 in {
671 defm MADD : MulAccum<0, "madd", add>;
672 defm MSUB : MulAccum<1, "msub", sub>;
674 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
675 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
676 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
677 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
679 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
680 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
681 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
682 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
683 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
684 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
685 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
686 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
687 } // AddedComplexity = 7
689 let AddedComplexity = 5 in {
690 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
691 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
692 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
693 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
695 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
696 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
697 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
698 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
700 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
701 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
702 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
703 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
704 } // AddedComplexity = 5
706 def : MulAccumWAlias<"mul", MADDWrrr>;
707 def : MulAccumXAlias<"mul", MADDXrrr>;
708 def : MulAccumWAlias<"mneg", MSUBWrrr>;
709 def : MulAccumXAlias<"mneg", MSUBXrrr>;
710 def : WideMulAccumAlias<"smull", SMADDLrrr>;
711 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
712 def : WideMulAccumAlias<"umull", UMADDLrrr>;
713 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
716 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
717 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
720 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
721 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
722 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
723 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
725 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
726 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
727 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
728 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
731 defm CAS : CompareAndSwap<0, 0, "">;
732 defm CASA : CompareAndSwap<1, 0, "a">;
733 defm CASL : CompareAndSwap<0, 1, "l">;
734 defm CASAL : CompareAndSwap<1, 1, "al">;
737 defm CASP : CompareAndSwapPair<0, 0, "">;
738 defm CASPA : CompareAndSwapPair<1, 0, "a">;
739 defm CASPL : CompareAndSwapPair<0, 1, "l">;
740 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
743 defm SWP : Swap<0, 0, "">;
744 defm SWPA : Swap<1, 0, "a">;
745 defm SWPL : Swap<0, 1, "l">;
746 defm SWPAL : Swap<1, 1, "al">;
748 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
749 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
750 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
751 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
752 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
754 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
755 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
756 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
757 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
759 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
760 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
761 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
762 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
764 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
765 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
766 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
767 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
769 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
770 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
771 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
772 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
774 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
775 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
776 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
777 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
779 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
780 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
781 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
782 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
784 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
785 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
786 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
787 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
789 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
790 defm : STOPregister<"stadd","LDADD">; // STADDx
791 defm : STOPregister<"stclr","LDCLR">; // STCLRx
792 defm : STOPregister<"steor","LDEOR">; // STEORx
793 defm : STOPregister<"stset","LDSET">; // STSETx
794 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
795 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
796 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
797 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
799 //===----------------------------------------------------------------------===//
800 // Logical instructions.
801 //===----------------------------------------------------------------------===//
804 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
805 defm AND : LogicalImm<0b00, "and", and, "bic">;
806 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
807 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
809 // FIXME: these aliases *are* canonical sometimes (when movz can't be
810 // used). Actually, it seems to be working right now, but putting logical_immXX
811 // here is a bit dodgy on the AsmParser side too.
812 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
813 logical_imm32:$imm), 0>;
814 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
815 logical_imm64:$imm), 0>;
819 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
820 defm BICS : LogicalRegS<0b11, 1, "bics",
821 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
822 defm AND : LogicalReg<0b00, 0, "and", and>;
823 defm BIC : LogicalReg<0b00, 1, "bic",
824 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
825 defm EON : LogicalReg<0b10, 1, "eon",
826 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
827 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
828 defm ORN : LogicalReg<0b01, 1, "orn",
829 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
830 defm ORR : LogicalReg<0b01, 0, "orr", or>;
832 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
833 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
835 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
836 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
838 def : InstAlias<"mvn $Wd, $Wm$sh",
839 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
840 def : InstAlias<"mvn $Xd, $Xm$sh",
841 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
843 def : InstAlias<"tst $src1, $src2",
844 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
845 def : InstAlias<"tst $src1, $src2",
846 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
848 def : InstAlias<"tst $src1, $src2",
849 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
850 def : InstAlias<"tst $src1, $src2",
851 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
853 def : InstAlias<"tst $src1, $src2$sh",
854 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
855 def : InstAlias<"tst $src1, $src2$sh",
856 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
859 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
860 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
863 //===----------------------------------------------------------------------===//
864 // One operand data processing instructions.
865 //===----------------------------------------------------------------------===//
867 defm CLS : OneOperandData<0b101, "cls">;
868 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
869 defm RBIT : OneOperandData<0b000, "rbit">;
871 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
872 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
874 def REV16Wr : OneWRegData<0b001, "rev16",
875 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
876 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
878 def : Pat<(cttz GPR32:$Rn),
879 (CLZWr (RBITWr GPR32:$Rn))>;
880 def : Pat<(cttz GPR64:$Rn),
881 (CLZXr (RBITXr GPR64:$Rn))>;
882 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
885 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
889 // Unlike the other one operand instructions, the instructions with the "rev"
890 // mnemonic do *not* just different in the size bit, but actually use different
891 // opcode bits for the different sizes.
892 def REVWr : OneWRegData<0b010, "rev", bswap>;
893 def REVXr : OneXRegData<0b011, "rev", bswap>;
894 def REV32Xr : OneXRegData<0b010, "rev32",
895 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
897 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
899 // The bswap commutes with the rotr so we want a pattern for both possible
901 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
902 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
904 //===----------------------------------------------------------------------===//
905 // Bitfield immediate extraction instruction.
906 //===----------------------------------------------------------------------===//
907 let hasSideEffects = 0 in
908 defm EXTR : ExtractImm<"extr">;
909 def : InstAlias<"ror $dst, $src, $shift",
910 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
911 def : InstAlias<"ror $dst, $src, $shift",
912 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
914 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
915 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
916 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
917 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
919 //===----------------------------------------------------------------------===//
920 // Other bitfield immediate instructions.
921 //===----------------------------------------------------------------------===//
922 let hasSideEffects = 0 in {
923 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
924 defm SBFM : BitfieldImm<0b00, "sbfm">;
925 defm UBFM : BitfieldImm<0b10, "ubfm">;
928 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
929 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
930 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
933 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
934 uint64_t enc = 31 - N->getZExtValue();
935 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
938 // min(7, 31 - shift_amt)
939 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
940 uint64_t enc = 31 - N->getZExtValue();
941 enc = enc > 7 ? 7 : enc;
942 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
945 // min(15, 31 - shift_amt)
946 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
947 uint64_t enc = 31 - N->getZExtValue();
948 enc = enc > 15 ? 15 : enc;
949 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
952 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
953 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
954 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
957 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
958 uint64_t enc = 63 - N->getZExtValue();
959 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
962 // min(7, 63 - shift_amt)
963 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
964 uint64_t enc = 63 - N->getZExtValue();
965 enc = enc > 7 ? 7 : enc;
966 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
969 // min(15, 63 - shift_amt)
970 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
971 uint64_t enc = 63 - N->getZExtValue();
972 enc = enc > 15 ? 15 : enc;
973 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
976 // min(31, 63 - shift_amt)
977 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
978 uint64_t enc = 63 - N->getZExtValue();
979 enc = enc > 31 ? 31 : enc;
980 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
983 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
984 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
985 (i64 (i32shift_b imm0_31:$imm)))>;
986 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
987 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
988 (i64 (i64shift_b imm0_63:$imm)))>;
990 let AddedComplexity = 10 in {
991 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
992 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
993 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
994 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
997 def : InstAlias<"asr $dst, $src, $shift",
998 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
999 def : InstAlias<"asr $dst, $src, $shift",
1000 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1001 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1002 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1003 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1004 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1005 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1007 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
1008 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1009 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
1010 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1012 def : InstAlias<"lsr $dst, $src, $shift",
1013 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1014 def : InstAlias<"lsr $dst, $src, $shift",
1015 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1016 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1017 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1018 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1019 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1020 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1022 //===----------------------------------------------------------------------===//
1023 // Conditionally set flags instructions.
1024 //===----------------------------------------------------------------------===//
1025 defm CCMN : CondSetFlagsImm<0, "ccmn">;
1026 defm CCMP : CondSetFlagsImm<1, "ccmp">;
1028 defm CCMN : CondSetFlagsReg<0, "ccmn">;
1029 defm CCMP : CondSetFlagsReg<1, "ccmp">;
1031 //===----------------------------------------------------------------------===//
1032 // Conditional select instructions.
1033 //===----------------------------------------------------------------------===//
1034 defm CSEL : CondSelect<0, 0b00, "csel">;
1036 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
1037 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1038 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1039 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1041 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1042 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1043 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1044 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1045 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1046 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1047 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1048 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1049 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1050 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1051 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1052 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1054 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
1055 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
1056 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
1057 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
1058 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
1059 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
1060 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
1061 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
1063 // The inverse of the condition code from the alias instruction is what is used
1064 // in the aliased instruction. The parser all ready inverts the condition code
1065 // for these aliases.
1066 def : InstAlias<"cset $dst, $cc",
1067 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1068 def : InstAlias<"cset $dst, $cc",
1069 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1071 def : InstAlias<"csetm $dst, $cc",
1072 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1073 def : InstAlias<"csetm $dst, $cc",
1074 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1076 def : InstAlias<"cinc $dst, $src, $cc",
1077 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1078 def : InstAlias<"cinc $dst, $src, $cc",
1079 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1081 def : InstAlias<"cinv $dst, $src, $cc",
1082 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1083 def : InstAlias<"cinv $dst, $src, $cc",
1084 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1086 def : InstAlias<"cneg $dst, $src, $cc",
1087 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1088 def : InstAlias<"cneg $dst, $src, $cc",
1089 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1091 //===----------------------------------------------------------------------===//
1092 // PC-relative instructions.
1093 //===----------------------------------------------------------------------===//
1094 let isReMaterializable = 1 in {
1095 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1096 def ADR : ADRI<0, "adr", adrlabel, []>;
1097 } // hasSideEffects = 0
1099 def ADRP : ADRI<1, "adrp", adrplabel,
1100 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1101 } // isReMaterializable = 1
1103 // page address of a constant pool entry, block address
1104 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1105 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1107 //===----------------------------------------------------------------------===//
1108 // Unconditional branch (register) instructions.
1109 //===----------------------------------------------------------------------===//
1111 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1112 def RET : BranchReg<0b0010, "ret", []>;
1113 def DRPS : SpecialReturn<0b0101, "drps">;
1114 def ERET : SpecialReturn<0b0100, "eret">;
1115 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1117 // Default to the LR register.
1118 def : InstAlias<"ret", (RET LR)>;
1120 let isCall = 1, Defs = [LR], Uses = [SP] in {
1121 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1124 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1125 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1126 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1128 // Create a separate pseudo-instruction for codegen to use so that we don't
1129 // flag lr as used in every function. It'll be restored before the RET by the
1130 // epilogue if it's legitimately used.
1131 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1132 let isTerminator = 1;
1137 // This is a directive-like pseudo-instruction. The purpose is to insert an
1138 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1139 // (which in the usual case is a BLR).
1140 let hasSideEffects = 1 in
1141 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1142 let AsmString = ".tlsdesccall $sym";
1145 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1146 // FIXME: can "hasSideEffects be dropped?
1147 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1148 isCodeGenOnly = 1 in
1150 : Pseudo<(outs), (ins i64imm:$sym),
1151 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
1152 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1153 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1155 //===----------------------------------------------------------------------===//
1156 // Conditional branch (immediate) instruction.
1157 //===----------------------------------------------------------------------===//
1158 def Bcc : BranchCond;
1160 //===----------------------------------------------------------------------===//
1161 // Compare-and-branch instructions.
1162 //===----------------------------------------------------------------------===//
1163 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1164 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1166 //===----------------------------------------------------------------------===//
1167 // Test-bit-and-branch instructions.
1168 //===----------------------------------------------------------------------===//
1169 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1170 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1172 //===----------------------------------------------------------------------===//
1173 // Unconditional branch (immediate) instructions.
1174 //===----------------------------------------------------------------------===//
1175 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1176 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1177 } // isBranch, isTerminator, isBarrier
1179 let isCall = 1, Defs = [LR], Uses = [SP] in {
1180 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1182 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1184 //===----------------------------------------------------------------------===//
1185 // Exception generation instructions.
1186 //===----------------------------------------------------------------------===//
1187 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1188 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1189 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1190 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1191 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1192 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1193 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1194 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1196 // DCPSn defaults to an immediate operand of zero if unspecified.
1197 def : InstAlias<"dcps1", (DCPS1 0)>;
1198 def : InstAlias<"dcps2", (DCPS2 0)>;
1199 def : InstAlias<"dcps3", (DCPS3 0)>;
1201 //===----------------------------------------------------------------------===//
1202 // Load instructions.
1203 //===----------------------------------------------------------------------===//
1205 // Pair (indexed, offset)
1206 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1207 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1208 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1209 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1210 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1212 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1214 // Pair (pre-indexed)
1215 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1216 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1217 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1218 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1219 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1221 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1223 // Pair (post-indexed)
1224 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1225 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1226 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1227 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1228 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1230 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1233 // Pair (no allocate)
1234 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1235 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1236 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1237 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1238 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1241 // (register offset)
1245 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1246 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1247 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1248 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1251 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1252 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1253 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1254 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1255 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1257 // Load sign-extended half-word
1258 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1259 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1261 // Load sign-extended byte
1262 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1263 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1265 // Load sign-extended word
1266 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1269 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1271 // For regular load, we do not have any alignment requirement.
1272 // Thus, it is safe to directly map the vector loads with interesting
1273 // addressing modes.
1274 // FIXME: We could do the same for bitconvert to floating point vectors.
1275 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1276 ValueType ScalTy, ValueType VecTy,
1277 Instruction LOADW, Instruction LOADX,
1279 def : Pat<(VecTy (scalar_to_vector (ScalTy
1280 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1281 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1282 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1285 def : Pat<(VecTy (scalar_to_vector (ScalTy
1286 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1287 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1288 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1292 let AddedComplexity = 10 in {
1293 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1294 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1296 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1297 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1299 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1300 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1302 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1303 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1305 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1306 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1308 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1310 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1313 def : Pat <(v1i64 (scalar_to_vector (i64
1314 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1315 ro_Wextend64:$extend))))),
1316 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1318 def : Pat <(v1i64 (scalar_to_vector (i64
1319 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1320 ro_Xextend64:$extend))))),
1321 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1324 // Match all load 64 bits width whose type is compatible with FPR64
1325 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1326 Instruction LOADW, Instruction LOADX> {
1328 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1329 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1331 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1332 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1335 let AddedComplexity = 10 in {
1336 let Predicates = [IsLE] in {
1337 // We must do vector loads with LD1 in big-endian.
1338 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1339 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1340 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1341 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1342 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1345 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1346 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1348 // Match all load 128 bits width whose type is compatible with FPR128
1349 let Predicates = [IsLE] in {
1350 // We must do vector loads with LD1 in big-endian.
1351 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1352 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1353 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1354 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1355 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1356 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1357 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1359 } // AddedComplexity = 10
1362 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1363 Instruction INSTW, Instruction INSTX> {
1364 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1365 (SUBREG_TO_REG (i64 0),
1366 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1369 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1370 (SUBREG_TO_REG (i64 0),
1371 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1375 let AddedComplexity = 10 in {
1376 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1377 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1378 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1380 // zextloadi1 -> zextloadi8
1381 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1383 // extload -> zextload
1384 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1385 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1386 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1388 // extloadi1 -> zextloadi8
1389 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1394 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1395 Instruction INSTW, Instruction INSTX> {
1396 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1397 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1399 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1400 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1404 let AddedComplexity = 10 in {
1405 // extload -> zextload
1406 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1407 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1408 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1410 // zextloadi1 -> zextloadi8
1411 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1415 // (unsigned immediate)
1417 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1419 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1420 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1422 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1423 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1425 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1426 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1427 [(set (f16 FPR16:$Rt),
1428 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1429 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1430 [(set (f32 FPR32:$Rt),
1431 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1432 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1433 [(set (f64 FPR64:$Rt),
1434 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1435 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1436 [(set (f128 FPR128:$Rt),
1437 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1439 // For regular load, we do not have any alignment requirement.
1440 // Thus, it is safe to directly map the vector loads with interesting
1441 // addressing modes.
1442 // FIXME: We could do the same for bitconvert to floating point vectors.
1443 def : Pat <(v8i8 (scalar_to_vector (i32
1444 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1445 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1446 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1447 def : Pat <(v16i8 (scalar_to_vector (i32
1448 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1449 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1450 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1451 def : Pat <(v4i16 (scalar_to_vector (i32
1452 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1453 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1454 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1455 def : Pat <(v8i16 (scalar_to_vector (i32
1456 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1457 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1458 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1459 def : Pat <(v2i32 (scalar_to_vector (i32
1460 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1461 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1462 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1463 def : Pat <(v4i32 (scalar_to_vector (i32
1464 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1465 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1466 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1467 def : Pat <(v1i64 (scalar_to_vector (i64
1468 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1469 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1470 def : Pat <(v2i64 (scalar_to_vector (i64
1471 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1472 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1473 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1475 // Match all load 64 bits width whose type is compatible with FPR64
1476 let Predicates = [IsLE] in {
1477 // We must use LD1 to perform vector loads in big-endian.
1478 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1479 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1480 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1481 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1482 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1483 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1484 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1485 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1486 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1487 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1489 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1490 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1491 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1492 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1494 // Match all load 128 bits width whose type is compatible with FPR128
1495 let Predicates = [IsLE] in {
1496 // We must use LD1 to perform vector loads in big-endian.
1497 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1498 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1499 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1500 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1501 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1502 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1503 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1504 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1505 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1506 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1507 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1508 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1509 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1510 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1512 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1513 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1515 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1517 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1518 uimm12s2:$offset)))]>;
1519 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1521 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1522 uimm12s1:$offset)))]>;
1524 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1525 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1526 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1527 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1529 // zextloadi1 -> zextloadi8
1530 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1531 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1532 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1533 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1535 // extload -> zextload
1536 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1537 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1538 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1539 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1540 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1541 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1542 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1543 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1544 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1545 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1546 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1547 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1548 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1549 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1551 // load sign-extended half-word
1552 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1554 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1555 uimm12s2:$offset)))]>;
1556 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1558 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1559 uimm12s2:$offset)))]>;
1561 // load sign-extended byte
1562 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1564 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1565 uimm12s1:$offset)))]>;
1566 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1568 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1569 uimm12s1:$offset)))]>;
1571 // load sign-extended word
1572 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1574 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1575 uimm12s4:$offset)))]>;
1577 // load zero-extended word
1578 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1579 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1582 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1583 [(AArch64Prefetch imm:$Rt,
1584 (am_indexed64 GPR64sp:$Rn,
1585 uimm12s8:$offset))]>;
1587 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1591 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1592 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1593 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1594 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1595 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1597 // load sign-extended word
1598 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1601 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1602 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1605 // (unscaled immediate)
1606 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1608 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1609 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1611 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1612 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1614 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1615 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1617 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1618 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1619 [(set (f32 FPR32:$Rt),
1620 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1621 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1622 [(set (f64 FPR64:$Rt),
1623 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1624 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1625 [(set (f128 FPR128:$Rt),
1626 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1629 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1631 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1633 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1635 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1637 // Match all load 64 bits width whose type is compatible with FPR64
1638 let Predicates = [IsLE] in {
1639 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1640 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1641 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1642 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1643 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1644 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1645 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1646 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1647 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1648 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1650 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1651 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1652 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1653 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1655 // Match all load 128 bits width whose type is compatible with FPR128
1656 let Predicates = [IsLE] in {
1657 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1658 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1659 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1660 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1661 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1662 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1663 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1664 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1665 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1666 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1667 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1668 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1669 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1670 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1674 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1675 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1676 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1677 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1678 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1679 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1680 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1681 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1682 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1683 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1684 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1685 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1686 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1687 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1689 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1690 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1691 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1692 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1693 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1694 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1695 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1696 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1697 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1698 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1699 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1700 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1701 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1702 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1706 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1708 // Define new assembler match classes as we want to only match these when
1709 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1710 // associate a DiagnosticType either, as we want the diagnostic for the
1711 // canonical form (the scaled operand) to take precedence.
1712 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1713 let Name = "SImm9OffsetFB" # Width;
1714 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1715 let RenderMethod = "addImmOperands";
1718 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1719 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1720 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1721 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1722 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1724 def simm9_offset_fb8 : Operand<i64> {
1725 let ParserMatchClass = SImm9OffsetFB8Operand;
1727 def simm9_offset_fb16 : Operand<i64> {
1728 let ParserMatchClass = SImm9OffsetFB16Operand;
1730 def simm9_offset_fb32 : Operand<i64> {
1731 let ParserMatchClass = SImm9OffsetFB32Operand;
1733 def simm9_offset_fb64 : Operand<i64> {
1734 let ParserMatchClass = SImm9OffsetFB64Operand;
1736 def simm9_offset_fb128 : Operand<i64> {
1737 let ParserMatchClass = SImm9OffsetFB128Operand;
1740 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1741 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1742 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1743 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1744 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1745 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1746 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1747 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1748 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1749 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1750 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1751 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1752 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1753 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1756 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1757 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1758 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1759 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1761 // load sign-extended half-word
1763 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1765 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1767 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1769 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1771 // load sign-extended byte
1773 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1775 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1777 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1779 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1781 // load sign-extended word
1783 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1785 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1787 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1788 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1789 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1790 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1791 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1792 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1793 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1794 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1795 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1796 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1797 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1798 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1799 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1800 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1801 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1804 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1805 [(AArch64Prefetch imm:$Rt,
1806 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1809 // (unscaled immediate, unprivileged)
1810 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1811 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1813 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1814 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1816 // load sign-extended half-word
1817 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1818 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1820 // load sign-extended byte
1821 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1822 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1824 // load sign-extended word
1825 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1828 // (immediate pre-indexed)
1829 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1830 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1831 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1832 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1833 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1834 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1835 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1837 // load sign-extended half-word
1838 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1839 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1841 // load sign-extended byte
1842 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1843 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1845 // load zero-extended byte
1846 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1847 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1849 // load sign-extended word
1850 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1853 // (immediate post-indexed)
1854 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1855 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1856 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1857 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1858 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1859 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1860 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1862 // load sign-extended half-word
1863 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1864 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1866 // load sign-extended byte
1867 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1868 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1870 // load zero-extended byte
1871 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1872 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1874 // load sign-extended word
1875 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1877 //===----------------------------------------------------------------------===//
1878 // Store instructions.
1879 //===----------------------------------------------------------------------===//
1881 // Pair (indexed, offset)
1882 // FIXME: Use dedicated range-checked addressing mode operand here.
1883 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1884 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1885 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1886 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1887 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1889 // Pair (pre-indexed)
1890 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1891 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1892 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1893 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1894 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1896 // Pair (pre-indexed)
1897 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1898 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1899 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1900 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1901 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1903 // Pair (no allocate)
1904 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1905 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1906 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1907 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1908 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1911 // (Register offset)
1914 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1915 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1916 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1917 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1921 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1922 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1923 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1924 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1925 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1927 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1928 Instruction STRW, Instruction STRX> {
1930 def : Pat<(storeop GPR64:$Rt,
1931 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1932 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1933 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1935 def : Pat<(storeop GPR64:$Rt,
1936 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1937 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1938 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1941 let AddedComplexity = 10 in {
1943 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1944 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1945 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1948 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1949 Instruction STRW, Instruction STRX> {
1950 def : Pat<(store (VecTy FPR:$Rt),
1951 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1952 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1954 def : Pat<(store (VecTy FPR:$Rt),
1955 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1956 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1959 let AddedComplexity = 10 in {
1960 // Match all store 64 bits width whose type is compatible with FPR64
1961 let Predicates = [IsLE] in {
1962 // We must use ST1 to store vectors in big-endian.
1963 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1964 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1965 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1966 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1967 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1970 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1971 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1973 // Match all store 128 bits width whose type is compatible with FPR128
1974 let Predicates = [IsLE] in {
1975 // We must use ST1 to store vectors in big-endian.
1976 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1977 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1978 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1979 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1980 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1981 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1982 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1984 } // AddedComplexity = 10
1986 // Match stores from lane 0 to the appropriate subreg's store.
1987 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
1988 ValueType VecTy, ValueType STy,
1989 SubRegIndex SubRegIdx,
1990 Instruction STRW, Instruction STRX> {
1992 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
1993 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1994 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
1995 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1997 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
1998 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1999 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2000 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2003 let AddedComplexity = 19 in {
2004 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2005 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
2006 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
2007 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
2008 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
2009 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
2010 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2014 // (unsigned immediate)
2015 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2017 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2018 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2020 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2021 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2023 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
2024 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2025 [(store (f16 FPR16:$Rt),
2026 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
2027 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2028 [(store (f32 FPR32:$Rt),
2029 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2030 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2031 [(store (f64 FPR64:$Rt),
2032 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2033 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2035 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2036 [(truncstorei16 GPR32:$Rt,
2037 (am_indexed16 GPR64sp:$Rn,
2038 uimm12s2:$offset))]>;
2039 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2040 [(truncstorei8 GPR32:$Rt,
2041 (am_indexed8 GPR64sp:$Rn,
2042 uimm12s1:$offset))]>;
2044 // Match all store 64 bits width whose type is compatible with FPR64
2045 let AddedComplexity = 10 in {
2046 let Predicates = [IsLE] in {
2047 // We must use ST1 to store vectors in big-endian.
2048 def : Pat<(store (v2f32 FPR64:$Rt),
2049 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2050 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2051 def : Pat<(store (v8i8 FPR64:$Rt),
2052 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2053 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2054 def : Pat<(store (v4i16 FPR64:$Rt),
2055 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2056 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2057 def : Pat<(store (v2i32 FPR64:$Rt),
2058 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2059 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2060 def : Pat<(store (v4f16 FPR64:$Rt),
2061 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2062 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2064 def : Pat<(store (v1f64 FPR64:$Rt),
2065 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2066 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2067 def : Pat<(store (v1i64 FPR64:$Rt),
2068 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2069 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2071 // Match all store 128 bits width whose type is compatible with FPR128
2072 let Predicates = [IsLE] in {
2073 // We must use ST1 to store vectors in big-endian.
2074 def : Pat<(store (v4f32 FPR128:$Rt),
2075 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2076 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2077 def : Pat<(store (v2f64 FPR128:$Rt),
2078 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2079 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2080 def : Pat<(store (v16i8 FPR128:$Rt),
2081 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2082 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2083 def : Pat<(store (v8i16 FPR128:$Rt),
2084 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2085 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2086 def : Pat<(store (v4i32 FPR128:$Rt),
2087 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2088 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2089 def : Pat<(store (v2i64 FPR128:$Rt),
2090 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2091 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2092 def : Pat<(store (v8f16 FPR128:$Rt),
2093 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2094 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2096 def : Pat<(store (f128 FPR128:$Rt),
2097 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2098 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2101 def : Pat<(truncstorei32 GPR64:$Rt,
2102 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2103 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2104 def : Pat<(truncstorei16 GPR64:$Rt,
2105 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2106 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2107 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2108 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2110 } // AddedComplexity = 10
2113 // (unscaled immediate)
2114 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2116 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2117 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2119 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2120 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2122 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2123 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2124 [(store (f16 FPR16:$Rt),
2125 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2126 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2127 [(store (f32 FPR32:$Rt),
2128 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2129 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2130 [(store (f64 FPR64:$Rt),
2131 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2132 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2133 [(store (f128 FPR128:$Rt),
2134 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2135 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2136 [(truncstorei16 GPR32:$Rt,
2137 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2138 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2139 [(truncstorei8 GPR32:$Rt,
2140 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2142 // Match all store 64 bits width whose type is compatible with FPR64
2143 let Predicates = [IsLE] in {
2144 // We must use ST1 to store vectors in big-endian.
2145 def : Pat<(store (v2f32 FPR64:$Rt),
2146 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2147 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2148 def : Pat<(store (v8i8 FPR64:$Rt),
2149 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2150 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2151 def : Pat<(store (v4i16 FPR64:$Rt),
2152 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2153 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2154 def : Pat<(store (v2i32 FPR64:$Rt),
2155 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2156 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2157 def : Pat<(store (v4f16 FPR64:$Rt),
2158 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2159 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2161 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2162 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2163 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2164 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2166 // Match all store 128 bits width whose type is compatible with FPR128
2167 let Predicates = [IsLE] in {
2168 // We must use ST1 to store vectors in big-endian.
2169 def : Pat<(store (v4f32 FPR128:$Rt),
2170 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2171 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2172 def : Pat<(store (v2f64 FPR128:$Rt),
2173 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2174 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2175 def : Pat<(store (v16i8 FPR128:$Rt),
2176 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2177 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2178 def : Pat<(store (v8i16 FPR128:$Rt),
2179 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2180 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2181 def : Pat<(store (v4i32 FPR128:$Rt),
2182 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2183 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2184 def : Pat<(store (v2i64 FPR128:$Rt),
2185 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2186 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2187 def : Pat<(store (v2f64 FPR128:$Rt),
2188 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2189 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2190 def : Pat<(store (v8f16 FPR128:$Rt),
2191 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2192 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2195 // unscaled i64 truncating stores
2196 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2197 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2198 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2199 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2200 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2201 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2204 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2205 def : InstAlias<"str $Rt, [$Rn, $offset]",
2206 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2207 def : InstAlias<"str $Rt, [$Rn, $offset]",
2208 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2209 def : InstAlias<"str $Rt, [$Rn, $offset]",
2210 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2211 def : InstAlias<"str $Rt, [$Rn, $offset]",
2212 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2213 def : InstAlias<"str $Rt, [$Rn, $offset]",
2214 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2215 def : InstAlias<"str $Rt, [$Rn, $offset]",
2216 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2217 def : InstAlias<"str $Rt, [$Rn, $offset]",
2218 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2220 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2221 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2222 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2223 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2226 // (unscaled immediate, unprivileged)
2227 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2228 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2230 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2231 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2234 // (immediate pre-indexed)
2235 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2236 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2237 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2238 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2239 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2240 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2241 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2243 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2244 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2247 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2248 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2250 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2251 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2253 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2254 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2257 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2258 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2259 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2260 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2261 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2262 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2263 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2264 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2265 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2266 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2267 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2268 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2269 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2270 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2272 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2273 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2274 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2275 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2276 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2277 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2278 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2279 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2280 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2281 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2282 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2283 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2284 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2285 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2288 // (immediate post-indexed)
2289 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2290 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2291 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2292 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2293 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2294 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2295 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2297 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2298 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2301 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2302 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2304 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2305 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2307 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2308 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2311 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2312 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2313 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2314 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2315 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2316 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2317 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2318 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2319 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2320 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2321 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2322 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2323 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2324 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2326 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2327 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2328 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2329 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2330 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2331 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2332 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2333 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2334 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2335 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2336 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2337 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2338 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2339 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2341 //===----------------------------------------------------------------------===//
2342 // Load/store exclusive instructions.
2343 //===----------------------------------------------------------------------===//
2345 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2346 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2347 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2348 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2350 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2351 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2352 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2353 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2355 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2356 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2357 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2358 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2360 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2361 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2362 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2363 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2365 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2366 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2367 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2368 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2370 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2371 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2372 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2373 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2375 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2376 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2378 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2379 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2381 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2382 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2384 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2385 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2387 let Predicates = [HasV8_1a] in {
2388 // v8.1a "Limited Order Region" extension load-acquire instructions
2389 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2390 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
2391 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2392 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2394 // v8.1a "Limited Order Region" extension store-release instructions
2395 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2396 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
2397 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2398 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2401 //===----------------------------------------------------------------------===//
2402 // Scaled floating point to integer conversion instructions.
2403 //===----------------------------------------------------------------------===//
2405 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2406 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2407 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2408 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2409 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2410 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2411 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2412 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2413 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2414 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2415 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2416 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2417 let isCodeGenOnly = 1 in {
2418 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2419 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2420 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2421 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2424 //===----------------------------------------------------------------------===//
2425 // Scaled integer to floating point conversion instructions.
2426 //===----------------------------------------------------------------------===//
2428 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2429 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2431 //===----------------------------------------------------------------------===//
2432 // Unscaled integer to floating point conversion instruction.
2433 //===----------------------------------------------------------------------===//
2435 defm FMOV : UnscaledConversion<"fmov">;
2437 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2438 let isReMaterializable = 1, isCodeGenOnly = 1 in {
2439 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2440 PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
2442 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2443 PseudoInstExpansion<(FMOVXDr FPR64:$Rd, XZR)>,
2447 //===----------------------------------------------------------------------===//
2448 // Floating point conversion instruction.
2449 //===----------------------------------------------------------------------===//
2451 defm FCVT : FPConversion<"fcvt">;
2453 //===----------------------------------------------------------------------===//
2454 // Floating point single operand instructions.
2455 //===----------------------------------------------------------------------===//
2457 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2458 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2459 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2460 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2461 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2462 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2463 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2464 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2466 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2467 (FRINTNDr FPR64:$Rn)>;
2469 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2470 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2471 // <rdar://problem/13715968>
2472 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2473 let hasSideEffects = 1 in {
2474 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2477 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2479 let SchedRW = [WriteFDiv] in {
2480 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2483 //===----------------------------------------------------------------------===//
2484 // Floating point two operand instructions.
2485 //===----------------------------------------------------------------------===//
2487 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2488 let SchedRW = [WriteFDiv] in {
2489 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2491 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2492 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2493 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2494 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2495 let SchedRW = [WriteFMul] in {
2496 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2497 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2499 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2501 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2502 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2503 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2504 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2505 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2506 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2507 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2508 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2510 //===----------------------------------------------------------------------===//
2511 // Floating point three operand instructions.
2512 //===----------------------------------------------------------------------===//
2514 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2515 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2516 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2517 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2518 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2519 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2520 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2522 // The following def pats catch the case where the LHS of an FMA is negated.
2523 // The TriOpFrag above catches the case where the middle operand is negated.
2525 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2526 // the NEON variant.
2527 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2528 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2530 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2531 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2533 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2535 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2536 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2538 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2539 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2541 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2542 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2544 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2545 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2547 //===----------------------------------------------------------------------===//
2548 // Floating point comparison instructions.
2549 //===----------------------------------------------------------------------===//
2551 defm FCMPE : FPComparison<1, "fcmpe">;
2552 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2554 //===----------------------------------------------------------------------===//
2555 // Floating point conditional comparison instructions.
2556 //===----------------------------------------------------------------------===//
2558 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2559 defm FCCMP : FPCondComparison<0, "fccmp">;
2561 //===----------------------------------------------------------------------===//
2562 // Floating point conditional select instruction.
2563 //===----------------------------------------------------------------------===//
2565 defm FCSEL : FPCondSelect<"fcsel">;
2567 // CSEL instructions providing f128 types need to be handled by a
2568 // pseudo-instruction since the eventual code will need to introduce basic
2569 // blocks and control flow.
2570 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2571 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2572 [(set (f128 FPR128:$Rd),
2573 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2574 (i32 imm:$cond), NZCV))]> {
2576 let usesCustomInserter = 1;
2580 //===----------------------------------------------------------------------===//
2581 // Floating point immediate move.
2582 //===----------------------------------------------------------------------===//
2584 let isReMaterializable = 1 in {
2585 defm FMOV : FPMoveImmediate<"fmov">;
2588 //===----------------------------------------------------------------------===//
2589 // Advanced SIMD two vector instructions.
2590 //===----------------------------------------------------------------------===//
2592 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2593 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2594 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2595 (ABSv8i8 V64:$src)>;
2596 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2597 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2598 (ABSv4i16 V64:$src)>;
2599 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2600 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2601 (ABSv2i32 V64:$src)>;
2602 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2603 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2604 (ABSv16i8 V128:$src)>;
2605 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2606 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2607 (ABSv8i16 V128:$src)>;
2608 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2609 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2610 (ABSv4i32 V128:$src)>;
2611 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2612 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2613 (ABSv2i64 V128:$src)>;
2615 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2616 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2617 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2618 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2619 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2620 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2621 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2622 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2623 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2625 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2626 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2627 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2628 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2629 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2630 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2631 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2632 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2633 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2634 (FCVTLv4i16 V64:$Rn)>;
2635 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2637 (FCVTLv8i16 V128:$Rn)>;
2638 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2639 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2641 (FCVTLv4i32 V128:$Rn)>;
2643 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2644 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2646 (FCVTLv8i16 V128:$Rn)>;
2648 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2649 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2650 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2651 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2652 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2653 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2654 (FCVTNv4i16 V128:$Rn)>;
2655 def : Pat<(concat_vectors V64:$Rd,
2656 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2657 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2658 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2659 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2660 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2661 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2662 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2663 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2664 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2665 int_aarch64_neon_fcvtxn>;
2666 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2667 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2668 let isCodeGenOnly = 1 in {
2669 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2670 int_aarch64_neon_fcvtzs>;
2671 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2672 int_aarch64_neon_fcvtzu>;
2674 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2675 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2676 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2677 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2678 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2679 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2680 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2681 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2682 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2683 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2684 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2685 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2686 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2687 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2688 // Aliases for MVN -> NOT.
2689 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2690 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2691 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2692 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2694 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2695 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2696 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2697 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2698 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2699 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2700 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2702 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2703 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2704 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2705 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2706 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2707 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2708 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2709 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2711 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2712 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2713 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2714 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2715 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2717 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2718 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2719 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2720 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2721 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2722 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2723 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2724 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2725 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2726 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2727 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2728 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2729 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2730 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2731 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2732 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2733 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2734 int_aarch64_neon_uaddlp>;
2735 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2736 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2737 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2738 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2739 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2740 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2742 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2743 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2744 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2745 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2746 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2747 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2749 // Patterns for vector long shift (by element width). These need to match all
2750 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2752 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2753 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2754 (SHLLv8i8 V64:$Rn)>;
2755 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2756 (SHLLv16i8 V128:$Rn)>;
2757 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2758 (SHLLv4i16 V64:$Rn)>;
2759 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2760 (SHLLv8i16 V128:$Rn)>;
2761 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2762 (SHLLv2i32 V64:$Rn)>;
2763 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2764 (SHLLv4i32 V128:$Rn)>;
2767 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2768 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2769 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2771 //===----------------------------------------------------------------------===//
2772 // Advanced SIMD three vector instructions.
2773 //===----------------------------------------------------------------------===//
2775 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2776 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2777 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2778 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2779 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2780 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2781 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2782 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2783 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2784 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2785 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2786 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2787 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2788 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2789 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2790 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2791 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2792 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2793 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2794 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2795 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2796 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2797 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2798 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2799 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2801 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2802 // instruction expects the addend first, while the fma intrinsic puts it last.
2803 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2804 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2805 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2806 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2808 // The following def pats catch the case where the LHS of an FMA is negated.
2809 // The TriOpFrag above catches the case where the middle operand is negated.
2810 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2811 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2813 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2814 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2816 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2817 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2819 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2820 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2821 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2822 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2823 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2824 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2825 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2826 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2827 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2828 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2829 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2830 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2831 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2832 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2833 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2834 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2835 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2836 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2837 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2838 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2839 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2840 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2841 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2842 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2843 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2844 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2845 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2846 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2847 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2848 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2849 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2850 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2851 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2852 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2853 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2854 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2855 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2856 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2857 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2858 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2859 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2860 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2861 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2862 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2863 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2864 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2865 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
2866 int_aarch64_neon_sqadd>;
2867 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
2868 int_aarch64_neon_sqsub>;
2870 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2871 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2872 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2873 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2874 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2875 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2876 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2877 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2878 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2879 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2880 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2882 def : Pat<(v8i8 (smin V64:$Rn, V64:$Rm)),
2883 (SMINv8i8 V64:$Rn, V64:$Rm)>;
2884 def : Pat<(v4i16 (smin V64:$Rn, V64:$Rm)),
2885 (SMINv4i16 V64:$Rn, V64:$Rm)>;
2886 def : Pat<(v2i32 (smin V64:$Rn, V64:$Rm)),
2887 (SMINv2i32 V64:$Rn, V64:$Rm)>;
2888 def : Pat<(v16i8 (smin V128:$Rn, V128:$Rm)),
2889 (SMINv16i8 V128:$Rn, V128:$Rm)>;
2890 def : Pat<(v8i16 (smin V128:$Rn, V128:$Rm)),
2891 (SMINv8i16 V128:$Rn, V128:$Rm)>;
2892 def : Pat<(v4i32 (smin V128:$Rn, V128:$Rm)),
2893 (SMINv4i32 V128:$Rn, V128:$Rm)>;
2894 def : Pat<(v8i8 (smax V64:$Rn, V64:$Rm)),
2895 (SMAXv8i8 V64:$Rn, V64:$Rm)>;
2896 def : Pat<(v4i16 (smax V64:$Rn, V64:$Rm)),
2897 (SMAXv4i16 V64:$Rn, V64:$Rm)>;
2898 def : Pat<(v2i32 (smax V64:$Rn, V64:$Rm)),
2899 (SMAXv2i32 V64:$Rn, V64:$Rm)>;
2900 def : Pat<(v16i8 (smax V128:$Rn, V128:$Rm)),
2901 (SMAXv16i8 V128:$Rn, V128:$Rm)>;
2902 def : Pat<(v8i16 (smax V128:$Rn, V128:$Rm)),
2903 (SMAXv8i16 V128:$Rn, V128:$Rm)>;
2904 def : Pat<(v4i32 (smax V128:$Rn, V128:$Rm)),
2905 (SMAXv4i32 V128:$Rn, V128:$Rm)>;
2906 def : Pat<(v8i8 (umin V64:$Rn, V64:$Rm)),
2907 (UMINv8i8 V64:$Rn, V64:$Rm)>;
2908 def : Pat<(v4i16 (umin V64:$Rn, V64:$Rm)),
2909 (UMINv4i16 V64:$Rn, V64:$Rm)>;
2910 def : Pat<(v2i32 (umin V64:$Rn, V64:$Rm)),
2911 (UMINv2i32 V64:$Rn, V64:$Rm)>;
2912 def : Pat<(v16i8 (umin V128:$Rn, V128:$Rm)),
2913 (UMINv16i8 V128:$Rn, V128:$Rm)>;
2914 def : Pat<(v8i16 (umin V128:$Rn, V128:$Rm)),
2915 (UMINv8i16 V128:$Rn, V128:$Rm)>;
2916 def : Pat<(v4i32 (umin V128:$Rn, V128:$Rm)),
2917 (UMINv4i32 V128:$Rn, V128:$Rm)>;
2918 def : Pat<(v8i8 (umax V64:$Rn, V64:$Rm)),
2919 (UMAXv8i8 V64:$Rn, V64:$Rm)>;
2920 def : Pat<(v4i16 (umax V64:$Rn, V64:$Rm)),
2921 (UMAXv4i16 V64:$Rn, V64:$Rm)>;
2922 def : Pat<(v2i32 (umax V64:$Rn, V64:$Rm)),
2923 (UMAXv2i32 V64:$Rn, V64:$Rm)>;
2924 def : Pat<(v16i8 (umax V128:$Rn, V128:$Rm)),
2925 (UMAXv16i8 V128:$Rn, V128:$Rm)>;
2926 def : Pat<(v8i16 (umax V128:$Rn, V128:$Rm)),
2927 (UMAXv8i16 V128:$Rn, V128:$Rm)>;
2928 def : Pat<(v4i32 (umax V128:$Rn, V128:$Rm)),
2929 (UMAXv4i32 V128:$Rn, V128:$Rm)>;
2931 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2932 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2933 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2934 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2935 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2936 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2937 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2938 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2940 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2941 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2942 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2943 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2944 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2945 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2946 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2947 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2949 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2950 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2951 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2952 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2953 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2954 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2955 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2956 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2958 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2959 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2960 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2961 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2962 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2963 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2964 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2965 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2967 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2968 "|cmls.8b\t$dst, $src1, $src2}",
2969 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2970 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2971 "|cmls.16b\t$dst, $src1, $src2}",
2972 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2973 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2974 "|cmls.4h\t$dst, $src1, $src2}",
2975 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2976 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2977 "|cmls.8h\t$dst, $src1, $src2}",
2978 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2979 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2980 "|cmls.2s\t$dst, $src1, $src2}",
2981 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2982 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2983 "|cmls.4s\t$dst, $src1, $src2}",
2984 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2985 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2986 "|cmls.2d\t$dst, $src1, $src2}",
2987 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2989 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2990 "|cmlo.8b\t$dst, $src1, $src2}",
2991 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2992 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2993 "|cmlo.16b\t$dst, $src1, $src2}",
2994 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2995 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2996 "|cmlo.4h\t$dst, $src1, $src2}",
2997 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2998 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2999 "|cmlo.8h\t$dst, $src1, $src2}",
3000 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3001 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
3002 "|cmlo.2s\t$dst, $src1, $src2}",
3003 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3004 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
3005 "|cmlo.4s\t$dst, $src1, $src2}",
3006 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3007 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
3008 "|cmlo.2d\t$dst, $src1, $src2}",
3009 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3011 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
3012 "|cmle.8b\t$dst, $src1, $src2}",
3013 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3014 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
3015 "|cmle.16b\t$dst, $src1, $src2}",
3016 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3017 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
3018 "|cmle.4h\t$dst, $src1, $src2}",
3019 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3020 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
3021 "|cmle.8h\t$dst, $src1, $src2}",
3022 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3023 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
3024 "|cmle.2s\t$dst, $src1, $src2}",
3025 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3026 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
3027 "|cmle.4s\t$dst, $src1, $src2}",
3028 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3029 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
3030 "|cmle.2d\t$dst, $src1, $src2}",
3031 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3033 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
3034 "|cmlt.8b\t$dst, $src1, $src2}",
3035 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3036 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
3037 "|cmlt.16b\t$dst, $src1, $src2}",
3038 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3039 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
3040 "|cmlt.4h\t$dst, $src1, $src2}",
3041 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3042 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
3043 "|cmlt.8h\t$dst, $src1, $src2}",
3044 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3045 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
3046 "|cmlt.2s\t$dst, $src1, $src2}",
3047 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3048 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
3049 "|cmlt.4s\t$dst, $src1, $src2}",
3050 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3051 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
3052 "|cmlt.2d\t$dst, $src1, $src2}",
3053 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3055 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3056 "|fcmle.2s\t$dst, $src1, $src2}",
3057 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3058 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3059 "|fcmle.4s\t$dst, $src1, $src2}",
3060 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3061 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
3062 "|fcmle.2d\t$dst, $src1, $src2}",
3063 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3065 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
3066 "|fcmlt.2s\t$dst, $src1, $src2}",
3067 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3068 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
3069 "|fcmlt.4s\t$dst, $src1, $src2}",
3070 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3071 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
3072 "|fcmlt.2d\t$dst, $src1, $src2}",
3073 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3075 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
3076 "|facle.2s\t$dst, $src1, $src2}",
3077 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3078 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
3079 "|facle.4s\t$dst, $src1, $src2}",
3080 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3081 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
3082 "|facle.2d\t$dst, $src1, $src2}",
3083 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3085 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
3086 "|faclt.2s\t$dst, $src1, $src2}",
3087 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3088 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
3089 "|faclt.4s\t$dst, $src1, $src2}",
3090 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3091 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
3092 "|faclt.2d\t$dst, $src1, $src2}",
3093 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3095 //===----------------------------------------------------------------------===//
3096 // Advanced SIMD three scalar instructions.
3097 //===----------------------------------------------------------------------===//
3099 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
3100 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
3101 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
3102 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
3103 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
3104 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
3105 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
3106 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
3107 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3108 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
3109 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
3110 int_aarch64_neon_facge>;
3111 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
3112 int_aarch64_neon_facgt>;
3113 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
3114 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
3115 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
3116 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
3117 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
3118 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
3119 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
3120 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
3121 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
3122 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
3123 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
3124 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
3125 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
3126 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
3127 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
3128 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
3129 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
3130 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
3131 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
3132 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3133 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3134 let Predicates = [HasV8_1a] in {
3135 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3136 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3137 def : Pat<(i32 (int_aarch64_neon_sqadd
3139 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3140 (i32 FPR32:$Rm))))),
3141 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3142 def : Pat<(i32 (int_aarch64_neon_sqsub
3144 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3145 (i32 FPR32:$Rm))))),
3146 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3149 def : InstAlias<"cmls $dst, $src1, $src2",
3150 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3151 def : InstAlias<"cmle $dst, $src1, $src2",
3152 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3153 def : InstAlias<"cmlo $dst, $src1, $src2",
3154 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3155 def : InstAlias<"cmlt $dst, $src1, $src2",
3156 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3157 def : InstAlias<"fcmle $dst, $src1, $src2",
3158 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3159 def : InstAlias<"fcmle $dst, $src1, $src2",
3160 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3161 def : InstAlias<"fcmlt $dst, $src1, $src2",
3162 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3163 def : InstAlias<"fcmlt $dst, $src1, $src2",
3164 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3165 def : InstAlias<"facle $dst, $src1, $src2",
3166 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3167 def : InstAlias<"facle $dst, $src1, $src2",
3168 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3169 def : InstAlias<"faclt $dst, $src1, $src2",
3170 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3171 def : InstAlias<"faclt $dst, $src1, $src2",
3172 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3174 //===----------------------------------------------------------------------===//
3175 // Advanced SIMD three scalar instructions (mixed operands).
3176 //===----------------------------------------------------------------------===//
3177 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3178 int_aarch64_neon_sqdmulls_scalar>;
3179 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3180 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3182 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3183 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3184 (i32 FPR32:$Rm))))),
3185 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3186 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3187 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3188 (i32 FPR32:$Rm))))),
3189 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3191 //===----------------------------------------------------------------------===//
3192 // Advanced SIMD two scalar instructions.
3193 //===----------------------------------------------------------------------===//
3195 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3196 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3197 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3198 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3199 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3200 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3201 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3202 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3203 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3204 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3205 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3206 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
3207 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
3208 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
3209 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
3210 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
3211 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
3212 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
3213 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
3214 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3215 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
3216 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
3217 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
3218 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
3219 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
3220 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3221 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3222 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3223 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3224 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3225 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3226 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3227 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3228 int_aarch64_neon_suqadd>;
3229 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3230 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3231 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3232 int_aarch64_neon_usqadd>;
3234 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3236 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3237 (FCVTASv1i64 FPR64:$Rn)>;
3238 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3239 (FCVTAUv1i64 FPR64:$Rn)>;
3240 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3241 (FCVTMSv1i64 FPR64:$Rn)>;
3242 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3243 (FCVTMUv1i64 FPR64:$Rn)>;
3244 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3245 (FCVTNSv1i64 FPR64:$Rn)>;
3246 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3247 (FCVTNUv1i64 FPR64:$Rn)>;
3248 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3249 (FCVTPSv1i64 FPR64:$Rn)>;
3250 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3251 (FCVTPUv1i64 FPR64:$Rn)>;
3253 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3254 (FRECPEv1i32 FPR32:$Rn)>;
3255 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3256 (FRECPEv1i64 FPR64:$Rn)>;
3257 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3258 (FRECPEv1i64 FPR64:$Rn)>;
3260 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3261 (FRECPXv1i32 FPR32:$Rn)>;
3262 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3263 (FRECPXv1i64 FPR64:$Rn)>;
3265 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3266 (FRSQRTEv1i32 FPR32:$Rn)>;
3267 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3268 (FRSQRTEv1i64 FPR64:$Rn)>;
3269 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3270 (FRSQRTEv1i64 FPR64:$Rn)>;
3272 // If an integer is about to be converted to a floating point value,
3273 // just load it on the floating point unit.
3274 // Here are the patterns for 8 and 16-bits to float.
3276 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3277 SDPatternOperator loadop, Instruction UCVTF,
3278 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3280 def : Pat<(DstTy (uint_to_fp (SrcTy
3281 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3282 ro.Wext:$extend))))),
3283 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3284 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3287 def : Pat<(DstTy (uint_to_fp (SrcTy
3288 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3289 ro.Wext:$extend))))),
3290 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3291 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3295 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3296 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3297 def : Pat <(f32 (uint_to_fp (i32
3298 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3299 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3300 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3301 def : Pat <(f32 (uint_to_fp (i32
3302 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3303 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3304 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3305 // 16-bits -> float.
3306 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3307 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3308 def : Pat <(f32 (uint_to_fp (i32
3309 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3310 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3311 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3312 def : Pat <(f32 (uint_to_fp (i32
3313 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3314 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3315 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3316 // 32-bits are handled in target specific dag combine:
3317 // performIntToFpCombine.
3318 // 64-bits integer to 32-bits floating point, not possible with
3319 // UCVTF on floating point registers (both source and destination
3320 // must have the same size).
3322 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3323 // 8-bits -> double.
3324 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3325 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3326 def : Pat <(f64 (uint_to_fp (i32
3327 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3328 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3329 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3330 def : Pat <(f64 (uint_to_fp (i32
3331 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3332 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3333 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3334 // 16-bits -> double.
3335 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3336 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3337 def : Pat <(f64 (uint_to_fp (i32
3338 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3339 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3340 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3341 def : Pat <(f64 (uint_to_fp (i32
3342 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3343 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3344 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3345 // 32-bits -> double.
3346 defm : UIntToFPROLoadPat<f64, i32, load,
3347 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3348 def : Pat <(f64 (uint_to_fp (i32
3349 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3350 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3351 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3352 def : Pat <(f64 (uint_to_fp (i32
3353 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3354 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3355 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3356 // 64-bits -> double are handled in target specific dag combine:
3357 // performIntToFpCombine.
3359 //===----------------------------------------------------------------------===//
3360 // Advanced SIMD three different-sized vector instructions.
3361 //===----------------------------------------------------------------------===//
3363 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3364 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3365 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3366 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3367 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3368 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3369 int_aarch64_neon_sabd>;
3370 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3371 int_aarch64_neon_sabd>;
3372 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3373 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3374 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3375 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3376 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3377 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3378 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3379 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3380 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3381 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3382 int_aarch64_neon_sqadd>;
3383 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3384 int_aarch64_neon_sqsub>;
3385 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3386 int_aarch64_neon_sqdmull>;
3387 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3388 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3389 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3390 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3391 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3392 int_aarch64_neon_uabd>;
3393 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3394 int_aarch64_neon_uabd>;
3395 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3396 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3397 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3398 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3399 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3400 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3401 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3402 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3403 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3404 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3405 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3406 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3407 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3409 // Additional patterns for SMULL and UMULL
3410 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3411 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3412 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3413 (INST8B V64:$Rn, V64:$Rm)>;
3414 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3415 (INST4H V64:$Rn, V64:$Rm)>;
3416 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3417 (INST2S V64:$Rn, V64:$Rm)>;
3420 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3421 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3422 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3423 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3425 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3426 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3427 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3428 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3429 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3430 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3431 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3432 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3433 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3436 defm : Neon_mulacc_widen_patterns<
3437 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3438 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3439 defm : Neon_mulacc_widen_patterns<
3440 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3441 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3442 defm : Neon_mulacc_widen_patterns<
3443 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3444 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3445 defm : Neon_mulacc_widen_patterns<
3446 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3447 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3449 // Patterns for 64-bit pmull
3450 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3451 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3452 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3453 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3454 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3456 // CodeGen patterns for addhn and subhn instructions, which can actually be
3457 // written in LLVM IR without too much difficulty.
3460 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3461 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3462 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3464 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3465 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3467 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3468 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3469 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3471 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3472 V128:$Rn, V128:$Rm)>;
3473 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3474 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3476 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3477 V128:$Rn, V128:$Rm)>;
3478 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3479 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3481 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3482 V128:$Rn, V128:$Rm)>;
3485 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3486 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3487 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3489 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3490 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3492 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3493 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3494 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3496 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3497 V128:$Rn, V128:$Rm)>;
3498 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3499 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3501 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3502 V128:$Rn, V128:$Rm)>;
3503 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3504 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3506 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3507 V128:$Rn, V128:$Rm)>;
3509 //----------------------------------------------------------------------------
3510 // AdvSIMD bitwise extract from vector instruction.
3511 //----------------------------------------------------------------------------
3513 defm EXT : SIMDBitwiseExtract<"ext">;
3515 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3516 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3517 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3518 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3519 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3520 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3521 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3522 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3523 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3524 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3525 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3526 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3527 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3528 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3529 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3530 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3531 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3532 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3533 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3534 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3536 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3538 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3539 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3540 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3541 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3542 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3543 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3544 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3545 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3546 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3547 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3548 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3549 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3550 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3551 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3554 //----------------------------------------------------------------------------
3555 // AdvSIMD zip vector
3556 //----------------------------------------------------------------------------
3558 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3559 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3560 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3561 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3562 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3563 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3565 //----------------------------------------------------------------------------
3566 // AdvSIMD TBL/TBX instructions
3567 //----------------------------------------------------------------------------
3569 defm TBL : SIMDTableLookup< 0, "tbl">;
3570 defm TBX : SIMDTableLookupTied<1, "tbx">;
3572 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3573 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3574 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3575 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3577 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3578 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3579 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3580 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3581 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3582 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3585 //----------------------------------------------------------------------------
3586 // AdvSIMD scalar CPY instruction
3587 //----------------------------------------------------------------------------
3589 defm CPY : SIMDScalarCPY<"cpy">;
3591 //----------------------------------------------------------------------------
3592 // AdvSIMD scalar pairwise instructions
3593 //----------------------------------------------------------------------------
3595 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3596 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3597 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3598 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3599 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3600 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3601 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3602 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3603 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3604 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3605 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3606 (FADDPv2i32p V64:$Rn)>;
3607 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3608 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3609 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3610 (FADDPv2i64p V128:$Rn)>;
3611 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3612 (FMAXNMPv2i32p V64:$Rn)>;
3613 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3614 (FMAXNMPv2i64p V128:$Rn)>;
3615 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3616 (FMAXPv2i32p V64:$Rn)>;
3617 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3618 (FMAXPv2i64p V128:$Rn)>;
3619 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3620 (FMINNMPv2i32p V64:$Rn)>;
3621 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3622 (FMINNMPv2i64p V128:$Rn)>;
3623 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3624 (FMINPv2i32p V64:$Rn)>;
3625 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3626 (FMINPv2i64p V128:$Rn)>;
3628 //----------------------------------------------------------------------------
3629 // AdvSIMD INS/DUP instructions
3630 //----------------------------------------------------------------------------
3632 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
3633 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
3634 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
3635 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
3636 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
3637 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
3638 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
3640 def DUPv2i64lane : SIMDDup64FromElement;
3641 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3642 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3643 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3644 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3645 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3646 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3648 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3649 (v2f32 (DUPv2i32lane
3650 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3652 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3653 (v4f32 (DUPv4i32lane
3654 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3656 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3657 (v2f64 (DUPv2i64lane
3658 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3660 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3661 (v4f16 (DUPv4i16lane
3662 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3664 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3665 (v8f16 (DUPv8i16lane
3666 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3669 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3670 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3671 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3672 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3674 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3675 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3676 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3677 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3678 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3679 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3681 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3682 // instruction even if the types don't match: we just have to remap the lane
3683 // carefully. N.b. this trick only applies to truncations.
3684 def VecIndex_x2 : SDNodeXForm<imm, [{
3685 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
3687 def VecIndex_x4 : SDNodeXForm<imm, [{
3688 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
3690 def VecIndex_x8 : SDNodeXForm<imm, [{
3691 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
3694 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3695 ValueType Src128VT, ValueType ScalVT,
3696 Instruction DUP, SDNodeXForm IdxXFORM> {
3697 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3699 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3701 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3703 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3706 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3707 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3708 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3710 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3711 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3712 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3714 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3715 SDNodeXForm IdxXFORM> {
3716 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3718 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3720 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3722 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3725 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3726 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3727 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3729 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3730 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3731 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3733 // SMOV and UMOV definitions, with some extra patterns for convenience
3737 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3738 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3739 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3740 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3741 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3742 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3743 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3744 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3745 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3746 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3747 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3748 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3750 // Extracting i8 or i16 elements will have the zero-extend transformed to
3751 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3752 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3753 // bits of the destination register.
3754 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3756 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3757 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3759 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3763 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3764 (SUBREG_TO_REG (i32 0),
3765 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3766 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3767 (SUBREG_TO_REG (i32 0),
3768 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3770 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3771 (SUBREG_TO_REG (i32 0),
3772 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3773 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3774 (SUBREG_TO_REG (i32 0),
3775 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3777 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3778 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3779 (i32 FPR32:$Rn), ssub))>;
3780 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3781 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3782 (i32 FPR32:$Rn), ssub))>;
3783 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3784 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3785 (i64 FPR64:$Rn), dsub))>;
3787 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3788 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3789 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3790 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3791 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3792 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3794 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3795 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3798 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3800 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3804 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3805 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3807 V128:$Rn, VectorIndexH:$imm,
3808 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3811 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3812 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3815 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3817 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3820 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3821 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3823 V128:$Rn, VectorIndexS:$imm,
3824 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3826 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3827 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3829 V128:$Rn, VectorIndexD:$imm,
3830 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3833 // Copy an element at a constant index in one vector into a constant indexed
3834 // element of another.
3835 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3836 // index type and INS extension
3837 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3838 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3839 VectorIndexB:$idx2)),
3841 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3843 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3844 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3845 VectorIndexH:$idx2)),
3847 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3849 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3850 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3851 VectorIndexS:$idx2)),
3853 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3855 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3856 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3857 VectorIndexD:$idx2)),
3859 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3862 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3863 ValueType VTScal, Instruction INS> {
3864 def : Pat<(VT128 (vector_insert V128:$src,
3865 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3867 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3869 def : Pat<(VT128 (vector_insert V128:$src,
3870 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3872 (INS V128:$src, imm:$Immd,
3873 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3875 def : Pat<(VT64 (vector_insert V64:$src,
3876 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3878 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3879 imm:$Immd, V128:$Rn, imm:$Immn),
3882 def : Pat<(VT64 (vector_insert V64:$src,
3883 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3886 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3887 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3891 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3892 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3893 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3896 // Floating point vector extractions are codegen'd as either a sequence of
3897 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
3898 // the lane number is anything other than zero.
3899 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3900 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3901 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3902 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3903 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3904 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3906 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3907 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
3908 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3909 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
3910 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3911 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
3913 // All concat_vectors operations are canonicalised to act on i64 vectors for
3914 // AArch64. In the general case we need an instruction, which had just as well be
3916 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3917 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3918 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3919 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3921 def : ConcatPat<v2i64, v1i64>;
3922 def : ConcatPat<v2f64, v1f64>;
3923 def : ConcatPat<v4i32, v2i32>;
3924 def : ConcatPat<v4f32, v2f32>;
3925 def : ConcatPat<v8i16, v4i16>;
3926 def : ConcatPat<v8f16, v4f16>;
3927 def : ConcatPat<v16i8, v8i8>;
3929 // If the high lanes are undef, though, we can just ignore them:
3930 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3931 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3932 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3934 def : ConcatUndefPat<v2i64, v1i64>;
3935 def : ConcatUndefPat<v2f64, v1f64>;
3936 def : ConcatUndefPat<v4i32, v2i32>;
3937 def : ConcatUndefPat<v4f32, v2f32>;
3938 def : ConcatUndefPat<v8i16, v4i16>;
3939 def : ConcatUndefPat<v16i8, v8i8>;
3941 //----------------------------------------------------------------------------
3942 // AdvSIMD across lanes instructions
3943 //----------------------------------------------------------------------------
3945 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3946 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3947 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3948 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3949 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3950 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3951 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3952 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3953 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3954 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3955 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3957 // Patterns for across-vector intrinsics, that have a node equivalent, that
3958 // returns a vector (with only the low lane defined) instead of a scalar.
3959 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
3960 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
3961 SDPatternOperator opNode> {
3962 // If a lane instruction caught the vector_extract around opNode, we can
3963 // directly match the latter to the instruction.
3964 def : Pat<(v8i8 (opNode V64:$Rn)),
3965 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3966 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
3967 def : Pat<(v16i8 (opNode V128:$Rn)),
3968 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3969 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
3970 def : Pat<(v4i16 (opNode V64:$Rn)),
3971 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3972 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
3973 def : Pat<(v8i16 (opNode V128:$Rn)),
3974 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3975 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
3976 def : Pat<(v4i32 (opNode V128:$Rn)),
3977 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3978 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
3981 // If none did, fallback to the explicit patterns, consuming the vector_extract.
3982 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
3983 (i32 0)), (i64 0))),
3984 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3985 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
3987 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
3988 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3989 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
3991 def : Pat<(i32 (vector_extract (insert_subvector undef,
3992 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
3993 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3994 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
3996 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
3997 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3998 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
4000 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
4001 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4002 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
4007 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
4008 SDPatternOperator opNode>
4009 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4010 // If there is a sign extension after this intrinsic, consume it as smov already
4012 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4013 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
4015 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4016 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4018 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4019 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
4021 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4022 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4024 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4025 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
4027 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4028 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4030 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4031 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
4033 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4034 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4038 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
4039 SDPatternOperator opNode>
4040 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4041 // If there is a masking operation keeping only what has been actually
4042 // generated, consume it.
4043 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4044 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
4045 (i32 (EXTRACT_SUBREG
4046 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4047 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4049 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4051 (i32 (EXTRACT_SUBREG
4052 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4053 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4055 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4056 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
4057 (i32 (EXTRACT_SUBREG
4058 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4059 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4061 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4063 (i32 (EXTRACT_SUBREG
4064 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4065 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4069 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
4070 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4071 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
4072 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4074 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
4075 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4076 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
4077 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4079 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
4080 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
4081 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
4083 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
4084 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
4085 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
4087 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
4088 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
4089 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
4091 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
4092 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
4093 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
4095 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
4096 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4098 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4099 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4101 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4103 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4104 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4107 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4108 (i32 (EXTRACT_SUBREG
4109 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4110 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4112 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4113 (i32 (EXTRACT_SUBREG
4114 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4115 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4118 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4119 (i64 (EXTRACT_SUBREG
4120 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4121 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4125 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
4127 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4128 (i32 (EXTRACT_SUBREG
4129 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4130 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4132 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4133 (i32 (EXTRACT_SUBREG
4134 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4135 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4138 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4139 (i32 (EXTRACT_SUBREG
4140 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4141 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4143 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4144 (i32 (EXTRACT_SUBREG
4145 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4146 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4149 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4150 (i64 (EXTRACT_SUBREG
4151 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4152 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4156 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4157 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4159 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4160 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4161 (i64 (EXTRACT_SUBREG
4162 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4163 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4165 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4166 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4167 (i64 (EXTRACT_SUBREG
4168 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4169 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4172 //------------------------------------------------------------------------------
4173 // AdvSIMD modified immediate instructions
4174 //------------------------------------------------------------------------------
4177 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4179 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4181 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4182 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4183 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4184 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4186 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4187 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4188 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4189 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4191 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4192 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4193 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4194 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4196 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4197 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4198 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4199 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4202 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4204 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4205 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4207 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4208 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4210 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4214 // EDIT byte mask: scalar
4215 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4216 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4217 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4218 // The movi_edit node has the immediate value already encoded, so we use
4219 // a plain imm0_255 here.
4220 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4221 (MOVID imm0_255:$shift)>;
4223 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4224 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4225 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4226 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4228 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4229 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4230 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4231 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4233 // EDIT byte mask: 2d
4235 // The movi_edit node has the immediate value already encoded, so we use
4236 // a plain imm0_255 in the pattern
4237 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4238 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4241 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4244 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4245 // Complexity is added to break a tie with a plain MOVI.
4246 let AddedComplexity = 1 in {
4247 def : Pat<(f32 fpimm0),
4248 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4250 def : Pat<(f64 fpimm0),
4251 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4255 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4256 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4257 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4258 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4260 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4261 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4262 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4263 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4265 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4266 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4268 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4269 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4271 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4272 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4273 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4274 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4276 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4277 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4278 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4279 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4281 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4282 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4283 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4284 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4285 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4286 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4287 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4288 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4290 // EDIT per word: 2s & 4s with MSL shifter
4291 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4292 [(set (v2i32 V64:$Rd),
4293 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4294 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4295 [(set (v4i32 V128:$Rd),
4296 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4298 // Per byte: 8b & 16b
4299 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4301 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4302 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4304 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4308 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4309 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4311 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4312 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4313 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4314 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4316 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4317 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4318 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4319 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4321 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4322 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4323 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4324 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4325 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4326 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4327 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4328 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4330 // EDIT per word: 2s & 4s with MSL shifter
4331 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4332 [(set (v2i32 V64:$Rd),
4333 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4334 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4335 [(set (v4i32 V128:$Rd),
4336 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4338 //----------------------------------------------------------------------------
4339 // AdvSIMD indexed element
4340 //----------------------------------------------------------------------------
4342 let hasSideEffects = 0 in {
4343 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4344 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4347 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4348 // instruction expects the addend first, while the intrinsic expects it last.
4350 // On the other hand, there are quite a few valid combinatorial options due to
4351 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4352 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4353 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4354 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4355 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4357 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4358 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4359 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4360 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4361 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4362 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4363 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4364 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4366 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4367 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4369 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4370 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4371 VectorIndexS:$idx))),
4372 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4373 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4374 (v2f32 (AArch64duplane32
4375 (v4f32 (insert_subvector undef,
4376 (v2f32 (fneg V64:$Rm)),
4378 VectorIndexS:$idx)))),
4379 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4380 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4381 VectorIndexS:$idx)>;
4382 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4383 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4384 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4385 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4387 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4389 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4390 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4391 VectorIndexS:$idx))),
4392 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4393 VectorIndexS:$idx)>;
4394 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4395 (v4f32 (AArch64duplane32
4396 (v4f32 (insert_subvector undef,
4397 (v2f32 (fneg V64:$Rm)),
4399 VectorIndexS:$idx)))),
4400 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4401 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4402 VectorIndexS:$idx)>;
4403 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4404 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4405 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4406 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4408 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4409 // (DUPLANE from 64-bit would be trivial).
4410 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4411 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4412 VectorIndexD:$idx))),
4414 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4415 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4416 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4417 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4418 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4420 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4421 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4422 (vector_extract (v4f32 (fneg V128:$Rm)),
4423 VectorIndexS:$idx))),
4424 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4425 V128:$Rm, VectorIndexS:$idx)>;
4426 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4427 (vector_extract (v2f32 (fneg V64:$Rm)),
4428 VectorIndexS:$idx))),
4429 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4430 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4432 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4433 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4434 (vector_extract (v2f64 (fneg V128:$Rm)),
4435 VectorIndexS:$idx))),
4436 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4437 V128:$Rm, VectorIndexS:$idx)>;
4440 defm : FMLSIndexedAfterNegPatterns<
4441 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4442 defm : FMLSIndexedAfterNegPatterns<
4443 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4445 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4446 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4448 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4449 (FMULv2i32_indexed V64:$Rn,
4450 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4452 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4453 (FMULv4i32_indexed V128:$Rn,
4454 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4456 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4457 (FMULv2i64_indexed V128:$Rn,
4458 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4461 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4462 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4463 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4464 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4465 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4466 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4467 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4468 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4469 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4470 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4471 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4472 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4473 int_aarch64_neon_smull>;
4474 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4475 int_aarch64_neon_sqadd>;
4476 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4477 int_aarch64_neon_sqsub>;
4478 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
4479 int_aarch64_neon_sqadd>;
4480 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
4481 int_aarch64_neon_sqsub>;
4482 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4483 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4484 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4485 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4486 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4487 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4488 int_aarch64_neon_umull>;
4490 // A scalar sqdmull with the second operand being a vector lane can be
4491 // handled directly with the indexed instruction encoding.
4492 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4493 (vector_extract (v4i32 V128:$Vm),
4494 VectorIndexS:$idx)),
4495 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4497 //----------------------------------------------------------------------------
4498 // AdvSIMD scalar shift instructions
4499 //----------------------------------------------------------------------------
4500 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4501 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4502 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4503 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4504 // Codegen patterns for the above. We don't put these directly on the
4505 // instructions because TableGen's type inference can't handle the truth.
4506 // Having the same base pattern for fp <--> int totally freaks it out.
4507 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4508 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4509 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4510 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4511 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4512 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4513 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4514 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4515 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4517 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4518 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4520 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4521 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4522 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4523 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4524 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4525 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4526 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4527 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4528 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4529 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4531 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4532 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4534 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4536 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4537 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4538 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4539 int_aarch64_neon_sqrshrn>;
4540 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4541 int_aarch64_neon_sqrshrun>;
4542 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4543 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4544 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4545 int_aarch64_neon_sqshrn>;
4546 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4547 int_aarch64_neon_sqshrun>;
4548 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4549 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4550 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4551 TriOpFrag<(add node:$LHS,
4552 (AArch64srshri node:$MHS, node:$RHS))>>;
4553 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4554 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4555 TriOpFrag<(add node:$LHS,
4556 (AArch64vashr node:$MHS, node:$RHS))>>;
4557 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4558 int_aarch64_neon_uqrshrn>;
4559 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4560 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4561 int_aarch64_neon_uqshrn>;
4562 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4563 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4564 TriOpFrag<(add node:$LHS,
4565 (AArch64urshri node:$MHS, node:$RHS))>>;
4566 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4567 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4568 TriOpFrag<(add node:$LHS,
4569 (AArch64vlshr node:$MHS, node:$RHS))>>;
4571 //----------------------------------------------------------------------------
4572 // AdvSIMD vector shift instructions
4573 //----------------------------------------------------------------------------
4574 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4575 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4576 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4577 int_aarch64_neon_vcvtfxs2fp>;
4578 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4579 int_aarch64_neon_rshrn>;
4580 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4581 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4582 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4583 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4584 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4585 (i32 vecshiftL64:$imm))),
4586 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4587 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4588 int_aarch64_neon_sqrshrn>;
4589 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4590 int_aarch64_neon_sqrshrun>;
4591 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4592 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4593 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4594 int_aarch64_neon_sqshrn>;
4595 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4596 int_aarch64_neon_sqshrun>;
4597 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4598 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4599 (i32 vecshiftR64:$imm))),
4600 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4601 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4602 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4603 TriOpFrag<(add node:$LHS,
4604 (AArch64srshri node:$MHS, node:$RHS))> >;
4605 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4606 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4608 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4609 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4610 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4611 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4612 int_aarch64_neon_vcvtfxu2fp>;
4613 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4614 int_aarch64_neon_uqrshrn>;
4615 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4616 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4617 int_aarch64_neon_uqshrn>;
4618 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4619 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4620 TriOpFrag<(add node:$LHS,
4621 (AArch64urshri node:$MHS, node:$RHS))> >;
4622 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4623 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4624 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4625 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4626 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4628 // SHRN patterns for when a logical right shift was used instead of arithmetic
4629 // (the immediate guarantees no sign bits actually end up in the result so it
4631 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4632 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4633 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4634 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4635 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4636 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4638 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4639 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4640 vecshiftR16Narrow:$imm)))),
4641 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4642 V128:$Rn, vecshiftR16Narrow:$imm)>;
4643 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4644 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4645 vecshiftR32Narrow:$imm)))),
4646 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4647 V128:$Rn, vecshiftR32Narrow:$imm)>;
4648 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4649 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4650 vecshiftR64Narrow:$imm)))),
4651 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4652 V128:$Rn, vecshiftR32Narrow:$imm)>;
4654 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4655 // Anyexts are implemented as zexts.
4656 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4657 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4658 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4659 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4660 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4661 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4662 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4663 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4664 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4665 // Also match an extend from the upper half of a 128 bit source register.
4666 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4667 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4668 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4669 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4670 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4671 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4672 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4673 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4674 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4675 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4676 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4677 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4678 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4679 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4680 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4681 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4682 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4683 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4685 // Vector shift sxtl aliases
4686 def : InstAlias<"sxtl.8h $dst, $src1",
4687 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4688 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4689 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4690 def : InstAlias<"sxtl.4s $dst, $src1",
4691 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4692 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4693 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4694 def : InstAlias<"sxtl.2d $dst, $src1",
4695 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4696 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4697 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4699 // Vector shift sxtl2 aliases
4700 def : InstAlias<"sxtl2.8h $dst, $src1",
4701 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4702 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4703 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4704 def : InstAlias<"sxtl2.4s $dst, $src1",
4705 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4706 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4707 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4708 def : InstAlias<"sxtl2.2d $dst, $src1",
4709 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4710 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4711 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4713 // Vector shift uxtl aliases
4714 def : InstAlias<"uxtl.8h $dst, $src1",
4715 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4716 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4717 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4718 def : InstAlias<"uxtl.4s $dst, $src1",
4719 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4720 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4721 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4722 def : InstAlias<"uxtl.2d $dst, $src1",
4723 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4724 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4725 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4727 // Vector shift uxtl2 aliases
4728 def : InstAlias<"uxtl2.8h $dst, $src1",
4729 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4730 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4731 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4732 def : InstAlias<"uxtl2.4s $dst, $src1",
4733 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4734 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4735 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4736 def : InstAlias<"uxtl2.2d $dst, $src1",
4737 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4738 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4739 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4741 // If an integer is about to be converted to a floating point value,
4742 // just load it on the floating point unit.
4743 // These patterns are more complex because floating point loads do not
4744 // support sign extension.
4745 // The sign extension has to be explicitly added and is only supported for
4746 // one step: byte-to-half, half-to-word, word-to-doubleword.
4747 // SCVTF GPR -> FPR is 9 cycles.
4748 // SCVTF FPR -> FPR is 4 cyclces.
4749 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4750 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4751 // and still being faster.
4752 // However, this is not good for code size.
4753 // 8-bits -> float. 2 sizes step-up.
4754 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4755 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4756 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4761 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4767 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4769 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4770 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4771 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4772 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4773 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4774 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4775 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4776 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4778 // 16-bits -> float. 1 size step-up.
4779 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4780 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4781 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4783 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4787 ssub)))>, Requires<[NotForCodeSize]>;
4789 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4790 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4791 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4792 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4793 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4794 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4795 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4796 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4798 // 32-bits to 32-bits are handled in target specific dag combine:
4799 // performIntToFpCombine.
4800 // 64-bits integer to 32-bits floating point, not possible with
4801 // SCVTF on floating point registers (both source and destination
4802 // must have the same size).
4804 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4805 // 8-bits -> double. 3 size step-up: give up.
4806 // 16-bits -> double. 2 size step.
4807 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4808 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4809 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4814 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4820 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4822 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4823 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4824 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4825 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4826 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4827 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4828 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4829 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4830 // 32-bits -> double. 1 size step-up.
4831 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4832 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4833 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4835 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4839 dsub)))>, Requires<[NotForCodeSize]>;
4841 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4842 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4843 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4844 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4845 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4846 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4847 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4848 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4850 // 64-bits -> double are handled in target specific dag combine:
4851 // performIntToFpCombine.
4854 //----------------------------------------------------------------------------
4855 // AdvSIMD Load-Store Structure
4856 //----------------------------------------------------------------------------
4857 defm LD1 : SIMDLd1Multiple<"ld1">;
4858 defm LD2 : SIMDLd2Multiple<"ld2">;
4859 defm LD3 : SIMDLd3Multiple<"ld3">;
4860 defm LD4 : SIMDLd4Multiple<"ld4">;
4862 defm ST1 : SIMDSt1Multiple<"st1">;
4863 defm ST2 : SIMDSt2Multiple<"st2">;
4864 defm ST3 : SIMDSt3Multiple<"st3">;
4865 defm ST4 : SIMDSt4Multiple<"st4">;
4867 class Ld1Pat<ValueType ty, Instruction INST>
4868 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4870 def : Ld1Pat<v16i8, LD1Onev16b>;
4871 def : Ld1Pat<v8i16, LD1Onev8h>;
4872 def : Ld1Pat<v4i32, LD1Onev4s>;
4873 def : Ld1Pat<v2i64, LD1Onev2d>;
4874 def : Ld1Pat<v8i8, LD1Onev8b>;
4875 def : Ld1Pat<v4i16, LD1Onev4h>;
4876 def : Ld1Pat<v2i32, LD1Onev2s>;
4877 def : Ld1Pat<v1i64, LD1Onev1d>;
4879 class St1Pat<ValueType ty, Instruction INST>
4880 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4881 (INST ty:$Vt, GPR64sp:$Rn)>;
4883 def : St1Pat<v16i8, ST1Onev16b>;
4884 def : St1Pat<v8i16, ST1Onev8h>;
4885 def : St1Pat<v4i32, ST1Onev4s>;
4886 def : St1Pat<v2i64, ST1Onev2d>;
4887 def : St1Pat<v8i8, ST1Onev8b>;
4888 def : St1Pat<v4i16, ST1Onev4h>;
4889 def : St1Pat<v2i32, ST1Onev2s>;
4890 def : St1Pat<v1i64, ST1Onev1d>;
4896 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4897 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4898 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4899 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4900 let mayLoad = 1, hasSideEffects = 0 in {
4901 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4902 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4903 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4904 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4905 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4906 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4907 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4908 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4909 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4910 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4911 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4912 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4913 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4914 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4915 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4916 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4919 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4920 (LD1Rv8b GPR64sp:$Rn)>;
4921 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4922 (LD1Rv16b GPR64sp:$Rn)>;
4923 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4924 (LD1Rv4h GPR64sp:$Rn)>;
4925 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4926 (LD1Rv8h GPR64sp:$Rn)>;
4927 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4928 (LD1Rv2s GPR64sp:$Rn)>;
4929 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4930 (LD1Rv4s GPR64sp:$Rn)>;
4931 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4932 (LD1Rv2d GPR64sp:$Rn)>;
4933 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4934 (LD1Rv1d GPR64sp:$Rn)>;
4935 // Grab the floating point version too
4936 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4937 (LD1Rv2s GPR64sp:$Rn)>;
4938 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4939 (LD1Rv4s GPR64sp:$Rn)>;
4940 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4941 (LD1Rv2d GPR64sp:$Rn)>;
4942 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4943 (LD1Rv1d GPR64sp:$Rn)>;
4944 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4945 (LD1Rv4h GPR64sp:$Rn)>;
4946 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4947 (LD1Rv8h GPR64sp:$Rn)>;
4949 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4950 ValueType VTy, ValueType STy, Instruction LD1>
4951 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4952 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4953 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4955 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4956 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4957 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4958 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4959 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4960 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4961 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4963 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4964 ValueType VTy, ValueType STy, Instruction LD1>
4965 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4966 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4968 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4969 VecIndex:$idx, GPR64sp:$Rn),
4972 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4973 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4974 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4975 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4976 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4979 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4980 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4981 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4982 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4985 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4986 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4987 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4988 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4990 let AddedComplexity = 19 in
4991 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4992 ValueType VTy, ValueType STy, Instruction ST1>
4994 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4996 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4998 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4999 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
5000 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
5001 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
5002 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
5003 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
5004 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
5006 let AddedComplexity = 19 in
5007 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5008 ValueType VTy, ValueType STy, Instruction ST1>
5010 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5012 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5013 VecIndex:$idx, GPR64sp:$Rn)>;
5015 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
5016 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
5017 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
5018 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
5019 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
5021 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5022 ValueType VTy, ValueType STy, Instruction ST1,
5024 def : Pat<(scalar_store
5025 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5026 GPR64sp:$Rn, offset),
5027 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5028 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5030 def : Pat<(scalar_store
5031 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5032 GPR64sp:$Rn, GPR64:$Rm),
5033 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5034 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5037 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
5038 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
5040 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
5041 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
5042 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
5043 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
5044 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
5046 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5047 ValueType VTy, ValueType STy, Instruction ST1,
5049 def : Pat<(scalar_store
5050 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5051 GPR64sp:$Rn, offset),
5052 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5054 def : Pat<(scalar_store
5055 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5056 GPR64sp:$Rn, GPR64:$Rm),
5057 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5060 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
5062 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
5064 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
5065 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
5066 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
5067 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
5068 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
5070 let mayStore = 1, hasSideEffects = 0 in {
5071 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
5072 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
5073 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5074 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5075 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
5076 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
5077 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5078 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5079 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
5080 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
5081 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
5082 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
5085 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
5086 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
5087 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
5088 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
5090 //----------------------------------------------------------------------------
5091 // Crypto extensions
5092 //----------------------------------------------------------------------------
5094 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
5095 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
5096 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
5097 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
5099 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
5100 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
5101 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
5102 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
5103 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
5104 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
5105 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
5107 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
5108 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
5109 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
5111 //----------------------------------------------------------------------------
5113 //----------------------------------------------------------------------------
5114 // FIXME: Like for X86, these should go in their own separate .td file.
5116 // Any instruction that defines a 32-bit result leaves the high half of the
5117 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
5118 // be copying from a truncate. But any other 32-bit operation will zero-extend
5120 // FIXME: X86 also checks for CMOV here. Do we need something similar?
5121 def def32 : PatLeaf<(i32 GPR32:$src), [{
5122 return N->getOpcode() != ISD::TRUNCATE &&
5123 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
5124 N->getOpcode() != ISD::CopyFromReg;
5127 // In the case of a 32-bit def that is known to implicitly zero-extend,
5128 // we can use a SUBREG_TO_REG.
5129 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
5131 // For an anyext, we don't care what the high bits are, so we can perform an
5132 // INSERT_SUBREF into an IMPLICIT_DEF.
5133 def : Pat<(i64 (anyext GPR32:$src)),
5134 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5136 // When we need to explicitly zero-extend, we use an unsigned bitfield move
5137 // instruction (UBFM) on the enclosing super-reg.
5138 def : Pat<(i64 (zext GPR32:$src)),
5139 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5141 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5142 // containing super-reg.
5143 def : Pat<(i64 (sext GPR32:$src)),
5144 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5145 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5146 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5147 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5148 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5149 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5150 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5151 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5153 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5154 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5155 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5156 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5157 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5158 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5160 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5161 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5162 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5163 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5164 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5165 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5167 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5168 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5169 (i64 (i64shift_a imm0_63:$imm)),
5170 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5172 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5173 // AddedComplexity for the following patterns since we want to match sext + sra
5174 // patterns before we attempt to match a single sra node.
5175 let AddedComplexity = 20 in {
5176 // We support all sext + sra combinations which preserve at least one bit of the
5177 // original value which is to be sign extended. E.g. we support shifts up to
5179 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5180 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5181 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5182 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5184 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5185 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5186 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5187 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5189 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5190 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5191 (i64 imm0_31:$imm), 31)>;
5192 } // AddedComplexity = 20
5194 // To truncate, we can simply extract from a subregister.
5195 def : Pat<(i32 (trunc GPR64sp:$src)),
5196 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5198 // __builtin_trap() uses the BRK instruction on AArch64.
5199 def : Pat<(trap), (BRK 1)>;
5201 // Conversions within AdvSIMD types in the same register size are free.
5202 // But because we need a consistent lane ordering, in big endian many
5203 // conversions require one or more REV instructions.
5205 // Consider a simple memory load followed by a bitconvert then a store.
5207 // v1 = BITCAST v2i32 v0 to v4i16
5210 // In big endian mode every memory access has an implicit byte swap. LDR and
5211 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5212 // is, they treat the vector as a sequence of elements to be byte-swapped.
5213 // The two pairs of instructions are fundamentally incompatible. We've decided
5214 // to use LD1/ST1 only to simplify compiler implementation.
5216 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5217 // the original code sequence:
5219 // v1 = REV v2i32 (implicit)
5220 // v2 = BITCAST v2i32 v1 to v4i16
5221 // v3 = REV v4i16 v2 (implicit)
5224 // But this is now broken - the value stored is different to the value loaded
5225 // due to lane reordering. To fix this, on every BITCAST we must perform two
5228 // v1 = REV v2i32 (implicit)
5230 // v3 = BITCAST v2i32 v2 to v4i16
5232 // v5 = REV v4i16 v4 (implicit)
5235 // This means an extra two instructions, but actually in most cases the two REV
5236 // instructions can be combined into one. For example:
5237 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5239 // There is also no 128-bit REV instruction. This must be synthesized with an
5242 // Most bitconverts require some sort of conversion. The only exceptions are:
5243 // a) Identity conversions - vNfX <-> vNiX
5244 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5247 // Natural vector casts (64 bit)
5248 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5249 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5250 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5251 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5252 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5253 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5255 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5256 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5257 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5258 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5259 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5261 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5262 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5263 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5264 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5265 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5267 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5268 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5269 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5270 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5271 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5272 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5273 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5275 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5276 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5277 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5278 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5279 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5281 // Natural vector casts (128 bit)
5282 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5283 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5284 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5285 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5286 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5287 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5288 def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5290 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5291 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5292 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5293 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5294 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5295 def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5296 def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5298 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5299 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5300 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5301 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5302 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5303 def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5304 def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5306 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5307 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5308 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5309 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5310 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5311 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5312 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5314 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5315 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5316 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5317 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5318 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5319 def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5320 def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5322 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5323 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5324 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5325 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5326 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5327 def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5328 def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5330 let Predicates = [IsLE] in {
5331 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5332 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5333 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5334 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5335 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5337 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5338 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5339 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5340 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5341 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5342 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5343 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5344 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5345 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5346 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5347 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5348 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5350 let Predicates = [IsBE] in {
5351 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5352 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5353 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5354 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5355 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5356 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5357 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5358 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5359 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5360 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5362 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5363 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5364 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5365 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5366 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5367 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5368 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5369 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5370 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5371 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5373 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5374 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5375 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5376 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5377 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5378 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5379 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5380 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5381 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5383 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5384 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5385 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5386 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5387 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5388 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5389 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5390 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5391 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5392 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5394 let Predicates = [IsLE] in {
5395 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5396 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5397 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5398 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5399 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5401 let Predicates = [IsBE] in {
5402 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5403 (v1i64 (REV64v2i32 FPR64:$src))>;
5404 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5405 (v1i64 (REV64v4i16 FPR64:$src))>;
5406 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5407 (v1i64 (REV64v8i8 FPR64:$src))>;
5408 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5409 (v1i64 (REV64v4i16 FPR64:$src))>;
5410 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5411 (v1i64 (REV64v2i32 FPR64:$src))>;
5413 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5414 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5416 let Predicates = [IsLE] in {
5417 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5418 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5419 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5420 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5421 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5422 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5424 let Predicates = [IsBE] in {
5425 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5426 (v2i32 (REV64v2i32 FPR64:$src))>;
5427 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5428 (v2i32 (REV32v4i16 FPR64:$src))>;
5429 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5430 (v2i32 (REV32v8i8 FPR64:$src))>;
5431 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5432 (v2i32 (REV64v2i32 FPR64:$src))>;
5433 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5434 (v2i32 (REV64v2i32 FPR64:$src))>;
5435 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5436 (v2i32 (REV64v4i16 FPR64:$src))>;
5438 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5440 let Predicates = [IsLE] in {
5441 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5442 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5443 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5444 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5445 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5446 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5447 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5449 let Predicates = [IsBE] in {
5450 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5451 (v4i16 (REV64v4i16 FPR64:$src))>;
5452 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5453 (v4i16 (REV32v4i16 FPR64:$src))>;
5454 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5455 (v4i16 (REV16v8i8 FPR64:$src))>;
5456 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5457 (v4i16 (REV64v4i16 FPR64:$src))>;
5458 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5459 (v4i16 (REV32v4i16 FPR64:$src))>;
5460 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5461 (v4i16 (REV32v4i16 FPR64:$src))>;
5462 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5463 (v4i16 (REV64v4i16 FPR64:$src))>;
5466 let Predicates = [IsLE] in {
5467 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5468 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5469 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5470 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5471 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5472 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5473 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5475 let Predicates = [IsBE] in {
5476 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5477 (v4f16 (REV64v4i16 FPR64:$src))>;
5478 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5479 (v4f16 (REV64v4i16 FPR64:$src))>;
5480 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5481 (v4f16 (REV64v4i16 FPR64:$src))>;
5482 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5483 (v4f16 (REV16v8i8 FPR64:$src))>;
5484 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5485 (v4f16 (REV64v4i16 FPR64:$src))>;
5486 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5487 (v4f16 (REV64v4i16 FPR64:$src))>;
5488 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5489 (v4f16 (REV64v4i16 FPR64:$src))>;
5494 let Predicates = [IsLE] in {
5495 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5496 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5497 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5498 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5499 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5500 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5501 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5503 let Predicates = [IsBE] in {
5504 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5505 (v8i8 (REV64v8i8 FPR64:$src))>;
5506 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5507 (v8i8 (REV32v8i8 FPR64:$src))>;
5508 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5509 (v8i8 (REV16v8i8 FPR64:$src))>;
5510 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5511 (v8i8 (REV64v8i8 FPR64:$src))>;
5512 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5513 (v8i8 (REV32v8i8 FPR64:$src))>;
5514 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5515 (v8i8 (REV64v8i8 FPR64:$src))>;
5516 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5517 (v8i8 (REV16v8i8 FPR64:$src))>;
5520 let Predicates = [IsLE] in {
5521 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5522 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5523 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5524 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5525 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5527 let Predicates = [IsBE] in {
5528 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5529 (f64 (REV64v2i32 FPR64:$src))>;
5530 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5531 (f64 (REV64v4i16 FPR64:$src))>;
5532 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5533 (f64 (REV64v2i32 FPR64:$src))>;
5534 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5535 (f64 (REV64v8i8 FPR64:$src))>;
5536 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5537 (f64 (REV64v4i16 FPR64:$src))>;
5539 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5540 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5542 let Predicates = [IsLE] in {
5543 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5544 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5545 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5546 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5547 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5549 let Predicates = [IsBE] in {
5550 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5551 (v1f64 (REV64v2i32 FPR64:$src))>;
5552 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5553 (v1f64 (REV64v4i16 FPR64:$src))>;
5554 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5555 (v1f64 (REV64v8i8 FPR64:$src))>;
5556 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5557 (v1f64 (REV64v2i32 FPR64:$src))>;
5558 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5559 (v1f64 (REV64v4i16 FPR64:$src))>;
5561 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5562 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5564 let Predicates = [IsLE] in {
5565 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5566 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5567 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5568 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5569 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5570 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5572 let Predicates = [IsBE] in {
5573 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5574 (v2f32 (REV64v2i32 FPR64:$src))>;
5575 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5576 (v2f32 (REV32v4i16 FPR64:$src))>;
5577 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5578 (v2f32 (REV32v8i8 FPR64:$src))>;
5579 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5580 (v2f32 (REV64v2i32 FPR64:$src))>;
5581 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5582 (v2f32 (REV64v2i32 FPR64:$src))>;
5583 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5584 (v2f32 (REV64v4i16 FPR64:$src))>;
5586 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5588 let Predicates = [IsLE] in {
5589 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5590 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5591 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5592 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5593 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5594 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5595 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5597 let Predicates = [IsBE] in {
5598 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5599 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5600 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5601 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5602 (REV64v4i32 FPR128:$src), (i32 8)))>;
5603 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5604 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5605 (REV64v8i16 FPR128:$src), (i32 8)))>;
5606 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5607 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5608 (REV64v8i16 FPR128:$src), (i32 8)))>;
5609 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5610 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5611 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5612 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5613 (REV64v4i32 FPR128:$src), (i32 8)))>;
5614 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5615 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5616 (REV64v16i8 FPR128:$src), (i32 8)))>;
5619 let Predicates = [IsLE] in {
5620 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5621 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5622 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5623 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5624 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5625 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5627 let Predicates = [IsBE] in {
5628 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5629 (v2f64 (EXTv16i8 FPR128:$src,
5630 FPR128:$src, (i32 8)))>;
5631 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5632 (v2f64 (REV64v4i32 FPR128:$src))>;
5633 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5634 (v2f64 (REV64v8i16 FPR128:$src))>;
5635 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5636 (v2f64 (REV64v8i16 FPR128:$src))>;
5637 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5638 (v2f64 (REV64v16i8 FPR128:$src))>;
5639 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5640 (v2f64 (REV64v4i32 FPR128:$src))>;
5642 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5644 let Predicates = [IsLE] in {
5645 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5646 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5647 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5648 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5649 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5650 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5652 let Predicates = [IsBE] in {
5653 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5654 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5655 (REV64v4i32 FPR128:$src), (i32 8)))>;
5656 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5657 (v4f32 (REV32v8i16 FPR128:$src))>;
5658 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5659 (v4f32 (REV32v8i16 FPR128:$src))>;
5660 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5661 (v4f32 (REV32v16i8 FPR128:$src))>;
5662 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5663 (v4f32 (REV64v4i32 FPR128:$src))>;
5664 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5665 (v4f32 (REV64v4i32 FPR128:$src))>;
5667 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5669 let Predicates = [IsLE] in {
5670 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5671 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5672 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5673 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5674 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5675 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5677 let Predicates = [IsBE] in {
5678 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5679 (v2i64 (EXTv16i8 FPR128:$src,
5680 FPR128:$src, (i32 8)))>;
5681 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5682 (v2i64 (REV64v4i32 FPR128:$src))>;
5683 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5684 (v2i64 (REV64v8i16 FPR128:$src))>;
5685 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5686 (v2i64 (REV64v16i8 FPR128:$src))>;
5687 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5688 (v2i64 (REV64v4i32 FPR128:$src))>;
5689 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5690 (v2i64 (REV64v8i16 FPR128:$src))>;
5692 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5694 let Predicates = [IsLE] in {
5695 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5696 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5697 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5698 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5699 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5700 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5702 let Predicates = [IsBE] in {
5703 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5704 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5705 (REV64v4i32 FPR128:$src),
5707 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5708 (v4i32 (REV64v4i32 FPR128:$src))>;
5709 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5710 (v4i32 (REV32v8i16 FPR128:$src))>;
5711 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5712 (v4i32 (REV32v16i8 FPR128:$src))>;
5713 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5714 (v4i32 (REV64v4i32 FPR128:$src))>;
5715 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5716 (v4i32 (REV32v8i16 FPR128:$src))>;
5718 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5720 let Predicates = [IsLE] in {
5721 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5722 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5723 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5724 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5725 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5726 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5727 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5729 let Predicates = [IsBE] in {
5730 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5731 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5732 (REV64v8i16 FPR128:$src),
5734 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5735 (v8i16 (REV64v8i16 FPR128:$src))>;
5736 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5737 (v8i16 (REV32v8i16 FPR128:$src))>;
5738 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5739 (v8i16 (REV16v16i8 FPR128:$src))>;
5740 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5741 (v8i16 (REV64v8i16 FPR128:$src))>;
5742 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5743 (v8i16 (REV32v8i16 FPR128:$src))>;
5744 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5745 (v8i16 (REV32v8i16 FPR128:$src))>;
5748 let Predicates = [IsLE] in {
5749 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5750 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5751 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5752 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5753 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5754 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5755 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5757 let Predicates = [IsBE] in {
5758 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5759 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5760 (REV64v8i16 FPR128:$src),
5762 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5763 (v8f16 (REV64v8i16 FPR128:$src))>;
5764 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5765 (v8f16 (REV32v8i16 FPR128:$src))>;
5766 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5767 (v8f16 (REV64v8i16 FPR128:$src))>;
5768 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5769 (v8f16 (REV16v16i8 FPR128:$src))>;
5770 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5771 (v8f16 (REV64v8i16 FPR128:$src))>;
5772 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5773 (v8f16 (REV32v8i16 FPR128:$src))>;
5776 let Predicates = [IsLE] in {
5777 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5778 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5779 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5780 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5781 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5782 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5783 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5785 let Predicates = [IsBE] in {
5786 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5787 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5788 (REV64v16i8 FPR128:$src),
5790 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5791 (v16i8 (REV64v16i8 FPR128:$src))>;
5792 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5793 (v16i8 (REV32v16i8 FPR128:$src))>;
5794 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5795 (v16i8 (REV16v16i8 FPR128:$src))>;
5796 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5797 (v16i8 (REV64v16i8 FPR128:$src))>;
5798 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5799 (v16i8 (REV32v16i8 FPR128:$src))>;
5800 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5801 (v16i8 (REV16v16i8 FPR128:$src))>;
5804 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5805 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5806 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5807 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5808 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5809 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5810 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5811 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5813 // A 64-bit subvector insert to the first 128-bit vector position
5814 // is a subregister copy that needs no instruction.
5815 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5816 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5817 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5818 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5819 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5820 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5821 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5822 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5823 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5824 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5825 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5826 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5827 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5828 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5830 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5832 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5833 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5834 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5835 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5836 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5837 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5838 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5839 // so we match on v4f32 here, not v2f32. This will also catch adding
5840 // the low two lanes of a true v4f32 vector.
5841 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5842 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5843 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5845 // Scalar 64-bit shifts in FPR64 registers.
5846 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5847 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5848 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5849 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5850 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5851 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5852 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5853 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5855 // Tail call return handling. These are all compiler pseudo-instructions,
5856 // so no encoding information or anything like that.
5857 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5858 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5859 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5862 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5863 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5864 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5865 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5866 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5867 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5869 include "AArch64InstrAtomics.td"