1 //===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 scalar instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto","crypto">;
24 // Use fused MAC if more precision in FP computation is allowed.
25 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
26 " FPOpFusion::Fast)">;
27 include "AArch64InstrFormats.td"
29 //===----------------------------------------------------------------------===//
30 // AArch64 specific pattern fragments.
32 // An 'fmul' node with a single use.
33 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
34 return N->hasOneUse();
38 //===----------------------------------------------------------------------===//
39 // Target-specific ISD nodes and profiles
40 //===----------------------------------------------------------------------===//
42 def SDT_A64ret : SDTypeProfile<0, 0, []>;
43 def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
47 // (ins NZCV, Condition, Dest)
48 def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;
49 def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>;
51 // (outs Result), (ins NZCV, IfTrue, IfFalse, Condition)
52 def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>,
55 def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>;
57 // (outs NZCV), (ins LHS, RHS, Condition)
58 def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
60 def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>;
63 // (outs GPR64), (ins)
64 def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
66 // A64 compares don't care about the cond really (they set all flags) so a
67 // simple binary operator is useful.
68 def A64cmp : PatFrag<(ops node:$lhs, node:$rhs),
69 (A64setcc node:$lhs, node:$rhs, cond)>;
72 // When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN
73 // instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C
74 // and V flags can be set differently by this operation. It comes down to
75 // whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are
76 // then everything is fine. If not then the optimization is wrong. Thus general
77 // comparisons are only valid if op2 != 0.
79 // So, finally, the only LLVM-native comparisons that don't mention C and V are
80 // SETEQ and SETNE. They're the only ones we can safely use CMN for in the
81 // absence of information about op2.
82 def equality_cond : PatLeaf<(cond), [{
83 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE;
86 def A64cmn : PatFrag<(ops node:$lhs, node:$rhs),
87 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>;
89 // There are two layers of indirection here, driven by the following
91 // + TableGen does not know CodeModel or Reloc so that decision should be
92 // made for a variable/address at ISelLowering.
93 // + The output of ISelLowering should be selectable (hence the Wrapper,
94 // rather than a bare target opcode)
95 def SDTAArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
101 def A64WrapperLarge :SDNode<"AArch64ISD::WrapperLarge", SDTAArch64WrapperLarge>;
103 def SDTAArch64WrapperSmall : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
108 def A64WrapperSmall :SDNode<"AArch64ISD::WrapperSmall", SDTAArch64WrapperSmall>;
111 def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
112 def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad,
116 // (A64BFI LHS, RHS, LSB, Width)
117 def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
122 def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>;
124 // (A64EXTR HiReg, LoReg, LSB)
125 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
127 def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
129 // (A64[SU]BFX Field, ImmR, ImmS).
131 // Note that ImmR and ImmS are already encoded for the actual instructions. The
132 // more natural LSB and Width mix together to form ImmR and ImmS, something
133 // which TableGen can't handle.
134 def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
135 def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>;
137 def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
139 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
141 //===----------------------------------------------------------------------===//
142 // Call sequence pseudo-instructions
143 //===----------------------------------------------------------------------===//
146 def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
147 def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
150 def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call,
151 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
153 // The TLSDESCCALL node is a variant call which goes to an indirectly calculated
154 // destination but needs a relocation against a fixed symbol. As such it has two
155 // certain operands: the callee and the relocated variable.
157 // The TLS ABI only allows it to be selected to a BLR instructin (with
158 // appropriate relocation).
159 def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
161 def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
162 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
166 def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
167 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart,
168 [SDNPHasChain, SDNPOutGlue]>;
170 def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>;
171 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd,
172 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
176 // These pseudo-instructions have special semantics by virtue of being passed to
177 // the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by
178 // LowerCall to (in our case) tell the back-end about stack adjustments for
179 // arguments passed on the stack. Here we select those markers to
180 // pseudo-instructions which explicitly set the stack, and finally in the
181 // RegisterInfo we convert them to a true stack adjustment.
182 let Defs = [XSP], Uses = [XSP] in {
183 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
184 [(AArch64callseq_start timm:$amt)]>;
186 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2),
187 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
190 //===----------------------------------------------------------------------===//
191 // Atomic operation pseudo-instructions
192 //===----------------------------------------------------------------------===//
194 // These get selected from C++ code as a pretty much direct translation from the
195 // generic DAG nodes. The one exception is the AtomicOrdering is added as an
196 // operand so that the eventual lowering can make use of it and choose
197 // acquire/release operations when required.
199 let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in {
200 multiclass AtomicSizes {
201 def _I8 : PseudoInst<(outs GPR32:$dst),
202 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
203 def _I16 : PseudoInst<(outs GPR32:$dst),
204 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
205 def _I32 : PseudoInst<(outs GPR32:$dst),
206 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
207 def _I64 : PseudoInst<(outs GPR64:$dst),
208 (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>;
212 defm ATOMIC_LOAD_ADD : AtomicSizes;
213 defm ATOMIC_LOAD_SUB : AtomicSizes;
214 defm ATOMIC_LOAD_AND : AtomicSizes;
215 defm ATOMIC_LOAD_OR : AtomicSizes;
216 defm ATOMIC_LOAD_XOR : AtomicSizes;
217 defm ATOMIC_LOAD_NAND : AtomicSizes;
218 defm ATOMIC_SWAP : AtomicSizes;
219 let Defs = [NZCV] in {
220 // These operations need a CMP to calculate the correct value
221 defm ATOMIC_LOAD_MIN : AtomicSizes;
222 defm ATOMIC_LOAD_MAX : AtomicSizes;
223 defm ATOMIC_LOAD_UMIN : AtomicSizes;
224 defm ATOMIC_LOAD_UMAX : AtomicSizes;
227 class AtomicCmpSwap<RegisterClass GPRData>
228 : PseudoInst<(outs GPRData:$dst),
229 (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new,
230 i32imm:$ordering), []> {
231 let usesCustomInserter = 1;
238 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>;
239 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>;
240 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>;
241 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>;
243 //===----------------------------------------------------------------------===//
244 // Add-subtract (extended register) instructions
245 //===----------------------------------------------------------------------===//
246 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP
248 // The RHS of these operations is conceptually a sign/zero-extended
249 // register, optionally shifted left by 1-4. The extension can be a
250 // NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but
251 // must be specified with one exception:
253 // If one of the registers is sp/wsp then LSL is an alias for UXTW in
254 // 32-bit instructions and UXTX in 64-bit versions, the shift amount
255 // is not optional in that case (but can explicitly be 0), and the
256 // entire suffix can be skipped (e.g. "add sp, x3, x2").
258 multiclass extend_operands<string PREFIX, string Diag> {
259 def _asmoperand : AsmOperandClass {
261 let RenderMethod = "addRegExtendOperands";
262 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
263 let DiagnosticType = "AddSubRegExtend" # Diag;
266 def _operand : Operand<i64>,
267 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
268 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
269 let DecoderMethod = "DecodeRegExtendOperand";
270 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
274 defm UXTB : extend_operands<"UXTB", "Small">;
275 defm UXTH : extend_operands<"UXTH", "Small">;
276 defm UXTW : extend_operands<"UXTW", "Small">;
277 defm UXTX : extend_operands<"UXTX", "Large">;
278 defm SXTB : extend_operands<"SXTB", "Small">;
279 defm SXTH : extend_operands<"SXTH", "Small">;
280 defm SXTW : extend_operands<"SXTW", "Small">;
281 defm SXTX : extend_operands<"SXTX", "Large">;
283 def LSL_extasmoperand : AsmOperandClass {
284 let Name = "RegExtendLSL";
285 let RenderMethod = "addRegExtendOperands";
286 let DiagnosticType = "AddSubRegExtendLarge";
289 def LSL_extoperand : Operand<i64> {
290 let ParserMatchClass = LSL_extasmoperand;
294 // The patterns for various sign-extensions are a little ugly and
295 // non-uniform because everything has already been promoted to the
296 // legal i64 and i32 types. We'll wrap the various variants up in a
297 // class for use later.
299 dag uxtb; dag uxth; dag uxtw; dag uxtx;
300 dag sxtb; dag sxth; dag sxtw; dag sxtx;
305 def extends_to_i64 : extend_types {
306 let uxtb = (and (anyext i32:$Rm), 255);
307 let uxth = (and (anyext i32:$Rm), 65535);
308 let uxtw = (zext i32:$Rm);
309 let uxtx = (i64 $Rm);
311 let sxtb = (sext_inreg (anyext i32:$Rm), i8);
312 let sxth = (sext_inreg (anyext i32:$Rm), i16);
313 let sxtw = (sext i32:$Rm);
314 let sxtx = (i64 $Rm);
321 def extends_to_i32 : extend_types {
322 let uxtb = (and i32:$Rm, 255);
323 let uxth = (and i32:$Rm, 65535);
324 let uxtw = (i32 i32:$Rm);
325 let uxtx = (i32 i32:$Rm);
327 let sxtb = (sext_inreg i32:$Rm, i8);
328 let sxth = (sext_inreg i32:$Rm, i16);
329 let sxtw = (i32 i32:$Rm);
330 let sxtx = (i32 i32:$Rm);
336 // Now, six of the extensions supported are easy and uniform: if the source size
337 // is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate
338 // those instructions in one block.
340 // The uxtx/sxtx could potentially be merged in, but three facts dissuaded me:
341 // + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would
343 // + Patterns are very different as well.
344 // + Passing different registers would be ugly (more fields in extend_types
345 // would probably be the best option).
346 multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
347 SDPatternOperator opfrag,
348 dag outs, extend_types exts> {
349 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
350 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
351 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
352 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
354 Sched<[WriteALU, ReadALU, ReadALU]>;
355 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
356 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
357 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
358 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
360 Sched<[WriteALU, ReadALU, ReadALU]>;
361 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
362 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
363 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
364 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
366 Sched<[WriteALU, ReadALU, ReadALU]>;
368 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
369 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
370 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
371 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
373 Sched<[WriteALU, ReadALU, ReadALU]>;
374 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
375 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
376 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
377 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
379 Sched<[WriteALU, ReadALU, ReadALU]>;
380 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
381 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
382 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
383 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
385 Sched<[WriteALU, ReadALU, ReadALU]>;
388 // These two could be merge in with the above, but their patterns aren't really
389 // necessary and the naming-scheme would necessarily break:
390 multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
392 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
394 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
395 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
396 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
398 Sched<[WriteALU, ReadALU, ReadALU]>;
400 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
402 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
403 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
404 [/* No Pattern: same as uxtx */],
406 Sched<[WriteALU, ReadALU, ReadALU]>;
409 multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
410 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
411 outs, (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
412 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
413 [/* No pattern: probably same as uxtw */],
415 Sched<[WriteALU, ReadALU, ReadALU]>;
417 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
418 outs, (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
419 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
420 [/* No Pattern: probably same as uxtw */],
422 Sched<[WriteALU, ReadALU, ReadALU]>;
425 class SetRD<RegisterClass RC, SDPatternOperator op>
426 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>;
427 class SetNZCV<SDPatternOperator op>
428 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
430 defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
431 (outs GPR64xsp:$Rd), extends_to_i64>,
432 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
433 (outs GPR64xsp:$Rd)>;
434 defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>,
435 (outs GPR32wsp:$Rd), extends_to_i32>,
436 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ",
437 (outs GPR32wsp:$Rd)>;
438 defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
439 (outs GPR64xsp:$Rd), extends_to_i64>,
440 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
441 (outs GPR64xsp:$Rd)>;
442 defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>,
443 (outs GPR32wsp:$Rd), extends_to_i32>,
444 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ",
445 (outs GPR32wsp:$Rd)>;
447 let Defs = [NZCV] in {
448 defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
449 (outs GPR64:$Rd), extends_to_i64>,
450 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
452 defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>,
453 (outs GPR32:$Rd), extends_to_i32>,
454 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ",
456 defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
457 (outs GPR64:$Rd), extends_to_i64>,
458 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
460 defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
461 (outs GPR32:$Rd), extends_to_i32>,
462 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ",
466 let SchedRW = [WriteCMP, ReadCMP, ReadCMP], Rd = 0b11111, isCompare = 1 in {
467 defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
468 (outs), extends_to_i64>,
469 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
470 defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
471 (outs), extends_to_i32>,
472 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
473 defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
474 (outs), extends_to_i64>,
475 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>;
476 defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
477 (outs), extends_to_i32>,
478 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>;
482 // Now patterns for the operation without a shift being needed. No patterns are
483 // created for uxtx/sxtx since they're non-uniform and it's expected that
484 // add/sub (shifted register) will handle those cases anyway.
485 multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
487 def : Pat<(nodeop exts.ty:$Rn, exts.uxtb),
488 (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>;
489 def : Pat<(nodeop exts.ty:$Rn, exts.uxth),
490 (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>;
491 def : Pat<(nodeop exts.ty:$Rn, exts.uxtw),
492 (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>;
494 def : Pat<(nodeop exts.ty:$Rn, exts.sxtb),
495 (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>;
496 def : Pat<(nodeop exts.ty:$Rn, exts.sxth),
497 (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>;
498 def : Pat<(nodeop exts.ty:$Rn, exts.sxtw),
499 (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>;
502 defm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>;
503 defm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>;
504 defm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>;
505 defm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>;
507 defm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>;
508 defm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>;
509 defm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>;
510 defm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>;
512 // An extend of "lsl #imm" is valid if and only if one of Rn and Rd is
513 // sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the
514 // operation. Also permitted in this case is complete omission of the argument,
515 // which implies "lsl #0".
516 multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
517 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
518 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
519 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
521 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"),
522 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
526 defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
527 defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
528 defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>;
529 defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>;
530 defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
531 defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
532 defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>;
533 defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>;
535 // Rd cannot be sp for flag-setting variants so only half of the aliases are
537 defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>;
538 defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>;
539 defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>;
540 defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>;
542 // CMP unfortunately has to be different because the instruction doesn't have a
544 multiclass cmp_lsl_aliases<string asmop, Instruction inst,
545 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
546 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
547 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
549 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"),
550 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
553 defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>;
554 defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>;
555 defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>;
556 defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>;
558 //===----------------------------------------------------------------------===//
559 // Add-subtract (immediate) instructions
560 //===----------------------------------------------------------------------===//
561 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV
563 // These instructions accept a 12-bit unsigned immediate, optionally shifted
564 // left by 12 bits. Official assembly format specifies a 12 bit immediate with
565 // one of "", "LSL #0", "LSL #12" supplementary operands.
567 // There are surprisingly few ways to make this work with TableGen, so this
568 // implementation has separate instructions for the "LSL #0" and "LSL #12"
571 // If the MCInst retained a single combined immediate (which could be 0x123000,
572 // for example) then both components (imm & shift) would have to be delegated to
573 // a single assembly operand. This would entail a separate operand parser
574 // (because the LSL would have to live in the same AArch64Operand as the
575 // immediate to be accessible); assembly parsing is rather complex and
576 // error-prone C++ code.
578 // By splitting the immediate, we can delegate handling this optional operand to
579 // an InstAlias. Supporting functions to generate the correct MCInst are still
580 // required, but these are essentially trivial and parsing can remain generic.
582 // Rejected plans with rationale:
583 // ------------------------------
585 // In an ideal world you'de have two first class immediate operands (in
586 // InOperandList, specifying imm12 and shift). Unfortunately this is not
587 // selectable by any means I could discover.
589 // An Instruction with two MCOperands hidden behind a single entry in
590 // InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional,
591 // but required more C++ code to handle encoding/decoding. Parsing (the intended
592 // main beneficiary) ended up equally complex because of the optional nature of
595 // Attempting to circumvent the need for a custom OperandParser above by giving
596 // InstAliases without the "lsl #0" failed. add/sub could be accommodated but
597 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands
598 // should be parsed: there was no way to accommodate an "lsl #12".
600 let ParserMethod = "ParseImmWithLSLOperand",
601 RenderMethod = "addImmWithLSLOperands" in {
602 // Derived PredicateMethod fields are different for each
603 def addsubimm_lsl0_asmoperand : AsmOperandClass {
604 let Name = "AddSubImmLSL0";
605 // If an error is reported against this operand, instruction could also be a
607 let DiagnosticType = "AddSubSecondSource";
610 def addsubimm_lsl12_asmoperand : AsmOperandClass {
611 let Name = "AddSubImmLSL12";
612 let DiagnosticType = "AddSubSecondSource";
616 def shr_12_XFORM : SDNodeXForm<imm, [{
617 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32);
620 def shr_12_neg_XFORM : SDNodeXForm<imm, [{
621 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32);
624 def neg_XFORM : SDNodeXForm<imm, [{
625 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32);
629 multiclass addsub_imm_operands<ValueType ty> {
630 let PrintMethod = "printAddSubImmLSL0Operand",
631 EncoderMethod = "getAddSubImmOpValue",
632 ParserMatchClass = addsubimm_lsl0_asmoperand in {
633 def _posimm_lsl0 : Operand<ty>,
634 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
635 def _negimm_lsl0 : Operand<ty>,
636 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }],
640 let PrintMethod = "printAddSubImmLSL12Operand",
641 EncoderMethod = "getAddSubImmOpValue",
642 ParserMatchClass = addsubimm_lsl12_asmoperand in {
643 def _posimm_lsl12 : Operand<ty>,
644 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
647 def _negimm_lsl12 : Operand<ty>,
648 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }],
653 // The add operands don't need any transformation
654 defm addsubimm_operand_i32 : addsub_imm_operands<i32>;
655 defm addsubimm_operand_i64 : addsub_imm_operands<i64>;
657 multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift,
658 string asmop, string cmpasmop,
659 Operand imm_operand, Operand cmp_imm_operand,
660 RegisterClass GPR, RegisterClass GPRsp,
661 AArch64Reg ZR, ValueType Ty> {
662 // All registers for non-S variants allow SP
663 def _s : A64I_addsubimm<sf, op, 0b0, shift,
665 (ins GPRsp:$Rn, imm_operand:$Imm12),
666 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
667 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
669 Sched<[WriteALU, ReadALU]>;
672 // S variants can read SP but would write to ZR
673 def _S : A64I_addsubimm<sf, op, 0b1, shift,
675 (ins GPRsp:$Rn, imm_operand:$Imm12),
676 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
677 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
679 Sched<[WriteALU, ReadALU]> {
683 // Note that the pattern here for ADDS is subtle. Canonically CMP
684 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to
685 // ADDS a, (-b). This is not true in general.
686 def _cmp : A64I_addsubimm<sf, op, 0b1, shift,
687 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
688 !strconcat(cmpasmop, " $Rn, $Imm12"),
690 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
692 Sched<[WriteCMP, ReadCMP]> {
700 multiclass addsubimm_shifts<string prefix, bit sf, bit op,
701 string asmop, string cmpasmop, string operand, string cmpoperand,
702 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR,
704 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
706 !cast<Operand>(operand # "_lsl0"),
707 !cast<Operand>(cmpoperand # "_lsl0"),
710 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01,
712 !cast<Operand>(operand # "_lsl12"),
713 !cast<Operand>(cmpoperand # "_lsl12"),
717 defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
718 "addsubimm_operand_i32_posimm",
719 "addsubimm_operand_i32_negimm",
720 GPR32, GPR32wsp, WZR, i32>;
721 defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
722 "addsubimm_operand_i64_posimm",
723 "addsubimm_operand_i64_negimm",
724 GPR64, GPR64xsp, XZR, i64>;
725 defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp",
726 "addsubimm_operand_i32_negimm",
727 "addsubimm_operand_i32_posimm",
728 GPR32, GPR32wsp, WZR, i32>;
729 defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp",
730 "addsubimm_operand_i64_negimm",
731 "addsubimm_operand_i64_posimm",
732 GPR64, GPR64xsp, XZR, i64>;
734 multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
735 def _fromsp : InstAlias<"mov $Rd, $Rn",
736 (addop GPRsp:$Rd, SP:$Rn, 0),
739 def _tosp : InstAlias<"mov $Rd, $Rn",
740 (addop SP:$Rd, GPRsp:$Rn, 0),
744 // Recall Rxsp is a RegisterClass containing *just* xsp.
745 defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>;
746 defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>;
748 //===----------------------------------------------------------------------===//
749 // Add-subtract (shifted register) instructions
750 //===----------------------------------------------------------------------===//
751 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
753 //===-------------------------------
754 // 1. The "shifted register" operands. Shared with logical insts.
755 //===-------------------------------
757 multiclass shift_operands<string prefix, string form> {
758 def _asmoperand_i32 : AsmOperandClass {
759 let Name = "Shift" # form # "i32";
760 let RenderMethod = "addShiftOperands";
761 let PredicateMethod = "isShift<A64SE::" # form # ", false>";
762 let DiagnosticType = "AddSubRegShift32";
765 // Note that the operand type is intentionally i64 because the DAGCombiner
766 // puts these into a canonical form.
767 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
769 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
770 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
771 let DecoderMethod = "Decode32BitShiftOperand";
774 def _asmoperand_i64 : AsmOperandClass {
775 let Name = "Shift" # form # "i64";
776 let RenderMethod = "addShiftOperands";
777 let PredicateMethod = "isShift<A64SE::" # form # ", true>";
778 let DiagnosticType = "AddSubRegShift64";
781 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
783 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
784 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
788 defm lsl_operand : shift_operands<"lsl_operand", "LSL">;
789 defm lsr_operand : shift_operands<"lsr_operand", "LSR">;
790 defm asr_operand : shift_operands<"asr_operand", "ASR">;
792 // Not used for add/sub, but defined here for completeness. The "logical
793 // (shifted register)" instructions *do* have an ROR variant.
794 defm ror_operand : shift_operands<"ror_operand", "ROR">;
796 //===-------------------------------
797 // 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions.
798 //===-------------------------------
800 // N.b. the commutable parameter is just !N. It will be first against the wall
801 // when the revolution comes.
802 multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
803 string asmop, SDPatternOperator opfrag, ValueType ty,
804 RegisterClass GPR, list<Register> defs> {
805 let isCommutable = commutable, Defs = defs in {
806 def _lsl : A64I_addsubshift<sf, op, s, 0b00,
808 (ins GPR:$Rn, GPR:$Rm,
809 !cast<Operand>("lsl_operand_" # ty):$Imm6),
810 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
811 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
812 !cast<Operand>("lsl_operand_" # ty):$Imm6))
815 Sched<[WriteALU, ReadALU]>;
817 def _lsr : A64I_addsubshift<sf, op, s, 0b01,
819 (ins GPR:$Rn, GPR:$Rm,
820 !cast<Operand>("lsr_operand_" # ty):$Imm6),
821 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
822 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
823 !cast<Operand>("lsr_operand_" # ty):$Imm6))
826 Sched<[WriteALU, ReadALU]>;
828 def _asr : A64I_addsubshift<sf, op, s, 0b10,
830 (ins GPR:$Rn, GPR:$Rm,
831 !cast<Operand>("asr_operand_" # ty):$Imm6),
832 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
833 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
834 !cast<Operand>("asr_operand_" # ty):$Imm6))
837 Sched<[WriteALU, ReadALU]>;
841 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
842 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
845 def : Pat<(opfrag ty:$Rn, ty:$Rm),
846 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
849 multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
850 string asmop, SDPatternOperator opfrag,
851 list<Register> defs> {
852 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
853 commutable, asmop, opfrag, i64, GPR64, defs>;
854 defm www : addsub_shifts<prefix # "www", 0b0, op, s,
855 commutable, asmop, opfrag, i32, GPR32, defs>;
859 defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>;
860 defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>;
862 defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>;
863 defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>;
865 //===-------------------------------
866 // 1. The NEG/NEGS aliases
867 //===-------------------------------
869 multiclass neg_alias<Instruction INST, RegisterClass GPR, Register ZR,
870 ValueType ty, Operand shift_operand, SDNode shiftop> {
871 def : InstAlias<"neg $Rd, $Rm, $Imm6",
872 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
874 def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)),
875 (INST ZR, $Rm, shift_operand:$Imm6)>;
878 defm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>;
879 defm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>;
880 defm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>;
881 def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
882 def : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>;
884 defm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>;
885 defm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>;
886 defm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>;
887 def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
888 def : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>;
890 // NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to
892 class negs_alias<Instruction INST, RegisterClass GPR,
893 Register ZR, Operand shift_operand, SDNode shiftop>
894 : InstAlias<"negs $Rd, $Rm, $Imm6",
895 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
897 def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
898 def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
899 def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>;
900 def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
902 def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
903 def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
904 def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
905 def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
907 //===-------------------------------
908 // 1. The CMP/CMN aliases
909 //===-------------------------------
911 multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
912 string asmop, SDPatternOperator opfrag, ValueType ty,
914 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
915 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
917 (ins GPR:$Rn, GPR:$Rm,
918 !cast<Operand>("lsl_operand_" # ty):$Imm6),
919 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
920 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
921 !cast<Operand>("lsl_operand_" # ty):$Imm6))
924 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
926 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
928 (ins GPR:$Rn, GPR:$Rm,
929 !cast<Operand>("lsr_operand_" # ty):$Imm6),
930 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
931 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
932 !cast<Operand>("lsr_operand_" # ty):$Imm6))
935 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
937 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
939 (ins GPR:$Rn, GPR:$Rm,
940 !cast<Operand>("asr_operand_" # ty):$Imm6),
941 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
942 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
943 !cast<Operand>("asr_operand_" # ty):$Imm6))
946 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
950 : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
951 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
953 def : Pat<(opfrag ty:$Rn, ty:$Rm),
954 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
957 defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>;
958 defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>;
960 defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>;
961 defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>;
963 //===----------------------------------------------------------------------===//
964 // Add-subtract (with carry) instructions
965 //===----------------------------------------------------------------------===//
966 // Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
968 multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
969 let Uses = [NZCV] in {
970 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
971 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
972 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
974 Sched<[WriteALU, ReadALU, ReadALU]>;
976 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
977 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
978 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
980 Sched<[WriteALU, ReadALU, ReadALU]>;
984 let isCommutable = 1 in {
985 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
988 defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
990 let Defs = [NZCV] in {
991 let isCommutable = 1 in {
992 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
995 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">;
998 def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>;
999 def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
1000 def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>;
1001 def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
1003 // Note that adde and sube can form a chain longer than two (e.g. for 256-bit
1004 // addition). So the flag-setting instructions are appropriate.
1005 def : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>;
1006 def : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>;
1007 def : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>;
1008 def : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>;
1010 //===----------------------------------------------------------------------===//
1012 //===----------------------------------------------------------------------===//
1013 // Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL,
1016 // Because of the rather complicated nearly-overlapping aliases, the decoding of
1017 // this range of instructions is handled manually. The architectural
1018 // instructions are BFM, SBFM and UBFM but a disassembler should never produce
1021 // In the end, the best option was to use BFM instructions for decoding under
1022 // almost all circumstances, but to create aliasing *Instructions* for each of
1023 // the canonical forms and specify a completely custom decoder which would
1024 // substitute the correct MCInst as needed.
1026 // This also simplifies instruction selection, parsing etc because the MCInsts
1027 // have a shape that's closer to their use in code.
1029 //===-------------------------------
1030 // 1. The architectural BFM instructions
1031 //===-------------------------------
1033 def uimm5_asmoperand : AsmOperandClass {
1035 let PredicateMethod = "isUImm<5>";
1036 let RenderMethod = "addImmOperands";
1037 let DiagnosticType = "UImm5";
1040 def uimm6_asmoperand : AsmOperandClass {
1042 let PredicateMethod = "isUImm<6>";
1043 let RenderMethod = "addImmOperands";
1044 let DiagnosticType = "UImm6";
1047 def bitfield32_imm : Operand<i64>,
1048 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
1049 let ParserMatchClass = uimm5_asmoperand;
1051 let DecoderMethod = "DecodeBitfield32ImmOperand";
1055 def bitfield64_imm : Operand<i64>,
1056 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
1057 let ParserMatchClass = uimm6_asmoperand;
1059 // Default decoder works in 64-bit case: the 6-bit field can take any value.
1062 multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
1063 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1064 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1065 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1067 Sched<[WriteALU, ReadALU]> {
1068 let DecoderMethod = "DecodeBitfieldInstruction";
1071 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1072 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1073 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1075 Sched<[WriteALU, ReadALU]> {
1076 let DecoderMethod = "DecodeBitfieldInstruction";
1080 defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">;
1081 defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">;
1083 // BFM instructions modify the destination register rather than defining it
1086 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1087 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1088 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1089 Sched<[WriteALU, ReadALU, ReadALU]> {
1090 let DecoderMethod = "DecodeBitfieldInstruction";
1091 let Constraints = "$src = $Rd";
1095 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1096 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1097 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1098 Sched<[WriteALU, ReadALU, ReadALU]> {
1099 let DecoderMethod = "DecodeBitfieldInstruction";
1100 let Constraints = "$src = $Rd";
1104 //===-------------------------------
1105 // 2. Extend aliases to 64-bit dest
1106 //===-------------------------------
1108 // Unfortunately the extensions that end up as 64-bits cannot be handled by an
1109 // instruction alias: their syntax is (for example) "SXTB x0, w0", which needs
1110 // to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is
1111 // not capable of such a map as far as I'm aware
1113 // Note that these instructions are strictly more specific than the
1114 // BFM ones (in ImmR) so they can handle their own decoding.
1115 class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty,
1116 string asmop, bits<6> imms, dag pattern>
1117 : A64I_bitfield<sf, opc, sf,
1118 (outs GPRDest:$Rd), (ins GPR32:$Rn),
1119 !strconcat(asmop, "\t$Rd, $Rn"),
1120 [(set dty:$Rd, pattern)], NoItinerary>,
1121 Sched<[WriteALU, ReadALU]> {
1122 let ImmR = 0b000000;
1126 // Signed extensions
1127 def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7,
1128 (sext_inreg (anyext i32:$Rn), i8)>;
1129 def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7,
1130 (sext_inreg i32:$Rn, i8)>;
1131 def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15,
1132 (sext_inreg (anyext i32:$Rn), i16)>;
1133 def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15,
1134 (sext_inreg i32:$Rn, i16)>;
1135 def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>;
1137 // Unsigned extensions
1138 def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7,
1139 (and i32:$Rn, 255)>;
1140 def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15,
1141 (and i32:$Rn, 65535)>;
1143 // The 64-bit unsigned variants are not strictly architectural but recommended
1145 let isAsmParserOnly = 1 in {
1146 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7,
1147 (and (anyext i32:$Rn), 255)>;
1148 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15,
1149 (and (anyext i32:$Rn), 65535)>;
1152 // Extra patterns for when the source register is actually 64-bits
1153 // too. There's no architectural difference here, it's just LLVM
1154 // shinanigans. There's no need for equivalent zero-extension patterns
1155 // because they'll already be caught by logical (immediate) matching.
1156 def : Pat<(sext_inreg i64:$Rn, i8),
1157 (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>;
1158 def : Pat<(sext_inreg i64:$Rn, i16),
1159 (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>;
1160 def : Pat<(sext_inreg i64:$Rn, i32),
1161 (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>;
1164 //===-------------------------------
1165 // 3. Aliases for ASR and LSR (the simple shifts)
1166 //===-------------------------------
1168 // These also handle their own decoding because ImmS being set makes
1169 // them take precedence over BFM.
1170 multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
1171 def wwi : A64I_bitfield<0b0, opc, 0b0,
1172 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
1173 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1174 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
1176 Sched<[WriteALU, ReadALU]> {
1180 def xxi : A64I_bitfield<0b1, opc, 0b1,
1181 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
1182 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1183 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
1185 Sched<[WriteALU, ReadALU]> {
1191 defm ASR : A64I_shift<0b00, "asr", sra>;
1192 defm LSR : A64I_shift<0b10, "lsr", srl>;
1194 //===-------------------------------
1195 // 4. Aliases for LSL
1196 //===-------------------------------
1198 // Unfortunately LSL and subsequent aliases are much more complicated. We need
1199 // to be able to say certain output instruction fields depend in a complex
1200 // manner on combinations of input assembly fields).
1202 // MIOperandInfo *might* have been able to do it, but at the cost of
1203 // significantly more C++ code.
1205 // N.b. contrary to usual practice these operands store the shift rather than
1206 // the machine bits in an MCInst. The complexity overhead of consistency
1207 // outweighed the benefits in this case (custom asmparser, printer and selection
1208 // vs custom encoder).
1209 def bitfield32_lsl_imm : Operand<i64>,
1210 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1211 let ParserMatchClass = uimm5_asmoperand;
1212 let EncoderMethod = "getBitfield32LSLOpValue";
1215 def bitfield64_lsl_imm : Operand<i64>,
1216 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1217 let ParserMatchClass = uimm6_asmoperand;
1218 let EncoderMethod = "getBitfield64LSLOpValue";
1221 class A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty,
1223 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
1224 "lsl\t$Rd, $Rn, $FullImm",
1225 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
1227 Sched<[WriteALU, ReadALU]> {
1229 let ImmR = FullImm{5-0};
1230 let ImmS = FullImm{11-6};
1232 // No disassembler allowed because it would overlap with BFM which does the
1234 let isAsmParserOnly = 1;
1237 def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>;
1238 def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>;
1240 //===-------------------------------
1241 // 5. Aliases for bitfield extract instructions
1242 //===-------------------------------
1244 def bfx32_width_asmoperand : AsmOperandClass {
1245 let Name = "BFX32Width";
1246 let PredicateMethod = "isBitfieldWidth<32>";
1247 let RenderMethod = "addBFXWidthOperands";
1248 let DiagnosticType = "Width32";
1251 def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
1252 let PrintMethod = "printBFXWidthOperand";
1253 let ParserMatchClass = bfx32_width_asmoperand;
1256 def bfx64_width_asmoperand : AsmOperandClass {
1257 let Name = "BFX64Width";
1258 let PredicateMethod = "isBitfieldWidth<64>";
1259 let RenderMethod = "addBFXWidthOperands";
1260 let DiagnosticType = "Width64";
1263 def bfx64_width : Operand<i64> {
1264 let PrintMethod = "printBFXWidthOperand";
1265 let ParserMatchClass = bfx64_width_asmoperand;
1269 multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
1270 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1271 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1272 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1273 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
1275 Sched<[WriteALU, ReadALU]> {
1276 // As above, no disassembler allowed.
1277 let isAsmParserOnly = 1;
1280 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1281 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1282 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1283 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
1285 Sched<[WriteALU, ReadALU]> {
1286 // As above, no disassembler allowed.
1287 let isAsmParserOnly = 1;
1291 defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>;
1292 defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
1294 // Again, variants based on BFM modify Rd so need it as an input too.
1295 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1296 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1297 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1298 Sched<[WriteALU, ReadALU, ReadALU]> {
1299 // As above, no disassembler allowed.
1300 let isAsmParserOnly = 1;
1301 let Constraints = "$src = $Rd";
1304 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1305 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1306 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1307 Sched<[WriteALU, ReadALU, ReadALU]> {
1308 // As above, no disassembler allowed.
1309 let isAsmParserOnly = 1;
1310 let Constraints = "$src = $Rd";
1313 // SBFX instructions can do a 1-instruction sign-extension of boolean values.
1314 def : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>;
1315 def : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>;
1316 def : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)),
1317 (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>;
1319 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
1320 // use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
1321 def : Pat<(i64 (zext i32:$Rn)), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31),
1324 //===-------------------------------
1325 // 6. Aliases for bitfield insert instructions
1326 //===-------------------------------
1328 def bfi32_lsb_asmoperand : AsmOperandClass {
1329 let Name = "BFI32LSB";
1330 let PredicateMethod = "isUImm<5>";
1331 let RenderMethod = "addBFILSBOperands<32>";
1332 let DiagnosticType = "UImm5";
1335 def bfi32_lsb : Operand<i64>,
1336 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1337 let PrintMethod = "printBFILSBOperand<32>";
1338 let ParserMatchClass = bfi32_lsb_asmoperand;
1341 def bfi64_lsb_asmoperand : AsmOperandClass {
1342 let Name = "BFI64LSB";
1343 let PredicateMethod = "isUImm<6>";
1344 let RenderMethod = "addBFILSBOperands<64>";
1345 let DiagnosticType = "UImm6";
1348 def bfi64_lsb : Operand<i64>,
1349 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1350 let PrintMethod = "printBFILSBOperand<64>";
1351 let ParserMatchClass = bfi64_lsb_asmoperand;
1354 // Width verification is performed during conversion so width operand can be
1355 // shared between 32/64-bit cases. Still needed for the print method though
1356 // because ImmR encodes "width - 1".
1357 def bfi32_width_asmoperand : AsmOperandClass {
1358 let Name = "BFI32Width";
1359 let PredicateMethod = "isBitfieldWidth<32>";
1360 let RenderMethod = "addBFIWidthOperands";
1361 let DiagnosticType = "Width32";
1364 def bfi32_width : Operand<i64>,
1365 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
1366 let PrintMethod = "printBFIWidthOperand";
1367 let ParserMatchClass = bfi32_width_asmoperand;
1370 def bfi64_width_asmoperand : AsmOperandClass {
1371 let Name = "BFI64Width";
1372 let PredicateMethod = "isBitfieldWidth<64>";
1373 let RenderMethod = "addBFIWidthOperands";
1374 let DiagnosticType = "Width64";
1377 def bfi64_width : Operand<i64>,
1378 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
1379 let PrintMethod = "printBFIWidthOperand";
1380 let ParserMatchClass = bfi64_width_asmoperand;
1383 multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
1384 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1385 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1386 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1388 Sched<[WriteALU, ReadALU]> {
1389 // As above, no disassembler allowed.
1390 let isAsmParserOnly = 1;
1393 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1394 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1395 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1397 Sched<[WriteALU, ReadALU]> {
1398 // As above, no disassembler allowed.
1399 let isAsmParserOnly = 1;
1403 defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">;
1404 defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">;
1407 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1408 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1409 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1410 Sched<[WriteALU, ReadALU, ReadALU]> {
1411 // As above, no disassembler allowed.
1412 let isAsmParserOnly = 1;
1413 let Constraints = "$src = $Rd";
1416 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1417 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1418 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1419 Sched<[WriteALU, ReadALU, ReadALU]> {
1420 // As above, no disassembler allowed.
1421 let isAsmParserOnly = 1;
1422 let Constraints = "$src = $Rd";
1425 //===----------------------------------------------------------------------===//
1426 // Compare and branch (immediate)
1427 //===----------------------------------------------------------------------===//
1428 // Contains: CBZ, CBNZ
1430 class label_asmoperand<int width, int scale> : AsmOperandClass {
1431 let Name = "Label" # width # "_" # scale;
1432 let PredicateMethod = "isLabel<" # width # "," # scale # ">";
1433 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
1434 let DiagnosticType = "Label";
1437 def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>;
1439 // All conditional immediate branches are the same really: 19 signed bits scaled
1440 // by the instruction-size (4).
1441 def bcc_target : Operand<OtherVT> {
1442 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
1443 let ParserMatchClass = label_wid19_scal4_asmoperand;
1444 let PrintMethod = "printLabelOperand<19, 4>";
1445 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>";
1446 let OperandType = "OPERAND_PCREL";
1449 multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
1450 let isBranch = 1, isTerminator = 1 in {
1451 def x : A64I_cmpbr<0b1, op,
1453 (ins GPR64:$Rt, bcc_target:$Label),
1454 !strconcat(asmop,"\t$Rt, $Label"),
1455 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
1457 Sched<[WriteBr, ReadBr]>;
1459 def w : A64I_cmpbr<0b0, op,
1461 (ins GPR32:$Rt, bcc_target:$Label),
1462 !strconcat(asmop,"\t$Rt, $Label"),
1463 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
1465 Sched<[WriteBr, ReadBr]>;
1469 defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{
1470 return Imm == A64CC::EQ;
1472 defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{
1473 return Imm == A64CC::NE;
1476 //===----------------------------------------------------------------------===//
1477 // Conditional branch (immediate) instructions
1478 //===----------------------------------------------------------------------===//
1481 def cond_code_asmoperand : AsmOperandClass {
1482 let Name = "CondCode";
1483 let DiagnosticType = "CondCode";
1486 def cond_code : Operand<i32>, ImmLeaf<i32, [{
1487 return Imm >= 0 && Imm <= 15;
1489 let PrintMethod = "printCondCodeOperand";
1490 let ParserMatchClass = cond_code_asmoperand;
1493 def Bcc : A64I_condbr<0b0, 0b0, (outs),
1494 (ins cond_code:$Cond, bcc_target:$Label),
1495 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1500 let isTerminator = 1;
1503 //===----------------------------------------------------------------------===//
1504 // Conditional compare (immediate) instructions
1505 //===----------------------------------------------------------------------===//
1506 // Contains: CCMN, CCMP
1508 def uimm4_asmoperand : AsmOperandClass {
1510 let PredicateMethod = "isUImm<4>";
1511 let RenderMethod = "addImmOperands";
1512 let DiagnosticType = "UImm4";
1515 def uimm4 : Operand<i32> {
1516 let ParserMatchClass = uimm4_asmoperand;
1519 def uimm5 : Operand<i32> {
1520 let ParserMatchClass = uimm5_asmoperand;
1523 // The only difference between this operand and the one for instructions like
1524 // B.cc is that it's parsed manually. The other get parsed implicitly as part of
1525 // the mnemonic handling.
1526 def cond_code_op_asmoperand : AsmOperandClass {
1527 let Name = "CondCodeOp";
1528 let RenderMethod = "addCondCodeOperands";
1529 let PredicateMethod = "isCondCode";
1530 let ParserMethod = "ParseCondCodeOperand";
1531 let DiagnosticType = "CondCode";
1534 def cond_code_op : Operand<i32> {
1535 let PrintMethod = "printCondCodeOperand";
1536 let ParserMatchClass = cond_code_op_asmoperand;
1539 class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1540 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
1541 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
1542 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1544 Sched<[WriteCMP, ReadCMP]> {
1548 def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">;
1549 def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">;
1550 def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">;
1551 def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">;
1553 //===----------------------------------------------------------------------===//
1554 // Conditional compare (register) instructions
1555 //===----------------------------------------------------------------------===//
1556 // Contains: CCMN, CCMP
1558 class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1559 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1,
1561 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1562 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1564 Sched<[WriteCMP, ReadCMP, ReadCMP]> {
1568 def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">;
1569 def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">;
1570 def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">;
1571 def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">;
1573 //===----------------------------------------------------------------------===//
1574 // Conditional select instructions
1575 //===----------------------------------------------------------------------===//
1576 // Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG
1578 // Condition code which is encoded as the inversion (semantically rather than
1579 // bitwise) in the instruction.
1580 def inv_cond_code_op_asmoperand : AsmOperandClass {
1581 let Name = "InvCondCodeOp";
1582 let RenderMethod = "addInvCondCodeOperands";
1583 let PredicateMethod = "isCondCode";
1584 let ParserMethod = "ParseCondCodeOperand";
1585 let DiagnosticType = "CondCode";
1588 def inv_cond_code_op : Operand<i32> {
1589 let ParserMatchClass = inv_cond_code_op_asmoperand;
1590 let PrintMethod = "printInverseCondCodeOperand";
1593 // Having a separate operand for the selectable use-case is debatable, but gives
1594 // consistency with cond_code.
1595 def inv_cond_XFORM : SDNodeXForm<imm, [{
1596 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue());
1597 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32);
1601 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>;
1604 multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
1605 SDPatternOperator select> {
1606 let Uses = [NZCV] in {
1607 def wwwc : A64I_condsel<0b0, op, 0b0, op2,
1609 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
1610 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1611 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
1613 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
1616 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
1618 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
1619 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1620 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
1622 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
1627 : PatFrag<(ops node:$lhs, node:$rhs),
1628 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>;
1630 class complex_select<SDPatternOperator opnode>
1631 : PatFrag<(ops node:$lhs, node:$rhs),
1632 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>;
1635 defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>;
1636 defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc",
1637 complex_select<PatFrag<(ops node:$val),
1638 (add node:$val, 1)>>>;
1639 defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>;
1640 defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>;
1642 // Now the instruction aliases, which fit nicely into LLVM's model:
1644 def : InstAlias<"cset $Rd, $Cond",
1645 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1646 def : InstAlias<"cset $Rd, $Cond",
1647 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1648 def : InstAlias<"csetm $Rd, $Cond",
1649 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1650 def : InstAlias<"csetm $Rd, $Cond",
1651 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1652 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1653 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1654 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1655 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1656 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1657 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1658 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1659 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1660 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1661 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1662 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1663 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1665 // Finally some helper patterns.
1667 // For CSET (a.k.a. zero-extension of icmp)
1668 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1669 (CSINCwwwc WZR, WZR, cond_code:$Cond)>;
1670 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1671 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>;
1673 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1674 (CSINCxxxc XZR, XZR, cond_code:$Cond)>;
1675 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1676 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>;
1678 // For CSETM (a.k.a. sign-extension of icmp)
1679 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1680 (CSINVwwwc WZR, WZR, cond_code:$Cond)>;
1681 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1682 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>;
1684 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1685 (CSINVxxxc XZR, XZR, cond_code:$Cond)>;
1686 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1687 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>;
1689 // CINC, CINV and CNEG get dealt with automatically, which leaves the issue of
1690 // commutativity. The instructions are to complex for isCommutable to be used,
1691 // so we have to create the patterns manually:
1693 // No commutable pattern for CSEL since the commuted version is isomorphic.
1696 def :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond),
1697 (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1698 def :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond),
1699 (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1702 def :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1703 (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1704 def :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1705 (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1708 def :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1709 (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1710 def :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1711 (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1713 //===----------------------------------------------------------------------===//
1714 // Data Processing (1 source) instructions
1715 //===----------------------------------------------------------------------===//
1716 // Contains: RBIT, REV16, REV, REV32, CLZ, CLS.
1718 // We define an unary operator which always fails. We will use this to
1719 // define unary operators that cannot be matched.
1721 class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop,
1722 list<dag> patterns, RegisterClass GPRrc,
1723 InstrItinClass itin>:
1728 !strconcat(asmop, "\t$Rd, $Rn"),
1733 Sched<[WriteALU, ReadALU]>;
1735 multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
1736 let hasSideEffects = 0 in {
1737 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>;
1738 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>;
1742 defm RBIT : A64I_dp_1src<0b000000, "rbit">;
1743 defm CLS : A64I_dp_1src<0b000101, "cls">;
1744 defm CLZ : A64I_dp_1src<0b000100, "clz">;
1746 def : Pat<(ctlz i32:$Rn), (CLZww $Rn)>;
1747 def : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>;
1748 def : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>;
1749 def : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>;
1751 def : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>;
1752 def : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>;
1753 def : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>;
1754 def : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>;
1757 def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev",
1758 [(set i32:$Rd, (bswap i32:$Rn))],
1759 GPR32, NoItinerary>;
1760 def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev",
1761 [(set i64:$Rd, (bswap i64:$Rn))],
1762 GPR64, NoItinerary>;
1763 def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32",
1764 [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))],
1765 GPR64, NoItinerary>;
1766 def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16",
1767 [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))],
1770 def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>;
1772 //===----------------------------------------------------------------------===//
1773 // Data Processing (2 sources) instructions
1774 //===----------------------------------------------------------------------===//
1775 // Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
1779 class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
1780 RegisterClass GPRsp,
1781 InstrItinClass itin>:
1785 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
1787 (ins GPRsp:$Rn, GPRsp:$Rm),
1790 Sched<[WriteALU, ReadALU, ReadALU]>;
1792 multiclass dp_2src_crc<bit c, string asmop> {
1793 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
1794 !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
1795 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
1796 !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
1797 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
1798 !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
1799 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
1800 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
1801 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
1803 Sched<[WriteALU, ReadALU, ReadALU]>;
1806 multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
1807 def www : dp_2src_impl<0b0,
1811 (op i32:$Rn, (i64 (zext i32:$Rm))))],
1814 def xxx : dp_2src_impl<0b1,
1817 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1823 multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> {
1824 def www : dp_2src_impl<0b0,
1827 [(set i32:$Rd, (op i32:$Rn, i32:$Rm))],
1830 def xxx : dp_2src_impl<0b1,
1833 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1838 // Here we define the data processing 2 source instructions.
1839 defm CRC32 : dp_2src_crc<0b0, "crc32">;
1840 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
1842 let SchedRW = [WriteDiv, ReadDiv, ReadDiv] in {
1843 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1844 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1847 let SchedRW = [WriteALUs, ReadALU, ReadALU] in {
1848 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1849 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1850 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1851 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1854 // Extra patterns for an incoming 64-bit value for a 32-bit
1855 // operation. Since the LLVM operations are undefined (as in C) if the
1856 // RHS is out of range, it's perfectly permissible to discard the high
1857 // bits of the GPR64.
1858 def : Pat<(shl i32:$Rn, i64:$Rm),
1859 (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1860 def : Pat<(srl i32:$Rn, i64:$Rm),
1861 (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1862 def : Pat<(sra i32:$Rn, i64:$Rm),
1863 (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1864 def : Pat<(rotr i32:$Rn, i64:$Rm),
1865 (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1867 // Here we define the aliases for the data processing 2 source instructions.
1868 def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">;
1869 def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">;
1870 def ASR_menmonic : MnemonicAlias<"asrv", "asr">;
1871 def ROR_menmonic : MnemonicAlias<"rorv", "ror">;
1873 //===----------------------------------------------------------------------===//
1874 // Data Processing (3 sources) instructions
1875 //===----------------------------------------------------------------------===//
1876 // Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH
1877 // + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL
1879 class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg,
1880 ValueType AccTy, RegisterClass SrcReg,
1881 string asmop, dag pattern>
1882 : A64I_dp3<sf, opcode,
1883 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
1884 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1885 [(set AccTy:$Rd, pattern)], NoItinerary>,
1886 Sched<[WriteMAC, ReadMAC, ReadMAC, ReadMAC]> {
1888 let Inst{14-10} = Ra;
1890 RegisterClass AccGPR = AccReg;
1891 RegisterClass SrcGPR = SrcReg;
1894 def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd",
1895 (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1896 def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd",
1897 (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1899 def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub",
1900 (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1901 def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub",
1902 (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1904 def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl",
1905 (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1906 def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl",
1907 (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1909 def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl",
1910 (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1911 def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl",
1912 (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1914 let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
1915 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
1916 (ins GPR64:$Rn, GPR64:$Rm),
1917 "umulh\t$Rd, $Rn, $Rm",
1918 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
1920 Sched<[WriteMAC, ReadMAC, ReadMAC]>;
1922 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
1923 (ins GPR64:$Rn, GPR64:$Rm),
1924 "smulh\t$Rd, $Rn, $Rm",
1925 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
1927 Sched<[WriteMAC, ReadMAC, ReadMAC]>;
1930 multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
1931 Register ZR, dag pattern> {
1932 def : InstAlias<asmop # " $Rd, $Rn, $Rm",
1933 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1935 def : Pat<pattern, (INST $Rn, $Rm, ZR)>;
1938 defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>;
1939 defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>;
1941 defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR,
1942 (sub 0, (mul i32:$Rn, i32:$Rm))>;
1943 defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR,
1944 (sub 0, (mul i64:$Rn, i64:$Rm))>;
1946 defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
1947 (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>;
1948 defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
1949 (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1951 defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
1952 (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>;
1953 defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
1954 (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1957 //===----------------------------------------------------------------------===//
1958 // Exception generation
1959 //===----------------------------------------------------------------------===//
1960 // Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
1962 def uimm16_asmoperand : AsmOperandClass {
1963 let Name = "UImm16";
1964 let PredicateMethod = "isUImm<16>";
1965 let RenderMethod = "addImmOperands";
1966 let DiagnosticType = "UImm16";
1969 def uimm16 : Operand<i32> {
1970 let ParserMatchClass = uimm16_asmoperand;
1973 class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
1974 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
1975 !strconcat(asmop, "\t$UImm16"), [], NoItinerary>,
1978 let isTerminator = 1;
1981 def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">;
1982 def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">;
1983 def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">;
1984 def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">;
1985 def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">;
1987 def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">;
1988 def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">;
1989 def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">;
1991 // The immediate is optional for the DCPS instructions, defaulting to 0.
1992 def : InstAlias<"dcps1", (DCPS1i 0)>;
1993 def : InstAlias<"dcps2", (DCPS2i 0)>;
1994 def : InstAlias<"dcps3", (DCPS3i 0)>;
1996 //===----------------------------------------------------------------------===//
1997 // Extract (immediate)
1998 //===----------------------------------------------------------------------===//
1999 // Contains: EXTR + alias ROR
2001 def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0,
2003 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB),
2004 "extr\t$Rd, $Rn, $Rm, $LSB",
2006 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
2008 Sched<[WriteALU, ReadALU, ReadALU]>;
2009 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
2011 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
2012 "extr\t$Rd, $Rn, $Rm, $LSB",
2014 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
2016 Sched<[WriteALU, ReadALU, ReadALU]>;
2018 def : InstAlias<"ror $Rd, $Rs, $LSB",
2019 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
2020 def : InstAlias<"ror $Rd, $Rs, $LSB",
2021 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>;
2023 def : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB),
2024 (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>;
2025 def : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB),
2026 (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>;
2028 //===----------------------------------------------------------------------===//
2029 // Floating-point compare instructions
2030 //===----------------------------------------------------------------------===//
2031 // Contains: FCMP, FCMPE
2033 def fpzero_asmoperand : AsmOperandClass {
2034 let Name = "FPZero";
2035 let ParserMethod = "ParseFPImmOperand";
2036 let DiagnosticType = "FPZero";
2039 def fpz32 : Operand<f32>,
2040 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
2041 let ParserMatchClass = fpzero_asmoperand;
2042 let PrintMethod = "printFPZeroOperand";
2043 let DecoderMethod = "DecodeFPZeroOperand";
2046 def fpz64 : Operand<f64>,
2047 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
2048 let ParserMatchClass = fpzero_asmoperand;
2049 let PrintMethod = "printFPZeroOperand";
2050 let DecoderMethod = "DecodeFPZeroOperand";
2053 def fpz64movi : Operand<i64>,
2054 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
2055 let ParserMatchClass = fpzero_asmoperand;
2056 let PrintMethod = "printFPZeroOperand";
2057 let DecoderMethod = "DecodeFPZeroOperand";
2060 multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
2061 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
2062 (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
2064 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
2068 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
2069 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary>,
2070 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
2075 defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm),
2076 (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>;
2077 defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm),
2078 (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>;
2080 // What would be Rm should be written as 0; note that even though it's called
2081 // "$Rm" here to fit in with the InstrFormats, it's actually an immediate.
2082 defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm),
2083 (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>;
2085 defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm),
2086 (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>;
2089 //===----------------------------------------------------------------------===//
2090 // Floating-point conditional compare instructions
2091 //===----------------------------------------------------------------------===//
2092 // Contains: FCCMP, FCCMPE
2094 class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop>
2095 : A64I_fpccmp<0b0, 0b0, type, op,
2097 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
2098 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
2100 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
2104 def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">;
2105 def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">;
2106 def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">;
2107 def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">;
2109 //===----------------------------------------------------------------------===//
2110 // Floating-point conditional select instructions
2111 //===----------------------------------------------------------------------===//
2114 let Uses = [NZCV] in {
2115 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
2116 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
2117 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2119 (simple_select f32:$Rn, f32:$Rm))],
2121 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2124 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
2125 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond),
2126 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2128 (simple_select f64:$Rn, f64:$Rm))],
2130 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2133 //===----------------------------------------------------------------------===//
2134 // Floating-point data-processing (1 source)
2135 //===----------------------------------------------------------------------===//
2136 // Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI].
2138 def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val),
2139 [{ (void)N; return false; }]>;
2141 // First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
2142 // syntax. Default to no pattern because most are odd enough not to have one.
2143 multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
2144 SDPatternOperator opnode = FPNoUnop> {
2145 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
2146 !strconcat(asmstr, "\t$Rd, $Rn"),
2147 [(set f32:$Rd, (opnode f32:$Rn))],
2149 Sched<[WriteFPALU, ReadFPALU]>;
2151 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
2152 !strconcat(asmstr, "\t$Rd, $Rn"),
2153 [(set f64:$Rd, (opnode f64:$Rn))],
2155 Sched<[WriteFPALU, ReadFPALU]>;
2158 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
2159 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
2160 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2161 let SchedRW = [WriteFPSqrt, ReadFPSqrt] in {
2162 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2165 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
2166 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
2167 defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>;
2168 defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>;
2169 defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">;
2170 defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>;
2171 defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>;
2173 // The FCVT instrucitons have different source and destination register-types,
2174 // but the fields are uniform everywhere a D-register (say) crops up. Package
2175 // this information in a Record.
2176 class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
2177 RegisterClass Class = rc;
2183 def FCVT16 : FCVTRegType<FPR16, 0b11, f16>;
2184 def FCVT32 : FCVTRegType<FPR32, 0b00, f32>;
2185 def FCVT64 : FCVTRegType<FPR64, 0b01, f64>;
2187 class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode>
2188 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0},
2189 {0,0,0,1, DestReg.t1, DestReg.t0},
2190 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
2192 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>,
2193 Sched<[WriteFPALU, ReadFPALU]>;
2195 def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
2196 def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
2197 def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>;
2198 def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>;
2199 def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>;
2200 def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>;
2203 //===----------------------------------------------------------------------===//
2204 // Floating-point data-processing (2 sources) instructions
2205 //===----------------------------------------------------------------------===//
2206 // Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
2208 def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs),
2209 [{ (void)N; return false; }]>;
2211 multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
2212 SDPatternOperator opnode> {
2213 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
2215 (ins FPR32:$Rn, FPR32:$Rm),
2216 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2217 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
2219 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2221 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
2223 (ins FPR64:$Rn, FPR64:$Rm),
2224 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2225 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
2227 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2230 let isCommutable = 1 in {
2231 let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
2232 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2234 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
2236 // No patterns for these.
2237 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>;
2238 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>;
2239 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
2240 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
2242 let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
2243 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2244 PatFrag<(ops node:$lhs, node:$rhs),
2245 (fneg (fmul node:$lhs, node:$rhs))> >;
2249 let SchedRW = [WriteFPDiv, ReadFPDiv, ReadFPDiv] in {
2250 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2252 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
2254 //===----------------------------------------------------------------------===//
2255 // Floating-point data-processing (3 sources) instructions
2256 //===----------------------------------------------------------------------===//
2257 // Contains: FMADD, FMSUB, FNMADD, FNMSUB
2259 def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2260 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>;
2261 def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2262 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>;
2263 def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2264 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>;
2266 class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT,
2267 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind>
2268 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd),
2269 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
2270 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
2271 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
2273 Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]>;
2275 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
2276 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
2277 def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>;
2278 def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>;
2280 def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>;
2281 def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>;
2282 def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>;
2283 def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>;
2285 // Extra patterns for when we're allowed to optimise separate multiplication and
2287 let Predicates = [HasFPARMv8, UseFusedMAC] in {
2288 def : Pat<(f32 (fadd FPR32:$Ra, (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)))),
2289 (FMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2290 def : Pat<(f32 (fsub FPR32:$Ra, (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)))),
2291 (FMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2292 def : Pat<(f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)))),
2293 (FNMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2294 def : Pat<(f32 (fsub (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra)),
2295 (FNMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2297 def : Pat<(f64 (fadd FPR64:$Ra, (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)))),
2298 (FMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2299 def : Pat<(f64 (fsub FPR64:$Ra, (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)))),
2300 (FMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2301 def : Pat<(f64 (fsub (f64 (fneg FPR64:$Ra)), (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)))),
2302 (FNMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2303 def : Pat<(f64 (fsub (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)), FPR64:$Ra)),
2304 (FNMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2308 //===----------------------------------------------------------------------===//
2309 // Floating-point <-> fixed-point conversion instructions
2310 //===----------------------------------------------------------------------===//
2311 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2313 // #1-#32 allowed, encoded as "64 - <specified imm>
2314 def fixedpos_asmoperand_i32 : AsmOperandClass {
2315 let Name = "CVTFixedPos32";
2316 let RenderMethod = "addCVTFixedPosOperands";
2317 let PredicateMethod = "isCVTFixedPos<32>";
2318 let DiagnosticType = "CVTFixedPos32";
2321 // Also encoded as "64 - <specified imm>" but #1-#64 allowed.
2322 def fixedpos_asmoperand_i64 : AsmOperandClass {
2323 let Name = "CVTFixedPos64";
2324 let RenderMethod = "addCVTFixedPosOperands";
2325 let PredicateMethod = "isCVTFixedPos<64>";
2326 let DiagnosticType = "CVTFixedPos64";
2329 // We need the cartesian product of f32/f64 i32/i64 operands for
2331 // + Selection needs to use operands of correct floating type
2332 // + Assembly parsing and decoding depend on integer width
2333 class cvtfix_i32_op<ValueType FloatVT>
2335 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
2336 let ParserMatchClass = fixedpos_asmoperand_i32;
2337 let DecoderMethod = "DecodeCVT32FixedPosOperand";
2338 let PrintMethod = "printCVTFixedPosOperand";
2341 class cvtfix_i64_op<ValueType FloatVT>
2343 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
2344 let ParserMatchClass = fixedpos_asmoperand_i64;
2345 let PrintMethod = "printCVTFixedPosOperand";
2348 // Because of the proliferation of weird operands, it's not really
2349 // worth going for a multiclass here. Oh well.
2351 class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
2352 RegisterClass GPR, RegisterClass FPR,
2353 ValueType DstTy, ValueType SrcTy,
2354 Operand scale_op, string asmop, SDNode cvtop>
2355 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
2356 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
2357 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2358 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
2360 Sched<[WriteFPALU, ReadFPALU]>;
2362 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
2363 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
2364 def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32,
2365 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>;
2366 def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32,
2367 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>;
2368 def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32,
2369 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>;
2371 def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64,
2372 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>;
2373 def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64,
2374 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>;
2375 def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64,
2376 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>;
2377 def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64,
2378 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>;
2381 class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode,
2382 RegisterClass FPR, RegisterClass GPR,
2383 ValueType DstTy, ValueType SrcTy,
2384 Operand scale_op, string asmop, SDNode cvtop>
2385 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode,
2386 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
2387 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2388 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
2390 Sched<[WriteFPALU, ReadFPALU]>;
2392 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
2393 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
2394 def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64,
2395 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>;
2396 def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32,
2397 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>;
2398 def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64,
2399 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>;
2400 def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32,
2401 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>;
2402 def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64,
2403 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>;
2404 def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32,
2405 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>;
2406 def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64,
2407 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>;
2409 //===----------------------------------------------------------------------===//
2410 // Floating-point <-> integer conversion instructions
2411 //===----------------------------------------------------------------------===//
2412 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2414 class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,
2415 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
2416 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
2417 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>,
2418 Sched<[WriteFPALU, ReadFPALU]>;
2420 multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
2421 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
2422 GPR32, FPR32, asmop # "s">;
2423 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
2424 GPR64, FPR32, asmop # "s">;
2425 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
2426 GPR32, FPR32, asmop # "u">;
2427 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
2428 GPR64, FPR32, asmop # "u">;
2430 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
2431 GPR32, FPR64, asmop # "s">;
2432 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
2433 GPR64, FPR64, asmop # "s">;
2434 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
2435 GPR32, FPR64, asmop # "u">;
2436 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
2437 GPR64, FPR64, asmop # "u">;
2440 defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
2441 defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">;
2442 defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">;
2443 defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">;
2444 defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">;
2446 let Predicates = [HasFPARMv8] in {
2447 def : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>;
2448 def : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>;
2449 def : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>;
2450 def : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>;
2451 def : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>;
2452 def : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>;
2453 def : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>;
2454 def : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>;
2457 multiclass A64I_inttofp<bit o0, string asmop> {
2458 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
2459 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
2460 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
2461 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>;
2464 defm S : A64I_inttofp<0b0, "scvtf">;
2465 defm U : A64I_inttofp<0b1, "ucvtf">;
2467 let Predicates = [HasFPARMv8] in {
2468 def : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>;
2469 def : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>;
2470 def : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>;
2471 def : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>;
2472 def : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>;
2473 def : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>;
2474 def : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>;
2475 def : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>;
2478 def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">;
2479 def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">;
2480 def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">;
2481 def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">;
2483 let Predicates = [HasFPARMv8] in {
2484 def : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>;
2485 def : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>;
2486 def : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>;
2487 def : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>;
2490 def lane1_asmoperand : AsmOperandClass {
2492 let RenderMethod = "addImmOperands";
2493 let DiagnosticType = "Lane1";
2496 def lane1 : Operand<i32> {
2497 let ParserMatchClass = lane1_asmoperand;
2498 let PrintMethod = "printBareImmOperand";
2501 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
2502 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
2503 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2504 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>,
2505 Sched<[WriteFPALU, ReadFPALU]>;
2507 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
2508 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2509 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>,
2510 Sched<[WriteFPALU, ReadFPALU]>;
2513 let Predicates = [HasFPARMv8] in {
2514 def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]",
2515 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>;
2517 def : InstAlias<"fmov $Rd.2d[$Lane], $Rn",
2518 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>;
2521 //===----------------------------------------------------------------------===//
2522 // Floating-point immediate instructions
2523 //===----------------------------------------------------------------------===//
2526 def fpimm_asmoperand : AsmOperandClass {
2527 let Name = "FMOVImm";
2528 let ParserMethod = "ParseFPImmOperand";
2529 let DiagnosticType = "FPImm";
2532 // The MCOperand for these instructions are the encoded 8-bit values.
2533 def SDXF_fpimm : SDNodeXForm<fpimm, [{
2535 A64Imms::isFPImm(N->getValueAPF(), Imm8);
2536 return CurDAG->getTargetConstant(Imm8, MVT::i32);
2539 class fmov_operand<ValueType FT>
2541 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
2543 let PrintMethod = "printFPImmOperand";
2544 let ParserMatchClass = fpimm_asmoperand;
2547 def fmov32_operand : fmov_operand<f32>;
2548 def fmov64_operand : fmov_operand<f64>;
2550 class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT,
2551 Operand fmov_operand>
2552 : A64I_fpimm<0b0, 0b0, type, 0b00000,
2554 (ins fmov_operand:$Imm8),
2556 [(set VT:$Rd, fmov_operand:$Imm8)],
2558 Sched<[WriteFPALU]>;
2560 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
2561 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
2563 //===----------------------------------------------------------------------===//
2564 // Load-register (literal) instructions
2565 //===----------------------------------------------------------------------===//
2566 // Contains: LDR, LDRSW, PRFM
2568 def ldrlit_label_asmoperand : AsmOperandClass {
2569 let Name = "LoadLitLabel";
2570 let RenderMethod = "addLabelOperands<19, 4>";
2571 let DiagnosticType = "Label";
2574 def ldrlit_label : Operand<i64> {
2575 let EncoderMethod = "getLoadLitLabelOpValue";
2577 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
2578 let PrintMethod = "printLabelOperand<19, 4>";
2579 let ParserMatchClass = ldrlit_label_asmoperand;
2580 let OperandType = "OPERAND_PCREL";
2583 // Various instructions take an immediate value (which can always be used),
2584 // where some numbers have a symbolic name to make things easier. These operands
2585 // and the associated functions abstract away the differences.
2586 multiclass namedimm<string prefix, string mapper> {
2587 def _asmoperand : AsmOperandClass {
2588 let Name = "NamedImm" # prefix;
2589 let PredicateMethod = "isUImm";
2590 let RenderMethod = "addImmOperands";
2591 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
2592 let DiagnosticType = "NamedImm_" # prefix;
2595 def _op : Operand<i32> {
2596 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
2597 let PrintMethod = "printNamedImmOperand<" # mapper # ">";
2598 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
2602 defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">;
2604 class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,
2605 list<dag> patterns = []>
2606 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
2607 "ldr\t$Rt, $Imm19", patterns, NoItinerary>,
2610 let mayLoad = 1 in {
2611 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
2612 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
2615 let Predicates = [HasFPARMv8] in {
2616 def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
2617 def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
2620 let mayLoad = 1 in {
2621 let Predicates = [HasFPARMv8] in {
2622 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
2625 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0,
2627 (ins ldrlit_label:$Imm19),
2628 "ldrsw\t$Rt, $Imm19",
2632 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
2633 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
2634 "prfm\t$Rt, $Imm19",
2636 Sched<[WriteLd, ReadLd]>;
2639 //===----------------------------------------------------------------------===//
2640 // Load-store exclusive instructions
2641 //===----------------------------------------------------------------------===//
2642 // Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB,
2643 // STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB,
2644 // STLRH, STLR, LDARB, LDARH, LDAR
2646 // Since these instructions have the undefined register bits set to 1 in
2647 // their canonical form, we need a post encoder method to set those bits
2648 // to 1 when encoding these instructions. We do this using the
2649 // fixLoadStoreExclusive function. This function has template parameters:
2651 // fixLoadStoreExclusive<int hasRs, int hasRt2>
2653 // hasRs indicates that the instruction uses the Rs field, so we won't set
2654 // it to 1 (and the same for Rt2). We don't need template parameters for
2655 // the other register fiels since Rt and Rn are always used.
2657 // This operand parses a GPR64xsp register, followed by an optional immediate
2659 def GPR64xsp0_asmoperand : AsmOperandClass {
2660 let Name = "GPR64xsp0";
2661 let PredicateMethod = "isWrappedReg";
2662 let RenderMethod = "addRegOperands";
2663 let ParserMethod = "ParseLSXAddressOperand";
2664 // Diagnostics are provided by ParserMethod
2667 def GPR64xsp0 : RegisterOperand<GPR64xsp> {
2668 let ParserMatchClass = GPR64xsp0_asmoperand;
2671 //===----------------------------------
2672 // Store-exclusive (releasing & normal)
2673 //===----------------------------------
2675 class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2676 dag ins, list<dag> pat,
2677 InstrItinClass itin> :
2678 A64I_LDSTex_stn <size,
2679 opcode{2}, 0, opcode{1}, opcode{0},
2681 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2684 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2685 let Constraints = "@earlyclobber $Rs";
2688 multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2689 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2690 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2692 Sched<[WriteSt, ReadSt, ReadSt]>;
2694 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2695 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2697 Sched<[WriteSt, ReadSt, ReadSt]>;
2699 def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
2700 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2702 Sched<[WriteSt, ReadSt, ReadSt]>;
2704 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
2705 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2707 Sched<[WriteSt, ReadSt, ReadSt]>;
2710 defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
2711 defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">;
2713 //===----------------------------------
2715 //===----------------------------------
2717 class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2718 dag ins, list<dag> pat,
2719 InstrItinClass itin> :
2720 A64I_LDSTex_tn <size,
2721 opcode{2}, 1, opcode{1}, opcode{0},
2723 !strconcat(asm, "\t$Rt, [$Rn]"),
2726 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2729 multiclass A64I_LRex<string asmstr, bits<3> opcode> {
2730 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2731 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2735 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2736 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2740 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
2741 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2745 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
2746 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2751 defm LDXR : A64I_LRex<"ldxr", 0b000>;
2752 defm LDAXR : A64I_LRex<"ldaxr", 0b001>;
2753 defm LDAR : A64I_LRex<"ldar", 0b101>;
2755 class acquiring_load<PatFrag base>
2756 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
2757 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2758 return Ordering == Acquire || Ordering == SequentiallyConsistent;
2761 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
2762 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
2763 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
2764 def atomic_load_acquire_64 : acquiring_load<atomic_load_64>;
2766 def : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>;
2767 def : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>;
2768 def : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>;
2769 def : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>;
2771 //===----------------------------------
2772 // Store-release (no exclusivity)
2773 //===----------------------------------
2775 class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2776 dag ins, list<dag> pat,
2777 InstrItinClass itin> :
2778 A64I_LDSTex_tn <size,
2779 opcode{2}, 0, opcode{1}, opcode{0},
2781 !strconcat(asm, "\t$Rt, [$Rn]"),
2784 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2787 class releasing_store<PatFrag base>
2788 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
2789 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2790 return Ordering == Release || Ordering == SequentiallyConsistent;
2793 def atomic_store_release_8 : releasing_store<atomic_store_8>;
2794 def atomic_store_release_16 : releasing_store<atomic_store_16>;
2795 def atomic_store_release_32 : releasing_store<atomic_store_32>;
2796 def atomic_store_release_64 : releasing_store<atomic_store_64>;
2798 multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
2799 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2800 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2801 [(atomic_store_release_8 i64:$Rn, i32:$Rt)],
2803 Sched<[WriteSt, ReadSt, ReadSt]>;
2805 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2806 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2807 [(atomic_store_release_16 i64:$Rn, i32:$Rt)],
2809 Sched<[WriteSt, ReadSt, ReadSt]>;
2811 def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
2812 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2813 [(atomic_store_release_32 i64:$Rn, i32:$Rt)],
2815 Sched<[WriteSt, ReadSt, ReadSt]>;
2817 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
2818 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2819 [(atomic_store_release_64 i64:$Rn, i64:$Rt)],
2821 Sched<[WriteSt, ReadSt, ReadSt]>;
2824 defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
2826 //===----------------------------------
2827 // Store-exclusive pair (releasing & normal)
2828 //===----------------------------------
2830 class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2831 dag ins, list<dag> pat,
2832 InstrItinClass itin> :
2833 A64I_LDSTex_stt2n <size,
2834 opcode{2}, 0, opcode{1}, opcode{0},
2836 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
2842 multiclass A64I_SPex<string asmstr, bits<3> opcode> {
2843 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
2844 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
2847 Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
2849 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
2850 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
2853 Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
2856 defm STXP : A64I_SPex<"stxp", 0b010>;
2857 defm STLXP : A64I_SPex<"stlxp", 0b011>;
2859 //===----------------------------------
2860 // Load-exclusive pair (acquiring & normal)
2861 //===----------------------------------
2863 class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2864 dag ins, list<dag> pat,
2865 InstrItinClass itin> :
2866 A64I_LDSTex_tt2n <size,
2867 opcode{2}, 1, opcode{1}, opcode{0},
2869 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
2872 let DecoderMethod = "DecodeLoadPairExclusiveInstruction";
2873 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
2876 multiclass A64I_LPex<string asmstr, bits<3> opcode> {
2877 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
2878 (outs GPR32:$Rt, GPR32:$Rt2),
2879 (ins GPR64xsp0:$Rn),
2881 Sched<[WriteLd, WriteLd, ReadLd]>;
2883 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
2884 (outs GPR64:$Rt, GPR64:$Rt2),
2885 (ins GPR64xsp0:$Rn),
2887 Sched<[WriteLd, WriteLd, ReadLd]>;
2890 defm LDXP : A64I_LPex<"ldxp", 0b010>;
2891 defm LDAXP : A64I_LPex<"ldaxp", 0b011>;
2893 //===----------------------------------------------------------------------===//
2894 // Load-store register (unscaled immediate) instructions
2895 //===----------------------------------------------------------------------===//
2896 // Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM
2900 //===----------------------------------------------------------------------===//
2901 // Load-store register (register offset) instructions
2902 //===----------------------------------------------------------------------===//
2903 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2907 //===----------------------------------------------------------------------===//
2908 // Load-store register (unsigned immediate) instructions
2909 //===----------------------------------------------------------------------===//
2910 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2914 //===----------------------------------------------------------------------===//
2915 // Load-store register (immediate post-indexed) instructions
2916 //===----------------------------------------------------------------------===//
2917 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2921 //===----------------------------------------------------------------------===//
2922 // Load-store register (immediate pre-indexed) instructions
2923 //===----------------------------------------------------------------------===//
2924 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2926 // Note that patterns are much later on in a completely separate section (they
2927 // need ADRPxi to be defined).
2929 //===-------------------------------
2930 // 1. Various operands needed
2931 //===-------------------------------
2933 //===-------------------------------
2934 // 1.1 Unsigned 12-bit immediate operands
2935 //===-------------------------------
2936 // The addressing mode for these instructions consists of an unsigned 12-bit
2937 // immediate which is scaled by the size of the memory access.
2939 // We represent this in the MC layer by two operands:
2940 // 1. A base register.
2941 // 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]"
2942 // would have '1' in this field.
2943 // This means that separate functions are needed for converting representations
2944 // which *are* aware of the intended access size.
2946 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
2947 // know the access size via some means. An isolated operand does not have this
2948 // information unless told from here, which means we need separate tablegen
2949 // Operands for each access size. This multiclass takes care of instantiating
2950 // the correct template functions in the rest of the backend.
2952 //===-------------------------------
2953 // 1.1 Unsigned 12-bit immediate operands
2954 //===-------------------------------
2956 multiclass offsets_uimm12<int MemSize, string prefix> {
2957 def uimm12_asmoperand : AsmOperandClass {
2958 let Name = "OffsetUImm12_" # MemSize;
2959 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
2960 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
2961 let DiagnosticType = "LoadStoreUImm12_" # MemSize;
2964 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which
2965 // complicates things beyond TableGen's ken.
2966 def uimm12 : Operand<i64>,
2967 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
2968 let ParserMatchClass
2969 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
2971 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">";
2972 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">";
2976 defm byte_ : offsets_uimm12<1, "byte_">;
2977 defm hword_ : offsets_uimm12<2, "hword_">;
2978 defm word_ : offsets_uimm12<4, "word_">;
2979 defm dword_ : offsets_uimm12<8, "dword_">;
2980 defm qword_ : offsets_uimm12<16, "qword_">;
2982 //===-------------------------------
2983 // 1.1 Signed 9-bit immediate operands
2984 //===-------------------------------
2986 // The MCInst is expected to store the bit-wise encoding of the value,
2987 // which amounts to lopping off the extended sign bits.
2988 def SDXF_simm9 : SDNodeXForm<imm, [{
2989 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
2992 def simm9_asmoperand : AsmOperandClass {
2994 let PredicateMethod = "isSImm<9>";
2995 let RenderMethod = "addSImmOperands<9>";
2996 let DiagnosticType = "LoadStoreSImm9";
2999 def simm9 : Operand<i64>,
3000 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
3002 let PrintMethod = "printOffsetSImm9Operand";
3003 let ParserMatchClass = simm9_asmoperand;
3007 //===-------------------------------
3008 // 1.3 Register offset extensions
3009 //===-------------------------------
3011 // The assembly-syntax for these addressing-modes is:
3012 // [<Xn|SP>, <R><m> {, <extend> {<amount>}}]
3014 // The essential semantics are:
3015 // + <amount> is a shift: #<log(transfer size)> or #0
3016 // + <R> can be W or X.
3017 // + If <R> is W, <extend> can be UXTW or SXTW
3018 // + If <R> is X, <extend> can be LSL or SXTX
3020 // The trickiest of those constraints is that Rm can be either GPR32 or GPR64,
3021 // which will need separate instructions for LLVM type-consistency. We'll also
3022 // need separate operands, of course.
3023 multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
3024 string Rm, string prefix> {
3025 def regext_asmoperand : AsmOperandClass {
3026 let Name = "AddrRegExtend_" # MemSize # "_" # Rm;
3027 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
3028 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
3029 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize;
3032 def regext : Operand<i64> {
3034 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
3036 let DecoderMethod = "DecodeAddrRegExtendOperand";
3037 let ParserMatchClass
3038 = !cast<AsmOperandClass>(prefix # regext_asmoperand);
3042 multiclass regexts_wx<int MemSize, string prefix> {
3043 // Rm is an X-register if LSL or SXTX are specified as the shift.
3044 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
3046 // Rm is a W-register if UXTW or SXTW are specified as the shift.
3047 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">;
3050 defm byte_ : regexts_wx<1, "byte_">;
3051 defm hword_ : regexts_wx<2, "hword_">;
3052 defm word_ : regexts_wx<4, "word_">;
3053 defm dword_ : regexts_wx<8, "dword_">;
3054 defm qword_ : regexts_wx<16, "qword_">;
3057 //===------------------------------
3058 // 2. The instructions themselves.
3059 //===------------------------------
3061 // We have the following instructions to implement:
3062 // | | B | H | W | X |
3063 // |-----------------+-------+-------+-------+--------|
3064 // | unsigned str | STRB | STRH | STR | STR |
3065 // | unsigned ldr | LDRB | LDRH | LDR | LDR |
3066 // | signed ldr to W | LDRSB | LDRSH | - | - |
3067 // | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) |
3069 // This will instantiate the LDR/STR instructions you'd expect to use for an
3070 // unsigned datatype (first two rows above) or floating-point register, which is
3071 // reasonably uniform across all access sizes.
3074 //===------------------------------
3075 // 2.1 Regular instructions
3076 //===------------------------------
3078 // This class covers the basic unsigned or irrelevantly-signed loads and stores,
3079 // to general-purpose and floating-point registers.
3081 class AddrParams<string prefix> {
3082 Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
3084 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
3085 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext");
3088 def byte_addrparams : AddrParams<"byte">;
3089 def hword_addrparams : AddrParams<"hword">;
3090 def word_addrparams : AddrParams<"word">;
3091 def dword_addrparams : AddrParams<"dword">;
3092 def qword_addrparams : AddrParams<"qword">;
3094 multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
3095 bit high_opc, string asmsuffix,
3096 RegisterClass GPR, AddrParams params> {
3097 // Unsigned immediate
3098 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
3099 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
3100 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
3102 Sched<[WriteSt, ReadSt, ReadSt]> {
3105 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
3106 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3108 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
3109 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3110 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
3112 Sched<[WriteLd, ReadLd]> {
3115 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
3116 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3118 // Register offset (four of these: load/store and Wm/Xm).
3119 let mayLoad = 1 in {
3120 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
3122 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3123 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3125 Sched<[WriteLd, ReadLd, ReadLd]>;
3127 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,
3129 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3130 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3132 Sched<[WriteLd, ReadLd, ReadLd]>;
3134 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
3135 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
3138 let mayStore = 1 in {
3139 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
3140 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
3141 params.regextWm:$Ext),
3142 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3144 Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
3146 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
3147 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
3148 params.regextXm:$Ext),
3149 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3151 Sched<[WriteSt, ReadSt, ReadSt, ReadSt]>;
3153 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
3154 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
3157 // Unaligned immediate
3158 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
3159 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3160 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3162 Sched<[WriteSt, ReadSt, ReadSt]> {
3165 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
3166 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3168 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
3169 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3170 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3172 Sched<[WriteLd, ReadLd]> {
3175 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
3176 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3179 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0},
3180 (outs GPR64xsp:$Rn_wb),
3181 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3182 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3184 Sched<[WriteSt, ReadSt, ReadSt]> {
3185 let Constraints = "$Rn = $Rn_wb";
3188 // Decoder only needed for unpredictability checking (FIXME).
3189 let DecoderMethod = "DecodeSingleIndexedInstruction";
3192 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1},
3193 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3194 (ins GPR64xsp:$Rn, simm9:$SImm9),
3195 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3197 Sched<[WriteLd, WriteLd, ReadLd]> {
3199 let Constraints = "$Rn = $Rn_wb";
3200 let DecoderMethod = "DecodeSingleIndexedInstruction";
3204 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0},
3205 (outs GPR64xsp:$Rn_wb),
3206 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3207 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3209 Sched<[WriteSt, ReadSt, ReadSt]> {
3210 let Constraints = "$Rn = $Rn_wb";
3213 // Decoder only needed for unpredictability checking (FIXME).
3214 let DecoderMethod = "DecodeSingleIndexedInstruction";
3217 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1},
3218 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3219 (ins GPR64xsp:$Rn, simm9:$SImm9),
3220 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3222 Sched<[WriteLd, WriteLd, ReadLd]> {
3224 let Constraints = "$Rn = $Rn_wb";
3225 let DecoderMethod = "DecodeSingleIndexedInstruction";
3230 // STRB/LDRB: First define the instructions
3232 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>;
3236 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>;
3239 // STR/LDR to/from a W register
3241 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>;
3243 // STR/LDR to/from an X register
3245 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>;
3247 let Predicates = [HasFPARMv8] in {
3248 // STR/LDR to/from a B register
3250 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>;
3252 // STR/LDR to/from an H register
3254 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>;
3256 // STR/LDR to/from an S register
3258 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>;
3259 // STR/LDR to/from a D register
3261 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
3262 // STR/LDR to/from a Q register
3264 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
3268 //===------------------------------
3270 //===------------------------------
3272 // Byte and half-word signed loads can both go into either an X or a W register,
3273 // so it's worth factoring out. Signed word loads don't fit because there is no
3275 multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
3278 def w : A64I_LSunsigimm<size, 0b0, 0b11,
3280 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3281 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3283 Sched<[WriteLd, ReadLd]> {
3286 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3287 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3289 def x : A64I_LSunsigimm<size, 0b0, 0b10,
3291 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3292 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3294 Sched<[WriteLd, ReadLd]> {
3297 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3298 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3301 let mayLoad = 1 in {
3302 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
3304 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3305 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3307 Sched<[WriteLd, ReadLd, ReadLd]>;
3309 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,
3311 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3312 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3314 Sched<[WriteLd, ReadLd, ReadLd]>;
3316 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,
3318 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3319 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3321 Sched<[WriteLd, ReadLd, ReadLd]>;
3323 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,
3325 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3326 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3328 Sched<[WriteLd, ReadLd, ReadLd]>;
3330 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3331 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
3334 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3335 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn,
3339 let mayLoad = 1 in {
3341 def w_U : A64I_LSunalimm<size, 0b0, 0b11,
3343 (ins GPR64xsp:$Rn, simm9:$SImm9),
3344 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3346 Sched<[WriteLd, ReadLd]>;
3348 def x_U : A64I_LSunalimm<size, 0b0, 0b10,
3350 (ins GPR64xsp:$Rn, simm9:$SImm9),
3351 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3353 Sched<[WriteLd, ReadLd]>;
3357 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11,
3358 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3359 (ins GPR64xsp:$Rn, simm9:$SImm9),
3360 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3362 Sched<[WriteLd, WriteLd, ReadLd]> {
3363 let Constraints = "$Rn = $Rn_wb";
3364 let DecoderMethod = "DecodeSingleIndexedInstruction";
3367 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10,
3368 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3369 (ins GPR64xsp:$Rn, simm9:$SImm9),
3370 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3372 Sched<[WriteLd, WriteLd, ReadLd]> {
3373 let Constraints = "$Rn = $Rn_wb";
3374 let DecoderMethod = "DecodeSingleIndexedInstruction";
3378 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11,
3379 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3380 (ins GPR64xsp:$Rn, simm9:$SImm9),
3381 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3383 Sched<[WriteLd, WriteLd, ReadLd]> {
3384 let Constraints = "$Rn = $Rn_wb";
3385 let DecoderMethod = "DecodeSingleIndexedInstruction";
3388 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10,
3389 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3390 (ins GPR64xsp:$Rn, simm9:$SImm9),
3391 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3393 Sched<[WriteLd, WriteLd, ReadLd]> {
3394 let Constraints = "$Rn = $Rn_wb";
3395 let DecoderMethod = "DecodeSingleIndexedInstruction";
3397 } // let mayLoad = 1
3401 defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">;
3403 defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">;
3405 // LDRSW: load a 32-bit register, sign-extending to 64-bits.
3407 : A64I_LSunsigimm<0b10, 0b0, 0b10,
3409 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
3410 "ldrsw\t$Rt, [$Rn, $UImm12]",
3412 Sched<[WriteLd, ReadLd]> {
3415 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3417 let mayLoad = 1 in {
3418 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
3420 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
3421 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3423 Sched<[WriteLd, ReadLd, ReadLd]>;
3425 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
3427 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
3428 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3430 Sched<[WriteLd, ReadLd, ReadLd]>;
3432 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
3433 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
3437 : A64I_LSunalimm<0b10, 0b0, 0b10,
3439 (ins GPR64xsp:$Rn, simm9:$SImm9),
3440 "ldursw\t$Rt, [$Rn, $SImm9]",
3442 Sched<[WriteLd, ReadLd]> {
3445 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3448 : A64I_LSpostind<0b10, 0b0, 0b10,
3449 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3450 (ins GPR64xsp:$Rn, simm9:$SImm9),
3451 "ldrsw\t$Rt, [$Rn], $SImm9",
3453 Sched<[WriteLd, WriteLd, ReadLd]> {
3455 let Constraints = "$Rn = $Rn_wb";
3456 let DecoderMethod = "DecodeSingleIndexedInstruction";
3459 def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10,
3460 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3461 (ins GPR64xsp:$Rn, simm9:$SImm9),
3462 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3464 Sched<[WriteLd, WriteLd, ReadLd]> {
3466 let Constraints = "$Rn = $Rn_wb";
3467 let DecoderMethod = "DecodeSingleIndexedInstruction";
3470 //===------------------------------
3471 // 2.4 Prefetch operations
3472 //===------------------------------
3474 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
3475 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
3476 "prfm\t$Rt, [$Rn, $UImm12]",
3478 Sched<[WritePreLd, ReadPreLd]> {
3481 def : InstAlias<"prfm $Rt, [$Rn]",
3482 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3484 let mayLoad = 1 in {
3485 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
3486 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3487 GPR32:$Rm, dword_Wm_regext:$Ext),
3488 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3490 Sched<[WritePreLd, ReadPreLd]>;
3491 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
3492 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3493 GPR64:$Rm, dword_Xm_regext:$Ext),
3494 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3496 Sched<[WritePreLd, ReadPreLd]>;
3499 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
3500 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn,
3504 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
3505 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3506 "prfum\t$Rt, [$Rn, $SImm9]",
3508 Sched<[WritePreLd, ReadPreLd]> {
3511 def : InstAlias<"prfum $Rt, [$Rn]",
3512 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3514 //===----------------------------------------------------------------------===//
3515 // Load-store register (unprivileged) instructions
3516 //===----------------------------------------------------------------------===//
3517 // Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH
3519 // These instructions very much mirror the "unscaled immediate" loads, but since
3520 // there are no floating-point variants we need to split them out into their own
3521 // section to avoid instantiation of "ldtr d0, [sp]" etc.
3523 multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
3525 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
3526 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3527 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3529 Sched<[WriteLd, ReadLd]> {
3533 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]",
3534 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3536 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
3537 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3538 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3540 Sched<[WriteLd, ReadLd]> {
3544 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]",
3545 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3549 // STTRB/LDTRB: First define the instructions
3550 defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">;
3553 defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">;
3555 // STTR/LDTR to/from a W register
3556 defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">;
3558 // STTR/LDTR to/from an X register
3559 defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">;
3561 // Now a class for the signed instructions that can go to either 32 or 64
3563 multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
3564 let mayLoad = 1 in {
3565 def w : A64I_LSunpriv<size, 0b0, 0b11,
3567 (ins GPR64xsp:$Rn, simm9:$SImm9),
3568 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3570 Sched<[WriteLd, ReadLd]>;
3572 def x : A64I_LSunpriv<size, 0b0, 0b10,
3574 (ins GPR64xsp:$Rn, simm9:$SImm9),
3575 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3577 Sched<[WriteLd, ReadLd]>;
3580 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3581 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3583 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3584 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3589 defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">;
3591 defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">;
3593 // And finally LDTRSW which only goes to 64 bits.
3594 def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10,
3596 (ins GPR64xsp:$Rn, simm9:$SImm9),
3597 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3599 Sched<[WriteLd, ReadLd]> {
3602 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3604 //===----------------------------------------------------------------------===//
3605 // Load-store register pair (offset) instructions
3606 //===----------------------------------------------------------------------===//
3610 //===----------------------------------------------------------------------===//
3611 // Load-store register pair (post-indexed) instructions
3612 //===----------------------------------------------------------------------===//
3613 // Contains: STP, LDP, LDPSW
3617 //===----------------------------------------------------------------------===//
3618 // Load-store register pair (pre-indexed) instructions
3619 //===----------------------------------------------------------------------===//
3620 // Contains: STP, LDP, LDPSW
3624 //===----------------------------------------------------------------------===//
3625 // Load-store non-temporal register pair (offset) instructions
3626 //===----------------------------------------------------------------------===//
3627 // Contains: STNP, LDNP
3630 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
3631 // know the access size via some means. An isolated operand does not have this
3632 // information unless told from here, which means we need separate tablegen
3633 // Operands for each access size. This multiclass takes care of instantiating
3634 // the correct template functions in the rest of the backend.
3636 multiclass offsets_simm7<string MemSize, string prefix> {
3637 // The bare signed 7-bit immediate is used in post-indexed instructions, but
3638 // because of the scaling performed a generic "simm7" operand isn't
3639 // appropriate here either.
3640 def simm7_asmoperand : AsmOperandClass {
3641 let Name = "SImm7_Scaled" # MemSize;
3642 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
3643 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
3644 let DiagnosticType = "LoadStoreSImm7_" # MemSize;
3647 def simm7 : Operand<i64> {
3648 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
3649 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
3653 defm word_ : offsets_simm7<"4", "word_">;
3654 defm dword_ : offsets_simm7<"8", "dword_">;
3655 defm qword_ : offsets_simm7<"16", "qword_">;
3657 multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
3658 Operand simm7, string prefix> {
3659 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
3660 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3661 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3662 Sched<[WriteLd, ReadLd]> {
3664 let DecoderMethod = "DecodeLDSTPairInstruction";
3666 def : InstAlias<"stp $Rt, $Rt2, [$Rn]",
3667 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt,
3668 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3670 def _LDR : A64I_LSPoffset<opc, v, 0b1,
3671 (outs SomeReg:$Rt, SomeReg:$Rt2),
3672 (ins GPR64xsp:$Rn, simm7:$SImm7),
3673 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3674 Sched<[WriteLd, WriteLd, ReadLd]> {
3676 let DecoderMethod = "DecodeLDSTPairInstruction";
3678 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]",
3679 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt,
3680 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3682 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0,
3683 (outs GPR64xsp:$Rn_wb),
3684 (ins SomeReg:$Rt, SomeReg:$Rt2,
3687 "stp\t$Rt, $Rt2, [$Rn], $SImm7",
3689 Sched<[WriteSt, ReadSt, ReadSt, ReadSt]> {
3691 let Constraints = "$Rn = $Rn_wb";
3693 // Decoder only needed for unpredictability checking (FIXME).
3694 let DecoderMethod = "DecodeLDSTPairInstruction";
3697 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1,
3698 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3699 (ins GPR64xsp:$Rn, simm7:$SImm7),
3700 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3702 Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
3704 let Constraints = "$Rn = $Rn_wb";
3705 let DecoderMethod = "DecodeLDSTPairInstruction";
3708 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
3709 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3710 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3712 Sched<[WriteSt, ReadSt, ReadSt, ReadSt]> {
3714 let Constraints = "$Rn = $Rn_wb";
3715 let DecoderMethod = "DecodeLDSTPairInstruction";
3718 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1,
3719 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3720 (ins GPR64xsp:$Rn, simm7:$SImm7),
3721 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3723 Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
3725 let Constraints = "$Rn = $Rn_wb";
3726 let DecoderMethod = "DecodeLDSTPairInstruction";
3729 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
3730 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3731 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3732 Sched<[WriteSt, ReadSt, ReadSt, ReadSt]> {
3734 let DecoderMethod = "DecodeLDSTPairInstruction";
3736 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]",
3737 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt,
3738 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3740 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
3741 (outs SomeReg:$Rt, SomeReg:$Rt2),
3742 (ins GPR64xsp:$Rn, simm7:$SImm7),
3743 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3744 Sched<[WriteLd, WriteLd, ReadLd]> {
3746 let DecoderMethod = "DecodeLDSTPairInstruction";
3748 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]",
3749 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt,
3750 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3755 defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">;
3756 defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
3758 let Predicates = [HasFPARMv8] in {
3759 defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
3760 defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">;
3761 defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
3766 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
3767 (outs GPR64:$Rt, GPR64:$Rt2),
3768 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3769 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3770 Sched<[WriteLd, WriteLd, ReadLd]> {
3772 let DecoderMethod = "DecodeLDSTPairInstruction";
3774 def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]",
3775 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>;
3777 def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1,
3778 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3779 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3780 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
3782 Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
3784 let Constraints = "$Rn = $Rn_wb";
3785 let DecoderMethod = "DecodeLDSTPairInstruction";
3788 def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1,
3789 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3790 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3791 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3793 Sched<[WriteLd, WriteLd, WriteLd, ReadLd]> {
3795 let Constraints = "$Rn = $Rn_wb";
3796 let DecoderMethod = "DecodeLDSTPairInstruction";
3799 //===----------------------------------------------------------------------===//
3800 // Logical (immediate) instructions
3801 //===----------------------------------------------------------------------===//
3802 // Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
3804 multiclass logical_imm_operands<string prefix, string note,
3805 int size, ValueType VT> {
3806 def _asmoperand : AsmOperandClass {
3807 let Name = "LogicalImm" # note # size;
3808 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
3809 let RenderMethod = "addLogicalImmOperands<" # size # ">";
3810 let DiagnosticType = "LogicalSecondSource";
3814 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
3815 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3816 let PrintMethod = "printLogicalImmOperand<" # size # ">";
3817 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
3821 defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>;
3822 defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>;
3824 // The mov versions only differ in assembly parsing, where they
3825 // exclude values representable with either MOVZ or MOVN.
3826 defm logical_imm32_mov
3827 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>;
3828 defm logical_imm64_mov
3829 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
3832 multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
3833 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
3834 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3835 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3837 (opnode i32:$Rn, logical_imm32_operand:$Imm))],
3839 Sched<[WriteALU, ReadALU]>;
3841 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
3842 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3843 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3845 (opnode i64:$Rn, logical_imm64_operand:$Imm))],
3847 Sched<[WriteALU, ReadALU]>;
3850 defm AND : A64I_logimmSizes<0b00, "and", and>;
3851 defm ORR : A64I_logimmSizes<0b01, "orr", or>;
3852 defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
3854 let Defs = [NZCV] in {
3855 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
3856 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3857 "ands\t$Rd, $Rn, $Imm",
3859 Sched<[WriteALU, ReadALU]>;
3861 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
3862 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3863 "ands\t$Rd, $Rn, $Imm",
3865 Sched<[WriteALU, ReadALU]>;
3868 def : InstAlias<"tst $Rn, $Imm",
3869 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
3870 def : InstAlias<"tst $Rn, $Imm",
3871 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
3872 // FIXME: these sometimes are canonical.
3873 def : InstAlias<"mov $Rd, $Imm",
3874 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm), 0>;
3875 def : InstAlias<"mov $Rd, $Imm",
3876 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm), 0>;
3878 //===----------------------------------------------------------------------===//
3879 // Logical (shifted register) instructions
3880 //===----------------------------------------------------------------------===//
3881 // Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV
3883 // Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS"
3884 // behaves differently for unsigned comparisons, so we defensively only allow
3885 // signed or n/a as the operand. In practice "unsigned greater than 0" is "not
3886 // equal to 0" and LLVM gives us this.
3887 def signed_cond : PatLeaf<(cond), [{
3888 return !isUnsignedIntSetCC(N->get());
3892 // These instructions share their "shift" operands with add/sub (shifted
3893 // register instructions). They are defined there.
3895 // N.b. the commutable parameter is just !N. It will be first against the wall
3896 // when the revolution comes.
3897 multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
3898 bit N, bit commutable,
3899 string asmop, SDPatternOperator opfrag, ValueType ty,
3900 RegisterClass GPR, list<Register> defs> {
3901 let isCommutable = commutable, Defs = defs in {
3902 def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
3904 (ins GPR:$Rn, GPR:$Rm,
3905 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3906 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3907 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
3908 !cast<Operand>("lsl_operand_" # ty):$Imm6))
3911 Sched<[WriteALU, ReadALU, ReadALU]>;
3913 def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
3915 (ins GPR:$Rn, GPR:$Rm,
3916 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3917 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3918 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
3919 !cast<Operand>("lsr_operand_" # ty):$Imm6))
3922 Sched<[WriteALU, ReadALU, ReadALU]>;
3924 def _asr : A64I_logicalshift<sf, opc, 0b10, N,
3926 (ins GPR:$Rn, GPR:$Rm,
3927 !cast<Operand>("asr_operand_" # ty):$Imm6),
3928 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3929 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
3930 !cast<Operand>("asr_operand_" # ty):$Imm6))
3933 Sched<[WriteALU, ReadALU, ReadALU]>;
3935 def _ror : A64I_logicalshift<sf, opc, 0b11, N,
3937 (ins GPR:$Rn, GPR:$Rm,
3938 !cast<Operand>("ror_operand_" # ty):$Imm6),
3939 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3940 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
3941 !cast<Operand>("ror_operand_" # ty):$Imm6))
3944 Sched<[WriteALU, ReadALU, ReadALU]>;
3948 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
3949 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
3952 def : Pat<(opfrag ty:$Rn, ty:$Rm),
3953 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3956 multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
3957 string asmop, SDPatternOperator opfrag,
3958 list<Register> defs> {
3959 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
3960 commutable, asmop, opfrag, i64, GPR64, defs>;
3961 defm www : logical_shifts<prefix # "www", 0b0, opc, N,
3962 commutable, asmop, opfrag, i32, GPR32, defs>;
3966 defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>;
3967 defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>;
3968 defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>;
3969 defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands",
3970 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs),
3971 [{ (void)N; return false; }]>,
3974 defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic",
3975 PatFrag<(ops node:$lhs, node:$rhs),
3976 (and node:$lhs, (not node:$rhs))>, []>;
3977 defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn",
3978 PatFrag<(ops node:$lhs, node:$rhs),
3979 (or node:$lhs, (not node:$rhs))>, []>;
3980 defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon",
3981 PatFrag<(ops node:$lhs, node:$rhs),
3982 (xor node:$lhs, (not node:$rhs))>, []>;
3983 defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics",
3984 PatFrag<(ops node:$lhs, node:$rhs),
3985 (and node:$lhs, (not node:$rhs)),
3986 [{ (void)N; return false; }]>,
3989 multiclass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3990 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
3991 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
3993 (ins GPR:$Rn, GPR:$Rm,
3994 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3995 "tst\t$Rn, $Rm, $Imm6",
3996 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
3997 !cast<Operand>("lsl_operand_" # ty):$Imm6)),
4000 Sched<[WriteALU, ReadALU, ReadALU]>;
4003 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
4005 (ins GPR:$Rn, GPR:$Rm,
4006 !cast<Operand>("lsr_operand_" # ty):$Imm6),
4007 "tst\t$Rn, $Rm, $Imm6",
4008 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
4009 !cast<Operand>("lsr_operand_" # ty):$Imm6)),
4012 Sched<[WriteALU, ReadALU, ReadALU]>;
4014 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
4016 (ins GPR:$Rn, GPR:$Rm,
4017 !cast<Operand>("asr_operand_" # ty):$Imm6),
4018 "tst\t$Rn, $Rm, $Imm6",
4019 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
4020 !cast<Operand>("asr_operand_" # ty):$Imm6)),
4023 Sched<[WriteALU, ReadALU, ReadALU]>;
4025 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
4027 (ins GPR:$Rn, GPR:$Rm,
4028 !cast<Operand>("ror_operand_" # ty):$Imm6),
4029 "tst\t$Rn, $Rm, $Imm6",
4030 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
4031 !cast<Operand>("ror_operand_" # ty):$Imm6)),
4034 Sched<[WriteALU, ReadALU, ReadALU]>;
4037 def _noshift : InstAlias<"tst $Rn, $Rm",
4038 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
4040 def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond),
4041 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
4044 defm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>;
4045 defm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>;
4048 multiclass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
4049 let isCommutable = 0, Rn = 0b11111 in {
4050 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
4053 !cast<Operand>("lsl_operand_" # ty):$Imm6),
4054 "mvn\t$Rd, $Rm, $Imm6",
4055 [(set ty:$Rd, (not (shl ty:$Rm,
4056 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
4058 Sched<[WriteALU, ReadALU, ReadALU]>;
4061 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
4064 !cast<Operand>("lsr_operand_" # ty):$Imm6),
4065 "mvn\t$Rd, $Rm, $Imm6",
4066 [(set ty:$Rd, (not (srl ty:$Rm,
4067 !cast<Operand>("lsr_operand_" # ty):$Imm6)))],
4069 Sched<[WriteALU, ReadALU, ReadALU]>;
4071 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
4074 !cast<Operand>("asr_operand_" # ty):$Imm6),
4075 "mvn\t$Rd, $Rm, $Imm6",
4076 [(set ty:$Rd, (not (sra ty:$Rm,
4077 !cast<Operand>("asr_operand_" # ty):$Imm6)))],
4079 Sched<[WriteALU, ReadALU, ReadALU]>;
4081 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
4084 !cast<Operand>("ror_operand_" # ty):$Imm6),
4085 "mvn\t$Rd, $Rm, $Imm6",
4086 [(set ty:$Rd, (not (rotr ty:$Rm,
4087 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
4089 Sched<[WriteALU, ReadALU, ReadALU]>;
4092 def _noshift : InstAlias<"mvn $Rn, $Rm",
4093 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
4095 def : Pat<(not ty:$Rm),
4096 (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>;
4099 defm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>;
4100 defm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>;
4102 def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
4103 def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
4105 //===----------------------------------------------------------------------===//
4106 // Move wide (immediate) instructions
4107 //===----------------------------------------------------------------------===//
4108 // Contains: MOVN, MOVZ, MOVK + MOV aliases
4110 // A wide variety of different relocations are needed for variants of these
4111 // instructions, so it turns out that we need a different operand for all of
4113 multiclass movw_operands<string prefix, string instname, int width> {
4114 def _imm_asmoperand : AsmOperandClass {
4115 let Name = instname # width # "Shifted" # shift;
4116 let PredicateMethod = "is" # instname # width # "Imm";
4117 let RenderMethod = "addMoveWideImmOperands";
4118 let ParserMethod = "ParseImmWithLSLOperand";
4119 let DiagnosticType = "MOVWUImm16";
4122 def _imm : Operand<i64> {
4123 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
4124 let PrintMethod = "printMoveWideImmOperand";
4125 let EncoderMethod = "getMoveWideImmOpValue";
4126 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">";
4128 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
4132 defm movn32 : movw_operands<"movn32", "MOVN", 32>;
4133 defm movn64 : movw_operands<"movn64", "MOVN", 64>;
4134 defm movz32 : movw_operands<"movz32", "MOVZ", 32>;
4135 defm movz64 : movw_operands<"movz64", "MOVZ", 64>;
4136 defm movk32 : movw_operands<"movk32", "MOVK", 32>;
4137 defm movk64 : movw_operands<"movk64", "MOVK", 64>;
4139 multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
4142 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
4143 !strconcat(asmop, "\t$Rd, $FullImm"),
4147 let UImm16 = FullImm{15-0};
4148 let Shift = FullImm{17-16};
4151 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
4152 !strconcat(asmop, "\t$Rd, $FullImm"),
4156 let UImm16 = FullImm{15-0};
4157 let Shift = FullImm{17-16};
4161 let isMoveImm = 1, isReMaterializable = 1,
4162 isAsCheapAsAMove = 1, hasSideEffects = 0 in {
4163 defm MOVN : A64I_movwSizes<0b00, "movn",
4164 (ins movn32_imm:$FullImm),
4165 (ins movn64_imm:$FullImm)>;
4167 // Some relocations are able to convert between a MOVZ and a MOVN. If these
4168 // are applied the instruction must be emitted with the corresponding bits as
4169 // 0, which means a MOVZ needs to override that bit from the default.
4170 let PostEncoderMethod = "fixMOVZ" in
4171 defm MOVZ : A64I_movwSizes<0b10, "movz",
4172 (ins movz32_imm:$FullImm),
4173 (ins movz64_imm:$FullImm)>;
4176 let Constraints = "$src = $Rd",
4177 SchedRW = [WriteALU, ReadALU] in
4178 defm MOVK : A64I_movwSizes<0b11, "movk",
4179 (ins GPR32:$src, movk32_imm:$FullImm),
4180 (ins GPR64:$src, movk64_imm:$FullImm)>;
4183 // And now the "MOV" aliases. These also need their own operands because what
4184 // they accept is completely different to what the base instructions accept.
4185 multiclass movalias_operand<string prefix, string basename,
4186 string immpredicate, int width> {
4187 def _asmoperand : AsmOperandClass {
4188 let Name = basename # width # "MovAlias";
4190 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
4192 = "addMoveWideMovAliasOperands<" # width # ", "
4193 # "A64Imms::" # immpredicate # ">";
4196 def _movimm : Operand<i64> {
4197 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
4199 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
4203 defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>;
4204 defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>;
4205 defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>;
4206 defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>;
4208 // FIXME: these are officially canonical aliases, but TableGen is too limited to
4209 // print them at the moment. I believe in this case an "AliasPredicate" method
4210 // will need to be implemented. to allow it, as well as the more generally
4211 // useful handling of non-register, non-constant operands.
4212 class movalias<Instruction INST, RegisterClass GPR, Operand operand>
4213 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>;
4215 def : movalias<MOVZwii, GPR32, movz32_movimm>;
4216 def : movalias<MOVZxii, GPR64, movz64_movimm>;
4217 def : movalias<MOVNwii, GPR32, movn32_movimm>;
4218 def : movalias<MOVNxii, GPR64, movn64_movimm>;
4220 def movw_addressref_g0 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<0>">;
4221 def movw_addressref_g1 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<1>">;
4222 def movw_addressref_g2 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<2>">;
4223 def movw_addressref_g3 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<3>">;
4225 def : Pat<(A64WrapperLarge movw_addressref_g3:$G3, movw_addressref_g2:$G2,
4226 movw_addressref_g1:$G1, movw_addressref_g0:$G0),
4227 (MOVKxii (MOVKxii (MOVKxii (MOVZxii movw_addressref_g3:$G3),
4228 movw_addressref_g2:$G2),
4229 movw_addressref_g1:$G1),
4230 movw_addressref_g0:$G0)>;
4232 //===----------------------------------------------------------------------===//
4233 // PC-relative addressing instructions
4234 //===----------------------------------------------------------------------===//
4235 // Contains: ADR, ADRP
4237 def adr_label : Operand<i64> {
4238 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>";
4240 // This label is a 21-bit offset from PC, unscaled
4241 let PrintMethod = "printLabelOperand<21, 1>";
4242 let ParserMatchClass = label_asmoperand<21, 1>;
4243 let OperandType = "OPERAND_PCREL";
4246 def adrp_label_asmoperand : AsmOperandClass {
4247 let Name = "AdrpLabel";
4248 let RenderMethod = "addLabelOperands<21, 4096>";
4249 let DiagnosticType = "Label";
4252 def adrp_label : Operand<i64> {
4253 let EncoderMethod = "getAdrpLabelOpValue";
4255 // This label is a 21-bit offset from PC, scaled by the page-size: 4096.
4256 let PrintMethod = "printLabelOperand<21, 4096>";
4257 let ParserMatchClass = adrp_label_asmoperand;
4258 let OperandType = "OPERAND_PCREL";
4261 let hasSideEffects = 0 in {
4262 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
4263 "adr\t$Rd, $Label", [], NoItinerary>,
4266 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
4267 "adrp\t$Rd, $Label", [], NoItinerary>,
4271 //===----------------------------------------------------------------------===//
4272 // System instructions
4273 //===----------------------------------------------------------------------===//
4274 // Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS
4275 // + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
4277 // Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
4278 def uimm3_asmoperand : AsmOperandClass {
4280 let PredicateMethod = "isUImm<3>";
4281 let RenderMethod = "addImmOperands";
4282 let DiagnosticType = "UImm3";
4285 def uimm3 : Operand<i32> {
4286 let ParserMatchClass = uimm3_asmoperand;
4289 // The HINT alias can accept a simple unsigned 7-bit immediate.
4290 def uimm7_asmoperand : AsmOperandClass {
4292 let PredicateMethod = "isUImm<7>";
4293 let RenderMethod = "addImmOperands";
4294 let DiagnosticType = "UImm7";
4297 def uimm7 : Operand<i32> {
4298 let ParserMatchClass = uimm7_asmoperand;
4301 // Multiclass namedimm is defined with the prefetch operands. Most of these fit
4302 // into the NamedImmMapper scheme well: they either accept a named operand or
4303 // any immediate under a particular value (which may be 0, implying no immediate
4305 defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">;
4306 defm isb : namedimm<"isb", "A64ISB::ISBMapper">;
4307 defm ic : namedimm<"ic", "A64IC::ICMapper">;
4308 defm dc : namedimm<"dc", "A64DC::DCMapper">;
4309 defm at : namedimm<"at", "A64AT::ATMapper">;
4310 defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">;
4312 // However, MRS and MSR are more complicated for a few reasons:
4313 // * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
4314 // implementation-defined effect
4315 // * Most registers are shared, but some are read-only or write-only.
4316 // * There is a variant of MSR which accepts the same register name (SPSel),
4317 // but which would have a different encoding.
4319 // In principle these could be resolved in with more complicated subclasses of
4320 // NamedImmMapper, however that imposes an overhead on other "named
4321 // immediates". Both in concrete terms with virtual tables and in unnecessary
4324 // The solution adopted here is to take the MRS/MSR Mappers out of the usual
4325 // hierarchy (they're not derived from NamedImmMapper) and to add logic for
4326 // their special situation.
4327 def mrs_asmoperand : AsmOperandClass {
4329 let ParserMethod = "ParseSysRegOperand";
4330 let DiagnosticType = "MRS";
4333 def mrs_op : Operand<i32> {
4334 let ParserMatchClass = mrs_asmoperand;
4335 let PrintMethod = "printMRSOperand";
4336 let DecoderMethod = "DecodeMRSOperand";
4339 def msr_asmoperand : AsmOperandClass {
4340 let Name = "MSRWithReg";
4342 // Note that SPSel is valid for both this and the pstate operands, but with
4343 // different immediate encodings. This is why these operands provide a string
4344 // AArch64Operand rather than an immediate. The overlap is small enough that
4345 // it could be resolved with hackery now, but who can say in future?
4346 let ParserMethod = "ParseSysRegOperand";
4347 let DiagnosticType = "MSR";
4350 def msr_op : Operand<i32> {
4351 let ParserMatchClass = msr_asmoperand;
4352 let PrintMethod = "printMSROperand";
4353 let DecoderMethod = "DecodeMSROperand";
4356 def pstate_asmoperand : AsmOperandClass {
4357 let Name = "MSRPState";
4358 // See comment above about parser.
4359 let ParserMethod = "ParseSysRegOperand";
4360 let DiagnosticType = "MSR";
4363 def pstate_op : Operand<i32> {
4364 let ParserMatchClass = pstate_asmoperand;
4365 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
4366 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
4369 // When <CRn> is specified, an assembler should accept something like "C4", not
4370 // the usual "#4" immediate.
4371 def CRx_asmoperand : AsmOperandClass {
4373 let PredicateMethod = "isUImm<4>";
4374 let RenderMethod = "addImmOperands";
4375 let ParserMethod = "ParseCRxOperand";
4376 // Diagnostics are handled in all cases by ParseCRxOperand.
4379 def CRx : Operand<i32> {
4380 let ParserMatchClass = CRx_asmoperand;
4381 let PrintMethod = "printCRxOperand";
4385 // Finally, we can start defining the instructions.
4387 // HINT is straightforward, with a few aliases.
4388 def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
4391 let CRm = UImm7{6-3};
4392 let Op2 = UImm7{2-0};
4400 def : InstAlias<"nop", (HINTi 0)>;
4401 def : InstAlias<"yield", (HINTi 1)>;
4402 def : InstAlias<"wfe", (HINTi 2)>;
4403 def : InstAlias<"wfi", (HINTi 3)>;
4404 def : InstAlias<"sev", (HINTi 4)>;
4405 def : InstAlias<"sevl", (HINTi 5)>;
4407 // Quite a few instructions then follow a similar pattern of fixing common
4408 // fields in the bitpattern, we'll define a helper-class for them.
4409 class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
4410 Operand operand, string asmop>
4411 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
4421 def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">;
4422 def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">;
4423 def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">;
4424 def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">;
4426 def : InstAlias<"clrex", (CLREXi 0b1111)>;
4427 def : InstAlias<"isb", (ISBi 0b1111)>;
4429 // (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP
4430 // configurations at least.
4431 def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>;
4433 // Any SYS bitpattern can be represented with a complex and opaque "SYS"
4435 def SYSiccix : A64I_system<0b0, (outs),
4436 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
4437 uimm3:$Op2, GPR64:$Rt),
4438 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
4443 // You can skip the Xt argument whether it makes sense or not for the generic
4445 def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2",
4446 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>;
4449 // But many have aliases, which obviously don't fit into
4450 class SYSalias<dag ins, string asmstring>
4451 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
4452 let isAsmParserOnly = 1;
4456 let Op1 = SysOp{13-11};
4457 let CRn = SysOp{10-7};
4458 let CRm = SysOp{6-3};
4459 let Op2 = SysOp{2-0};
4462 def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
4464 def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
4468 def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">;
4469 def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">;
4471 def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
4473 def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
4478 def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
4479 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
4480 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
4485 // The instructions themselves are rather simple for MSR and MRS.
4486 def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
4487 "msr\t$SysReg, $Rt", [], NoItinerary> {
4489 let Op0 = SysReg{15-14};
4490 let Op1 = SysReg{13-11};
4491 let CRn = SysReg{10-7};
4492 let CRm = SysReg{6-3};
4493 let Op2 = SysReg{2-0};
4496 def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
4497 "mrs\t$Rt, $SysReg", [], NoItinerary> {
4499 let Op0 = SysReg{15-14};
4500 let Op1 = SysReg{13-11};
4501 let CRn = SysReg{10-7};
4502 let CRm = SysReg{6-3};
4503 let Op2 = SysReg{2-0};
4506 def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
4507 "msr\t$PState, $CRm", [], NoItinerary> {
4511 let Op1 = PState{5-3};
4513 let Op2 = PState{2-0};
4517 //===----------------------------------------------------------------------===//
4518 // Test & branch (immediate) instructions
4519 //===----------------------------------------------------------------------===//
4520 // Contains: TBZ, TBNZ
4522 // The bit to test is a simple unsigned 6-bit immediate in the X-register
4524 def uimm6 : Operand<i64> {
4525 let ParserMatchClass = uimm6_asmoperand;
4528 def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
4530 def tbimm_target : Operand<OtherVT> {
4531 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
4533 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
4534 let PrintMethod = "printLabelOperand<14, 4>";
4535 let ParserMatchClass = label_wid14_scal4_asmoperand;
4537 let OperandType = "OPERAND_PCREL";
4540 def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>;
4541 def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>;
4543 // These instructions correspond to patterns involving "and" with a power of
4544 // two, which we need to be able to select.
4545 def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
4546 def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
4548 let isBranch = 1, isTerminator = 1 in {
4549 def TBZxii : A64I_TBimm<0b0, (outs),
4550 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4551 "tbz\t$Rt, $Imm, $Label",
4552 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4557 def TBNZxii : A64I_TBimm<0b1, (outs),
4558 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4559 "tbnz\t$Rt, $Imm, $Label",
4560 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4566 // Note, these instructions overlap with the above 64-bit patterns. This is
4567 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both
4568 // do the same thing and are both permitted assembly. They also both have
4569 // sensible DAG patterns.
4570 def TBZwii : A64I_TBimm<0b0, (outs),
4571 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4572 "tbz\t$Rt, $Imm, $Label",
4573 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4580 def TBNZwii : A64I_TBimm<0b1, (outs),
4581 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4582 "tbnz\t$Rt, $Imm, $Label",
4583 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4591 //===----------------------------------------------------------------------===//
4592 // Unconditional branch (immediate) instructions
4593 //===----------------------------------------------------------------------===//
4596 def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
4598 def bimm_target : Operand<OtherVT> {
4599 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
4601 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4602 let PrintMethod = "printLabelOperand<26, 4>";
4603 let ParserMatchClass = label_wid26_scal4_asmoperand;
4605 let OperandType = "OPERAND_PCREL";
4608 def blimm_target : Operand<i64> {
4609 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
4611 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4612 let PrintMethod = "printLabelOperand<26, 4>";
4613 let ParserMatchClass = label_wid26_scal4_asmoperand;
4615 let OperandType = "OPERAND_PCREL";
4618 class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type>
4619 : A64I_Bimm<op, (outs), (ins lbl_type:$Label),
4620 !strconcat(asmop, "\t$Label"), patterns,
4624 let isBranch = 1 in {
4625 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
4626 let isTerminator = 1;
4630 let SchedRW = [WriteBrL] in {
4631 def BLimm : A64I_BimmImpl<0b1, "bl",
4632 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4639 def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>;
4641 //===----------------------------------------------------------------------===//
4642 // Unconditional branch (register) instructions
4643 //===----------------------------------------------------------------------===//
4644 // Contains: BR, BLR, RET, ERET, DRP.
4646 // Most of the notional opcode fields in the A64I_Breg format are fixed in A64
4648 class A64I_BregImpl<bits<4> opc,
4649 dag outs, dag ins, string asmstr, list<dag> patterns,
4650 InstrItinClass itin = NoItinerary>
4651 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
4652 outs, ins, asmstr, patterns, itin>,
4655 let isIndirectBranch = 1;
4658 // Note that these are not marked isCall or isReturn because as far as LLVM is
4659 // concerned they're not. "ret" is just another jump unless it has been selected
4660 // by LLVM as the function's return.
4662 let isBranch = 1 in {
4663 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
4664 "br\t$Rn", [(brind i64:$Rn)]> {
4666 let isTerminator = 1;
4669 let SchedRW = [WriteBrL] in {
4670 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4671 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4678 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
4681 let isTerminator = 1;
4685 // Create a separate pseudo-instruction for codegen to use so that we don't
4686 // flag x30 as used in every function. It'll be restored before the RET by the
4687 // epilogue if it's legitimately used.
4688 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
4689 let isTerminator = 1;
4694 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
4697 let isTerminator = 1;
4701 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
4707 def RETAlias : InstAlias<"ret", (RETx X30)>;
4710 //===----------------------------------------------------------------------===//
4711 // Address generation patterns
4712 //===----------------------------------------------------------------------===//
4714 // Primary method of address generation for the small/absolute memory model is
4715 // an ADRP/ADR pair:
4716 // ADRP x0, some_variable
4717 // ADD x0, x0, #:lo12:some_variable
4719 // The load/store elision of the ADD is accomplished when selecting
4720 // addressing-modes. This just mops up the cases where that doesn't work and we
4721 // really need an address in some register.
4723 // This wrapper applies a LO12 modifier to the address. Otherwise we could just
4724 // use the same address.
4726 class ADRP_ADD<SDNode Wrapper, SDNode addrop>
4727 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)),
4728 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>;
4730 def : ADRP_ADD<A64WrapperSmall, tblockaddress>;
4731 def : ADRP_ADD<A64WrapperSmall, texternalsym>;
4732 def : ADRP_ADD<A64WrapperSmall, tglobaladdr>;
4733 def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>;
4734 def : ADRP_ADD<A64WrapperSmall, tjumptable>;
4735 def : ADRP_ADD<A64WrapperSmall, tconstpool>;
4737 //===----------------------------------------------------------------------===//
4738 // GOT access patterns
4739 //===----------------------------------------------------------------------===//
4741 class GOTLoadSmall<SDNode addrfrag>
4742 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)),
4743 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>;
4745 def : GOTLoadSmall<texternalsym>;
4746 def : GOTLoadSmall<tglobaladdr>;
4747 def : GOTLoadSmall<tglobaltlsaddr>;
4749 //===----------------------------------------------------------------------===//
4750 // Tail call handling
4751 //===----------------------------------------------------------------------===//
4753 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
4755 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
4756 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
4759 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff),
4760 [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>;
4763 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
4765 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
4766 (Bimm bimm_target:$Label)>;
4768 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [],
4773 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
4774 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>;
4776 //===----------------------------------------------------------------------===//
4777 // Thread local storage
4778 //===----------------------------------------------------------------------===//
4780 // This is a pseudo-instruction representing the ".tlsdesccall" directive in
4781 // assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the
4782 // current location. It should always be immediately followed by a BLR
4783 // instruction, and is intended solely for relaxation by the linker.
4785 def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
4787 def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
4788 let hasSideEffects = 1;
4791 def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
4792 [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> {
4797 def : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var),
4798 (TLSDESC_BLRx $Rn, texternalsym:$Var)>;
4800 //===----------------------------------------------------------------------===//
4801 // Bitfield patterns
4802 //===----------------------------------------------------------------------===//
4804 def bfi32_lsb_to_immr : SDNodeXForm<imm, [{
4805 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64);
4808 def bfi64_lsb_to_immr : SDNodeXForm<imm, [{
4809 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64);
4812 def bfi_width_to_imms : SDNodeXForm<imm, [{
4813 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64);
4817 // The simpler patterns deal with cases where no AND mask is actually needed
4818 // (either all bits are used or the low 32 bits are used).
4819 let AddedComplexity = 10 in {
4821 def : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4823 (bfi64_lsb_to_immr (i64 imm:$ImmR)),
4824 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4826 def : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS),
4828 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4829 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4832 def : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4834 (SUBREG_TO_REG (i64 0),
4835 (BFIwwii (EXTRACT_SUBREG $src, sub_32),
4836 (EXTRACT_SUBREG $Rn, sub_32),
4837 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4838 (bfi_width_to_imms (i64 imm:$ImmS))),
4843 //===----------------------------------------------------------------------===//
4844 // Miscellaneous patterns
4845 //===----------------------------------------------------------------------===//
4847 // Truncation from 64 to 32-bits just involves renaming your register.
4848 def : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>;
4850 // Similarly, extension where we don't care about the high bits is
4852 def : Pat<(i64 (anyext i32:$val)),
4853 (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>;
4855 // SELECT instructions providing f128 types need to be handled by a
4856 // pseudo-instruction since the eventual code will need to introduce basic
4857 // blocks and control flow.
4858 def F128CSEL : PseudoInst<(outs FPR128:$Rd),
4859 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
4860 [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> {
4862 let usesCustomInserter = 1;
4865 //===----------------------------------------------------------------------===//
4866 // Load/store patterns
4867 //===----------------------------------------------------------------------===//
4869 // There are lots of patterns here, because we need to allow at least three
4870 // parameters to vary independently.
4871 // 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ...
4872 // 2. LLVM source: zextloadi8, anyextloadi8, ...
4873 // 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ...
4875 // The biggest problem turns out to be the address-generation variable. At the
4876 // point of instantiation we need to produce two DAGs, one for the pattern and
4877 // one for the instruction. Doing this at the lowest level of classes doesn't
4880 // Consider the simple uimm12 addressing mode, and the desire to match both (add
4881 // GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the
4882 // instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or
4883 // "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this
4884 // operation, and PatFrags are for selection not output.
4886 // As a result, the address-generation patterns are the final
4887 // instantiations. However, we do still need to vary the operand for the address
4888 // further down (At the point we're deciding A64WrapperSmall, we don't know
4889 // the memory width of the operation).
4891 //===------------------------------
4892 // 1. Basic infrastructural defs
4893 //===------------------------------
4895 // First, some simple classes for !foreach and !subst to use:
4906 // You can't use !subst on an actual immediate, but you *can* use it on an
4907 // operand record that happens to match a single immediate. So we do.
4908 def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>;
4909 def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>;
4910 def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>;
4911 def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>;
4912 def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>;
4914 // If the low bits of a pointer are known to be 0 then an "or" is just as good
4915 // as addition for computing an offset. This fragment forwards that check for
4917 def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),
4919 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
4922 // Load/store (unsigned immediate) operations with relocations against global
4923 // symbols (for lo12) are only valid if those symbols have correct alignment
4924 // (since the immediate offset is divided by the access scale, it can't have a
4927 // The guaranteed alignment is provided as part of the WrapperSmall
4928 // operation, and checked against one of these.
4929 def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>;
4930 def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>;
4931 def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>;
4932 def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>;
4933 def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>;
4935 // "Normal" load/store instructions can be used on atomic operations, provided
4936 // the ordering parameter is at most "monotonic". Anything above that needs
4937 // special handling with acquire/release instructions.
4938 class simple_load<PatFrag base>
4939 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4940 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4943 def atomic_load_simple_i8 : simple_load<atomic_load_8>;
4944 def atomic_load_simple_i16 : simple_load<atomic_load_16>;
4945 def atomic_load_simple_i32 : simple_load<atomic_load_32>;
4946 def atomic_load_simple_i64 : simple_load<atomic_load_64>;
4948 class simple_store<PatFrag base>
4949 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4950 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4953 def atomic_store_simple_i8 : simple_store<atomic_store_8>;
4954 def atomic_store_simple_i16 : simple_store<atomic_store_16>;
4955 def atomic_store_simple_i32 : simple_store<atomic_store_32>;
4956 def atomic_store_simple_i64 : simple_store<atomic_store_64>;
4958 //===------------------------------
4959 // 2. UImm12 and SImm9
4960 //===------------------------------
4962 // These instructions have two operands providing the address so they can be
4963 // treated similarly for most purposes.
4965 //===------------------------------
4966 // 2.1 Base patterns covering extend/truncate semantics
4967 //===------------------------------
4969 // Atomic patterns can be shared between integer operations of all sizes, a
4970 // quick multiclass here allows reuse.
4971 multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4972 dag Offset, dag address, ValueType transty,
4974 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4975 (LOAD Base, Offset)>;
4977 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
4978 (STORE $Rt, Base, Offset)>;
4981 // Instructions accessing a memory chunk smaller than a register (or, in a
4982 // pinch, the same size) have a characteristic set of patterns they want to
4983 // match: extending loads and truncating stores. This class deals with the
4984 // sign-neutral version of those patterns.
4986 // It will be instantiated across multiple addressing-modes.
4987 multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
4988 dag Base, dag Offset,
4989 dag address, ValueType sty>
4990 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> {
4991 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
4993 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
4995 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4996 // register was actually set.
4997 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4998 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
5000 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
5001 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
5003 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
5004 (STORE $Rt, Base, Offset)>;
5006 // For truncating store from 64-bits, we have to manually tell LLVM to
5007 // ignore the high bits of the x register.
5008 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
5009 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
5012 // Next come patterns for sign-extending loads.
5013 multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
5014 dag address, ValueType sty> {
5015 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
5016 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
5018 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
5019 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>;
5023 // and finally "natural-width" loads and stores come next.
5024 multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
5025 dag Offset, dag address, ValueType sty> {
5026 def : Pat<(sty (load address)), (LOAD Base, Offset)>;
5027 def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>;
5030 // Integer operations also get atomic instructions to select for.
5031 multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
5032 dag Offset, dag address, ValueType sty>
5033 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>,
5034 ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>;
5036 //===------------------------------
5037 // 2.2. Addressing-mode instantiations
5038 //===------------------------------
5040 multiclass uimm12_pats<dag address, dag Base, dag Offset> {
5041 defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
5042 !foreach(decls.pattern, Offset,
5043 !subst(OFFSET, byte_uimm12, decls.pattern)),
5044 !foreach(decls.pattern, address,
5045 !subst(OFFSET, byte_uimm12,
5046 !subst(ALIGN, any_align, decls.pattern))),
5048 defm : ls_small_pats<LS16_LDR, LS16_STR, Base,
5049 !foreach(decls.pattern, Offset,
5050 !subst(OFFSET, hword_uimm12, decls.pattern)),
5051 !foreach(decls.pattern, address,
5052 !subst(OFFSET, hword_uimm12,
5053 !subst(ALIGN, min_align2, decls.pattern))),
5055 defm : ls_small_pats<LS32_LDR, LS32_STR, Base,
5056 !foreach(decls.pattern, Offset,
5057 !subst(OFFSET, word_uimm12, decls.pattern)),
5058 !foreach(decls.pattern, address,
5059 !subst(OFFSET, word_uimm12,
5060 !subst(ALIGN, min_align4, decls.pattern))),
5063 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base,
5064 !foreach(decls.pattern, Offset,
5065 !subst(OFFSET, word_uimm12, decls.pattern)),
5066 !foreach(decls.pattern, address,
5067 !subst(OFFSET, word_uimm12,
5068 !subst(ALIGN, min_align4, decls.pattern))),
5071 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base,
5072 !foreach(decls.pattern, Offset,
5073 !subst(OFFSET, dword_uimm12, decls.pattern)),
5074 !foreach(decls.pattern, address,
5075 !subst(OFFSET, dword_uimm12,
5076 !subst(ALIGN, min_align8, decls.pattern))),
5079 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base,
5080 !foreach(decls.pattern, Offset,
5081 !subst(OFFSET, hword_uimm12, decls.pattern)),
5082 !foreach(decls.pattern, address,
5083 !subst(OFFSET, hword_uimm12,
5084 !subst(ALIGN, min_align2, decls.pattern))),
5087 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base,
5088 !foreach(decls.pattern, Offset,
5089 !subst(OFFSET, word_uimm12, decls.pattern)),
5090 !foreach(decls.pattern, address,
5091 !subst(OFFSET, word_uimm12,
5092 !subst(ALIGN, min_align4, decls.pattern))),
5095 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
5096 !foreach(decls.pattern, Offset,
5097 !subst(OFFSET, dword_uimm12, decls.pattern)),
5098 !foreach(decls.pattern, address,
5099 !subst(OFFSET, dword_uimm12,
5100 !subst(ALIGN, min_align8, decls.pattern))),
5103 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
5104 !foreach(decls.pattern, Offset,
5105 !subst(OFFSET, qword_uimm12, decls.pattern)),
5106 !foreach(decls.pattern, address,
5107 !subst(OFFSET, qword_uimm12,
5108 !subst(ALIGN, min_align16, decls.pattern))),
5111 defm : load_signed_pats<"B", "", Base,
5112 !foreach(decls.pattern, Offset,
5113 !subst(OFFSET, byte_uimm12, decls.pattern)),
5114 !foreach(decls.pattern, address,
5115 !subst(OFFSET, byte_uimm12,
5116 !subst(ALIGN, any_align, decls.pattern))),
5119 defm : load_signed_pats<"H", "", Base,
5120 !foreach(decls.pattern, Offset,
5121 !subst(OFFSET, hword_uimm12, decls.pattern)),
5122 !foreach(decls.pattern, address,
5123 !subst(OFFSET, hword_uimm12,
5124 !subst(ALIGN, min_align2, decls.pattern))),
5127 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5128 !subst(OFFSET, word_uimm12,
5129 !subst(ALIGN, min_align4, decls.pattern)))),
5130 (LDRSWx Base, !foreach(decls.pattern, Offset,
5131 !subst(OFFSET, word_uimm12, decls.pattern)))>;
5134 // Straightforward patterns of last resort: a pointer with or without an
5135 // appropriate offset.
5136 defm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>;
5137 defm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12),
5138 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
5140 // The offset could be hidden behind an "or", of course:
5141 defm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12),
5142 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
5144 // Global addresses under the small-absolute model should use these
5145 // instructions. There are ELF relocations specifically for it.
5146 defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
5147 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
5149 defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
5151 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
5153 // External symbols that make it this far should also get standard relocations.
5154 defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
5156 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
5158 defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
5159 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
5161 // We also want to use uimm12 instructions for local variables at the moment.
5162 def tframeindex_XFORM : SDNodeXForm<frameindex, [{
5163 int FI = cast<FrameIndexSDNode>(N)->getIndex();
5164 return CurDAG->getTargetFrameIndex(FI, MVT::i64);
5167 defm : uimm12_pats<(i64 frameindex:$Rn),
5168 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>;
5170 // These can be much simpler than uimm12 because we don't to change the operand
5171 // type (e.g. LDURB and LDURH take the same operands).
5172 multiclass simm9_pats<dag address, dag Base, dag Offset> {
5173 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
5174 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
5176 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>;
5177 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>;
5179 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>;
5180 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>;
5181 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>;
5182 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address,
5185 def : Pat<(i64 (zextloadi32 address)),
5186 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
5188 def : Pat<(truncstorei32 i64:$Rt, address),
5189 (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
5191 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>;
5192 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>;
5193 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>;
5196 defm : simm9_pats<(add i64:$Rn, simm9:$SImm9),
5197 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
5199 defm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9),
5200 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
5203 //===------------------------------
5204 // 3. Register offset patterns
5205 //===------------------------------
5207 // Atomic patterns can be shared between integer operations of all sizes, a
5208 // quick multiclass here allows reuse.
5209 multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
5210 dag Offset, dag Extend, dag address,
5211 ValueType transty, ValueType sty> {
5212 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
5213 (LOAD Base, Offset, Extend)>;
5215 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
5216 (STORE $Rt, Base, Offset, Extend)>;
5219 // The register offset instructions take three operands giving the instruction,
5220 // and have an annoying split between instructions where Rm is 32-bit and
5221 // 64-bit. So we need a special hierarchy to describe them. Other than that the
5222 // same operations should be supported as for simm9 and uimm12 addressing.
5224 multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
5225 dag Base, dag Offset, dag Extend,
5226 dag address, ValueType sty>
5227 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> {
5228 def : Pat<(!cast<SDNode>(zextload # sty) address),
5229 (LOAD Base, Offset, Extend)>;
5231 def : Pat<(!cast<SDNode>(extload # sty) address),
5232 (LOAD Base, Offset, Extend)>;
5234 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
5235 // register was actually set.
5236 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
5237 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
5239 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
5240 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
5242 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
5243 (STORE $Rt, Base, Offset, Extend)>;
5245 // For truncating store from 64-bits, we have to manually tell LLVM to
5246 // ignore the high bits of the x register.
5247 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
5248 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>;
5252 // Next come patterns for sign-extending loads.
5253 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
5254 dag address, ValueType sty> {
5255 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
5256 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
5257 Base, Offset, Extend)>;
5259 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
5260 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
5261 Base, Offset, Extend)>;
5264 // and finally "natural-width" loads and stores come next.
5265 multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
5266 dag Base, dag Offset, dag Extend, dag address,
5268 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
5269 def : Pat<(store sty:$Rt, address),
5270 (STORE $Rt, Base, Offset, Extend)>;
5273 multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
5274 dag Base, dag Offset, dag Extend, dag address,
5276 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>,
5277 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>;
5279 multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
5281 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
5282 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
5283 Base, Offset, Extend,
5284 !foreach(decls.pattern, address,
5285 !subst(SHIFT, imm_eq0, decls.pattern)),
5287 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"),
5288 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"),
5289 Base, Offset, Extend,
5290 !foreach(decls.pattern, address,
5291 !subst(SHIFT, imm_eq1, decls.pattern)),
5293 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5294 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5295 Base, Offset, Extend,
5296 !foreach(decls.pattern, address,
5297 !subst(SHIFT, imm_eq2, decls.pattern)),
5300 defm : ro_int_neutral_pats<
5301 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5302 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5303 Base, Offset, Extend,
5304 !foreach(decls.pattern, address,
5305 !subst(SHIFT, imm_eq2, decls.pattern)),
5308 defm : ro_int_neutral_pats<
5309 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
5310 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
5311 Base, Offset, Extend,
5312 !foreach(decls.pattern, address,
5313 !subst(SHIFT, imm_eq3, decls.pattern)),
5316 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
5317 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
5318 Base, Offset, Extend,
5319 !foreach(decls.pattern, address,
5320 !subst(SHIFT, imm_eq1, decls.pattern)),
5323 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"),
5324 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"),
5325 Base, Offset, Extend,
5326 !foreach(decls.pattern, address,
5327 !subst(SHIFT, imm_eq2, decls.pattern)),
5330 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"),
5331 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"),
5332 Base, Offset, Extend,
5333 !foreach(decls.pattern, address,
5334 !subst(SHIFT, imm_eq3, decls.pattern)),
5337 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"),
5338 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"),
5339 Base, Offset, Extend,
5340 !foreach(decls.pattern, address,
5341 !subst(SHIFT, imm_eq4, decls.pattern)),
5344 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
5345 !foreach(decls.pattern, address,
5346 !subst(SHIFT, imm_eq0, decls.pattern)),
5349 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend,
5350 !foreach(decls.pattern, address,
5351 !subst(SHIFT, imm_eq1, decls.pattern)),
5354 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5355 !subst(SHIFT, imm_eq2, decls.pattern))),
5356 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset")
5357 Base, Offset, Extend)>;
5361 // Finally we're in a position to tell LLVM exactly what addresses are reachable
5362 // using register-offset instructions. Essentially a base plus a possibly
5363 // extended, possibly shifted (by access size) offset.
5365 defm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)),
5366 (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>;
5368 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)),
5369 (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>;
5371 defm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)),
5372 (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>;
5374 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)),
5375 (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>;
5377 defm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm),
5378 (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>;
5380 defm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)),
5381 (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>;
5383 //===----------------------------------------------------------------------===//
5384 // Advanced SIMD (NEON) Support
5387 include "AArch64InstrNEON.td"