1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
20 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
21 def HasNEON : Predicate<"Subtarget->hasNEON()">,
22 AssemblerPredicate<"FeatureNEON", "neon">;
23 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
24 AssemblerPredicate<"FeatureCrypto", "crypto">;
25 def HasCRC : Predicate<"Subtarget->hasCRC()">,
26 AssemblerPredicate<"FeatureCRC", "crc">;
27 def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;
28 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
29 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
30 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
32 //===----------------------------------------------------------------------===//
33 // AArch64-specific DAG Nodes.
36 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
37 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
43 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
49 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
50 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
57 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
58 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
60 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
61 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
62 SDTCisVT<2, OtherVT>]>;
65 def SDT_AArch64CSel : SDTypeProfile<1, 4,
70 def SDT_AArch64CCMP : SDTypeProfile<1, 5,
77 def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
84 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
87 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
88 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
89 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
92 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
93 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
94 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
95 SDTCisInt<2>, SDTCisInt<3>]>;
96 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
97 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
98 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
99 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
101 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
102 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
103 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
104 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
106 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
109 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
110 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
112 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
114 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
117 // Generates the general dynamic sequences, i.e.
118 // adrp x0, :tlsdesc:var
119 // ldr x1, [x0, #:tlsdesc_lo12:var]
120 // add x0, x0, #:tlsdesc_lo12:var
124 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
125 // number of operands (the variable)
126 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
129 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
130 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
131 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
132 SDTCisSameAs<1, 4>]>;
136 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
137 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
138 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
139 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
140 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
141 [SDNPHasChain, SDNPOutGlue]>;
142 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
143 SDCallSeqEnd<[ SDTCisVT<0, i32>,
145 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
146 def AArch64call : SDNode<"AArch64ISD::CALL",
147 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
150 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
152 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
154 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
156 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
158 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
162 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
163 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
164 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
165 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
166 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
167 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
168 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
169 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
170 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
172 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
173 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
175 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
176 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
178 def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;
179 def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;
180 def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
182 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
184 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
186 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
187 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
188 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
189 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
190 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
192 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
193 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
194 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
195 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
196 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
197 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
199 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
200 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
201 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
202 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
203 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
204 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
205 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
207 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
208 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
209 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
210 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
212 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
213 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
214 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
215 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
216 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
217 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
218 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
219 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
221 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
222 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
223 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
225 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
226 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
227 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
228 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
229 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
231 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
232 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
233 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
235 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
236 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
237 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
238 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
239 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
240 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
241 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
243 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
244 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
245 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
246 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
247 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
249 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
250 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
252 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
254 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
255 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
257 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
258 [SDNPHasChain, SDNPSideEffect]>;
260 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
261 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
263 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
264 SDT_AArch64TLSDescCallSeq,
265 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
269 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
270 SDT_AArch64WrapperLarge>;
272 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
274 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
275 SDTCisSameAs<1, 2>]>;
276 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
277 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
279 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
280 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
281 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
282 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
283 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
284 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
286 //===----------------------------------------------------------------------===//
288 //===----------------------------------------------------------------------===//
290 // AArch64 Instruction Predicate Definitions.
292 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
293 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
294 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
295 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
296 def ForCodeSize : Predicate<"ForCodeSize">;
297 def NotForCodeSize : Predicate<"!ForCodeSize">;
299 include "AArch64InstrFormats.td"
301 //===----------------------------------------------------------------------===//
303 //===----------------------------------------------------------------------===//
304 // Miscellaneous instructions.
305 //===----------------------------------------------------------------------===//
307 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
308 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
309 [(AArch64callseq_start timm:$amt)]>;
310 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
311 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
312 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
314 let isReMaterializable = 1, isCodeGenOnly = 1 in {
315 // FIXME: The following pseudo instructions are only needed because remat
316 // cannot handle multiple instructions. When that changes, they can be
317 // removed, along with the AArch64Wrapper node.
319 let AddedComplexity = 10 in
320 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
321 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
324 // The MOVaddr instruction should match only when the add is not folded
325 // into a load or store address.
327 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
328 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
329 tglobaladdr:$low))]>,
330 Sched<[WriteAdrAdr]>;
332 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
333 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
335 Sched<[WriteAdrAdr]>;
337 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
338 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
340 Sched<[WriteAdrAdr]>;
342 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
343 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
344 tblockaddress:$low))]>,
345 Sched<[WriteAdrAdr]>;
347 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
348 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
349 tglobaltlsaddr:$low))]>,
350 Sched<[WriteAdrAdr]>;
352 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
353 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
354 texternalsym:$low))]>,
355 Sched<[WriteAdrAdr]>;
357 } // isReMaterializable, isCodeGenOnly
359 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
360 (LOADgot tglobaltlsaddr:$addr)>;
362 def : Pat<(AArch64LOADgot texternalsym:$addr),
363 (LOADgot texternalsym:$addr)>;
365 def : Pat<(AArch64LOADgot tconstpool:$addr),
366 (LOADgot tconstpool:$addr)>;
368 //===----------------------------------------------------------------------===//
369 // System instructions.
370 //===----------------------------------------------------------------------===//
372 def HINT : HintI<"hint">;
373 def : InstAlias<"nop", (HINT 0b000)>;
374 def : InstAlias<"yield",(HINT 0b001)>;
375 def : InstAlias<"wfe", (HINT 0b010)>;
376 def : InstAlias<"wfi", (HINT 0b011)>;
377 def : InstAlias<"sev", (HINT 0b100)>;
378 def : InstAlias<"sevl", (HINT 0b101)>;
380 // As far as LLVM is concerned this writes to the system's exclusive monitors.
381 let mayLoad = 1, mayStore = 1 in
382 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
384 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
385 // model patterns with sufficiently fine granularity.
386 let mayLoad = ?, mayStore = ? in {
387 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
388 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
390 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
391 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
393 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
394 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
397 def : InstAlias<"clrex", (CLREX 0xf)>;
398 def : InstAlias<"isb", (ISB 0xf)>;
402 def MSRpstate: MSRpstateI;
404 // The thread pointer (on Linux, at least, where this has been implemented) is
406 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
408 // The cycle counter PMC register is PMCCNTR_EL0.
409 let Predicates = [HasPerfMon] in
410 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
412 // Generic system instructions
413 def SYSxt : SystemXtI<0, "sys">;
414 def SYSLxt : SystemLXtI<1, "sysl">;
416 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
417 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
418 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
420 //===----------------------------------------------------------------------===//
421 // Move immediate instructions.
422 //===----------------------------------------------------------------------===//
424 defm MOVK : InsertImmediate<0b11, "movk">;
425 defm MOVN : MoveImmediate<0b00, "movn">;
427 let PostEncoderMethod = "fixMOVZ" in
428 defm MOVZ : MoveImmediate<0b10, "movz">;
430 // First group of aliases covers an implicit "lsl #0".
431 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
432 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
433 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
434 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
435 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
436 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
438 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
439 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
440 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
441 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
442 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
444 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
445 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
446 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
447 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
449 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
450 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
451 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
452 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
454 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
455 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
457 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
458 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
460 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
461 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
463 // Final group of aliases covers true "mov $Rd, $imm" cases.
464 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
465 int width, int shift> {
466 def _asmoperand : AsmOperandClass {
467 let Name = basename # width # "_lsl" # shift # "MovAlias";
468 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
470 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
473 def _movimm : Operand<i32> {
474 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
477 def : InstAlias<"mov $Rd, $imm",
478 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
481 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
482 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
484 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
485 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
486 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
487 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
489 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
490 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
492 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
493 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
494 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
495 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
497 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
498 isAsCheapAsAMove = 1 in {
499 // FIXME: The following pseudo instructions are only needed because remat
500 // cannot handle multiple instructions. When that changes, we can select
501 // directly to the real instructions and get rid of these pseudos.
504 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
505 [(set GPR32:$dst, imm:$src)]>,
508 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
509 [(set GPR64:$dst, imm:$src)]>,
511 } // isReMaterializable, isCodeGenOnly
513 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
514 // eventual expansion code fewer bits to worry about getting right. Marshalling
515 // the types is a little tricky though:
516 def i64imm_32bit : ImmLeaf<i64, [{
517 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
520 def trunc_imm : SDNodeXForm<imm, [{
521 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
524 def : Pat<(i64 i64imm_32bit:$src),
525 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
527 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
528 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
529 return CurDAG->getTargetConstant(
530 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
533 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
534 return CurDAG->getTargetConstant(
535 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
539 def : Pat<(f32 fpimm:$in),
540 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
541 def : Pat<(f64 fpimm:$in),
542 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
545 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
547 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
548 tglobaladdr:$g1, tglobaladdr:$g0),
549 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
550 tglobaladdr:$g2, 32),
551 tglobaladdr:$g1, 16),
552 tglobaladdr:$g0, 0)>;
554 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
555 tblockaddress:$g1, tblockaddress:$g0),
556 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
557 tblockaddress:$g2, 32),
558 tblockaddress:$g1, 16),
559 tblockaddress:$g0, 0)>;
561 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
562 tconstpool:$g1, tconstpool:$g0),
563 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
568 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
569 tjumptable:$g1, tjumptable:$g0),
570 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
576 //===----------------------------------------------------------------------===//
577 // Arithmetic instructions.
578 //===----------------------------------------------------------------------===//
580 // Add/subtract with carry.
581 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
582 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
584 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
585 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
586 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
587 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
590 defm ADD : AddSub<0, "add", "sub", add>;
591 defm SUB : AddSub<1, "sub", "add">;
593 def : InstAlias<"mov $dst, $src",
594 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
595 def : InstAlias<"mov $dst, $src",
596 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
597 def : InstAlias<"mov $dst, $src",
598 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
599 def : InstAlias<"mov $dst, $src",
600 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
602 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
603 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
605 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
606 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
607 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
608 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
609 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
610 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
611 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
612 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
613 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
614 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
615 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
616 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
617 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
618 let AddedComplexity = 1 in {
619 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
620 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
621 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
622 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
625 // Because of the immediate format for add/sub-imm instructions, the
626 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
627 // These patterns capture that transformation.
628 let AddedComplexity = 1 in {
629 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
630 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
631 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
632 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
633 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
634 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
635 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
636 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
639 // Because of the immediate format for add/sub-imm instructions, the
640 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
641 // These patterns capture that transformation.
642 let AddedComplexity = 1 in {
643 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
644 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
645 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
646 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
647 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
648 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
649 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
650 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
653 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
654 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
655 def : InstAlias<"neg $dst, $src$shift",
656 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
657 def : InstAlias<"neg $dst, $src$shift",
658 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
660 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
661 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
662 def : InstAlias<"negs $dst, $src$shift",
663 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
664 def : InstAlias<"negs $dst, $src$shift",
665 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
668 // Unsigned/Signed divide
669 defm UDIV : Div<0, "udiv", udiv>;
670 defm SDIV : Div<1, "sdiv", sdiv>;
671 let isCodeGenOnly = 1 in {
672 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
673 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
677 defm ASRV : Shift<0b10, "asr", sra>;
678 defm LSLV : Shift<0b00, "lsl", shl>;
679 defm LSRV : Shift<0b01, "lsr", srl>;
680 defm RORV : Shift<0b11, "ror", rotr>;
682 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
683 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
684 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
685 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
686 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
687 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
688 def : ShiftAlias<"rorv", RORVWr, GPR32>;
689 def : ShiftAlias<"rorv", RORVXr, GPR64>;
692 let AddedComplexity = 7 in {
693 defm MADD : MulAccum<0, "madd", add>;
694 defm MSUB : MulAccum<1, "msub", sub>;
696 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
697 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
698 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
699 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
701 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
702 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
703 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
704 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
705 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
706 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
707 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
708 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
709 } // AddedComplexity = 7
711 let AddedComplexity = 5 in {
712 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
713 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
714 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
715 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
717 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
718 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
719 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
720 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
722 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
723 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
724 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
725 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
726 } // AddedComplexity = 5
728 def : MulAccumWAlias<"mul", MADDWrrr>;
729 def : MulAccumXAlias<"mul", MADDXrrr>;
730 def : MulAccumWAlias<"mneg", MSUBWrrr>;
731 def : MulAccumXAlias<"mneg", MSUBXrrr>;
732 def : WideMulAccumAlias<"smull", SMADDLrrr>;
733 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
734 def : WideMulAccumAlias<"umull", UMADDLrrr>;
735 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
738 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
739 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
742 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
743 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
744 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
745 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
747 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
748 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
749 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
750 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
753 defm CAS : CompareAndSwap<0, 0, "">;
754 defm CASA : CompareAndSwap<1, 0, "a">;
755 defm CASL : CompareAndSwap<0, 1, "l">;
756 defm CASAL : CompareAndSwap<1, 1, "al">;
759 defm CASP : CompareAndSwapPair<0, 0, "">;
760 defm CASPA : CompareAndSwapPair<1, 0, "a">;
761 defm CASPL : CompareAndSwapPair<0, 1, "l">;
762 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
765 defm SWP : Swap<0, 0, "">;
766 defm SWPA : Swap<1, 0, "a">;
767 defm SWPL : Swap<0, 1, "l">;
768 defm SWPAL : Swap<1, 1, "al">;
770 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
771 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
772 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
773 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
774 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
776 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
777 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
778 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
779 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
781 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
782 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
783 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
784 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
786 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
787 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
788 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
789 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
791 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
792 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
793 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
794 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
796 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
797 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
798 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
799 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
801 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
802 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
803 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
804 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
806 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
807 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
808 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
809 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
811 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
812 defm : STOPregister<"stadd","LDADD">; // STADDx
813 defm : STOPregister<"stclr","LDCLR">; // STCLRx
814 defm : STOPregister<"steor","LDEOR">; // STEORx
815 defm : STOPregister<"stset","LDSET">; // STSETx
816 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
817 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
818 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
819 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
821 //===----------------------------------------------------------------------===//
822 // Logical instructions.
823 //===----------------------------------------------------------------------===//
826 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
827 defm AND : LogicalImm<0b00, "and", and, "bic">;
828 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
829 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
831 // FIXME: these aliases *are* canonical sometimes (when movz can't be
832 // used). Actually, it seems to be working right now, but putting logical_immXX
833 // here is a bit dodgy on the AsmParser side too.
834 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
835 logical_imm32:$imm), 0>;
836 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
837 logical_imm64:$imm), 0>;
841 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
842 defm BICS : LogicalRegS<0b11, 1, "bics",
843 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
844 defm AND : LogicalReg<0b00, 0, "and", and>;
845 defm BIC : LogicalReg<0b00, 1, "bic",
846 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
847 defm EON : LogicalReg<0b10, 1, "eon",
848 BinOpFrag<(not (xor node:$LHS, node:$RHS))>>;
849 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
850 defm ORN : LogicalReg<0b01, 1, "orn",
851 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
852 defm ORR : LogicalReg<0b01, 0, "orr", or>;
854 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
855 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
857 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
858 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
860 def : InstAlias<"mvn $Wd, $Wm$sh",
861 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
862 def : InstAlias<"mvn $Xd, $Xm$sh",
863 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
865 def : InstAlias<"tst $src1, $src2",
866 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
867 def : InstAlias<"tst $src1, $src2",
868 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
870 def : InstAlias<"tst $src1, $src2",
871 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
872 def : InstAlias<"tst $src1, $src2",
873 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
875 def : InstAlias<"tst $src1, $src2$sh",
876 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
877 def : InstAlias<"tst $src1, $src2$sh",
878 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
881 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
882 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
885 //===----------------------------------------------------------------------===//
886 // One operand data processing instructions.
887 //===----------------------------------------------------------------------===//
889 defm CLS : OneOperandData<0b101, "cls">;
890 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
891 defm RBIT : OneOperandData<0b000, "rbit">;
893 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
894 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
896 def REV16Wr : OneWRegData<0b001, "rev16",
897 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
898 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
900 def : Pat<(cttz GPR32:$Rn),
901 (CLZWr (RBITWr GPR32:$Rn))>;
902 def : Pat<(cttz GPR64:$Rn),
903 (CLZXr (RBITXr GPR64:$Rn))>;
904 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
907 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
911 // Unlike the other one operand instructions, the instructions with the "rev"
912 // mnemonic do *not* just different in the size bit, but actually use different
913 // opcode bits for the different sizes.
914 def REVWr : OneWRegData<0b010, "rev", bswap>;
915 def REVXr : OneXRegData<0b011, "rev", bswap>;
916 def REV32Xr : OneXRegData<0b010, "rev32",
917 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
919 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
921 // The bswap commutes with the rotr so we want a pattern for both possible
923 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
924 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
926 //===----------------------------------------------------------------------===//
927 // Bitfield immediate extraction instruction.
928 //===----------------------------------------------------------------------===//
929 let hasSideEffects = 0 in
930 defm EXTR : ExtractImm<"extr">;
931 def : InstAlias<"ror $dst, $src, $shift",
932 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
933 def : InstAlias<"ror $dst, $src, $shift",
934 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
936 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
937 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
938 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
939 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
941 //===----------------------------------------------------------------------===//
942 // Other bitfield immediate instructions.
943 //===----------------------------------------------------------------------===//
944 let hasSideEffects = 0 in {
945 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
946 defm SBFM : BitfieldImm<0b00, "sbfm">;
947 defm UBFM : BitfieldImm<0b10, "ubfm">;
950 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
951 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
952 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
955 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
956 uint64_t enc = 31 - N->getZExtValue();
957 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
960 // min(7, 31 - shift_amt)
961 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
962 uint64_t enc = 31 - N->getZExtValue();
963 enc = enc > 7 ? 7 : enc;
964 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
967 // min(15, 31 - shift_amt)
968 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
969 uint64_t enc = 31 - N->getZExtValue();
970 enc = enc > 15 ? 15 : enc;
971 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
974 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
975 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
976 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
979 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
980 uint64_t enc = 63 - N->getZExtValue();
981 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
984 // min(7, 63 - shift_amt)
985 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
986 uint64_t enc = 63 - N->getZExtValue();
987 enc = enc > 7 ? 7 : enc;
988 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
991 // min(15, 63 - shift_amt)
992 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
993 uint64_t enc = 63 - N->getZExtValue();
994 enc = enc > 15 ? 15 : enc;
995 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
998 // min(31, 63 - shift_amt)
999 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
1000 uint64_t enc = 63 - N->getZExtValue();
1001 enc = enc > 31 ? 31 : enc;
1002 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1005 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
1006 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
1007 (i64 (i32shift_b imm0_31:$imm)))>;
1008 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
1009 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
1010 (i64 (i64shift_b imm0_63:$imm)))>;
1012 let AddedComplexity = 10 in {
1013 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
1014 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1015 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
1016 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1019 def : InstAlias<"asr $dst, $src, $shift",
1020 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1021 def : InstAlias<"asr $dst, $src, $shift",
1022 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1023 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1024 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1025 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1026 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1027 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1029 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
1030 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1031 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
1032 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1034 def : InstAlias<"lsr $dst, $src, $shift",
1035 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1036 def : InstAlias<"lsr $dst, $src, $shift",
1037 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1038 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1039 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1040 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1041 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1042 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1044 //===----------------------------------------------------------------------===//
1045 // Conditional comparison instructions.
1046 //===----------------------------------------------------------------------===//
1047 defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;
1048 defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;
1050 //===----------------------------------------------------------------------===//
1051 // Conditional select instructions.
1052 //===----------------------------------------------------------------------===//
1053 defm CSEL : CondSelect<0, 0b00, "csel">;
1055 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
1056 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1057 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1058 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1060 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1061 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1062 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1063 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1064 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1065 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1066 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1067 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1068 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1069 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1070 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1071 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1073 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
1074 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
1075 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
1076 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
1077 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
1078 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
1079 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
1080 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
1082 // The inverse of the condition code from the alias instruction is what is used
1083 // in the aliased instruction. The parser all ready inverts the condition code
1084 // for these aliases.
1085 def : InstAlias<"cset $dst, $cc",
1086 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1087 def : InstAlias<"cset $dst, $cc",
1088 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1090 def : InstAlias<"csetm $dst, $cc",
1091 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1092 def : InstAlias<"csetm $dst, $cc",
1093 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1095 def : InstAlias<"cinc $dst, $src, $cc",
1096 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1097 def : InstAlias<"cinc $dst, $src, $cc",
1098 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1100 def : InstAlias<"cinv $dst, $src, $cc",
1101 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1102 def : InstAlias<"cinv $dst, $src, $cc",
1103 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1105 def : InstAlias<"cneg $dst, $src, $cc",
1106 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1107 def : InstAlias<"cneg $dst, $src, $cc",
1108 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1110 //===----------------------------------------------------------------------===//
1111 // PC-relative instructions.
1112 //===----------------------------------------------------------------------===//
1113 let isReMaterializable = 1 in {
1114 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1115 def ADR : ADRI<0, "adr", adrlabel, []>;
1116 } // hasSideEffects = 0
1118 def ADRP : ADRI<1, "adrp", adrplabel,
1119 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1120 } // isReMaterializable = 1
1122 // page address of a constant pool entry, block address
1123 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1124 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1126 //===----------------------------------------------------------------------===//
1127 // Unconditional branch (register) instructions.
1128 //===----------------------------------------------------------------------===//
1130 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1131 def RET : BranchReg<0b0010, "ret", []>;
1132 def DRPS : SpecialReturn<0b0101, "drps">;
1133 def ERET : SpecialReturn<0b0100, "eret">;
1134 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1136 // Default to the LR register.
1137 def : InstAlias<"ret", (RET LR)>;
1139 let isCall = 1, Defs = [LR], Uses = [SP] in {
1140 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1143 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1144 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1145 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1147 // Create a separate pseudo-instruction for codegen to use so that we don't
1148 // flag lr as used in every function. It'll be restored before the RET by the
1149 // epilogue if it's legitimately used.
1150 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1151 let isTerminator = 1;
1156 // This is a directive-like pseudo-instruction. The purpose is to insert an
1157 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1158 // (which in the usual case is a BLR).
1159 let hasSideEffects = 1 in
1160 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1161 let AsmString = ".tlsdesccall $sym";
1164 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1165 // FIXME: can "hasSideEffects be dropped?
1166 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1167 isCodeGenOnly = 1 in
1169 : Pseudo<(outs), (ins i64imm:$sym),
1170 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
1171 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1172 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1174 //===----------------------------------------------------------------------===//
1175 // Conditional branch (immediate) instruction.
1176 //===----------------------------------------------------------------------===//
1177 def Bcc : BranchCond;
1179 //===----------------------------------------------------------------------===//
1180 // Compare-and-branch instructions.
1181 //===----------------------------------------------------------------------===//
1182 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1183 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1185 //===----------------------------------------------------------------------===//
1186 // Test-bit-and-branch instructions.
1187 //===----------------------------------------------------------------------===//
1188 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1189 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1191 //===----------------------------------------------------------------------===//
1192 // Unconditional branch (immediate) instructions.
1193 //===----------------------------------------------------------------------===//
1194 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1195 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1196 } // isBranch, isTerminator, isBarrier
1198 let isCall = 1, Defs = [LR], Uses = [SP] in {
1199 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1201 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1203 //===----------------------------------------------------------------------===//
1204 // Exception generation instructions.
1205 //===----------------------------------------------------------------------===//
1206 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1207 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1208 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1209 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1210 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1211 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1212 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1213 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1215 // DCPSn defaults to an immediate operand of zero if unspecified.
1216 def : InstAlias<"dcps1", (DCPS1 0)>;
1217 def : InstAlias<"dcps2", (DCPS2 0)>;
1218 def : InstAlias<"dcps3", (DCPS3 0)>;
1220 //===----------------------------------------------------------------------===//
1221 // Load instructions.
1222 //===----------------------------------------------------------------------===//
1224 // Pair (indexed, offset)
1225 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1226 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1227 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1228 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1229 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1231 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1233 // Pair (pre-indexed)
1234 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1235 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1236 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1237 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1238 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1240 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1242 // Pair (post-indexed)
1243 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1244 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1245 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1246 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1247 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1249 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1252 // Pair (no allocate)
1253 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1254 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1255 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1256 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1257 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1260 // (register offset)
1264 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1265 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1266 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1267 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1270 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1271 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1272 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1273 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1274 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1276 // Load sign-extended half-word
1277 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1278 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1280 // Load sign-extended byte
1281 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1282 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1284 // Load sign-extended word
1285 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1288 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1290 // For regular load, we do not have any alignment requirement.
1291 // Thus, it is safe to directly map the vector loads with interesting
1292 // addressing modes.
1293 // FIXME: We could do the same for bitconvert to floating point vectors.
1294 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1295 ValueType ScalTy, ValueType VecTy,
1296 Instruction LOADW, Instruction LOADX,
1298 def : Pat<(VecTy (scalar_to_vector (ScalTy
1299 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1300 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1301 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1304 def : Pat<(VecTy (scalar_to_vector (ScalTy
1305 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1306 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1307 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1311 let AddedComplexity = 10 in {
1312 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1313 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1315 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1316 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1318 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1319 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1321 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1322 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1324 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1325 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1327 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1329 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1332 def : Pat <(v1i64 (scalar_to_vector (i64
1333 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1334 ro_Wextend64:$extend))))),
1335 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1337 def : Pat <(v1i64 (scalar_to_vector (i64
1338 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1339 ro_Xextend64:$extend))))),
1340 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1343 // Match all load 64 bits width whose type is compatible with FPR64
1344 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1345 Instruction LOADW, Instruction LOADX> {
1347 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1348 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1350 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1351 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1354 let AddedComplexity = 10 in {
1355 let Predicates = [IsLE] in {
1356 // We must do vector loads with LD1 in big-endian.
1357 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1358 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1359 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1360 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1361 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1364 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1365 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1367 // Match all load 128 bits width whose type is compatible with FPR128
1368 let Predicates = [IsLE] in {
1369 // We must do vector loads with LD1 in big-endian.
1370 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1371 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1372 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1373 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1374 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1375 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1376 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1378 } // AddedComplexity = 10
1381 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1382 Instruction INSTW, Instruction INSTX> {
1383 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1384 (SUBREG_TO_REG (i64 0),
1385 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1388 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1389 (SUBREG_TO_REG (i64 0),
1390 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1394 let AddedComplexity = 10 in {
1395 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1396 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1397 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1399 // zextloadi1 -> zextloadi8
1400 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1402 // extload -> zextload
1403 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1404 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1405 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1407 // extloadi1 -> zextloadi8
1408 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1413 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1414 Instruction INSTW, Instruction INSTX> {
1415 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1416 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1418 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1419 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1423 let AddedComplexity = 10 in {
1424 // extload -> zextload
1425 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1426 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1427 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1429 // zextloadi1 -> zextloadi8
1430 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1434 // (unsigned immediate)
1436 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1438 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1439 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1441 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1442 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1444 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1445 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1446 [(set (f16 FPR16:$Rt),
1447 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1448 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1449 [(set (f32 FPR32:$Rt),
1450 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1451 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1452 [(set (f64 FPR64:$Rt),
1453 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1454 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1455 [(set (f128 FPR128:$Rt),
1456 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1458 // For regular load, we do not have any alignment requirement.
1459 // Thus, it is safe to directly map the vector loads with interesting
1460 // addressing modes.
1461 // FIXME: We could do the same for bitconvert to floating point vectors.
1462 def : Pat <(v8i8 (scalar_to_vector (i32
1463 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1464 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1465 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1466 def : Pat <(v16i8 (scalar_to_vector (i32
1467 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1468 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1469 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1470 def : Pat <(v4i16 (scalar_to_vector (i32
1471 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1472 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1473 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1474 def : Pat <(v8i16 (scalar_to_vector (i32
1475 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1476 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1477 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1478 def : Pat <(v2i32 (scalar_to_vector (i32
1479 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1480 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1481 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1482 def : Pat <(v4i32 (scalar_to_vector (i32
1483 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1484 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1485 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1486 def : Pat <(v1i64 (scalar_to_vector (i64
1487 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1488 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1489 def : Pat <(v2i64 (scalar_to_vector (i64
1490 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1491 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1492 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1494 // Match all load 64 bits width whose type is compatible with FPR64
1495 let Predicates = [IsLE] in {
1496 // We must use LD1 to perform vector loads in big-endian.
1497 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1498 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1499 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1500 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1501 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1502 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1503 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1504 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1505 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1506 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1508 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1509 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1510 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1511 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1513 // Match all load 128 bits width whose type is compatible with FPR128
1514 let Predicates = [IsLE] in {
1515 // We must use LD1 to perform vector loads in big-endian.
1516 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1517 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1518 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1519 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1520 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1521 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1522 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1523 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1524 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1525 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1526 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1527 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1528 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1529 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1531 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1532 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1534 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1536 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1537 uimm12s2:$offset)))]>;
1538 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1540 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1541 uimm12s1:$offset)))]>;
1543 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1544 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1545 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1546 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1548 // zextloadi1 -> zextloadi8
1549 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1550 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1551 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1552 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1554 // extload -> zextload
1555 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1556 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1557 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1558 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1559 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1560 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1561 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1562 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1563 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1564 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1565 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1566 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1567 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1568 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1570 // load sign-extended half-word
1571 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1573 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1574 uimm12s2:$offset)))]>;
1575 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1577 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1578 uimm12s2:$offset)))]>;
1580 // load sign-extended byte
1581 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1583 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1584 uimm12s1:$offset)))]>;
1585 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1587 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1588 uimm12s1:$offset)))]>;
1590 // load sign-extended word
1591 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1593 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1594 uimm12s4:$offset)))]>;
1596 // load zero-extended word
1597 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1598 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1601 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1602 [(AArch64Prefetch imm:$Rt,
1603 (am_indexed64 GPR64sp:$Rn,
1604 uimm12s8:$offset))]>;
1606 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1610 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1611 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1612 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1613 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1614 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1616 // load sign-extended word
1617 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1620 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1621 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1624 // (unscaled immediate)
1625 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1627 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1628 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1630 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1631 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1633 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1634 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1636 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1637 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1638 [(set (f32 FPR32:$Rt),
1639 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1640 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1641 [(set (f64 FPR64:$Rt),
1642 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1643 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1644 [(set (f128 FPR128:$Rt),
1645 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1648 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1650 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1652 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1654 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1656 // Match all load 64 bits width whose type is compatible with FPR64
1657 let Predicates = [IsLE] in {
1658 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1659 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1660 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1661 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1662 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1663 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1664 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1665 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1666 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1667 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1669 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1670 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1671 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1672 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1674 // Match all load 128 bits width whose type is compatible with FPR128
1675 let Predicates = [IsLE] in {
1676 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1677 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1678 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1679 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1680 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1681 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1682 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1683 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1684 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1685 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1686 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1687 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1688 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1689 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1693 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1694 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1695 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1696 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1697 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1698 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1699 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1700 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1701 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1702 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1703 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1704 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1705 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1706 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1708 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1709 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1710 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1711 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1712 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1713 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1714 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1715 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1716 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1717 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1718 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1719 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1720 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1721 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1725 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1727 // Define new assembler match classes as we want to only match these when
1728 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1729 // associate a DiagnosticType either, as we want the diagnostic for the
1730 // canonical form (the scaled operand) to take precedence.
1731 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1732 let Name = "SImm9OffsetFB" # Width;
1733 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1734 let RenderMethod = "addImmOperands";
1737 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1738 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1739 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1740 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1741 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1743 def simm9_offset_fb8 : Operand<i64> {
1744 let ParserMatchClass = SImm9OffsetFB8Operand;
1746 def simm9_offset_fb16 : Operand<i64> {
1747 let ParserMatchClass = SImm9OffsetFB16Operand;
1749 def simm9_offset_fb32 : Operand<i64> {
1750 let ParserMatchClass = SImm9OffsetFB32Operand;
1752 def simm9_offset_fb64 : Operand<i64> {
1753 let ParserMatchClass = SImm9OffsetFB64Operand;
1755 def simm9_offset_fb128 : Operand<i64> {
1756 let ParserMatchClass = SImm9OffsetFB128Operand;
1759 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1760 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1761 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1762 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1763 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1764 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1765 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1766 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1767 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1768 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1769 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1770 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1771 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1772 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1775 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1776 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1777 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1778 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1780 // load sign-extended half-word
1782 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1784 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1786 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1788 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1790 // load sign-extended byte
1792 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1794 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1796 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1798 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1800 // load sign-extended word
1802 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1804 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1806 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1807 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1808 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1809 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1810 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1811 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1812 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1813 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1814 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1815 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1816 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1817 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1818 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1819 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1820 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1823 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1824 [(AArch64Prefetch imm:$Rt,
1825 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1828 // (unscaled immediate, unprivileged)
1829 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1830 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1832 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1833 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1835 // load sign-extended half-word
1836 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1837 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1839 // load sign-extended byte
1840 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1841 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1843 // load sign-extended word
1844 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1847 // (immediate pre-indexed)
1848 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1849 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1850 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1851 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1852 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1853 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1854 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1856 // load sign-extended half-word
1857 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1858 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1860 // load sign-extended byte
1861 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1862 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1864 // load zero-extended byte
1865 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1866 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1868 // load sign-extended word
1869 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1872 // (immediate post-indexed)
1873 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1874 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1875 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1876 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1877 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1878 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1879 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1881 // load sign-extended half-word
1882 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1883 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1885 // load sign-extended byte
1886 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1887 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1889 // load zero-extended byte
1890 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1891 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1893 // load sign-extended word
1894 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1896 //===----------------------------------------------------------------------===//
1897 // Store instructions.
1898 //===----------------------------------------------------------------------===//
1900 // Pair (indexed, offset)
1901 // FIXME: Use dedicated range-checked addressing mode operand here.
1902 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1903 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1904 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1905 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1906 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1908 // Pair (pre-indexed)
1909 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1910 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1911 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1912 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1913 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1915 // Pair (pre-indexed)
1916 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1917 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1918 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1919 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1920 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1922 // Pair (no allocate)
1923 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1924 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1925 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1926 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1927 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1930 // (Register offset)
1933 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1934 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1935 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1936 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1940 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1941 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1942 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1943 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1944 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1946 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1947 Instruction STRW, Instruction STRX> {
1949 def : Pat<(storeop GPR64:$Rt,
1950 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1951 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1952 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1954 def : Pat<(storeop GPR64:$Rt,
1955 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1956 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1957 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1960 let AddedComplexity = 10 in {
1962 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1963 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1964 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1967 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1968 Instruction STRW, Instruction STRX> {
1969 def : Pat<(store (VecTy FPR:$Rt),
1970 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1971 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1973 def : Pat<(store (VecTy FPR:$Rt),
1974 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1975 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1978 let AddedComplexity = 10 in {
1979 // Match all store 64 bits width whose type is compatible with FPR64
1980 let Predicates = [IsLE] in {
1981 // We must use ST1 to store vectors in big-endian.
1982 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1983 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1984 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1985 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1986 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1989 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1990 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1992 // Match all store 128 bits width whose type is compatible with FPR128
1993 let Predicates = [IsLE] in {
1994 // We must use ST1 to store vectors in big-endian.
1995 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1996 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1997 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1998 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1999 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
2000 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
2001 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2003 } // AddedComplexity = 10
2005 // Match stores from lane 0 to the appropriate subreg's store.
2006 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
2007 ValueType VecTy, ValueType STy,
2008 SubRegIndex SubRegIdx,
2009 Instruction STRW, Instruction STRX> {
2011 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2012 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2013 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2014 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2016 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2017 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2018 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2019 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2022 let AddedComplexity = 19 in {
2023 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2024 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
2025 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
2026 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
2027 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
2028 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
2029 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2033 // (unsigned immediate)
2034 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2036 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2037 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2039 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2040 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2042 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
2043 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2044 [(store (f16 FPR16:$Rt),
2045 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
2046 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2047 [(store (f32 FPR32:$Rt),
2048 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2049 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2050 [(store (f64 FPR64:$Rt),
2051 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2052 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2054 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2055 [(truncstorei16 GPR32:$Rt,
2056 (am_indexed16 GPR64sp:$Rn,
2057 uimm12s2:$offset))]>;
2058 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2059 [(truncstorei8 GPR32:$Rt,
2060 (am_indexed8 GPR64sp:$Rn,
2061 uimm12s1:$offset))]>;
2063 // Match all store 64 bits width whose type is compatible with FPR64
2064 let AddedComplexity = 10 in {
2065 let Predicates = [IsLE] in {
2066 // We must use ST1 to store vectors in big-endian.
2067 def : Pat<(store (v2f32 FPR64:$Rt),
2068 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2069 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2070 def : Pat<(store (v8i8 FPR64:$Rt),
2071 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2072 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2073 def : Pat<(store (v4i16 FPR64:$Rt),
2074 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2075 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2076 def : Pat<(store (v2i32 FPR64:$Rt),
2077 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2078 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2079 def : Pat<(store (v4f16 FPR64:$Rt),
2080 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2081 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2083 def : Pat<(store (v1f64 FPR64:$Rt),
2084 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2085 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2086 def : Pat<(store (v1i64 FPR64:$Rt),
2087 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2088 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2090 // Match all store 128 bits width whose type is compatible with FPR128
2091 let Predicates = [IsLE] in {
2092 // We must use ST1 to store vectors in big-endian.
2093 def : Pat<(store (v4f32 FPR128:$Rt),
2094 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2095 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2096 def : Pat<(store (v2f64 FPR128:$Rt),
2097 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2098 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2099 def : Pat<(store (v16i8 FPR128:$Rt),
2100 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2101 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2102 def : Pat<(store (v8i16 FPR128:$Rt),
2103 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2104 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2105 def : Pat<(store (v4i32 FPR128:$Rt),
2106 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2107 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2108 def : Pat<(store (v2i64 FPR128:$Rt),
2109 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2110 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2111 def : Pat<(store (v8f16 FPR128:$Rt),
2112 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2113 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2115 def : Pat<(store (f128 FPR128:$Rt),
2116 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2117 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2120 def : Pat<(truncstorei32 GPR64:$Rt,
2121 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2122 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2123 def : Pat<(truncstorei16 GPR64:$Rt,
2124 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2125 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2126 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2127 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2129 } // AddedComplexity = 10
2132 // (unscaled immediate)
2133 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2135 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2136 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2138 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2139 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2141 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2142 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2143 [(store (f16 FPR16:$Rt),
2144 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2145 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2146 [(store (f32 FPR32:$Rt),
2147 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2148 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2149 [(store (f64 FPR64:$Rt),
2150 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2151 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2152 [(store (f128 FPR128:$Rt),
2153 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2154 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2155 [(truncstorei16 GPR32:$Rt,
2156 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2157 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2158 [(truncstorei8 GPR32:$Rt,
2159 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2161 // Match all store 64 bits width whose type is compatible with FPR64
2162 let Predicates = [IsLE] in {
2163 // We must use ST1 to store vectors in big-endian.
2164 def : Pat<(store (v2f32 FPR64:$Rt),
2165 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2166 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2167 def : Pat<(store (v8i8 FPR64:$Rt),
2168 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2169 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2170 def : Pat<(store (v4i16 FPR64:$Rt),
2171 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2172 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2173 def : Pat<(store (v2i32 FPR64:$Rt),
2174 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2175 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2176 def : Pat<(store (v4f16 FPR64:$Rt),
2177 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2178 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2180 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2181 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2182 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2183 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2185 // Match all store 128 bits width whose type is compatible with FPR128
2186 let Predicates = [IsLE] in {
2187 // We must use ST1 to store vectors in big-endian.
2188 def : Pat<(store (v4f32 FPR128:$Rt),
2189 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2190 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2191 def : Pat<(store (v2f64 FPR128:$Rt),
2192 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2193 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2194 def : Pat<(store (v16i8 FPR128:$Rt),
2195 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2196 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2197 def : Pat<(store (v8i16 FPR128:$Rt),
2198 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2199 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2200 def : Pat<(store (v4i32 FPR128:$Rt),
2201 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2202 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2203 def : Pat<(store (v2i64 FPR128:$Rt),
2204 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2205 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2206 def : Pat<(store (v2f64 FPR128:$Rt),
2207 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2208 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2209 def : Pat<(store (v8f16 FPR128:$Rt),
2210 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2211 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2214 // unscaled i64 truncating stores
2215 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2216 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2217 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2218 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2219 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2220 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2223 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2224 def : InstAlias<"str $Rt, [$Rn, $offset]",
2225 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2226 def : InstAlias<"str $Rt, [$Rn, $offset]",
2227 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2228 def : InstAlias<"str $Rt, [$Rn, $offset]",
2229 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2230 def : InstAlias<"str $Rt, [$Rn, $offset]",
2231 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2232 def : InstAlias<"str $Rt, [$Rn, $offset]",
2233 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2234 def : InstAlias<"str $Rt, [$Rn, $offset]",
2235 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2236 def : InstAlias<"str $Rt, [$Rn, $offset]",
2237 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2239 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2240 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2241 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2242 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2245 // (unscaled immediate, unprivileged)
2246 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2247 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2249 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2250 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2253 // (immediate pre-indexed)
2254 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2255 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2256 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2257 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2258 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2259 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2260 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2262 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2263 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2266 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2267 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2269 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2270 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2272 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2273 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2276 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2277 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2278 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2279 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2280 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2281 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2282 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2283 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2284 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2285 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2286 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2287 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2288 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2289 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2291 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2292 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2293 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2294 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2295 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2296 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2297 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2298 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2299 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2300 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2301 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2302 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2303 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2304 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2307 // (immediate post-indexed)
2308 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2309 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2310 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2311 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2312 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2313 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2314 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2316 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2317 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2320 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2321 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2323 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2324 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2326 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2327 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2330 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2331 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2332 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2333 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2334 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2335 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2336 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2337 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2338 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2339 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2340 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2341 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2342 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2343 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2345 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2346 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2347 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2348 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2349 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2350 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2351 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2352 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2353 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2354 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2355 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2356 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2357 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2358 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2360 //===----------------------------------------------------------------------===//
2361 // Load/store exclusive instructions.
2362 //===----------------------------------------------------------------------===//
2364 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2365 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2366 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2367 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2369 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2370 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2371 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2372 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2374 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2375 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2376 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2377 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2379 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2380 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2381 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2382 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2384 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2385 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2386 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2387 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2389 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2390 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2391 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2392 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2394 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2395 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2397 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2398 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2400 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2401 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2403 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2404 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2406 let Predicates = [HasV8_1a] in {
2407 // v8.1a "Limited Order Region" extension load-acquire instructions
2408 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2409 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
2410 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2411 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2413 // v8.1a "Limited Order Region" extension store-release instructions
2414 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2415 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
2416 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2417 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2420 //===----------------------------------------------------------------------===//
2421 // Scaled floating point to integer conversion instructions.
2422 //===----------------------------------------------------------------------===//
2424 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2425 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2426 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2427 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2428 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2429 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2430 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2431 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2432 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2433 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2434 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2435 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2436 let isCodeGenOnly = 1 in {
2437 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2438 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2439 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2440 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2443 //===----------------------------------------------------------------------===//
2444 // Scaled integer to floating point conversion instructions.
2445 //===----------------------------------------------------------------------===//
2447 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2448 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2450 //===----------------------------------------------------------------------===//
2451 // Unscaled integer to floating point conversion instruction.
2452 //===----------------------------------------------------------------------===//
2454 defm FMOV : UnscaledConversion<"fmov">;
2456 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2457 let isReMaterializable = 1, isCodeGenOnly = 1 in {
2458 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2459 PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
2461 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2462 PseudoInstExpansion<(FMOVXDr FPR64:$Rd, XZR)>,
2466 //===----------------------------------------------------------------------===//
2467 // Floating point conversion instruction.
2468 //===----------------------------------------------------------------------===//
2470 defm FCVT : FPConversion<"fcvt">;
2472 //===----------------------------------------------------------------------===//
2473 // Floating point single operand instructions.
2474 //===----------------------------------------------------------------------===//
2476 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2477 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2478 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2479 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2480 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2481 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2482 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2483 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2485 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2486 (FRINTNDr FPR64:$Rn)>;
2488 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2489 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2490 // <rdar://problem/13715968>
2491 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2492 let hasSideEffects = 1 in {
2493 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2496 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2498 let SchedRW = [WriteFDiv] in {
2499 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2502 //===----------------------------------------------------------------------===//
2503 // Floating point two operand instructions.
2504 //===----------------------------------------------------------------------===//
2506 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2507 let SchedRW = [WriteFDiv] in {
2508 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2510 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>;
2511 defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;
2512 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>;
2513 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
2514 let SchedRW = [WriteFMul] in {
2515 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2516 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2518 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2520 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2521 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2522 def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2523 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2524 def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2525 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2526 def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2527 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2529 //===----------------------------------------------------------------------===//
2530 // Floating point three operand instructions.
2531 //===----------------------------------------------------------------------===//
2533 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2534 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2535 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2536 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2537 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2538 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2539 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2541 // The following def pats catch the case where the LHS of an FMA is negated.
2542 // The TriOpFrag above catches the case where the middle operand is negated.
2544 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2545 // the NEON variant.
2546 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2547 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2549 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2550 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2552 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2554 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2555 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2557 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2558 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2560 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2561 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2563 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2564 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2566 //===----------------------------------------------------------------------===//
2567 // Floating point comparison instructions.
2568 //===----------------------------------------------------------------------===//
2570 defm FCMPE : FPComparison<1, "fcmpe">;
2571 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2573 //===----------------------------------------------------------------------===//
2574 // Floating point conditional comparison instructions.
2575 //===----------------------------------------------------------------------===//
2577 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2578 defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;
2580 //===----------------------------------------------------------------------===//
2581 // Floating point conditional select instruction.
2582 //===----------------------------------------------------------------------===//
2584 defm FCSEL : FPCondSelect<"fcsel">;
2586 // CSEL instructions providing f128 types need to be handled by a
2587 // pseudo-instruction since the eventual code will need to introduce basic
2588 // blocks and control flow.
2589 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2590 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2591 [(set (f128 FPR128:$Rd),
2592 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2593 (i32 imm:$cond), NZCV))]> {
2595 let usesCustomInserter = 1;
2599 //===----------------------------------------------------------------------===//
2600 // Floating point immediate move.
2601 //===----------------------------------------------------------------------===//
2603 let isReMaterializable = 1 in {
2604 defm FMOV : FPMoveImmediate<"fmov">;
2607 //===----------------------------------------------------------------------===//
2608 // Advanced SIMD two vector instructions.
2609 //===----------------------------------------------------------------------===//
2611 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2612 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2613 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2614 (ABSv8i8 V64:$src)>;
2615 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2616 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2617 (ABSv4i16 V64:$src)>;
2618 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2619 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2620 (ABSv2i32 V64:$src)>;
2621 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2622 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2623 (ABSv16i8 V128:$src)>;
2624 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2625 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2626 (ABSv8i16 V128:$src)>;
2627 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2628 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2629 (ABSv4i32 V128:$src)>;
2630 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2631 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2632 (ABSv2i64 V128:$src)>;
2634 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2635 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2636 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2637 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2638 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2639 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2640 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2641 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2642 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2644 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2645 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2646 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2647 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2648 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2649 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2650 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2651 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2652 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2653 (FCVTLv4i16 V64:$Rn)>;
2654 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2656 (FCVTLv8i16 V128:$Rn)>;
2657 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2658 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2660 (FCVTLv4i32 V128:$Rn)>;
2662 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2663 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2665 (FCVTLv8i16 V128:$Rn)>;
2667 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2668 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2669 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2670 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2671 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2672 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2673 (FCVTNv4i16 V128:$Rn)>;
2674 def : Pat<(concat_vectors V64:$Rd,
2675 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2676 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2677 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2678 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2679 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2680 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2681 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2682 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2683 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2684 int_aarch64_neon_fcvtxn>;
2685 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2686 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2687 let isCodeGenOnly = 1 in {
2688 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2689 int_aarch64_neon_fcvtzs>;
2690 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2691 int_aarch64_neon_fcvtzu>;
2693 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2694 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2695 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2696 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2697 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2698 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2699 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2700 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2701 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2702 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2703 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2704 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2705 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2706 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2707 // Aliases for MVN -> NOT.
2708 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2709 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2710 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2711 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2713 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2714 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2715 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2716 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2717 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2718 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2719 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2721 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2722 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2723 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2724 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2725 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2726 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2727 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2728 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2730 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2731 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2732 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2733 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2734 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2736 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2737 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2738 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2739 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2740 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2741 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2742 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2743 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2744 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2745 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2746 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2747 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2748 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2749 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2750 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2751 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2752 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2753 int_aarch64_neon_uaddlp>;
2754 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2755 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2756 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2757 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2758 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2759 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2761 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2762 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2763 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2764 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2765 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2766 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2768 // Patterns for vector long shift (by element width). These need to match all
2769 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2771 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2772 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2773 (SHLLv8i8 V64:$Rn)>;
2774 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2775 (SHLLv16i8 V128:$Rn)>;
2776 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2777 (SHLLv4i16 V64:$Rn)>;
2778 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2779 (SHLLv8i16 V128:$Rn)>;
2780 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2781 (SHLLv2i32 V64:$Rn)>;
2782 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2783 (SHLLv4i32 V128:$Rn)>;
2786 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2787 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2788 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2790 //===----------------------------------------------------------------------===//
2791 // Advanced SIMD three vector instructions.
2792 //===----------------------------------------------------------------------===//
2794 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2795 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2796 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2797 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2798 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2799 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2800 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2801 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2802 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2803 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2804 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2805 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2806 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2807 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2808 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2809 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2810 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2811 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2812 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", fmaxnum>;
2813 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2814 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", fmaxnan>;
2815 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2816 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", fminnum>;
2817 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2818 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", fminnan>;
2820 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2821 // instruction expects the addend first, while the fma intrinsic puts it last.
2822 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2823 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2824 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2825 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2827 // The following def pats catch the case where the LHS of an FMA is negated.
2828 // The TriOpFrag above catches the case where the middle operand is negated.
2829 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2830 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2832 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2833 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2835 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2836 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2838 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2839 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2840 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2841 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2842 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2843 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2844 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2845 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2846 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2847 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2848 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2849 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2850 TriOpFrag<(add node:$LHS, (sabsdiff node:$MHS, node:$RHS))> >;
2851 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", sabsdiff>;
2852 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2853 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2854 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2855 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>;
2856 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2857 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>;
2858 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2859 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2860 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2861 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2862 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2863 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2864 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2865 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2866 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2867 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2868 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2869 TriOpFrag<(add node:$LHS, (uabsdiff node:$MHS, node:$RHS))> >;
2870 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", uabsdiff>;
2871 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2872 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2873 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2874 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>;
2875 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2876 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>;
2877 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2878 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2879 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2880 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2881 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2882 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2883 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2884 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
2885 int_aarch64_neon_sqadd>;
2886 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
2887 int_aarch64_neon_sqsub>;
2889 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2890 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2891 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2892 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2893 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2894 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2895 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2896 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2897 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2898 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2899 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2902 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2903 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2904 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2905 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2906 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2907 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2908 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2909 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2911 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2912 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2913 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2914 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2915 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2916 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2917 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2918 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2920 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2921 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2922 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2923 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2924 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2925 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2926 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2927 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2929 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2930 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2931 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2932 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2933 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2934 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2935 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2936 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2938 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2939 "|cmls.8b\t$dst, $src1, $src2}",
2940 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2941 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2942 "|cmls.16b\t$dst, $src1, $src2}",
2943 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2944 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2945 "|cmls.4h\t$dst, $src1, $src2}",
2946 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2947 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2948 "|cmls.8h\t$dst, $src1, $src2}",
2949 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2950 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2951 "|cmls.2s\t$dst, $src1, $src2}",
2952 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2953 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2954 "|cmls.4s\t$dst, $src1, $src2}",
2955 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2956 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2957 "|cmls.2d\t$dst, $src1, $src2}",
2958 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2960 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2961 "|cmlo.8b\t$dst, $src1, $src2}",
2962 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2963 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2964 "|cmlo.16b\t$dst, $src1, $src2}",
2965 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2966 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2967 "|cmlo.4h\t$dst, $src1, $src2}",
2968 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2969 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2970 "|cmlo.8h\t$dst, $src1, $src2}",
2971 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2972 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2973 "|cmlo.2s\t$dst, $src1, $src2}",
2974 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2975 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2976 "|cmlo.4s\t$dst, $src1, $src2}",
2977 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2978 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2979 "|cmlo.2d\t$dst, $src1, $src2}",
2980 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2982 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2983 "|cmle.8b\t$dst, $src1, $src2}",
2984 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2985 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2986 "|cmle.16b\t$dst, $src1, $src2}",
2987 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2988 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2989 "|cmle.4h\t$dst, $src1, $src2}",
2990 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2991 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2992 "|cmle.8h\t$dst, $src1, $src2}",
2993 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2994 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2995 "|cmle.2s\t$dst, $src1, $src2}",
2996 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2997 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2998 "|cmle.4s\t$dst, $src1, $src2}",
2999 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3000 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
3001 "|cmle.2d\t$dst, $src1, $src2}",
3002 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3004 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
3005 "|cmlt.8b\t$dst, $src1, $src2}",
3006 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3007 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
3008 "|cmlt.16b\t$dst, $src1, $src2}",
3009 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3010 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
3011 "|cmlt.4h\t$dst, $src1, $src2}",
3012 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3013 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
3014 "|cmlt.8h\t$dst, $src1, $src2}",
3015 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3016 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
3017 "|cmlt.2s\t$dst, $src1, $src2}",
3018 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3019 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
3020 "|cmlt.4s\t$dst, $src1, $src2}",
3021 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3022 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
3023 "|cmlt.2d\t$dst, $src1, $src2}",
3024 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3026 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3027 "|fcmle.2s\t$dst, $src1, $src2}",
3028 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3029 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3030 "|fcmle.4s\t$dst, $src1, $src2}",
3031 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3032 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
3033 "|fcmle.2d\t$dst, $src1, $src2}",
3034 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3036 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
3037 "|fcmlt.2s\t$dst, $src1, $src2}",
3038 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3039 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
3040 "|fcmlt.4s\t$dst, $src1, $src2}",
3041 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3042 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
3043 "|fcmlt.2d\t$dst, $src1, $src2}",
3044 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3046 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
3047 "|facle.2s\t$dst, $src1, $src2}",
3048 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3049 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
3050 "|facle.4s\t$dst, $src1, $src2}",
3051 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3052 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
3053 "|facle.2d\t$dst, $src1, $src2}",
3054 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3056 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
3057 "|faclt.2s\t$dst, $src1, $src2}",
3058 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3059 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
3060 "|faclt.4s\t$dst, $src1, $src2}",
3061 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3062 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
3063 "|faclt.2d\t$dst, $src1, $src2}",
3064 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3066 //===----------------------------------------------------------------------===//
3067 // Advanced SIMD three scalar instructions.
3068 //===----------------------------------------------------------------------===//
3070 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
3071 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
3072 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
3073 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
3074 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
3075 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
3076 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
3077 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
3078 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3079 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
3080 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
3081 int_aarch64_neon_facge>;
3082 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
3083 int_aarch64_neon_facgt>;
3084 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
3085 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
3086 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
3087 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
3088 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
3089 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
3090 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
3091 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
3092 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
3093 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
3094 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
3095 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
3096 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
3097 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
3098 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
3099 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
3100 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
3101 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
3102 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
3103 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3104 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3105 let Predicates = [HasV8_1a] in {
3106 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3107 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3108 def : Pat<(i32 (int_aarch64_neon_sqadd
3110 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3111 (i32 FPR32:$Rm))))),
3112 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3113 def : Pat<(i32 (int_aarch64_neon_sqsub
3115 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3116 (i32 FPR32:$Rm))))),
3117 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3120 def : InstAlias<"cmls $dst, $src1, $src2",
3121 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3122 def : InstAlias<"cmle $dst, $src1, $src2",
3123 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3124 def : InstAlias<"cmlo $dst, $src1, $src2",
3125 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3126 def : InstAlias<"cmlt $dst, $src1, $src2",
3127 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3128 def : InstAlias<"fcmle $dst, $src1, $src2",
3129 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3130 def : InstAlias<"fcmle $dst, $src1, $src2",
3131 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3132 def : InstAlias<"fcmlt $dst, $src1, $src2",
3133 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3134 def : InstAlias<"fcmlt $dst, $src1, $src2",
3135 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3136 def : InstAlias<"facle $dst, $src1, $src2",
3137 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3138 def : InstAlias<"facle $dst, $src1, $src2",
3139 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3140 def : InstAlias<"faclt $dst, $src1, $src2",
3141 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3142 def : InstAlias<"faclt $dst, $src1, $src2",
3143 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3145 //===----------------------------------------------------------------------===//
3146 // Advanced SIMD three scalar instructions (mixed operands).
3147 //===----------------------------------------------------------------------===//
3148 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3149 int_aarch64_neon_sqdmulls_scalar>;
3150 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3151 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3153 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3154 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3155 (i32 FPR32:$Rm))))),
3156 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3157 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3158 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3159 (i32 FPR32:$Rm))))),
3160 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3162 //===----------------------------------------------------------------------===//
3163 // Advanced SIMD two scalar instructions.
3164 //===----------------------------------------------------------------------===//
3166 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3167 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3168 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3169 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3170 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3171 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3172 defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3173 defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3174 defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3175 defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3176 defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3177 defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">;
3178 defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">;
3179 defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">;
3180 defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">;
3181 defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">;
3182 defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">;
3183 defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">;
3184 defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">;
3185 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3186 defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">;
3187 defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">;
3188 defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">;
3189 defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">;
3190 defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">;
3191 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3192 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3193 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3194 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3195 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3196 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3197 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3198 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3199 int_aarch64_neon_suqadd>;
3200 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3201 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3202 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3203 int_aarch64_neon_usqadd>;
3205 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3207 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3208 (FCVTASv1i64 FPR64:$Rn)>;
3209 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3210 (FCVTAUv1i64 FPR64:$Rn)>;
3211 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3212 (FCVTMSv1i64 FPR64:$Rn)>;
3213 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3214 (FCVTMUv1i64 FPR64:$Rn)>;
3215 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3216 (FCVTNSv1i64 FPR64:$Rn)>;
3217 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3218 (FCVTNUv1i64 FPR64:$Rn)>;
3219 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3220 (FCVTPSv1i64 FPR64:$Rn)>;
3221 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3222 (FCVTPUv1i64 FPR64:$Rn)>;
3224 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3225 (FRECPEv1i32 FPR32:$Rn)>;
3226 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3227 (FRECPEv1i64 FPR64:$Rn)>;
3228 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3229 (FRECPEv1i64 FPR64:$Rn)>;
3231 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3232 (FRECPXv1i32 FPR32:$Rn)>;
3233 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3234 (FRECPXv1i64 FPR64:$Rn)>;
3236 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3237 (FRSQRTEv1i32 FPR32:$Rn)>;
3238 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3239 (FRSQRTEv1i64 FPR64:$Rn)>;
3240 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3241 (FRSQRTEv1i64 FPR64:$Rn)>;
3243 // If an integer is about to be converted to a floating point value,
3244 // just load it on the floating point unit.
3245 // Here are the patterns for 8 and 16-bits to float.
3247 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3248 SDPatternOperator loadop, Instruction UCVTF,
3249 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3251 def : Pat<(DstTy (uint_to_fp (SrcTy
3252 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3253 ro.Wext:$extend))))),
3254 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3255 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3258 def : Pat<(DstTy (uint_to_fp (SrcTy
3259 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3260 ro.Wext:$extend))))),
3261 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3262 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3266 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3267 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3268 def : Pat <(f32 (uint_to_fp (i32
3269 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3270 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3271 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3272 def : Pat <(f32 (uint_to_fp (i32
3273 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3274 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3275 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3276 // 16-bits -> float.
3277 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3278 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3279 def : Pat <(f32 (uint_to_fp (i32
3280 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3281 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3282 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3283 def : Pat <(f32 (uint_to_fp (i32
3284 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3285 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3286 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3287 // 32-bits are handled in target specific dag combine:
3288 // performIntToFpCombine.
3289 // 64-bits integer to 32-bits floating point, not possible with
3290 // UCVTF on floating point registers (both source and destination
3291 // must have the same size).
3293 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3294 // 8-bits -> double.
3295 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3296 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3297 def : Pat <(f64 (uint_to_fp (i32
3298 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3299 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3300 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3301 def : Pat <(f64 (uint_to_fp (i32
3302 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3303 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3304 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3305 // 16-bits -> double.
3306 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3307 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3308 def : Pat <(f64 (uint_to_fp (i32
3309 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3310 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3311 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3312 def : Pat <(f64 (uint_to_fp (i32
3313 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3314 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3315 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3316 // 32-bits -> double.
3317 defm : UIntToFPROLoadPat<f64, i32, load,
3318 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3319 def : Pat <(f64 (uint_to_fp (i32
3320 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3321 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3322 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3323 def : Pat <(f64 (uint_to_fp (i32
3324 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3325 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3326 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3327 // 64-bits -> double are handled in target specific dag combine:
3328 // performIntToFpCombine.
3330 //===----------------------------------------------------------------------===//
3331 // Advanced SIMD three different-sized vector instructions.
3332 //===----------------------------------------------------------------------===//
3334 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3335 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3336 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3337 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3338 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3339 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3341 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3343 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3344 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3345 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3346 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3347 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3348 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3349 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3350 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3351 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3352 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3353 int_aarch64_neon_sqadd>;
3354 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3355 int_aarch64_neon_sqsub>;
3356 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3357 int_aarch64_neon_sqdmull>;
3358 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3359 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3360 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3361 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3362 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3364 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3366 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3367 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3368 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3369 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3370 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3371 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3372 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3373 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3374 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3375 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3376 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3377 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3378 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3380 // Additional patterns for SMULL and UMULL
3381 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3382 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3383 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3384 (INST8B V64:$Rn, V64:$Rm)>;
3385 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3386 (INST4H V64:$Rn, V64:$Rm)>;
3387 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3388 (INST2S V64:$Rn, V64:$Rm)>;
3391 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3392 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3393 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3394 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3396 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3397 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3398 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3399 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3400 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3401 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3402 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3403 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3404 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3407 defm : Neon_mulacc_widen_patterns<
3408 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3409 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3410 defm : Neon_mulacc_widen_patterns<
3411 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3412 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3413 defm : Neon_mulacc_widen_patterns<
3414 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3415 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3416 defm : Neon_mulacc_widen_patterns<
3417 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3418 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3420 // Patterns for 64-bit pmull
3421 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3422 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3423 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3424 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3425 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3427 // CodeGen patterns for addhn and subhn instructions, which can actually be
3428 // written in LLVM IR without too much difficulty.
3431 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3432 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3433 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3435 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3436 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3438 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3439 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3440 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3442 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3443 V128:$Rn, V128:$Rm)>;
3444 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3445 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3447 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3448 V128:$Rn, V128:$Rm)>;
3449 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3450 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3452 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3453 V128:$Rn, V128:$Rm)>;
3456 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3457 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3458 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3460 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3461 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3463 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3464 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3465 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3467 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3468 V128:$Rn, V128:$Rm)>;
3469 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3470 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3472 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3473 V128:$Rn, V128:$Rm)>;
3474 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3475 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3477 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3478 V128:$Rn, V128:$Rm)>;
3480 //----------------------------------------------------------------------------
3481 // AdvSIMD bitwise extract from vector instruction.
3482 //----------------------------------------------------------------------------
3484 defm EXT : SIMDBitwiseExtract<"ext">;
3486 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3487 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3488 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3489 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3490 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3491 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3492 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3493 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3494 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3495 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3496 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3497 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3498 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3499 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3500 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3501 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3502 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3503 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3504 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3505 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3507 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3509 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3510 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3511 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3512 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3513 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3514 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3515 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3516 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3517 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3518 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3519 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3520 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3521 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3522 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3525 //----------------------------------------------------------------------------
3526 // AdvSIMD zip vector
3527 //----------------------------------------------------------------------------
3529 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3530 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3531 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3532 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3533 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3534 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3536 //----------------------------------------------------------------------------
3537 // AdvSIMD TBL/TBX instructions
3538 //----------------------------------------------------------------------------
3540 defm TBL : SIMDTableLookup< 0, "tbl">;
3541 defm TBX : SIMDTableLookupTied<1, "tbx">;
3543 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3544 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3545 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3546 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3548 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3549 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3550 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3551 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3552 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3553 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3556 //----------------------------------------------------------------------------
3557 // AdvSIMD scalar CPY instruction
3558 //----------------------------------------------------------------------------
3560 defm CPY : SIMDScalarCPY<"cpy">;
3562 //----------------------------------------------------------------------------
3563 // AdvSIMD scalar pairwise instructions
3564 //----------------------------------------------------------------------------
3566 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3567 defm FADDP : SIMDFPPairwiseScalar<1, 0, 0b01101, "faddp">;
3568 defm FMAXNMP : SIMDFPPairwiseScalar<1, 0, 0b01100, "fmaxnmp">;
3569 defm FMAXP : SIMDFPPairwiseScalar<1, 0, 0b01111, "fmaxp">;
3570 defm FMINNMP : SIMDFPPairwiseScalar<1, 1, 0b01100, "fminnmp">;
3571 defm FMINP : SIMDFPPairwiseScalar<1, 1, 0b01111, "fminp">;
3572 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3573 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3574 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3575 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3576 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3577 (FADDPv2i32p V64:$Rn)>;
3578 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3579 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3580 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3581 (FADDPv2i64p V128:$Rn)>;
3582 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3583 (FMAXNMPv2i32p V64:$Rn)>;
3584 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3585 (FMAXNMPv2i64p V128:$Rn)>;
3586 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3587 (FMAXPv2i32p V64:$Rn)>;
3588 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3589 (FMAXPv2i64p V128:$Rn)>;
3590 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3591 (FMINNMPv2i32p V64:$Rn)>;
3592 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3593 (FMINNMPv2i64p V128:$Rn)>;
3594 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3595 (FMINPv2i32p V64:$Rn)>;
3596 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3597 (FMINPv2i64p V128:$Rn)>;
3599 //----------------------------------------------------------------------------
3600 // AdvSIMD INS/DUP instructions
3601 //----------------------------------------------------------------------------
3603 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
3604 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
3605 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
3606 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
3607 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
3608 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
3609 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
3611 def DUPv2i64lane : SIMDDup64FromElement;
3612 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3613 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3614 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3615 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3616 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3617 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3619 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3620 (v2f32 (DUPv2i32lane
3621 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3623 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3624 (v4f32 (DUPv4i32lane
3625 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3627 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3628 (v2f64 (DUPv2i64lane
3629 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3631 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3632 (v4f16 (DUPv4i16lane
3633 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3635 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3636 (v8f16 (DUPv8i16lane
3637 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3640 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3641 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3642 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3643 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3645 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3646 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3647 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3648 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3649 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3650 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3652 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3653 // instruction even if the types don't match: we just have to remap the lane
3654 // carefully. N.b. this trick only applies to truncations.
3655 def VecIndex_x2 : SDNodeXForm<imm, [{
3656 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
3658 def VecIndex_x4 : SDNodeXForm<imm, [{
3659 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
3661 def VecIndex_x8 : SDNodeXForm<imm, [{
3662 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
3665 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3666 ValueType Src128VT, ValueType ScalVT,
3667 Instruction DUP, SDNodeXForm IdxXFORM> {
3668 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3670 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3672 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3674 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3677 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3678 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3679 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3681 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3682 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3683 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3685 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3686 SDNodeXForm IdxXFORM> {
3687 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3689 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3691 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3693 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3696 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3697 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3698 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3700 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3701 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3702 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3704 // SMOV and UMOV definitions, with some extra patterns for convenience
3708 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3709 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3710 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3711 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3712 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3713 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3714 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3715 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3716 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3717 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3718 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3719 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3721 // Extracting i8 or i16 elements will have the zero-extend transformed to
3722 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3723 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3724 // bits of the destination register.
3725 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3727 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3728 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3730 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3734 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3735 (SUBREG_TO_REG (i32 0),
3736 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3737 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3738 (SUBREG_TO_REG (i32 0),
3739 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3741 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3742 (SUBREG_TO_REG (i32 0),
3743 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3744 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3745 (SUBREG_TO_REG (i32 0),
3746 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3748 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3749 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3750 (i32 FPR32:$Rn), ssub))>;
3751 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3752 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3753 (i32 FPR32:$Rn), ssub))>;
3754 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3755 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3756 (i64 FPR64:$Rn), dsub))>;
3758 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3759 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3760 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3761 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3762 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3763 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3765 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3766 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3769 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3771 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3775 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3776 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3778 V128:$Rn, VectorIndexH:$imm,
3779 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3782 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3783 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3786 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3788 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3791 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3792 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3794 V128:$Rn, VectorIndexS:$imm,
3795 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3797 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3798 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3800 V128:$Rn, VectorIndexD:$imm,
3801 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3804 // Copy an element at a constant index in one vector into a constant indexed
3805 // element of another.
3806 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3807 // index type and INS extension
3808 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3809 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3810 VectorIndexB:$idx2)),
3812 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3814 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3815 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3816 VectorIndexH:$idx2)),
3818 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3820 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3821 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3822 VectorIndexS:$idx2)),
3824 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3826 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3827 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3828 VectorIndexD:$idx2)),
3830 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3833 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3834 ValueType VTScal, Instruction INS> {
3835 def : Pat<(VT128 (vector_insert V128:$src,
3836 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3838 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3840 def : Pat<(VT128 (vector_insert V128:$src,
3841 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3843 (INS V128:$src, imm:$Immd,
3844 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3846 def : Pat<(VT64 (vector_insert V64:$src,
3847 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3849 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3850 imm:$Immd, V128:$Rn, imm:$Immn),
3853 def : Pat<(VT64 (vector_insert V64:$src,
3854 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3857 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3858 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3862 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3863 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3864 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3867 // Floating point vector extractions are codegen'd as either a sequence of
3868 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
3869 // the lane number is anything other than zero.
3870 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3871 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3872 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3873 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3874 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3875 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3877 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3878 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
3879 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3880 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
3881 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3882 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
3884 // All concat_vectors operations are canonicalised to act on i64 vectors for
3885 // AArch64. In the general case we need an instruction, which had just as well be
3887 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3888 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3889 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3890 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3892 def : ConcatPat<v2i64, v1i64>;
3893 def : ConcatPat<v2f64, v1f64>;
3894 def : ConcatPat<v4i32, v2i32>;
3895 def : ConcatPat<v4f32, v2f32>;
3896 def : ConcatPat<v8i16, v4i16>;
3897 def : ConcatPat<v8f16, v4f16>;
3898 def : ConcatPat<v16i8, v8i8>;
3900 // If the high lanes are undef, though, we can just ignore them:
3901 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3902 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3903 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3905 def : ConcatUndefPat<v2i64, v1i64>;
3906 def : ConcatUndefPat<v2f64, v1f64>;
3907 def : ConcatUndefPat<v4i32, v2i32>;
3908 def : ConcatUndefPat<v4f32, v2f32>;
3909 def : ConcatUndefPat<v8i16, v4i16>;
3910 def : ConcatUndefPat<v16i8, v8i8>;
3912 //----------------------------------------------------------------------------
3913 // AdvSIMD across lanes instructions
3914 //----------------------------------------------------------------------------
3916 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3917 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3918 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3919 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3920 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3921 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3922 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3923 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3924 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3925 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3926 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3928 // Patterns for across-vector intrinsics, that have a node equivalent, that
3929 // returns a vector (with only the low lane defined) instead of a scalar.
3930 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
3931 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
3932 SDPatternOperator opNode> {
3933 // If a lane instruction caught the vector_extract around opNode, we can
3934 // directly match the latter to the instruction.
3935 def : Pat<(v8i8 (opNode V64:$Rn)),
3936 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3937 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
3938 def : Pat<(v16i8 (opNode V128:$Rn)),
3939 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3940 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
3941 def : Pat<(v4i16 (opNode V64:$Rn)),
3942 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3943 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
3944 def : Pat<(v8i16 (opNode V128:$Rn)),
3945 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3946 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
3947 def : Pat<(v4i32 (opNode V128:$Rn)),
3948 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3949 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
3952 // If none did, fallback to the explicit patterns, consuming the vector_extract.
3953 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
3954 (i32 0)), (i64 0))),
3955 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
3956 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
3958 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
3959 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3960 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
3962 def : Pat<(i32 (vector_extract (insert_subvector undef,
3963 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
3964 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
3965 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
3967 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
3968 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
3969 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
3971 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
3972 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3973 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
3978 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
3979 SDPatternOperator opNode>
3980 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
3981 // If there is a sign extension after this intrinsic, consume it as smov already
3983 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
3984 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
3986 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3987 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3989 def : Pat<(i32 (sext_inreg (i32 (vector_extract
3990 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
3992 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3993 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3995 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
3996 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
3998 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3999 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4001 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4002 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
4004 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4005 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4009 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
4010 SDPatternOperator opNode>
4011 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4012 // If there is a masking operation keeping only what has been actually
4013 // generated, consume it.
4014 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4015 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
4016 (i32 (EXTRACT_SUBREG
4017 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4018 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4020 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4022 (i32 (EXTRACT_SUBREG
4023 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4024 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4026 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4027 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
4028 (i32 (EXTRACT_SUBREG
4029 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4030 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4032 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4034 (i32 (EXTRACT_SUBREG
4035 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4036 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4040 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
4041 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4042 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
4043 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4045 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
4046 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4047 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
4048 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4050 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
4051 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
4052 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
4054 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
4055 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
4056 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
4058 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
4059 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
4060 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
4062 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
4063 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
4064 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
4066 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
4067 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4069 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4070 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4072 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4074 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4075 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4078 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4079 (i32 (EXTRACT_SUBREG
4080 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4081 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4083 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4084 (i32 (EXTRACT_SUBREG
4085 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4086 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4089 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4090 (i64 (EXTRACT_SUBREG
4091 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4092 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4096 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
4098 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4099 (i32 (EXTRACT_SUBREG
4100 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4101 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4103 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4104 (i32 (EXTRACT_SUBREG
4105 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4106 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4109 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4110 (i32 (EXTRACT_SUBREG
4111 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4112 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4114 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4115 (i32 (EXTRACT_SUBREG
4116 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4117 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4120 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4121 (i64 (EXTRACT_SUBREG
4122 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4123 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4127 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4128 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4130 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4131 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4132 (i64 (EXTRACT_SUBREG
4133 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4134 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4136 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4137 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4138 (i64 (EXTRACT_SUBREG
4139 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4140 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4143 //------------------------------------------------------------------------------
4144 // AdvSIMD modified immediate instructions
4145 //------------------------------------------------------------------------------
4148 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4150 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4152 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4153 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4154 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4155 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4157 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4158 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4159 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4160 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4162 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4163 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4164 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4165 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4167 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4168 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4169 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4170 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4173 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4175 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4176 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4178 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4179 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4181 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4185 // EDIT byte mask: scalar
4186 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4187 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4188 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4189 // The movi_edit node has the immediate value already encoded, so we use
4190 // a plain imm0_255 here.
4191 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4192 (MOVID imm0_255:$shift)>;
4194 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4195 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4196 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4197 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4199 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4200 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4201 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4202 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4204 // EDIT byte mask: 2d
4206 // The movi_edit node has the immediate value already encoded, so we use
4207 // a plain imm0_255 in the pattern
4208 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4209 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4212 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4215 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4216 // Complexity is added to break a tie with a plain MOVI.
4217 let AddedComplexity = 1 in {
4218 def : Pat<(f32 fpimm0),
4219 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4221 def : Pat<(f64 fpimm0),
4222 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4226 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4227 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4228 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4229 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4231 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4232 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4233 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4234 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4236 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4237 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4239 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4240 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4242 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4243 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4244 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4245 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4247 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4248 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4249 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4250 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4252 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4253 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4254 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4255 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4256 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4257 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4258 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4259 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4261 // EDIT per word: 2s & 4s with MSL shifter
4262 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4263 [(set (v2i32 V64:$Rd),
4264 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4265 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4266 [(set (v4i32 V128:$Rd),
4267 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4269 // Per byte: 8b & 16b
4270 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4272 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4273 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4275 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4279 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4280 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4282 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4283 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4284 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4285 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4287 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4288 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4289 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4290 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4292 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4293 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4294 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4295 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4296 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4297 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4298 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4299 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4301 // EDIT per word: 2s & 4s with MSL shifter
4302 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4303 [(set (v2i32 V64:$Rd),
4304 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4305 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4306 [(set (v4i32 V128:$Rd),
4307 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4309 //----------------------------------------------------------------------------
4310 // AdvSIMD indexed element
4311 //----------------------------------------------------------------------------
4313 let hasSideEffects = 0 in {
4314 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">;
4315 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">;
4318 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4319 // instruction expects the addend first, while the intrinsic expects it last.
4321 // On the other hand, there are quite a few valid combinatorial options due to
4322 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4323 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4324 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4325 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4326 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4328 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4329 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4330 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4331 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4332 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4333 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4334 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4335 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4337 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4338 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4340 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4341 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4342 VectorIndexS:$idx))),
4343 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4344 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4345 (v2f32 (AArch64duplane32
4346 (v4f32 (insert_subvector undef,
4347 (v2f32 (fneg V64:$Rm)),
4349 VectorIndexS:$idx)))),
4350 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4351 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4352 VectorIndexS:$idx)>;
4353 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4354 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4355 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4356 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4358 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4360 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4361 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4362 VectorIndexS:$idx))),
4363 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4364 VectorIndexS:$idx)>;
4365 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4366 (v4f32 (AArch64duplane32
4367 (v4f32 (insert_subvector undef,
4368 (v2f32 (fneg V64:$Rm)),
4370 VectorIndexS:$idx)))),
4371 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4372 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4373 VectorIndexS:$idx)>;
4374 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4375 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4376 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4377 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4379 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4380 // (DUPLANE from 64-bit would be trivial).
4381 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4382 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4383 VectorIndexD:$idx))),
4385 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4386 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4387 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4388 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4389 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4391 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4392 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4393 (vector_extract (v4f32 (fneg V128:$Rm)),
4394 VectorIndexS:$idx))),
4395 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4396 V128:$Rm, VectorIndexS:$idx)>;
4397 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4398 (vector_extract (v4f32 (insert_subvector undef,
4399 (v2f32 (fneg V64:$Rm)),
4401 VectorIndexS:$idx))),
4402 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4403 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4405 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4406 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4407 (vector_extract (v2f64 (fneg V128:$Rm)),
4408 VectorIndexS:$idx))),
4409 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4410 V128:$Rm, VectorIndexS:$idx)>;
4413 defm : FMLSIndexedAfterNegPatterns<
4414 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4415 defm : FMLSIndexedAfterNegPatterns<
4416 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4418 defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4419 defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>;
4421 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4422 (FMULv2i32_indexed V64:$Rn,
4423 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4425 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4426 (FMULv4i32_indexed V128:$Rn,
4427 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4429 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4430 (FMULv2i64_indexed V128:$Rn,
4431 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4434 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4435 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4436 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4437 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4438 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4439 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4440 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4441 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4442 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4443 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4444 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4445 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4446 int_aarch64_neon_smull>;
4447 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4448 int_aarch64_neon_sqadd>;
4449 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4450 int_aarch64_neon_sqsub>;
4451 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
4452 int_aarch64_neon_sqadd>;
4453 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
4454 int_aarch64_neon_sqsub>;
4455 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4456 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4457 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4458 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4459 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4460 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4461 int_aarch64_neon_umull>;
4463 // A scalar sqdmull with the second operand being a vector lane can be
4464 // handled directly with the indexed instruction encoding.
4465 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4466 (vector_extract (v4i32 V128:$Vm),
4467 VectorIndexS:$idx)),
4468 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4470 //----------------------------------------------------------------------------
4471 // AdvSIMD scalar shift instructions
4472 //----------------------------------------------------------------------------
4473 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4474 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4475 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4476 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4477 // Codegen patterns for the above. We don't put these directly on the
4478 // instructions because TableGen's type inference can't handle the truth.
4479 // Having the same base pattern for fp <--> int totally freaks it out.
4480 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4481 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4482 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4483 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4484 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4485 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4486 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4487 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4488 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4490 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4491 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4493 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4494 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4495 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4496 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4497 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4498 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4499 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4500 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4501 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4502 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4504 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4505 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4507 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4509 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4510 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4511 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4512 int_aarch64_neon_sqrshrn>;
4513 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4514 int_aarch64_neon_sqrshrun>;
4515 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4516 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4517 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4518 int_aarch64_neon_sqshrn>;
4519 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4520 int_aarch64_neon_sqshrun>;
4521 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4522 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4523 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4524 TriOpFrag<(add node:$LHS,
4525 (AArch64srshri node:$MHS, node:$RHS))>>;
4526 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4527 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4528 TriOpFrag<(add node:$LHS,
4529 (AArch64vashr node:$MHS, node:$RHS))>>;
4530 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4531 int_aarch64_neon_uqrshrn>;
4532 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4533 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4534 int_aarch64_neon_uqshrn>;
4535 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4536 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4537 TriOpFrag<(add node:$LHS,
4538 (AArch64urshri node:$MHS, node:$RHS))>>;
4539 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4540 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4541 TriOpFrag<(add node:$LHS,
4542 (AArch64vlshr node:$MHS, node:$RHS))>>;
4544 //----------------------------------------------------------------------------
4545 // AdvSIMD vector shift instructions
4546 //----------------------------------------------------------------------------
4547 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4548 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4549 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4550 int_aarch64_neon_vcvtfxs2fp>;
4551 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4552 int_aarch64_neon_rshrn>;
4553 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4554 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4555 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4556 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4557 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4558 (i32 vecshiftL64:$imm))),
4559 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4560 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4561 int_aarch64_neon_sqrshrn>;
4562 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4563 int_aarch64_neon_sqrshrun>;
4564 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4565 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4566 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4567 int_aarch64_neon_sqshrn>;
4568 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4569 int_aarch64_neon_sqshrun>;
4570 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4571 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4572 (i32 vecshiftR64:$imm))),
4573 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4574 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4575 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4576 TriOpFrag<(add node:$LHS,
4577 (AArch64srshri node:$MHS, node:$RHS))> >;
4578 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4579 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4581 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4582 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4583 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4584 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4585 int_aarch64_neon_vcvtfxu2fp>;
4586 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4587 int_aarch64_neon_uqrshrn>;
4588 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4589 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4590 int_aarch64_neon_uqshrn>;
4591 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4592 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4593 TriOpFrag<(add node:$LHS,
4594 (AArch64urshri node:$MHS, node:$RHS))> >;
4595 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4596 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4597 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4598 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4599 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4601 // SHRN patterns for when a logical right shift was used instead of arithmetic
4602 // (the immediate guarantees no sign bits actually end up in the result so it
4604 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4605 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4606 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4607 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4608 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4609 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4611 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4612 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4613 vecshiftR16Narrow:$imm)))),
4614 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4615 V128:$Rn, vecshiftR16Narrow:$imm)>;
4616 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4617 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4618 vecshiftR32Narrow:$imm)))),
4619 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4620 V128:$Rn, vecshiftR32Narrow:$imm)>;
4621 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4622 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4623 vecshiftR64Narrow:$imm)))),
4624 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4625 V128:$Rn, vecshiftR32Narrow:$imm)>;
4627 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4628 // Anyexts are implemented as zexts.
4629 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4630 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4631 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4632 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4633 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4634 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4635 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4636 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4637 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4638 // Also match an extend from the upper half of a 128 bit source register.
4639 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4640 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4641 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4642 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4643 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4644 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4645 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4646 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4647 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4648 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4649 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4650 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4651 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4652 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4653 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4654 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4655 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4656 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4658 // Vector shift sxtl aliases
4659 def : InstAlias<"sxtl.8h $dst, $src1",
4660 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4661 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4662 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4663 def : InstAlias<"sxtl.4s $dst, $src1",
4664 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4665 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4666 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4667 def : InstAlias<"sxtl.2d $dst, $src1",
4668 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4669 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4670 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4672 // Vector shift sxtl2 aliases
4673 def : InstAlias<"sxtl2.8h $dst, $src1",
4674 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4675 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4676 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4677 def : InstAlias<"sxtl2.4s $dst, $src1",
4678 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4679 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4680 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4681 def : InstAlias<"sxtl2.2d $dst, $src1",
4682 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4683 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4684 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4686 // Vector shift uxtl aliases
4687 def : InstAlias<"uxtl.8h $dst, $src1",
4688 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4689 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4690 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4691 def : InstAlias<"uxtl.4s $dst, $src1",
4692 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4693 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4694 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4695 def : InstAlias<"uxtl.2d $dst, $src1",
4696 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4697 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4698 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4700 // Vector shift uxtl2 aliases
4701 def : InstAlias<"uxtl2.8h $dst, $src1",
4702 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4703 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4704 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4705 def : InstAlias<"uxtl2.4s $dst, $src1",
4706 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4707 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4708 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4709 def : InstAlias<"uxtl2.2d $dst, $src1",
4710 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4711 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4712 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4714 // If an integer is about to be converted to a floating point value,
4715 // just load it on the floating point unit.
4716 // These patterns are more complex because floating point loads do not
4717 // support sign extension.
4718 // The sign extension has to be explicitly added and is only supported for
4719 // one step: byte-to-half, half-to-word, word-to-doubleword.
4720 // SCVTF GPR -> FPR is 9 cycles.
4721 // SCVTF FPR -> FPR is 4 cyclces.
4722 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4723 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4724 // and still being faster.
4725 // However, this is not good for code size.
4726 // 8-bits -> float. 2 sizes step-up.
4727 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4728 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4729 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4734 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4740 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4742 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4743 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4744 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4745 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4746 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4747 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4748 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4749 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4751 // 16-bits -> float. 1 size step-up.
4752 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4753 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4754 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4756 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4760 ssub)))>, Requires<[NotForCodeSize]>;
4762 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4763 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4764 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4765 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4766 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4767 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4768 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4769 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4771 // 32-bits to 32-bits are handled in target specific dag combine:
4772 // performIntToFpCombine.
4773 // 64-bits integer to 32-bits floating point, not possible with
4774 // SCVTF on floating point registers (both source and destination
4775 // must have the same size).
4777 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4778 // 8-bits -> double. 3 size step-up: give up.
4779 // 16-bits -> double. 2 size step.
4780 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4781 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4782 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4787 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4793 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4795 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4796 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4797 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4798 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4799 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4800 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4801 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4802 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4803 // 32-bits -> double. 1 size step-up.
4804 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4805 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4806 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4808 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4812 dsub)))>, Requires<[NotForCodeSize]>;
4814 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4815 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4816 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4817 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4818 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4819 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4820 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4821 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4823 // 64-bits -> double are handled in target specific dag combine:
4824 // performIntToFpCombine.
4827 //----------------------------------------------------------------------------
4828 // AdvSIMD Load-Store Structure
4829 //----------------------------------------------------------------------------
4830 defm LD1 : SIMDLd1Multiple<"ld1">;
4831 defm LD2 : SIMDLd2Multiple<"ld2">;
4832 defm LD3 : SIMDLd3Multiple<"ld3">;
4833 defm LD4 : SIMDLd4Multiple<"ld4">;
4835 defm ST1 : SIMDSt1Multiple<"st1">;
4836 defm ST2 : SIMDSt2Multiple<"st2">;
4837 defm ST3 : SIMDSt3Multiple<"st3">;
4838 defm ST4 : SIMDSt4Multiple<"st4">;
4840 class Ld1Pat<ValueType ty, Instruction INST>
4841 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4843 def : Ld1Pat<v16i8, LD1Onev16b>;
4844 def : Ld1Pat<v8i16, LD1Onev8h>;
4845 def : Ld1Pat<v4i32, LD1Onev4s>;
4846 def : Ld1Pat<v2i64, LD1Onev2d>;
4847 def : Ld1Pat<v8i8, LD1Onev8b>;
4848 def : Ld1Pat<v4i16, LD1Onev4h>;
4849 def : Ld1Pat<v2i32, LD1Onev2s>;
4850 def : Ld1Pat<v1i64, LD1Onev1d>;
4852 class St1Pat<ValueType ty, Instruction INST>
4853 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4854 (INST ty:$Vt, GPR64sp:$Rn)>;
4856 def : St1Pat<v16i8, ST1Onev16b>;
4857 def : St1Pat<v8i16, ST1Onev8h>;
4858 def : St1Pat<v4i32, ST1Onev4s>;
4859 def : St1Pat<v2i64, ST1Onev2d>;
4860 def : St1Pat<v8i8, ST1Onev8b>;
4861 def : St1Pat<v4i16, ST1Onev4h>;
4862 def : St1Pat<v2i32, ST1Onev2s>;
4863 def : St1Pat<v1i64, ST1Onev1d>;
4869 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4870 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4871 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4872 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4873 let mayLoad = 1, hasSideEffects = 0 in {
4874 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4875 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4876 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4877 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4878 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4879 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4880 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4881 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4882 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4883 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4884 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4885 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4886 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4887 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4888 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4889 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4892 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4893 (LD1Rv8b GPR64sp:$Rn)>;
4894 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4895 (LD1Rv16b GPR64sp:$Rn)>;
4896 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4897 (LD1Rv4h GPR64sp:$Rn)>;
4898 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4899 (LD1Rv8h GPR64sp:$Rn)>;
4900 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4901 (LD1Rv2s GPR64sp:$Rn)>;
4902 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4903 (LD1Rv4s GPR64sp:$Rn)>;
4904 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4905 (LD1Rv2d GPR64sp:$Rn)>;
4906 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4907 (LD1Rv1d GPR64sp:$Rn)>;
4908 // Grab the floating point version too
4909 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4910 (LD1Rv2s GPR64sp:$Rn)>;
4911 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4912 (LD1Rv4s GPR64sp:$Rn)>;
4913 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4914 (LD1Rv2d GPR64sp:$Rn)>;
4915 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4916 (LD1Rv1d GPR64sp:$Rn)>;
4917 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4918 (LD1Rv4h GPR64sp:$Rn)>;
4919 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4920 (LD1Rv8h GPR64sp:$Rn)>;
4922 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4923 ValueType VTy, ValueType STy, Instruction LD1>
4924 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4925 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4926 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4928 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4929 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4930 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4931 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4932 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4933 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4934 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4936 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4937 ValueType VTy, ValueType STy, Instruction LD1>
4938 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4939 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4941 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4942 VecIndex:$idx, GPR64sp:$Rn),
4945 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4946 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4947 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4948 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4949 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4952 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4953 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4954 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4955 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4958 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4959 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4960 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4961 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4963 let AddedComplexity = 19 in
4964 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4965 ValueType VTy, ValueType STy, Instruction ST1>
4967 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4969 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4971 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4972 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4973 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4974 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4975 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4976 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4977 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
4979 let AddedComplexity = 19 in
4980 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4981 ValueType VTy, ValueType STy, Instruction ST1>
4983 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4985 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4986 VecIndex:$idx, GPR64sp:$Rn)>;
4988 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4989 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4990 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4991 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4992 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
4994 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4995 ValueType VTy, ValueType STy, Instruction ST1,
4997 def : Pat<(scalar_store
4998 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4999 GPR64sp:$Rn, offset),
5000 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5001 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5003 def : Pat<(scalar_store
5004 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5005 GPR64sp:$Rn, GPR64:$Rm),
5006 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5007 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5010 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
5011 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
5013 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
5014 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
5015 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
5016 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
5017 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
5019 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5020 ValueType VTy, ValueType STy, Instruction ST1,
5022 def : Pat<(scalar_store
5023 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5024 GPR64sp:$Rn, offset),
5025 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5027 def : Pat<(scalar_store
5028 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5029 GPR64sp:$Rn, GPR64:$Rm),
5030 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5033 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
5035 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
5037 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
5038 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
5039 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
5040 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
5041 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
5043 let mayStore = 1, hasSideEffects = 0 in {
5044 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
5045 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
5046 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5047 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5048 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
5049 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
5050 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5051 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5052 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
5053 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
5054 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
5055 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
5058 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
5059 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
5060 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
5061 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
5063 //----------------------------------------------------------------------------
5064 // Crypto extensions
5065 //----------------------------------------------------------------------------
5067 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
5068 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
5069 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
5070 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
5072 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
5073 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
5074 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
5075 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
5076 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
5077 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
5078 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
5080 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
5081 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
5082 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
5084 //----------------------------------------------------------------------------
5086 //----------------------------------------------------------------------------
5087 // FIXME: Like for X86, these should go in their own separate .td file.
5089 // Any instruction that defines a 32-bit result leaves the high half of the
5090 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
5091 // be copying from a truncate. But any other 32-bit operation will zero-extend
5093 // FIXME: X86 also checks for CMOV here. Do we need something similar?
5094 def def32 : PatLeaf<(i32 GPR32:$src), [{
5095 return N->getOpcode() != ISD::TRUNCATE &&
5096 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
5097 N->getOpcode() != ISD::CopyFromReg;
5100 // In the case of a 32-bit def that is known to implicitly zero-extend,
5101 // we can use a SUBREG_TO_REG.
5102 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
5104 // For an anyext, we don't care what the high bits are, so we can perform an
5105 // INSERT_SUBREF into an IMPLICIT_DEF.
5106 def : Pat<(i64 (anyext GPR32:$src)),
5107 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5109 // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and
5110 // then assert the extension has happened.
5111 def : Pat<(i64 (zext GPR32:$src)),
5112 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>;
5114 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5115 // containing super-reg.
5116 def : Pat<(i64 (sext GPR32:$src)),
5117 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5118 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5119 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5120 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5121 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5122 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5123 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5124 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5126 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5127 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5128 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5129 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5130 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5131 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5133 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5134 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5135 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5136 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5137 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5138 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5140 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5141 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5142 (i64 (i64shift_a imm0_63:$imm)),
5143 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5145 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5146 // AddedComplexity for the following patterns since we want to match sext + sra
5147 // patterns before we attempt to match a single sra node.
5148 let AddedComplexity = 20 in {
5149 // We support all sext + sra combinations which preserve at least one bit of the
5150 // original value which is to be sign extended. E.g. we support shifts up to
5152 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5153 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5154 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5155 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5157 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5158 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5159 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5160 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5162 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5163 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5164 (i64 imm0_31:$imm), 31)>;
5165 } // AddedComplexity = 20
5167 // To truncate, we can simply extract from a subregister.
5168 def : Pat<(i32 (trunc GPR64sp:$src)),
5169 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5171 // __builtin_trap() uses the BRK instruction on AArch64.
5172 def : Pat<(trap), (BRK 1)>;
5174 // Conversions within AdvSIMD types in the same register size are free.
5175 // But because we need a consistent lane ordering, in big endian many
5176 // conversions require one or more REV instructions.
5178 // Consider a simple memory load followed by a bitconvert then a store.
5180 // v1 = BITCAST v2i32 v0 to v4i16
5183 // In big endian mode every memory access has an implicit byte swap. LDR and
5184 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5185 // is, they treat the vector as a sequence of elements to be byte-swapped.
5186 // The two pairs of instructions are fundamentally incompatible. We've decided
5187 // to use LD1/ST1 only to simplify compiler implementation.
5189 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5190 // the original code sequence:
5192 // v1 = REV v2i32 (implicit)
5193 // v2 = BITCAST v2i32 v1 to v4i16
5194 // v3 = REV v4i16 v2 (implicit)
5197 // But this is now broken - the value stored is different to the value loaded
5198 // due to lane reordering. To fix this, on every BITCAST we must perform two
5201 // v1 = REV v2i32 (implicit)
5203 // v3 = BITCAST v2i32 v2 to v4i16
5205 // v5 = REV v4i16 v4 (implicit)
5208 // This means an extra two instructions, but actually in most cases the two REV
5209 // instructions can be combined into one. For example:
5210 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5212 // There is also no 128-bit REV instruction. This must be synthesized with an
5215 // Most bitconverts require some sort of conversion. The only exceptions are:
5216 // a) Identity conversions - vNfX <-> vNiX
5217 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5220 // Natural vector casts (64 bit)
5221 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5222 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5223 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5224 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5225 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5226 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5228 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5229 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5230 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5231 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5232 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5234 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5235 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5236 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5237 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5238 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5240 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5241 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5242 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5243 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5244 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5245 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5246 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5248 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5249 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5250 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5251 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5252 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5254 // Natural vector casts (128 bit)
5255 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5256 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5257 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5258 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5259 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5260 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5261 def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5263 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5264 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5265 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5266 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5267 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5268 def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5269 def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5271 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5272 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5273 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5274 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5275 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5276 def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5277 def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5279 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5280 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5281 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5282 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5283 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5284 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5285 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5287 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5288 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5289 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5290 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5291 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5292 def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5293 def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5295 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5296 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5297 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5298 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5299 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5300 def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5301 def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5303 let Predicates = [IsLE] in {
5304 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5305 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5306 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5307 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5308 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5310 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5311 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5312 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5313 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5314 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5315 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5316 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5317 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5318 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5319 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5320 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5321 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5323 let Predicates = [IsBE] in {
5324 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5325 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5326 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5327 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5328 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5329 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5330 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5331 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5332 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5333 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5335 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5336 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5337 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5338 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5339 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5340 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5341 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5342 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5343 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5344 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5346 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5347 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5348 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5349 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5350 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5351 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5352 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5353 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5354 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5356 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5357 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5358 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5359 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5360 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5361 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5362 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5363 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5364 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5365 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5367 let Predicates = [IsLE] in {
5368 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5369 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5370 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5371 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5372 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5374 let Predicates = [IsBE] in {
5375 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5376 (v1i64 (REV64v2i32 FPR64:$src))>;
5377 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5378 (v1i64 (REV64v4i16 FPR64:$src))>;
5379 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5380 (v1i64 (REV64v8i8 FPR64:$src))>;
5381 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5382 (v1i64 (REV64v4i16 FPR64:$src))>;
5383 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5384 (v1i64 (REV64v2i32 FPR64:$src))>;
5386 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5387 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5389 let Predicates = [IsLE] in {
5390 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5391 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5392 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5393 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5394 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5395 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5397 let Predicates = [IsBE] in {
5398 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5399 (v2i32 (REV64v2i32 FPR64:$src))>;
5400 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5401 (v2i32 (REV32v4i16 FPR64:$src))>;
5402 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5403 (v2i32 (REV32v8i8 FPR64:$src))>;
5404 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5405 (v2i32 (REV64v2i32 FPR64:$src))>;
5406 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5407 (v2i32 (REV64v2i32 FPR64:$src))>;
5408 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5409 (v2i32 (REV64v4i16 FPR64:$src))>;
5411 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5413 let Predicates = [IsLE] in {
5414 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5415 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5416 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5417 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5418 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5419 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5420 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5422 let Predicates = [IsBE] in {
5423 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5424 (v4i16 (REV64v4i16 FPR64:$src))>;
5425 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5426 (v4i16 (REV32v4i16 FPR64:$src))>;
5427 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5428 (v4i16 (REV16v8i8 FPR64:$src))>;
5429 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5430 (v4i16 (REV64v4i16 FPR64:$src))>;
5431 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5432 (v4i16 (REV32v4i16 FPR64:$src))>;
5433 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5434 (v4i16 (REV32v4i16 FPR64:$src))>;
5435 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5436 (v4i16 (REV64v4i16 FPR64:$src))>;
5439 let Predicates = [IsLE] in {
5440 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5441 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5442 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5443 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5444 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5445 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5446 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5448 let Predicates = [IsBE] in {
5449 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5450 (v4f16 (REV64v4i16 FPR64:$src))>;
5451 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5452 (v4f16 (REV64v4i16 FPR64:$src))>;
5453 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5454 (v4f16 (REV64v4i16 FPR64:$src))>;
5455 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5456 (v4f16 (REV16v8i8 FPR64:$src))>;
5457 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5458 (v4f16 (REV64v4i16 FPR64:$src))>;
5459 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5460 (v4f16 (REV64v4i16 FPR64:$src))>;
5461 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5462 (v4f16 (REV64v4i16 FPR64:$src))>;
5467 let Predicates = [IsLE] in {
5468 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5469 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5470 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5471 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5472 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5473 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5474 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5476 let Predicates = [IsBE] in {
5477 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5478 (v8i8 (REV64v8i8 FPR64:$src))>;
5479 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5480 (v8i8 (REV32v8i8 FPR64:$src))>;
5481 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5482 (v8i8 (REV16v8i8 FPR64:$src))>;
5483 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5484 (v8i8 (REV64v8i8 FPR64:$src))>;
5485 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5486 (v8i8 (REV32v8i8 FPR64:$src))>;
5487 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5488 (v8i8 (REV64v8i8 FPR64:$src))>;
5489 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5490 (v8i8 (REV16v8i8 FPR64:$src))>;
5493 let Predicates = [IsLE] in {
5494 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5495 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5496 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5497 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5498 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5500 let Predicates = [IsBE] in {
5501 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5502 (f64 (REV64v2i32 FPR64:$src))>;
5503 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5504 (f64 (REV64v4i16 FPR64:$src))>;
5505 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5506 (f64 (REV64v2i32 FPR64:$src))>;
5507 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5508 (f64 (REV64v8i8 FPR64:$src))>;
5509 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5510 (f64 (REV64v4i16 FPR64:$src))>;
5512 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5513 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5515 let Predicates = [IsLE] in {
5516 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5517 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5518 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5519 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5520 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5522 let Predicates = [IsBE] in {
5523 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5524 (v1f64 (REV64v2i32 FPR64:$src))>;
5525 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5526 (v1f64 (REV64v4i16 FPR64:$src))>;
5527 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5528 (v1f64 (REV64v8i8 FPR64:$src))>;
5529 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5530 (v1f64 (REV64v2i32 FPR64:$src))>;
5531 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5532 (v1f64 (REV64v4i16 FPR64:$src))>;
5534 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5535 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5537 let Predicates = [IsLE] in {
5538 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5539 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5540 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5541 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5542 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5543 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5545 let Predicates = [IsBE] in {
5546 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5547 (v2f32 (REV64v2i32 FPR64:$src))>;
5548 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5549 (v2f32 (REV32v4i16 FPR64:$src))>;
5550 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5551 (v2f32 (REV32v8i8 FPR64:$src))>;
5552 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5553 (v2f32 (REV64v2i32 FPR64:$src))>;
5554 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5555 (v2f32 (REV64v2i32 FPR64:$src))>;
5556 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5557 (v2f32 (REV64v4i16 FPR64:$src))>;
5559 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5561 let Predicates = [IsLE] in {
5562 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5563 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5564 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5565 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5566 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5567 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5568 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5570 let Predicates = [IsBE] in {
5571 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5572 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5573 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5574 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5575 (REV64v4i32 FPR128:$src), (i32 8)))>;
5576 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5577 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5578 (REV64v8i16 FPR128:$src), (i32 8)))>;
5579 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5580 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5581 (REV64v8i16 FPR128:$src), (i32 8)))>;
5582 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5583 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5584 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5585 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5586 (REV64v4i32 FPR128:$src), (i32 8)))>;
5587 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5588 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5589 (REV64v16i8 FPR128:$src), (i32 8)))>;
5592 let Predicates = [IsLE] in {
5593 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5594 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5595 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5596 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5597 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5598 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5600 let Predicates = [IsBE] in {
5601 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5602 (v2f64 (EXTv16i8 FPR128:$src,
5603 FPR128:$src, (i32 8)))>;
5604 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5605 (v2f64 (REV64v4i32 FPR128:$src))>;
5606 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5607 (v2f64 (REV64v8i16 FPR128:$src))>;
5608 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5609 (v2f64 (REV64v8i16 FPR128:$src))>;
5610 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5611 (v2f64 (REV64v16i8 FPR128:$src))>;
5612 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5613 (v2f64 (REV64v4i32 FPR128:$src))>;
5615 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5617 let Predicates = [IsLE] in {
5618 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5619 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5620 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5621 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5622 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5623 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5625 let Predicates = [IsBE] in {
5626 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5627 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5628 (REV64v4i32 FPR128:$src), (i32 8)))>;
5629 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5630 (v4f32 (REV32v8i16 FPR128:$src))>;
5631 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5632 (v4f32 (REV32v8i16 FPR128:$src))>;
5633 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5634 (v4f32 (REV32v16i8 FPR128:$src))>;
5635 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5636 (v4f32 (REV64v4i32 FPR128:$src))>;
5637 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5638 (v4f32 (REV64v4i32 FPR128:$src))>;
5640 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5642 let Predicates = [IsLE] in {
5643 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5644 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5645 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5646 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5647 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5648 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5650 let Predicates = [IsBE] in {
5651 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5652 (v2i64 (EXTv16i8 FPR128:$src,
5653 FPR128:$src, (i32 8)))>;
5654 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5655 (v2i64 (REV64v4i32 FPR128:$src))>;
5656 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5657 (v2i64 (REV64v8i16 FPR128:$src))>;
5658 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5659 (v2i64 (REV64v16i8 FPR128:$src))>;
5660 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5661 (v2i64 (REV64v4i32 FPR128:$src))>;
5662 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5663 (v2i64 (REV64v8i16 FPR128:$src))>;
5665 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5667 let Predicates = [IsLE] in {
5668 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5669 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5670 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5671 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5672 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5673 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5675 let Predicates = [IsBE] in {
5676 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5677 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5678 (REV64v4i32 FPR128:$src),
5680 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5681 (v4i32 (REV64v4i32 FPR128:$src))>;
5682 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5683 (v4i32 (REV32v8i16 FPR128:$src))>;
5684 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5685 (v4i32 (REV32v16i8 FPR128:$src))>;
5686 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5687 (v4i32 (REV64v4i32 FPR128:$src))>;
5688 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5689 (v4i32 (REV32v8i16 FPR128:$src))>;
5691 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5693 let Predicates = [IsLE] in {
5694 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5695 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5696 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5697 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5698 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5699 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5700 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5702 let Predicates = [IsBE] in {
5703 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5704 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5705 (REV64v8i16 FPR128:$src),
5707 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5708 (v8i16 (REV64v8i16 FPR128:$src))>;
5709 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5710 (v8i16 (REV32v8i16 FPR128:$src))>;
5711 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5712 (v8i16 (REV16v16i8 FPR128:$src))>;
5713 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5714 (v8i16 (REV64v8i16 FPR128:$src))>;
5715 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5716 (v8i16 (REV32v8i16 FPR128:$src))>;
5717 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5718 (v8i16 (REV32v8i16 FPR128:$src))>;
5721 let Predicates = [IsLE] in {
5722 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5723 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5724 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5725 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5726 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5727 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5728 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5730 let Predicates = [IsBE] in {
5731 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5732 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5733 (REV64v8i16 FPR128:$src),
5735 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5736 (v8f16 (REV64v8i16 FPR128:$src))>;
5737 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5738 (v8f16 (REV32v8i16 FPR128:$src))>;
5739 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5740 (v8f16 (REV64v8i16 FPR128:$src))>;
5741 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5742 (v8f16 (REV16v16i8 FPR128:$src))>;
5743 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5744 (v8f16 (REV64v8i16 FPR128:$src))>;
5745 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5746 (v8f16 (REV32v8i16 FPR128:$src))>;
5749 let Predicates = [IsLE] in {
5750 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5751 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5752 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5753 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5754 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5755 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5756 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5758 let Predicates = [IsBE] in {
5759 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5760 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5761 (REV64v16i8 FPR128:$src),
5763 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5764 (v16i8 (REV64v16i8 FPR128:$src))>;
5765 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5766 (v16i8 (REV32v16i8 FPR128:$src))>;
5767 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5768 (v16i8 (REV16v16i8 FPR128:$src))>;
5769 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5770 (v16i8 (REV64v16i8 FPR128:$src))>;
5771 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5772 (v16i8 (REV32v16i8 FPR128:$src))>;
5773 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5774 (v16i8 (REV16v16i8 FPR128:$src))>;
5777 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5778 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5779 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5780 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5781 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5782 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5783 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5784 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5786 // A 64-bit subvector insert to the first 128-bit vector position
5787 // is a subregister copy that needs no instruction.
5788 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5789 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5790 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5791 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5792 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5793 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5794 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5795 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5796 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5797 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5798 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5799 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5800 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5801 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5803 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5805 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5806 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5807 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5808 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5809 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5810 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5811 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5812 // so we match on v4f32 here, not v2f32. This will also catch adding
5813 // the low two lanes of a true v4f32 vector.
5814 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5815 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5816 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5818 // Scalar 64-bit shifts in FPR64 registers.
5819 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5820 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5821 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5822 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5823 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5824 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5825 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5826 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5828 // Patterns for nontemporal/no-allocate stores.
5829 // We have to resort to tricks to turn a single-input store into a store pair,
5830 // because there is no single-input nontemporal store, only STNP.
5831 let Predicates = [IsLE] in {
5832 let AddedComplexity = 15 in {
5833 class NTStore128Pat<ValueType VT> :
5834 Pat<(nontemporalstore (VT FPR128:$Rt),
5835 (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
5836 (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub),
5837 (CPYi64 FPR128:$Rt, (i64 1)),
5838 GPR64sp:$Rn, simm7s8:$offset)>;
5840 def : NTStore128Pat<v2i64>;
5841 def : NTStore128Pat<v4i32>;
5842 def : NTStore128Pat<v8i16>;
5843 def : NTStore128Pat<v16i8>;
5845 class NTStore64Pat<ValueType VT> :
5846 Pat<(nontemporalstore (VT FPR64:$Rt),
5847 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
5848 (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub),
5849 (CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)),
5850 GPR64sp:$Rn, simm7s4:$offset)>;
5852 // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64?
5853 def : NTStore64Pat<v1f64>;
5854 def : NTStore64Pat<v1i64>;
5855 def : NTStore64Pat<v2i32>;
5856 def : NTStore64Pat<v4i16>;
5857 def : NTStore64Pat<v8i8>;
5859 def : Pat<(nontemporalstore GPR64:$Rt,
5860 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
5861 (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32),
5862 (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 0, 31), sub_32),
5863 GPR64sp:$Rn, simm7s4:$offset)>;
5864 } // AddedComplexity=10
5865 } // Predicates = [IsLE]
5867 // Tail call return handling. These are all compiler pseudo-instructions,
5868 // so no encoding information or anything like that.
5869 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5870 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5871 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5874 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5875 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5876 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5877 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5878 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5879 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5881 include "AArch64InstrAtomics.td"