1 //===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 scalar instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "AArch64InstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Target-specific ISD nodes and profiles
18 //===----------------------------------------------------------------------===//
20 def SDT_A64ret : SDTypeProfile<0, 0, []>;
21 def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
25 // (ins NZCV, Condition, Dest)
26 def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;
27 def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>;
29 // (outs Result), (ins NZCV, IfTrue, IfFalse, Condition)
30 def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>,
33 def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>;
35 // (outs NZCV), (ins LHS, RHS, Condition)
36 def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
38 def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>;
41 // (outs GPR64), (ins)
42 def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
44 // A64 compares don't care about the cond really (they set all flags) so a
45 // simple binary operator is useful.
46 def A64cmp : PatFrag<(ops node:$lhs, node:$rhs),
47 (A64setcc node:$lhs, node:$rhs, cond)>;
50 // When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN
51 // instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C
52 // and V flags can be set differently by this operation. It comes down to
53 // whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are
54 // then everything is fine. If not then the optimization is wrong. Thus general
55 // comparisons are only valid if op2 != 0.
57 // So, finally, the only LLVM-native comparisons that don't mention C and V are
58 // SETEQ and SETNE. They're the only ones we can safely use CMN for in the
59 // absence of information about op2.
60 def equality_cond : PatLeaf<(cond), [{
61 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE;
64 def A64cmn : PatFrag<(ops node:$lhs, node:$rhs),
65 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>;
67 // There are two layers of indirection here, driven by the following
69 // + TableGen does not know CodeModel or Reloc so that decision should be
70 // made for a variable/address at ISelLowering.
71 // + The output of ISelLowering should be selectable (hence the Wrapper,
72 // rather than a bare target opcode)
73 def SDTAArch64Wrapper : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
78 def A64WrapperSmall : SDNode<"AArch64ISD::WrapperSmall", SDTAArch64Wrapper>;
81 def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
82 def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad,
86 // (A64BFI LHS, RHS, LSB, Width)
87 def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
92 def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>;
94 // (A64EXTR HiReg, LoReg, LSB)
95 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
97 def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
99 // (A64[SU]BFX Field, ImmR, ImmS).
101 // Note that ImmR and ImmS are already encoded for the actual instructions. The
102 // more natural LSB and Width mix together to form ImmR and ImmS, something
103 // which TableGen can't handle.
104 def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
105 def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>;
107 def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
109 //===----------------------------------------------------------------------===//
110 // Call sequence pseudo-instructions
111 //===----------------------------------------------------------------------===//
114 def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
115 def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
118 def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call,
119 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
121 // The TLSDESCCALL node is a variant call which goes to an indirectly calculated
122 // destination but needs a relocation against a fixed symbol. As such it has two
123 // certain operands: the callee and the relocated variable.
125 // The TLS ABI only allows it to be selected to a BLR instructin (with
126 // appropriate relocation).
127 def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
129 def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
130 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
134 def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
135 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart,
136 [SDNPHasChain, SDNPOutGlue]>;
138 def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>;
139 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 // These pseudo-instructions have special semantics by virtue of being passed to
145 // the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by
146 // LowerCall to (in our case) tell the back-end about stack adjustments for
147 // arguments passed on the stack. Here we select those markers to
148 // pseudo-instructions which explicitly set the stack, and finally in the
149 // RegisterInfo we convert them to a true stack adjustment.
150 let Defs = [XSP], Uses = [XSP] in {
151 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
152 [(AArch64callseq_start timm:$amt)]>;
154 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2),
155 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
158 //===----------------------------------------------------------------------===//
159 // Atomic operation pseudo-instructions
160 //===----------------------------------------------------------------------===//
162 let usesCustomInserter = 1, Defs = [NZCV] in {
163 multiclass AtomicSizes<string opname> {
164 def _I8 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
165 [(set GPR32:$dst, (!cast<SDNode>(opname # "_8") GPR64:$ptr, GPR32:$incr))]>;
166 def _I16 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
167 [(set GPR32:$dst, (!cast<SDNode>(opname # "_16") GPR64:$ptr, GPR32:$incr))]>;
168 def _I32 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
169 [(set GPR32:$dst, (!cast<SDNode>(opname # "_32") GPR64:$ptr, GPR32:$incr))]>;
170 def _I64 : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$incr),
171 [(set GPR64:$dst, (!cast<SDNode>(opname # "_64") GPR64:$ptr, GPR64:$incr))]>;
175 defm ATOMIC_LOAD_ADD : AtomicSizes<"atomic_load_add">;
176 defm ATOMIC_LOAD_SUB : AtomicSizes<"atomic_load_sub">;
177 defm ATOMIC_LOAD_AND : AtomicSizes<"atomic_load_and">;
178 defm ATOMIC_LOAD_OR : AtomicSizes<"atomic_load_or">;
179 defm ATOMIC_LOAD_XOR : AtomicSizes<"atomic_load_xor">;
180 defm ATOMIC_LOAD_NAND : AtomicSizes<"atomic_load_nand">;
181 defm ATOMIC_LOAD_MIN : AtomicSizes<"atomic_load_min">;
182 defm ATOMIC_LOAD_MAX : AtomicSizes<"atomic_load_max">;
183 defm ATOMIC_LOAD_UMIN : AtomicSizes<"atomic_load_umin">;
184 defm ATOMIC_LOAD_UMAX : AtomicSizes<"atomic_load_umax">;
185 defm ATOMIC_SWAP : AtomicSizes<"atomic_swap">;
187 let usesCustomInserter = 1, Defs = [NZCV] in {
188 def ATOMIC_CMP_SWAP_I8
189 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
191 (atomic_cmp_swap_8 GPR64:$ptr, GPR32:$old, GPR32:$new))]>;
192 def ATOMIC_CMP_SWAP_I16
193 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
195 (atomic_cmp_swap_16 GPR64:$ptr, GPR32:$old, GPR32:$new))]>;
196 def ATOMIC_CMP_SWAP_I32
197 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new),
199 (atomic_cmp_swap_32 GPR64:$ptr, GPR32:$old, GPR32:$new))]>;
200 def ATOMIC_CMP_SWAP_I64
201 : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$old, GPR64:$new),
203 (atomic_cmp_swap_64 GPR64:$ptr, GPR64:$old, GPR64:$new))]>;
206 //===----------------------------------------------------------------------===//
207 // Add-subtract (extended register) instructions
208 //===----------------------------------------------------------------------===//
209 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP
211 // The RHS of these operations is conceptually a sign/zero-extended
212 // register, optionally shifted left by 1-4. The extension can be a
213 // NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but
214 // must be specified with one exception:
216 // If one of the registers is sp/wsp then LSL is an alias for UXTW in
217 // 32-bit instructions and UXTX in 64-bit versions, the shift amount
218 // is not optional in that case (but can explicitly be 0), and the
219 // entire suffix can be skipped (e.g. "add sp, x3, x2").
221 multiclass extend_operands<string PREFIX, string Diag> {
222 def _asmoperand : AsmOperandClass {
224 let RenderMethod = "addRegExtendOperands";
225 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
226 let DiagnosticType = "AddSubRegExtend" # Diag;
229 def _operand : Operand<i64>,
230 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
231 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
232 let DecoderMethod = "DecodeRegExtendOperand";
233 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
237 defm UXTB : extend_operands<"UXTB", "Small">;
238 defm UXTH : extend_operands<"UXTH", "Small">;
239 defm UXTW : extend_operands<"UXTW", "Small">;
240 defm UXTX : extend_operands<"UXTX", "Large">;
241 defm SXTB : extend_operands<"SXTB", "Small">;
242 defm SXTH : extend_operands<"SXTH", "Small">;
243 defm SXTW : extend_operands<"SXTW", "Small">;
244 defm SXTX : extend_operands<"SXTX", "Large">;
246 def LSL_extasmoperand : AsmOperandClass {
247 let Name = "RegExtendLSL";
248 let RenderMethod = "addRegExtendOperands";
249 let DiagnosticType = "AddSubRegExtendLarge";
252 def LSL_extoperand : Operand<i64> {
253 let ParserMatchClass = LSL_extasmoperand;
257 // The patterns for various sign-extensions are a little ugly and
258 // non-uniform because everything has already been promoted to the
259 // legal i64 and i32 types. We'll wrap the various variants up in a
260 // class for use later.
262 dag uxtb; dag uxth; dag uxtw; dag uxtx;
263 dag sxtb; dag sxth; dag sxtw; dag sxtx;
266 def extends_to_i64 : extend_types {
267 let uxtb = (and (anyext GPR32:$Rm), 255);
268 let uxth = (and (anyext GPR32:$Rm), 65535);
269 let uxtw = (zext GPR32:$Rm);
270 let uxtx = (i64 GPR64:$Rm);
272 let sxtb = (sext_inreg (anyext GPR32:$Rm), i8);
273 let sxth = (sext_inreg (anyext GPR32:$Rm), i16);
274 let sxtw = (sext GPR32:$Rm);
275 let sxtx = (i64 GPR64:$Rm);
279 def extends_to_i32 : extend_types {
280 let uxtb = (and GPR32:$Rm, 255);
281 let uxth = (and GPR32:$Rm, 65535);
282 let uxtw = (i32 GPR32:$Rm);
283 let uxtx = (i32 GPR32:$Rm);
285 let sxtb = (sext_inreg GPR32:$Rm, i8);
286 let sxth = (sext_inreg GPR32:$Rm, i16);
287 let sxtw = (i32 GPR32:$Rm);
288 let sxtx = (i32 GPR32:$Rm);
291 // Now, six of the extensions supported are easy and uniform: if the source size
292 // is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate
293 // those instructions in one block.
295 // The uxtx/sxtx could potentially be merged in, but three facts dissuaded me:
296 // + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would
298 // + Patterns are very different as well.
299 // + Passing different registers would be ugly (more fields in extend_types
300 // would probably be the best option).
301 multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
302 SDPatternOperator opfrag,
303 dag outs, extend_types exts, RegisterClass GPRsp> {
304 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
306 (ins GPRsp:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
307 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
308 [(opfrag GPRsp:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
310 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
312 (ins GPRsp:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
313 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
314 [(opfrag GPRsp:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
316 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
318 (ins GPRsp:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
319 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
320 [(opfrag GPRsp:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
323 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
325 (ins GPRsp:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
326 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
327 [(opfrag GPRsp:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
329 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
331 (ins GPRsp:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
332 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
333 [(opfrag GPRsp:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
335 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
337 (ins GPRsp:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
338 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
339 [(opfrag GPRsp:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
343 // These two could be merge in with the above, but their patterns aren't really
344 // necessary and the naming-scheme would necessarily break:
345 multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
347 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
349 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
350 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
351 [(opfrag GPR64xsp:$Rn, (shl GPR64:$Rm, UXTX_operand:$Imm3))],
354 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
356 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
357 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
358 [/* No Pattern: same as uxtx */],
362 multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
363 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
365 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
366 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
367 [/* No pattern: probably same as uxtw */],
370 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
372 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
373 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
374 [/* No Pattern: probably same as uxtw */],
378 class SetRD<RegisterClass RC, SDPatternOperator op>
379 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>;
380 class SetNZCV<SDPatternOperator op>
381 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
383 defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
384 (outs GPR64xsp:$Rd), extends_to_i64, GPR64xsp>,
385 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
386 (outs GPR64xsp:$Rd)>;
387 defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>,
388 (outs GPR32wsp:$Rd), extends_to_i32, GPR32wsp>,
389 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ",
390 (outs GPR32wsp:$Rd)>;
391 defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
392 (outs GPR64xsp:$Rd), extends_to_i64, GPR64xsp>,
393 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
394 (outs GPR64xsp:$Rd)>;
395 defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>,
396 (outs GPR32wsp:$Rd), extends_to_i32, GPR32wsp>,
397 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ",
398 (outs GPR32wsp:$Rd)>;
400 let Defs = [NZCV] in {
401 defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
402 (outs GPR64:$Rd), extends_to_i64, GPR64xsp>,
403 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
405 defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>,
406 (outs GPR32:$Rd), extends_to_i32, GPR32wsp>,
407 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ",
409 defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
410 (outs GPR64:$Rd), extends_to_i64, GPR64xsp>,
411 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
413 defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
414 (outs GPR32:$Rd), extends_to_i32, GPR32wsp>,
415 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ",
419 let Rd = 0b11111, isCompare = 1 in {
420 defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
421 (outs), extends_to_i64, GPR64xsp>,
422 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
423 defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
424 (outs), extends_to_i32, GPR32wsp>,
425 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
426 defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
427 (outs), extends_to_i64, GPR64xsp>,
428 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>;
429 defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
430 (outs), extends_to_i32, GPR32wsp>,
431 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>;
435 // Now patterns for the operation without a shift being needed. No patterns are
436 // created for uxtx/sxtx since they're non-uniform and it's expected that
437 // add/sub (shifted register) will handle those cases anyway.
438 multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
439 RegisterClass GPRsp, extend_types exts> {
440 def : Pat<(nodeop GPRsp:$Rn, exts.uxtb),
441 (!cast<Instruction>(prefix # "w_uxtb") GPRsp:$Rn, GPR32:$Rm, 0)>;
442 def : Pat<(nodeop GPRsp:$Rn, exts.uxth),
443 (!cast<Instruction>(prefix # "w_uxth") GPRsp:$Rn, GPR32:$Rm, 0)>;
444 def : Pat<(nodeop GPRsp:$Rn, exts.uxtw),
445 (!cast<Instruction>(prefix # "w_uxtw") GPRsp:$Rn, GPR32:$Rm, 0)>;
447 def : Pat<(nodeop GPRsp:$Rn, exts.sxtb),
448 (!cast<Instruction>(prefix # "w_sxtb") GPRsp:$Rn, GPR32:$Rm, 0)>;
449 def : Pat<(nodeop GPRsp:$Rn, exts.sxth),
450 (!cast<Instruction>(prefix # "w_sxth") GPRsp:$Rn, GPR32:$Rm, 0)>;
451 def : Pat<(nodeop GPRsp:$Rn, exts.sxtw),
452 (!cast<Instruction>(prefix # "w_sxtw") GPRsp:$Rn, GPR32:$Rm, 0)>;
455 defm : addsubext_noshift_patterns<"ADDxx", add, GPR64xsp, extends_to_i64>;
456 defm : addsubext_noshift_patterns<"ADDww", add, GPR32wsp, extends_to_i32>;
457 defm : addsubext_noshift_patterns<"SUBxx", sub, GPR64xsp, extends_to_i64>;
458 defm : addsubext_noshift_patterns<"SUBww", sub, GPR32wsp, extends_to_i32>;
460 defm : addsubext_noshift_patterns<"CMNx", A64cmn, GPR64xsp, extends_to_i64>;
461 defm : addsubext_noshift_patterns<"CMNw", A64cmn, GPR32wsp, extends_to_i32>;
462 defm : addsubext_noshift_patterns<"CMPx", A64cmp, GPR64xsp, extends_to_i64>;
463 defm : addsubext_noshift_patterns<"CMPw", A64cmp, GPR32wsp, extends_to_i32>;
465 // An extend of "lsl #imm" is valid if and only if one of Rn and Rd is
466 // sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the
467 // operation. Also permitted in this case is complete omission of the argument,
468 // which implies "lsl #0".
469 multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
470 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
471 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
472 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
474 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"),
475 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
479 defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
480 defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
481 defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>;
482 defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>;
483 defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
484 defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
485 defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>;
486 defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>;
488 // Rd cannot be sp for flag-setting variants so only half of the aliases are
490 defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>;
491 defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>;
492 defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>;
493 defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>;
495 // CMP unfortunately has to be different because the instruction doesn't have a
497 multiclass cmp_lsl_aliases<string asmop, Instruction inst,
498 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
499 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
500 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
502 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"),
503 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
506 defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>;
507 defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>;
508 defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>;
509 defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>;
511 //===----------------------------------------------------------------------===//
512 // Add-subtract (immediate) instructions
513 //===----------------------------------------------------------------------===//
514 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV
516 // These instructions accept a 12-bit unsigned immediate, optionally shifted
517 // left by 12 bits. Official assembly format specifies a 12 bit immediate with
518 // one of "", "LSL #0", "LSL #12" supplementary operands.
520 // There are surprisingly few ways to make this work with TableGen, so this
521 // implementation has separate instructions for the "LSL #0" and "LSL #12"
524 // If the MCInst retained a single combined immediate (which could be 0x123000,
525 // for example) then both components (imm & shift) would have to be delegated to
526 // a single assembly operand. This would entail a separate operand parser
527 // (because the LSL would have to live in the same AArch64Operand as the
528 // immediate to be accessible); assembly parsing is rather complex and
529 // error-prone C++ code.
531 // By splitting the immediate, we can delegate handling this optional operand to
532 // an InstAlias. Supporting functions to generate the correct MCInst are still
533 // required, but these are essentially trivial and parsing can remain generic.
535 // Rejected plans with rationale:
536 // ------------------------------
538 // In an ideal world you'de have two first class immediate operands (in
539 // InOperandList, specifying imm12 and shift). Unfortunately this is not
540 // selectable by any means I could discover.
542 // An Instruction with two MCOperands hidden behind a single entry in
543 // InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional,
544 // but required more C++ code to handle encoding/decoding. Parsing (the intended
545 // main beneficiary) ended up equally complex because of the optional nature of
548 // Attempting to circumvent the need for a custom OperandParser above by giving
549 // InstAliases without the "lsl #0" failed. add/sub could be accommodated but
550 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands
551 // should be parsed: there was no way to accommodate an "lsl #12".
553 let ParserMethod = "ParseImmWithLSLOperand",
554 RenderMethod = "addImmWithLSLOperands" in {
555 // Derived PredicateMethod fields are different for each
556 def addsubimm_lsl0_asmoperand : AsmOperandClass {
557 let Name = "AddSubImmLSL0";
558 // If an error is reported against this operand, instruction could also be a
560 let DiagnosticType = "AddSubSecondSource";
563 def addsubimm_lsl12_asmoperand : AsmOperandClass {
564 let Name = "AddSubImmLSL12";
565 let DiagnosticType = "AddSubSecondSource";
569 def shr_12_XFORM : SDNodeXForm<imm, [{
570 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32);
573 def shr_12_neg_XFORM : SDNodeXForm<imm, [{
574 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32);
577 def neg_XFORM : SDNodeXForm<imm, [{
578 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32);
582 multiclass addsub_imm_operands<ValueType ty> {
583 let PrintMethod = "printAddSubImmLSL0Operand",
584 EncoderMethod = "getAddSubImmOpValue",
585 ParserMatchClass = addsubimm_lsl0_asmoperand in {
586 def _posimm_lsl0 : Operand<ty>,
587 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
588 def _negimm_lsl0 : Operand<ty>,
589 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }],
593 let PrintMethod = "printAddSubImmLSL12Operand",
594 EncoderMethod = "getAddSubImmOpValue",
595 ParserMatchClass = addsubimm_lsl12_asmoperand in {
596 def _posimm_lsl12 : Operand<ty>,
597 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
600 def _negimm_lsl12 : Operand<ty>,
601 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }],
606 // The add operands don't need any transformation
607 defm addsubimm_operand_i32 : addsub_imm_operands<i32>;
608 defm addsubimm_operand_i64 : addsub_imm_operands<i64>;
610 multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift,
611 string asmop, string cmpasmop,
612 Operand imm_operand, Operand cmp_imm_operand,
613 RegisterClass GPR, RegisterClass GPRsp,
615 // All registers for non-S variants allow SP
616 def _s : A64I_addsubimm<sf, op, 0b0, shift,
618 (ins GPRsp:$Rn, imm_operand:$Imm12),
619 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
621 (add GPRsp:$Rn, imm_operand:$Imm12))],
625 // S variants can read SP but would write to ZR
626 def _S : A64I_addsubimm<sf, op, 0b1, shift,
628 (ins GPRsp:$Rn, imm_operand:$Imm12),
629 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
630 [(set GPR:$Rd, (addc GPRsp:$Rn, imm_operand:$Imm12))],
635 // Note that the pattern here for ADDS is subtle. Canonically CMP
636 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to
637 // ADDS a, (-b). This is not true in general.
638 def _cmp : A64I_addsubimm<sf, op, 0b1, shift,
639 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
640 !strconcat(cmpasmop, " $Rn, $Imm12"),
642 (A64cmp GPRsp:$Rn, cmp_imm_operand:$Imm12))],
651 multiclass addsubimm_shifts<string prefix, bit sf, bit op,
652 string asmop, string cmpasmop, string operand, string cmpoperand,
653 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR> {
654 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
656 !cast<Operand>(operand # "_lsl0"),
657 !cast<Operand>(cmpoperand # "_lsl0"),
660 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01,
662 !cast<Operand>(operand # "_lsl12"),
663 !cast<Operand>(cmpoperand # "_lsl12"),
667 defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
668 "addsubimm_operand_i32_posimm",
669 "addsubimm_operand_i32_negimm",
670 GPR32, GPR32wsp, WZR>;
671 defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
672 "addsubimm_operand_i64_posimm",
673 "addsubimm_operand_i64_negimm",
674 GPR64, GPR64xsp, XZR>;
675 defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp",
676 "addsubimm_operand_i32_negimm",
677 "addsubimm_operand_i32_posimm",
678 GPR32, GPR32wsp, WZR>;
679 defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp",
680 "addsubimm_operand_i64_negimm",
681 "addsubimm_operand_i64_posimm",
682 GPR64, GPR64xsp, XZR>;
684 multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
685 def _fromsp : InstAlias<"mov $Rd, $Rn",
686 (addop GPRsp:$Rd, SP:$Rn, 0),
689 def _tosp : InstAlias<"mov $Rd, $Rn",
690 (addop SP:$Rd, GPRsp:$Rn, 0),
694 // Recall Rxsp is a RegisterClass containing *just* xsp.
695 defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>;
696 defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>;
698 //===----------------------------------------------------------------------===//
699 // Add-subtract (shifted register) instructions
700 //===----------------------------------------------------------------------===//
701 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
703 //===-------------------------------
704 // 1. The "shifed register" operands. Shared with logical insts.
705 //===-------------------------------
707 multiclass shift_operands<string prefix, string form> {
708 def _asmoperand_i32 : AsmOperandClass {
709 let Name = "Shift" # form # "i32";
710 let RenderMethod = "addShiftOperands";
711 let PredicateMethod = "isShift<A64SE::" # form # ", false>";
712 let DiagnosticType = "AddSubRegShift32";
715 // Note that the operand type is intentionally i64 because the DAGCombiner
716 // puts these into a canonical form.
717 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
719 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
720 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
721 let DecoderMethod = "Decode32BitShiftOperand";
724 def _asmoperand_i64 : AsmOperandClass {
725 let Name = "Shift" # form # "i64";
726 let RenderMethod = "addShiftOperands";
727 let PredicateMethod = "isShift<A64SE::" # form # ", true>";
728 let DiagnosticType = "AddSubRegShift64";
731 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
733 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
734 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
738 defm lsl_operand : shift_operands<"lsl_operand", "LSL">;
739 defm lsr_operand : shift_operands<"lsr_operand", "LSR">;
740 defm asr_operand : shift_operands<"asr_operand", "ASR">;
742 // Not used for add/sub, but defined here for completeness. The "logical
743 // (shifted register)" instructions *do* have an ROR variant.
744 defm ror_operand : shift_operands<"ror_operand", "ROR">;
746 //===-------------------------------
747 // 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions.
748 //===-------------------------------
750 // N.b. the commutable parameter is just !N. It will be first against the wall
751 // when the revolution comes.
752 multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
753 string asmop, SDPatternOperator opfrag, string sty,
754 RegisterClass GPR, list<Register> defs> {
755 let isCommutable = commutable, Defs = defs in {
756 def _lsl : A64I_addsubshift<sf, op, s, 0b00,
758 (ins GPR:$Rn, GPR:$Rm,
759 !cast<Operand>("lsl_operand_" # sty):$Imm6),
760 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
761 [(set GPR:$Rd, (opfrag GPR:$Rn, (shl GPR:$Rm,
762 !cast<Operand>("lsl_operand_" # sty):$Imm6))
766 def _lsr : A64I_addsubshift<sf, op, s, 0b01,
768 (ins GPR:$Rn, GPR:$Rm,
769 !cast<Operand>("lsr_operand_" # sty):$Imm6),
770 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
771 [(set GPR:$Rd, (opfrag GPR:$Rn, (srl GPR:$Rm,
772 !cast<Operand>("lsr_operand_" # sty):$Imm6))
776 def _asr : A64I_addsubshift<sf, op, s, 0b10,
778 (ins GPR:$Rn, GPR:$Rm,
779 !cast<Operand>("asr_operand_" # sty):$Imm6),
780 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
781 [(set GPR:$Rd, (opfrag GPR:$Rn, (sra GPR:$Rm,
782 !cast<Operand>("asr_operand_" # sty):$Imm6))
788 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
789 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
792 def : Pat<(opfrag GPR:$Rn, GPR:$Rm),
793 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
796 multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
797 string asmop, SDPatternOperator opfrag,
798 list<Register> defs> {
799 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
800 commutable, asmop, opfrag, "i64", GPR64, defs>;
801 defm www : addsub_shifts<prefix # "www", 0b0, op, s,
802 commutable, asmop, opfrag, "i32", GPR32, defs>;
806 defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>;
807 defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>;
809 defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>;
810 defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>;
812 //===-------------------------------
813 // 1. The NEG/NEGS aliases
814 //===-------------------------------
816 multiclass neg_alias<Instruction INST, RegisterClass GPR,
817 Register ZR, Operand shift_operand, SDNode shiftop> {
818 def : InstAlias<"neg $Rd, $Rm, $Imm6",
819 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
821 def : Pat<(sub 0, (shiftop GPR:$Rm, shift_operand:$Imm6)),
822 (INST ZR, GPR:$Rm, shift_operand:$Imm6)>;
825 defm : neg_alias<SUBwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
826 defm : neg_alias<SUBwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
827 defm : neg_alias<SUBwww_asr, GPR32, WZR, asr_operand_i32, sra>;
828 def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
829 def : Pat<(sub 0, GPR32:$Rm), (SUBwww_lsl WZR, GPR32:$Rm, 0)>;
831 defm : neg_alias<SUBxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
832 defm : neg_alias<SUBxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
833 defm : neg_alias<SUBxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
834 def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
835 def : Pat<(sub 0, GPR64:$Rm), (SUBxxx_lsl XZR, GPR64:$Rm, 0)>;
837 // NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to
839 class negs_alias<Instruction INST, RegisterClass GPR,
840 Register ZR, Operand shift_operand, SDNode shiftop>
841 : InstAlias<"negs $Rd, $Rm, $Imm6",
842 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
844 def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
845 def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
846 def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>;
847 def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
849 def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
850 def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
851 def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
852 def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
854 //===-------------------------------
855 // 1. The CMP/CMN aliases
856 //===-------------------------------
858 multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
859 string asmop, SDPatternOperator opfrag, string sty,
861 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
862 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
864 (ins GPR:$Rn, GPR:$Rm,
865 !cast<Operand>("lsl_operand_" # sty):$Imm6),
866 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
867 [(set NZCV, (opfrag GPR:$Rn, (shl GPR:$Rm,
868 !cast<Operand>("lsl_operand_" # sty):$Imm6))
872 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
874 (ins GPR:$Rn, GPR:$Rm,
875 !cast<Operand>("lsr_operand_" # sty):$Imm6),
876 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
877 [(set NZCV, (opfrag GPR:$Rn, (srl GPR:$Rm,
878 !cast<Operand>("lsr_operand_" # sty):$Imm6))
882 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
884 (ins GPR:$Rn, GPR:$Rm,
885 !cast<Operand>("asr_operand_" # sty):$Imm6),
886 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
887 [(set NZCV, (opfrag GPR:$Rn, (sra GPR:$Rm,
888 !cast<Operand>("asr_operand_" # sty):$Imm6))
894 : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
895 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
897 def : Pat<(opfrag GPR:$Rn, GPR:$Rm),
898 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
901 defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, "i32", GPR32>;
902 defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, "i64", GPR64>;
904 defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, "i32", GPR32>;
905 defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, "i64", GPR64>;
907 //===----------------------------------------------------------------------===//
908 // Add-subtract (with carry) instructions
909 //===----------------------------------------------------------------------===//
910 // Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
912 multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
913 let Uses = [NZCV] in {
914 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
915 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
916 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
919 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
920 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
921 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
926 let isCommutable = 1 in {
927 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
930 defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
932 let Defs = [NZCV] in {
933 let isCommutable = 1 in {
934 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
937 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">;
940 def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>;
941 def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
942 def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>;
943 def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
945 // Note that adde and sube can form a chain longer than two (e.g. for 256-bit
946 // addition). So the flag-setting instructions are appropriate.
947 def : Pat<(adde GPR32:$Rn, GPR32:$Rm), (ADCSwww GPR32:$Rn, GPR32:$Rm)>;
948 def : Pat<(adde GPR64:$Rn, GPR64:$Rm), (ADCSxxx GPR64:$Rn, GPR64:$Rm)>;
949 def : Pat<(sube GPR32:$Rn, GPR32:$Rm), (SBCSwww GPR32:$Rn, GPR32:$Rm)>;
950 def : Pat<(sube GPR64:$Rn, GPR64:$Rm), (SBCSxxx GPR64:$Rn, GPR64:$Rm)>;
952 //===----------------------------------------------------------------------===//
954 //===----------------------------------------------------------------------===//
955 // Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL,
958 // Because of the rather complicated nearly-overlapping aliases, the decoding of
959 // this range of instructions is handled manually. The architectural
960 // instructions are BFM, SBFM and UBFM but a disassembler should never produce
963 // In the end, the best option was to use BFM instructions for decoding under
964 // almost all circumstances, but to create aliasing *Instructions* for each of
965 // the canonical forms and specify a completely custom decoder which would
966 // substitute the correct MCInst as needed.
968 // This also simplifies instruction selection, parsing etc because the MCInsts
969 // have a shape that's closer to their use in code.
971 //===-------------------------------
972 // 1. The architectural BFM instructions
973 //===-------------------------------
975 def uimm5_asmoperand : AsmOperandClass {
977 let PredicateMethod = "isUImm<5>";
978 let RenderMethod = "addImmOperands";
979 let DiagnosticType = "UImm5";
982 def uimm6_asmoperand : AsmOperandClass {
984 let PredicateMethod = "isUImm<6>";
985 let RenderMethod = "addImmOperands";
986 let DiagnosticType = "UImm6";
989 def bitfield32_imm : Operand<i64>,
990 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
991 let ParserMatchClass = uimm5_asmoperand;
993 let DecoderMethod = "DecodeBitfield32ImmOperand";
997 def bitfield64_imm : Operand<i64>,
998 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
999 let ParserMatchClass = uimm6_asmoperand;
1001 // Default decoder works in 64-bit case: the 6-bit field can take any value.
1004 multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
1005 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1006 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1007 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1009 let DecoderMethod = "DecodeBitfieldInstruction";
1012 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1013 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1014 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1016 let DecoderMethod = "DecodeBitfieldInstruction";
1020 defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">;
1021 defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">;
1023 // BFM instructions modify the destination register rather than defining it
1026 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1027 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1028 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1029 let DecoderMethod = "DecodeBitfieldInstruction";
1030 let Constraints = "$src = $Rd";
1034 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1035 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1036 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1037 let DecoderMethod = "DecodeBitfieldInstruction";
1038 let Constraints = "$src = $Rd";
1042 //===-------------------------------
1043 // 2. Extend aliases to 64-bit dest
1044 //===-------------------------------
1046 // Unfortunately the extensions that end up as 64-bits cannot be handled by an
1047 // instruction alias: their syntax is (for example) "SXTB x0, w0", which needs
1048 // to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is
1049 // not capable of such a map as far as I'm aware
1051 // Note that these instructions are strictly more specific than the
1052 // BFM ones (in ImmR) so they can handle their own decoding.
1053 class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, string asmop,
1054 bits<6> imms, dag pattern>
1055 : A64I_bitfield<sf, opc, sf,
1056 (outs GPRDest:$Rd), (ins GPR32:$Rn),
1057 !strconcat(asmop, "\t$Rd, $Rn"),
1058 [(set GPRDest:$Rd, pattern)], NoItinerary> {
1059 let ImmR = 0b000000;
1063 // Signed extensions
1064 def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, "sxtb", 7,
1065 (sext_inreg (anyext GPR32:$Rn), i8)>;
1066 def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, "sxtb", 7,
1067 (sext_inreg GPR32:$Rn, i8)>;
1068 def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, "sxth", 15,
1069 (sext_inreg (anyext GPR32:$Rn), i16)>;
1070 def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, "sxth", 15,
1071 (sext_inreg GPR32:$Rn, i16)>;
1072 def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, "sxtw", 31, (sext GPR32:$Rn)>;
1074 // Unsigned extensions
1075 def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, "uxtb", 7,
1076 (and GPR32:$Rn, 255)>;
1077 def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, "uxth", 15,
1078 (and GPR32:$Rn, 65535)>;
1080 // The 64-bit unsigned variants are not strictly architectural but recommended
1082 let isAsmParserOnly = 1 in {
1083 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, "uxtb", 7,
1084 (and (anyext GPR32:$Rn), 255)>;
1085 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, "uxth", 15,
1086 (and (anyext GPR32:$Rn), 65535)>;
1089 // Extra patterns for when the source register is actually 64-bits
1090 // too. There's no architectural difference here, it's just LLVM
1091 // shinanigans. There's no need for equivalent zero-extension patterns
1092 // because they'll already be caught by logical (immediate) matching.
1093 def : Pat<(sext_inreg GPR64:$Rn, i8),
1094 (SXTBxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
1095 def : Pat<(sext_inreg GPR64:$Rn, i16),
1096 (SXTHxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
1097 def : Pat<(sext_inreg GPR64:$Rn, i32),
1098 (SXTWxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
1101 //===-------------------------------
1102 // 3. Aliases for ASR and LSR (the simple shifts)
1103 //===-------------------------------
1105 // These also handle their own decoding because ImmS being set makes
1106 // them take precedence over BFM.
1107 multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
1108 def wwi : A64I_bitfield<0b0, opc, 0b0,
1109 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
1110 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1111 [(set GPR32:$Rd, (opnode GPR32:$Rn, bitfield32_imm:$ImmR))],
1116 def xxi : A64I_bitfield<0b1, opc, 0b1,
1117 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
1118 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1119 [(set GPR64:$Rd, (opnode GPR64:$Rn, bitfield64_imm:$ImmR))],
1126 defm ASR : A64I_shift<0b00, "asr", sra>;
1127 defm LSR : A64I_shift<0b10, "lsr", srl>;
1129 //===-------------------------------
1130 // 4. Aliases for LSL
1131 //===-------------------------------
1133 // Unfortunately LSL and subsequent aliases are much more complicated. We need
1134 // to be able to say certain output instruction fields depend in a complex
1135 // manner on combinations of input assembly fields).
1137 // MIOperandInfo *might* have been able to do it, but at the cost of
1138 // significantly more C++ code.
1140 // N.b. contrary to usual practice these operands store the shift rather than
1141 // the machine bits in an MCInst. The complexity overhead of consistency
1142 // outweighed the benefits in this case (custom asmparser, printer and selection
1143 // vs custom encoder).
1144 def bitfield32_lsl_imm : Operand<i64>,
1145 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1146 let ParserMatchClass = uimm5_asmoperand;
1147 let EncoderMethod = "getBitfield32LSLOpValue";
1150 def bitfield64_lsl_imm : Operand<i64>,
1151 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1152 let ParserMatchClass = uimm6_asmoperand;
1153 let EncoderMethod = "getBitfield64LSLOpValue";
1156 class A64I_bitfield_lsl<bit sf, RegisterClass GPR, Operand operand>
1157 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
1158 "lsl\t$Rd, $Rn, $FullImm",
1159 [(set GPR:$Rd, (shl GPR:$Rn, operand:$FullImm))],
1162 let ImmR = FullImm{5-0};
1163 let ImmS = FullImm{11-6};
1165 // No disassembler allowed because it would overlap with BFM which does the
1167 let isAsmParserOnly = 1;
1170 def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, bitfield32_lsl_imm>;
1171 def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, bitfield64_lsl_imm>;
1173 //===-------------------------------
1174 // 5. Aliases for bitfield extract instructions
1175 //===-------------------------------
1177 def bfx32_width_asmoperand : AsmOperandClass {
1178 let Name = "BFX32Width";
1179 let PredicateMethod = "isBitfieldWidth<32>";
1180 let RenderMethod = "addBFXWidthOperands";
1181 let DiagnosticType = "Width32";
1184 def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
1185 let PrintMethod = "printBFXWidthOperand";
1186 let ParserMatchClass = bfx32_width_asmoperand;
1189 def bfx64_width_asmoperand : AsmOperandClass {
1190 let Name = "BFX64Width";
1191 let PredicateMethod = "isBitfieldWidth<64>";
1192 let RenderMethod = "addBFXWidthOperands";
1193 let DiagnosticType = "Width64";
1196 def bfx64_width : Operand<i64> {
1197 let PrintMethod = "printBFXWidthOperand";
1198 let ParserMatchClass = bfx64_width_asmoperand;
1202 multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
1203 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1204 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1205 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1206 [(set GPR32:$Rd, (op GPR32:$Rn, imm:$ImmR, imm:$ImmS))],
1208 // As above, no disassembler allowed.
1209 let isAsmParserOnly = 1;
1212 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1213 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1214 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1215 [(set GPR64:$Rd, (op GPR64:$Rn, imm:$ImmR, imm:$ImmS))],
1217 // As above, no disassembler allowed.
1218 let isAsmParserOnly = 1;
1222 defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>;
1223 defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
1225 // Again, variants based on BFM modify Rd so need it as an input too.
1226 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1227 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1228 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1229 // As above, no disassembler allowed.
1230 let isAsmParserOnly = 1;
1231 let Constraints = "$src = $Rd";
1234 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1235 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1236 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1237 // As above, no disassembler allowed.
1238 let isAsmParserOnly = 1;
1239 let Constraints = "$src = $Rd";
1242 // SBFX instructions can do a 1-instruction sign-extension of boolean values.
1243 def : Pat<(sext_inreg GPR64:$Rn, i1), (SBFXxxii GPR64:$Rn, 0, 0)>;
1244 def : Pat<(sext_inreg GPR32:$Rn, i1), (SBFXwwii GPR32:$Rn, 0, 0)>;
1245 def : Pat<(i64 (sext_inreg (anyext GPR32:$Rn), i1)),
1246 (SBFXxxii (SUBREG_TO_REG (i64 0), GPR32:$Rn, sub_32), 0, 0)>;
1248 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
1249 // use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
1250 def : Pat<(zext GPR32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii GPR32:$Rn, 0, 31),
1253 //===-------------------------------
1254 // 6. Aliases for bitfield insert instructions
1255 //===-------------------------------
1257 def bfi32_lsb_asmoperand : AsmOperandClass {
1258 let Name = "BFI32LSB";
1259 let PredicateMethod = "isUImm<5>";
1260 let RenderMethod = "addBFILSBOperands<32>";
1261 let DiagnosticType = "UImm5";
1264 def bfi32_lsb : Operand<i64>,
1265 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1266 let PrintMethod = "printBFILSBOperand<32>";
1267 let ParserMatchClass = bfi32_lsb_asmoperand;
1270 def bfi64_lsb_asmoperand : AsmOperandClass {
1271 let Name = "BFI64LSB";
1272 let PredicateMethod = "isUImm<6>";
1273 let RenderMethod = "addBFILSBOperands<64>";
1274 let DiagnosticType = "UImm6";
1277 def bfi64_lsb : Operand<i64>,
1278 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1279 let PrintMethod = "printBFILSBOperand<64>";
1280 let ParserMatchClass = bfi64_lsb_asmoperand;
1283 // Width verification is performed during conversion so width operand can be
1284 // shared between 32/64-bit cases. Still needed for the print method though
1285 // because ImmR encodes "width - 1".
1286 def bfi32_width_asmoperand : AsmOperandClass {
1287 let Name = "BFI32Width";
1288 let PredicateMethod = "isBitfieldWidth<32>";
1289 let RenderMethod = "addBFIWidthOperands";
1290 let DiagnosticType = "Width32";
1293 def bfi32_width : Operand<i64>,
1294 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
1295 let PrintMethod = "printBFIWidthOperand";
1296 let ParserMatchClass = bfi32_width_asmoperand;
1299 def bfi64_width_asmoperand : AsmOperandClass {
1300 let Name = "BFI64Width";
1301 let PredicateMethod = "isBitfieldWidth<64>";
1302 let RenderMethod = "addBFIWidthOperands";
1303 let DiagnosticType = "Width64";
1306 def bfi64_width : Operand<i64>,
1307 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
1308 let PrintMethod = "printBFIWidthOperand";
1309 let ParserMatchClass = bfi64_width_asmoperand;
1312 multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
1313 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1314 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1315 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1317 // As above, no disassembler allowed.
1318 let isAsmParserOnly = 1;
1321 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1322 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1323 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1325 // As above, no disassembler allowed.
1326 let isAsmParserOnly = 1;
1330 defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">;
1331 defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">;
1334 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1335 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1336 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1337 // As above, no disassembler allowed.
1338 let isAsmParserOnly = 1;
1339 let Constraints = "$src = $Rd";
1342 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1343 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1344 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1345 // As above, no disassembler allowed.
1346 let isAsmParserOnly = 1;
1347 let Constraints = "$src = $Rd";
1350 //===----------------------------------------------------------------------===//
1351 // Compare and branch (immediate)
1352 //===----------------------------------------------------------------------===//
1353 // Contains: CBZ, CBNZ
1355 class label_asmoperand<int width, int scale> : AsmOperandClass {
1356 let Name = "Label" # width # "_" # scale;
1357 let PredicateMethod = "isLabel<" # width # "," # scale # ">";
1358 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
1359 let DiagnosticType = "Label";
1362 def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>;
1364 // All conditional immediate branches are the same really: 19 signed bits scaled
1365 // by the instruction-size (4).
1366 def bcc_target : Operand<OtherVT> {
1367 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
1368 let ParserMatchClass = label_wid19_scal4_asmoperand;
1369 let PrintMethod = "printLabelOperand<19, 4>";
1370 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>";
1371 let OperandType = "OPERAND_PCREL";
1374 multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
1375 let isBranch = 1, isTerminator = 1 in {
1376 def x : A64I_cmpbr<0b1, op,
1378 (ins GPR64:$Rt, bcc_target:$Label),
1379 !strconcat(asmop,"\t$Rt, $Label"),
1380 [(A64br_cc (A64cmp GPR64:$Rt, 0), SETOP, bb:$Label)],
1383 def w : A64I_cmpbr<0b0, op,
1385 (ins GPR32:$Rt, bcc_target:$Label),
1386 !strconcat(asmop,"\t$Rt, $Label"),
1387 [(A64br_cc (A64cmp GPR32:$Rt, 0), SETOP, bb:$Label)],
1392 defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{
1393 return Imm == A64CC::EQ;
1395 defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{
1396 return Imm == A64CC::NE;
1399 //===----------------------------------------------------------------------===//
1400 // Conditional branch (immediate) instructions
1401 //===----------------------------------------------------------------------===//
1404 def cond_code_asmoperand : AsmOperandClass {
1405 let Name = "CondCode";
1406 let DiagnosticType = "CondCode";
1409 def cond_code : Operand<i32>, ImmLeaf<i32, [{
1410 return Imm >= 0 && Imm <= 15;
1412 let PrintMethod = "printCondCodeOperand";
1413 let ParserMatchClass = cond_code_asmoperand;
1416 def Bcc : A64I_condbr<0b0, 0b0, (outs),
1417 (ins cond_code:$Cond, bcc_target:$Label),
1418 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1422 let isTerminator = 1;
1425 //===----------------------------------------------------------------------===//
1426 // Conditional compare (immediate) instructions
1427 //===----------------------------------------------------------------------===//
1428 // Contains: CCMN, CCMP
1430 def uimm4_asmoperand : AsmOperandClass {
1432 let PredicateMethod = "isUImm<4>";
1433 let RenderMethod = "addImmOperands";
1434 let DiagnosticType = "UImm4";
1437 def uimm4 : Operand<i32> {
1438 let ParserMatchClass = uimm4_asmoperand;
1441 def uimm5 : Operand<i32> {
1442 let ParserMatchClass = uimm5_asmoperand;
1445 // The only difference between this operand and the one for instructions like
1446 // B.cc is that it's parsed manually. The other get parsed implicitly as part of
1447 // the mnemonic handling.
1448 def cond_code_op_asmoperand : AsmOperandClass {
1449 let Name = "CondCodeOp";
1450 let RenderMethod = "addCondCodeOperands";
1451 let PredicateMethod = "isCondCode";
1452 let ParserMethod = "ParseCondCodeOperand";
1453 let DiagnosticType = "CondCode";
1456 def cond_code_op : Operand<i32> {
1457 let PrintMethod = "printCondCodeOperand";
1458 let ParserMatchClass = cond_code_op_asmoperand;
1461 class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1462 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
1463 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
1464 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1469 def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">;
1470 def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">;
1471 def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">;
1472 def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">;
1474 //===----------------------------------------------------------------------===//
1475 // Conditional compare (register) instructions
1476 //===----------------------------------------------------------------------===//
1477 // Contains: CCMN, CCMP
1479 class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1480 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1,
1482 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1483 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1488 def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">;
1489 def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">;
1490 def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">;
1491 def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">;
1493 //===----------------------------------------------------------------------===//
1494 // Conditional select instructions
1495 //===----------------------------------------------------------------------===//
1496 // Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG
1498 // Condition code which is encoded as the inversion (semantically rather than
1499 // bitwise) in the instruction.
1500 def inv_cond_code_op_asmoperand : AsmOperandClass {
1501 let Name = "InvCondCodeOp";
1502 let RenderMethod = "addInvCondCodeOperands";
1503 let PredicateMethod = "isCondCode";
1504 let ParserMethod = "ParseCondCodeOperand";
1505 let DiagnosticType = "CondCode";
1508 def inv_cond_code_op : Operand<i32> {
1509 let ParserMatchClass = inv_cond_code_op_asmoperand;
1512 // Having a separate operand for the selectable use-case is debatable, but gives
1513 // consistency with cond_code.
1514 def inv_cond_XFORM : SDNodeXForm<imm, [{
1515 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue());
1516 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32);
1520 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>;
1523 multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
1524 SDPatternOperator select> {
1525 let Uses = [NZCV] in {
1526 def wwwc : A64I_condsel<0b0, op, 0b0, op2,
1528 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
1529 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1530 [(set GPR32:$Rd, (select GPR32:$Rn, GPR32:$Rm))],
1534 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
1536 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
1537 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1538 [(set GPR64:$Rd, (select GPR64:$Rn, GPR64:$Rm))],
1544 : PatFrag<(ops node:$lhs, node:$rhs),
1545 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>;
1547 class complex_select<SDPatternOperator opnode>
1548 : PatFrag<(ops node:$lhs, node:$rhs),
1549 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>;
1552 defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>;
1553 defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc",
1554 complex_select<PatFrag<(ops node:$val),
1555 (add node:$val, 1)>>>;
1556 defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>;
1557 defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>;
1559 // Now the instruction aliases, which fit nicely into LLVM's model:
1561 def : InstAlias<"cset $Rd, $Cond",
1562 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1563 def : InstAlias<"cset $Rd, $Cond",
1564 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1565 def : InstAlias<"csetm $Rd, $Cond",
1566 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1567 def : InstAlias<"csetm $Rd, $Cond",
1568 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1569 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1570 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1571 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1572 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1573 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1574 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1575 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1576 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1577 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1578 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1579 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1580 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1582 // Finally some helper patterns.
1584 // For CSET (a.k.a. zero-extension of icmp)
1585 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1586 (CSINCwwwc WZR, WZR, cond_code:$Cond)>;
1587 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1588 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>;
1590 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1591 (CSINCxxxc XZR, XZR, cond_code:$Cond)>;
1592 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1593 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>;
1595 // For CSETM (a.k.a. sign-extension of icmp)
1596 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1597 (CSINVwwwc WZR, WZR, cond_code:$Cond)>;
1598 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1599 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>;
1601 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1602 (CSINVxxxc XZR, XZR, cond_code:$Cond)>;
1603 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1604 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>;
1606 // CINC, CINV and CNEG get dealt with automatically, which leaves the issue of
1607 // commutativity. The instructions are to complex for isCommutable to be used,
1608 // so we have to create the patterns manually:
1610 // No commutable pattern for CSEL since the commuted version is isomorphic.
1613 def :Pat<(A64select_cc NZCV, (add GPR32:$Rm, 1), GPR32:$Rn,
1614 inv_cond_code:$Cond),
1615 (CSINCwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
1616 def :Pat<(A64select_cc NZCV, (add GPR64:$Rm, 1), GPR64:$Rn,
1617 inv_cond_code:$Cond),
1618 (CSINCxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
1621 def :Pat<(A64select_cc NZCV, (not GPR32:$Rm), GPR32:$Rn, inv_cond_code:$Cond),
1622 (CSINVwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
1623 def :Pat<(A64select_cc NZCV, (not GPR64:$Rm), GPR64:$Rn, inv_cond_code:$Cond),
1624 (CSINVxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
1627 def :Pat<(A64select_cc NZCV, (ineg GPR32:$Rm), GPR32:$Rn, inv_cond_code:$Cond),
1628 (CSNEGwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
1629 def :Pat<(A64select_cc NZCV, (ineg GPR64:$Rm), GPR64:$Rn, inv_cond_code:$Cond),
1630 (CSNEGxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
1632 //===----------------------------------------------------------------------===//
1633 // Data Processing (1 source) instructions
1634 //===----------------------------------------------------------------------===//
1635 // Contains: RBIT, REV16, REV, REV32, CLZ, CLS.
1637 // We define an unary operator which always fails. We will use this to
1638 // define unary operators that cannot be matched.
1640 class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop,
1641 list<dag> patterns, RegisterClass GPRrc,
1642 InstrItinClass itin>:
1647 !strconcat(asmop, "\t$Rd, $Rn"),
1653 multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
1654 let hasSideEffects = 0 in {
1655 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>;
1656 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>;
1660 defm RBIT : A64I_dp_1src<0b000000, "rbit">;
1661 defm CLS : A64I_dp_1src<0b000101, "cls">;
1662 defm CLZ : A64I_dp_1src<0b000100, "clz">;
1664 def : Pat<(ctlz GPR32:$Rn), (CLZww GPR32:$Rn)>;
1665 def : Pat<(ctlz GPR64:$Rn), (CLZxx GPR64:$Rn)>;
1666 def : Pat<(ctlz_zero_undef GPR32:$Rn), (CLZww GPR32:$Rn)>;
1667 def : Pat<(ctlz_zero_undef GPR64:$Rn), (CLZxx GPR64:$Rn)>;
1669 def : Pat<(cttz GPR32:$Rn), (CLZww (RBITww GPR32:$Rn))>;
1670 def : Pat<(cttz GPR64:$Rn), (CLZxx (RBITxx GPR64:$Rn))>;
1671 def : Pat<(cttz_zero_undef GPR32:$Rn), (CLZww (RBITww GPR32:$Rn))>;
1672 def : Pat<(cttz_zero_undef GPR64:$Rn), (CLZxx (RBITxx GPR64:$Rn))>;
1675 def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev",
1676 [(set GPR32:$Rd, (bswap GPR32:$Rn))],
1677 GPR32, NoItinerary>;
1678 def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev",
1679 [(set GPR64:$Rd, (bswap GPR64:$Rn))],
1680 GPR64, NoItinerary>;
1681 def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32",
1682 [(set GPR64:$Rd, (bswap (rotr GPR64:$Rn, (i64 32))))],
1683 GPR64, NoItinerary>;
1684 def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16",
1685 [(set GPR32:$Rd, (bswap (rotr GPR32:$Rn, (i64 16))))],
1688 def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>;
1690 //===----------------------------------------------------------------------===//
1691 // Data Processing (2 sources) instructions
1692 //===----------------------------------------------------------------------===//
1693 // Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
1697 class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
1698 RegisterClass GPRsp,
1699 InstrItinClass itin>:
1703 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
1705 (ins GPRsp:$Rn, GPRsp:$Rm),
1709 multiclass dp_2src_crc<bit c, string asmop> {
1710 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
1711 !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
1712 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
1713 !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
1714 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
1715 !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
1716 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
1717 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
1718 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
1722 multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
1723 def www : dp_2src_impl<0b0,
1727 (op GPR32:$Rn, (i64 (zext GPR32:$Rm))))],
1730 def xxx : dp_2src_impl<0b1,
1733 [(set GPR64:$Rd, (op GPR64:$Rn, GPR64:$Rm))],
1739 multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> {
1740 def www : dp_2src_impl<0b0,
1743 [(set GPR32:$Rd, (op GPR32:$Rn, GPR32:$Rm))],
1746 def xxx : dp_2src_impl<0b1,
1749 [(set GPR64:$Rd, (op GPR64:$Rn, GPR64:$Rm))],
1754 // Here we define the data processing 2 source instructions.
1755 defm CRC32 : dp_2src_crc<0b0, "crc32">;
1756 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
1758 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1759 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1761 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1762 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1763 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1764 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1766 // Extra patterns for an incoming 64-bit value for a 32-bit
1767 // operation. Since the LLVM operations are undefined (as in C) if the
1768 // RHS is out of range, it's perfectly permissible to discard the high
1769 // bits of the GPR64.
1770 def : Pat<(shl GPR32:$Rn, GPR64:$Rm),
1771 (LSLVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1772 def : Pat<(srl GPR32:$Rn, GPR64:$Rm),
1773 (LSRVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1774 def : Pat<(sra GPR32:$Rn, GPR64:$Rm),
1775 (ASRVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1776 def : Pat<(rotr GPR32:$Rn, GPR64:$Rm),
1777 (RORVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1779 // Here we define the aliases for the data processing 2 source instructions.
1780 def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">;
1781 def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">;
1782 def ASR_menmonic : MnemonicAlias<"asrv", "asr">;
1783 def ROR_menmonic : MnemonicAlias<"rorv", "ror">;
1785 //===----------------------------------------------------------------------===//
1786 // Data Processing (3 sources) instructions
1787 //===----------------------------------------------------------------------===//
1788 // Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH
1789 // + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL
1791 class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg,
1792 RegisterClass SrcReg, string asmop, dag pattern>
1793 : A64I_dp3<sf, opcode,
1794 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
1795 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1796 [(set AccReg:$Rd, pattern)], NoItinerary> {
1797 RegisterClass AccGPR = AccReg;
1798 RegisterClass SrcGPR = SrcReg;
1801 def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, GPR32, "madd",
1802 (add GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm))>;
1803 def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, GPR64, "madd",
1804 (add GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm))>;
1806 def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, GPR32, "msub",
1807 (sub GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm))>;
1808 def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, GPR64, "msub",
1809 (sub GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm))>;
1811 def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, GPR32, "smaddl",
1812 (add GPR64:$Ra, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
1813 def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, GPR32, "smsubl",
1814 (sub GPR64:$Ra, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
1816 def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, GPR32, "umaddl",
1817 (add GPR64:$Ra, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
1818 def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, GPR32, "umsubl",
1819 (sub GPR64:$Ra, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
1821 let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
1822 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
1823 (ins GPR64:$Rn, GPR64:$Rm),
1824 "umulh\t$Rd, $Rn, $Rm",
1825 [(set GPR64:$Rd, (mulhu GPR64:$Rn, GPR64:$Rm))],
1828 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
1829 (ins GPR64:$Rn, GPR64:$Rm),
1830 "smulh\t$Rd, $Rn, $Rm",
1831 [(set GPR64:$Rd, (mulhs GPR64:$Rn, GPR64:$Rm))],
1835 multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
1836 Register ZR, dag pattern> {
1837 def : InstAlias<asmop # " $Rd, $Rn, $Rm",
1838 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1840 def : Pat<pattern, (INST INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1843 defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul GPR32:$Rn, GPR32:$Rm)>;
1844 defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul GPR64:$Rn, GPR64:$Rm)>;
1846 defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR,
1847 (sub 0, (mul GPR32:$Rn, GPR32:$Rm))>;
1848 defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR,
1849 (sub 0, (mul GPR64:$Rn, GPR64:$Rm))>;
1851 defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
1852 (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm))>;
1853 defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
1854 (sub 0, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
1856 defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
1857 (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm))>;
1858 defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
1859 (sub 0, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
1862 //===----------------------------------------------------------------------===//
1863 // Exception generation
1864 //===----------------------------------------------------------------------===//
1865 // Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
1867 def uimm16_asmoperand : AsmOperandClass {
1868 let Name = "UImm16";
1869 let PredicateMethod = "isUImm<16>";
1870 let RenderMethod = "addImmOperands";
1871 let DiagnosticType = "UImm16";
1874 def uimm16 : Operand<i32> {
1875 let ParserMatchClass = uimm16_asmoperand;
1878 class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
1879 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
1880 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
1882 let isTerminator = 1;
1885 def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">;
1886 def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">;
1887 def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">;
1888 def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">;
1889 def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">;
1891 def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">;
1892 def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">;
1893 def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">;
1895 // The immediate is optional for the DCPS instructions, defaulting to 0.
1896 def : InstAlias<"dcps1", (DCPS1i 0)>;
1897 def : InstAlias<"dcps2", (DCPS2i 0)>;
1898 def : InstAlias<"dcps3", (DCPS3i 0)>;
1900 //===----------------------------------------------------------------------===//
1901 // Extract (immediate)
1902 //===----------------------------------------------------------------------===//
1903 // Contains: EXTR + alias ROR
1905 def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0,
1907 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB),
1908 "extr\t$Rd, $Rn, $Rm, $LSB",
1910 (A64Extr GPR32:$Rn, GPR32:$Rm, imm:$LSB))],
1912 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
1914 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
1915 "extr\t$Rd, $Rn, $Rm, $LSB",
1917 (A64Extr GPR64:$Rn, GPR64:$Rm, imm:$LSB))],
1920 def : InstAlias<"ror $Rd, $Rs, $LSB",
1921 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
1922 def : InstAlias<"ror $Rd, $Rs, $LSB",
1923 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>;
1925 def : Pat<(rotr GPR32:$Rn, bitfield32_imm:$LSB),
1926 (EXTRwwwi GPR32:$Rn, GPR32:$Rn, bitfield32_imm:$LSB)>;
1927 def : Pat<(rotr GPR64:$Rn, bitfield64_imm:$LSB),
1928 (EXTRxxxi GPR64:$Rn, GPR64:$Rn, bitfield64_imm:$LSB)>;
1930 //===----------------------------------------------------------------------===//
1931 // Floating-point compare instructions
1932 //===----------------------------------------------------------------------===//
1933 // Contains: FCMP, FCMPE
1935 def fpzero_asmoperand : AsmOperandClass {
1936 let Name = "FPZero";
1937 let ParserMethod = "ParseFPImmOperand";
1938 let DiagnosticType = "FPZero";
1941 def fpz32 : Operand<f32>,
1942 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
1943 let ParserMatchClass = fpzero_asmoperand;
1944 let PrintMethod = "printFPZeroOperand";
1947 def fpz64 : Operand<f64>,
1948 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
1949 let ParserMatchClass = fpzero_asmoperand;
1950 let PrintMethod = "printFPZeroOperand";
1953 multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, string asmop2,
1955 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
1956 (outs), ins, !strconcat("fcmp\t$Rn, ", asmop2),
1957 [pattern], NoItinerary> {
1961 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
1962 (outs), ins, !strconcat("fcmpe\t$Rn, ", asmop2),
1968 defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm), "$Rm",
1969 (set NZCV, (A64cmp (f32 FPR32:$Rn), FPR32:$Rm))>;
1970 defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm), "$Rm",
1971 (set NZCV, (A64cmp (f64 FPR64:$Rn), FPR64:$Rm))>;
1973 // What would be Rm should be written as 0, but anything is valid for
1974 // disassembly so we can't set the bits
1975 let PostEncoderMethod = "fixFCMPImm" in {
1976 defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Imm), "$Imm",
1977 (set NZCV, (A64cmp (f32 FPR32:$Rn), fpz32:$Imm))>;
1979 defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Imm), "$Imm",
1980 (set NZCV, (A64cmp (f64 FPR64:$Rn), fpz64:$Imm))>;
1984 //===----------------------------------------------------------------------===//
1985 // Floating-point conditional compare instructions
1986 //===----------------------------------------------------------------------===//
1987 // Contains: FCCMP, FCCMPE
1989 class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop>
1990 : A64I_fpccmp<0b0, 0b0, type, op,
1992 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1993 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1998 def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">;
1999 def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">;
2000 def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">;
2001 def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">;
2003 //===----------------------------------------------------------------------===//
2004 // Floating-point conditional select instructions
2005 //===----------------------------------------------------------------------===//
2008 let Uses = [NZCV] in {
2009 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
2010 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
2011 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2013 (simple_select (f32 FPR32:$Rn),
2018 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
2019 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond),
2020 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2022 (simple_select (f64 FPR64:$Rn),
2027 //===----------------------------------------------------------------------===//
2028 // Floating-point data-processing (1 source)
2029 //===----------------------------------------------------------------------===//
2030 // Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI].
2032 def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val),
2033 [{ (void)N; return false; }]>;
2035 // First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
2036 // syntax. Default to no pattern because most are odd enough not to have one.
2037 multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
2038 SDPatternOperator opnode = FPNoUnop> {
2039 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
2040 !strconcat(asmstr, "\t$Rd, $Rn"),
2041 [(set (f32 FPR32:$Rd), (opnode FPR32:$Rn))],
2044 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
2045 !strconcat(asmstr, "\t$Rd, $Rn"),
2046 [(set (f64 FPR64:$Rd), (opnode FPR64:$Rn))],
2050 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
2051 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
2052 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2053 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2055 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
2056 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
2057 defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>;
2058 defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>;
2059 defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">;
2060 defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>;
2061 defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>;
2063 // The FCVT instrucitons have different source and destination register-types,
2064 // but the fields are uniform everywhere a D-register (say) crops up. Package
2065 // this information in a Record.
2066 class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
2067 RegisterClass Class = rc;
2073 def FCVT16 : FCVTRegType<FPR16, 0b11, f16>;
2074 def FCVT32 : FCVTRegType<FPR32, 0b00, f32>;
2075 def FCVT64 : FCVTRegType<FPR64, 0b01, f64>;
2077 class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode>
2078 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0},
2079 {0,0,0,1, DestReg.t1, DestReg.t0},
2080 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
2082 [(set (DestReg.VT DestReg.Class:$Rd),
2083 (opnode (SrcReg.VT SrcReg.Class:$Rn)))], NoItinerary>;
2085 def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
2086 def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
2087 def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>;
2088 def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>;
2089 def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>;
2090 def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>;
2093 //===----------------------------------------------------------------------===//
2094 // Floating-point data-processing (2 sources) instructions
2095 //===----------------------------------------------------------------------===//
2096 // Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
2098 def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs),
2099 [{ (void)N; return false; }]>;
2101 multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
2102 SDPatternOperator opnode> {
2103 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
2105 (ins FPR32:$Rn, FPR32:$Rm),
2106 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2107 [(set (f32 FPR32:$Rd), (opnode FPR32:$Rn, FPR32:$Rm))],
2110 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
2112 (ins FPR64:$Rn, FPR64:$Rm),
2113 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2114 [(set (f64 FPR64:$Rd), (opnode FPR64:$Rn, FPR64:$Rm))],
2118 let isCommutable = 1 in {
2119 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2120 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
2122 // No patterns for these.
2123 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>;
2124 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>;
2125 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
2126 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
2128 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2129 PatFrag<(ops node:$lhs, node:$rhs),
2130 (fneg (fmul node:$lhs, node:$rhs))> >;
2133 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2134 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
2136 //===----------------------------------------------------------------------===//
2137 // Floating-point data-processing (3 sources) instructions
2138 //===----------------------------------------------------------------------===//
2139 // Contains: FMADD, FMSUB, FNMADD, FNMSUB
2141 def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2142 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>;
2143 def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2144 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>;
2145 def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2146 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>;
2148 class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT,
2149 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind>
2150 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd),
2151 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
2152 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
2153 [(set FPR:$Rd, (fmakind (VT FPR:$Rn), FPR:$Rm, FPR:$Ra))],
2156 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
2157 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
2158 def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>;
2159 def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>;
2161 def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>;
2162 def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>;
2163 def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>;
2164 def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>;
2166 //===----------------------------------------------------------------------===//
2167 // Floating-point <-> fixed-point conversion instructions
2168 //===----------------------------------------------------------------------===//
2169 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2171 // #1-#32 allowed, encoded as "64 - <specified imm>
2172 def fixedpos_asmoperand_i32 : AsmOperandClass {
2173 let Name = "CVTFixedPos32";
2174 let RenderMethod = "addCVTFixedPosOperands";
2175 let PredicateMethod = "isCVTFixedPos<32>";
2176 let DiagnosticType = "CVTFixedPos32";
2179 // Also encoded as "64 - <specified imm>" but #1-#64 allowed.
2180 def fixedpos_asmoperand_i64 : AsmOperandClass {
2181 let Name = "CVTFixedPos64";
2182 let RenderMethod = "addCVTFixedPosOperands";
2183 let PredicateMethod = "isCVTFixedPos<64>";
2184 let DiagnosticType = "CVTFixedPos64";
2187 // We need the cartesian product of f32/f64 i32/i64 operands for
2189 // + Selection needs to use operands of correct floating type
2190 // + Assembly parsing and decoding depend on integer width
2191 class cvtfix_i32_op<ValueType FloatVT>
2193 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
2194 let ParserMatchClass = fixedpos_asmoperand_i32;
2195 let DecoderMethod = "DecodeCVT32FixedPosOperand";
2196 let PrintMethod = "printCVTFixedPosOperand";
2199 class cvtfix_i64_op<ValueType FloatVT>
2201 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
2202 let ParserMatchClass = fixedpos_asmoperand_i64;
2203 let PrintMethod = "printCVTFixedPosOperand";
2206 // Because of the proliferation of weird operands, it's not really
2207 // worth going for a multiclass here. Oh well.
2209 class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
2210 RegisterClass GPR, RegisterClass FPR, Operand scale_op,
2211 string asmop, SDNode cvtop>
2212 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
2213 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
2214 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2215 [(set GPR:$Rd, (cvtop (fmul FPR:$Rn, scale_op:$Scale)))],
2218 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32,
2219 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
2220 def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32,
2221 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>;
2222 def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32,
2223 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>;
2224 def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32,
2225 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>;
2227 def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64,
2228 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>;
2229 def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64,
2230 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>;
2231 def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64,
2232 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>;
2233 def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64,
2234 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>;
2237 class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode,
2238 RegisterClass FPR, RegisterClass GPR, Operand scale_op,
2239 string asmop, SDNode cvtop>
2240 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode,
2241 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
2242 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2243 [(set FPR:$Rd, (fdiv (cvtop GPR:$Rn), scale_op:$Scale))],
2246 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32,
2247 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
2248 def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64,
2249 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>;
2250 def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32,
2251 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>;
2252 def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64,
2253 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>;
2254 def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32,
2255 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>;
2256 def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64,
2257 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>;
2258 def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32,
2259 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>;
2260 def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64,
2261 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>;
2263 //===----------------------------------------------------------------------===//
2264 // Floating-point <-> integer conversion instructions
2265 //===----------------------------------------------------------------------===//
2266 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2268 class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,
2269 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
2270 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
2271 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
2273 multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
2274 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
2275 GPR32, FPR32, asmop # "s">;
2276 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
2277 GPR64, FPR32, asmop # "s">;
2278 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
2279 GPR32, FPR32, asmop # "u">;
2280 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
2281 GPR64, FPR32, asmop # "u">;
2283 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
2284 GPR32, FPR64, asmop # "s">;
2285 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
2286 GPR64, FPR64, asmop # "s">;
2287 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
2288 GPR32, FPR64, asmop # "u">;
2289 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
2290 GPR64, FPR64, asmop # "u">;
2293 defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
2294 defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">;
2295 defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">;
2296 defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">;
2297 defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">;
2299 def : Pat<(i32 (fp_to_sint FPR32:$Rn)), (FCVTZSws FPR32:$Rn)>;
2300 def : Pat<(i64 (fp_to_sint FPR32:$Rn)), (FCVTZSxs FPR32:$Rn)>;
2301 def : Pat<(i32 (fp_to_uint FPR32:$Rn)), (FCVTZUws FPR32:$Rn)>;
2302 def : Pat<(i64 (fp_to_uint FPR32:$Rn)), (FCVTZUxs FPR32:$Rn)>;
2303 def : Pat<(i32 (fp_to_sint (f64 FPR64:$Rn))), (FCVTZSwd FPR64:$Rn)>;
2304 def : Pat<(i64 (fp_to_sint (f64 FPR64:$Rn))), (FCVTZSxd FPR64:$Rn)>;
2305 def : Pat<(i32 (fp_to_uint (f64 FPR64:$Rn))), (FCVTZUwd FPR64:$Rn)>;
2306 def : Pat<(i64 (fp_to_uint (f64 FPR64:$Rn))), (FCVTZUxd FPR64:$Rn)>;
2308 multiclass A64I_inttofp<bit o0, string asmop> {
2309 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
2310 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
2311 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
2312 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>;
2315 defm S : A64I_inttofp<0b0, "scvtf">;
2316 defm U : A64I_inttofp<0b1, "ucvtf">;
2318 def : Pat<(f32 (sint_to_fp GPR32:$Rn)), (SCVTFsw GPR32:$Rn)>;
2319 def : Pat<(f32 (sint_to_fp GPR64:$Rn)), (SCVTFsx GPR64:$Rn)>;
2320 def : Pat<(f64 (sint_to_fp GPR32:$Rn)), (SCVTFdw GPR32:$Rn)>;
2321 def : Pat<(f64 (sint_to_fp GPR64:$Rn)), (SCVTFdx GPR64:$Rn)>;
2322 def : Pat<(f32 (uint_to_fp GPR32:$Rn)), (UCVTFsw GPR32:$Rn)>;
2323 def : Pat<(f32 (uint_to_fp GPR64:$Rn)), (UCVTFsx GPR64:$Rn)>;
2324 def : Pat<(f64 (uint_to_fp GPR32:$Rn)), (UCVTFdw GPR32:$Rn)>;
2325 def : Pat<(f64 (uint_to_fp GPR64:$Rn)), (UCVTFdx GPR64:$Rn)>;
2327 def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">;
2328 def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">;
2329 def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">;
2330 def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">;
2332 def : Pat<(i32 (bitconvert (f32 FPR32:$Rn))), (FMOVws FPR32:$Rn)>;
2333 def : Pat<(f32 (bitconvert (i32 GPR32:$Rn))), (FMOVsw GPR32:$Rn)>;
2334 def : Pat<(i64 (bitconvert (f64 FPR64:$Rn))), (FMOVxd FPR64:$Rn)>;
2335 def : Pat<(f64 (bitconvert (i64 GPR64:$Rn))), (FMOVdx GPR64:$Rn)>;
2337 def lane1_asmoperand : AsmOperandClass {
2339 let RenderMethod = "addImmOperands";
2340 let DiagnosticType = "Lane1";
2343 def lane1 : Operand<i32> {
2344 let ParserMatchClass = lane1_asmoperand;
2345 let PrintMethod = "printBareImmOperand";
2348 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
2349 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
2350 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2351 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
2353 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
2354 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2355 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
2358 def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]",
2359 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>;
2361 def : InstAlias<"fmov $Rd.2d[$Lane], $Rn",
2362 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>;
2364 //===----------------------------------------------------------------------===//
2365 // Floating-point immediate instructions
2366 //===----------------------------------------------------------------------===//
2369 def fpimm_asmoperand : AsmOperandClass {
2370 let Name = "FMOVImm";
2371 let ParserMethod = "ParseFPImmOperand";
2372 let DiagnosticType = "FPImm";
2375 // The MCOperand for these instructions are the encoded 8-bit values.
2376 def SDXF_fpimm : SDNodeXForm<fpimm, [{
2378 A64Imms::isFPImm(N->getValueAPF(), Imm8);
2379 return CurDAG->getTargetConstant(Imm8, MVT::i32);
2382 class fmov_operand<ValueType FT>
2384 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
2386 let PrintMethod = "printFPImmOperand";
2387 let ParserMatchClass = fpimm_asmoperand;
2390 def fmov32_operand : fmov_operand<f32>;
2391 def fmov64_operand : fmov_operand<f64>;
2393 class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT,
2394 Operand fmov_operand>
2395 : A64I_fpimm<0b0, 0b0, type, 0b00000,
2397 (ins fmov_operand:$Imm8),
2399 [(set (VT Reg:$Rd), fmov_operand:$Imm8)],
2402 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
2403 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
2405 //===----------------------------------------------------------------------===//
2406 // Load-register (literal) instructions
2407 //===----------------------------------------------------------------------===//
2408 // Contains: LDR, LDRSW, PRFM
2410 def ldrlit_label_asmoperand : AsmOperandClass {
2411 let Name = "LoadLitLabel";
2412 let RenderMethod = "addLabelOperands<19, 4>";
2413 let DiagnosticType = "Label";
2416 def ldrlit_label : Operand<i64> {
2417 let EncoderMethod = "getLoadLitLabelOpValue";
2419 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
2420 let PrintMethod = "printLabelOperand<19, 4>";
2421 let ParserMatchClass = ldrlit_label_asmoperand;
2422 let OperandType = "OPERAND_PCREL";
2425 // Various instructions take an immediate value (which can always be used),
2426 // where some numbers have a symbolic name to make things easier. These operands
2427 // and the associated functions abstract away the differences.
2428 multiclass namedimm<string prefix, string mapper> {
2429 def _asmoperand : AsmOperandClass {
2430 let Name = "NamedImm" # prefix;
2431 let PredicateMethod = "isUImm";
2432 let RenderMethod = "addImmOperands";
2433 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
2434 let DiagnosticType = "NamedImm_" # prefix;
2437 def _op : Operand<i32> {
2438 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
2439 let PrintMethod = "printNamedImmOperand<" # mapper # ">";
2440 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
2444 defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">;
2446 class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,
2447 list<dag> patterns = []>
2448 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
2449 "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
2451 let mayLoad = 1 in {
2452 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
2453 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
2456 def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
2457 def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
2459 let mayLoad = 1 in {
2460 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
2463 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0,
2465 (ins ldrlit_label:$Imm19),
2466 "ldrsw\t$Rt, $Imm19",
2469 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
2470 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
2471 "prfm\t$Rt, $Imm19",
2475 //===----------------------------------------------------------------------===//
2476 // Load-store exclusive instructions
2477 //===----------------------------------------------------------------------===//
2478 // Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB,
2479 // STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB,
2480 // STLRH, STLR, LDARB, LDARH, LDAR
2482 // Since these instructions have the undefined register bits set to 1 in
2483 // their canonical form, we need a post encoder method to set those bits
2484 // to 1 when encoding these instructions. We do this using the
2485 // fixLoadStoreExclusive function. This function has template parameters:
2487 // fixLoadStoreExclusive<int hasRs, int hasRt2>
2489 // hasRs indicates that the instruction uses the Rs field, so we won't set
2490 // it to 1 (and the same for Rt2). We don't need template parameters for
2491 // the other register fiels since Rt and Rn are always used.
2493 // This operand parses a GPR64xsp register, followed by an optional immediate
2495 def GPR64xsp0_asmoperand : AsmOperandClass {
2496 let Name = "GPR64xsp0";
2497 let PredicateMethod = "isWrappedReg";
2498 let RenderMethod = "addRegOperands";
2499 let ParserMethod = "ParseLSXAddressOperand";
2500 // Diagnostics are provided by ParserMethod
2503 def GPR64xsp0 : RegisterOperand<GPR64xsp> {
2504 let ParserMatchClass = GPR64xsp0_asmoperand;
2507 //===----------------------------------
2508 // Store-exclusive (releasing & normal)
2509 //===----------------------------------
2511 class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2512 dag ins, list<dag> pat,
2513 InstrItinClass itin> :
2514 A64I_LDSTex_stn <size,
2515 opcode{2}, 0, opcode{1}, opcode{0},
2517 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2520 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2523 multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2524 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2525 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2528 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2529 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2532 def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
2533 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2536 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
2537 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2541 defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
2542 defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">;
2544 //===----------------------------------
2546 //===----------------------------------
2548 class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2549 dag ins, list<dag> pat,
2550 InstrItinClass itin> :
2551 A64I_LDSTex_tn <size,
2552 opcode{2}, 1, opcode{1}, opcode{0},
2554 !strconcat(asm, "\t$Rt, [$Rn]"),
2557 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2560 multiclass A64I_LRex<string asmstr, bits<3> opcode> {
2561 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2562 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2565 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2566 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2569 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
2570 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2573 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
2574 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2578 defm LDXR : A64I_LRex<"ldxr", 0b000>;
2579 defm LDAXR : A64I_LRex<"ldaxr", 0b001>;
2580 defm LDAR : A64I_LRex<"ldar", 0b101>;
2582 class acquiring_load<PatFrag base>
2583 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
2584 return cast<AtomicSDNode>(N)->getOrdering() == Acquire;
2587 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
2588 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
2589 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
2590 def atomic_load_acquire_64 : acquiring_load<atomic_load_64>;
2592 def : Pat<(atomic_load_acquire_8 GPR64xsp:$Rn), (LDAR_byte GPR64xsp0:$Rn)>;
2593 def : Pat<(atomic_load_acquire_16 GPR64xsp:$Rn), (LDAR_hword GPR64xsp0:$Rn)>;
2594 def : Pat<(atomic_load_acquire_32 GPR64xsp:$Rn), (LDAR_word GPR64xsp0:$Rn)>;
2595 def : Pat<(atomic_load_acquire_64 GPR64xsp:$Rn), (LDAR_dword GPR64xsp0:$Rn)>;
2597 //===----------------------------------
2598 // Store-release (no exclusivity)
2599 //===----------------------------------
2601 class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2602 dag ins, list<dag> pat,
2603 InstrItinClass itin> :
2604 A64I_LDSTex_tn <size,
2605 opcode{2}, 0, opcode{1}, opcode{0},
2607 !strconcat(asm, "\t$Rt, [$Rn]"),
2610 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2613 class releasing_store<PatFrag base>
2614 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
2615 return cast<AtomicSDNode>(N)->getOrdering() == Release;
2618 def atomic_store_release_8 : releasing_store<atomic_store_8>;
2619 def atomic_store_release_16 : releasing_store<atomic_store_16>;
2620 def atomic_store_release_32 : releasing_store<atomic_store_32>;
2621 def atomic_store_release_64 : releasing_store<atomic_store_64>;
2623 multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
2624 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2625 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2626 [(atomic_store_release_8 GPR64xsp0:$Rn, GPR32:$Rt)],
2629 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2630 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2631 [(atomic_store_release_16 GPR64xsp0:$Rn, GPR32:$Rt)],
2634 def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
2635 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2636 [(atomic_store_release_32 GPR64xsp0:$Rn, GPR32:$Rt)],
2639 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
2640 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2641 [(atomic_store_release_64 GPR64xsp0:$Rn, GPR64:$Rt)],
2645 defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
2647 //===----------------------------------
2648 // Store-exclusive pair (releasing & normal)
2649 //===----------------------------------
2651 class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2652 dag ins, list<dag> pat,
2653 InstrItinClass itin> :
2654 A64I_LDSTex_stt2n <size,
2655 opcode{2}, 0, opcode{1}, opcode{0},
2657 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
2663 multiclass A64I_SPex<string asmstr, bits<3> opcode> {
2664 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
2665 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
2669 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
2670 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
2675 defm STXP : A64I_SPex<"stxp", 0b010>;
2676 defm STLXP : A64I_SPex<"stlxp", 0b011>;
2678 //===----------------------------------
2679 // Load-exclusive pair (acquiring & normal)
2680 //===----------------------------------
2682 class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2683 dag ins, list<dag> pat,
2684 InstrItinClass itin> :
2685 A64I_LDSTex_tt2n <size,
2686 opcode{2}, 1, opcode{1}, opcode{0},
2688 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
2691 let DecoderMethod = "DecodeLoadPairExclusiveInstruction";
2692 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
2695 multiclass A64I_LPex<string asmstr, bits<3> opcode> {
2696 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
2697 (outs GPR32:$Rt, GPR32:$Rt2),
2698 (ins GPR64xsp0:$Rn),
2701 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
2702 (outs GPR64:$Rt, GPR64:$Rt2),
2703 (ins GPR64xsp0:$Rn),
2707 defm LDXP : A64I_LPex<"ldxp", 0b010>;
2708 defm LDAXP : A64I_LPex<"ldaxp", 0b011>;
2710 //===----------------------------------------------------------------------===//
2711 // Load-store register (unscaled immediate) instructions
2712 //===----------------------------------------------------------------------===//
2713 // Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM
2717 //===----------------------------------------------------------------------===//
2718 // Load-store register (register offset) instructions
2719 //===----------------------------------------------------------------------===//
2720 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2724 //===----------------------------------------------------------------------===//
2725 // Load-store register (unsigned immediate) instructions
2726 //===----------------------------------------------------------------------===//
2727 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2731 //===----------------------------------------------------------------------===//
2732 // Load-store register (immediate post-indexed) instructions
2733 //===----------------------------------------------------------------------===//
2734 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2738 //===----------------------------------------------------------------------===//
2739 // Load-store register (immediate pre-indexed) instructions
2740 //===----------------------------------------------------------------------===//
2741 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2743 // Note that patterns are much later on in a completely separate section (they
2744 // need ADRPxi to be defined).
2746 //===-------------------------------
2747 // 1. Various operands needed
2748 //===-------------------------------
2750 //===-------------------------------
2751 // 1.1 Unsigned 12-bit immediate operands
2752 //===-------------------------------
2753 // The addressing mode for these instructions consists of an unsigned 12-bit
2754 // immediate which is scaled by the size of the memory access.
2756 // We represent this in the MC layer by two operands:
2757 // 1. A base register.
2758 // 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]"
2759 // would have '1' in this field.
2760 // This means that separate functions are needed for converting representations
2761 // which *are* aware of the intended access size.
2763 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
2764 // know the access size via some means. An isolated operand does not have this
2765 // information unless told from here, which means we need separate tablegen
2766 // Operands for each access size. This multiclass takes care of instantiating
2767 // the correct template functions in the rest of the backend.
2769 //===-------------------------------
2770 // 1.1 Unsigned 12-bit immediate operands
2771 //===-------------------------------
2773 multiclass offsets_uimm12<int MemSize, string prefix> {
2774 def uimm12_asmoperand : AsmOperandClass {
2775 let Name = "OffsetUImm12_" # MemSize;
2776 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
2777 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
2778 let DiagnosticType = "LoadStoreUImm12_" # MemSize;
2781 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which
2782 // complicates things beyond TableGen's ken.
2783 def uimm12 : Operand<i64>,
2784 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
2785 let ParserMatchClass
2786 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
2788 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">";
2789 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">";
2793 defm byte_ : offsets_uimm12<1, "byte_">;
2794 defm hword_ : offsets_uimm12<2, "hword_">;
2795 defm word_ : offsets_uimm12<4, "word_">;
2796 defm dword_ : offsets_uimm12<8, "dword_">;
2797 defm qword_ : offsets_uimm12<16, "qword_">;
2799 //===-------------------------------
2800 // 1.1 Signed 9-bit immediate operands
2801 //===-------------------------------
2803 // The MCInst is expected to store the bit-wise encoding of the value,
2804 // which amounts to lopping off the extended sign bits.
2805 def SDXF_simm9 : SDNodeXForm<imm, [{
2806 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
2809 def simm9_asmoperand : AsmOperandClass {
2811 let PredicateMethod = "isSImm<9>";
2812 let RenderMethod = "addSImmOperands<9>";
2813 let DiagnosticType = "LoadStoreSImm9";
2816 def simm9 : Operand<i64>,
2817 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
2819 let PrintMethod = "printOffsetSImm9Operand";
2820 let ParserMatchClass = simm9_asmoperand;
2824 //===-------------------------------
2825 // 1.3 Register offset extensions
2826 //===-------------------------------
2828 // The assembly-syntax for these addressing-modes is:
2829 // [<Xn|SP>, <R><m> {, <extend> {<amount>}}]
2831 // The essential semantics are:
2832 // + <amount> is a shift: #<log(transfer size)> or #0
2833 // + <R> can be W or X.
2834 // + If <R> is W, <extend> can be UXTW or SXTW
2835 // + If <R> is X, <extend> can be LSL or SXTX
2837 // The trickiest of those constraints is that Rm can be either GPR32 or GPR64,
2838 // which will need separate instructions for LLVM type-consistency. We'll also
2839 // need separate operands, of course.
2840 multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
2841 string Rm, string prefix> {
2842 def regext_asmoperand : AsmOperandClass {
2843 let Name = "AddrRegExtend_" # MemSize # "_" # Rm;
2844 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
2845 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
2846 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize;
2849 def regext : Operand<i64> {
2851 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
2853 let DecoderMethod = "DecodeAddrRegExtendOperand";
2854 let ParserMatchClass
2855 = !cast<AsmOperandClass>(prefix # regext_asmoperand);
2859 multiclass regexts_wx<int MemSize, string prefix> {
2860 // Rm is an X-register if LSL or SXTX are specified as the shift.
2861 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
2863 // Rm is a W-register if UXTW or SXTW are specified as the shift.
2864 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">;
2867 defm byte_ : regexts_wx<1, "byte_">;
2868 defm hword_ : regexts_wx<2, "hword_">;
2869 defm word_ : regexts_wx<4, "word_">;
2870 defm dword_ : regexts_wx<8, "dword_">;
2871 defm qword_ : regexts_wx<16, "qword_">;
2874 //===------------------------------
2875 // 2. The instructions themselves.
2876 //===------------------------------
2878 // We have the following instructions to implement:
2879 // | | B | H | W | X |
2880 // |-----------------+-------+-------+-------+--------|
2881 // | unsigned str | STRB | STRH | STR | STR |
2882 // | unsigned ldr | LDRB | LDRH | LDR | LDR |
2883 // | signed ldr to W | LDRSB | LDRSH | - | - |
2884 // | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) |
2886 // This will instantiate the LDR/STR instructions you'd expect to use for an
2887 // unsigned datatype (first two rows above) or floating-point register, which is
2888 // reasonably uniform across all access sizes.
2891 //===------------------------------
2892 // 2.1 Regular instructions
2893 //===------------------------------
2895 // This class covers the basic unsigned or irrelevantly-signed loads and stores,
2896 // to general-purpose and floating-point registers.
2898 class AddrParams<string prefix> {
2899 Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
2901 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
2902 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext");
2905 def byte_addrparams : AddrParams<"byte">;
2906 def hword_addrparams : AddrParams<"hword">;
2907 def word_addrparams : AddrParams<"word">;
2908 def dword_addrparams : AddrParams<"dword">;
2909 def qword_addrparams : AddrParams<"qword">;
2911 multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
2912 bit high_opc, string asmsuffix,
2913 RegisterClass GPR, AddrParams params> {
2914 // Unsigned immediate
2915 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
2916 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
2917 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2921 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
2922 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2924 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
2925 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
2926 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
2930 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
2931 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2933 // Register offset (four of these: load/store and Wm/Xm).
2934 let mayLoad = 1 in {
2935 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
2937 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
2938 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2941 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,
2943 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
2944 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2947 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
2948 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
2951 let mayStore = 1 in {
2952 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
2953 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
2954 params.regextWm:$Ext),
2955 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2958 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
2959 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
2960 params.regextXm:$Ext),
2961 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
2964 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
2965 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
2968 // Unaligned immediate
2969 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
2970 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
2971 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
2975 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
2976 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2978 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
2979 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
2980 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
2984 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
2985 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
2988 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0},
2989 (outs GPR64xsp:$Rn_wb),
2990 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
2991 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
2993 let Constraints = "$Rn = $Rn_wb";
2996 // Decoder only needed for unpredictability checking (FIXME).
2997 let DecoderMethod = "DecodeSingleIndexedInstruction";
3000 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1},
3001 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3002 (ins GPR64xsp:$Rn, simm9:$SImm9),
3003 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3006 let Constraints = "$Rn = $Rn_wb";
3007 let DecoderMethod = "DecodeSingleIndexedInstruction";
3011 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0},
3012 (outs GPR64xsp:$Rn_wb),
3013 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3014 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3016 let Constraints = "$Rn = $Rn_wb";
3019 // Decoder only needed for unpredictability checking (FIXME).
3020 let DecoderMethod = "DecodeSingleIndexedInstruction";
3023 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1},
3024 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3025 (ins GPR64xsp:$Rn, simm9:$SImm9),
3026 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3029 let Constraints = "$Rn = $Rn_wb";
3030 let DecoderMethod = "DecodeSingleIndexedInstruction";
3035 // STRB/LDRB: First define the instructions
3037 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>;
3041 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>;
3044 // STR/LDR to/from a W register
3046 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>;
3048 // STR/LDR to/from an X register
3050 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>;
3052 // STR/LDR to/from a B register
3054 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>;
3056 // STR/LDR to/from an H register
3058 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>;
3060 // STR/LDR to/from an S register
3062 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>;
3063 // STR/LDR to/from a D register
3065 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
3066 // STR/LDR to/from a Q register
3068 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
3071 //===------------------------------
3073 //===------------------------------
3075 // Byte and half-word signed loads can both go into either an X or a W register,
3076 // so it's worth factoring out. Signed word loads don't fit because there is no
3078 multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
3081 def w : A64I_LSunsigimm<size, 0b0, 0b11,
3083 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3084 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3088 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3089 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3091 def x : A64I_LSunsigimm<size, 0b0, 0b10,
3093 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3094 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3098 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3099 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3102 let mayLoad = 1 in {
3103 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
3105 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3106 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3109 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,
3111 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3112 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3115 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,
3117 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3118 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3121 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,
3123 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3124 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3127 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3128 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
3131 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3132 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn,
3136 let mayLoad = 1 in {
3138 def w_U : A64I_LSunalimm<size, 0b0, 0b11,
3140 (ins GPR64xsp:$Rn, simm9:$SImm9),
3141 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3144 def x_U : A64I_LSunalimm<size, 0b0, 0b10,
3146 (ins GPR64xsp:$Rn, simm9:$SImm9),
3147 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3152 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11,
3153 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3154 (ins GPR64xsp:$Rn, simm9:$SImm9),
3155 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3157 let Constraints = "$Rn = $Rn_wb";
3158 let DecoderMethod = "DecodeSingleIndexedInstruction";
3161 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10,
3162 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3163 (ins GPR64xsp:$Rn, simm9:$SImm9),
3164 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3166 let Constraints = "$Rn = $Rn_wb";
3167 let DecoderMethod = "DecodeSingleIndexedInstruction";
3171 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11,
3172 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3173 (ins GPR64xsp:$Rn, simm9:$SImm9),
3174 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3176 let Constraints = "$Rn = $Rn_wb";
3177 let DecoderMethod = "DecodeSingleIndexedInstruction";
3180 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10,
3181 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3182 (ins GPR64xsp:$Rn, simm9:$SImm9),
3183 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3185 let Constraints = "$Rn = $Rn_wb";
3186 let DecoderMethod = "DecodeSingleIndexedInstruction";
3188 } // let mayLoad = 1
3192 defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">;
3194 defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">;
3196 // LDRSW: load a 32-bit register, sign-extending to 64-bits.
3198 : A64I_LSunsigimm<0b10, 0b0, 0b10,
3200 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
3201 "ldrsw\t$Rt, [$Rn, $UImm12]",
3205 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3207 let mayLoad = 1 in {
3208 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
3210 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
3211 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3214 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
3216 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
3217 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3220 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
3221 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
3225 : A64I_LSunalimm<0b10, 0b0, 0b10,
3227 (ins GPR64xsp:$Rn, simm9:$SImm9),
3228 "ldursw\t$Rt, [$Rn, $SImm9]",
3232 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3235 : A64I_LSpostind<0b10, 0b0, 0b10,
3236 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3237 (ins GPR64xsp:$Rn, simm9:$SImm9),
3238 "ldrsw\t$Rt, [$Rn], $SImm9",
3241 let Constraints = "$Rn = $Rn_wb";
3242 let DecoderMethod = "DecodeSingleIndexedInstruction";
3245 def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10,
3246 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3247 (ins GPR64xsp:$Rn, simm9:$SImm9),
3248 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3251 let Constraints = "$Rn = $Rn_wb";
3252 let DecoderMethod = "DecodeSingleIndexedInstruction";
3255 //===------------------------------
3256 // 2.4 Prefetch operations
3257 //===------------------------------
3259 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
3260 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
3261 "prfm\t$Rt, [$Rn, $UImm12]",
3265 def : InstAlias<"prfm $Rt, [$Rn]",
3266 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3268 let mayLoad = 1 in {
3269 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
3270 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3271 GPR32:$Rm, dword_Wm_regext:$Ext),
3272 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3274 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
3275 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3276 GPR64:$Rm, dword_Xm_regext:$Ext),
3277 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3281 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
3282 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn,
3286 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
3287 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3288 "prfum\t$Rt, [$Rn, $SImm9]",
3292 def : InstAlias<"prfum $Rt, [$Rn]",
3293 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3295 //===----------------------------------------------------------------------===//
3296 // Load-store register (unprivileged) instructions
3297 //===----------------------------------------------------------------------===//
3298 // Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH
3300 // These instructions very much mirror the "unscaled immediate" loads, but since
3301 // there are no floating-point variants we need to split them out into their own
3302 // section to avoid instantiation of "ldtr d0, [sp]" etc.
3304 multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
3306 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
3307 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3308 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3313 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]",
3314 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3316 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
3317 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3318 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3323 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]",
3324 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3328 // STTRB/LDTRB: First define the instructions
3329 defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">;
3332 defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">;
3334 // STTR/LDTR to/from a W register
3335 defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">;
3337 // STTR/LDTR to/from an X register
3338 defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">;
3340 // Now a class for the signed instructions that can go to either 32 or 64
3342 multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
3343 let mayLoad = 1 in {
3344 def w : A64I_LSunpriv<size, 0b0, 0b11,
3346 (ins GPR64xsp:$Rn, simm9:$SImm9),
3347 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3350 def x : A64I_LSunpriv<size, 0b0, 0b10,
3352 (ins GPR64xsp:$Rn, simm9:$SImm9),
3353 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3357 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3358 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3360 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3361 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3366 defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">;
3368 defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">;
3370 // And finally LDTRSW which only goes to 64 bits.
3371 def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10,
3373 (ins GPR64xsp:$Rn, simm9:$SImm9),
3374 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3378 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3380 //===----------------------------------------------------------------------===//
3381 // Load-store register pair (offset) instructions
3382 //===----------------------------------------------------------------------===//
3386 //===----------------------------------------------------------------------===//
3387 // Load-store register pair (post-indexed) instructions
3388 //===----------------------------------------------------------------------===//
3389 // Contains: STP, LDP, LDPSW
3393 //===----------------------------------------------------------------------===//
3394 // Load-store register pair (pre-indexed) instructions
3395 //===----------------------------------------------------------------------===//
3396 // Contains: STP, LDP, LDPSW
3400 //===----------------------------------------------------------------------===//
3401 // Load-store non-temporal register pair (offset) instructions
3402 //===----------------------------------------------------------------------===//
3403 // Contains: STNP, LDNP
3406 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
3407 // know the access size via some means. An isolated operand does not have this
3408 // information unless told from here, which means we need separate tablegen
3409 // Operands for each access size. This multiclass takes care of instantiating
3410 // the correct template functions in the rest of the backend.
3412 multiclass offsets_simm7<string MemSize, string prefix> {
3413 // The bare signed 7-bit immediate is used in post-indexed instructions, but
3414 // because of the scaling performed a generic "simm7" operand isn't
3415 // appropriate here either.
3416 def simm7_asmoperand : AsmOperandClass {
3417 let Name = "SImm7_Scaled" # MemSize;
3418 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
3419 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
3420 let DiagnosticType = "LoadStoreSImm7_" # MemSize;
3423 def simm7 : Operand<i64> {
3424 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
3425 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
3429 defm word_ : offsets_simm7<"4", "word_">;
3430 defm dword_ : offsets_simm7<"8", "dword_">;
3431 defm qword_ : offsets_simm7<"16", "qword_">;
3433 multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
3434 Operand simm7, string prefix> {
3435 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
3436 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3437 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3439 let DecoderMethod = "DecodeLDSTPairInstruction";
3441 def : InstAlias<"stp $Rt, $Rt2, [$Rn]",
3442 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt,
3443 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3445 def _LDR : A64I_LSPoffset<opc, v, 0b1,
3446 (outs SomeReg:$Rt, SomeReg:$Rt2),
3447 (ins GPR64xsp:$Rn, simm7:$SImm7),
3448 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3450 let DecoderMethod = "DecodeLDSTPairInstruction";
3452 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]",
3453 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt,
3454 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3456 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0,
3457 (outs GPR64xsp:$Rn_wb),
3458 (ins SomeReg:$Rt, SomeReg:$Rt2,
3461 "stp\t$Rt, $Rt2, [$Rn], $SImm7",
3464 let Constraints = "$Rn = $Rn_wb";
3466 // Decoder only needed for unpredictability checking (FIXME).
3467 let DecoderMethod = "DecodeLDSTPairInstruction";
3470 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1,
3471 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3472 (ins GPR64xsp:$Rn, simm7:$SImm7),
3473 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3476 let Constraints = "$Rn = $Rn_wb";
3477 let DecoderMethod = "DecodeLDSTPairInstruction";
3480 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
3481 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3482 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3485 let Constraints = "$Rn = $Rn_wb";
3486 let DecoderMethod = "DecodeLDSTPairInstruction";
3489 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1,
3490 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3491 (ins GPR64xsp:$Rn, simm7:$SImm7),
3492 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3495 let Constraints = "$Rn = $Rn_wb";
3496 let DecoderMethod = "DecodeLDSTPairInstruction";
3499 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
3500 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3501 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3503 let DecoderMethod = "DecodeLDSTPairInstruction";
3505 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]",
3506 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt,
3507 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3509 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
3510 (outs SomeReg:$Rt, SomeReg:$Rt2),
3511 (ins GPR64xsp:$Rn, simm7:$SImm7),
3512 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3514 let DecoderMethod = "DecodeLDSTPairInstruction";
3516 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]",
3517 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt,
3518 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3523 defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">;
3524 defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
3525 defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
3526 defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">;
3527 defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
3531 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
3532 (outs GPR64:$Rt, GPR64:$Rt2),
3533 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3534 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3536 let DecoderMethod = "DecodeLDSTPairInstruction";
3538 def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]",
3539 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>;
3541 def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1,
3542 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3543 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3544 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
3547 let Constraints = "$Rn = $Rn_wb";
3548 let DecoderMethod = "DecodeLDSTPairInstruction";
3551 def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1,
3552 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3553 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3554 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3557 let Constraints = "$Rn = $Rn_wb";
3558 let DecoderMethod = "DecodeLDSTPairInstruction";
3561 //===----------------------------------------------------------------------===//
3562 // Logical (immediate) instructions
3563 //===----------------------------------------------------------------------===//
3564 // Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
3566 multiclass logical_imm_operands<string prefix, string note,
3567 int size, ValueType VT> {
3568 def _asmoperand : AsmOperandClass {
3569 let Name = "LogicalImm" # note # size;
3570 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
3571 let RenderMethod = "addLogicalImmOperands<" # size # ">";
3572 let DiagnosticType = "LogicalSecondSource";
3576 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
3577 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3578 let PrintMethod = "printLogicalImmOperand<" # size # ">";
3579 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
3583 defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>;
3584 defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>;
3586 // The mov versions only differ in assembly parsing, where they
3587 // exclude values representable with either MOVZ or MOVN.
3588 defm logical_imm32_mov
3589 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>;
3590 defm logical_imm64_mov
3591 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
3594 multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
3595 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
3596 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3597 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3599 (opnode GPR32:$Rn, logical_imm32_operand:$Imm))],
3602 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
3603 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3604 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3606 (opnode GPR64:$Rn, logical_imm64_operand:$Imm))],
3610 defm AND : A64I_logimmSizes<0b00, "and", and>;
3611 defm ORR : A64I_logimmSizes<0b01, "orr", or>;
3612 defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
3614 let Defs = [NZCV] in {
3615 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
3616 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3617 "ands\t$Rd, $Rn, $Imm",
3620 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
3621 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3622 "ands\t$Rd, $Rn, $Imm",
3627 def : InstAlias<"tst $Rn, $Imm",
3628 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
3629 def : InstAlias<"tst $Rn, $Imm",
3630 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
3631 def : InstAlias<"mov $Rd, $Imm",
3632 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>;
3633 def : InstAlias<"mov $Rd, $Imm",
3634 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>;
3636 //===----------------------------------------------------------------------===//
3637 // Logical (shifted register) instructions
3638 //===----------------------------------------------------------------------===//
3639 // Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV
3641 // Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS"
3642 // behaves differently for unsigned comparisons, so we defensively only allow
3643 // signed or n/a as the operand. In practice "unsigned greater than 0" is "not
3644 // equal to 0" and LLVM gives us this.
3645 def signed_cond : PatLeaf<(cond), [{
3646 return !isUnsignedIntSetCC(N->get());
3650 // These instructions share their "shift" operands with add/sub (shifted
3651 // register instructions). They are defined there.
3653 // N.b. the commutable parameter is just !N. It will be first against the wall
3654 // when the revolution comes.
3655 multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
3656 bit N, bit commutable,
3657 string asmop, SDPatternOperator opfrag, string sty,
3658 RegisterClass GPR, list<Register> defs> {
3659 let isCommutable = commutable, Defs = defs in {
3660 def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
3662 (ins GPR:$Rn, GPR:$Rm,
3663 !cast<Operand>("lsl_operand_" # sty):$Imm6),
3664 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3665 [(set GPR:$Rd, (opfrag GPR:$Rn, (shl GPR:$Rm,
3666 !cast<Operand>("lsl_operand_" # sty):$Imm6))
3670 def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
3672 (ins GPR:$Rn, GPR:$Rm,
3673 !cast<Operand>("lsr_operand_" # sty):$Imm6),
3674 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3675 [(set GPR:$Rd, (opfrag GPR:$Rn, (srl GPR:$Rm,
3676 !cast<Operand>("lsr_operand_" # sty):$Imm6))
3680 def _asr : A64I_logicalshift<sf, opc, 0b10, N,
3682 (ins GPR:$Rn, GPR:$Rm,
3683 !cast<Operand>("asr_operand_" # sty):$Imm6),
3684 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3685 [(set GPR:$Rd, (opfrag GPR:$Rn, (sra GPR:$Rm,
3686 !cast<Operand>("asr_operand_" # sty):$Imm6))
3690 def _ror : A64I_logicalshift<sf, opc, 0b11, N,
3692 (ins GPR:$Rn, GPR:$Rm,
3693 !cast<Operand>("ror_operand_" # sty):$Imm6),
3694 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3695 [(set GPR:$Rd, (opfrag GPR:$Rn, (rotr GPR:$Rm,
3696 !cast<Operand>("ror_operand_" # sty):$Imm6))
3702 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
3703 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
3706 def : Pat<(opfrag GPR:$Rn, GPR:$Rm),
3707 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3710 multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
3711 string asmop, SDPatternOperator opfrag,
3712 list<Register> defs> {
3713 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
3714 commutable, asmop, opfrag, "i64", GPR64, defs>;
3715 defm www : logical_shifts<prefix # "www", 0b0, opc, N,
3716 commutable, asmop, opfrag, "i32", GPR32, defs>;
3720 defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>;
3721 defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>;
3722 defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>;
3723 defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands",
3724 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs),
3725 [{ (void)N; return false; }]>,
3728 defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic",
3729 PatFrag<(ops node:$lhs, node:$rhs),
3730 (and node:$lhs, (not node:$rhs))>, []>;
3731 defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn",
3732 PatFrag<(ops node:$lhs, node:$rhs),
3733 (or node:$lhs, (not node:$rhs))>, []>;
3734 defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon",
3735 PatFrag<(ops node:$lhs, node:$rhs),
3736 (xor node:$lhs, (not node:$rhs))>, []>;
3737 defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics",
3738 PatFrag<(ops node:$lhs, node:$rhs),
3739 (and node:$lhs, (not node:$rhs)),
3740 [{ (void)N; return false; }]>,
3743 multiclass tst_shifts<string prefix, bit sf, string sty, RegisterClass GPR> {
3744 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
3745 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
3747 (ins GPR:$Rn, GPR:$Rm,
3748 !cast<Operand>("lsl_operand_" # sty):$Imm6),
3749 "tst\t$Rn, $Rm, $Imm6",
3750 [(set NZCV, (A64setcc (and GPR:$Rn, (shl GPR:$Rm,
3751 !cast<Operand>("lsl_operand_" # sty):$Imm6)),
3756 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
3758 (ins GPR:$Rn, GPR:$Rm,
3759 !cast<Operand>("lsr_operand_" # sty):$Imm6),
3760 "tst\t$Rn, $Rm, $Imm6",
3761 [(set NZCV, (A64setcc (and GPR:$Rn, (srl GPR:$Rm,
3762 !cast<Operand>("lsr_operand_" # sty):$Imm6)),
3766 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
3768 (ins GPR:$Rn, GPR:$Rm,
3769 !cast<Operand>("asr_operand_" # sty):$Imm6),
3770 "tst\t$Rn, $Rm, $Imm6",
3771 [(set NZCV, (A64setcc (and GPR:$Rn, (sra GPR:$Rm,
3772 !cast<Operand>("asr_operand_" # sty):$Imm6)),
3776 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
3778 (ins GPR:$Rn, GPR:$Rm,
3779 !cast<Operand>("ror_operand_" # sty):$Imm6),
3780 "tst\t$Rn, $Rm, $Imm6",
3781 [(set NZCV, (A64setcc (and GPR:$Rn, (rotr GPR:$Rm,
3782 !cast<Operand>("ror_operand_" # sty):$Imm6)),
3787 def _noshift : InstAlias<"tst $Rn, $Rm",
3788 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3790 def : Pat<(A64setcc (and GPR:$Rn, GPR:$Rm), 0, signed_cond),
3791 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3794 defm TSTxx : tst_shifts<"TSTxx", 0b1, "i64", GPR64>;
3795 defm TSTww : tst_shifts<"TSTww", 0b0, "i32", GPR32>;
3798 multiclass mvn_shifts<string prefix, bit sf, string sty, RegisterClass GPR> {
3799 let isCommutable = 0, Rn = 0b11111 in {
3800 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
3803 !cast<Operand>("lsl_operand_" # sty):$Imm6),
3804 "mvn\t$Rd, $Rm, $Imm6",
3805 [(set GPR:$Rd, (not (shl GPR:$Rm,
3806 !cast<Operand>("lsl_operand_" # sty):$Imm6)))],
3810 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
3813 !cast<Operand>("lsr_operand_" # sty):$Imm6),
3814 "mvn\t$Rd, $Rm, $Imm6",
3815 [(set GPR:$Rd, (not (srl GPR:$Rm,
3816 !cast<Operand>("lsr_operand_" # sty):$Imm6)))],
3819 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
3822 !cast<Operand>("asr_operand_" # sty):$Imm6),
3823 "mvn\t$Rd, $Rm, $Imm6",
3824 [(set GPR:$Rd, (not (sra GPR:$Rm,
3825 !cast<Operand>("asr_operand_" # sty):$Imm6)))],
3828 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
3831 !cast<Operand>("ror_operand_" # sty):$Imm6),
3832 "mvn\t$Rd, $Rm, $Imm6",
3833 [(set GPR:$Rd, (not (rotr GPR:$Rm,
3834 !cast<Operand>("lsl_operand_" # sty):$Imm6)))],
3838 def _noshift : InstAlias<"mvn $Rn, $Rm",
3839 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
3841 def : Pat<(not GPR:$Rm),
3842 (!cast<Instruction>(prefix # "_lsl") GPR:$Rm, 0)>;
3845 defm MVNxx : mvn_shifts<"MVNxx", 0b1, "i64", GPR64>;
3846 defm MVNww : mvn_shifts<"MVNww", 0b0, "i32", GPR32>;
3848 def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
3849 def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
3851 //===----------------------------------------------------------------------===//
3852 // Move wide (immediate) instructions
3853 //===----------------------------------------------------------------------===//
3854 // Contains: MOVN, MOVZ, MOVK + MOV aliases
3856 // A wide variety of different relocations are needed for variants of these
3857 // instructions, so it turns out that we need a different operand for all of
3859 multiclass movw_operands<string prefix, string instname, int width> {
3860 def _imm_asmoperand : AsmOperandClass {
3861 let Name = instname # width # "Shifted" # shift;
3862 let PredicateMethod = "is" # instname # width # "Imm";
3863 let RenderMethod = "addMoveWideImmOperands";
3864 let ParserMethod = "ParseImmWithLSLOperand";
3865 let DiagnosticType = "MOVWUImm16";
3868 def _imm : Operand<i32> {
3869 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
3870 let PrintMethod = "printMoveWideImmOperand";
3871 let EncoderMethod = "getMoveWideImmOpValue";
3872 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">";
3874 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3878 defm movn32 : movw_operands<"movn32", "MOVN", 32>;
3879 defm movn64 : movw_operands<"movn64", "MOVN", 64>;
3880 defm movz32 : movw_operands<"movz32", "MOVZ", 32>;
3881 defm movz64 : movw_operands<"movz64", "MOVZ", 64>;
3882 defm movk32 : movw_operands<"movk32", "MOVK", 32>;
3883 defm movk64 : movw_operands<"movk64", "MOVK", 64>;
3885 multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
3888 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
3889 !strconcat(asmop, "\t$Rd, $FullImm"),
3892 let UImm16 = FullImm{15-0};
3893 let Shift = FullImm{17-16};
3896 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
3897 !strconcat(asmop, "\t$Rd, $FullImm"),
3900 let UImm16 = FullImm{15-0};
3901 let Shift = FullImm{17-16};
3905 let isMoveImm = 1, isReMaterializable = 1,
3906 isAsCheapAsAMove = 1, hasSideEffects = 0 in {
3907 defm MOVN : A64I_movwSizes<0b00, "movn",
3908 (ins movn32_imm:$FullImm),
3909 (ins movn64_imm:$FullImm)>;
3911 // Some relocations are able to convert between a MOVZ and a MOVN. If these
3912 // are applied the instruction must be emitted with the corresponding bits as
3913 // 0, which means a MOVZ needs to override that bit from the default.
3914 let PostEncoderMethod = "fixMOVZ" in
3915 defm MOVZ : A64I_movwSizes<0b10, "movz",
3916 (ins movz32_imm:$FullImm),
3917 (ins movz64_imm:$FullImm)>;
3920 let Constraints = "$src = $Rd" in
3921 defm MOVK : A64I_movwSizes<0b11, "movk",
3922 (ins GPR32:$src, movk32_imm:$FullImm),
3923 (ins GPR64:$src, movk64_imm:$FullImm)>;
3926 // And now the "MOV" aliases. These also need their own operands because what
3927 // they accept is completely different to what the base instructions accept.
3928 multiclass movalias_operand<string prefix, string basename,
3929 string immpredicate, int width> {
3930 def _asmoperand : AsmOperandClass {
3931 let Name = basename # width # "MovAlias";
3933 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
3935 = "addMoveWideMovAliasOperands<" # width # ", "
3936 # "A64Imms::" # immpredicate # ">";
3939 def _movimm : Operand<i32> {
3940 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3942 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
3946 defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>;
3947 defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>;
3948 defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>;
3949 defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>;
3951 // FIXME: these are officially canonical aliases, but TableGen is too limited to
3952 // print them at the moment. I believe in this case an "AliasPredicate" method
3953 // will need to be implemented. to allow it, as well as the more generally
3954 // useful handling of non-register, non-constant operands.
3955 class movalias<Instruction INST, RegisterClass GPR, Operand operand>
3956 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>;
3958 def : movalias<MOVZwii, GPR32, movz32_movimm>;
3959 def : movalias<MOVZxii, GPR64, movz64_movimm>;
3960 def : movalias<MOVNwii, GPR32, movn32_movimm>;
3961 def : movalias<MOVNxii, GPR64, movn64_movimm>;
3963 //===----------------------------------------------------------------------===//
3964 // PC-relative addressing instructions
3965 //===----------------------------------------------------------------------===//
3966 // Contains: ADR, ADRP
3968 def adr_label : Operand<i64> {
3969 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>";
3971 // This label is a 21-bit offset from PC, unscaled
3972 let PrintMethod = "printLabelOperand<21, 1>";
3973 let ParserMatchClass = label_asmoperand<21, 1>;
3974 let OperandType = "OPERAND_PCREL";
3977 def adrp_label_asmoperand : AsmOperandClass {
3978 let Name = "AdrpLabel";
3979 let RenderMethod = "addLabelOperands<21, 4096>";
3980 let DiagnosticType = "Label";
3983 def adrp_label : Operand<i64> {
3984 let EncoderMethod = "getAdrpLabelOpValue";
3986 // This label is a 21-bit offset from PC, scaled by the page-size: 4096.
3987 let PrintMethod = "printLabelOperand<21, 4096>";
3988 let ParserMatchClass = adrp_label_asmoperand;
3989 let OperandType = "OPERAND_PCREL";
3992 let hasSideEffects = 0 in {
3993 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
3994 "adr\t$Rd, $Label", [], NoItinerary>;
3996 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
3997 "adrp\t$Rd, $Label", [], NoItinerary>;
4000 //===----------------------------------------------------------------------===//
4001 // System instructions
4002 //===----------------------------------------------------------------------===//
4003 // Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS
4004 // + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
4006 // Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
4007 def uimm3_asmoperand : AsmOperandClass {
4009 let PredicateMethod = "isUImm<3>";
4010 let RenderMethod = "addImmOperands";
4011 let DiagnosticType = "UImm3";
4014 def uimm3 : Operand<i32> {
4015 let ParserMatchClass = uimm3_asmoperand;
4018 // The HINT alias can accept a simple unsigned 7-bit immediate.
4019 def uimm7_asmoperand : AsmOperandClass {
4021 let PredicateMethod = "isUImm<7>";
4022 let RenderMethod = "addImmOperands";
4023 let DiagnosticType = "UImm7";
4026 def uimm7 : Operand<i32> {
4027 let ParserMatchClass = uimm7_asmoperand;
4030 // Multiclass namedimm is defined with the prefetch operands. Most of these fit
4031 // into the NamedImmMapper scheme well: they either accept a named operand or
4032 // any immediate under a particular value (which may be 0, implying no immediate
4034 defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">;
4035 defm isb : namedimm<"isb", "A64ISB::ISBMapper">;
4036 defm ic : namedimm<"ic", "A64IC::ICMapper">;
4037 defm dc : namedimm<"dc", "A64DC::DCMapper">;
4038 defm at : namedimm<"at", "A64AT::ATMapper">;
4039 defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">;
4041 // However, MRS and MSR are more complicated for a few reasons:
4042 // * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
4043 // implementation-defined effect
4044 // * Most registers are shared, but some are read-only or write-only.
4045 // * There is a variant of MSR which accepts the same register name (SPSel),
4046 // but which would have a different encoding.
4048 // In principle these could be resolved in with more complicated subclasses of
4049 // NamedImmMapper, however that imposes an overhead on other "named
4050 // immediates". Both in concrete terms with virtual tables and in unnecessary
4053 // The solution adopted here is to take the MRS/MSR Mappers out of the usual
4054 // hierarchy (they're not derived from NamedImmMapper) and to add logic for
4055 // their special situation.
4056 def mrs_asmoperand : AsmOperandClass {
4058 let ParserMethod = "ParseSysRegOperand";
4059 let DiagnosticType = "MRS";
4062 def mrs_op : Operand<i32> {
4063 let ParserMatchClass = mrs_asmoperand;
4064 let PrintMethod = "printMRSOperand";
4065 let DecoderMethod = "DecodeMRSOperand";
4068 def msr_asmoperand : AsmOperandClass {
4069 let Name = "MSRWithReg";
4071 // Note that SPSel is valid for both this and the pstate operands, but with
4072 // different immediate encodings. This is why these operands provide a string
4073 // AArch64Operand rather than an immediate. The overlap is small enough that
4074 // it could be resolved with hackery now, but who can say in future?
4075 let ParserMethod = "ParseSysRegOperand";
4076 let DiagnosticType = "MSR";
4079 def msr_op : Operand<i32> {
4080 let ParserMatchClass = msr_asmoperand;
4081 let PrintMethod = "printMSROperand";
4082 let DecoderMethod = "DecodeMSROperand";
4085 def pstate_asmoperand : AsmOperandClass {
4086 let Name = "MSRPState";
4087 // See comment above about parser.
4088 let ParserMethod = "ParseSysRegOperand";
4089 let DiagnosticType = "MSR";
4092 def pstate_op : Operand<i32> {
4093 let ParserMatchClass = pstate_asmoperand;
4094 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
4095 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
4098 // When <CRn> is specified, an assembler should accept something like "C4", not
4099 // the usual "#4" immediate.
4100 def CRx_asmoperand : AsmOperandClass {
4102 let PredicateMethod = "isUImm<4>";
4103 let RenderMethod = "addImmOperands";
4104 let ParserMethod = "ParseCRxOperand";
4105 // Diagnostics are handled in all cases by ParseCRxOperand.
4108 def CRx : Operand<i32> {
4109 let ParserMatchClass = CRx_asmoperand;
4110 let PrintMethod = "printCRxOperand";
4114 // Finally, we can start defining the instructions.
4116 // HINT is straightforward, with a few aliases.
4117 def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
4120 let CRm = UImm7{6-3};
4121 let Op2 = UImm7{2-0};
4129 def : InstAlias<"nop", (HINTi 0)>;
4130 def : InstAlias<"yield", (HINTi 1)>;
4131 def : InstAlias<"wfe", (HINTi 2)>;
4132 def : InstAlias<"wfi", (HINTi 3)>;
4133 def : InstAlias<"sev", (HINTi 4)>;
4134 def : InstAlias<"sevl", (HINTi 5)>;
4136 // Quite a few instructions then follow a similar pattern of fixing common
4137 // fields in the bitpattern, we'll define a helper-class for them.
4138 class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
4139 Operand operand, string asmop>
4140 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
4150 def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">;
4151 def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">;
4152 def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">;
4153 def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">;
4155 def : InstAlias<"clrex", (CLREXi 0b1111)>;
4156 def : InstAlias<"isb", (ISBi 0b1111)>;
4158 // (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP
4159 // configurations at least.
4160 def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>;
4162 // Any SYS bitpattern can be represented with a complex and opaque "SYS"
4164 def SYSiccix : A64I_system<0b0, (outs),
4165 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
4166 uimm3:$Op2, GPR64:$Rt),
4167 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
4172 // You can skip the Xt argument whether it makes sense or not for the generic
4174 def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2",
4175 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>;
4178 // But many have aliases, which obviously don't fit into
4179 class SYSalias<dag ins, string asmstring>
4180 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
4181 let isAsmParserOnly = 1;
4185 let Op1 = SysOp{13-11};
4186 let CRn = SysOp{10-7};
4187 let CRm = SysOp{6-3};
4188 let Op2 = SysOp{2-0};
4191 def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
4193 def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
4197 def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">;
4198 def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">;
4200 def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
4202 def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
4207 def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
4208 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
4209 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
4214 // The instructions themselves are rather simple for MSR and MRS.
4215 def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
4216 "msr\t$SysReg, $Rt", [], NoItinerary> {
4218 let Op0 = SysReg{15-14};
4219 let Op1 = SysReg{13-11};
4220 let CRn = SysReg{10-7};
4221 let CRm = SysReg{6-3};
4222 let Op2 = SysReg{2-0};
4225 def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
4226 "mrs\t$Rt, $SysReg", [], NoItinerary> {
4228 let Op0 = SysReg{15-14};
4229 let Op1 = SysReg{13-11};
4230 let CRn = SysReg{10-7};
4231 let CRm = SysReg{6-3};
4232 let Op2 = SysReg{2-0};
4235 def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
4236 "msr\t$PState, $CRm", [], NoItinerary> {
4240 let Op1 = PState{5-3};
4242 let Op2 = PState{2-0};
4246 //===----------------------------------------------------------------------===//
4247 // Test & branch (immediate) instructions
4248 //===----------------------------------------------------------------------===//
4249 // Contains: TBZ, TBNZ
4251 // The bit to test is a simple unsigned 6-bit immediate in the X-register
4253 def uimm6 : Operand<i64> {
4254 let ParserMatchClass = uimm6_asmoperand;
4257 def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
4259 def tbimm_target : Operand<OtherVT> {
4260 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
4262 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
4263 let PrintMethod = "printLabelOperand<14, 4>";
4264 let ParserMatchClass = label_wid14_scal4_asmoperand;
4266 let OperandType = "OPERAND_PCREL";
4269 def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>;
4270 def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>;
4272 // These instructions correspond to patterns involving "and" with a power of
4273 // two, which we need to be able to select.
4274 def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
4275 def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
4277 let isBranch = 1, isTerminator = 1 in {
4278 def TBZxii : A64I_TBimm<0b0, (outs),
4279 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4280 "tbz\t$Rt, $Imm, $Label",
4281 [(A64br_cc (A64cmp (and GPR64:$Rt, tstb64_pat:$Imm), 0),
4285 def TBNZxii : A64I_TBimm<0b1, (outs),
4286 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4287 "tbnz\t$Rt, $Imm, $Label",
4288 [(A64br_cc (A64cmp (and GPR64:$Rt, tstb64_pat:$Imm), 0),
4293 // Note, these instructions overlap with the above 64-bit patterns. This is
4294 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both
4295 // do the same thing and are both permitted assembly. They also both have
4296 // sensible DAG patterns.
4297 def TBZwii : A64I_TBimm<0b0, (outs),
4298 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4299 "tbz\t$Rt, $Imm, $Label",
4300 [(A64br_cc (A64cmp (and GPR32:$Rt, tstb32_pat:$Imm), 0),
4306 def TBNZwii : A64I_TBimm<0b1, (outs),
4307 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4308 "tbnz\t$Rt, $Imm, $Label",
4309 [(A64br_cc (A64cmp (and GPR32:$Rt, tstb32_pat:$Imm), 0),
4316 //===----------------------------------------------------------------------===//
4317 // Unconditional branch (immediate) instructions
4318 //===----------------------------------------------------------------------===//
4321 def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
4323 def bimm_target : Operand<OtherVT> {
4324 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
4326 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4327 let PrintMethod = "printLabelOperand<26, 4>";
4328 let ParserMatchClass = label_wid26_scal4_asmoperand;
4330 let OperandType = "OPERAND_PCREL";
4333 def blimm_target : Operand<i64> {
4334 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
4336 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4337 let PrintMethod = "printLabelOperand<26, 4>";
4338 let ParserMatchClass = label_wid26_scal4_asmoperand;
4340 let OperandType = "OPERAND_PCREL";
4343 class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type>
4344 : A64I_Bimm<op, (outs), (ins lbl_type:$Label),
4345 !strconcat(asmop, "\t$Label"), patterns,
4348 let isBranch = 1 in {
4349 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
4350 let isTerminator = 1;
4354 def BLimm : A64I_BimmImpl<0b1, "bl",
4355 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4361 def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>;
4363 //===----------------------------------------------------------------------===//
4364 // Unconditional branch (register) instructions
4365 //===----------------------------------------------------------------------===//
4366 // Contains: BR, BLR, RET, ERET, DRP.
4368 // Most of the notional opcode fields in the A64I_Breg format are fixed in A64
4370 class A64I_BregImpl<bits<4> opc,
4371 dag outs, dag ins, string asmstr, list<dag> patterns,
4372 InstrItinClass itin = NoItinerary>
4373 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
4374 outs, ins, asmstr, patterns, itin> {
4376 let isIndirectBranch = 1;
4379 // Note that these are not marked isCall or isReturn because as far as LLVM is
4380 // concerned they're not. "ret" is just another jump unless it has been selected
4381 // by LLVM as the function's return.
4383 let isBranch = 1 in {
4384 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
4385 "br\t$Rn", [(brind GPR64:$Rn)]> {
4387 let isTerminator = 1;
4390 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4391 "blr\t$Rn", [(AArch64Call GPR64:$Rn)]> {
4397 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
4400 let isTerminator = 1;
4404 // Create a separate pseudo-instruction for codegen to use so that we don't
4405 // flag x30 as used in every function. It'll be restored before the RET by the
4406 // epilogue if it's legitimately used.
4407 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
4408 let isTerminator = 1;
4413 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
4416 let isTerminator = 1;
4420 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
4426 def RETAlias : InstAlias<"ret", (RETx X30)>;
4429 //===----------------------------------------------------------------------===//
4430 // Address generation patterns
4431 //===----------------------------------------------------------------------===//
4433 // Primary method of address generation for the small/absolute memory model is
4434 // an ADRP/ADR pair:
4435 // ADRP x0, some_variable
4436 // ADD x0, x0, #:lo12:some_variable
4438 // The load/store elision of the ADD is accomplished when selecting
4439 // addressing-modes. This just mops up the cases where that doesn't work and we
4440 // really need an address in some register.
4442 // This wrapper applies a LO12 modifier to the address. Otherwise we could just
4443 // use the same address.
4445 class ADRP_ADD<SDNode Wrapper, SDNode addrop>
4446 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)),
4447 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>;
4449 def : ADRP_ADD<A64WrapperSmall, tblockaddress>;
4450 def : ADRP_ADD<A64WrapperSmall, texternalsym>;
4451 def : ADRP_ADD<A64WrapperSmall, tglobaladdr>;
4452 def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>;
4453 def : ADRP_ADD<A64WrapperSmall, tjumptable>;
4455 //===----------------------------------------------------------------------===//
4456 // GOT access patterns
4457 //===----------------------------------------------------------------------===//
4461 class GOTLoadSmall<SDNode addrfrag>
4462 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)),
4463 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>;
4465 def : GOTLoadSmall<texternalsym>;
4466 def : GOTLoadSmall<tglobaladdr>;
4467 def : GOTLoadSmall<tglobaltlsaddr>;
4469 //===----------------------------------------------------------------------===//
4470 // Tail call handling
4471 //===----------------------------------------------------------------------===//
4473 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
4475 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
4476 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
4479 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff),
4480 [(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff))]>;
4483 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
4485 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
4486 (Bimm bimm_target:$Label)>;
4488 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [],
4493 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
4494 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>;
4496 //===----------------------------------------------------------------------===//
4497 // Thread local storage
4498 //===----------------------------------------------------------------------===//
4500 // This is a pseudo-instruction representing the ".tlsdesccall" directive in
4501 // assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the
4502 // current location. It should always be immediately followed by a BLR
4503 // instruction, and is intended solely for relaxation by the linker.
4505 def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
4507 def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
4508 let hasSideEffects = 1;
4511 def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
4512 [(A64tlsdesc_blr GPR64:$Rn, tglobaltlsaddr:$Var)]> {
4517 def : Pat<(A64tlsdesc_blr GPR64:$Rn, texternalsym:$Var),
4518 (TLSDESC_BLRx GPR64:$Rn, texternalsym:$Var)>;
4520 //===----------------------------------------------------------------------===//
4521 // Bitfield patterns
4522 //===----------------------------------------------------------------------===//
4524 def bfi32_lsb_to_immr : SDNodeXForm<imm, [{
4525 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64);
4528 def bfi64_lsb_to_immr : SDNodeXForm<imm, [{
4529 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64);
4532 def bfi_width_to_imms : SDNodeXForm<imm, [{
4533 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64);
4537 // The simpler patterns deal with cases where no AND mask is actually needed
4538 // (either all bits are used or the low 32 bits are used).
4539 let AddedComplexity = 10 in {
4541 def : Pat<(A64Bfi GPR64:$src, GPR64:$Rn, imm:$ImmR, imm:$ImmS),
4542 (BFIxxii GPR64:$src, GPR64:$Rn,
4543 (bfi64_lsb_to_immr (i64 imm:$ImmR)),
4544 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4546 def : Pat<(A64Bfi GPR32:$src, GPR32:$Rn, imm:$ImmR, imm:$ImmS),
4547 (BFIwwii GPR32:$src, GPR32:$Rn,
4548 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4549 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4552 def : Pat<(and (A64Bfi GPR64:$src, GPR64:$Rn, imm:$ImmR, imm:$ImmS),
4554 (SUBREG_TO_REG (i64 0),
4555 (BFIwwii (EXTRACT_SUBREG GPR64:$src, sub_32),
4556 (EXTRACT_SUBREG GPR64:$Rn, sub_32),
4557 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4558 (bfi_width_to_imms (i64 imm:$ImmS))),
4563 //===----------------------------------------------------------------------===//
4564 // Miscellaneous patterns
4565 //===----------------------------------------------------------------------===//
4567 // Truncation from 64 to 32-bits just involves renaming your register.
4568 def : Pat<(i32 (trunc (i64 GPR64:$val))), (EXTRACT_SUBREG GPR64:$val, sub_32)>;
4570 // Similarly, extension where we don't care about the high bits is
4572 def : Pat<(i64 (anyext (i32 GPR32:$val))),
4573 (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$val, sub_32)>;
4575 // SELECT instructions providing f128 types need to be handled by a
4576 // pseudo-instruction since the eventual code will need to introduce basic
4577 // blocks and control flow.
4578 def F128CSEL : PseudoInst<(outs FPR128:$Rd),
4579 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
4580 [(set FPR128:$Rd, (simple_select (f128 FPR128:$Rn),
4583 let usesCustomInserter = 1;
4586 //===----------------------------------------------------------------------===//
4587 // Load/store patterns
4588 //===----------------------------------------------------------------------===//
4590 // There are lots of patterns here, because we need to allow at least three
4591 // parameters to vary independently.
4592 // 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ...
4593 // 2. LLVM source: zextloadi8, anyextloadi8, ...
4594 // 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ...
4596 // The biggest problem turns out to be the address-generation variable. At the
4597 // point of instantiation we need to produce two DAGs, one for the pattern and
4598 // one for the instruction. Doing this at the lowest level of classes doesn't
4601 // Consider the simple uimm12 addressing mode, and the desire to match both (add
4602 // GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the
4603 // instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or
4604 // "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this
4605 // operation, and PatFrags are for selection not output.
4607 // As a result, the address-generation patterns are the final
4608 // instantiations. However, we do still need to vary the operand for the address
4609 // further down (At the point we're deciding A64WrapperSmall, we don't know
4610 // the memory width of the operation).
4612 //===------------------------------
4613 // 1. Basic infrastructural defs
4614 //===------------------------------
4616 // First, some simple classes for !foreach and !subst to use:
4627 // You can't use !subst on an actual immediate, but you *can* use it on an
4628 // operand record that happens to match a single immediate. So we do.
4629 def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>;
4630 def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>;
4631 def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>;
4632 def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>;
4633 def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>;
4635 // If the low bits of a pointer are known to be 0 then an "or" is just as good
4636 // as addition for computing an offset. This fragment forwards that check for
4638 def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),
4640 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
4643 // Load/store (unsigned immediate) operations with relocations against global
4644 // symbols (for lo12) are only valid if those symbols have correct alignment
4645 // (since the immediate offset is divided by the access scale, it can't have a
4648 // The guaranteed alignment is provided as part of the WrapperSmall
4649 // operation, and checked against one of these.
4650 def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>;
4651 def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>;
4652 def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>;
4653 def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>;
4654 def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>;
4656 // "Normal" load/store instructions can be used on atomic operations, provided
4657 // the ordering parameter is at most "monotonic". Anything above that needs
4658 // special handling with acquire/release instructions.
4659 class simple_load<PatFrag base>
4660 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4661 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4664 def atomic_load_simple_i8 : simple_load<atomic_load_8>;
4665 def atomic_load_simple_i16 : simple_load<atomic_load_16>;
4666 def atomic_load_simple_i32 : simple_load<atomic_load_32>;
4667 def atomic_load_simple_i64 : simple_load<atomic_load_64>;
4669 class simple_store<PatFrag base>
4670 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4671 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4674 def atomic_store_simple_i8 : simple_store<atomic_store_8>;
4675 def atomic_store_simple_i16 : simple_store<atomic_store_16>;
4676 def atomic_store_simple_i32 : simple_store<atomic_store_32>;
4677 def atomic_store_simple_i64 : simple_store<atomic_store_64>;
4679 //===------------------------------
4680 // 2. UImm12 and SImm9
4681 //===------------------------------
4683 // These instructions have two operands providing the address so they can be
4684 // treated similarly for most purposes.
4686 //===------------------------------
4687 // 2.1 Base patterns covering extend/truncate semantics
4688 //===------------------------------
4690 // Atomic patterns can be shared between integer operations of all sizes, a
4691 // quick multiclass here allows reuse.
4692 multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4693 dag Offset, dag address, RegisterClass TPR,
4695 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4696 (LOAD Base, Offset)>;
4698 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, TPR:$Rt),
4699 (STORE TPR:$Rt, Base, Offset)>;
4702 // Instructions accessing a memory chunk smaller than a register (or, in a
4703 // pinch, the same size) have a characteristic set of patterns they want to
4704 // match: extending loads and truncating stores. This class deals with the
4705 // sign-neutral version of those patterns.
4707 // It will be instantiated across multiple addressing-modes.
4708 multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
4709 dag Base, dag Offset,
4710 dag address, ValueType sty>
4711 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, GPR32, sty> {
4712 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
4714 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
4716 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4717 // register was actually set.
4718 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4719 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4721 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4722 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4724 def : Pat<(!cast<SDNode>(truncstore # sty) GPR32:$Rt, address),
4725 (STORE GPR32:$Rt, Base, Offset)>;
4727 // For truncating store from 64-bits, we have to manually tell LLVM to
4728 // ignore the high bits of the x register.
4729 def : Pat<(!cast<SDNode>(truncstore # sty) GPR64:$Rt, address),
4730 (STORE (EXTRACT_SUBREG GPR64:$Rt, sub_32), Base, Offset)>;
4733 // Next come patterns for sign-extending loads.
4734 multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
4735 dag address, ValueType sty> {
4736 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4737 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
4739 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4740 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>;
4744 // and finally "natural-width" loads and stores come next.
4745 multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4746 dag Offset, dag address, RegisterClass TPR,
4748 def : Pat<(sty (load address)), (LOAD Base, Offset)>;
4749 def : Pat<(store (sty TPR:$Rt), address), (STORE TPR:$Rt, Base, Offset)>;
4752 // Integer operations also get atomic instructions to select for.
4753 multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4754 dag Offset, dag address, RegisterClass TPR,
4756 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, TPR, sty>,
4757 ls_atomic_pats<LOAD, STORE, Base, Offset, address, TPR, sty>;
4759 //===------------------------------
4760 // 2.2. Addressing-mode instantiations
4761 //===------------------------------
4763 multiclass uimm12_pats<dag address, dag Base, dag Offset> {
4764 defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
4765 !foreach(decls.pattern, Offset,
4766 !subst(OFFSET, byte_uimm12, decls.pattern)),
4767 !foreach(decls.pattern, address,
4768 !subst(OFFSET, byte_uimm12,
4769 !subst(ALIGN, any_align, decls.pattern))),
4771 defm : ls_small_pats<LS16_LDR, LS16_STR, Base,
4772 !foreach(decls.pattern, Offset,
4773 !subst(OFFSET, hword_uimm12, decls.pattern)),
4774 !foreach(decls.pattern, address,
4775 !subst(OFFSET, hword_uimm12,
4776 !subst(ALIGN, min_align2, decls.pattern))),
4778 defm : ls_small_pats<LS32_LDR, LS32_STR, Base,
4779 !foreach(decls.pattern, Offset,
4780 !subst(OFFSET, word_uimm12, decls.pattern)),
4781 !foreach(decls.pattern, address,
4782 !subst(OFFSET, word_uimm12,
4783 !subst(ALIGN, min_align4, decls.pattern))),
4786 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base,
4787 !foreach(decls.pattern, Offset,
4788 !subst(OFFSET, word_uimm12, decls.pattern)),
4789 !foreach(decls.pattern, address,
4790 !subst(OFFSET, word_uimm12,
4791 !subst(ALIGN, min_align4, decls.pattern))),
4794 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base,
4795 !foreach(decls.pattern, Offset,
4796 !subst(OFFSET, dword_uimm12, decls.pattern)),
4797 !foreach(decls.pattern, address,
4798 !subst(OFFSET, dword_uimm12,
4799 !subst(ALIGN, min_align8, decls.pattern))),
4802 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base,
4803 !foreach(decls.pattern, Offset,
4804 !subst(OFFSET, hword_uimm12, decls.pattern)),
4805 !foreach(decls.pattern, address,
4806 !subst(OFFSET, hword_uimm12,
4807 !subst(ALIGN, min_align2, decls.pattern))),
4810 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base,
4811 !foreach(decls.pattern, Offset,
4812 !subst(OFFSET, word_uimm12, decls.pattern)),
4813 !foreach(decls.pattern, address,
4814 !subst(OFFSET, word_uimm12,
4815 !subst(ALIGN, min_align4, decls.pattern))),
4818 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
4819 !foreach(decls.pattern, Offset,
4820 !subst(OFFSET, dword_uimm12, decls.pattern)),
4821 !foreach(decls.pattern, address,
4822 !subst(OFFSET, dword_uimm12,
4823 !subst(ALIGN, min_align8, decls.pattern))),
4826 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
4827 !foreach(decls.pattern, Offset,
4828 !subst(OFFSET, qword_uimm12, decls.pattern)),
4829 !foreach(decls.pattern, address,
4830 !subst(OFFSET, qword_uimm12,
4831 !subst(ALIGN, min_align16, decls.pattern))),
4834 defm : load_signed_pats<"B", "", Base,
4835 !foreach(decls.pattern, Offset,
4836 !subst(OFFSET, byte_uimm12, decls.pattern)),
4837 !foreach(decls.pattern, address,
4838 !subst(OFFSET, byte_uimm12,
4839 !subst(ALIGN, any_align, decls.pattern))),
4842 defm : load_signed_pats<"H", "", Base,
4843 !foreach(decls.pattern, Offset,
4844 !subst(OFFSET, hword_uimm12, decls.pattern)),
4845 !foreach(decls.pattern, address,
4846 !subst(OFFSET, hword_uimm12,
4847 !subst(ALIGN, min_align2, decls.pattern))),
4850 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
4851 !subst(OFFSET, word_uimm12,
4852 !subst(ALIGN, min_align4, decls.pattern)))),
4853 (LDRSWx Base, !foreach(decls.pattern, Offset,
4854 !subst(OFFSET, word_uimm12, decls.pattern)))>;
4857 // Straightforward patterns of last resort: a pointer with or without an
4858 // appropriate offset.
4859 defm : uimm12_pats<(i64 GPR64xsp:$Rn), (i64 GPR64xsp:$Rn), (i64 0)>;
4860 defm : uimm12_pats<(add GPR64xsp:$Rn, OFFSET:$UImm12),
4861 (i64 GPR64xsp:$Rn), (i64 OFFSET:$UImm12)>;
4863 // The offset could be hidden behind an "or", of course:
4864 defm : uimm12_pats<(add_like_or GPR64xsp:$Rn, OFFSET:$UImm12),
4865 (i64 GPR64xsp:$Rn), (i64 OFFSET:$UImm12)>;
4867 // Global addresses under the small-absolute model should use these
4868 // instructions. There are ELF relocations specifically for it.
4869 defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
4870 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
4872 defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
4874 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
4876 // External symbols that make it this far should also get standard relocations.
4877 defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
4879 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
4881 defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
4882 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
4884 // We also want to use uimm12 instructions for local variables at the moment.
4885 def tframeindex_XFORM : SDNodeXForm<frameindex, [{
4886 int FI = cast<FrameIndexSDNode>(N)->getIndex();
4887 return CurDAG->getTargetFrameIndex(FI, MVT::i64);
4890 defm : uimm12_pats<(i64 frameindex:$Rn),
4891 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>;
4893 // These can be much simpler than uimm12 because we don't to change the operand
4894 // type (e.g. LDURB and LDURH take the same operands).
4895 multiclass simm9_pats<dag address, dag Base, dag Offset> {
4896 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
4897 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
4899 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address,
4901 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address,
4904 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address,
4906 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address,
4908 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address,
4910 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address,
4913 def : Pat<(i64 (zextloadi32 address)),
4914 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
4916 def : Pat<(truncstorei32 GPR64:$Rt, address),
4917 (LS32_STUR (EXTRACT_SUBREG GPR64:$Rt, sub_32), Base, Offset)>;
4919 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>;
4920 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>;
4921 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>;
4924 defm : simm9_pats<(add GPR64xsp:$Rn, simm9:$SImm9),
4925 (i64 GPR64xsp:$Rn), (SDXF_simm9 simm9:$SImm9)>;
4927 defm : simm9_pats<(add_like_or GPR64xsp:$Rn, simm9:$SImm9),
4928 (i64 GPR64xsp:$Rn), (SDXF_simm9 simm9:$SImm9)>;
4931 //===------------------------------
4932 // 3. Register offset patterns
4933 //===------------------------------
4935 // Atomic patterns can be shared between integer operations of all sizes, a
4936 // quick multiclass here allows reuse.
4937 multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4938 dag Offset, dag Extend, dag address,
4939 RegisterClass TPR, ValueType sty> {
4940 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4941 (LOAD Base, Offset, Extend)>;
4943 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, TPR:$Rt),
4944 (STORE TPR:$Rt, Base, Offset, Extend)>;
4947 // The register offset instructions take three operands giving the instruction,
4948 // and have an annoying split between instructions where Rm is 32-bit and
4949 // 64-bit. So we need a special hierarchy to describe them. Other than that the
4950 // same operations should be supported as for simm9 and uimm12 addressing.
4952 multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
4953 dag Base, dag Offset, dag Extend,
4954 dag address, ValueType sty>
4955 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, GPR32, sty> {
4956 def : Pat<(!cast<SDNode>(zextload # sty) address),
4957 (LOAD Base, Offset, Extend)>;
4959 def : Pat<(!cast<SDNode>(extload # sty) address),
4960 (LOAD Base, Offset, Extend)>;
4962 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4963 // register was actually set.
4964 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4965 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
4967 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4968 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
4970 def : Pat<(!cast<SDNode>(truncstore # sty) GPR32:$Rt, address),
4971 (STORE GPR32:$Rt, Base, Offset, Extend)>;
4973 // For truncating store from 64-bits, we have to manually tell LLVM to
4974 // ignore the high bits of the x register.
4975 def : Pat<(!cast<SDNode>(truncstore # sty) GPR64:$Rt, address),
4976 (STORE (EXTRACT_SUBREG GPR64:$Rt, sub_32), Base, Offset, Extend)>;
4980 // Next come patterns for sign-extending loads.
4981 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
4982 dag address, ValueType sty> {
4983 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4984 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
4985 Base, Offset, Extend)>;
4987 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4988 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
4989 Base, Offset, Extend)>;
4992 // and finally "natural-width" loads and stores come next.
4993 multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
4994 dag Base, dag Offset, dag Extend, dag address,
4995 RegisterClass TPR, ValueType sty> {
4996 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
4997 def : Pat<(store (sty TPR:$Rt), address),
4998 (STORE TPR:$Rt, Base, Offset, Extend)>;
5001 multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
5002 dag Base, dag Offset, dag Extend, dag address,
5003 RegisterClass TPR, ValueType sty>
5004 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, TPR, sty>,
5005 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, TPR, sty>;
5007 multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
5009 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
5010 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
5011 Base, Offset, Extend,
5012 !foreach(decls.pattern, address,
5013 !subst(SHIFT, imm_eq0, decls.pattern)),
5015 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"),
5016 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"),
5017 Base, Offset, Extend,
5018 !foreach(decls.pattern, address,
5019 !subst(SHIFT, imm_eq1, decls.pattern)),
5021 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5022 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5023 Base, Offset, Extend,
5024 !foreach(decls.pattern, address,
5025 !subst(SHIFT, imm_eq2, decls.pattern)),
5028 defm : ro_int_neutral_pats<
5029 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5030 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5031 Base, Offset, Extend,
5032 !foreach(decls.pattern, address,
5033 !subst(SHIFT, imm_eq2, decls.pattern)),
5036 defm : ro_int_neutral_pats<
5037 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
5038 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
5039 Base, Offset, Extend,
5040 !foreach(decls.pattern, address,
5041 !subst(SHIFT, imm_eq3, decls.pattern)),
5044 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
5045 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
5046 Base, Offset, Extend,
5047 !foreach(decls.pattern, address,
5048 !subst(SHIFT, imm_eq1, decls.pattern)),
5051 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"),
5052 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"),
5053 Base, Offset, Extend,
5054 !foreach(decls.pattern, address,
5055 !subst(SHIFT, imm_eq2, decls.pattern)),
5058 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"),
5059 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"),
5060 Base, Offset, Extend,
5061 !foreach(decls.pattern, address,
5062 !subst(SHIFT, imm_eq3, decls.pattern)),
5065 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"),
5066 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"),
5067 Base, Offset, Extend,
5068 !foreach(decls.pattern, address,
5069 !subst(SHIFT, imm_eq4, decls.pattern)),
5072 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
5073 !foreach(decls.pattern, address,
5074 !subst(SHIFT, imm_eq0, decls.pattern)),
5077 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend,
5078 !foreach(decls.pattern, address,
5079 !subst(SHIFT, imm_eq1, decls.pattern)),
5082 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5083 !subst(SHIFT, imm_eq2, decls.pattern))),
5084 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset")
5085 Base, Offset, Extend)>;
5089 // Finally we're in a position to tell LLVM exactly what addresses are reachable
5090 // using register-offset instructions. Essentially a base plus a possibly
5091 // extended, possibly shifted (by access size) offset.
5093 defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (sext GPR32:$Rm)),
5094 (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 6)>;
5096 defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (shl (sext GPR32:$Rm), SHIFT)),
5097 (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 7)>;
5099 defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (zext GPR32:$Rm)),
5100 (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 2)>;
5102 defm : regoff_pats<"Wm", (add GPR64xsp:$Rn, (shl (zext GPR32:$Rm), SHIFT)),
5103 (i64 GPR64xsp:$Rn), (i32 GPR32:$Rm), (i64 3)>;
5105 defm : regoff_pats<"Xm", (add GPR64xsp:$Rn, GPR64:$Rm),
5106 (i64 GPR64xsp:$Rn), (i64 GPR64:$Rm), (i64 2)>;
5108 defm : regoff_pats<"Xm", (add GPR64xsp:$Rn, (shl GPR64:$Rm, SHIFT)),
5109 (i64 GPR64xsp:$Rn), (i64 GPR64:$Rm), (i64 3)>;