1 //===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 scalar instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto","crypto">;
24 // Use fused MAC if more precision in FP computation is allowed.
25 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
26 " FPOpFusion::Fast)">;
27 include "AArch64InstrFormats.td"
29 //===----------------------------------------------------------------------===//
30 // AArch64 specific pattern fragments.
32 // An 'fmul' node with a single use.
33 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
34 return N->hasOneUse();
38 //===----------------------------------------------------------------------===//
39 // Target-specific ISD nodes and profiles
40 //===----------------------------------------------------------------------===//
42 def SDT_A64ret : SDTypeProfile<0, 0, []>;
43 def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
47 // (ins NZCV, Condition, Dest)
48 def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;
49 def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>;
51 // (outs Result), (ins NZCV, IfTrue, IfFalse, Condition)
52 def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>,
55 def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>;
57 // (outs NZCV), (ins LHS, RHS, Condition)
58 def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
60 def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>;
63 // (outs GPR64), (ins)
64 def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
66 // A64 compares don't care about the cond really (they set all flags) so a
67 // simple binary operator is useful.
68 def A64cmp : PatFrag<(ops node:$lhs, node:$rhs),
69 (A64setcc node:$lhs, node:$rhs, cond)>;
72 // When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN
73 // instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C
74 // and V flags can be set differently by this operation. It comes down to
75 // whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are
76 // then everything is fine. If not then the optimization is wrong. Thus general
77 // comparisons are only valid if op2 != 0.
79 // So, finally, the only LLVM-native comparisons that don't mention C and V are
80 // SETEQ and SETNE. They're the only ones we can safely use CMN for in the
81 // absence of information about op2.
82 def equality_cond : PatLeaf<(cond), [{
83 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE;
86 def A64cmn : PatFrag<(ops node:$lhs, node:$rhs),
87 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>;
89 // There are two layers of indirection here, driven by the following
91 // + TableGen does not know CodeModel or Reloc so that decision should be
92 // made for a variable/address at ISelLowering.
93 // + The output of ISelLowering should be selectable (hence the Wrapper,
94 // rather than a bare target opcode)
95 def SDTAArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
101 def A64WrapperLarge :SDNode<"AArch64ISD::WrapperLarge", SDTAArch64WrapperLarge>;
103 def SDTAArch64WrapperSmall : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
108 def A64WrapperSmall :SDNode<"AArch64ISD::WrapperSmall", SDTAArch64WrapperSmall>;
111 def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
112 def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad,
116 // (A64BFI LHS, RHS, LSB, Width)
117 def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
122 def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>;
124 // (A64EXTR HiReg, LoReg, LSB)
125 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
127 def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
129 // (A64[SU]BFX Field, ImmR, ImmS).
131 // Note that ImmR and ImmS are already encoded for the actual instructions. The
132 // more natural LSB and Width mix together to form ImmR and ImmS, something
133 // which TableGen can't handle.
134 def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
135 def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>;
137 def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>;
139 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
141 //===----------------------------------------------------------------------===//
142 // Call sequence pseudo-instructions
143 //===----------------------------------------------------------------------===//
146 def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
147 def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
150 def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call,
151 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
153 // The TLSDESCCALL node is a variant call which goes to an indirectly calculated
154 // destination but needs a relocation against a fixed symbol. As such it has two
155 // certain operands: the callee and the relocated variable.
157 // The TLS ABI only allows it to be selected to a BLR instructin (with
158 // appropriate relocation).
159 def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
161 def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
162 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
166 def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
167 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart,
168 [SDNPHasChain, SDNPOutGlue]>;
170 def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>;
171 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd,
172 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
176 // These pseudo-instructions have special semantics by virtue of being passed to
177 // the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by
178 // LowerCall to (in our case) tell the back-end about stack adjustments for
179 // arguments passed on the stack. Here we select those markers to
180 // pseudo-instructions which explicitly set the stack, and finally in the
181 // RegisterInfo we convert them to a true stack adjustment.
182 let Defs = [XSP], Uses = [XSP] in {
183 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
184 [(AArch64callseq_start timm:$amt)]>;
186 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2),
187 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
190 //===----------------------------------------------------------------------===//
191 // Atomic operation pseudo-instructions
192 //===----------------------------------------------------------------------===//
194 // These get selected from C++ code as a pretty much direct translation from the
195 // generic DAG nodes. The one exception is the AtomicOrdering is added as an
196 // operand so that the eventual lowering can make use of it and choose
197 // acquire/release operations when required.
199 let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in {
200 multiclass AtomicSizes {
201 def _I8 : PseudoInst<(outs GPR32:$dst),
202 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
203 def _I16 : PseudoInst<(outs GPR32:$dst),
204 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
205 def _I32 : PseudoInst<(outs GPR32:$dst),
206 (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>;
207 def _I64 : PseudoInst<(outs GPR64:$dst),
208 (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>;
212 defm ATOMIC_LOAD_ADD : AtomicSizes;
213 defm ATOMIC_LOAD_SUB : AtomicSizes;
214 defm ATOMIC_LOAD_AND : AtomicSizes;
215 defm ATOMIC_LOAD_OR : AtomicSizes;
216 defm ATOMIC_LOAD_XOR : AtomicSizes;
217 defm ATOMIC_LOAD_NAND : AtomicSizes;
218 defm ATOMIC_SWAP : AtomicSizes;
219 let Defs = [NZCV] in {
220 // These operations need a CMP to calculate the correct value
221 defm ATOMIC_LOAD_MIN : AtomicSizes;
222 defm ATOMIC_LOAD_MAX : AtomicSizes;
223 defm ATOMIC_LOAD_UMIN : AtomicSizes;
224 defm ATOMIC_LOAD_UMAX : AtomicSizes;
227 class AtomicCmpSwap<RegisterClass GPRData>
228 : PseudoInst<(outs GPRData:$dst),
229 (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new,
230 i32imm:$ordering), []> {
231 let usesCustomInserter = 1;
238 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>;
239 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>;
240 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>;
241 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>;
243 //===----------------------------------------------------------------------===//
244 // Add-subtract (extended register) instructions
245 //===----------------------------------------------------------------------===//
246 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP
248 // The RHS of these operations is conceptually a sign/zero-extended
249 // register, optionally shifted left by 1-4. The extension can be a
250 // NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but
251 // must be specified with one exception:
253 // If one of the registers is sp/wsp then LSL is an alias for UXTW in
254 // 32-bit instructions and UXTX in 64-bit versions, the shift amount
255 // is not optional in that case (but can explicitly be 0), and the
256 // entire suffix can be skipped (e.g. "add sp, x3, x2").
258 multiclass extend_operands<string PREFIX, string Diag> {
259 def _asmoperand : AsmOperandClass {
261 let RenderMethod = "addRegExtendOperands";
262 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
263 let DiagnosticType = "AddSubRegExtend" # Diag;
266 def _operand : Operand<i64>,
267 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
268 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
269 let DecoderMethod = "DecodeRegExtendOperand";
270 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
274 defm UXTB : extend_operands<"UXTB", "Small">;
275 defm UXTH : extend_operands<"UXTH", "Small">;
276 defm UXTW : extend_operands<"UXTW", "Small">;
277 defm UXTX : extend_operands<"UXTX", "Large">;
278 defm SXTB : extend_operands<"SXTB", "Small">;
279 defm SXTH : extend_operands<"SXTH", "Small">;
280 defm SXTW : extend_operands<"SXTW", "Small">;
281 defm SXTX : extend_operands<"SXTX", "Large">;
283 def LSL_extasmoperand : AsmOperandClass {
284 let Name = "RegExtendLSL";
285 let RenderMethod = "addRegExtendOperands";
286 let DiagnosticType = "AddSubRegExtendLarge";
289 def LSL_extoperand : Operand<i64> {
290 let ParserMatchClass = LSL_extasmoperand;
294 // The patterns for various sign-extensions are a little ugly and
295 // non-uniform because everything has already been promoted to the
296 // legal i64 and i32 types. We'll wrap the various variants up in a
297 // class for use later.
299 dag uxtb; dag uxth; dag uxtw; dag uxtx;
300 dag sxtb; dag sxth; dag sxtw; dag sxtx;
305 def extends_to_i64 : extend_types {
306 let uxtb = (and (anyext i32:$Rm), 255);
307 let uxth = (and (anyext i32:$Rm), 65535);
308 let uxtw = (zext i32:$Rm);
309 let uxtx = (i64 $Rm);
311 let sxtb = (sext_inreg (anyext i32:$Rm), i8);
312 let sxth = (sext_inreg (anyext i32:$Rm), i16);
313 let sxtw = (sext i32:$Rm);
314 let sxtx = (i64 $Rm);
321 def extends_to_i32 : extend_types {
322 let uxtb = (and i32:$Rm, 255);
323 let uxth = (and i32:$Rm, 65535);
324 let uxtw = (i32 i32:$Rm);
325 let uxtx = (i32 i32:$Rm);
327 let sxtb = (sext_inreg i32:$Rm, i8);
328 let sxth = (sext_inreg i32:$Rm, i16);
329 let sxtw = (i32 i32:$Rm);
330 let sxtx = (i32 i32:$Rm);
336 // Now, six of the extensions supported are easy and uniform: if the source size
337 // is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate
338 // those instructions in one block.
340 // The uxtx/sxtx could potentially be merged in, but three facts dissuaded me:
341 // + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would
343 // + Patterns are very different as well.
344 // + Passing different registers would be ugly (more fields in extend_types
345 // would probably be the best option).
346 multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
347 SDPatternOperator opfrag,
348 dag outs, extend_types exts> {
349 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
350 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
351 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
352 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
354 Sched<[WriteALU, ReadALU, ReadALU]>;
355 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001,
356 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
357 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
358 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
360 Sched<[WriteALU, ReadALU, ReadALU]>;
361 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010,
362 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
363 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
364 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
366 Sched<[WriteALU, ReadALU, ReadALU]>;
368 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100,
369 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
370 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
371 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
373 Sched<[WriteALU, ReadALU, ReadALU]>;
374 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101,
375 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
376 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
377 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
379 Sched<[WriteALU, ReadALU, ReadALU]>;
380 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110,
381 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
382 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
383 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
385 Sched<[WriteALU, ReadALU, ReadALU]>;
388 // These two could be merge in with the above, but their patterns aren't really
389 // necessary and the naming-scheme would necessarily break:
390 multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
392 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
394 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
395 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
396 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
398 Sched<[WriteALU, ReadALU, ReadALU]>;
400 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
402 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
403 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
404 [/* No Pattern: same as uxtx */],
406 Sched<[WriteALU, ReadALU, ReadALU]>;
409 multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
410 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
411 outs, (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
412 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
413 [/* No pattern: probably same as uxtw */],
415 Sched<[WriteALU, ReadALU, ReadALU]>;
417 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
418 outs, (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
419 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
420 [/* No Pattern: probably same as uxtw */],
422 Sched<[WriteALU, ReadALU, ReadALU]>;
425 class SetRD<RegisterClass RC, SDPatternOperator op>
426 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>;
427 class SetNZCV<SDPatternOperator op>
428 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>;
430 defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
431 (outs GPR64xsp:$Rd), extends_to_i64>,
432 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>,
433 (outs GPR64xsp:$Rd)>;
434 defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>,
435 (outs GPR32wsp:$Rd), extends_to_i32>,
436 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ",
437 (outs GPR32wsp:$Rd)>;
438 defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
439 (outs GPR64xsp:$Rd), extends_to_i64>,
440 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>,
441 (outs GPR64xsp:$Rd)>;
442 defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>,
443 (outs GPR32wsp:$Rd), extends_to_i32>,
444 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ",
445 (outs GPR32wsp:$Rd)>;
447 let Defs = [NZCV] in {
448 defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
449 (outs GPR64:$Rd), extends_to_i64>,
450 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>,
452 defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>,
453 (outs GPR32:$Rd), extends_to_i32>,
454 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ",
456 defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
457 (outs GPR64:$Rd), extends_to_i64>,
458 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>,
460 defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>,
461 (outs GPR32:$Rd), extends_to_i32>,
462 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ",
466 let Rd = 0b11111, isCompare = 1 in {
467 defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
468 (outs), extends_to_i64>,
469 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>;
470 defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>,
471 (outs), extends_to_i32>,
472 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>;
473 defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
474 (outs), extends_to_i64>,
475 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>;
476 defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>,
477 (outs), extends_to_i32>,
478 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>;
482 // Now patterns for the operation without a shift being needed. No patterns are
483 // created for uxtx/sxtx since they're non-uniform and it's expected that
484 // add/sub (shifted register) will handle those cases anyway.
485 multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
487 def : Pat<(nodeop exts.ty:$Rn, exts.uxtb),
488 (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>;
489 def : Pat<(nodeop exts.ty:$Rn, exts.uxth),
490 (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>;
491 def : Pat<(nodeop exts.ty:$Rn, exts.uxtw),
492 (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>;
494 def : Pat<(nodeop exts.ty:$Rn, exts.sxtb),
495 (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>;
496 def : Pat<(nodeop exts.ty:$Rn, exts.sxth),
497 (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>;
498 def : Pat<(nodeop exts.ty:$Rn, exts.sxtw),
499 (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>;
502 defm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>;
503 defm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>;
504 defm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>;
505 defm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>;
507 defm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>;
508 defm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>;
509 defm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>;
510 defm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>;
512 // An extend of "lsl #imm" is valid if and only if one of Rn and Rd is
513 // sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the
514 // operation. Also permitted in this case is complete omission of the argument,
515 // which implies "lsl #0".
516 multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
517 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
518 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
519 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
521 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"),
522 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
526 defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
527 defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
528 defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>;
529 defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>;
530 defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>;
531 defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>;
532 defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>;
533 defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>;
535 // Rd cannot be sp for flag-setting variants so only half of the aliases are
537 defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>;
538 defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>;
539 defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>;
540 defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>;
542 // CMP unfortunately has to be different because the instruction doesn't have a
544 multiclass cmp_lsl_aliases<string asmop, Instruction inst,
545 RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
546 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
547 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
549 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"),
550 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>;
553 defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>;
554 defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>;
555 defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>;
556 defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>;
558 //===----------------------------------------------------------------------===//
559 // Add-subtract (immediate) instructions
560 //===----------------------------------------------------------------------===//
561 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV
563 // These instructions accept a 12-bit unsigned immediate, optionally shifted
564 // left by 12 bits. Official assembly format specifies a 12 bit immediate with
565 // one of "", "LSL #0", "LSL #12" supplementary operands.
567 // There are surprisingly few ways to make this work with TableGen, so this
568 // implementation has separate instructions for the "LSL #0" and "LSL #12"
571 // If the MCInst retained a single combined immediate (which could be 0x123000,
572 // for example) then both components (imm & shift) would have to be delegated to
573 // a single assembly operand. This would entail a separate operand parser
574 // (because the LSL would have to live in the same AArch64Operand as the
575 // immediate to be accessible); assembly parsing is rather complex and
576 // error-prone C++ code.
578 // By splitting the immediate, we can delegate handling this optional operand to
579 // an InstAlias. Supporting functions to generate the correct MCInst are still
580 // required, but these are essentially trivial and parsing can remain generic.
582 // Rejected plans with rationale:
583 // ------------------------------
585 // In an ideal world you'de have two first class immediate operands (in
586 // InOperandList, specifying imm12 and shift). Unfortunately this is not
587 // selectable by any means I could discover.
589 // An Instruction with two MCOperands hidden behind a single entry in
590 // InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional,
591 // but required more C++ code to handle encoding/decoding. Parsing (the intended
592 // main beneficiary) ended up equally complex because of the optional nature of
595 // Attempting to circumvent the need for a custom OperandParser above by giving
596 // InstAliases without the "lsl #0" failed. add/sub could be accommodated but
597 // the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands
598 // should be parsed: there was no way to accommodate an "lsl #12".
600 let ParserMethod = "ParseImmWithLSLOperand",
601 RenderMethod = "addImmWithLSLOperands" in {
602 // Derived PredicateMethod fields are different for each
603 def addsubimm_lsl0_asmoperand : AsmOperandClass {
604 let Name = "AddSubImmLSL0";
605 // If an error is reported against this operand, instruction could also be a
607 let DiagnosticType = "AddSubSecondSource";
610 def addsubimm_lsl12_asmoperand : AsmOperandClass {
611 let Name = "AddSubImmLSL12";
612 let DiagnosticType = "AddSubSecondSource";
616 def shr_12_XFORM : SDNodeXForm<imm, [{
617 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32);
620 def shr_12_neg_XFORM : SDNodeXForm<imm, [{
621 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32);
624 def neg_XFORM : SDNodeXForm<imm, [{
625 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32);
629 multiclass addsub_imm_operands<ValueType ty> {
630 let PrintMethod = "printAddSubImmLSL0Operand",
631 EncoderMethod = "getAddSubImmOpValue",
632 ParserMatchClass = addsubimm_lsl0_asmoperand in {
633 def _posimm_lsl0 : Operand<ty>,
634 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
635 def _negimm_lsl0 : Operand<ty>,
636 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }],
640 let PrintMethod = "printAddSubImmLSL12Operand",
641 EncoderMethod = "getAddSubImmOpValue",
642 ParserMatchClass = addsubimm_lsl12_asmoperand in {
643 def _posimm_lsl12 : Operand<ty>,
644 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
647 def _negimm_lsl12 : Operand<ty>,
648 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }],
653 // The add operands don't need any transformation
654 defm addsubimm_operand_i32 : addsub_imm_operands<i32>;
655 defm addsubimm_operand_i64 : addsub_imm_operands<i64>;
657 multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift,
658 string asmop, string cmpasmop,
659 Operand imm_operand, Operand cmp_imm_operand,
660 RegisterClass GPR, RegisterClass GPRsp,
661 AArch64Reg ZR, ValueType Ty> {
662 // All registers for non-S variants allow SP
663 def _s : A64I_addsubimm<sf, op, 0b0, shift,
665 (ins GPRsp:$Rn, imm_operand:$Imm12),
666 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
667 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
669 Sched<[WriteALU, ReadALU]>;
672 // S variants can read SP but would write to ZR
673 def _S : A64I_addsubimm<sf, op, 0b1, shift,
675 (ins GPRsp:$Rn, imm_operand:$Imm12),
676 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
677 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
679 Sched<[WriteALU, ReadALU]> {
683 // Note that the pattern here for ADDS is subtle. Canonically CMP
684 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to
685 // ADDS a, (-b). This is not true in general.
686 def _cmp : A64I_addsubimm<sf, op, 0b1, shift,
687 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12),
688 !strconcat(cmpasmop, " $Rn, $Imm12"),
690 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
692 Sched<[WriteALU, ReadALU]> {
700 multiclass addsubimm_shifts<string prefix, bit sf, bit op,
701 string asmop, string cmpasmop, string operand, string cmpoperand,
702 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR,
704 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
706 !cast<Operand>(operand # "_lsl0"),
707 !cast<Operand>(cmpoperand # "_lsl0"),
710 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01,
712 !cast<Operand>(operand # "_lsl12"),
713 !cast<Operand>(cmpoperand # "_lsl12"),
717 defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn",
718 "addsubimm_operand_i32_posimm",
719 "addsubimm_operand_i32_negimm",
720 GPR32, GPR32wsp, WZR, i32>;
721 defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn",
722 "addsubimm_operand_i64_posimm",
723 "addsubimm_operand_i64_negimm",
724 GPR64, GPR64xsp, XZR, i64>;
725 defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp",
726 "addsubimm_operand_i32_negimm",
727 "addsubimm_operand_i32_posimm",
728 GPR32, GPR32wsp, WZR, i32>;
729 defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp",
730 "addsubimm_operand_i64_negimm",
731 "addsubimm_operand_i64_posimm",
732 GPR64, GPR64xsp, XZR, i64>;
734 multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
735 def _fromsp : InstAlias<"mov $Rd, $Rn",
736 (addop GPRsp:$Rd, SP:$Rn, 0),
739 def _tosp : InstAlias<"mov $Rd, $Rn",
740 (addop SP:$Rd, GPRsp:$Rn, 0),
744 // Recall Rxsp is a RegisterClass containing *just* xsp.
745 defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>;
746 defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>;
748 //===----------------------------------------------------------------------===//
749 // Add-subtract (shifted register) instructions
750 //===----------------------------------------------------------------------===//
751 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
753 //===-------------------------------
754 // 1. The "shifted register" operands. Shared with logical insts.
755 //===-------------------------------
757 multiclass shift_operands<string prefix, string form> {
758 def _asmoperand_i32 : AsmOperandClass {
759 let Name = "Shift" # form # "i32";
760 let RenderMethod = "addShiftOperands";
761 let PredicateMethod = "isShift<A64SE::" # form # ", false>";
762 let DiagnosticType = "AddSubRegShift32";
765 // Note that the operand type is intentionally i64 because the DAGCombiner
766 // puts these into a canonical form.
767 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
769 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
770 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
771 let DecoderMethod = "Decode32BitShiftOperand";
774 def _asmoperand_i64 : AsmOperandClass {
775 let Name = "Shift" # form # "i64";
776 let RenderMethod = "addShiftOperands";
777 let PredicateMethod = "isShift<A64SE::" # form # ", true>";
778 let DiagnosticType = "AddSubRegShift64";
781 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
783 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
784 let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
788 defm lsl_operand : shift_operands<"lsl_operand", "LSL">;
789 defm lsr_operand : shift_operands<"lsr_operand", "LSR">;
790 defm asr_operand : shift_operands<"asr_operand", "ASR">;
792 // Not used for add/sub, but defined here for completeness. The "logical
793 // (shifted register)" instructions *do* have an ROR variant.
794 defm ror_operand : shift_operands<"ror_operand", "ROR">;
796 //===-------------------------------
797 // 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions.
798 //===-------------------------------
800 // N.b. the commutable parameter is just !N. It will be first against the wall
801 // when the revolution comes.
802 multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
803 string asmop, SDPatternOperator opfrag, ValueType ty,
804 RegisterClass GPR, list<Register> defs> {
805 let isCommutable = commutable, Defs = defs in {
806 def _lsl : A64I_addsubshift<sf, op, s, 0b00,
808 (ins GPR:$Rn, GPR:$Rm,
809 !cast<Operand>("lsl_operand_" # ty):$Imm6),
810 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
811 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
812 !cast<Operand>("lsl_operand_" # ty):$Imm6))
815 Sched<[WriteALU, ReadALU]>;
817 def _lsr : A64I_addsubshift<sf, op, s, 0b01,
819 (ins GPR:$Rn, GPR:$Rm,
820 !cast<Operand>("lsr_operand_" # ty):$Imm6),
821 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
822 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
823 !cast<Operand>("lsr_operand_" # ty):$Imm6))
826 Sched<[WriteALU, ReadALU]>;
828 def _asr : A64I_addsubshift<sf, op, s, 0b10,
830 (ins GPR:$Rn, GPR:$Rm,
831 !cast<Operand>("asr_operand_" # ty):$Imm6),
832 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
833 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
834 !cast<Operand>("asr_operand_" # ty):$Imm6))
837 Sched<[WriteALU, ReadALU]>;
841 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
842 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
845 def : Pat<(opfrag ty:$Rn, ty:$Rm),
846 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
849 multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
850 string asmop, SDPatternOperator opfrag,
851 list<Register> defs> {
852 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
853 commutable, asmop, opfrag, i64, GPR64, defs>;
854 defm www : addsub_shifts<prefix # "www", 0b0, op, s,
855 commutable, asmop, opfrag, i32, GPR32, defs>;
859 defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>;
860 defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>;
862 defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>;
863 defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>;
865 //===-------------------------------
866 // 1. The NEG/NEGS aliases
867 //===-------------------------------
869 multiclass neg_alias<Instruction INST, RegisterClass GPR, Register ZR,
870 ValueType ty, Operand shift_operand, SDNode shiftop> {
871 def : InstAlias<"neg $Rd, $Rm, $Imm6",
872 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
874 def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)),
875 (INST ZR, $Rm, shift_operand:$Imm6)>;
878 defm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>;
879 defm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>;
880 defm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>;
881 def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
882 def : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>;
884 defm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>;
885 defm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>;
886 defm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>;
887 def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
888 def : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>;
890 // NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to
892 class negs_alias<Instruction INST, RegisterClass GPR,
893 Register ZR, Operand shift_operand, SDNode shiftop>
894 : InstAlias<"negs $Rd, $Rm, $Imm6",
895 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
897 def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>;
898 def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>;
899 def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>;
900 def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
902 def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>;
903 def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>;
904 def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>;
905 def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
907 //===-------------------------------
908 // 1. The CMP/CMN aliases
909 //===-------------------------------
911 multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
912 string asmop, SDPatternOperator opfrag, ValueType ty,
914 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
915 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
917 (ins GPR:$Rn, GPR:$Rm,
918 !cast<Operand>("lsl_operand_" # ty):$Imm6),
919 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
920 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
921 !cast<Operand>("lsl_operand_" # ty):$Imm6))
924 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
926 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01,
928 (ins GPR:$Rn, GPR:$Rm,
929 !cast<Operand>("lsr_operand_" # ty):$Imm6),
930 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
931 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
932 !cast<Operand>("lsr_operand_" # ty):$Imm6))
935 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
937 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10,
939 (ins GPR:$Rn, GPR:$Rm,
940 !cast<Operand>("asr_operand_" # ty):$Imm6),
941 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"),
942 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
943 !cast<Operand>("asr_operand_" # ty):$Imm6))
946 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
950 : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
951 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
953 def : Pat<(opfrag ty:$Rn, ty:$Rm),
954 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
957 defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>;
958 defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>;
960 defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>;
961 defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>;
963 //===----------------------------------------------------------------------===//
964 // Add-subtract (with carry) instructions
965 //===----------------------------------------------------------------------===//
966 // Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
968 multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
969 let Uses = [NZCV] in {
970 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
971 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
972 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
974 Sched<[WriteALU, ReadALU, ReadALU]>;
976 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
977 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
978 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
980 Sched<[WriteALU, ReadALU, ReadALU]>;
984 let isCommutable = 1 in {
985 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
988 defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
990 let Defs = [NZCV] in {
991 let isCommutable = 1 in {
992 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
995 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">;
998 def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>;
999 def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
1000 def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>;
1001 def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>;
1003 // Note that adde and sube can form a chain longer than two (e.g. for 256-bit
1004 // addition). So the flag-setting instructions are appropriate.
1005 def : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>;
1006 def : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>;
1007 def : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>;
1008 def : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>;
1010 //===----------------------------------------------------------------------===//
1012 //===----------------------------------------------------------------------===//
1013 // Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL,
1016 // Because of the rather complicated nearly-overlapping aliases, the decoding of
1017 // this range of instructions is handled manually. The architectural
1018 // instructions are BFM, SBFM and UBFM but a disassembler should never produce
1021 // In the end, the best option was to use BFM instructions for decoding under
1022 // almost all circumstances, but to create aliasing *Instructions* for each of
1023 // the canonical forms and specify a completely custom decoder which would
1024 // substitute the correct MCInst as needed.
1026 // This also simplifies instruction selection, parsing etc because the MCInsts
1027 // have a shape that's closer to their use in code.
1029 //===-------------------------------
1030 // 1. The architectural BFM instructions
1031 //===-------------------------------
1033 def uimm5_asmoperand : AsmOperandClass {
1035 let PredicateMethod = "isUImm<5>";
1036 let RenderMethod = "addImmOperands";
1037 let DiagnosticType = "UImm5";
1040 def uimm6_asmoperand : AsmOperandClass {
1042 let PredicateMethod = "isUImm<6>";
1043 let RenderMethod = "addImmOperands";
1044 let DiagnosticType = "UImm6";
1047 def bitfield32_imm : Operand<i64>,
1048 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
1049 let ParserMatchClass = uimm5_asmoperand;
1051 let DecoderMethod = "DecodeBitfield32ImmOperand";
1055 def bitfield64_imm : Operand<i64>,
1056 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
1057 let ParserMatchClass = uimm6_asmoperand;
1059 // Default decoder works in 64-bit case: the 6-bit field can take any value.
1062 multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
1063 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1064 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1065 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1067 Sched<[WriteALU, ReadALU]> {
1068 let DecoderMethod = "DecodeBitfieldInstruction";
1071 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1072 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1073 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1075 Sched<[WriteALU, ReadALU]> {
1076 let DecoderMethod = "DecodeBitfieldInstruction";
1080 defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">;
1081 defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">;
1083 // BFM instructions modify the destination register rather than defining it
1086 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1087 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1088 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1089 Sched<[WriteALU, ReadALU]> {
1090 let DecoderMethod = "DecodeBitfieldInstruction";
1091 let Constraints = "$src = $Rd";
1095 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1096 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1097 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1098 Sched<[WriteALU, ReadALU]> {
1099 let DecoderMethod = "DecodeBitfieldInstruction";
1100 let Constraints = "$src = $Rd";
1104 //===-------------------------------
1105 // 2. Extend aliases to 64-bit dest
1106 //===-------------------------------
1108 // Unfortunately the extensions that end up as 64-bits cannot be handled by an
1109 // instruction alias: their syntax is (for example) "SXTB x0, w0", which needs
1110 // to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is
1111 // not capable of such a map as far as I'm aware
1113 // Note that these instructions are strictly more specific than the
1114 // BFM ones (in ImmR) so they can handle their own decoding.
1115 class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty,
1116 string asmop, bits<6> imms, dag pattern>
1117 : A64I_bitfield<sf, opc, sf,
1118 (outs GPRDest:$Rd), (ins GPR32:$Rn),
1119 !strconcat(asmop, "\t$Rd, $Rn"),
1120 [(set dty:$Rd, pattern)], NoItinerary>,
1121 Sched<[WriteALU, ReadALU]> {
1122 let ImmR = 0b000000;
1126 // Signed extensions
1127 def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7,
1128 (sext_inreg (anyext i32:$Rn), i8)>;
1129 def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7,
1130 (sext_inreg i32:$Rn, i8)>;
1131 def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15,
1132 (sext_inreg (anyext i32:$Rn), i16)>;
1133 def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15,
1134 (sext_inreg i32:$Rn, i16)>;
1135 def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>;
1137 // Unsigned extensions
1138 def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7,
1139 (and i32:$Rn, 255)>;
1140 def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15,
1141 (and i32:$Rn, 65535)>;
1143 // The 64-bit unsigned variants are not strictly architectural but recommended
1145 let isAsmParserOnly = 1 in {
1146 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7,
1147 (and (anyext i32:$Rn), 255)>;
1148 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15,
1149 (and (anyext i32:$Rn), 65535)>;
1152 // Extra patterns for when the source register is actually 64-bits
1153 // too. There's no architectural difference here, it's just LLVM
1154 // shinanigans. There's no need for equivalent zero-extension patterns
1155 // because they'll already be caught by logical (immediate) matching.
1156 def : Pat<(sext_inreg i64:$Rn, i8),
1157 (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>;
1158 def : Pat<(sext_inreg i64:$Rn, i16),
1159 (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>;
1160 def : Pat<(sext_inreg i64:$Rn, i32),
1161 (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>;
1164 //===-------------------------------
1165 // 3. Aliases for ASR and LSR (the simple shifts)
1166 //===-------------------------------
1168 // These also handle their own decoding because ImmS being set makes
1169 // them take precedence over BFM.
1170 multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
1171 def wwi : A64I_bitfield<0b0, opc, 0b0,
1172 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
1173 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1174 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
1176 Sched<[WriteALU, ReadALU]> {
1180 def xxi : A64I_bitfield<0b1, opc, 0b1,
1181 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
1182 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
1183 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
1185 Sched<[WriteALU, ReadALU]> {
1191 defm ASR : A64I_shift<0b00, "asr", sra>;
1192 defm LSR : A64I_shift<0b10, "lsr", srl>;
1194 //===-------------------------------
1195 // 4. Aliases for LSL
1196 //===-------------------------------
1198 // Unfortunately LSL and subsequent aliases are much more complicated. We need
1199 // to be able to say certain output instruction fields depend in a complex
1200 // manner on combinations of input assembly fields).
1202 // MIOperandInfo *might* have been able to do it, but at the cost of
1203 // significantly more C++ code.
1205 // N.b. contrary to usual practice these operands store the shift rather than
1206 // the machine bits in an MCInst. The complexity overhead of consistency
1207 // outweighed the benefits in this case (custom asmparser, printer and selection
1208 // vs custom encoder).
1209 def bitfield32_lsl_imm : Operand<i64>,
1210 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1211 let ParserMatchClass = uimm5_asmoperand;
1212 let EncoderMethod = "getBitfield32LSLOpValue";
1215 def bitfield64_lsl_imm : Operand<i64>,
1216 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1217 let ParserMatchClass = uimm6_asmoperand;
1218 let EncoderMethod = "getBitfield64LSLOpValue";
1221 class A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty,
1223 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
1224 "lsl\t$Rd, $Rn, $FullImm",
1225 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
1227 Sched<[WriteALU, ReadALU]> {
1229 let ImmR = FullImm{5-0};
1230 let ImmS = FullImm{11-6};
1232 // No disassembler allowed because it would overlap with BFM which does the
1234 let isAsmParserOnly = 1;
1237 def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>;
1238 def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>;
1240 //===-------------------------------
1241 // 5. Aliases for bitfield extract instructions
1242 //===-------------------------------
1244 def bfx32_width_asmoperand : AsmOperandClass {
1245 let Name = "BFX32Width";
1246 let PredicateMethod = "isBitfieldWidth<32>";
1247 let RenderMethod = "addBFXWidthOperands";
1248 let DiagnosticType = "Width32";
1251 def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
1252 let PrintMethod = "printBFXWidthOperand";
1253 let ParserMatchClass = bfx32_width_asmoperand;
1256 def bfx64_width_asmoperand : AsmOperandClass {
1257 let Name = "BFX64Width";
1258 let PredicateMethod = "isBitfieldWidth<64>";
1259 let RenderMethod = "addBFXWidthOperands";
1260 let DiagnosticType = "Width64";
1263 def bfx64_width : Operand<i64> {
1264 let PrintMethod = "printBFXWidthOperand";
1265 let ParserMatchClass = bfx64_width_asmoperand;
1269 multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
1270 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1271 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1272 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1273 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
1275 Sched<[WriteALU, ReadALU]> {
1276 // As above, no disassembler allowed.
1277 let isAsmParserOnly = 1;
1280 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1281 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1282 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1283 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
1285 Sched<[WriteALU, ReadALU]> {
1286 // As above, no disassembler allowed.
1287 let isAsmParserOnly = 1;
1291 defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>;
1292 defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>;
1294 // Again, variants based on BFM modify Rd so need it as an input too.
1295 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1296 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1297 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1298 Sched<[WriteALU, ReadALU]> {
1299 // As above, no disassembler allowed.
1300 let isAsmParserOnly = 1;
1301 let Constraints = "$src = $Rd";
1304 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1305 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1306 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1307 Sched<[WriteALU, ReadALU]> {
1308 // As above, no disassembler allowed.
1309 let isAsmParserOnly = 1;
1310 let Constraints = "$src = $Rd";
1313 // SBFX instructions can do a 1-instruction sign-extension of boolean values.
1314 def : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>;
1315 def : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>;
1316 def : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)),
1317 (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>;
1319 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
1320 // use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
1321 def : Pat<(i64 (zext i32:$Rn)), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31),
1324 //===-------------------------------
1325 // 6. Aliases for bitfield insert instructions
1326 //===-------------------------------
1328 def bfi32_lsb_asmoperand : AsmOperandClass {
1329 let Name = "BFI32LSB";
1330 let PredicateMethod = "isUImm<5>";
1331 let RenderMethod = "addBFILSBOperands<32>";
1332 let DiagnosticType = "UImm5";
1335 def bfi32_lsb : Operand<i64>,
1336 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
1337 let PrintMethod = "printBFILSBOperand<32>";
1338 let ParserMatchClass = bfi32_lsb_asmoperand;
1341 def bfi64_lsb_asmoperand : AsmOperandClass {
1342 let Name = "BFI64LSB";
1343 let PredicateMethod = "isUImm<6>";
1344 let RenderMethod = "addBFILSBOperands<64>";
1345 let DiagnosticType = "UImm6";
1348 def bfi64_lsb : Operand<i64>,
1349 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
1350 let PrintMethod = "printBFILSBOperand<64>";
1351 let ParserMatchClass = bfi64_lsb_asmoperand;
1354 // Width verification is performed during conversion so width operand can be
1355 // shared between 32/64-bit cases. Still needed for the print method though
1356 // because ImmR encodes "width - 1".
1357 def bfi32_width_asmoperand : AsmOperandClass {
1358 let Name = "BFI32Width";
1359 let PredicateMethod = "isBitfieldWidth<32>";
1360 let RenderMethod = "addBFIWidthOperands";
1361 let DiagnosticType = "Width32";
1364 def bfi32_width : Operand<i64>,
1365 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
1366 let PrintMethod = "printBFIWidthOperand";
1367 let ParserMatchClass = bfi32_width_asmoperand;
1370 def bfi64_width_asmoperand : AsmOperandClass {
1371 let Name = "BFI64Width";
1372 let PredicateMethod = "isBitfieldWidth<64>";
1373 let RenderMethod = "addBFIWidthOperands";
1374 let DiagnosticType = "Width64";
1377 def bfi64_width : Operand<i64>,
1378 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
1379 let PrintMethod = "printBFIWidthOperand";
1380 let ParserMatchClass = bfi64_width_asmoperand;
1383 multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
1384 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
1385 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1386 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1388 Sched<[WriteALU, ReadALU]> {
1389 // As above, no disassembler allowed.
1390 let isAsmParserOnly = 1;
1393 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
1394 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1395 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1397 Sched<[WriteALU, ReadALU]> {
1398 // As above, no disassembler allowed.
1399 let isAsmParserOnly = 1;
1403 defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">;
1404 defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">;
1407 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1408 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1409 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1410 Sched<[WriteALU, ReadALU]> {
1411 // As above, no disassembler allowed.
1412 let isAsmParserOnly = 1;
1413 let Constraints = "$src = $Rd";
1416 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1417 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1418 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1419 Sched<[WriteALU, ReadALU]> {
1420 // As above, no disassembler allowed.
1421 let isAsmParserOnly = 1;
1422 let Constraints = "$src = $Rd";
1425 //===----------------------------------------------------------------------===//
1426 // Compare and branch (immediate)
1427 //===----------------------------------------------------------------------===//
1428 // Contains: CBZ, CBNZ
1430 class label_asmoperand<int width, int scale> : AsmOperandClass {
1431 let Name = "Label" # width # "_" # scale;
1432 let PredicateMethod = "isLabel<" # width # "," # scale # ">";
1433 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
1434 let DiagnosticType = "Label";
1437 def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>;
1439 // All conditional immediate branches are the same really: 19 signed bits scaled
1440 // by the instruction-size (4).
1441 def bcc_target : Operand<OtherVT> {
1442 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
1443 let ParserMatchClass = label_wid19_scal4_asmoperand;
1444 let PrintMethod = "printLabelOperand<19, 4>";
1445 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>";
1446 let OperandType = "OPERAND_PCREL";
1449 multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
1450 let isBranch = 1, isTerminator = 1 in {
1451 def x : A64I_cmpbr<0b1, op,
1453 (ins GPR64:$Rt, bcc_target:$Label),
1454 !strconcat(asmop,"\t$Rt, $Label"),
1455 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
1457 Sched<[WriteBr, ReadBr]>;
1459 def w : A64I_cmpbr<0b0, op,
1461 (ins GPR32:$Rt, bcc_target:$Label),
1462 !strconcat(asmop,"\t$Rt, $Label"),
1463 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
1465 Sched<[WriteBr, ReadBr]>;
1469 defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{
1470 return Imm == A64CC::EQ;
1472 defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{
1473 return Imm == A64CC::NE;
1476 //===----------------------------------------------------------------------===//
1477 // Conditional branch (immediate) instructions
1478 //===----------------------------------------------------------------------===//
1481 def cond_code_asmoperand : AsmOperandClass {
1482 let Name = "CondCode";
1483 let DiagnosticType = "CondCode";
1486 def cond_code : Operand<i32>, ImmLeaf<i32, [{
1487 return Imm >= 0 && Imm <= 15;
1489 let PrintMethod = "printCondCodeOperand";
1490 let ParserMatchClass = cond_code_asmoperand;
1493 def Bcc : A64I_condbr<0b0, 0b0, (outs),
1494 (ins cond_code:$Cond, bcc_target:$Label),
1495 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1500 let isTerminator = 1;
1503 //===----------------------------------------------------------------------===//
1504 // Conditional compare (immediate) instructions
1505 //===----------------------------------------------------------------------===//
1506 // Contains: CCMN, CCMP
1508 def uimm4_asmoperand : AsmOperandClass {
1510 let PredicateMethod = "isUImm<4>";
1511 let RenderMethod = "addImmOperands";
1512 let DiagnosticType = "UImm4";
1515 def uimm4 : Operand<i32> {
1516 let ParserMatchClass = uimm4_asmoperand;
1519 def uimm5 : Operand<i32> {
1520 let ParserMatchClass = uimm5_asmoperand;
1523 // The only difference between this operand and the one for instructions like
1524 // B.cc is that it's parsed manually. The other get parsed implicitly as part of
1525 // the mnemonic handling.
1526 def cond_code_op_asmoperand : AsmOperandClass {
1527 let Name = "CondCodeOp";
1528 let RenderMethod = "addCondCodeOperands";
1529 let PredicateMethod = "isCondCode";
1530 let ParserMethod = "ParseCondCodeOperand";
1531 let DiagnosticType = "CondCode";
1534 def cond_code_op : Operand<i32> {
1535 let PrintMethod = "printCondCodeOperand";
1536 let ParserMatchClass = cond_code_op_asmoperand;
1539 class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1540 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
1541 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
1542 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1544 Sched<[WriteCMP, ReadCMP]> {
1548 def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">;
1549 def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">;
1550 def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">;
1551 def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">;
1553 //===----------------------------------------------------------------------===//
1554 // Conditional compare (register) instructions
1555 //===----------------------------------------------------------------------===//
1556 // Contains: CCMN, CCMP
1558 class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop>
1559 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1,
1561 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
1562 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
1567 def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">;
1568 def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">;
1569 def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">;
1570 def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">;
1572 //===----------------------------------------------------------------------===//
1573 // Conditional select instructions
1574 //===----------------------------------------------------------------------===//
1575 // Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG
1577 // Condition code which is encoded as the inversion (semantically rather than
1578 // bitwise) in the instruction.
1579 def inv_cond_code_op_asmoperand : AsmOperandClass {
1580 let Name = "InvCondCodeOp";
1581 let RenderMethod = "addInvCondCodeOperands";
1582 let PredicateMethod = "isCondCode";
1583 let ParserMethod = "ParseCondCodeOperand";
1584 let DiagnosticType = "CondCode";
1587 def inv_cond_code_op : Operand<i32> {
1588 let ParserMatchClass = inv_cond_code_op_asmoperand;
1591 // Having a separate operand for the selectable use-case is debatable, but gives
1592 // consistency with cond_code.
1593 def inv_cond_XFORM : SDNodeXForm<imm, [{
1594 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue());
1595 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32);
1599 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>;
1602 multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
1603 SDPatternOperator select> {
1604 let Uses = [NZCV] in {
1605 def wwwc : A64I_condsel<0b0, op, 0b0, op2,
1607 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
1608 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1609 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
1611 Sched<[WriteCMP, ReadCMP]>;
1614 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
1616 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
1617 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
1618 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
1620 Sched<[WriteCMP, ReadCMP]>;
1625 : PatFrag<(ops node:$lhs, node:$rhs),
1626 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>;
1628 class complex_select<SDPatternOperator opnode>
1629 : PatFrag<(ops node:$lhs, node:$rhs),
1630 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>;
1633 defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>;
1634 defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc",
1635 complex_select<PatFrag<(ops node:$val),
1636 (add node:$val, 1)>>>;
1637 defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>;
1638 defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>;
1640 // Now the instruction aliases, which fit nicely into LLVM's model:
1642 def : InstAlias<"cset $Rd, $Cond",
1643 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1644 def : InstAlias<"cset $Rd, $Cond",
1645 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1646 def : InstAlias<"csetm $Rd, $Cond",
1647 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>;
1648 def : InstAlias<"csetm $Rd, $Cond",
1649 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>;
1650 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1651 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1652 def : InstAlias<"cinc $Rd, $Rn, $Cond",
1653 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1654 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1655 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1656 def : InstAlias<"cinv $Rd, $Rn, $Cond",
1657 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1658 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1659 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>;
1660 def : InstAlias<"cneg $Rd, $Rn, $Cond",
1661 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>;
1663 // Finally some helper patterns.
1665 // For CSET (a.k.a. zero-extension of icmp)
1666 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1667 (CSINCwwwc WZR, WZR, cond_code:$Cond)>;
1668 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1669 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>;
1671 def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond),
1672 (CSINCxxxc XZR, XZR, cond_code:$Cond)>;
1673 def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond),
1674 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>;
1676 // For CSETM (a.k.a. sign-extension of icmp)
1677 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1678 (CSINVwwwc WZR, WZR, cond_code:$Cond)>;
1679 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1680 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>;
1682 def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond),
1683 (CSINVxxxc XZR, XZR, cond_code:$Cond)>;
1684 def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond),
1685 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>;
1687 // CINC, CINV and CNEG get dealt with automatically, which leaves the issue of
1688 // commutativity. The instructions are to complex for isCommutable to be used,
1689 // so we have to create the patterns manually:
1691 // No commutable pattern for CSEL since the commuted version is isomorphic.
1694 def :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond),
1695 (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1696 def :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond),
1697 (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1700 def :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1701 (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1702 def :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1703 (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1706 def :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond),
1707 (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>;
1708 def :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond),
1709 (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>;
1711 //===----------------------------------------------------------------------===//
1712 // Data Processing (1 source) instructions
1713 //===----------------------------------------------------------------------===//
1714 // Contains: RBIT, REV16, REV, REV32, CLZ, CLS.
1716 // We define an unary operator which always fails. We will use this to
1717 // define unary operators that cannot be matched.
1719 class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop,
1720 list<dag> patterns, RegisterClass GPRrc,
1721 InstrItinClass itin>:
1726 !strconcat(asmop, "\t$Rd, $Rn"),
1731 Sched<[WriteALU, ReadALU]>;
1733 multiclass A64I_dp_1src <bits<6> opcode, string asmop> {
1734 let hasSideEffects = 0 in {
1735 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>;
1736 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>;
1740 defm RBIT : A64I_dp_1src<0b000000, "rbit">;
1741 defm CLS : A64I_dp_1src<0b000101, "cls">;
1742 defm CLZ : A64I_dp_1src<0b000100, "clz">;
1744 def : Pat<(ctlz i32:$Rn), (CLZww $Rn)>;
1745 def : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>;
1746 def : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>;
1747 def : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>;
1749 def : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>;
1750 def : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>;
1751 def : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>;
1752 def : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>;
1755 def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev",
1756 [(set i32:$Rd, (bswap i32:$Rn))],
1757 GPR32, NoItinerary>;
1758 def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev",
1759 [(set i64:$Rd, (bswap i64:$Rn))],
1760 GPR64, NoItinerary>;
1761 def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32",
1762 [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))],
1763 GPR64, NoItinerary>;
1764 def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16",
1765 [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))],
1768 def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>;
1770 //===----------------------------------------------------------------------===//
1771 // Data Processing (2 sources) instructions
1772 //===----------------------------------------------------------------------===//
1773 // Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
1777 class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
1778 RegisterClass GPRsp,
1779 InstrItinClass itin>:
1783 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
1785 (ins GPRsp:$Rn, GPRsp:$Rm),
1788 Sched<[WriteALU, ReadALU, ReadALU]>;
1790 multiclass dp_2src_crc<bit c, string asmop> {
1791 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
1792 !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
1793 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
1794 !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
1795 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
1796 !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
1797 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
1798 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
1799 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
1803 multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
1804 def www : dp_2src_impl<0b0,
1808 (op i32:$Rn, (i64 (zext i32:$Rm))))],
1811 def xxx : dp_2src_impl<0b1,
1814 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1820 multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> {
1821 def www : dp_2src_impl<0b0,
1824 [(set i32:$Rd, (op i32:$Rn, i32:$Rm))],
1827 def xxx : dp_2src_impl<0b1,
1830 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))],
1835 // Here we define the data processing 2 source instructions.
1836 defm CRC32 : dp_2src_crc<0b0, "crc32">;
1837 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
1839 let SchedRW = [WriteDiv, ReadDiv, ReadDiv] in {
1840 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1841 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1844 let SchedRW = [WriteALUs, ReadALU, ReadALU] in {
1845 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1846 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1847 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1848 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1851 // Extra patterns for an incoming 64-bit value for a 32-bit
1852 // operation. Since the LLVM operations are undefined (as in C) if the
1853 // RHS is out of range, it's perfectly permissible to discard the high
1854 // bits of the GPR64.
1855 def : Pat<(shl i32:$Rn, i64:$Rm),
1856 (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1857 def : Pat<(srl i32:$Rn, i64:$Rm),
1858 (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1859 def : Pat<(sra i32:$Rn, i64:$Rm),
1860 (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1861 def : Pat<(rotr i32:$Rn, i64:$Rm),
1862 (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>;
1864 // Here we define the aliases for the data processing 2 source instructions.
1865 def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">;
1866 def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">;
1867 def ASR_menmonic : MnemonicAlias<"asrv", "asr">;
1868 def ROR_menmonic : MnemonicAlias<"rorv", "ror">;
1870 //===----------------------------------------------------------------------===//
1871 // Data Processing (3 sources) instructions
1872 //===----------------------------------------------------------------------===//
1873 // Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH
1874 // + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL
1876 class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg,
1877 ValueType AccTy, RegisterClass SrcReg,
1878 string asmop, dag pattern>
1879 : A64I_dp3<sf, opcode,
1880 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
1881 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1882 [(set AccTy:$Rd, pattern)], NoItinerary>,
1883 Sched<[WriteMAC, ReadMAC, ReadMAC, ReadMAC]> {
1884 RegisterClass AccGPR = AccReg;
1885 RegisterClass SrcGPR = SrcReg;
1888 def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd",
1889 (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1890 def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd",
1891 (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1893 def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub",
1894 (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>;
1895 def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub",
1896 (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>;
1898 def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl",
1899 (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1900 def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl",
1901 (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1903 def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl",
1904 (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1905 def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl",
1906 (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1908 let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
1909 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
1910 (ins GPR64:$Rn, GPR64:$Rm),
1911 "umulh\t$Rd, $Rn, $Rm",
1912 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
1914 Sched<[WriteMAC, ReadMAC, ReadMAC]>;
1916 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
1917 (ins GPR64:$Rn, GPR64:$Rm),
1918 "smulh\t$Rd, $Rn, $Rm",
1919 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
1921 Sched<[WriteMAC, ReadMAC, ReadMAC]>;
1924 multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
1925 Register ZR, dag pattern> {
1926 def : InstAlias<asmop # " $Rd, $Rn, $Rm",
1927 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
1929 def : Pat<pattern, (INST $Rn, $Rm, ZR)>;
1932 defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>;
1933 defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>;
1935 defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR,
1936 (sub 0, (mul i32:$Rn, i32:$Rm))>;
1937 defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR,
1938 (sub 0, (mul i64:$Rn, i64:$Rm))>;
1940 defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
1941 (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>;
1942 defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
1943 (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>;
1945 defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
1946 (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>;
1947 defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
1948 (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>;
1951 //===----------------------------------------------------------------------===//
1952 // Exception generation
1953 //===----------------------------------------------------------------------===//
1954 // Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
1956 def uimm16_asmoperand : AsmOperandClass {
1957 let Name = "UImm16";
1958 let PredicateMethod = "isUImm<16>";
1959 let RenderMethod = "addImmOperands";
1960 let DiagnosticType = "UImm16";
1963 def uimm16 : Operand<i32> {
1964 let ParserMatchClass = uimm16_asmoperand;
1967 class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
1968 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
1969 !strconcat(asmop, "\t$UImm16"), [], NoItinerary>,
1972 let isTerminator = 1;
1975 def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">;
1976 def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">;
1977 def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">;
1978 def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">;
1979 def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">;
1981 def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">;
1982 def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">;
1983 def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">;
1985 // The immediate is optional for the DCPS instructions, defaulting to 0.
1986 def : InstAlias<"dcps1", (DCPS1i 0)>;
1987 def : InstAlias<"dcps2", (DCPS2i 0)>;
1988 def : InstAlias<"dcps3", (DCPS3i 0)>;
1990 //===----------------------------------------------------------------------===//
1991 // Extract (immediate)
1992 //===----------------------------------------------------------------------===//
1993 // Contains: EXTR + alias ROR
1995 def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0,
1997 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB),
1998 "extr\t$Rd, $Rn, $Rm, $LSB",
2000 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
2002 Sched<[WriteALU, ReadALU, ReadALU]>;
2003 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
2005 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
2006 "extr\t$Rd, $Rn, $Rm, $LSB",
2008 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
2010 Sched<[WriteALU, ReadALU, ReadALU]>;
2012 def : InstAlias<"ror $Rd, $Rs, $LSB",
2013 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
2014 def : InstAlias<"ror $Rd, $Rs, $LSB",
2015 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>;
2017 def : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB),
2018 (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>;
2019 def : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB),
2020 (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>;
2022 //===----------------------------------------------------------------------===//
2023 // Floating-point compare instructions
2024 //===----------------------------------------------------------------------===//
2025 // Contains: FCMP, FCMPE
2027 def fpzero_asmoperand : AsmOperandClass {
2028 let Name = "FPZero";
2029 let ParserMethod = "ParseFPImmOperand";
2030 let DiagnosticType = "FPZero";
2033 def fpz32 : Operand<f32>,
2034 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
2035 let ParserMatchClass = fpzero_asmoperand;
2036 let PrintMethod = "printFPZeroOperand";
2037 let DecoderMethod = "DecodeFPZeroOperand";
2040 def fpz64 : Operand<f64>,
2041 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
2042 let ParserMatchClass = fpzero_asmoperand;
2043 let PrintMethod = "printFPZeroOperand";
2044 let DecoderMethod = "DecodeFPZeroOperand";
2047 def fpz64movi : Operand<i64>,
2048 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
2049 let ParserMatchClass = fpzero_asmoperand;
2050 let PrintMethod = "printFPZeroOperand";
2051 let DecoderMethod = "DecodeFPZeroOperand";
2054 multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
2055 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
2056 (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
2058 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
2062 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
2063 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary>,
2064 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
2069 defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm),
2070 (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>;
2071 defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm),
2072 (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>;
2074 // What would be Rm should be written as 0; note that even though it's called
2075 // "$Rm" here to fit in with the InstrFormats, it's actually an immediate.
2076 defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm),
2077 (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>;
2079 defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm),
2080 (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>;
2083 //===----------------------------------------------------------------------===//
2084 // Floating-point conditional compare instructions
2085 //===----------------------------------------------------------------------===//
2086 // Contains: FCCMP, FCCMPE
2088 class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop>
2089 : A64I_fpccmp<0b0, 0b0, type, op,
2091 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
2092 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
2094 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
2098 def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">;
2099 def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">;
2100 def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">;
2101 def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">;
2103 //===----------------------------------------------------------------------===//
2104 // Floating-point conditional select instructions
2105 //===----------------------------------------------------------------------===//
2108 let Uses = [NZCV] in {
2109 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
2110 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
2111 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2113 (simple_select f32:$Rn, f32:$Rm))],
2115 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2118 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
2119 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond),
2120 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2122 (simple_select f64:$Rn, f64:$Rm))],
2124 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2127 //===----------------------------------------------------------------------===//
2128 // Floating-point data-processing (1 source)
2129 //===----------------------------------------------------------------------===//
2130 // Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI].
2132 def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val),
2133 [{ (void)N; return false; }]>;
2135 // First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
2136 // syntax. Default to no pattern because most are odd enough not to have one.
2137 multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
2138 SDPatternOperator opnode = FPNoUnop> {
2139 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
2140 !strconcat(asmstr, "\t$Rd, $Rn"),
2141 [(set f32:$Rd, (opnode f32:$Rn))],
2143 Sched<[WriteFPALU, ReadFPALU]>;
2145 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
2146 !strconcat(asmstr, "\t$Rd, $Rn"),
2147 [(set f64:$Rd, (opnode f64:$Rn))],
2149 Sched<[WriteFPALU, ReadFPALU]>;
2152 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
2153 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
2154 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2155 let SchedRW = [WriteFPSqrt, ReadFPSqrt] in {
2156 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2159 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
2160 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
2161 defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>;
2162 defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>;
2163 defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">;
2164 defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>;
2165 defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>;
2167 // The FCVT instrucitons have different source and destination register-types,
2168 // but the fields are uniform everywhere a D-register (say) crops up. Package
2169 // this information in a Record.
2170 class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
2171 RegisterClass Class = rc;
2177 def FCVT16 : FCVTRegType<FPR16, 0b11, f16>;
2178 def FCVT32 : FCVTRegType<FPR32, 0b00, f32>;
2179 def FCVT64 : FCVTRegType<FPR64, 0b01, f64>;
2181 class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode>
2182 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0},
2183 {0,0,0,1, DestReg.t1, DestReg.t0},
2184 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
2186 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>,
2187 Sched<[WriteFPALU, ReadFPALU]>;
2189 def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>;
2190 def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>;
2191 def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>;
2192 def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>;
2193 def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>;
2194 def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>;
2197 //===----------------------------------------------------------------------===//
2198 // Floating-point data-processing (2 sources) instructions
2199 //===----------------------------------------------------------------------===//
2200 // Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
2202 def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs),
2203 [{ (void)N; return false; }]>;
2205 multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
2206 SDPatternOperator opnode> {
2207 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
2209 (ins FPR32:$Rn, FPR32:$Rm),
2210 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2211 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
2213 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2215 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
2217 (ins FPR64:$Rn, FPR64:$Rm),
2218 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
2219 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
2221 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2224 let isCommutable = 1 in {
2225 let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
2226 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2228 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
2230 // No patterns for these.
2231 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>;
2232 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>;
2233 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
2234 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
2236 let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
2237 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2238 PatFrag<(ops node:$lhs, node:$rhs),
2239 (fneg (fmul node:$lhs, node:$rhs))> >;
2243 let SchedRW = [WriteFPDiv, ReadFPDiv, ReadFPDiv] in {
2244 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2246 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
2248 //===----------------------------------------------------------------------===//
2249 // Floating-point data-processing (3 sources) instructions
2250 //===----------------------------------------------------------------------===//
2251 // Contains: FMADD, FMSUB, FNMADD, FNMSUB
2253 def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2254 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>;
2255 def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2256 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>;
2257 def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra),
2258 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>;
2260 class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT,
2261 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind>
2262 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd),
2263 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
2264 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
2265 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
2267 Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]>;
2269 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
2270 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
2271 def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>;
2272 def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>;
2274 def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>;
2275 def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>;
2276 def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>;
2277 def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>;
2279 // Extra patterns for when we're allowed to optimise separate multiplication and
2281 let Predicates = [HasFPARMv8, UseFusedMAC] in {
2282 def : Pat<(f32 (fadd FPR32:$Ra, (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)))),
2283 (FMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2284 def : Pat<(f32 (fsub FPR32:$Ra, (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)))),
2285 (FMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2286 def : Pat<(f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)))),
2287 (FNMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2288 def : Pat<(f32 (fsub (f32 (fmul_su FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra)),
2289 (FNMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2291 def : Pat<(f64 (fadd FPR64:$Ra, (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)))),
2292 (FMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2293 def : Pat<(f64 (fsub FPR64:$Ra, (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)))),
2294 (FMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2295 def : Pat<(f64 (fsub (f64 (fneg FPR64:$Ra)), (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)))),
2296 (FNMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2297 def : Pat<(f64 (fsub (f64 (fmul_su FPR64:$Rn, FPR64:$Rm)), FPR64:$Ra)),
2298 (FNMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2302 //===----------------------------------------------------------------------===//
2303 // Floating-point <-> fixed-point conversion instructions
2304 //===----------------------------------------------------------------------===//
2305 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2307 // #1-#32 allowed, encoded as "64 - <specified imm>
2308 def fixedpos_asmoperand_i32 : AsmOperandClass {
2309 let Name = "CVTFixedPos32";
2310 let RenderMethod = "addCVTFixedPosOperands";
2311 let PredicateMethod = "isCVTFixedPos<32>";
2312 let DiagnosticType = "CVTFixedPos32";
2315 // Also encoded as "64 - <specified imm>" but #1-#64 allowed.
2316 def fixedpos_asmoperand_i64 : AsmOperandClass {
2317 let Name = "CVTFixedPos64";
2318 let RenderMethod = "addCVTFixedPosOperands";
2319 let PredicateMethod = "isCVTFixedPos<64>";
2320 let DiagnosticType = "CVTFixedPos64";
2323 // We need the cartesian product of f32/f64 i32/i64 operands for
2325 // + Selection needs to use operands of correct floating type
2326 // + Assembly parsing and decoding depend on integer width
2327 class cvtfix_i32_op<ValueType FloatVT>
2329 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
2330 let ParserMatchClass = fixedpos_asmoperand_i32;
2331 let DecoderMethod = "DecodeCVT32FixedPosOperand";
2332 let PrintMethod = "printCVTFixedPosOperand";
2335 class cvtfix_i64_op<ValueType FloatVT>
2337 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
2338 let ParserMatchClass = fixedpos_asmoperand_i64;
2339 let PrintMethod = "printCVTFixedPosOperand";
2342 // Because of the proliferation of weird operands, it's not really
2343 // worth going for a multiclass here. Oh well.
2345 class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode,
2346 RegisterClass GPR, RegisterClass FPR,
2347 ValueType DstTy, ValueType SrcTy,
2348 Operand scale_op, string asmop, SDNode cvtop>
2349 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode,
2350 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
2351 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2352 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
2354 Sched<[WriteFPALU, ReadFPALU]>;
2356 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
2357 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>;
2358 def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32,
2359 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>;
2360 def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32,
2361 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>;
2362 def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32,
2363 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>;
2365 def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64,
2366 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>;
2367 def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64,
2368 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>;
2369 def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64,
2370 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>;
2371 def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64,
2372 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>;
2375 class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode,
2376 RegisterClass FPR, RegisterClass GPR,
2377 ValueType DstTy, ValueType SrcTy,
2378 Operand scale_op, string asmop, SDNode cvtop>
2379 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode,
2380 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
2381 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
2382 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
2384 Sched<[WriteFPALU, ReadFPALU]>;
2386 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
2387 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>;
2388 def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64,
2389 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>;
2390 def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32,
2391 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>;
2392 def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64,
2393 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>;
2394 def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32,
2395 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>;
2396 def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64,
2397 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>;
2398 def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32,
2399 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>;
2400 def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64,
2401 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>;
2403 //===----------------------------------------------------------------------===//
2404 // Floating-point <-> integer conversion instructions
2405 //===----------------------------------------------------------------------===//
2406 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
2408 class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode,
2409 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
2410 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
2411 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>,
2412 Sched<[WriteFPALU, ReadFPALU]>;
2414 multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
2415 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
2416 GPR32, FPR32, asmop # "s">;
2417 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
2418 GPR64, FPR32, asmop # "s">;
2419 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
2420 GPR32, FPR32, asmop # "u">;
2421 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
2422 GPR64, FPR32, asmop # "u">;
2424 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
2425 GPR32, FPR64, asmop # "s">;
2426 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
2427 GPR64, FPR64, asmop # "s">;
2428 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
2429 GPR32, FPR64, asmop # "u">;
2430 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
2431 GPR64, FPR64, asmop # "u">;
2434 defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
2435 defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">;
2436 defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">;
2437 defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">;
2438 defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">;
2440 let Predicates = [HasFPARMv8] in {
2441 def : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>;
2442 def : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>;
2443 def : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>;
2444 def : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>;
2445 def : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>;
2446 def : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>;
2447 def : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>;
2448 def : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>;
2451 multiclass A64I_inttofp<bit o0, string asmop> {
2452 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
2453 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
2454 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
2455 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>;
2458 defm S : A64I_inttofp<0b0, "scvtf">;
2459 defm U : A64I_inttofp<0b1, "ucvtf">;
2461 let Predicates = [HasFPARMv8] in {
2462 def : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>;
2463 def : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>;
2464 def : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>;
2465 def : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>;
2466 def : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>;
2467 def : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>;
2468 def : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>;
2469 def : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>;
2472 def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">;
2473 def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">;
2474 def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">;
2475 def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">;
2477 let Predicates = [HasFPARMv8] in {
2478 def : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>;
2479 def : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>;
2480 def : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>;
2481 def : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>;
2484 def lane1_asmoperand : AsmOperandClass {
2486 let RenderMethod = "addImmOperands";
2487 let DiagnosticType = "Lane1";
2490 def lane1 : Operand<i32> {
2491 let ParserMatchClass = lane1_asmoperand;
2492 let PrintMethod = "printBareImmOperand";
2495 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
2496 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
2497 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2498 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>,
2499 Sched<[WriteFPALU, ReadFPALU]>;
2501 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
2502 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2503 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>,
2504 Sched<[WriteFPALU, ReadFPALU]>;
2507 let Predicates = [HasFPARMv8] in {
2508 def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]",
2509 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>;
2511 def : InstAlias<"fmov $Rd.2d[$Lane], $Rn",
2512 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>;
2515 //===----------------------------------------------------------------------===//
2516 // Floating-point immediate instructions
2517 //===----------------------------------------------------------------------===//
2520 def fpimm_asmoperand : AsmOperandClass {
2521 let Name = "FMOVImm";
2522 let ParserMethod = "ParseFPImmOperand";
2523 let DiagnosticType = "FPImm";
2526 // The MCOperand for these instructions are the encoded 8-bit values.
2527 def SDXF_fpimm : SDNodeXForm<fpimm, [{
2529 A64Imms::isFPImm(N->getValueAPF(), Imm8);
2530 return CurDAG->getTargetConstant(Imm8, MVT::i32);
2533 class fmov_operand<ValueType FT>
2535 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
2537 let PrintMethod = "printFPImmOperand";
2538 let ParserMatchClass = fpimm_asmoperand;
2541 def fmov32_operand : fmov_operand<f32>;
2542 def fmov64_operand : fmov_operand<f64>;
2544 class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT,
2545 Operand fmov_operand>
2546 : A64I_fpimm<0b0, 0b0, type, 0b00000,
2548 (ins fmov_operand:$Imm8),
2550 [(set VT:$Rd, fmov_operand:$Imm8)],
2552 Sched<[WriteFPALU]>;
2554 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
2555 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
2557 //===----------------------------------------------------------------------===//
2558 // Load-register (literal) instructions
2559 //===----------------------------------------------------------------------===//
2560 // Contains: LDR, LDRSW, PRFM
2562 def ldrlit_label_asmoperand : AsmOperandClass {
2563 let Name = "LoadLitLabel";
2564 let RenderMethod = "addLabelOperands<19, 4>";
2565 let DiagnosticType = "Label";
2568 def ldrlit_label : Operand<i64> {
2569 let EncoderMethod = "getLoadLitLabelOpValue";
2571 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
2572 let PrintMethod = "printLabelOperand<19, 4>";
2573 let ParserMatchClass = ldrlit_label_asmoperand;
2574 let OperandType = "OPERAND_PCREL";
2577 // Various instructions take an immediate value (which can always be used),
2578 // where some numbers have a symbolic name to make things easier. These operands
2579 // and the associated functions abstract away the differences.
2580 multiclass namedimm<string prefix, string mapper> {
2581 def _asmoperand : AsmOperandClass {
2582 let Name = "NamedImm" # prefix;
2583 let PredicateMethod = "isUImm";
2584 let RenderMethod = "addImmOperands";
2585 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
2586 let DiagnosticType = "NamedImm_" # prefix;
2589 def _op : Operand<i32> {
2590 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
2591 let PrintMethod = "printNamedImmOperand<" # mapper # ">";
2592 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
2596 defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">;
2598 class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg,
2599 list<dag> patterns = []>
2600 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
2601 "ldr\t$Rt, $Imm19", patterns, NoItinerary>,
2604 let mayLoad = 1 in {
2605 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
2606 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
2609 let Predicates = [HasFPARMv8] in {
2610 def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
2611 def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
2614 let mayLoad = 1 in {
2615 let Predicates = [HasFPARMv8] in {
2616 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
2619 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0,
2621 (ins ldrlit_label:$Imm19),
2622 "ldrsw\t$Rt, $Imm19",
2626 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
2627 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
2628 "prfm\t$Rt, $Imm19",
2633 //===----------------------------------------------------------------------===//
2634 // Load-store exclusive instructions
2635 //===----------------------------------------------------------------------===//
2636 // Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB,
2637 // STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB,
2638 // STLRH, STLR, LDARB, LDARH, LDAR
2640 // Since these instructions have the undefined register bits set to 1 in
2641 // their canonical form, we need a post encoder method to set those bits
2642 // to 1 when encoding these instructions. We do this using the
2643 // fixLoadStoreExclusive function. This function has template parameters:
2645 // fixLoadStoreExclusive<int hasRs, int hasRt2>
2647 // hasRs indicates that the instruction uses the Rs field, so we won't set
2648 // it to 1 (and the same for Rt2). We don't need template parameters for
2649 // the other register fiels since Rt and Rn are always used.
2651 // This operand parses a GPR64xsp register, followed by an optional immediate
2653 def GPR64xsp0_asmoperand : AsmOperandClass {
2654 let Name = "GPR64xsp0";
2655 let PredicateMethod = "isWrappedReg";
2656 let RenderMethod = "addRegOperands";
2657 let ParserMethod = "ParseLSXAddressOperand";
2658 // Diagnostics are provided by ParserMethod
2661 def GPR64xsp0 : RegisterOperand<GPR64xsp> {
2662 let ParserMatchClass = GPR64xsp0_asmoperand;
2665 //===----------------------------------
2666 // Store-exclusive (releasing & normal)
2667 //===----------------------------------
2669 class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2670 dag ins, list<dag> pat,
2671 InstrItinClass itin> :
2672 A64I_LDSTex_stn <size,
2673 opcode{2}, 0, opcode{1}, opcode{0},
2675 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
2678 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2679 let Constraints = "@earlyclobber $Rs";
2682 multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> {
2683 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2684 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2687 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2688 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2691 def _word: A64I_SRexs_impl<0b10, opcode, asmstr,
2692 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2695 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr,
2696 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2700 defm STXR : A64I_SRex<"stxr", 0b000, "STXR">;
2701 defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">;
2703 //===----------------------------------
2705 //===----------------------------------
2707 class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2708 dag ins, list<dag> pat,
2709 InstrItinClass itin> :
2710 A64I_LDSTex_tn <size,
2711 opcode{2}, 1, opcode{1}, opcode{0},
2713 !strconcat(asm, "\t$Rt, [$Rn]"),
2716 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2719 multiclass A64I_LRex<string asmstr, bits<3> opcode> {
2720 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2721 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2725 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2726 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2730 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
2731 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2735 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
2736 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2741 defm LDXR : A64I_LRex<"ldxr", 0b000>;
2742 defm LDAXR : A64I_LRex<"ldaxr", 0b001>;
2743 defm LDAR : A64I_LRex<"ldar", 0b101>;
2745 class acquiring_load<PatFrag base>
2746 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
2747 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2748 return Ordering == Acquire || Ordering == SequentiallyConsistent;
2751 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
2752 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
2753 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
2754 def atomic_load_acquire_64 : acquiring_load<atomic_load_64>;
2756 def : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>;
2757 def : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>;
2758 def : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>;
2759 def : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>;
2761 //===----------------------------------
2762 // Store-release (no exclusivity)
2763 //===----------------------------------
2765 class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2766 dag ins, list<dag> pat,
2767 InstrItinClass itin> :
2768 A64I_LDSTex_tn <size,
2769 opcode{2}, 0, opcode{1}, opcode{0},
2771 !strconcat(asm, "\t$Rt, [$Rn]"),
2774 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
2777 class releasing_store<PatFrag base>
2778 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
2779 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
2780 return Ordering == Release || Ordering == SequentiallyConsistent;
2783 def atomic_store_release_8 : releasing_store<atomic_store_8>;
2784 def atomic_store_release_16 : releasing_store<atomic_store_16>;
2785 def atomic_store_release_32 : releasing_store<atomic_store_32>;
2786 def atomic_store_release_64 : releasing_store<atomic_store_64>;
2788 multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> {
2789 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
2790 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2791 [(atomic_store_release_8 i64:$Rn, i32:$Rt)],
2794 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
2795 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2796 [(atomic_store_release_16 i64:$Rn, i32:$Rt)],
2799 def _word: A64I_SLexs_impl<0b10, opcode, asmstr,
2800 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn),
2801 [(atomic_store_release_32 i64:$Rn, i32:$Rt)],
2804 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr,
2805 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn),
2806 [(atomic_store_release_64 i64:$Rn, i64:$Rt)],
2810 defm STLR : A64I_SLex<"stlr", 0b101, "STLR">;
2812 //===----------------------------------
2813 // Store-exclusive pair (releasing & normal)
2814 //===----------------------------------
2816 class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2817 dag ins, list<dag> pat,
2818 InstrItinClass itin> :
2819 A64I_LDSTex_stt2n <size,
2820 opcode{2}, 0, opcode{1}, opcode{0},
2822 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
2828 multiclass A64I_SPex<string asmstr, bits<3> opcode> {
2829 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs),
2830 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2,
2834 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs),
2835 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2,
2840 defm STXP : A64I_SPex<"stxp", 0b010>;
2841 defm STLXP : A64I_SPex<"stlxp", 0b011>;
2843 //===----------------------------------
2844 // Load-exclusive pair (acquiring & normal)
2845 //===----------------------------------
2847 class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
2848 dag ins, list<dag> pat,
2849 InstrItinClass itin> :
2850 A64I_LDSTex_tt2n <size,
2851 opcode{2}, 1, opcode{1}, opcode{0},
2853 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
2856 let DecoderMethod = "DecodeLoadPairExclusiveInstruction";
2857 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
2860 multiclass A64I_LPex<string asmstr, bits<3> opcode> {
2861 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
2862 (outs GPR32:$Rt, GPR32:$Rt2),
2863 (ins GPR64xsp0:$Rn),
2867 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
2868 (outs GPR64:$Rt, GPR64:$Rt2),
2869 (ins GPR64xsp0:$Rn),
2874 defm LDXP : A64I_LPex<"ldxp", 0b010>;
2875 defm LDAXP : A64I_LPex<"ldaxp", 0b011>;
2877 //===----------------------------------------------------------------------===//
2878 // Load-store register (unscaled immediate) instructions
2879 //===----------------------------------------------------------------------===//
2880 // Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM
2884 //===----------------------------------------------------------------------===//
2885 // Load-store register (register offset) instructions
2886 //===----------------------------------------------------------------------===//
2887 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2891 //===----------------------------------------------------------------------===//
2892 // Load-store register (unsigned immediate) instructions
2893 //===----------------------------------------------------------------------===//
2894 // Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM
2898 //===----------------------------------------------------------------------===//
2899 // Load-store register (immediate post-indexed) instructions
2900 //===----------------------------------------------------------------------===//
2901 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2905 //===----------------------------------------------------------------------===//
2906 // Load-store register (immediate pre-indexed) instructions
2907 //===----------------------------------------------------------------------===//
2908 // Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW
2910 // Note that patterns are much later on in a completely separate section (they
2911 // need ADRPxi to be defined).
2913 //===-------------------------------
2914 // 1. Various operands needed
2915 //===-------------------------------
2917 //===-------------------------------
2918 // 1.1 Unsigned 12-bit immediate operands
2919 //===-------------------------------
2920 // The addressing mode for these instructions consists of an unsigned 12-bit
2921 // immediate which is scaled by the size of the memory access.
2923 // We represent this in the MC layer by two operands:
2924 // 1. A base register.
2925 // 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]"
2926 // would have '1' in this field.
2927 // This means that separate functions are needed for converting representations
2928 // which *are* aware of the intended access size.
2930 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
2931 // know the access size via some means. An isolated operand does not have this
2932 // information unless told from here, which means we need separate tablegen
2933 // Operands for each access size. This multiclass takes care of instantiating
2934 // the correct template functions in the rest of the backend.
2936 //===-------------------------------
2937 // 1.1 Unsigned 12-bit immediate operands
2938 //===-------------------------------
2940 multiclass offsets_uimm12<int MemSize, string prefix> {
2941 def uimm12_asmoperand : AsmOperandClass {
2942 let Name = "OffsetUImm12_" # MemSize;
2943 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
2944 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
2945 let DiagnosticType = "LoadStoreUImm12_" # MemSize;
2948 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which
2949 // complicates things beyond TableGen's ken.
2950 def uimm12 : Operand<i64>,
2951 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
2952 let ParserMatchClass
2953 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
2955 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">";
2956 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">";
2960 defm byte_ : offsets_uimm12<1, "byte_">;
2961 defm hword_ : offsets_uimm12<2, "hword_">;
2962 defm word_ : offsets_uimm12<4, "word_">;
2963 defm dword_ : offsets_uimm12<8, "dword_">;
2964 defm qword_ : offsets_uimm12<16, "qword_">;
2966 //===-------------------------------
2967 // 1.1 Signed 9-bit immediate operands
2968 //===-------------------------------
2970 // The MCInst is expected to store the bit-wise encoding of the value,
2971 // which amounts to lopping off the extended sign bits.
2972 def SDXF_simm9 : SDNodeXForm<imm, [{
2973 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
2976 def simm9_asmoperand : AsmOperandClass {
2978 let PredicateMethod = "isSImm<9>";
2979 let RenderMethod = "addSImmOperands<9>";
2980 let DiagnosticType = "LoadStoreSImm9";
2983 def simm9 : Operand<i64>,
2984 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
2986 let PrintMethod = "printOffsetSImm9Operand";
2987 let ParserMatchClass = simm9_asmoperand;
2991 //===-------------------------------
2992 // 1.3 Register offset extensions
2993 //===-------------------------------
2995 // The assembly-syntax for these addressing-modes is:
2996 // [<Xn|SP>, <R><m> {, <extend> {<amount>}}]
2998 // The essential semantics are:
2999 // + <amount> is a shift: #<log(transfer size)> or #0
3000 // + <R> can be W or X.
3001 // + If <R> is W, <extend> can be UXTW or SXTW
3002 // + If <R> is X, <extend> can be LSL or SXTX
3004 // The trickiest of those constraints is that Rm can be either GPR32 or GPR64,
3005 // which will need separate instructions for LLVM type-consistency. We'll also
3006 // need separate operands, of course.
3007 multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
3008 string Rm, string prefix> {
3009 def regext_asmoperand : AsmOperandClass {
3010 let Name = "AddrRegExtend_" # MemSize # "_" # Rm;
3011 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
3012 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
3013 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize;
3016 def regext : Operand<i64> {
3018 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
3020 let DecoderMethod = "DecodeAddrRegExtendOperand";
3021 let ParserMatchClass
3022 = !cast<AsmOperandClass>(prefix # regext_asmoperand);
3026 multiclass regexts_wx<int MemSize, string prefix> {
3027 // Rm is an X-register if LSL or SXTX are specified as the shift.
3028 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
3030 // Rm is a W-register if UXTW or SXTW are specified as the shift.
3031 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">;
3034 defm byte_ : regexts_wx<1, "byte_">;
3035 defm hword_ : regexts_wx<2, "hword_">;
3036 defm word_ : regexts_wx<4, "word_">;
3037 defm dword_ : regexts_wx<8, "dword_">;
3038 defm qword_ : regexts_wx<16, "qword_">;
3041 //===------------------------------
3042 // 2. The instructions themselves.
3043 //===------------------------------
3045 // We have the following instructions to implement:
3046 // | | B | H | W | X |
3047 // |-----------------+-------+-------+-------+--------|
3048 // | unsigned str | STRB | STRH | STR | STR |
3049 // | unsigned ldr | LDRB | LDRH | LDR | LDR |
3050 // | signed ldr to W | LDRSB | LDRSH | - | - |
3051 // | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) |
3053 // This will instantiate the LDR/STR instructions you'd expect to use for an
3054 // unsigned datatype (first two rows above) or floating-point register, which is
3055 // reasonably uniform across all access sizes.
3058 //===------------------------------
3059 // 2.1 Regular instructions
3060 //===------------------------------
3062 // This class covers the basic unsigned or irrelevantly-signed loads and stores,
3063 // to general-purpose and floating-point registers.
3065 class AddrParams<string prefix> {
3066 Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
3068 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
3069 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext");
3072 def byte_addrparams : AddrParams<"byte">;
3073 def hword_addrparams : AddrParams<"hword">;
3074 def word_addrparams : AddrParams<"word">;
3075 def dword_addrparams : AddrParams<"dword">;
3076 def qword_addrparams : AddrParams<"qword">;
3078 multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
3079 bit high_opc, string asmsuffix,
3080 RegisterClass GPR, AddrParams params> {
3081 // Unsigned immediate
3082 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
3083 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
3084 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
3088 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
3089 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3091 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
3092 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3093 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
3095 Sched<[WriteLd, ReadLd]> {
3098 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
3099 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3101 // Register offset (four of these: load/store and Wm/Xm).
3102 let mayLoad = 1 in {
3103 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
3105 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3106 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3108 Sched<[WriteLd, ReadLd, ReadLd]>;
3110 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1,
3112 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3113 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3115 Sched<[WriteLd, ReadLd, ReadLd]>;
3117 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
3118 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
3121 let mayStore = 1 in {
3122 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
3123 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
3124 params.regextWm:$Ext),
3125 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3128 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1,
3129 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm,
3130 params.regextXm:$Ext),
3131 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3134 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]",
3135 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn,
3138 // Unaligned immediate
3139 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
3140 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3141 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3145 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
3146 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3148 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
3149 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3150 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3152 Sched<[WriteLd, ReadLd]> {
3155 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
3156 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3159 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0},
3160 (outs GPR64xsp:$Rn_wb),
3161 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3162 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3164 let Constraints = "$Rn = $Rn_wb";
3167 // Decoder only needed for unpredictability checking (FIXME).
3168 let DecoderMethod = "DecodeSingleIndexedInstruction";
3171 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1},
3172 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3173 (ins GPR64xsp:$Rn, simm9:$SImm9),
3174 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3176 Sched<[WriteLd, ReadLd]> {
3178 let Constraints = "$Rn = $Rn_wb";
3179 let DecoderMethod = "DecodeSingleIndexedInstruction";
3183 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0},
3184 (outs GPR64xsp:$Rn_wb),
3185 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3186 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3188 let Constraints = "$Rn = $Rn_wb";
3191 // Decoder only needed for unpredictability checking (FIXME).
3192 let DecoderMethod = "DecodeSingleIndexedInstruction";
3195 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1},
3196 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
3197 (ins GPR64xsp:$Rn, simm9:$SImm9),
3198 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3200 Sched<[WriteLd, ReadLd]> {
3202 let Constraints = "$Rn = $Rn_wb";
3203 let DecoderMethod = "DecodeSingleIndexedInstruction";
3208 // STRB/LDRB: First define the instructions
3210 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>;
3214 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>;
3217 // STR/LDR to/from a W register
3219 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>;
3221 // STR/LDR to/from an X register
3223 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>;
3225 let Predicates = [HasFPARMv8] in {
3226 // STR/LDR to/from a B register
3228 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>;
3230 // STR/LDR to/from an H register
3232 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>;
3234 // STR/LDR to/from an S register
3236 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>;
3237 // STR/LDR to/from a D register
3239 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
3240 // STR/LDR to/from a Q register
3242 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
3246 //===------------------------------
3248 //===------------------------------
3250 // Byte and half-word signed loads can both go into either an X or a W register,
3251 // so it's worth factoring out. Signed word loads don't fit because there is no
3253 multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
3256 def w : A64I_LSunsigimm<size, 0b0, 0b11,
3258 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3259 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3261 Sched<[WriteLd, ReadLd]> {
3264 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3265 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3267 def x : A64I_LSunsigimm<size, 0b0, 0b10,
3269 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
3270 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3272 Sched<[WriteLd, ReadLd]> {
3275 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
3276 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3279 let mayLoad = 1 in {
3280 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
3282 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3283 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3285 Sched<[WriteLd, ReadLd, ReadLd]>;
3287 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1,
3289 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3290 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3292 Sched<[WriteLd, ReadLd, ReadLd]>;
3294 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0,
3296 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
3297 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3299 Sched<[WriteLd, ReadLd, ReadLd]>;
3301 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1,
3303 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
3304 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3306 Sched<[WriteLd, ReadLd, ReadLd]>;
3308 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3309 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
3312 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
3313 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn,
3317 let mayLoad = 1 in {
3319 def w_U : A64I_LSunalimm<size, 0b0, 0b11,
3321 (ins GPR64xsp:$Rn, simm9:$SImm9),
3322 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3324 Sched<[WriteLd, ReadLd]>;
3326 def x_U : A64I_LSunalimm<size, 0b0, 0b10,
3328 (ins GPR64xsp:$Rn, simm9:$SImm9),
3329 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3331 Sched<[WriteLd, ReadLd]>;
3335 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11,
3336 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3337 (ins GPR64xsp:$Rn, simm9:$SImm9),
3338 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3340 Sched<[WriteLd, ReadLd]> {
3341 let Constraints = "$Rn = $Rn_wb";
3342 let DecoderMethod = "DecodeSingleIndexedInstruction";
3345 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10,
3346 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3347 (ins GPR64xsp:$Rn, simm9:$SImm9),
3348 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3350 Sched<[WriteLd, ReadLd]> {
3351 let Constraints = "$Rn = $Rn_wb";
3352 let DecoderMethod = "DecodeSingleIndexedInstruction";
3356 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11,
3357 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
3358 (ins GPR64xsp:$Rn, simm9:$SImm9),
3359 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3361 Sched<[WriteLd, ReadLd]> {
3362 let Constraints = "$Rn = $Rn_wb";
3363 let DecoderMethod = "DecodeSingleIndexedInstruction";
3366 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10,
3367 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3368 (ins GPR64xsp:$Rn, simm9:$SImm9),
3369 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3371 Sched<[WriteLd, ReadLd]> {
3372 let Constraints = "$Rn = $Rn_wb";
3373 let DecoderMethod = "DecodeSingleIndexedInstruction";
3375 } // let mayLoad = 1
3379 defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">;
3381 defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">;
3383 // LDRSW: load a 32-bit register, sign-extending to 64-bits.
3385 : A64I_LSunsigimm<0b10, 0b0, 0b10,
3387 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
3388 "ldrsw\t$Rt, [$Rn, $UImm12]",
3390 Sched<[WriteLd, ReadLd]> {
3393 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3395 let mayLoad = 1 in {
3396 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
3398 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
3399 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3401 Sched<[WriteLd, ReadLd, ReadLd]>;
3403 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
3405 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
3406 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3408 Sched<[WriteLd, ReadLd, ReadLd]>;
3410 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
3411 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
3415 : A64I_LSunalimm<0b10, 0b0, 0b10,
3417 (ins GPR64xsp:$Rn, simm9:$SImm9),
3418 "ldursw\t$Rt, [$Rn, $SImm9]",
3420 Sched<[WriteLd, ReadLd]> {
3423 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3426 : A64I_LSpostind<0b10, 0b0, 0b10,
3427 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3428 (ins GPR64xsp:$Rn, simm9:$SImm9),
3429 "ldrsw\t$Rt, [$Rn], $SImm9",
3431 Sched<[WriteLd, ReadLd]> {
3433 let Constraints = "$Rn = $Rn_wb";
3434 let DecoderMethod = "DecodeSingleIndexedInstruction";
3437 def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10,
3438 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
3439 (ins GPR64xsp:$Rn, simm9:$SImm9),
3440 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3442 Sched<[WriteLd, ReadLd]> {
3444 let Constraints = "$Rn = $Rn_wb";
3445 let DecoderMethod = "DecodeSingleIndexedInstruction";
3448 //===------------------------------
3449 // 2.4 Prefetch operations
3450 //===------------------------------
3452 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
3453 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
3454 "prfm\t$Rt, [$Rn, $UImm12]",
3456 Sched<[WritePreLd, ReadPreLd]> {
3459 def : InstAlias<"prfm $Rt, [$Rn]",
3460 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3462 let mayLoad = 1 in {
3463 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
3464 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3465 GPR32:$Rm, dword_Wm_regext:$Ext),
3466 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3468 Sched<[WritePreLd, ReadPreLd]>;
3469 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
3470 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
3471 GPR64:$Rm, dword_Xm_regext:$Ext),
3472 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3474 Sched<[WritePreLd, ReadPreLd]>;
3477 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
3478 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn,
3482 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
3483 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3484 "prfum\t$Rt, [$Rn, $SImm9]",
3486 Sched<[WritePreLd, ReadPreLd]> {
3489 def : InstAlias<"prfum $Rt, [$Rn]",
3490 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
3492 //===----------------------------------------------------------------------===//
3493 // Load-store register (unprivileged) instructions
3494 //===----------------------------------------------------------------------===//
3495 // Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH
3497 // These instructions very much mirror the "unscaled immediate" loads, but since
3498 // there are no floating-point variants we need to split them out into their own
3499 // section to avoid instantiation of "ldtr d0, [sp]" etc.
3501 multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
3503 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
3504 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
3505 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3507 Sched<[WriteLd, ReadLd]> {
3511 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]",
3512 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3514 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
3515 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
3516 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3518 Sched<[WriteLd, ReadLd]> {
3522 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]",
3523 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
3527 // STTRB/LDTRB: First define the instructions
3528 defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">;
3531 defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">;
3533 // STTR/LDTR to/from a W register
3534 defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">;
3536 // STTR/LDTR to/from an X register
3537 defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">;
3539 // Now a class for the signed instructions that can go to either 32 or 64
3541 multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
3542 let mayLoad = 1 in {
3543 def w : A64I_LSunpriv<size, 0b0, 0b11,
3545 (ins GPR64xsp:$Rn, simm9:$SImm9),
3546 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3548 Sched<[WriteLd, ReadLd]>;
3550 def x : A64I_LSunpriv<size, 0b0, 0b10,
3552 (ins GPR64xsp:$Rn, simm9:$SImm9),
3553 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3555 Sched<[WriteLd, ReadLd]>;
3558 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3559 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>;
3561 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
3562 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3567 defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">;
3569 defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">;
3571 // And finally LDTRSW which only goes to 64 bits.
3572 def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10,
3574 (ins GPR64xsp:$Rn, simm9:$SImm9),
3575 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3577 Sched<[WriteLd, ReadLd]> {
3580 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
3582 //===----------------------------------------------------------------------===//
3583 // Load-store register pair (offset) instructions
3584 //===----------------------------------------------------------------------===//
3588 //===----------------------------------------------------------------------===//
3589 // Load-store register pair (post-indexed) instructions
3590 //===----------------------------------------------------------------------===//
3591 // Contains: STP, LDP, LDPSW
3595 //===----------------------------------------------------------------------===//
3596 // Load-store register pair (pre-indexed) instructions
3597 //===----------------------------------------------------------------------===//
3598 // Contains: STP, LDP, LDPSW
3602 //===----------------------------------------------------------------------===//
3603 // Load-store non-temporal register pair (offset) instructions
3604 //===----------------------------------------------------------------------===//
3605 // Contains: STNP, LDNP
3608 // Anything that creates an MCInst (Decoding, selection and AsmParsing) has to
3609 // know the access size via some means. An isolated operand does not have this
3610 // information unless told from here, which means we need separate tablegen
3611 // Operands for each access size. This multiclass takes care of instantiating
3612 // the correct template functions in the rest of the backend.
3614 multiclass offsets_simm7<string MemSize, string prefix> {
3615 // The bare signed 7-bit immediate is used in post-indexed instructions, but
3616 // because of the scaling performed a generic "simm7" operand isn't
3617 // appropriate here either.
3618 def simm7_asmoperand : AsmOperandClass {
3619 let Name = "SImm7_Scaled" # MemSize;
3620 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
3621 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
3622 let DiagnosticType = "LoadStoreSImm7_" # MemSize;
3625 def simm7 : Operand<i64> {
3626 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
3627 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
3631 defm word_ : offsets_simm7<"4", "word_">;
3632 defm dword_ : offsets_simm7<"8", "dword_">;
3633 defm qword_ : offsets_simm7<"16", "qword_">;
3635 multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
3636 Operand simm7, string prefix> {
3637 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
3638 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3639 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3640 Sched<[WriteLd, ReadLd]> {
3642 let DecoderMethod = "DecodeLDSTPairInstruction";
3644 def : InstAlias<"stp $Rt, $Rt2, [$Rn]",
3645 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt,
3646 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3648 def _LDR : A64I_LSPoffset<opc, v, 0b1,
3649 (outs SomeReg:$Rt, SomeReg:$Rt2),
3650 (ins GPR64xsp:$Rn, simm7:$SImm7),
3651 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3652 Sched<[WriteLd, ReadLd]> {
3654 let DecoderMethod = "DecodeLDSTPairInstruction";
3656 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]",
3657 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt,
3658 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3660 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0,
3661 (outs GPR64xsp:$Rn_wb),
3662 (ins SomeReg:$Rt, SomeReg:$Rt2,
3665 "stp\t$Rt, $Rt2, [$Rn], $SImm7",
3668 let Constraints = "$Rn = $Rn_wb";
3670 // Decoder only needed for unpredictability checking (FIXME).
3671 let DecoderMethod = "DecodeLDSTPairInstruction";
3674 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1,
3675 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3676 (ins GPR64xsp:$Rn, simm7:$SImm7),
3677 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3679 Sched<[WriteLd, ReadLd]> {
3681 let Constraints = "$Rn = $Rn_wb";
3682 let DecoderMethod = "DecodeLDSTPairInstruction";
3685 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
3686 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3687 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3690 let Constraints = "$Rn = $Rn_wb";
3691 let DecoderMethod = "DecodeLDSTPairInstruction";
3694 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1,
3695 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
3696 (ins GPR64xsp:$Rn, simm7:$SImm7),
3697 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3699 Sched<[WriteLd, ReadLd]> {
3701 let Constraints = "$Rn = $Rn_wb";
3702 let DecoderMethod = "DecodeLDSTPairInstruction";
3705 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
3706 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3707 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3709 let DecoderMethod = "DecodeLDSTPairInstruction";
3711 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]",
3712 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt,
3713 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3715 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
3716 (outs SomeReg:$Rt, SomeReg:$Rt2),
3717 (ins GPR64xsp:$Rn, simm7:$SImm7),
3718 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3719 Sched<[WriteLd, ReadLd]> {
3721 let DecoderMethod = "DecodeLDSTPairInstruction";
3723 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]",
3724 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt,
3725 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>;
3730 defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">;
3731 defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
3733 let Predicates = [HasFPARMv8] in {
3734 defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
3735 defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">;
3736 defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
3741 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
3742 (outs GPR64:$Rt, GPR64:$Rt2),
3743 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3744 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3745 Sched<[WriteLd, ReadLd]> {
3747 let DecoderMethod = "DecodeLDSTPairInstruction";
3749 def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]",
3750 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>;
3752 def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1,
3753 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3754 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3755 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
3758 let Constraints = "$Rn = $Rn_wb";
3759 let DecoderMethod = "DecodeLDSTPairInstruction";
3762 def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1,
3763 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
3764 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3765 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3767 Sched<[WriteLd, ReadLd]> {
3769 let Constraints = "$Rn = $Rn_wb";
3770 let DecoderMethod = "DecodeLDSTPairInstruction";
3773 //===----------------------------------------------------------------------===//
3774 // Logical (immediate) instructions
3775 //===----------------------------------------------------------------------===//
3776 // Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
3778 multiclass logical_imm_operands<string prefix, string note,
3779 int size, ValueType VT> {
3780 def _asmoperand : AsmOperandClass {
3781 let Name = "LogicalImm" # note # size;
3782 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
3783 let RenderMethod = "addLogicalImmOperands<" # size # ">";
3784 let DiagnosticType = "LogicalSecondSource";
3788 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
3789 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
3790 let PrintMethod = "printLogicalImmOperand<" # size # ">";
3791 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
3795 defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>;
3796 defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>;
3798 // The mov versions only differ in assembly parsing, where they
3799 // exclude values representable with either MOVZ or MOVN.
3800 defm logical_imm32_mov
3801 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>;
3802 defm logical_imm64_mov
3803 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
3806 multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
3807 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
3808 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3809 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3811 (opnode i32:$Rn, logical_imm32_operand:$Imm))],
3813 Sched<[WriteALU, ReadALU]>;
3815 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
3816 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3817 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3819 (opnode i64:$Rn, logical_imm64_operand:$Imm))],
3821 Sched<[WriteALU, ReadALU]>;
3824 defm AND : A64I_logimmSizes<0b00, "and", and>;
3825 defm ORR : A64I_logimmSizes<0b01, "orr", or>;
3826 defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
3828 let Defs = [NZCV] in {
3829 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
3830 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
3831 "ands\t$Rd, $Rn, $Imm",
3833 Sched<[WriteALU, ReadALU]>;
3835 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
3836 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
3837 "ands\t$Rd, $Rn, $Imm",
3839 Sched<[WriteALU, ReadALU]>;
3843 def : InstAlias<"tst $Rn, $Imm",
3844 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
3845 def : InstAlias<"tst $Rn, $Imm",
3846 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
3847 def : InstAlias<"mov $Rd, $Imm",
3848 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>;
3849 def : InstAlias<"mov $Rd, $Imm",
3850 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>;
3852 //===----------------------------------------------------------------------===//
3853 // Logical (shifted register) instructions
3854 //===----------------------------------------------------------------------===//
3855 // Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV
3857 // Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS"
3858 // behaves differently for unsigned comparisons, so we defensively only allow
3859 // signed or n/a as the operand. In practice "unsigned greater than 0" is "not
3860 // equal to 0" and LLVM gives us this.
3861 def signed_cond : PatLeaf<(cond), [{
3862 return !isUnsignedIntSetCC(N->get());
3866 // These instructions share their "shift" operands with add/sub (shifted
3867 // register instructions). They are defined there.
3869 // N.b. the commutable parameter is just !N. It will be first against the wall
3870 // when the revolution comes.
3871 multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
3872 bit N, bit commutable,
3873 string asmop, SDPatternOperator opfrag, ValueType ty,
3874 RegisterClass GPR, list<Register> defs> {
3875 let isCommutable = commutable, Defs = defs in {
3876 def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
3878 (ins GPR:$Rn, GPR:$Rm,
3879 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3880 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3881 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
3882 !cast<Operand>("lsl_operand_" # ty):$Imm6))
3885 Sched<[WriteALU, ReadALU, ReadALU]>;
3887 def _lsr : A64I_logicalshift<sf, opc, 0b01, N,
3889 (ins GPR:$Rn, GPR:$Rm,
3890 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3891 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3892 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
3893 !cast<Operand>("lsr_operand_" # ty):$Imm6))
3896 Sched<[WriteALU, ReadALU, ReadALU]>;
3898 def _asr : A64I_logicalshift<sf, opc, 0b10, N,
3900 (ins GPR:$Rn, GPR:$Rm,
3901 !cast<Operand>("asr_operand_" # ty):$Imm6),
3902 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3903 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
3904 !cast<Operand>("asr_operand_" # ty):$Imm6))
3907 Sched<[WriteALU, ReadALU, ReadALU]>;
3909 def _ror : A64I_logicalshift<sf, opc, 0b11, N,
3911 (ins GPR:$Rn, GPR:$Rm,
3912 !cast<Operand>("ror_operand_" # ty):$Imm6),
3913 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"),
3914 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
3915 !cast<Operand>("ror_operand_" # ty):$Imm6))
3918 Sched<[WriteALU, ReadALU, ReadALU]>;
3922 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
3923 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn,
3926 def : Pat<(opfrag ty:$Rn, ty:$Rm),
3927 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
3930 multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
3931 string asmop, SDPatternOperator opfrag,
3932 list<Register> defs> {
3933 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
3934 commutable, asmop, opfrag, i64, GPR64, defs>;
3935 defm www : logical_shifts<prefix # "www", 0b0, opc, N,
3936 commutable, asmop, opfrag, i32, GPR32, defs>;
3940 defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>;
3941 defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>;
3942 defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>;
3943 defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands",
3944 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs),
3945 [{ (void)N; return false; }]>,
3948 defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic",
3949 PatFrag<(ops node:$lhs, node:$rhs),
3950 (and node:$lhs, (not node:$rhs))>, []>;
3951 defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn",
3952 PatFrag<(ops node:$lhs, node:$rhs),
3953 (or node:$lhs, (not node:$rhs))>, []>;
3954 defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon",
3955 PatFrag<(ops node:$lhs, node:$rhs),
3956 (xor node:$lhs, (not node:$rhs))>, []>;
3957 defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics",
3958 PatFrag<(ops node:$lhs, node:$rhs),
3959 (and node:$lhs, (not node:$rhs)),
3960 [{ (void)N; return false; }]>,
3963 multiclass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
3964 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
3965 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
3967 (ins GPR:$Rn, GPR:$Rm,
3968 !cast<Operand>("lsl_operand_" # ty):$Imm6),
3969 "tst\t$Rn, $Rm, $Imm6",
3970 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
3971 !cast<Operand>("lsl_operand_" # ty):$Imm6)),
3974 Sched<[WriteALU, ReadALU, ReadALU]>;
3977 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0,
3979 (ins GPR:$Rn, GPR:$Rm,
3980 !cast<Operand>("lsr_operand_" # ty):$Imm6),
3981 "tst\t$Rn, $Rm, $Imm6",
3982 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
3983 !cast<Operand>("lsr_operand_" # ty):$Imm6)),
3986 Sched<[WriteALU, ReadALU, ReadALU]>;
3988 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0,
3990 (ins GPR:$Rn, GPR:$Rm,
3991 !cast<Operand>("asr_operand_" # ty):$Imm6),
3992 "tst\t$Rn, $Rm, $Imm6",
3993 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
3994 !cast<Operand>("asr_operand_" # ty):$Imm6)),
3997 Sched<[WriteALU, ReadALU, ReadALU]>;
3999 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0,
4001 (ins GPR:$Rn, GPR:$Rm,
4002 !cast<Operand>("ror_operand_" # ty):$Imm6),
4003 "tst\t$Rn, $Rm, $Imm6",
4004 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
4005 !cast<Operand>("ror_operand_" # ty):$Imm6)),
4008 Sched<[WriteALU, ReadALU, ReadALU]>;
4011 def _noshift : InstAlias<"tst $Rn, $Rm",
4012 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
4014 def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond),
4015 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>;
4018 defm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>;
4019 defm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>;
4022 multiclass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> {
4023 let isCommutable = 0, Rn = 0b11111 in {
4024 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
4027 !cast<Operand>("lsl_operand_" # ty):$Imm6),
4028 "mvn\t$Rd, $Rm, $Imm6",
4029 [(set ty:$Rd, (not (shl ty:$Rm,
4030 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
4032 Sched<[WriteALU, ReadALU, ReadALU]>;
4035 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1,
4038 !cast<Operand>("lsr_operand_" # ty):$Imm6),
4039 "mvn\t$Rd, $Rm, $Imm6",
4040 [(set ty:$Rd, (not (srl ty:$Rm,
4041 !cast<Operand>("lsr_operand_" # ty):$Imm6)))],
4043 Sched<[WriteALU, ReadALU, ReadALU]>;
4045 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1,
4048 !cast<Operand>("asr_operand_" # ty):$Imm6),
4049 "mvn\t$Rd, $Rm, $Imm6",
4050 [(set ty:$Rd, (not (sra ty:$Rm,
4051 !cast<Operand>("asr_operand_" # ty):$Imm6)))],
4053 Sched<[WriteALU, ReadALU, ReadALU]>;
4055 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1,
4058 !cast<Operand>("ror_operand_" # ty):$Imm6),
4059 "mvn\t$Rd, $Rm, $Imm6",
4060 [(set ty:$Rd, (not (rotr ty:$Rm,
4061 !cast<Operand>("lsl_operand_" # ty):$Imm6)))],
4063 Sched<[WriteALU, ReadALU, ReadALU]>;
4066 def _noshift : InstAlias<"mvn $Rn, $Rm",
4067 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>;
4069 def : Pat<(not ty:$Rm),
4070 (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>;
4073 defm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>;
4074 defm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>;
4076 def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>;
4077 def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>;
4079 //===----------------------------------------------------------------------===//
4080 // Move wide (immediate) instructions
4081 //===----------------------------------------------------------------------===//
4082 // Contains: MOVN, MOVZ, MOVK + MOV aliases
4084 // A wide variety of different relocations are needed for variants of these
4085 // instructions, so it turns out that we need a different operand for all of
4087 multiclass movw_operands<string prefix, string instname, int width> {
4088 def _imm_asmoperand : AsmOperandClass {
4089 let Name = instname # width # "Shifted" # shift;
4090 let PredicateMethod = "is" # instname # width # "Imm";
4091 let RenderMethod = "addMoveWideImmOperands";
4092 let ParserMethod = "ParseImmWithLSLOperand";
4093 let DiagnosticType = "MOVWUImm16";
4096 def _imm : Operand<i64> {
4097 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
4098 let PrintMethod = "printMoveWideImmOperand";
4099 let EncoderMethod = "getMoveWideImmOpValue";
4100 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">";
4102 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
4106 defm movn32 : movw_operands<"movn32", "MOVN", 32>;
4107 defm movn64 : movw_operands<"movn64", "MOVN", 64>;
4108 defm movz32 : movw_operands<"movz32", "MOVZ", 32>;
4109 defm movz64 : movw_operands<"movz64", "MOVZ", 64>;
4110 defm movk32 : movw_operands<"movk32", "MOVK", 32>;
4111 defm movk64 : movw_operands<"movk64", "MOVK", 64>;
4113 multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
4116 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
4117 !strconcat(asmop, "\t$Rd, $FullImm"),
4121 let UImm16 = FullImm{15-0};
4122 let Shift = FullImm{17-16};
4125 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
4126 !strconcat(asmop, "\t$Rd, $FullImm"),
4130 let UImm16 = FullImm{15-0};
4131 let Shift = FullImm{17-16};
4135 let isMoveImm = 1, isReMaterializable = 1,
4136 isAsCheapAsAMove = 1, hasSideEffects = 0 in {
4137 defm MOVN : A64I_movwSizes<0b00, "movn",
4138 (ins movn32_imm:$FullImm),
4139 (ins movn64_imm:$FullImm)>;
4141 // Some relocations are able to convert between a MOVZ and a MOVN. If these
4142 // are applied the instruction must be emitted with the corresponding bits as
4143 // 0, which means a MOVZ needs to override that bit from the default.
4144 let PostEncoderMethod = "fixMOVZ" in
4145 defm MOVZ : A64I_movwSizes<0b10, "movz",
4146 (ins movz32_imm:$FullImm),
4147 (ins movz64_imm:$FullImm)>;
4150 let Constraints = "$src = $Rd" in
4151 defm MOVK : A64I_movwSizes<0b11, "movk",
4152 (ins GPR32:$src, movk32_imm:$FullImm),
4153 (ins GPR64:$src, movk64_imm:$FullImm)>;
4156 // And now the "MOV" aliases. These also need their own operands because what
4157 // they accept is completely different to what the base instructions accept.
4158 multiclass movalias_operand<string prefix, string basename,
4159 string immpredicate, int width> {
4160 def _asmoperand : AsmOperandClass {
4161 let Name = basename # width # "MovAlias";
4163 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
4165 = "addMoveWideMovAliasOperands<" # width # ", "
4166 # "A64Imms::" # immpredicate # ">";
4169 def _movimm : Operand<i64> {
4170 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
4172 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
4176 defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>;
4177 defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>;
4178 defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>;
4179 defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>;
4181 // FIXME: these are officially canonical aliases, but TableGen is too limited to
4182 // print them at the moment. I believe in this case an "AliasPredicate" method
4183 // will need to be implemented. to allow it, as well as the more generally
4184 // useful handling of non-register, non-constant operands.
4185 class movalias<Instruction INST, RegisterClass GPR, Operand operand>
4186 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>;
4188 def : movalias<MOVZwii, GPR32, movz32_movimm>;
4189 def : movalias<MOVZxii, GPR64, movz64_movimm>;
4190 def : movalias<MOVNwii, GPR32, movn32_movimm>;
4191 def : movalias<MOVNxii, GPR64, movn64_movimm>;
4193 def movw_addressref_g0 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<0>">;
4194 def movw_addressref_g1 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<1>">;
4195 def movw_addressref_g2 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<2>">;
4196 def movw_addressref_g3 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<3>">;
4198 def : Pat<(A64WrapperLarge movw_addressref_g3:$G3, movw_addressref_g2:$G2,
4199 movw_addressref_g1:$G1, movw_addressref_g0:$G0),
4200 (MOVKxii (MOVKxii (MOVKxii (MOVZxii movw_addressref_g3:$G3),
4201 movw_addressref_g2:$G2),
4202 movw_addressref_g1:$G1),
4203 movw_addressref_g0:$G0)>;
4205 //===----------------------------------------------------------------------===//
4206 // PC-relative addressing instructions
4207 //===----------------------------------------------------------------------===//
4208 // Contains: ADR, ADRP
4210 def adr_label : Operand<i64> {
4211 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>";
4213 // This label is a 21-bit offset from PC, unscaled
4214 let PrintMethod = "printLabelOperand<21, 1>";
4215 let ParserMatchClass = label_asmoperand<21, 1>;
4216 let OperandType = "OPERAND_PCREL";
4219 def adrp_label_asmoperand : AsmOperandClass {
4220 let Name = "AdrpLabel";
4221 let RenderMethod = "addLabelOperands<21, 4096>";
4222 let DiagnosticType = "Label";
4225 def adrp_label : Operand<i64> {
4226 let EncoderMethod = "getAdrpLabelOpValue";
4228 // This label is a 21-bit offset from PC, scaled by the page-size: 4096.
4229 let PrintMethod = "printLabelOperand<21, 4096>";
4230 let ParserMatchClass = adrp_label_asmoperand;
4231 let OperandType = "OPERAND_PCREL";
4234 let hasSideEffects = 0 in {
4235 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
4236 "adr\t$Rd, $Label", [], NoItinerary>,
4239 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
4240 "adrp\t$Rd, $Label", [], NoItinerary>,
4244 //===----------------------------------------------------------------------===//
4245 // System instructions
4246 //===----------------------------------------------------------------------===//
4247 // Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS
4248 // + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
4250 // Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
4251 def uimm3_asmoperand : AsmOperandClass {
4253 let PredicateMethod = "isUImm<3>";
4254 let RenderMethod = "addImmOperands";
4255 let DiagnosticType = "UImm3";
4258 def uimm3 : Operand<i32> {
4259 let ParserMatchClass = uimm3_asmoperand;
4262 // The HINT alias can accept a simple unsigned 7-bit immediate.
4263 def uimm7_asmoperand : AsmOperandClass {
4265 let PredicateMethod = "isUImm<7>";
4266 let RenderMethod = "addImmOperands";
4267 let DiagnosticType = "UImm7";
4270 def uimm7 : Operand<i32> {
4271 let ParserMatchClass = uimm7_asmoperand;
4274 // Multiclass namedimm is defined with the prefetch operands. Most of these fit
4275 // into the NamedImmMapper scheme well: they either accept a named operand or
4276 // any immediate under a particular value (which may be 0, implying no immediate
4278 defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">;
4279 defm isb : namedimm<"isb", "A64ISB::ISBMapper">;
4280 defm ic : namedimm<"ic", "A64IC::ICMapper">;
4281 defm dc : namedimm<"dc", "A64DC::DCMapper">;
4282 defm at : namedimm<"at", "A64AT::ATMapper">;
4283 defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">;
4285 // However, MRS and MSR are more complicated for a few reasons:
4286 // * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
4287 // implementation-defined effect
4288 // * Most registers are shared, but some are read-only or write-only.
4289 // * There is a variant of MSR which accepts the same register name (SPSel),
4290 // but which would have a different encoding.
4292 // In principle these could be resolved in with more complicated subclasses of
4293 // NamedImmMapper, however that imposes an overhead on other "named
4294 // immediates". Both in concrete terms with virtual tables and in unnecessary
4297 // The solution adopted here is to take the MRS/MSR Mappers out of the usual
4298 // hierarchy (they're not derived from NamedImmMapper) and to add logic for
4299 // their special situation.
4300 def mrs_asmoperand : AsmOperandClass {
4302 let ParserMethod = "ParseSysRegOperand";
4303 let DiagnosticType = "MRS";
4306 def mrs_op : Operand<i32> {
4307 let ParserMatchClass = mrs_asmoperand;
4308 let PrintMethod = "printMRSOperand";
4309 let DecoderMethod = "DecodeMRSOperand";
4312 def msr_asmoperand : AsmOperandClass {
4313 let Name = "MSRWithReg";
4315 // Note that SPSel is valid for both this and the pstate operands, but with
4316 // different immediate encodings. This is why these operands provide a string
4317 // AArch64Operand rather than an immediate. The overlap is small enough that
4318 // it could be resolved with hackery now, but who can say in future?
4319 let ParserMethod = "ParseSysRegOperand";
4320 let DiagnosticType = "MSR";
4323 def msr_op : Operand<i32> {
4324 let ParserMatchClass = msr_asmoperand;
4325 let PrintMethod = "printMSROperand";
4326 let DecoderMethod = "DecodeMSROperand";
4329 def pstate_asmoperand : AsmOperandClass {
4330 let Name = "MSRPState";
4331 // See comment above about parser.
4332 let ParserMethod = "ParseSysRegOperand";
4333 let DiagnosticType = "MSR";
4336 def pstate_op : Operand<i32> {
4337 let ParserMatchClass = pstate_asmoperand;
4338 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
4339 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
4342 // When <CRn> is specified, an assembler should accept something like "C4", not
4343 // the usual "#4" immediate.
4344 def CRx_asmoperand : AsmOperandClass {
4346 let PredicateMethod = "isUImm<4>";
4347 let RenderMethod = "addImmOperands";
4348 let ParserMethod = "ParseCRxOperand";
4349 // Diagnostics are handled in all cases by ParseCRxOperand.
4352 def CRx : Operand<i32> {
4353 let ParserMatchClass = CRx_asmoperand;
4354 let PrintMethod = "printCRxOperand";
4358 // Finally, we can start defining the instructions.
4360 // HINT is straightforward, with a few aliases.
4361 def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
4364 let CRm = UImm7{6-3};
4365 let Op2 = UImm7{2-0};
4373 def : InstAlias<"nop", (HINTi 0)>;
4374 def : InstAlias<"yield", (HINTi 1)>;
4375 def : InstAlias<"wfe", (HINTi 2)>;
4376 def : InstAlias<"wfi", (HINTi 3)>;
4377 def : InstAlias<"sev", (HINTi 4)>;
4378 def : InstAlias<"sevl", (HINTi 5)>;
4380 // Quite a few instructions then follow a similar pattern of fixing common
4381 // fields in the bitpattern, we'll define a helper-class for them.
4382 class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
4383 Operand operand, string asmop>
4384 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
4394 def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">;
4395 def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">;
4396 def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">;
4397 def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">;
4399 def : InstAlias<"clrex", (CLREXi 0b1111)>;
4400 def : InstAlias<"isb", (ISBi 0b1111)>;
4402 // (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP
4403 // configurations at least.
4404 def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>;
4406 // Any SYS bitpattern can be represented with a complex and opaque "SYS"
4408 def SYSiccix : A64I_system<0b0, (outs),
4409 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
4410 uimm3:$Op2, GPR64:$Rt),
4411 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
4416 // You can skip the Xt argument whether it makes sense or not for the generic
4418 def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2",
4419 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>;
4422 // But many have aliases, which obviously don't fit into
4423 class SYSalias<dag ins, string asmstring>
4424 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
4425 let isAsmParserOnly = 1;
4429 let Op1 = SysOp{13-11};
4430 let CRn = SysOp{10-7};
4431 let CRm = SysOp{6-3};
4432 let Op2 = SysOp{2-0};
4435 def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
4437 def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
4441 def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">;
4442 def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">;
4444 def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
4446 def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
4451 def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
4452 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
4453 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
4458 // The instructions themselves are rather simple for MSR and MRS.
4459 def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
4460 "msr\t$SysReg, $Rt", [], NoItinerary> {
4462 let Op0 = SysReg{15-14};
4463 let Op1 = SysReg{13-11};
4464 let CRn = SysReg{10-7};
4465 let CRm = SysReg{6-3};
4466 let Op2 = SysReg{2-0};
4469 def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
4470 "mrs\t$Rt, $SysReg", [], NoItinerary> {
4472 let Op0 = SysReg{15-14};
4473 let Op1 = SysReg{13-11};
4474 let CRn = SysReg{10-7};
4475 let CRm = SysReg{6-3};
4476 let Op2 = SysReg{2-0};
4479 def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
4480 "msr\t$PState, $CRm", [], NoItinerary> {
4484 let Op1 = PState{5-3};
4486 let Op2 = PState{2-0};
4490 //===----------------------------------------------------------------------===//
4491 // Test & branch (immediate) instructions
4492 //===----------------------------------------------------------------------===//
4493 // Contains: TBZ, TBNZ
4495 // The bit to test is a simple unsigned 6-bit immediate in the X-register
4497 def uimm6 : Operand<i64> {
4498 let ParserMatchClass = uimm6_asmoperand;
4501 def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
4503 def tbimm_target : Operand<OtherVT> {
4504 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
4506 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
4507 let PrintMethod = "printLabelOperand<14, 4>";
4508 let ParserMatchClass = label_wid14_scal4_asmoperand;
4510 let OperandType = "OPERAND_PCREL";
4513 def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>;
4514 def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>;
4516 // These instructions correspond to patterns involving "and" with a power of
4517 // two, which we need to be able to select.
4518 def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
4519 def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
4521 let isBranch = 1, isTerminator = 1 in {
4522 def TBZxii : A64I_TBimm<0b0, (outs),
4523 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4524 "tbz\t$Rt, $Imm, $Label",
4525 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4530 def TBNZxii : A64I_TBimm<0b1, (outs),
4531 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
4532 "tbnz\t$Rt, $Imm, $Label",
4533 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
4539 // Note, these instructions overlap with the above 64-bit patterns. This is
4540 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both
4541 // do the same thing and are both permitted assembly. They also both have
4542 // sensible DAG patterns.
4543 def TBZwii : A64I_TBimm<0b0, (outs),
4544 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4545 "tbz\t$Rt, $Imm, $Label",
4546 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4553 def TBNZwii : A64I_TBimm<0b1, (outs),
4554 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label),
4555 "tbnz\t$Rt, $Imm, $Label",
4556 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
4564 //===----------------------------------------------------------------------===//
4565 // Unconditional branch (immediate) instructions
4566 //===----------------------------------------------------------------------===//
4569 def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
4571 def bimm_target : Operand<OtherVT> {
4572 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
4574 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4575 let PrintMethod = "printLabelOperand<26, 4>";
4576 let ParserMatchClass = label_wid26_scal4_asmoperand;
4578 let OperandType = "OPERAND_PCREL";
4581 def blimm_target : Operand<i64> {
4582 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
4584 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
4585 let PrintMethod = "printLabelOperand<26, 4>";
4586 let ParserMatchClass = label_wid26_scal4_asmoperand;
4588 let OperandType = "OPERAND_PCREL";
4591 class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type>
4592 : A64I_Bimm<op, (outs), (ins lbl_type:$Label),
4593 !strconcat(asmop, "\t$Label"), patterns,
4597 let isBranch = 1 in {
4598 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
4599 let isTerminator = 1;
4603 let SchedRW = [WriteBrL] in {
4604 def BLimm : A64I_BimmImpl<0b1, "bl",
4605 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4612 def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>;
4614 //===----------------------------------------------------------------------===//
4615 // Unconditional branch (register) instructions
4616 //===----------------------------------------------------------------------===//
4617 // Contains: BR, BLR, RET, ERET, DRP.
4619 // Most of the notional opcode fields in the A64I_Breg format are fixed in A64
4621 class A64I_BregImpl<bits<4> opc,
4622 dag outs, dag ins, string asmstr, list<dag> patterns,
4623 InstrItinClass itin = NoItinerary>
4624 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
4625 outs, ins, asmstr, patterns, itin>,
4628 let isIndirectBranch = 1;
4631 // Note that these are not marked isCall or isReturn because as far as LLVM is
4632 // concerned they're not. "ret" is just another jump unless it has been selected
4633 // by LLVM as the function's return.
4635 let isBranch = 1 in {
4636 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
4637 "br\t$Rn", [(brind i64:$Rn)]> {
4639 let isTerminator = 1;
4642 let SchedRW = [WriteBrL] in {
4643 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4644 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4651 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
4654 let isTerminator = 1;
4658 // Create a separate pseudo-instruction for codegen to use so that we don't
4659 // flag x30 as used in every function. It'll be restored before the RET by the
4660 // epilogue if it's legitimately used.
4661 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
4662 let isTerminator = 1;
4667 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
4670 let isTerminator = 1;
4674 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
4680 def RETAlias : InstAlias<"ret", (RETx X30)>;
4683 //===----------------------------------------------------------------------===//
4684 // Address generation patterns
4685 //===----------------------------------------------------------------------===//
4687 // Primary method of address generation for the small/absolute memory model is
4688 // an ADRP/ADR pair:
4689 // ADRP x0, some_variable
4690 // ADD x0, x0, #:lo12:some_variable
4692 // The load/store elision of the ADD is accomplished when selecting
4693 // addressing-modes. This just mops up the cases where that doesn't work and we
4694 // really need an address in some register.
4696 // This wrapper applies a LO12 modifier to the address. Otherwise we could just
4697 // use the same address.
4699 class ADRP_ADD<SDNode Wrapper, SDNode addrop>
4700 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)),
4701 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>;
4703 def : ADRP_ADD<A64WrapperSmall, tblockaddress>;
4704 def : ADRP_ADD<A64WrapperSmall, texternalsym>;
4705 def : ADRP_ADD<A64WrapperSmall, tglobaladdr>;
4706 def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>;
4707 def : ADRP_ADD<A64WrapperSmall, tjumptable>;
4708 def : ADRP_ADD<A64WrapperSmall, tconstpool>;
4710 //===----------------------------------------------------------------------===//
4711 // GOT access patterns
4712 //===----------------------------------------------------------------------===//
4714 class GOTLoadSmall<SDNode addrfrag>
4715 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)),
4716 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>;
4718 def : GOTLoadSmall<texternalsym>;
4719 def : GOTLoadSmall<tglobaladdr>;
4720 def : GOTLoadSmall<tglobaltlsaddr>;
4722 //===----------------------------------------------------------------------===//
4723 // Tail call handling
4724 //===----------------------------------------------------------------------===//
4726 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
4728 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
4729 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
4732 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff),
4733 [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>;
4736 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
4738 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
4739 (Bimm bimm_target:$Label)>;
4741 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [],
4746 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
4747 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>;
4749 //===----------------------------------------------------------------------===//
4750 // Thread local storage
4751 //===----------------------------------------------------------------------===//
4753 // This is a pseudo-instruction representing the ".tlsdesccall" directive in
4754 // assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the
4755 // current location. It should always be immediately followed by a BLR
4756 // instruction, and is intended solely for relaxation by the linker.
4758 def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
4760 def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
4761 let hasSideEffects = 1;
4764 def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
4765 [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> {
4770 def : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var),
4771 (TLSDESC_BLRx $Rn, texternalsym:$Var)>;
4773 //===----------------------------------------------------------------------===//
4774 // Bitfield patterns
4775 //===----------------------------------------------------------------------===//
4777 def bfi32_lsb_to_immr : SDNodeXForm<imm, [{
4778 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64);
4781 def bfi64_lsb_to_immr : SDNodeXForm<imm, [{
4782 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64);
4785 def bfi_width_to_imms : SDNodeXForm<imm, [{
4786 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64);
4790 // The simpler patterns deal with cases where no AND mask is actually needed
4791 // (either all bits are used or the low 32 bits are used).
4792 let AddedComplexity = 10 in {
4794 def : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4796 (bfi64_lsb_to_immr (i64 imm:$ImmR)),
4797 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4799 def : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS),
4801 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4802 (bfi_width_to_imms (i64 imm:$ImmS)))>;
4805 def : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS),
4807 (SUBREG_TO_REG (i64 0),
4808 (BFIwwii (EXTRACT_SUBREG $src, sub_32),
4809 (EXTRACT_SUBREG $Rn, sub_32),
4810 (bfi32_lsb_to_immr (i64 imm:$ImmR)),
4811 (bfi_width_to_imms (i64 imm:$ImmS))),
4816 //===----------------------------------------------------------------------===//
4817 // Miscellaneous patterns
4818 //===----------------------------------------------------------------------===//
4820 // Truncation from 64 to 32-bits just involves renaming your register.
4821 def : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>;
4823 // Similarly, extension where we don't care about the high bits is
4825 def : Pat<(i64 (anyext i32:$val)),
4826 (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>;
4828 // SELECT instructions providing f128 types need to be handled by a
4829 // pseudo-instruction since the eventual code will need to introduce basic
4830 // blocks and control flow.
4831 def F128CSEL : PseudoInst<(outs FPR128:$Rd),
4832 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
4833 [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> {
4835 let usesCustomInserter = 1;
4838 //===----------------------------------------------------------------------===//
4839 // Load/store patterns
4840 //===----------------------------------------------------------------------===//
4842 // There are lots of patterns here, because we need to allow at least three
4843 // parameters to vary independently.
4844 // 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ...
4845 // 2. LLVM source: zextloadi8, anyextloadi8, ...
4846 // 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ...
4848 // The biggest problem turns out to be the address-generation variable. At the
4849 // point of instantiation we need to produce two DAGs, one for the pattern and
4850 // one for the instruction. Doing this at the lowest level of classes doesn't
4853 // Consider the simple uimm12 addressing mode, and the desire to match both (add
4854 // GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the
4855 // instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or
4856 // "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this
4857 // operation, and PatFrags are for selection not output.
4859 // As a result, the address-generation patterns are the final
4860 // instantiations. However, we do still need to vary the operand for the address
4861 // further down (At the point we're deciding A64WrapperSmall, we don't know
4862 // the memory width of the operation).
4864 //===------------------------------
4865 // 1. Basic infrastructural defs
4866 //===------------------------------
4868 // First, some simple classes for !foreach and !subst to use:
4879 // You can't use !subst on an actual immediate, but you *can* use it on an
4880 // operand record that happens to match a single immediate. So we do.
4881 def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>;
4882 def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>;
4883 def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>;
4884 def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>;
4885 def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>;
4887 // If the low bits of a pointer are known to be 0 then an "or" is just as good
4888 // as addition for computing an offset. This fragment forwards that check for
4890 def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),
4892 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0));
4895 // Load/store (unsigned immediate) operations with relocations against global
4896 // symbols (for lo12) are only valid if those symbols have correct alignment
4897 // (since the immediate offset is divided by the access scale, it can't have a
4900 // The guaranteed alignment is provided as part of the WrapperSmall
4901 // operation, and checked against one of these.
4902 def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>;
4903 def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>;
4904 def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>;
4905 def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>;
4906 def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>;
4908 // "Normal" load/store instructions can be used on atomic operations, provided
4909 // the ordering parameter is at most "monotonic". Anything above that needs
4910 // special handling with acquire/release instructions.
4911 class simple_load<PatFrag base>
4912 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4913 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4916 def atomic_load_simple_i8 : simple_load<atomic_load_8>;
4917 def atomic_load_simple_i16 : simple_load<atomic_load_16>;
4918 def atomic_load_simple_i32 : simple_load<atomic_load_32>;
4919 def atomic_load_simple_i64 : simple_load<atomic_load_64>;
4921 class simple_store<PatFrag base>
4922 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4923 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic;
4926 def atomic_store_simple_i8 : simple_store<atomic_store_8>;
4927 def atomic_store_simple_i16 : simple_store<atomic_store_16>;
4928 def atomic_store_simple_i32 : simple_store<atomic_store_32>;
4929 def atomic_store_simple_i64 : simple_store<atomic_store_64>;
4931 //===------------------------------
4932 // 2. UImm12 and SImm9
4933 //===------------------------------
4935 // These instructions have two operands providing the address so they can be
4936 // treated similarly for most purposes.
4938 //===------------------------------
4939 // 2.1 Base patterns covering extend/truncate semantics
4940 //===------------------------------
4942 // Atomic patterns can be shared between integer operations of all sizes, a
4943 // quick multiclass here allows reuse.
4944 multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
4945 dag Offset, dag address, ValueType transty,
4947 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
4948 (LOAD Base, Offset)>;
4950 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
4951 (STORE $Rt, Base, Offset)>;
4954 // Instructions accessing a memory chunk smaller than a register (or, in a
4955 // pinch, the same size) have a characteristic set of patterns they want to
4956 // match: extending loads and truncating stores. This class deals with the
4957 // sign-neutral version of those patterns.
4959 // It will be instantiated across multiple addressing-modes.
4960 multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
4961 dag Base, dag Offset,
4962 dag address, ValueType sty>
4963 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> {
4964 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
4966 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
4968 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
4969 // register was actually set.
4970 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
4971 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4973 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
4974 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4976 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
4977 (STORE $Rt, Base, Offset)>;
4979 // For truncating store from 64-bits, we have to manually tell LLVM to
4980 // ignore the high bits of the x register.
4981 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
4982 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
4985 // Next come patterns for sign-extending loads.
4986 multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
4987 dag address, ValueType sty> {
4988 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
4989 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
4991 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
4992 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>;
4996 // and finally "natural-width" loads and stores come next.
4997 multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
4998 dag Offset, dag address, ValueType sty> {
4999 def : Pat<(sty (load address)), (LOAD Base, Offset)>;
5000 def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>;
5003 // Integer operations also get atomic instructions to select for.
5004 multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
5005 dag Offset, dag address, ValueType sty>
5006 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>,
5007 ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>;
5009 //===------------------------------
5010 // 2.2. Addressing-mode instantiations
5011 //===------------------------------
5013 multiclass uimm12_pats<dag address, dag Base, dag Offset> {
5014 defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
5015 !foreach(decls.pattern, Offset,
5016 !subst(OFFSET, byte_uimm12, decls.pattern)),
5017 !foreach(decls.pattern, address,
5018 !subst(OFFSET, byte_uimm12,
5019 !subst(ALIGN, any_align, decls.pattern))),
5021 defm : ls_small_pats<LS16_LDR, LS16_STR, Base,
5022 !foreach(decls.pattern, Offset,
5023 !subst(OFFSET, hword_uimm12, decls.pattern)),
5024 !foreach(decls.pattern, address,
5025 !subst(OFFSET, hword_uimm12,
5026 !subst(ALIGN, min_align2, decls.pattern))),
5028 defm : ls_small_pats<LS32_LDR, LS32_STR, Base,
5029 !foreach(decls.pattern, Offset,
5030 !subst(OFFSET, word_uimm12, decls.pattern)),
5031 !foreach(decls.pattern, address,
5032 !subst(OFFSET, word_uimm12,
5033 !subst(ALIGN, min_align4, decls.pattern))),
5036 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base,
5037 !foreach(decls.pattern, Offset,
5038 !subst(OFFSET, word_uimm12, decls.pattern)),
5039 !foreach(decls.pattern, address,
5040 !subst(OFFSET, word_uimm12,
5041 !subst(ALIGN, min_align4, decls.pattern))),
5044 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base,
5045 !foreach(decls.pattern, Offset,
5046 !subst(OFFSET, dword_uimm12, decls.pattern)),
5047 !foreach(decls.pattern, address,
5048 !subst(OFFSET, dword_uimm12,
5049 !subst(ALIGN, min_align8, decls.pattern))),
5052 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base,
5053 !foreach(decls.pattern, Offset,
5054 !subst(OFFSET, hword_uimm12, decls.pattern)),
5055 !foreach(decls.pattern, address,
5056 !subst(OFFSET, hword_uimm12,
5057 !subst(ALIGN, min_align2, decls.pattern))),
5060 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base,
5061 !foreach(decls.pattern, Offset,
5062 !subst(OFFSET, word_uimm12, decls.pattern)),
5063 !foreach(decls.pattern, address,
5064 !subst(OFFSET, word_uimm12,
5065 !subst(ALIGN, min_align4, decls.pattern))),
5068 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
5069 !foreach(decls.pattern, Offset,
5070 !subst(OFFSET, dword_uimm12, decls.pattern)),
5071 !foreach(decls.pattern, address,
5072 !subst(OFFSET, dword_uimm12,
5073 !subst(ALIGN, min_align8, decls.pattern))),
5076 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
5077 !foreach(decls.pattern, Offset,
5078 !subst(OFFSET, qword_uimm12, decls.pattern)),
5079 !foreach(decls.pattern, address,
5080 !subst(OFFSET, qword_uimm12,
5081 !subst(ALIGN, min_align16, decls.pattern))),
5084 defm : load_signed_pats<"B", "", Base,
5085 !foreach(decls.pattern, Offset,
5086 !subst(OFFSET, byte_uimm12, decls.pattern)),
5087 !foreach(decls.pattern, address,
5088 !subst(OFFSET, byte_uimm12,
5089 !subst(ALIGN, any_align, decls.pattern))),
5092 defm : load_signed_pats<"H", "", Base,
5093 !foreach(decls.pattern, Offset,
5094 !subst(OFFSET, hword_uimm12, decls.pattern)),
5095 !foreach(decls.pattern, address,
5096 !subst(OFFSET, hword_uimm12,
5097 !subst(ALIGN, min_align2, decls.pattern))),
5100 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5101 !subst(OFFSET, word_uimm12,
5102 !subst(ALIGN, min_align4, decls.pattern)))),
5103 (LDRSWx Base, !foreach(decls.pattern, Offset,
5104 !subst(OFFSET, word_uimm12, decls.pattern)))>;
5107 // Straightforward patterns of last resort: a pointer with or without an
5108 // appropriate offset.
5109 defm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>;
5110 defm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12),
5111 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
5113 // The offset could be hidden behind an "or", of course:
5114 defm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12),
5115 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>;
5117 // Global addresses under the small-absolute model should use these
5118 // instructions. There are ELF relocations specifically for it.
5119 defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
5120 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
5122 defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
5124 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
5126 // External symbols that make it this far should also get standard relocations.
5127 defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
5129 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
5131 defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
5132 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
5134 // We also want to use uimm12 instructions for local variables at the moment.
5135 def tframeindex_XFORM : SDNodeXForm<frameindex, [{
5136 int FI = cast<FrameIndexSDNode>(N)->getIndex();
5137 return CurDAG->getTargetFrameIndex(FI, MVT::i64);
5140 defm : uimm12_pats<(i64 frameindex:$Rn),
5141 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>;
5143 // These can be much simpler than uimm12 because we don't to change the operand
5144 // type (e.g. LDURB and LDURH take the same operands).
5145 multiclass simm9_pats<dag address, dag Base, dag Offset> {
5146 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
5147 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
5149 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>;
5150 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>;
5152 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>;
5153 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>;
5154 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>;
5155 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address,
5158 def : Pat<(i64 (zextloadi32 address)),
5159 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
5161 def : Pat<(truncstorei32 i64:$Rt, address),
5162 (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>;
5164 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>;
5165 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>;
5166 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>;
5169 defm : simm9_pats<(add i64:$Rn, simm9:$SImm9),
5170 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
5172 defm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9),
5173 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>;
5176 //===------------------------------
5177 // 3. Register offset patterns
5178 //===------------------------------
5180 // Atomic patterns can be shared between integer operations of all sizes, a
5181 // quick multiclass here allows reuse.
5182 multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
5183 dag Offset, dag Extend, dag address,
5184 ValueType transty, ValueType sty> {
5185 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
5186 (LOAD Base, Offset, Extend)>;
5188 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt),
5189 (STORE $Rt, Base, Offset, Extend)>;
5192 // The register offset instructions take three operands giving the instruction,
5193 // and have an annoying split between instructions where Rm is 32-bit and
5194 // 64-bit. So we need a special hierarchy to describe them. Other than that the
5195 // same operations should be supported as for simm9 and uimm12 addressing.
5197 multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
5198 dag Base, dag Offset, dag Extend,
5199 dag address, ValueType sty>
5200 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> {
5201 def : Pat<(!cast<SDNode>(zextload # sty) address),
5202 (LOAD Base, Offset, Extend)>;
5204 def : Pat<(!cast<SDNode>(extload # sty) address),
5205 (LOAD Base, Offset, Extend)>;
5207 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit
5208 // register was actually set.
5209 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)),
5210 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
5212 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)),
5213 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
5215 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address),
5216 (STORE $Rt, Base, Offset, Extend)>;
5218 // For truncating store from 64-bits, we have to manually tell LLVM to
5219 // ignore the high bits of the x register.
5220 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address),
5221 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>;
5225 // Next come patterns for sign-extending loads.
5226 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
5227 dag address, ValueType sty> {
5228 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
5229 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
5230 Base, Offset, Extend)>;
5232 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)),
5233 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
5234 Base, Offset, Extend)>;
5237 // and finally "natural-width" loads and stores come next.
5238 multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
5239 dag Base, dag Offset, dag Extend, dag address,
5241 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
5242 def : Pat<(store sty:$Rt, address),
5243 (STORE $Rt, Base, Offset, Extend)>;
5246 multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
5247 dag Base, dag Offset, dag Extend, dag address,
5249 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>,
5250 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>;
5252 multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
5254 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
5255 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
5256 Base, Offset, Extend,
5257 !foreach(decls.pattern, address,
5258 !subst(SHIFT, imm_eq0, decls.pattern)),
5260 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"),
5261 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"),
5262 Base, Offset, Extend,
5263 !foreach(decls.pattern, address,
5264 !subst(SHIFT, imm_eq1, decls.pattern)),
5266 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5267 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5268 Base, Offset, Extend,
5269 !foreach(decls.pattern, address,
5270 !subst(SHIFT, imm_eq2, decls.pattern)),
5273 defm : ro_int_neutral_pats<
5274 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
5275 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
5276 Base, Offset, Extend,
5277 !foreach(decls.pattern, address,
5278 !subst(SHIFT, imm_eq2, decls.pattern)),
5281 defm : ro_int_neutral_pats<
5282 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
5283 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
5284 Base, Offset, Extend,
5285 !foreach(decls.pattern, address,
5286 !subst(SHIFT, imm_eq3, decls.pattern)),
5289 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
5290 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
5291 Base, Offset, Extend,
5292 !foreach(decls.pattern, address,
5293 !subst(SHIFT, imm_eq1, decls.pattern)),
5296 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"),
5297 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"),
5298 Base, Offset, Extend,
5299 !foreach(decls.pattern, address,
5300 !subst(SHIFT, imm_eq2, decls.pattern)),
5303 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"),
5304 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"),
5305 Base, Offset, Extend,
5306 !foreach(decls.pattern, address,
5307 !subst(SHIFT, imm_eq3, decls.pattern)),
5310 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"),
5311 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"),
5312 Base, Offset, Extend,
5313 !foreach(decls.pattern, address,
5314 !subst(SHIFT, imm_eq4, decls.pattern)),
5317 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
5318 !foreach(decls.pattern, address,
5319 !subst(SHIFT, imm_eq0, decls.pattern)),
5322 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend,
5323 !foreach(decls.pattern, address,
5324 !subst(SHIFT, imm_eq1, decls.pattern)),
5327 def : Pat<(sextloadi32 !foreach(decls.pattern, address,
5328 !subst(SHIFT, imm_eq2, decls.pattern))),
5329 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset")
5330 Base, Offset, Extend)>;
5334 // Finally we're in a position to tell LLVM exactly what addresses are reachable
5335 // using register-offset instructions. Essentially a base plus a possibly
5336 // extended, possibly shifted (by access size) offset.
5338 defm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)),
5339 (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>;
5341 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)),
5342 (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>;
5344 defm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)),
5345 (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>;
5347 defm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)),
5348 (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>;
5350 defm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm),
5351 (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>;
5353 defm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)),
5354 (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>;
5356 //===----------------------------------------------------------------------===//
5357 // Advanced SIMD (NEON) Support
5360 include "AArch64InstrNEON.td"