1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe AArch64 instructions format here
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<2> val> {
21 def PseudoFrm : Format<0>;
22 def NormalFrm : Format<1>; // Do we need any others?
24 // AArch64 Instruction Format
25 class AArch64Inst<Format f, string cstr> : Instruction {
26 field bits<32> Inst; // Instruction encoding.
27 // Mask of bits that cause an encoding to be UNPREDICTABLE.
28 // If a bit is set, then if the corresponding bit in the
29 // target encoding differs from its value in the "Inst" field,
30 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
31 field bits<32> Unpredictable = 0;
32 // SoftFail is the generic name for this field, but we alias it so
33 // as to make it more obvious what it means in ARM-land.
34 field bits<32> SoftFail = Unpredictable;
35 let Namespace = "AArch64";
37 bits<2> Form = F.Value;
39 let Constraints = cstr;
42 // Pseudo instructions (don't have encoding information)
43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
44 : AArch64Inst<PseudoFrm, cstr> {
45 dag OutOperandList = oops;
46 dag InOperandList = iops;
47 let Pattern = pattern;
48 let isCodeGenOnly = 1;
51 // Real instructions (have encoding information)
52 class EncodedI<string cstr, list<dag> pattern> : AArch64Inst<NormalFrm, cstr> {
53 let Pattern = pattern;
57 // Normal instructions
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
60 : EncodedI<cstr, pattern> {
61 dag OutOperandList = oops;
62 dag InOperandList = iops;
63 let AsmString = !strconcat(asm, operands);
66 class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
67 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
68 class UnOpFrag<dag res> : PatFrag<(ops node:$LHS), res>;
70 // Helper fragment for an extract of the high portion of a 128-bit vector.
71 def extract_high_v16i8 :
72 UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
73 def extract_high_v8i16 :
74 UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
75 def extract_high_v4i32 :
76 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
77 def extract_high_v2i64 :
78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
80 //===----------------------------------------------------------------------===//
81 // Asm Operand Classes.
84 // Shifter operand for arithmetic shifted encodings.
85 def ShifterOperand : AsmOperandClass {
89 // Shifter operand for mov immediate encodings.
90 def MovImm32ShifterOperand : AsmOperandClass {
91 let SuperClasses = [ShifterOperand];
92 let Name = "MovImm32Shifter";
93 let RenderMethod = "addShifterOperands";
94 let DiagnosticType = "InvalidMovImm32Shift";
96 def MovImm64ShifterOperand : AsmOperandClass {
97 let SuperClasses = [ShifterOperand];
98 let Name = "MovImm64Shifter";
99 let RenderMethod = "addShifterOperands";
100 let DiagnosticType = "InvalidMovImm64Shift";
103 // Shifter operand for arithmetic register shifted encodings.
104 class ArithmeticShifterOperand<int width> : AsmOperandClass {
105 let SuperClasses = [ShifterOperand];
106 let Name = "ArithmeticShifter" # width;
107 let PredicateMethod = "isArithmeticShifter<" # width # ">";
108 let RenderMethod = "addShifterOperands";
109 let DiagnosticType = "AddSubRegShift" # width;
112 def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>;
113 def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>;
115 // Shifter operand for logical register shifted encodings.
116 class LogicalShifterOperand<int width> : AsmOperandClass {
117 let SuperClasses = [ShifterOperand];
118 let Name = "LogicalShifter" # width;
119 let PredicateMethod = "isLogicalShifter<" # width # ">";
120 let RenderMethod = "addShifterOperands";
121 let DiagnosticType = "AddSubRegShift" # width;
124 def LogicalShifterOperand32 : LogicalShifterOperand<32>;
125 def LogicalShifterOperand64 : LogicalShifterOperand<64>;
127 // Shifter operand for logical vector 128/64-bit shifted encodings.
128 def LogicalVecShifterOperand : AsmOperandClass {
129 let SuperClasses = [ShifterOperand];
130 let Name = "LogicalVecShifter";
131 let RenderMethod = "addShifterOperands";
133 def LogicalVecHalfWordShifterOperand : AsmOperandClass {
134 let SuperClasses = [LogicalVecShifterOperand];
135 let Name = "LogicalVecHalfWordShifter";
136 let RenderMethod = "addShifterOperands";
139 // The "MSL" shifter on the vector MOVI instruction.
140 def MoveVecShifterOperand : AsmOperandClass {
141 let SuperClasses = [ShifterOperand];
142 let Name = "MoveVecShifter";
143 let RenderMethod = "addShifterOperands";
146 // Extend operand for arithmetic encodings.
147 def ExtendOperand : AsmOperandClass {
149 let DiagnosticType = "AddSubRegExtendLarge";
151 def ExtendOperand64 : AsmOperandClass {
152 let SuperClasses = [ExtendOperand];
153 let Name = "Extend64";
154 let DiagnosticType = "AddSubRegExtendSmall";
156 // 'extend' that's a lsl of a 64-bit register.
157 def ExtendOperandLSL64 : AsmOperandClass {
158 let SuperClasses = [ExtendOperand];
159 let Name = "ExtendLSL64";
160 let RenderMethod = "addExtend64Operands";
161 let DiagnosticType = "AddSubRegExtendLarge";
164 // 8-bit floating-point immediate encodings.
165 def FPImmOperand : AsmOperandClass {
167 let ParserMethod = "tryParseFPImm";
168 let DiagnosticType = "InvalidFPImm";
171 def CondCode : AsmOperandClass {
172 let Name = "CondCode";
173 let DiagnosticType = "InvalidCondCode";
176 // A 32-bit register pasrsed as 64-bit
177 def GPR32as64Operand : AsmOperandClass {
178 let Name = "GPR32as64";
180 def GPR32as64 : RegisterOperand<GPR32> {
181 let ParserMatchClass = GPR32as64Operand;
184 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
185 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
186 // are encoded as the eight bit value 'abcdefgh'.
187 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
190 //===----------------------------------------------------------------------===//
191 // Operand Definitions.
194 // ADR[P] instruction labels.
195 def AdrpOperand : AsmOperandClass {
196 let Name = "AdrpLabel";
197 let ParserMethod = "tryParseAdrpLabel";
198 let DiagnosticType = "InvalidLabel";
200 def adrplabel : Operand<i64> {
201 let EncoderMethod = "getAdrLabelOpValue";
202 let PrintMethod = "printAdrpLabel";
203 let ParserMatchClass = AdrpOperand;
206 def AdrOperand : AsmOperandClass {
207 let Name = "AdrLabel";
208 let ParserMethod = "tryParseAdrLabel";
209 let DiagnosticType = "InvalidLabel";
211 def adrlabel : Operand<i64> {
212 let EncoderMethod = "getAdrLabelOpValue";
213 let ParserMatchClass = AdrOperand;
216 // simm9 predicate - True if the immediate is in the range [-256, 255].
217 def SImm9Operand : AsmOperandClass {
219 let DiagnosticType = "InvalidMemoryIndexedSImm9";
221 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
222 let ParserMatchClass = SImm9Operand;
225 // simm7sN predicate - True if the immediate is a multiple of N in the range
226 // [-64 * N, 63 * N].
227 class SImm7Scaled<int Scale> : AsmOperandClass {
228 let Name = "SImm7s" # Scale;
229 let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm7";
232 def SImm7s4Operand : SImm7Scaled<4>;
233 def SImm7s8Operand : SImm7Scaled<8>;
234 def SImm7s16Operand : SImm7Scaled<16>;
236 def simm7s4 : Operand<i32> {
237 let ParserMatchClass = SImm7s4Operand;
238 let PrintMethod = "printImmScale<4>";
241 def simm7s8 : Operand<i32> {
242 let ParserMatchClass = SImm7s8Operand;
243 let PrintMethod = "printImmScale<8>";
246 def simm7s16 : Operand<i32> {
247 let ParserMatchClass = SImm7s16Operand;
248 let PrintMethod = "printImmScale<16>";
251 def am_indexed7s8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S8", []>;
252 def am_indexed7s16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S16", []>;
253 def am_indexed7s32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S32", []>;
254 def am_indexed7s64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S64", []>;
255 def am_indexed7s128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S128", []>;
257 class AsmImmRange<int Low, int High> : AsmOperandClass {
258 let Name = "Imm" # Low # "_" # High;
259 let DiagnosticType = "InvalidImm" # Low # "_" # High;
262 def Imm1_8Operand : AsmImmRange<1, 8>;
263 def Imm1_16Operand : AsmImmRange<1, 16>;
264 def Imm1_32Operand : AsmImmRange<1, 32>;
265 def Imm1_64Operand : AsmImmRange<1, 64>;
267 def MovZSymbolG3AsmOperand : AsmOperandClass {
268 let Name = "MovZSymbolG3";
269 let RenderMethod = "addImmOperands";
272 def movz_symbol_g3 : Operand<i32> {
273 let ParserMatchClass = MovZSymbolG3AsmOperand;
276 def MovZSymbolG2AsmOperand : AsmOperandClass {
277 let Name = "MovZSymbolG2";
278 let RenderMethod = "addImmOperands";
281 def movz_symbol_g2 : Operand<i32> {
282 let ParserMatchClass = MovZSymbolG2AsmOperand;
285 def MovZSymbolG1AsmOperand : AsmOperandClass {
286 let Name = "MovZSymbolG1";
287 let RenderMethod = "addImmOperands";
290 def movz_symbol_g1 : Operand<i32> {
291 let ParserMatchClass = MovZSymbolG1AsmOperand;
294 def MovZSymbolG0AsmOperand : AsmOperandClass {
295 let Name = "MovZSymbolG0";
296 let RenderMethod = "addImmOperands";
299 def movz_symbol_g0 : Operand<i32> {
300 let ParserMatchClass = MovZSymbolG0AsmOperand;
303 def MovKSymbolG3AsmOperand : AsmOperandClass {
304 let Name = "MovKSymbolG3";
305 let RenderMethod = "addImmOperands";
308 def movk_symbol_g3 : Operand<i32> {
309 let ParserMatchClass = MovKSymbolG3AsmOperand;
312 def MovKSymbolG2AsmOperand : AsmOperandClass {
313 let Name = "MovKSymbolG2";
314 let RenderMethod = "addImmOperands";
317 def movk_symbol_g2 : Operand<i32> {
318 let ParserMatchClass = MovKSymbolG2AsmOperand;
321 def MovKSymbolG1AsmOperand : AsmOperandClass {
322 let Name = "MovKSymbolG1";
323 let RenderMethod = "addImmOperands";
326 def movk_symbol_g1 : Operand<i32> {
327 let ParserMatchClass = MovKSymbolG1AsmOperand;
330 def MovKSymbolG0AsmOperand : AsmOperandClass {
331 let Name = "MovKSymbolG0";
332 let RenderMethod = "addImmOperands";
335 def movk_symbol_g0 : Operand<i32> {
336 let ParserMatchClass = MovKSymbolG0AsmOperand;
339 class fixedpoint_i32<ValueType FloatVT>
341 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
342 let EncoderMethod = "getFixedPointScaleOpValue";
343 let DecoderMethod = "DecodeFixedPointScaleImm32";
344 let ParserMatchClass = Imm1_32Operand;
347 class fixedpoint_i64<ValueType FloatVT>
349 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
350 let EncoderMethod = "getFixedPointScaleOpValue";
351 let DecoderMethod = "DecodeFixedPointScaleImm64";
352 let ParserMatchClass = Imm1_64Operand;
355 def fixedpoint_f16_i32 : fixedpoint_i32<f16>;
356 def fixedpoint_f32_i32 : fixedpoint_i32<f32>;
357 def fixedpoint_f64_i32 : fixedpoint_i32<f64>;
359 def fixedpoint_f16_i64 : fixedpoint_i64<f16>;
360 def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
361 def fixedpoint_f64_i64 : fixedpoint_i64<f64>;
363 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
364 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
366 let EncoderMethod = "getVecShiftR8OpValue";
367 let DecoderMethod = "DecodeVecShiftR8Imm";
368 let ParserMatchClass = Imm1_8Operand;
370 def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
371 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
373 let EncoderMethod = "getVecShiftR16OpValue";
374 let DecoderMethod = "DecodeVecShiftR16Imm";
375 let ParserMatchClass = Imm1_16Operand;
377 def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
378 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
380 let EncoderMethod = "getVecShiftR16OpValue";
381 let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
382 let ParserMatchClass = Imm1_8Operand;
384 def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
385 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
387 let EncoderMethod = "getVecShiftR32OpValue";
388 let DecoderMethod = "DecodeVecShiftR32Imm";
389 let ParserMatchClass = Imm1_32Operand;
391 def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
392 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
394 let EncoderMethod = "getVecShiftR32OpValue";
395 let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
396 let ParserMatchClass = Imm1_16Operand;
398 def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
399 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
401 let EncoderMethod = "getVecShiftR64OpValue";
402 let DecoderMethod = "DecodeVecShiftR64Imm";
403 let ParserMatchClass = Imm1_64Operand;
405 def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
406 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
408 let EncoderMethod = "getVecShiftR64OpValue";
409 let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
410 let ParserMatchClass = Imm1_32Operand;
413 def Imm0_1Operand : AsmImmRange<0, 1>;
414 def Imm0_7Operand : AsmImmRange<0, 7>;
415 def Imm0_15Operand : AsmImmRange<0, 15>;
416 def Imm0_31Operand : AsmImmRange<0, 31>;
417 def Imm0_63Operand : AsmImmRange<0, 63>;
419 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
420 return (((uint32_t)Imm) < 8);
422 let EncoderMethod = "getVecShiftL8OpValue";
423 let DecoderMethod = "DecodeVecShiftL8Imm";
424 let ParserMatchClass = Imm0_7Operand;
426 def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
427 return (((uint32_t)Imm) < 16);
429 let EncoderMethod = "getVecShiftL16OpValue";
430 let DecoderMethod = "DecodeVecShiftL16Imm";
431 let ParserMatchClass = Imm0_15Operand;
433 def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
434 return (((uint32_t)Imm) < 32);
436 let EncoderMethod = "getVecShiftL32OpValue";
437 let DecoderMethod = "DecodeVecShiftL32Imm";
438 let ParserMatchClass = Imm0_31Operand;
440 def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
441 return (((uint32_t)Imm) < 64);
443 let EncoderMethod = "getVecShiftL64OpValue";
444 let DecoderMethod = "DecodeVecShiftL64Imm";
445 let ParserMatchClass = Imm0_63Operand;
449 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
450 // instructions for splatting repeating bit patterns across the immediate.
451 def logical_imm32_XFORM : SDNodeXForm<imm, [{
452 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
453 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
455 def logical_imm64_XFORM : SDNodeXForm<imm, [{
456 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
457 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
460 let DiagnosticType = "LogicalSecondSource" in {
461 def LogicalImm32Operand : AsmOperandClass {
462 let Name = "LogicalImm32";
464 def LogicalImm64Operand : AsmOperandClass {
465 let Name = "LogicalImm64";
467 def LogicalImm32NotOperand : AsmOperandClass {
468 let Name = "LogicalImm32Not";
470 def LogicalImm64NotOperand : AsmOperandClass {
471 let Name = "LogicalImm64Not";
474 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
475 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 32);
476 }], logical_imm32_XFORM> {
477 let PrintMethod = "printLogicalImm32";
478 let ParserMatchClass = LogicalImm32Operand;
480 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
481 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 64);
482 }], logical_imm64_XFORM> {
483 let PrintMethod = "printLogicalImm64";
484 let ParserMatchClass = LogicalImm64Operand;
486 def logical_imm32_not : Operand<i32> {
487 let ParserMatchClass = LogicalImm32NotOperand;
489 def logical_imm64_not : Operand<i64> {
490 let ParserMatchClass = LogicalImm64NotOperand;
493 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
494 def Imm0_65535Operand : AsmImmRange<0, 65535>;
495 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
496 return ((uint32_t)Imm) < 65536;
498 let ParserMatchClass = Imm0_65535Operand;
499 let PrintMethod = "printHexImm";
502 // imm0_255 predicate - True if the immediate is in the range [0,255].
503 def Imm0_255Operand : AsmOperandClass { let Name = "Imm0_255"; }
504 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
505 return ((uint32_t)Imm) < 256;
507 let ParserMatchClass = Imm0_255Operand;
508 let PrintMethod = "printHexImm";
511 // imm0_127 predicate - True if the immediate is in the range [0,127]
512 def Imm0_127Operand : AsmImmRange<0, 127>;
513 def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
514 return ((uint32_t)Imm) < 128;
516 let ParserMatchClass = Imm0_127Operand;
517 let PrintMethod = "printHexImm";
520 // NOTE: These imm0_N operands have to be of type i64 because i64 is the size
521 // for all shift-amounts.
523 // imm0_63 predicate - True if the immediate is in the range [0,63]
524 def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
525 return ((uint64_t)Imm) < 64;
527 let ParserMatchClass = Imm0_63Operand;
530 // imm0_31 predicate - True if the immediate is in the range [0,31]
531 def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
532 return ((uint64_t)Imm) < 32;
534 let ParserMatchClass = Imm0_31Operand;
537 // True if the 32-bit immediate is in the range [0,31]
538 def imm32_0_31 : Operand<i32>, ImmLeaf<i32, [{
539 return ((uint64_t)Imm) < 32;
541 let ParserMatchClass = Imm0_31Operand;
544 // imm0_1 predicate - True if the immediate is in the range [0,1]
545 def imm0_1 : Operand<i64>, ImmLeaf<i64, [{
546 return ((uint64_t)Imm) < 2;
548 let ParserMatchClass = Imm0_1Operand;
551 // imm0_15 predicate - True if the immediate is in the range [0,15]
552 def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
553 return ((uint64_t)Imm) < 16;
555 let ParserMatchClass = Imm0_15Operand;
558 // imm0_7 predicate - True if the immediate is in the range [0,7]
559 def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
560 return ((uint64_t)Imm) < 8;
562 let ParserMatchClass = Imm0_7Operand;
565 // imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15]
566 def imm32_0_15 : Operand<i32>, ImmLeaf<i32, [{
567 return ((uint32_t)Imm) < 16;
569 let ParserMatchClass = Imm0_15Operand;
572 // An arithmetic shifter operand:
573 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
575 class arith_shift<ValueType Ty, int width> : Operand<Ty> {
576 let PrintMethod = "printShifter";
577 let ParserMatchClass = !cast<AsmOperandClass>(
578 "ArithmeticShifterOperand" # width);
581 def arith_shift32 : arith_shift<i32, 32>;
582 def arith_shift64 : arith_shift<i64, 64>;
584 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
586 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
587 let PrintMethod = "printShiftedRegister";
588 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
591 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
592 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
594 // An arithmetic shifter operand:
595 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
597 class logical_shift<int width> : Operand<i32> {
598 let PrintMethod = "printShifter";
599 let ParserMatchClass = !cast<AsmOperandClass>(
600 "LogicalShifterOperand" # width);
603 def logical_shift32 : logical_shift<32>;
604 def logical_shift64 : logical_shift<64>;
606 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
608 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
609 let PrintMethod = "printShiftedRegister";
610 let MIOperandInfo = (ops regclass, shiftop);
613 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
614 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
616 // A logical vector shifter operand:
617 // {7-6} - shift type: 00 = lsl
618 // {5-0} - imm6: #0, #8, #16, or #24
619 def logical_vec_shift : Operand<i32> {
620 let PrintMethod = "printShifter";
621 let EncoderMethod = "getVecShifterOpValue";
622 let ParserMatchClass = LogicalVecShifterOperand;
625 // A logical vector half-word shifter operand:
626 // {7-6} - shift type: 00 = lsl
627 // {5-0} - imm6: #0 or #8
628 def logical_vec_hw_shift : Operand<i32> {
629 let PrintMethod = "printShifter";
630 let EncoderMethod = "getVecShifterOpValue";
631 let ParserMatchClass = LogicalVecHalfWordShifterOperand;
634 // A vector move shifter operand:
635 // {0} - imm1: #8 or #16
636 def move_vec_shift : Operand<i32> {
637 let PrintMethod = "printShifter";
638 let EncoderMethod = "getMoveVecShifterOpValue";
639 let ParserMatchClass = MoveVecShifterOperand;
642 let DiagnosticType = "AddSubSecondSource" in {
643 def AddSubImmOperand : AsmOperandClass {
644 let Name = "AddSubImm";
645 let ParserMethod = "tryParseAddSubImm";
647 def AddSubImmNegOperand : AsmOperandClass {
648 let Name = "AddSubImmNeg";
649 let ParserMethod = "tryParseAddSubImm";
652 // An ADD/SUB immediate shifter operand:
654 // {7-6} - shift type: 00 = lsl
655 // {5-0} - imm6: #0 or #12
656 class addsub_shifted_imm<ValueType Ty>
657 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
658 let PrintMethod = "printAddSubImm";
659 let EncoderMethod = "getAddSubImmOpValue";
660 let ParserMatchClass = AddSubImmOperand;
661 let MIOperandInfo = (ops i32imm, i32imm);
664 class addsub_shifted_imm_neg<ValueType Ty>
666 let EncoderMethod = "getAddSubImmOpValue";
667 let ParserMatchClass = AddSubImmNegOperand;
668 let MIOperandInfo = (ops i32imm, i32imm);
671 def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
672 def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
673 def addsub_shifted_imm32_neg : addsub_shifted_imm_neg<i32>;
674 def addsub_shifted_imm64_neg : addsub_shifted_imm_neg<i64>;
676 class neg_addsub_shifted_imm<ValueType Ty>
677 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
678 let PrintMethod = "printAddSubImm";
679 let EncoderMethod = "getAddSubImmOpValue";
680 let ParserMatchClass = AddSubImmOperand;
681 let MIOperandInfo = (ops i32imm, i32imm);
684 def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
685 def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;
687 // An extend operand:
688 // {5-3} - extend type
690 def arith_extend : Operand<i32> {
691 let PrintMethod = "printArithExtend";
692 let ParserMatchClass = ExtendOperand;
694 def arith_extend64 : Operand<i32> {
695 let PrintMethod = "printArithExtend";
696 let ParserMatchClass = ExtendOperand64;
699 // 'extend' that's a lsl of a 64-bit register.
700 def arith_extendlsl64 : Operand<i32> {
701 let PrintMethod = "printArithExtend";
702 let ParserMatchClass = ExtendOperandLSL64;
705 class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
706 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
707 let PrintMethod = "printExtendedRegister";
708 let MIOperandInfo = (ops GPR32, arith_extend);
711 class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
712 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
713 let PrintMethod = "printExtendedRegister";
714 let MIOperandInfo = (ops GPR32, arith_extend64);
717 // Floating-point immediate.
718 def fpimm16 : Operand<f16>,
719 PatLeaf<(f16 fpimm), [{
720 return AArch64_AM::getFP16Imm(N->getValueAPF()) != -1;
721 }], SDNodeXForm<fpimm, [{
722 APFloat InVal = N->getValueAPF();
723 uint32_t enc = AArch64_AM::getFP16Imm(InVal);
724 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
726 let ParserMatchClass = FPImmOperand;
727 let PrintMethod = "printFPImmOperand";
729 def fpimm32 : Operand<f32>,
730 PatLeaf<(f32 fpimm), [{
731 return AArch64_AM::getFP32Imm(N->getValueAPF()) != -1;
732 }], SDNodeXForm<fpimm, [{
733 APFloat InVal = N->getValueAPF();
734 uint32_t enc = AArch64_AM::getFP32Imm(InVal);
735 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
737 let ParserMatchClass = FPImmOperand;
738 let PrintMethod = "printFPImmOperand";
740 def fpimm64 : Operand<f64>,
741 PatLeaf<(f64 fpimm), [{
742 return AArch64_AM::getFP64Imm(N->getValueAPF()) != -1;
743 }], SDNodeXForm<fpimm, [{
744 APFloat InVal = N->getValueAPF();
745 uint32_t enc = AArch64_AM::getFP64Imm(InVal);
746 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
748 let ParserMatchClass = FPImmOperand;
749 let PrintMethod = "printFPImmOperand";
752 def fpimm8 : Operand<i32> {
753 let ParserMatchClass = FPImmOperand;
754 let PrintMethod = "printFPImmOperand";
757 def fpimm0 : PatLeaf<(fpimm), [{
758 return N->isExactlyValue(+0.0);
761 // Vector lane operands
762 class AsmVectorIndex<string Suffix> : AsmOperandClass {
763 let Name = "VectorIndex" # Suffix;
764 let DiagnosticType = "InvalidIndex" # Suffix;
766 def VectorIndex1Operand : AsmVectorIndex<"1">;
767 def VectorIndexBOperand : AsmVectorIndex<"B">;
768 def VectorIndexHOperand : AsmVectorIndex<"H">;
769 def VectorIndexSOperand : AsmVectorIndex<"S">;
770 def VectorIndexDOperand : AsmVectorIndex<"D">;
772 def VectorIndex1 : Operand<i64>, ImmLeaf<i64, [{
773 return ((uint64_t)Imm) == 1;
775 let ParserMatchClass = VectorIndex1Operand;
776 let PrintMethod = "printVectorIndex";
777 let MIOperandInfo = (ops i64imm);
779 def VectorIndexB : Operand<i64>, ImmLeaf<i64, [{
780 return ((uint64_t)Imm) < 16;
782 let ParserMatchClass = VectorIndexBOperand;
783 let PrintMethod = "printVectorIndex";
784 let MIOperandInfo = (ops i64imm);
786 def VectorIndexH : Operand<i64>, ImmLeaf<i64, [{
787 return ((uint64_t)Imm) < 8;
789 let ParserMatchClass = VectorIndexHOperand;
790 let PrintMethod = "printVectorIndex";
791 let MIOperandInfo = (ops i64imm);
793 def VectorIndexS : Operand<i64>, ImmLeaf<i64, [{
794 return ((uint64_t)Imm) < 4;
796 let ParserMatchClass = VectorIndexSOperand;
797 let PrintMethod = "printVectorIndex";
798 let MIOperandInfo = (ops i64imm);
800 def VectorIndexD : Operand<i64>, ImmLeaf<i64, [{
801 return ((uint64_t)Imm) < 2;
803 let ParserMatchClass = VectorIndexDOperand;
804 let PrintMethod = "printVectorIndex";
805 let MIOperandInfo = (ops i64imm);
808 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
809 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
810 // are encoded as the eight bit value 'abcdefgh'.
811 def simdimmtype10 : Operand<i32>,
812 PatLeaf<(f64 fpimm), [{
813 return AArch64_AM::isAdvSIMDModImmType10(N->getValueAPF()
816 }], SDNodeXForm<fpimm, [{
817 APFloat InVal = N->getValueAPF();
818 uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
821 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
823 let ParserMatchClass = SIMDImmType10Operand;
824 let PrintMethod = "printSIMDType10Operand";
832 // Base encoding for system instruction operands.
833 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
834 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
835 list<dag> pattern = []>
836 : I<oops, iops, asm, operands, "", pattern> {
837 let Inst{31-22} = 0b1101010100;
841 // System instructions which do not have an Rt register.
842 class SimpleSystemI<bit L, dag iops, string asm, string operands,
843 list<dag> pattern = []>
844 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
845 let Inst{4-0} = 0b11111;
848 // System instructions which have an Rt register.
849 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
850 : BaseSystemI<L, oops, iops, asm, operands>,
856 // Hint instructions that take both a CRm and a 3-bit immediate.
857 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
858 // model patterns with sufficiently fine granularity
859 let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
860 class HintI<string mnemonic>
861 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#"\t$imm", "",
862 [(int_aarch64_hint imm0_127:$imm)]>,
865 let Inst{20-12} = 0b000110010;
866 let Inst{11-5} = imm;
869 // System instructions taking a single literal operand which encodes into
870 // CRm. op2 differentiates the opcodes.
871 def BarrierAsmOperand : AsmOperandClass {
872 let Name = "Barrier";
873 let ParserMethod = "tryParseBarrierOperand";
875 def barrier_op : Operand<i32> {
876 let PrintMethod = "printBarrierOption";
877 let ParserMatchClass = BarrierAsmOperand;
879 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
880 list<dag> pattern = []>
881 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
882 Sched<[WriteBarrier]> {
884 let Inst{20-12} = 0b000110011;
885 let Inst{11-8} = CRm;
889 // MRS/MSR system instructions. These have different operand classes because
890 // a different subset of registers can be accessed through each instruction.
891 def MRSSystemRegisterOperand : AsmOperandClass {
892 let Name = "MRSSystemRegister";
893 let ParserMethod = "tryParseSysReg";
894 let DiagnosticType = "MRS";
896 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
897 def mrs_sysreg_op : Operand<i32> {
898 let ParserMatchClass = MRSSystemRegisterOperand;
899 let DecoderMethod = "DecodeMRSSystemRegister";
900 let PrintMethod = "printMRSSystemRegister";
903 def MSRSystemRegisterOperand : AsmOperandClass {
904 let Name = "MSRSystemRegister";
905 let ParserMethod = "tryParseSysReg";
906 let DiagnosticType = "MSR";
908 def msr_sysreg_op : Operand<i32> {
909 let ParserMatchClass = MSRSystemRegisterOperand;
910 let DecoderMethod = "DecodeMSRSystemRegister";
911 let PrintMethod = "printMSRSystemRegister";
914 def PSBHintOperand : AsmOperandClass {
915 let Name = "PSBHint";
916 let ParserMethod = "tryParsePSBHint";
918 def psbhint_op : Operand<i32> {
919 let ParserMatchClass = PSBHintOperand;
920 let PrintMethod = "printPSBHintOp";
921 let MCOperandPredicate = [{
922 // Check, if operand is valid, to fix exhaustive aliasing in disassembly.
923 // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
927 (void)AArch64PSBHint::PSBHintMapper().toString(MCOp.getImm(),
928 STI.getFeatureBits(), ValidNamed);
933 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
934 "mrs", "\t$Rt, $systemreg"> {
936 let Inst{20-5} = systemreg;
939 // FIXME: Some of these def NZCV, others don't. Best way to model that?
940 // Explicitly modeling each of the system register as a register class
941 // would do it, but feels like overkill at this point.
942 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
943 "msr", "\t$systemreg, $Rt"> {
945 let Inst{20-5} = systemreg;
948 def SystemPStateFieldWithImm0_15Operand : AsmOperandClass {
949 let Name = "SystemPStateFieldWithImm0_15";
950 let ParserMethod = "tryParseSysReg";
952 def pstatefield4_op : Operand<i32> {
953 let ParserMatchClass = SystemPStateFieldWithImm0_15Operand;
954 let PrintMethod = "printSystemPStateField";
958 class MSRpstateImm0_15
959 : SimpleSystemI<0, (ins pstatefield4_op:$pstatefield, imm0_15:$imm),
960 "msr", "\t$pstatefield, $imm">,
964 let Inst{20-19} = 0b00;
965 let Inst{18-16} = pstatefield{5-3};
966 let Inst{15-12} = 0b0100;
967 let Inst{11-8} = imm;
968 let Inst{7-5} = pstatefield{2-0};
970 let DecoderMethod = "DecodeSystemPStateInstruction";
971 // MSRpstateI aliases with MSRI. When the MSRpstateI decoder method returns
972 // Fail the decoder should attempt to decode the instruction as MSRI.
973 let hasCompleteDecoder = 0;
976 def SystemPStateFieldWithImm0_1Operand : AsmOperandClass {
977 let Name = "SystemPStateFieldWithImm0_1";
978 let ParserMethod = "tryParseSysReg";
980 def pstatefield1_op : Operand<i32> {
981 let ParserMatchClass = SystemPStateFieldWithImm0_1Operand;
982 let PrintMethod = "printSystemPStateField";
986 class MSRpstateImm0_1
987 : SimpleSystemI<0, (ins pstatefield1_op:$pstatefield, imm0_1:$imm),
988 "msr", "\t$pstatefield, $imm">,
992 let Inst{20-19} = 0b00;
993 let Inst{18-16} = pstatefield{5-3};
994 let Inst{15-9} = 0b0100000;
996 let Inst{7-5} = pstatefield{2-0};
998 let DecoderMethod = "DecodeSystemPStateInstruction";
999 // MSRpstateI aliases with MSRI. When the MSRpstateI decoder method returns
1000 // Fail the decoder should attempt to decode the instruction as MSRI.
1001 let hasCompleteDecoder = 0;
1004 // SYS and SYSL generic system instructions.
1005 def SysCRAsmOperand : AsmOperandClass {
1007 let ParserMethod = "tryParseSysCROperand";
1010 def sys_cr_op : Operand<i32> {
1011 let PrintMethod = "printSysCROperand";
1012 let ParserMatchClass = SysCRAsmOperand;
1015 class SystemXtI<bit L, string asm>
1016 : RtSystemI<L, (outs),
1017 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
1018 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
1023 let Inst{20-19} = 0b01;
1024 let Inst{18-16} = op1;
1025 let Inst{15-12} = Cn;
1026 let Inst{11-8} = Cm;
1027 let Inst{7-5} = op2;
1030 class SystemLXtI<bit L, string asm>
1031 : RtSystemI<L, (outs),
1032 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
1033 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
1038 let Inst{20-19} = 0b01;
1039 let Inst{18-16} = op1;
1040 let Inst{15-12} = Cn;
1041 let Inst{11-8} = Cm;
1042 let Inst{7-5} = op2;
1046 // Branch (register) instructions:
1054 // otherwise UNDEFINED
1055 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
1056 string operands, list<dag> pattern>
1057 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
1058 let Inst{31-25} = 0b1101011;
1059 let Inst{24-21} = opc;
1060 let Inst{20-16} = 0b11111;
1061 let Inst{15-10} = 0b000000;
1062 let Inst{4-0} = 0b00000;
1065 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
1066 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1071 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
1072 class SpecialReturn<bits<4> opc, string asm>
1073 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
1074 let Inst{9-5} = 0b11111;
1078 // Conditional branch instruction.
1082 // 4-bit immediate. Pretty-printed as <cc>
1083 def ccode : Operand<i32> {
1084 let PrintMethod = "printCondCode";
1085 let ParserMatchClass = CondCode;
1087 def inv_ccode : Operand<i32> {
1088 // AL and NV are invalid in the aliases which use inv_ccode
1089 let PrintMethod = "printInverseCondCode";
1090 let ParserMatchClass = CondCode;
1091 let MCOperandPredicate = [{
1092 return MCOp.isImm() &&
1093 MCOp.getImm() != AArch64CC::AL &&
1094 MCOp.getImm() != AArch64CC::NV;
1098 // Conditional branch target. 19-bit immediate. The low two bits of the target
1099 // offset are implied zero and so are not part of the immediate.
1100 def PCRelLabel19Operand : AsmOperandClass {
1101 let Name = "PCRelLabel19";
1102 let DiagnosticType = "InvalidLabel";
1104 def am_brcond : Operand<OtherVT> {
1105 let EncoderMethod = "getCondBranchTargetOpValue";
1106 let DecoderMethod = "DecodePCRelLabel19";
1107 let PrintMethod = "printAlignedLabel";
1108 let ParserMatchClass = PCRelLabel19Operand;
1111 class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
1112 "b", ".$cond\t$target", "",
1113 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
1116 let isTerminator = 1;
1121 let Inst{31-24} = 0b01010100;
1122 let Inst{23-5} = target;
1124 let Inst{3-0} = cond;
1128 // Compare-and-branch instructions.
1130 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
1131 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
1132 asm, "\t$Rt, $target", "",
1133 [(node regtype:$Rt, bb:$target)]>,
1136 let isTerminator = 1;
1140 let Inst{30-25} = 0b011010;
1142 let Inst{23-5} = target;
1146 multiclass CmpBranch<bit op, string asm, SDNode node> {
1147 def W : BaseCmpBranch<GPR32, op, asm, node> {
1150 def X : BaseCmpBranch<GPR64, op, asm, node> {
1156 // Test-bit-and-branch instructions.
1158 // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
1159 // the target offset are implied zero and so are not part of the immediate.
1160 def BranchTarget14Operand : AsmOperandClass {
1161 let Name = "BranchTarget14";
1163 def am_tbrcond : Operand<OtherVT> {
1164 let EncoderMethod = "getTestBranchTargetOpValue";
1165 let PrintMethod = "printAlignedLabel";
1166 let ParserMatchClass = BranchTarget14Operand;
1169 // AsmOperand classes to emit (or not) special diagnostics
1170 def TBZImm0_31Operand : AsmOperandClass {
1171 let Name = "TBZImm0_31";
1172 let PredicateMethod = "isImm0_31";
1173 let RenderMethod = "addImm0_31Operands";
1175 def TBZImm32_63Operand : AsmOperandClass {
1176 let Name = "Imm32_63";
1177 let DiagnosticType = "InvalidImm0_63";
1180 class tbz_imm0_31<AsmOperandClass matcher> : Operand<i64>, ImmLeaf<i64, [{
1181 return (((uint32_t)Imm) < 32);
1183 let ParserMatchClass = matcher;
1186 def tbz_imm0_31_diag : tbz_imm0_31<Imm0_31Operand>;
1187 def tbz_imm0_31_nodiag : tbz_imm0_31<TBZImm0_31Operand>;
1189 def tbz_imm32_63 : Operand<i64>, ImmLeaf<i64, [{
1190 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
1192 let ParserMatchClass = TBZImm32_63Operand;
1195 class BaseTestBranch<RegisterClass regtype, Operand immtype,
1196 bit op, string asm, SDNode node>
1197 : I<(outs), (ins regtype:$Rt, immtype:$bit_off, am_tbrcond:$target),
1198 asm, "\t$Rt, $bit_off, $target", "",
1199 [(node regtype:$Rt, immtype:$bit_off, bb:$target)]>,
1202 let isTerminator = 1;
1208 let Inst{30-25} = 0b011011;
1210 let Inst{23-19} = bit_off{4-0};
1211 let Inst{18-5} = target;
1214 let DecoderMethod = "DecodeTestAndBranch";
1217 multiclass TestBranch<bit op, string asm, SDNode node> {
1218 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1222 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1226 // Alias X-reg with 0-31 imm to W-Reg.
1227 def : InstAlias<asm # "\t$Rd, $imm, $target",
1228 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1229 tbz_imm0_31_nodiag:$imm, am_tbrcond:$target), 0>;
1230 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1231 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1232 tbz_imm0_31_diag:$imm, bb:$target)>;
1236 // Unconditional branch (immediate) instructions.
1238 def BranchTarget26Operand : AsmOperandClass {
1239 let Name = "BranchTarget26";
1240 let DiagnosticType = "InvalidLabel";
1242 def am_b_target : Operand<OtherVT> {
1243 let EncoderMethod = "getBranchTargetOpValue";
1244 let PrintMethod = "printAlignedLabel";
1245 let ParserMatchClass = BranchTarget26Operand;
1247 def am_bl_target : Operand<i64> {
1248 let EncoderMethod = "getBranchTargetOpValue";
1249 let PrintMethod = "printAlignedLabel";
1250 let ParserMatchClass = BranchTarget26Operand;
1253 class BImm<bit op, dag iops, string asm, list<dag> pattern>
1254 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
1257 let Inst{30-26} = 0b00101;
1258 let Inst{25-0} = addr;
1260 let DecoderMethod = "DecodeUnconditionalBranch";
1263 class BranchImm<bit op, string asm, list<dag> pattern>
1264 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
1265 class CallImm<bit op, string asm, list<dag> pattern>
1266 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
1269 // Basic one-operand data processing instructions.
1272 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1273 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1274 SDPatternOperator node>
1275 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1276 [(set regtype:$Rd, (node regtype:$Rn))]>,
1277 Sched<[WriteI, ReadI]> {
1281 let Inst{30-13} = 0b101101011000000000;
1282 let Inst{12-10} = opc;
1287 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1288 multiclass OneOperandData<bits<3> opc, string asm,
1289 SDPatternOperator node = null_frag> {
1290 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1294 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1299 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1300 : BaseOneOperandData<opc, GPR32, asm, node> {
1304 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1305 : BaseOneOperandData<opc, GPR64, asm, node> {
1310 // Basic two-operand data processing instructions.
1312 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1314 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1315 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1316 Sched<[WriteI, ReadI, ReadI]> {
1321 let Inst{30} = isSub;
1322 let Inst{28-21} = 0b11010000;
1323 let Inst{20-16} = Rm;
1324 let Inst{15-10} = 0;
1329 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1331 : BaseBaseAddSubCarry<isSub, regtype, asm,
1332 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1334 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1336 : BaseBaseAddSubCarry<isSub, regtype, asm,
1337 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1342 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1343 SDNode OpNode, SDNode OpNode_setflags> {
1344 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1348 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1354 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1359 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1366 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1367 SDPatternOperator OpNode>
1368 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1369 asm, "\t$Rd, $Rn, $Rm", "",
1370 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1374 let Inst{30-21} = 0b0011010110;
1375 let Inst{20-16} = Rm;
1376 let Inst{15-14} = 0b00;
1377 let Inst{13-10} = opc;
1382 class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
1383 SDPatternOperator OpNode>
1384 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
1385 let Inst{10} = isSigned;
1388 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
1389 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1390 Sched<[WriteID32, ReadID, ReadID]> {
1393 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1394 Sched<[WriteID64, ReadID, ReadID]> {
1399 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1400 SDPatternOperator OpNode = null_frag>
1401 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
1402 Sched<[WriteIS, ReadI]> {
1403 let Inst{11-10} = shift_type;
1406 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1407 def Wr : BaseShift<shift_type, GPR32, asm> {
1411 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1415 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1416 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1417 (EXTRACT_SUBREG i64:$Rm, sub_32))>;
1419 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1420 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1422 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1423 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1425 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1426 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1429 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
1430 : InstAlias<asm#"\t$dst, $src1, $src2",
1431 (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;
1433 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1434 RegisterClass addtype, string asm,
1436 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1437 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1442 let Inst{30-24} = 0b0011011;
1443 let Inst{23-21} = opc;
1444 let Inst{20-16} = Rm;
1445 let Inst{15} = isSub;
1446 let Inst{14-10} = Ra;
1451 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1452 // MADD/MSUB generation is decided by MachineCombiner.cpp
1453 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1454 [/*(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))*/]>,
1455 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1459 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1460 [/*(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))*/]>,
1461 Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> {
1466 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1467 SDNode AccNode, SDNode ExtNode>
1468 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1469 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1470 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1471 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1475 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1476 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1477 asm, "\t$Rd, $Rn, $Rm", "",
1478 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1479 Sched<[WriteIM64, ReadIM, ReadIM]> {
1483 let Inst{31-24} = 0b10011011;
1484 let Inst{23-21} = opc;
1485 let Inst{20-16} = Rm;
1490 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
1491 // (i.e. all bits 1) but is ignored by the processor.
1492 let PostEncoderMethod = "fixMulHigh";
1495 class MulAccumWAlias<string asm, Instruction inst>
1496 : InstAlias<asm#"\t$dst, $src1, $src2",
1497 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1498 class MulAccumXAlias<string asm, Instruction inst>
1499 : InstAlias<asm#"\t$dst, $src1, $src2",
1500 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1501 class WideMulAccumAlias<string asm, Instruction inst>
1502 : InstAlias<asm#"\t$dst, $src1, $src2",
1503 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1505 class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
1506 SDPatternOperator OpNode, string asm>
1507 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1508 asm, "\t$Rd, $Rn, $Rm", "",
1509 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1510 Sched<[WriteISReg, ReadI, ReadISReg]> {
1516 let Inst{30-21} = 0b0011010110;
1517 let Inst{20-16} = Rm;
1518 let Inst{15-13} = 0b010;
1520 let Inst{11-10} = sz;
1523 let Predicates = [HasCRC];
1527 // Address generation.
1530 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
1531 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1536 let Inst{31} = page;
1537 let Inst{30-29} = label{1-0};
1538 let Inst{28-24} = 0b10000;
1539 let Inst{23-5} = label{20-2};
1542 let DecoderMethod = "DecodeAdrInstruction";
1549 def movimm32_imm : Operand<i32> {
1550 let ParserMatchClass = Imm0_65535Operand;
1551 let EncoderMethod = "getMoveWideImmOpValue";
1552 let PrintMethod = "printHexImm";
1554 def movimm32_shift : Operand<i32> {
1555 let PrintMethod = "printShifter";
1556 let ParserMatchClass = MovImm32ShifterOperand;
1558 def movimm64_shift : Operand<i32> {
1559 let PrintMethod = "printShifter";
1560 let ParserMatchClass = MovImm64ShifterOperand;
1563 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1564 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1566 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1567 asm, "\t$Rd, $imm$shift", "", []>,
1572 let Inst{30-29} = opc;
1573 let Inst{28-23} = 0b100101;
1574 let Inst{22-21} = shift{5-4};
1575 let Inst{20-5} = imm;
1578 let DecoderMethod = "DecodeMoveImmInstruction";
1581 multiclass MoveImmediate<bits<2> opc, string asm> {
1582 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1586 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1591 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1592 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1594 : I<(outs regtype:$Rd),
1595 (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
1596 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1597 Sched<[WriteI, ReadI]> {
1601 let Inst{30-29} = opc;
1602 let Inst{28-23} = 0b100101;
1603 let Inst{22-21} = shift{5-4};
1604 let Inst{20-5} = imm;
1607 let DecoderMethod = "DecodeMoveImmInstruction";
1610 multiclass InsertImmediate<bits<2> opc, string asm> {
1611 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1615 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1624 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1625 RegisterClass srcRegtype, addsub_shifted_imm immtype,
1626 string asm, SDPatternOperator OpNode>
1627 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1628 asm, "\t$Rd, $Rn, $imm", "",
1629 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1630 Sched<[WriteI, ReadI]> {
1634 let Inst{30} = isSub;
1635 let Inst{29} = setFlags;
1636 let Inst{28-24} = 0b10001;
1637 let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
1638 let Inst{21-10} = imm{11-0};
1641 let DecoderMethod = "DecodeBaseAddSubImm";
1644 class BaseAddSubRegPseudo<RegisterClass regtype,
1645 SDPatternOperator OpNode>
1646 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1647 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1648 Sched<[WriteI, ReadI, ReadI]>;
1650 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1651 arith_shifted_reg shifted_regtype, string asm,
1652 SDPatternOperator OpNode>
1653 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1654 asm, "\t$Rd, $Rn, $Rm", "",
1655 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1656 Sched<[WriteISReg, ReadI, ReadISReg]> {
1657 // The operands are in order to match the 'addr' MI operands, so we
1658 // don't need an encoder method and by-name matching. Just use the default
1659 // in-order handling. Since we're using by-order, make sure the names
1665 let Inst{30} = isSub;
1666 let Inst{29} = setFlags;
1667 let Inst{28-24} = 0b01011;
1668 let Inst{23-22} = shift{7-6};
1670 let Inst{20-16} = src2;
1671 let Inst{15-10} = shift{5-0};
1672 let Inst{9-5} = src1;
1673 let Inst{4-0} = dst;
1675 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1678 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1679 RegisterClass src1Regtype, Operand src2Regtype,
1680 string asm, SDPatternOperator OpNode>
1681 : I<(outs dstRegtype:$R1),
1682 (ins src1Regtype:$R2, src2Regtype:$R3),
1683 asm, "\t$R1, $R2, $R3", "",
1684 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
1685 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1690 let Inst{30} = isSub;
1691 let Inst{29} = setFlags;
1692 let Inst{28-24} = 0b01011;
1693 let Inst{23-21} = 0b001;
1694 let Inst{20-16} = Rm;
1695 let Inst{15-13} = ext{5-3};
1696 let Inst{12-10} = ext{2-0};
1700 let DecoderMethod = "DecodeAddSubERegInstruction";
1703 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1704 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1705 RegisterClass src1Regtype, RegisterClass src2Regtype,
1706 Operand ext_op, string asm>
1707 : I<(outs dstRegtype:$Rd),
1708 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1709 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1710 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1715 let Inst{30} = isSub;
1716 let Inst{29} = setFlags;
1717 let Inst{28-24} = 0b01011;
1718 let Inst{23-21} = 0b001;
1719 let Inst{20-16} = Rm;
1720 let Inst{15} = ext{5};
1721 let Inst{12-10} = ext{2-0};
1725 let DecoderMethod = "DecodeAddSubERegInstruction";
1728 // Aliases for register+register add/subtract.
1729 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
1730 RegisterClass src1Regtype, RegisterClass src2Regtype,
1732 : InstAlias<asm#"\t$dst, $src1, $src2",
1733 (inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
1736 multiclass AddSub<bit isSub, string mnemonic, string alias,
1737 SDPatternOperator OpNode = null_frag> {
1738 let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1739 // Add/Subtract immediate
1740 // Increase the weight of the immediate variant to try to match it before
1741 // the extended register variant.
1742 // We used to match the register variant before the immediate when the
1743 // register argument could be implicitly zero-extended.
1744 let AddedComplexity = 6 in
1745 def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1749 let AddedComplexity = 6 in
1750 def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1755 // Add/Subtract register - Only used for CodeGen
1756 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1757 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1759 // Add/Subtract shifted register
1760 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1764 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1770 // Add/Subtract extended register
1771 let AddedComplexity = 1, hasSideEffects = 0 in {
1772 def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1773 arith_extended_reg32<i32>, mnemonic, OpNode> {
1776 def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1777 arith_extended_reg32to64<i64>, mnemonic, OpNode> {
1782 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1783 arith_extendlsl64, mnemonic> {
1784 // UXTX and SXTX only.
1785 let Inst{14-13} = 0b11;
1789 // add Rd, Rb, -imm -> sub Rd, Rn, imm
1790 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1791 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32sp:$Rn,
1792 addsub_shifted_imm32_neg:$imm), 0>;
1793 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1794 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64sp:$Rn,
1795 addsub_shifted_imm64_neg:$imm), 0>;
1797 // Register/register aliases with no shift when SP is not used.
1798 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1799 GPR32, GPR32, GPR32, 0>;
1800 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1801 GPR64, GPR64, GPR64, 0>;
1803 // Register/register aliases with no shift when either the destination or
1804 // first source register is SP.
1805 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1806 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1807 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1808 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
1809 def : AddSubRegAlias<mnemonic,
1810 !cast<Instruction>(NAME#"Xrx64"),
1811 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1812 def : AddSubRegAlias<mnemonic,
1813 !cast<Instruction>(NAME#"Xrx64"),
1814 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1817 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
1818 string alias, string cmpAlias> {
1819 let isCompare = 1, Defs = [NZCV] in {
1820 // Add/Subtract immediate
1821 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1825 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1830 // Add/Subtract register
1831 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1832 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1834 // Add/Subtract shifted register
1835 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1839 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1844 // Add/Subtract extended register
1845 let AddedComplexity = 1 in {
1846 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1847 arith_extended_reg32<i32>, mnemonic, OpNode> {
1850 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1851 arith_extended_reg32<i64>, mnemonic, OpNode> {
1856 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1857 arith_extendlsl64, mnemonic> {
1858 // UXTX and SXTX only.
1859 let Inst{14-13} = 0b11;
1864 // Support negative immediates, e.g. adds Rd, Rn, -imm -> subs Rd, Rn, imm
1865 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1866 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32sp:$Rn,
1867 addsub_shifted_imm32_neg:$imm), 0>;
1868 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1869 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64sp:$Rn,
1870 addsub_shifted_imm64_neg:$imm), 0>;
1873 def : InstAlias<cmp#"\t$src, $imm", (!cast<Instruction>(NAME#"Wri")
1874 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm), 5>;
1875 def : InstAlias<cmp#"\t$src, $imm", (!cast<Instruction>(NAME#"Xri")
1876 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
1877 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
1878 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1879 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
1880 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1881 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
1882 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
1883 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
1884 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
1885 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
1886 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
1888 // Support negative immediates, e.g. cmp Rn, -imm -> cmn Rn, imm
1889 def : InstAlias<cmpAlias#"\t$src, $imm", (!cast<Instruction>(NAME#"Wri")
1890 WZR, GPR32sp:$src, addsub_shifted_imm32_neg:$imm), 0>;
1891 def : InstAlias<cmpAlias#"\t$src, $imm", (!cast<Instruction>(NAME#"Xri")
1892 XZR, GPR64sp:$src, addsub_shifted_imm64_neg:$imm), 0>;
1894 // Compare shorthands
1895 def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrs")
1896 WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
1897 def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrs")
1898 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
1899 def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrx")
1900 WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
1901 def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrx64")
1902 XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;
1904 // Register/register aliases with no shift when SP is not used.
1905 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1906 GPR32, GPR32, GPR32, 0>;
1907 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1908 GPR64, GPR64, GPR64, 0>;
1910 // Register/register aliases with no shift when the first source register
1912 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1913 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
1914 def : AddSubRegAlias<mnemonic,
1915 !cast<Instruction>(NAME#"Xrx64"),
1916 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
1922 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1924 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
1926 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1928 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1929 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1930 Sched<[WriteExtr, ReadExtrHi]> {
1936 let Inst{30-23} = 0b00100111;
1938 let Inst{20-16} = Rm;
1939 let Inst{15-10} = imm;
1944 multiclass ExtractImm<string asm> {
1945 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1947 (AArch64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1950 // imm<5> must be zero.
1953 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1955 (AArch64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1966 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1967 class BaseBitfieldImm<bits<2> opc,
1968 RegisterClass regtype, Operand imm_type, string asm>
1969 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1970 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1971 Sched<[WriteIS, ReadI]> {
1977 let Inst{30-29} = opc;
1978 let Inst{28-23} = 0b100110;
1979 let Inst{21-16} = immr;
1980 let Inst{15-10} = imms;
1985 multiclass BitfieldImm<bits<2> opc, string asm> {
1986 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1989 // imms<5> and immr<5> must be zero, else ReservedValue().
1993 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1999 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2000 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
2001 RegisterClass regtype, Operand imm_type, string asm>
2002 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
2004 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
2005 Sched<[WriteIS, ReadI]> {
2011 let Inst{30-29} = opc;
2012 let Inst{28-23} = 0b100110;
2013 let Inst{21-16} = immr;
2014 let Inst{15-10} = imms;
2019 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
2020 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
2023 // imms<5> and immr<5> must be zero, else ReservedValue().
2027 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
2037 // Logical (immediate)
2038 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
2039 RegisterClass sregtype, Operand imm_type, string asm,
2041 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
2042 asm, "\t$Rd, $Rn, $imm", "", pattern>,
2043 Sched<[WriteI, ReadI]> {
2047 let Inst{30-29} = opc;
2048 let Inst{28-23} = 0b100100;
2049 let Inst{22} = imm{12};
2050 let Inst{21-16} = imm{11-6};
2051 let Inst{15-10} = imm{5-0};
2055 let DecoderMethod = "DecodeLogicalImmInstruction";
2058 // Logical (shifted register)
2059 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
2060 logical_shifted_reg shifted_regtype, string asm,
2062 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
2063 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
2064 Sched<[WriteISReg, ReadI, ReadISReg]> {
2065 // The operands are in order to match the 'addr' MI operands, so we
2066 // don't need an encoder method and by-name matching. Just use the default
2067 // in-order handling. Since we're using by-order, make sure the names
2073 let Inst{30-29} = opc;
2074 let Inst{28-24} = 0b01010;
2075 let Inst{23-22} = shift{7-6};
2077 let Inst{20-16} = src2;
2078 let Inst{15-10} = shift{5-0};
2079 let Inst{9-5} = src1;
2080 let Inst{4-0} = dst;
2082 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
2085 // Aliases for register+register logical instructions.
2086 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
2087 : InstAlias<asm#"\t$dst, $src1, $src2",
2088 (inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
2090 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
2092 let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in
2093 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
2094 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
2095 logical_imm32:$imm))]> {
2097 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
2099 let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in
2100 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
2101 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
2102 logical_imm64:$imm))]> {
2106 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2107 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
2108 logical_imm32_not:$imm), 0>;
2109 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2110 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
2111 logical_imm64_not:$imm), 0>;
2114 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode,
2116 let isCompare = 1, Defs = [NZCV] in {
2117 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
2118 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
2120 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
2122 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
2123 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
2126 } // end Defs = [NZCV]
2128 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2129 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
2130 logical_imm32_not:$imm), 0>;
2131 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2132 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
2133 logical_imm64_not:$imm), 0>;
2136 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
2137 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2138 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2139 Sched<[WriteI, ReadI, ReadI]>;
2141 // Split from LogicalImm as not all instructions have both.
2142 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
2143 SDPatternOperator OpNode> {
2144 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2145 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2146 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2149 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2150 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2151 logical_shifted_reg32:$Rm))]> {
2154 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2155 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2156 logical_shifted_reg64:$Rm))]> {
2160 def : LogicalRegAlias<mnemonic,
2161 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2162 def : LogicalRegAlias<mnemonic,
2163 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2166 // Split from LogicalReg to allow setting NZCV Defs
2167 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
2168 SDPatternOperator OpNode = null_frag> {
2169 let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
2170 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2171 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2173 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2174 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2177 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2178 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2183 def : LogicalRegAlias<mnemonic,
2184 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2185 def : LogicalRegAlias<mnemonic,
2186 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2190 // Conditionally set flags
2193 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2194 class BaseCondComparisonImm<bit op, RegisterClass regtype, ImmLeaf immtype,
2195 string mnemonic, SDNode OpNode>
2196 : I<(outs), (ins regtype:$Rn, immtype:$imm, imm32_0_15:$nzcv, ccode:$cond),
2197 mnemonic, "\t$Rn, $imm, $nzcv, $cond", "",
2198 [(set NZCV, (OpNode regtype:$Rn, immtype:$imm, (i32 imm:$nzcv),
2199 (i32 imm:$cond), NZCV))]>,
2200 Sched<[WriteI, ReadI]> {
2210 let Inst{29-21} = 0b111010010;
2211 let Inst{20-16} = imm;
2212 let Inst{15-12} = cond;
2213 let Inst{11-10} = 0b10;
2216 let Inst{3-0} = nzcv;
2219 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2220 class BaseCondComparisonReg<bit op, RegisterClass regtype, string mnemonic,
2222 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
2223 mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "",
2224 [(set NZCV, (OpNode regtype:$Rn, regtype:$Rm, (i32 imm:$nzcv),
2225 (i32 imm:$cond), NZCV))]>,
2226 Sched<[WriteI, ReadI, ReadI]> {
2236 let Inst{29-21} = 0b111010010;
2237 let Inst{20-16} = Rm;
2238 let Inst{15-12} = cond;
2239 let Inst{11-10} = 0b00;
2242 let Inst{3-0} = nzcv;
2245 multiclass CondComparison<bit op, string mnemonic, SDNode OpNode> {
2246 // immediate operand variants
2247 def Wi : BaseCondComparisonImm<op, GPR32, imm32_0_31, mnemonic, OpNode> {
2250 def Xi : BaseCondComparisonImm<op, GPR64, imm0_31, mnemonic, OpNode> {
2253 // register operand variants
2254 def Wr : BaseCondComparisonReg<op, GPR32, mnemonic, OpNode> {
2257 def Xr : BaseCondComparisonReg<op, GPR64, mnemonic, OpNode> {
2263 // Conditional select
2266 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
2267 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2268 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2270 (AArch64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
2271 Sched<[WriteI, ReadI, ReadI]> {
2280 let Inst{29-21} = 0b011010100;
2281 let Inst{20-16} = Rm;
2282 let Inst{15-12} = cond;
2283 let Inst{11-10} = op2;
2288 multiclass CondSelect<bit op, bits<2> op2, string asm> {
2289 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
2292 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
2297 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
2299 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2300 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2302 (AArch64csel regtype:$Rn, (frag regtype:$Rm),
2303 (i32 imm:$cond), NZCV))]>,
2304 Sched<[WriteI, ReadI, ReadI]> {
2313 let Inst{29-21} = 0b011010100;
2314 let Inst{20-16} = Rm;
2315 let Inst{15-12} = cond;
2316 let Inst{11-10} = op2;
2321 def inv_cond_XFORM : SDNodeXForm<imm, [{
2322 AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue());
2323 return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), SDLoc(N),
2327 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
2328 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
2331 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
2335 def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2336 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2337 (inv_cond_XFORM imm:$cond))>;
2339 def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2340 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2341 (inv_cond_XFORM imm:$cond))>;
2345 // Special Mask Value
2347 def maski8_or_more : Operand<i32>,
2348 ImmLeaf<i32, [{ return (Imm & 0xff) == 0xff; }]> {
2350 def maski16_or_more : Operand<i32>,
2351 ImmLeaf<i32, [{ return (Imm & 0xffff) == 0xffff; }]> {
2359 // (unsigned immediate)
2360 // Indexed for 8-bit registers. offset is in range [0,4095].
2361 def am_indexed8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []>;
2362 def am_indexed16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []>;
2363 def am_indexed32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []>;
2364 def am_indexed64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []>;
2365 def am_indexed128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []>;
2367 class UImm12OffsetOperand<int Scale> : AsmOperandClass {
2368 let Name = "UImm12Offset" # Scale;
2369 let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">";
2370 let PredicateMethod = "isUImm12Offset<" # Scale # ">";
2371 let DiagnosticType = "InvalidMemoryIndexed" # Scale;
2374 def UImm12OffsetScale1Operand : UImm12OffsetOperand<1>;
2375 def UImm12OffsetScale2Operand : UImm12OffsetOperand<2>;
2376 def UImm12OffsetScale4Operand : UImm12OffsetOperand<4>;
2377 def UImm12OffsetScale8Operand : UImm12OffsetOperand<8>;
2378 def UImm12OffsetScale16Operand : UImm12OffsetOperand<16>;
2380 class uimm12_scaled<int Scale> : Operand<i64> {
2381 let ParserMatchClass
2382 = !cast<AsmOperandClass>("UImm12OffsetScale" # Scale # "Operand");
2384 = "getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale" # Scale # ">";
2385 let PrintMethod = "printUImm12Offset<" # Scale # ">";
2388 def uimm12s1 : uimm12_scaled<1>;
2389 def uimm12s2 : uimm12_scaled<2>;
2390 def uimm12s4 : uimm12_scaled<4>;
2391 def uimm12s8 : uimm12_scaled<8>;
2392 def uimm12s16 : uimm12_scaled<16>;
2394 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2395 string asm, list<dag> pattern>
2396 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2402 let Inst{31-30} = sz;
2403 let Inst{29-27} = 0b111;
2405 let Inst{25-24} = 0b01;
2406 let Inst{23-22} = opc;
2407 let Inst{21-10} = offset;
2411 let DecoderMethod = "DecodeUnsignedLdStInstruction";
2414 multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2415 Operand indextype, string asm, list<dag> pattern> {
2416 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2417 def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
2418 (ins GPR64sp:$Rn, indextype:$offset),
2422 def : InstAlias<asm # "\t$Rt, [$Rn]",
2423 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2426 multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2427 Operand indextype, string asm, list<dag> pattern> {
2428 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2429 def ui : BaseLoadStoreUI<sz, V, opc, (outs),
2430 (ins regtype:$Rt, GPR64sp:$Rn, indextype:$offset),
2434 def : InstAlias<asm # "\t$Rt, [$Rn]",
2435 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2438 def PrefetchOperand : AsmOperandClass {
2439 let Name = "Prefetch";
2440 let ParserMethod = "tryParsePrefetch";
2442 def prfop : Operand<i32> {
2443 let PrintMethod = "printPrefetchOp";
2444 let ParserMatchClass = PrefetchOperand;
2447 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2448 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2449 : BaseLoadStoreUI<sz, V, opc,
2450 (outs), (ins prfop:$Rt, GPR64sp:$Rn, uimm12s8:$offset),
2458 // Load literal address: 19-bit immediate. The low two bits of the target
2459 // offset are implied zero and so are not part of the immediate.
2460 def am_ldrlit : Operand<OtherVT> {
2461 let EncoderMethod = "getLoadLiteralOpValue";
2462 let DecoderMethod = "DecodePCRelLabel19";
2463 let PrintMethod = "printAlignedLabel";
2464 let ParserMatchClass = PCRelLabel19Operand;
2467 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2468 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2469 : I<(outs regtype:$Rt), (ins am_ldrlit:$label),
2470 asm, "\t$Rt, $label", "", []>,
2474 let Inst{31-30} = opc;
2475 let Inst{29-27} = 0b011;
2477 let Inst{25-24} = 0b00;
2478 let Inst{23-5} = label;
2482 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2483 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2484 : I<(outs), (ins prfop:$Rt, am_ldrlit:$label),
2485 asm, "\t$Rt, $label", "", pat>,
2489 let Inst{31-30} = opc;
2490 let Inst{29-27} = 0b011;
2492 let Inst{25-24} = 0b00;
2493 let Inst{23-5} = label;
2498 // Load/store register offset
2501 def ro_Xindexed8 : ComplexPattern<i64, 4, "SelectAddrModeXRO<8>", []>;
2502 def ro_Xindexed16 : ComplexPattern<i64, 4, "SelectAddrModeXRO<16>", []>;
2503 def ro_Xindexed32 : ComplexPattern<i64, 4, "SelectAddrModeXRO<32>", []>;
2504 def ro_Xindexed64 : ComplexPattern<i64, 4, "SelectAddrModeXRO<64>", []>;
2505 def ro_Xindexed128 : ComplexPattern<i64, 4, "SelectAddrModeXRO<128>", []>;
2507 def ro_Windexed8 : ComplexPattern<i64, 4, "SelectAddrModeWRO<8>", []>;
2508 def ro_Windexed16 : ComplexPattern<i64, 4, "SelectAddrModeWRO<16>", []>;
2509 def ro_Windexed32 : ComplexPattern<i64, 4, "SelectAddrModeWRO<32>", []>;
2510 def ro_Windexed64 : ComplexPattern<i64, 4, "SelectAddrModeWRO<64>", []>;
2511 def ro_Windexed128 : ComplexPattern<i64, 4, "SelectAddrModeWRO<128>", []>;
2513 class MemExtendOperand<string Reg, int Width> : AsmOperandClass {
2514 let Name = "Mem" # Reg # "Extend" # Width;
2515 let PredicateMethod = "isMem" # Reg # "Extend<" # Width # ">";
2516 let RenderMethod = "addMemExtendOperands";
2517 let DiagnosticType = "InvalidMemory" # Reg # "Extend" # Width;
2520 def MemWExtend8Operand : MemExtendOperand<"W", 8> {
2521 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2522 // the trivial shift.
2523 let RenderMethod = "addMemExtend8Operands";
2525 def MemWExtend16Operand : MemExtendOperand<"W", 16>;
2526 def MemWExtend32Operand : MemExtendOperand<"W", 32>;
2527 def MemWExtend64Operand : MemExtendOperand<"W", 64>;
2528 def MemWExtend128Operand : MemExtendOperand<"W", 128>;
2530 def MemXExtend8Operand : MemExtendOperand<"X", 8> {
2531 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2532 // the trivial shift.
2533 let RenderMethod = "addMemExtend8Operands";
2535 def MemXExtend16Operand : MemExtendOperand<"X", 16>;
2536 def MemXExtend32Operand : MemExtendOperand<"X", 32>;
2537 def MemXExtend64Operand : MemExtendOperand<"X", 64>;
2538 def MemXExtend128Operand : MemExtendOperand<"X", 128>;
2540 class ro_extend<AsmOperandClass ParserClass, string Reg, int Width>
2542 let ParserMatchClass = ParserClass;
2543 let PrintMethod = "printMemExtend<'" # Reg # "', " # Width # ">";
2544 let DecoderMethod = "DecodeMemExtend";
2545 let EncoderMethod = "getMemExtendOpValue";
2546 let MIOperandInfo = (ops i32imm:$signed, i32imm:$doshift);
2549 def ro_Wextend8 : ro_extend<MemWExtend8Operand, "w", 8>;
2550 def ro_Wextend16 : ro_extend<MemWExtend16Operand, "w", 16>;
2551 def ro_Wextend32 : ro_extend<MemWExtend32Operand, "w", 32>;
2552 def ro_Wextend64 : ro_extend<MemWExtend64Operand, "w", 64>;
2553 def ro_Wextend128 : ro_extend<MemWExtend128Operand, "w", 128>;
2555 def ro_Xextend8 : ro_extend<MemXExtend8Operand, "x", 8>;
2556 def ro_Xextend16 : ro_extend<MemXExtend16Operand, "x", 16>;
2557 def ro_Xextend32 : ro_extend<MemXExtend32Operand, "x", 32>;
2558 def ro_Xextend64 : ro_extend<MemXExtend64Operand, "x", 64>;
2559 def ro_Xextend128 : ro_extend<MemXExtend128Operand, "x", 128>;
2561 class ROAddrMode<ComplexPattern windex, ComplexPattern xindex,
2562 Operand wextend, Operand xextend> {
2563 // CodeGen-level pattern covering the entire addressing mode.
2564 ComplexPattern Wpat = windex;
2565 ComplexPattern Xpat = xindex;
2567 // Asm-level Operand covering the valid "uxtw #3" style syntax.
2568 Operand Wext = wextend;
2569 Operand Xext = xextend;
2572 def ro8 : ROAddrMode<ro_Windexed8, ro_Xindexed8, ro_Wextend8, ro_Xextend8>;
2573 def ro16 : ROAddrMode<ro_Windexed16, ro_Xindexed16, ro_Wextend16, ro_Xextend16>;
2574 def ro32 : ROAddrMode<ro_Windexed32, ro_Xindexed32, ro_Wextend32, ro_Xextend32>;
2575 def ro64 : ROAddrMode<ro_Windexed64, ro_Xindexed64, ro_Wextend64, ro_Xextend64>;
2576 def ro128 : ROAddrMode<ro_Windexed128, ro_Xindexed128, ro_Wextend128,
2579 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2580 string asm, dag ins, dag outs, list<dag> pat>
2581 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2586 let Inst{31-30} = sz;
2587 let Inst{29-27} = 0b111;
2589 let Inst{25-24} = 0b00;
2590 let Inst{23-22} = opc;
2592 let Inst{20-16} = Rm;
2593 let Inst{15} = extend{1}; // sign extend Rm?
2595 let Inst{12} = extend{0}; // do shift?
2596 let Inst{11-10} = 0b10;
2601 class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
2602 : InstAlias<asm # "\t$Rt, [$Rn, $Rm]",
2603 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2605 multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2606 string asm, ValueType Ty, SDPatternOperator loadop> {
2607 let AddedComplexity = 10 in
2608 def roW : LoadStore8RO<sz, V, opc, regtype, asm,
2610 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2611 [(set (Ty regtype:$Rt),
2612 (loadop (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2613 ro_Wextend8:$extend)))]>,
2614 Sched<[WriteLDIdx, ReadAdrBase]> {
2618 let AddedComplexity = 10 in
2619 def roX : LoadStore8RO<sz, V, opc, regtype, asm,
2621 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2622 [(set (Ty regtype:$Rt),
2623 (loadop (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2624 ro_Xextend8:$extend)))]>,
2625 Sched<[WriteLDIdx, ReadAdrBase]> {
2629 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2632 multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2633 string asm, ValueType Ty, SDPatternOperator storeop> {
2634 let AddedComplexity = 10 in
2635 def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2636 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2637 [(storeop (Ty regtype:$Rt),
2638 (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2639 ro_Wextend8:$extend))]>,
2640 Sched<[WriteSTIdx, ReadAdrBase]> {
2644 let AddedComplexity = 10 in
2645 def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2646 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2647 [(storeop (Ty regtype:$Rt),
2648 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2649 ro_Xextend8:$extend))]>,
2650 Sched<[WriteSTIdx, ReadAdrBase]> {
2654 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2657 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2658 string asm, dag ins, dag outs, list<dag> pat>
2659 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2664 let Inst{31-30} = sz;
2665 let Inst{29-27} = 0b111;
2667 let Inst{25-24} = 0b00;
2668 let Inst{23-22} = opc;
2670 let Inst{20-16} = Rm;
2671 let Inst{15} = extend{1}; // sign extend Rm?
2673 let Inst{12} = extend{0}; // do shift?
2674 let Inst{11-10} = 0b10;
2679 multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2680 string asm, ValueType Ty, SDPatternOperator loadop> {
2681 let AddedComplexity = 10 in
2682 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2683 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2684 [(set (Ty regtype:$Rt),
2685 (loadop (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2686 ro_Wextend16:$extend)))]>,
2687 Sched<[WriteLDIdx, ReadAdrBase]> {
2691 let AddedComplexity = 10 in
2692 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2693 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2694 [(set (Ty regtype:$Rt),
2695 (loadop (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2696 ro_Xextend16:$extend)))]>,
2697 Sched<[WriteLDIdx, ReadAdrBase]> {
2701 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2704 multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2705 string asm, ValueType Ty, SDPatternOperator storeop> {
2706 let AddedComplexity = 10 in
2707 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2708 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2709 [(storeop (Ty regtype:$Rt),
2710 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2711 ro_Wextend16:$extend))]>,
2712 Sched<[WriteSTIdx, ReadAdrBase]> {
2716 let AddedComplexity = 10 in
2717 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2718 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2719 [(storeop (Ty regtype:$Rt),
2720 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2721 ro_Xextend16:$extend))]>,
2722 Sched<[WriteSTIdx, ReadAdrBase]> {
2726 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2729 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2730 string asm, dag ins, dag outs, list<dag> pat>
2731 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2736 let Inst{31-30} = sz;
2737 let Inst{29-27} = 0b111;
2739 let Inst{25-24} = 0b00;
2740 let Inst{23-22} = opc;
2742 let Inst{20-16} = Rm;
2743 let Inst{15} = extend{1}; // sign extend Rm?
2745 let Inst{12} = extend{0}; // do shift?
2746 let Inst{11-10} = 0b10;
2751 multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2752 string asm, ValueType Ty, SDPatternOperator loadop> {
2753 let AddedComplexity = 10 in
2754 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2755 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2756 [(set (Ty regtype:$Rt),
2757 (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2758 ro_Wextend32:$extend)))]>,
2759 Sched<[WriteLDIdx, ReadAdrBase]> {
2763 let AddedComplexity = 10 in
2764 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2765 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2766 [(set (Ty regtype:$Rt),
2767 (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2768 ro_Xextend32:$extend)))]>,
2769 Sched<[WriteLDIdx, ReadAdrBase]> {
2773 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2776 multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2777 string asm, ValueType Ty, SDPatternOperator storeop> {
2778 let AddedComplexity = 10 in
2779 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2780 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2781 [(storeop (Ty regtype:$Rt),
2782 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2783 ro_Wextend32:$extend))]>,
2784 Sched<[WriteSTIdx, ReadAdrBase]> {
2788 let AddedComplexity = 10 in
2789 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2790 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2791 [(storeop (Ty regtype:$Rt),
2792 (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2793 ro_Xextend32:$extend))]>,
2794 Sched<[WriteSTIdx, ReadAdrBase]> {
2798 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2801 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2802 string asm, dag ins, dag outs, list<dag> pat>
2803 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2808 let Inst{31-30} = sz;
2809 let Inst{29-27} = 0b111;
2811 let Inst{25-24} = 0b00;
2812 let Inst{23-22} = opc;
2814 let Inst{20-16} = Rm;
2815 let Inst{15} = extend{1}; // sign extend Rm?
2817 let Inst{12} = extend{0}; // do shift?
2818 let Inst{11-10} = 0b10;
2823 multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2824 string asm, ValueType Ty, SDPatternOperator loadop> {
2825 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2826 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2827 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2828 [(set (Ty regtype:$Rt),
2829 (loadop (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2830 ro_Wextend64:$extend)))]>,
2831 Sched<[WriteLDIdx, ReadAdrBase]> {
2835 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2836 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2837 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2838 [(set (Ty regtype:$Rt),
2839 (loadop (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2840 ro_Xextend64:$extend)))]>,
2841 Sched<[WriteLDIdx, ReadAdrBase]> {
2845 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2848 multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2849 string asm, ValueType Ty, SDPatternOperator storeop> {
2850 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2851 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2852 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2853 [(storeop (Ty regtype:$Rt),
2854 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2855 ro_Wextend64:$extend))]>,
2856 Sched<[WriteSTIdx, ReadAdrBase]> {
2860 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2861 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2862 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2863 [(storeop (Ty regtype:$Rt),
2864 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2865 ro_Xextend64:$extend))]>,
2866 Sched<[WriteSTIdx, ReadAdrBase]> {
2870 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2873 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2874 string asm, dag ins, dag outs, list<dag> pat>
2875 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2880 let Inst{31-30} = sz;
2881 let Inst{29-27} = 0b111;
2883 let Inst{25-24} = 0b00;
2884 let Inst{23-22} = opc;
2886 let Inst{20-16} = Rm;
2887 let Inst{15} = extend{1}; // sign extend Rm?
2889 let Inst{12} = extend{0}; // do shift?
2890 let Inst{11-10} = 0b10;
2895 multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2896 string asm, ValueType Ty, SDPatternOperator loadop> {
2897 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2898 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2899 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2900 [(set (Ty regtype:$Rt),
2901 (loadop (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2902 ro_Wextend128:$extend)))]>,
2903 Sched<[WriteLDIdx, ReadAdrBase]> {
2907 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2908 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2909 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2910 [(set (Ty regtype:$Rt),
2911 (loadop (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2912 ro_Xextend128:$extend)))]>,
2913 Sched<[WriteLDIdx, ReadAdrBase]> {
2917 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2920 multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2921 string asm, ValueType Ty, SDPatternOperator storeop> {
2922 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2923 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2924 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2925 [(storeop (Ty regtype:$Rt),
2926 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2927 ro_Wextend128:$extend))]>,
2928 Sched<[WriteSTIdx, ReadAdrBase]> {
2932 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2933 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2934 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2935 [(storeop (Ty regtype:$Rt),
2936 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2937 ro_Xextend128:$extend))]>,
2938 Sched<[WriteSTIdx, ReadAdrBase]> {
2942 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2945 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2946 class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
2947 string asm, list<dag> pat>
2948 : I<outs, ins, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat>,
2954 let Inst{31-30} = sz;
2955 let Inst{29-27} = 0b111;
2957 let Inst{25-24} = 0b00;
2958 let Inst{23-22} = opc;
2960 let Inst{20-16} = Rm;
2961 let Inst{15} = extend{1}; // sign extend Rm?
2963 let Inst{12} = extend{0}; // do shift?
2964 let Inst{11-10} = 0b10;
2969 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
2970 def roW : BasePrefetchRO<sz, V, opc, (outs),
2971 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2972 asm, [(AArch64Prefetch imm:$Rt,
2973 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2974 ro_Wextend64:$extend))]> {
2978 def roX : BasePrefetchRO<sz, V, opc, (outs),
2979 (ins prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2980 asm, [(AArch64Prefetch imm:$Rt,
2981 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2982 ro_Xextend64:$extend))]> {
2986 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
2987 (!cast<Instruction>(NAME # "roX") prfop:$Rt,
2988 GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2992 // Load/store unscaled immediate
2995 def am_unscaled8 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
2996 def am_unscaled16 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled16", []>;
2997 def am_unscaled32 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
2998 def am_unscaled64 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
2999 def am_unscaled128 :ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
3001 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3002 string asm, list<dag> pattern>
3003 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
3007 let Inst{31-30} = sz;
3008 let Inst{29-27} = 0b111;
3010 let Inst{25-24} = 0b00;
3011 let Inst{23-22} = opc;
3013 let Inst{20-12} = offset;
3014 let Inst{11-10} = 0b00;
3018 let DecoderMethod = "DecodeSignedLdStInstruction";
3021 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3022 string asm, list<dag> pattern> {
3023 let AddedComplexity = 1 in // try this before LoadUI
3024 def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
3025 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
3028 def : InstAlias<asm # "\t$Rt, [$Rn]",
3029 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
3032 multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3033 string asm, list<dag> pattern> {
3034 let AddedComplexity = 1 in // try this before StoreUI
3035 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
3036 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3040 def : InstAlias<asm # "\t$Rt, [$Rn]",
3041 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
3044 multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
3046 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3047 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
3048 (ins prfop:$Rt, GPR64sp:$Rn, simm9:$offset),
3052 def : InstAlias<asm # "\t$Rt, [$Rn]",
3053 (!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>;
3057 // Load/store unscaled immediate, unprivileged
3060 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
3061 dag oops, dag iops, string asm>
3062 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", []> {
3066 let Inst{31-30} = sz;
3067 let Inst{29-27} = 0b111;
3069 let Inst{25-24} = 0b00;
3070 let Inst{23-22} = opc;
3072 let Inst{20-12} = offset;
3073 let Inst{11-10} = 0b10;
3077 let DecoderMethod = "DecodeSignedLdStInstruction";
3080 multiclass LoadUnprivileged<bits<2> sz, bit V, bits<2> opc,
3081 RegisterClass regtype, string asm> {
3082 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in
3083 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs regtype:$Rt),
3084 (ins GPR64sp:$Rn, simm9:$offset), asm>,
3087 def : InstAlias<asm # "\t$Rt, [$Rn]",
3088 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
3091 multiclass StoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
3092 RegisterClass regtype, string asm> {
3093 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
3094 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs),
3095 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3099 def : InstAlias<asm # "\t$Rt, [$Rn]",
3100 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
3104 // Load/store pre-indexed
3107 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3108 string asm, string cstr, list<dag> pat>
3109 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]!", cstr, pat> {
3113 let Inst{31-30} = sz;
3114 let Inst{29-27} = 0b111;
3116 let Inst{25-24} = 0;
3117 let Inst{23-22} = opc;
3119 let Inst{20-12} = offset;
3120 let Inst{11-10} = 0b11;
3124 let DecoderMethod = "DecodeSignedLdStInstruction";
3127 let hasSideEffects = 0 in {
3128 let mayStore = 0, mayLoad = 1 in
3129 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3131 : BaseLoadStorePreIdx<sz, V, opc,
3132 (outs GPR64sp:$wback, regtype:$Rt),
3133 (ins GPR64sp:$Rn, simm9:$offset), asm,
3134 "$Rn = $wback,@earlyclobber $wback", []>,
3135 Sched<[WriteLD, WriteAdr]>;
3137 let mayStore = 1, mayLoad = 0 in
3138 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3139 string asm, SDPatternOperator storeop, ValueType Ty>
3140 : BaseLoadStorePreIdx<sz, V, opc,
3141 (outs GPR64sp:$wback),
3142 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3143 asm, "$Rn = $wback,@earlyclobber $wback",
3144 [(set GPR64sp:$wback,
3145 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3146 Sched<[WriteAdr, WriteST]>;
3147 } // hasSideEffects = 0
3150 // Load/store post-indexed
3153 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3154 string asm, string cstr, list<dag> pat>
3155 : I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
3159 let Inst{31-30} = sz;
3160 let Inst{29-27} = 0b111;
3162 let Inst{25-24} = 0b00;
3163 let Inst{23-22} = opc;
3165 let Inst{20-12} = offset;
3166 let Inst{11-10} = 0b01;
3170 let DecoderMethod = "DecodeSignedLdStInstruction";
3173 let hasSideEffects = 0 in {
3174 let mayStore = 0, mayLoad = 1 in
3175 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3177 : BaseLoadStorePostIdx<sz, V, opc,
3178 (outs GPR64sp:$wback, regtype:$Rt),
3179 (ins GPR64sp:$Rn, simm9:$offset),
3180 asm, "$Rn = $wback,@earlyclobber $wback", []>,
3181 Sched<[WriteLD, WriteI]>;
3183 let mayStore = 1, mayLoad = 0 in
3184 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3185 string asm, SDPatternOperator storeop, ValueType Ty>
3186 : BaseLoadStorePostIdx<sz, V, opc,
3187 (outs GPR64sp:$wback),
3188 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3189 asm, "$Rn = $wback,@earlyclobber $wback",
3190 [(set GPR64sp:$wback,
3191 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3192 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
3193 } // hasSideEffects = 0
3200 // (indexed, offset)
3202 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
3204 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3209 let Inst{31-30} = opc;
3210 let Inst{29-27} = 0b101;
3212 let Inst{25-23} = 0b010;
3214 let Inst{21-15} = offset;
3215 let Inst{14-10} = Rt2;
3219 let DecoderMethod = "DecodePairLdStInstruction";
3222 multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
3223 Operand indextype, string asm> {
3224 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3225 def i : BaseLoadStorePairOffset<opc, V, 1,
3226 (outs regtype:$Rt, regtype:$Rt2),
3227 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3228 Sched<[WriteLD, WriteLDHi]>;
3230 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3231 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3236 multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
3237 Operand indextype, string asm> {
3238 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
3239 def i : BaseLoadStorePairOffset<opc, V, 0, (outs),
3240 (ins regtype:$Rt, regtype:$Rt2,
3241 GPR64sp:$Rn, indextype:$offset),
3245 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3246 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3251 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3253 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
3258 let Inst{31-30} = opc;
3259 let Inst{29-27} = 0b101;
3261 let Inst{25-23} = 0b011;
3263 let Inst{21-15} = offset;
3264 let Inst{14-10} = Rt2;
3268 let DecoderMethod = "DecodePairLdStInstruction";
3271 let hasSideEffects = 0 in {
3272 let mayStore = 0, mayLoad = 1 in
3273 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3274 Operand indextype, string asm>
3275 : BaseLoadStorePairPreIdx<opc, V, 1,
3276 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3277 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3278 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3280 let mayStore = 1, mayLoad = 0 in
3281 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3282 Operand indextype, string asm>
3283 : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
3284 (ins regtype:$Rt, regtype:$Rt2,
3285 GPR64sp:$Rn, indextype:$offset),
3287 Sched<[WriteAdr, WriteSTP]>;
3288 } // hasSideEffects = 0
3292 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3294 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback,@earlyclobber $wback", []> {
3299 let Inst{31-30} = opc;
3300 let Inst{29-27} = 0b101;
3302 let Inst{25-23} = 0b001;
3304 let Inst{21-15} = offset;
3305 let Inst{14-10} = Rt2;
3309 let DecoderMethod = "DecodePairLdStInstruction";
3312 let hasSideEffects = 0 in {
3313 let mayStore = 0, mayLoad = 1 in
3314 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3315 Operand idxtype, string asm>
3316 : BaseLoadStorePairPostIdx<opc, V, 1,
3317 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3318 (ins GPR64sp:$Rn, idxtype:$offset), asm>,
3319 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3321 let mayStore = 1, mayLoad = 0 in
3322 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3323 Operand idxtype, string asm>
3324 : BaseLoadStorePairPostIdx<opc, V, 0, (outs GPR64sp:$wback),
3325 (ins regtype:$Rt, regtype:$Rt2,
3326 GPR64sp:$Rn, idxtype:$offset),
3328 Sched<[WriteAdr, WriteSTP]>;
3329 } // hasSideEffects = 0
3333 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
3335 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3340 let Inst{31-30} = opc;
3341 let Inst{29-27} = 0b101;
3343 let Inst{25-23} = 0b000;
3345 let Inst{21-15} = offset;
3346 let Inst{14-10} = Rt2;
3350 let DecoderMethod = "DecodePairLdStInstruction";
3353 multiclass LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3354 Operand indextype, string asm> {
3355 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3356 def i : BaseLoadStorePairNoAlloc<opc, V, 1,
3357 (outs regtype:$Rt, regtype:$Rt2),
3358 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3359 Sched<[WriteLD, WriteLDHi]>;
3362 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3363 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3367 multiclass StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3368 Operand indextype, string asm> {
3369 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in
3370 def i : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
3371 (ins regtype:$Rt, regtype:$Rt2,
3372 GPR64sp:$Rn, indextype:$offset),
3376 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3377 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3382 // Load/store exclusive
3385 // True exclusive operations write to and/or read from the system's exclusive
3386 // monitors, which as far as a compiler is concerned can be modelled as a
3387 // random shared memory address. Hence LoadExclusive mayStore.
3389 // Since these instructions have the undefined register bits set to 1 in
3390 // their canonical form, we need a post encoder method to set those bits
3391 // to 1 when encoding these instructions. We do this using the
3392 // fixLoadStoreExclusive function. This function has template parameters:
3394 // fixLoadStoreExclusive<int hasRs, int hasRt2>
3396 // hasRs indicates that the instruction uses the Rs field, so we won't set
3397 // it to 1 (and the same for Rt2). We don't need template parameters for
3398 // the other register fields since Rt and Rn are always used.
3400 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
3401 class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3402 dag oops, dag iops, string asm, string operands>
3403 : I<oops, iops, asm, operands, "", []> {
3404 let Inst{31-30} = sz;
3405 let Inst{29-24} = 0b001000;
3411 let DecoderMethod = "DecodeExclusiveLdStInstruction";
3414 // Neither Rs nor Rt2 operands.
3415 class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3416 dag oops, dag iops, string asm, string operands>
3417 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
3420 let Inst{20-16} = 0b11111;
3421 let Unpredictable{20-16} = 0b11111;
3422 let Inst{14-10} = 0b11111;
3423 let Unpredictable{14-10} = 0b11111;
3427 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
3430 // Simple load acquires don't set the exclusive monitor
3431 let mayLoad = 1, mayStore = 0 in
3432 class LoadAcquire<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3433 RegisterClass regtype, string asm>
3434 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3435 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3438 class LoadExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3439 RegisterClass regtype, string asm>
3440 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3441 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3444 class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3445 RegisterClass regtype, string asm>
3446 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3447 (outs regtype:$Rt, regtype:$Rt2),
3448 (ins GPR64sp0:$Rn), asm,
3449 "\t$Rt, $Rt2, [$Rn]">,
3450 Sched<[WriteLD, WriteLDHi]> {
3454 let Inst{14-10} = Rt2;
3458 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
3461 // Simple store release operations do not check the exclusive monitor.
3462 let mayLoad = 0, mayStore = 1 in
3463 class StoreRelease<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3464 RegisterClass regtype, string asm>
3465 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs),
3466 (ins regtype:$Rt, GPR64sp0:$Rn),
3467 asm, "\t$Rt, [$Rn]">,
3470 let mayLoad = 1, mayStore = 1 in
3471 class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3472 RegisterClass regtype, string asm>
3473 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
3474 (ins regtype:$Rt, GPR64sp0:$Rn),
3475 asm, "\t$Ws, $Rt, [$Rn]">,
3480 let Inst{20-16} = Ws;
3484 let Constraints = "@earlyclobber $Ws";
3485 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
3488 class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3489 RegisterClass regtype, string asm>
3490 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3492 (ins regtype:$Rt, regtype:$Rt2, GPR64sp0:$Rn),
3493 asm, "\t$Ws, $Rt, $Rt2, [$Rn]">,
3499 let Inst{20-16} = Ws;
3500 let Inst{14-10} = Rt2;
3504 let Constraints = "@earlyclobber $Ws";
3508 // Exception generation
3511 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3512 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
3513 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
3516 let Inst{31-24} = 0b11010100;
3517 let Inst{23-21} = op1;
3518 let Inst{20-5} = imm;
3519 let Inst{4-2} = 0b000;
3523 let Predicates = [HasFPARMv8] in {
3526 // Floating point to integer conversion
3529 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
3530 RegisterClass srcType, RegisterClass dstType,
3531 string asm, list<dag> pattern>
3532 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3533 asm, "\t$Rd, $Rn", "", pattern>,
3534 Sched<[WriteFCvt]> {
3537 let Inst{30-29} = 0b00;
3538 let Inst{28-24} = 0b11110;
3539 let Inst{23-22} = type;
3541 let Inst{20-19} = rmode;
3542 let Inst{18-16} = opcode;
3543 let Inst{15-10} = 0;
3548 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3549 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
3550 RegisterClass srcType, RegisterClass dstType,
3551 Operand immType, string asm, list<dag> pattern>
3552 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3553 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3554 Sched<[WriteFCvt]> {
3558 let Inst{30-29} = 0b00;
3559 let Inst{28-24} = 0b11110;
3560 let Inst{23-22} = type;
3562 let Inst{20-19} = rmode;
3563 let Inst{18-16} = opcode;
3564 let Inst{15-10} = scale;
3569 multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
3570 SDPatternOperator OpN> {
3571 // Unscaled half-precision to 32-bit
3572 def UWHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR32, asm,
3573 [(set GPR32:$Rd, (OpN FPR16:$Rn))]> {
3574 let Inst{31} = 0; // 32-bit GPR flag
3575 let Predicates = [HasFullFP16];
3578 // Unscaled half-precision to 64-bit
3579 def UXHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR64, asm,
3580 [(set GPR64:$Rd, (OpN FPR16:$Rn))]> {
3581 let Inst{31} = 1; // 64-bit GPR flag
3582 let Predicates = [HasFullFP16];
3585 // Unscaled single-precision to 32-bit
3586 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3587 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3588 let Inst{31} = 0; // 32-bit GPR flag
3591 // Unscaled single-precision to 64-bit
3592 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3593 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3594 let Inst{31} = 1; // 64-bit GPR flag
3597 // Unscaled double-precision to 32-bit
3598 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3599 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3600 let Inst{31} = 0; // 32-bit GPR flag
3603 // Unscaled double-precision to 64-bit
3604 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3605 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3606 let Inst{31} = 1; // 64-bit GPR flag
3610 multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
3611 SDPatternOperator OpN> {
3612 // Scaled half-precision to 32-bit
3613 def SWHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR32,
3614 fixedpoint_f16_i32, asm,
3615 [(set GPR32:$Rd, (OpN (fmul FPR16:$Rn,
3616 fixedpoint_f16_i32:$scale)))]> {
3617 let Inst{31} = 0; // 32-bit GPR flag
3619 let Predicates = [HasFullFP16];
3622 // Scaled half-precision to 64-bit
3623 def SXHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR64,
3624 fixedpoint_f16_i64, asm,
3625 [(set GPR64:$Rd, (OpN (fmul FPR16:$Rn,
3626 fixedpoint_f16_i64:$scale)))]> {
3627 let Inst{31} = 1; // 64-bit GPR flag
3628 let Predicates = [HasFullFP16];
3631 // Scaled single-precision to 32-bit
3632 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3633 fixedpoint_f32_i32, asm,
3634 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3635 fixedpoint_f32_i32:$scale)))]> {
3636 let Inst{31} = 0; // 32-bit GPR flag
3640 // Scaled single-precision to 64-bit
3641 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3642 fixedpoint_f32_i64, asm,
3643 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3644 fixedpoint_f32_i64:$scale)))]> {
3645 let Inst{31} = 1; // 64-bit GPR flag
3648 // Scaled double-precision to 32-bit
3649 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3650 fixedpoint_f64_i32, asm,
3651 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3652 fixedpoint_f64_i32:$scale)))]> {
3653 let Inst{31} = 0; // 32-bit GPR flag
3657 // Scaled double-precision to 64-bit
3658 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3659 fixedpoint_f64_i64, asm,
3660 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3661 fixedpoint_f64_i64:$scale)))]> {
3662 let Inst{31} = 1; // 64-bit GPR flag
3667 // Integer to floating point conversion
3670 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
3671 class BaseIntegerToFP<bit isUnsigned,
3672 RegisterClass srcType, RegisterClass dstType,
3673 Operand immType, string asm, list<dag> pattern>
3674 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3675 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3676 Sched<[WriteFCvt]> {
3680 let Inst{30-24} = 0b0011110;
3681 let Inst{21-17} = 0b00001;
3682 let Inst{16} = isUnsigned;
3683 let Inst{15-10} = scale;
3688 class BaseIntegerToFPUnscaled<bit isUnsigned,
3689 RegisterClass srcType, RegisterClass dstType,
3690 ValueType dvt, string asm, SDNode node>
3691 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3692 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3693 Sched<[WriteFCvt]> {
3697 let Inst{30-24} = 0b0011110;
3698 let Inst{21-17} = 0b10001;
3699 let Inst{16} = isUnsigned;
3700 let Inst{15-10} = 0b000000;
3705 multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
3707 def UWHri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR16, f16, asm, node> {
3708 let Inst{31} = 0; // 32-bit GPR flag
3709 let Inst{23-22} = 0b11; // 16-bit FPR flag
3710 let Predicates = [HasFullFP16];
3713 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3714 let Inst{31} = 0; // 32-bit GPR flag
3715 let Inst{23-22} = 0b00; // 32-bit FPR flag
3718 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3719 let Inst{31} = 0; // 32-bit GPR flag
3720 let Inst{23-22} = 0b01; // 64-bit FPR flag
3723 def UXHri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR16, f16, asm, node> {
3724 let Inst{31} = 1; // 64-bit GPR flag
3725 let Inst{23-22} = 0b11; // 16-bit FPR flag
3726 let Predicates = [HasFullFP16];
3729 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3730 let Inst{31} = 1; // 64-bit GPR flag
3731 let Inst{23-22} = 0b00; // 32-bit FPR flag
3734 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3735 let Inst{31} = 1; // 64-bit GPR flag
3736 let Inst{23-22} = 0b01; // 64-bit FPR flag
3740 def SWHri: BaseIntegerToFP<isUnsigned, GPR32, FPR16, fixedpoint_f16_i32, asm,
3742 (fdiv (node GPR32:$Rn),
3743 fixedpoint_f16_i32:$scale))]> {
3744 let Inst{31} = 0; // 32-bit GPR flag
3745 let Inst{23-22} = 0b11; // 16-bit FPR flag
3747 let Predicates = [HasFullFP16];
3750 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
3752 (fdiv (node GPR32:$Rn),
3753 fixedpoint_f32_i32:$scale))]> {
3754 let Inst{31} = 0; // 32-bit GPR flag
3755 let Inst{23-22} = 0b00; // 32-bit FPR flag
3759 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
3761 (fdiv (node GPR32:$Rn),
3762 fixedpoint_f64_i32:$scale))]> {
3763 let Inst{31} = 0; // 32-bit GPR flag
3764 let Inst{23-22} = 0b01; // 64-bit FPR flag
3768 def SXHri: BaseIntegerToFP<isUnsigned, GPR64, FPR16, fixedpoint_f16_i64, asm,
3770 (fdiv (node GPR64:$Rn),
3771 fixedpoint_f16_i64:$scale))]> {
3772 let Inst{31} = 1; // 64-bit GPR flag
3773 let Inst{23-22} = 0b11; // 16-bit FPR flag
3774 let Predicates = [HasFullFP16];
3777 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
3779 (fdiv (node GPR64:$Rn),
3780 fixedpoint_f32_i64:$scale))]> {
3781 let Inst{31} = 1; // 64-bit GPR flag
3782 let Inst{23-22} = 0b00; // 32-bit FPR flag
3785 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
3787 (fdiv (node GPR64:$Rn),
3788 fixedpoint_f64_i64:$scale))]> {
3789 let Inst{31} = 1; // 64-bit GPR flag
3790 let Inst{23-22} = 0b01; // 64-bit FPR flag
3795 // Unscaled integer <-> floating point conversion (i.e. FMOV)
3798 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3799 class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
3800 RegisterClass srcType, RegisterClass dstType,
3802 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3803 // We use COPY_TO_REGCLASS for these bitconvert operations.
3804 // copyPhysReg() expands the resultant COPY instructions after
3805 // regalloc is done. This gives greater freedom for the allocator
3806 // and related passes (coalescing, copy propagation, et. al.) to
3807 // be more effective.
3808 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3809 Sched<[WriteFCopy]> {
3812 let Inst{30-24} = 0b0011110;
3814 let Inst{20-19} = rmode;
3815 let Inst{18-16} = opcode;
3816 let Inst{15-10} = 0b000000;
3821 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3822 class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
3823 RegisterClass srcType, RegisterOperand dstType, string asm,
3825 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3826 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3827 Sched<[WriteFCopy]> {
3830 let Inst{30-23} = 0b00111101;
3832 let Inst{20-19} = rmode;
3833 let Inst{18-16} = opcode;
3834 let Inst{15-10} = 0b000000;
3838 let DecoderMethod = "DecodeFMOVLaneInstruction";
3841 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3842 class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
3843 RegisterOperand srcType, RegisterClass dstType, string asm,
3845 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3846 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3847 Sched<[WriteFCopy]> {
3850 let Inst{30-23} = 0b00111101;
3852 let Inst{20-19} = rmode;
3853 let Inst{18-16} = opcode;
3854 let Inst{15-10} = 0b000000;
3858 let DecoderMethod = "DecodeFMOVLaneInstruction";
3862 multiclass UnscaledConversion<string asm> {
3863 def WHr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR16, asm> {
3864 let Inst{31} = 0; // 32-bit GPR flag
3865 let Inst{23-22} = 0b11; // 16-bit FPR flag
3866 let Predicates = [HasFullFP16];
3869 def XHr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR16, asm> {
3870 let Inst{31} = 1; // 64-bit GPR flag
3871 let Inst{23-22} = 0b11; // 16-bit FPR flag
3872 let Predicates = [HasFullFP16];
3875 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3876 let Inst{31} = 0; // 32-bit GPR flag
3877 let Inst{23-22} = 0b00; // 32-bit FPR flag
3880 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3881 let Inst{31} = 1; // 64-bit GPR flag
3882 let Inst{23-22} = 0b01; // 64-bit FPR flag
3885 def HWr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR32, asm> {
3886 let Inst{31} = 0; // 32-bit GPR flag
3887 let Inst{23-22} = 0b11; // 16-bit FPR flag
3888 let Predicates = [HasFullFP16];
3891 def HXr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR64, asm> {
3892 let Inst{31} = 1; // 64-bit GPR flag
3893 let Inst{23-22} = 0b11; // 16-bit FPR flag
3894 let Predicates = [HasFullFP16];
3897 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3898 let Inst{31} = 0; // 32-bit GPR flag
3899 let Inst{23-22} = 0b00; // 32-bit FPR flag
3902 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3903 let Inst{31} = 1; // 64-bit GPR flag
3904 let Inst{23-22} = 0b01; // 64-bit FPR flag
3907 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3913 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3921 // Floating point conversion
3924 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
3925 RegisterClass srcType, string asm, list<dag> pattern>
3926 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3927 Sched<[WriteFCvt]> {
3930 let Inst{31-24} = 0b00011110;
3931 let Inst{23-22} = type;
3932 let Inst{21-17} = 0b10001;
3933 let Inst{16-15} = opcode;
3934 let Inst{14-10} = 0b10000;
3939 multiclass FPConversion<string asm> {
3940 // Double-precision to Half-precision
3941 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
3942 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3944 // Double-precision to Single-precision
3945 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3946 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3948 // Half-precision to Double-precision
3949 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
3950 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3952 // Half-precision to Single-precision
3953 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3954 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3956 // Single-precision to Double-precision
3957 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3958 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3960 // Single-precision to Half-precision
3961 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
3962 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3966 // Single operand floating point data processing
3969 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3970 class BaseSingleOperandFPData<bits<4> opcode, RegisterClass regtype,
3971 ValueType vt, string asm, SDPatternOperator node>
3972 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3973 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3977 let Inst{31-24} = 0b00011110;
3978 let Inst{21-19} = 0b100;
3979 let Inst{18-15} = opcode;
3980 let Inst{14-10} = 0b10000;
3985 multiclass SingleOperandFPData<bits<4> opcode, string asm,
3986 SDPatternOperator node = null_frag> {
3987 def Hr : BaseSingleOperandFPData<opcode, FPR16, f16, asm, node> {
3988 let Inst{23-22} = 0b11; // 16-bit size flag
3989 let Predicates = [HasFullFP16];
3992 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
3993 let Inst{23-22} = 0b00; // 32-bit size flag
3996 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
3997 let Inst{23-22} = 0b01; // 64-bit size flag
4002 // Two operand floating point data processing
4005 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4006 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
4007 string asm, list<dag> pat>
4008 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
4009 asm, "\t$Rd, $Rn, $Rm", "", pat>,
4014 let Inst{31-24} = 0b00011110;
4016 let Inst{20-16} = Rm;
4017 let Inst{15-12} = opcode;
4018 let Inst{11-10} = 0b10;
4023 multiclass TwoOperandFPData<bits<4> opcode, string asm,
4024 SDPatternOperator node = null_frag> {
4025 def Hrr : BaseTwoOperandFPData<opcode, FPR16, asm,
4026 [(set (f16 FPR16:$Rd),
4027 (node (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]> {
4028 let Inst{23-22} = 0b11; // 16-bit size flag
4029 let Predicates = [HasFullFP16];
4032 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
4033 [(set (f32 FPR32:$Rd),
4034 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
4035 let Inst{23-22} = 0b00; // 32-bit size flag
4038 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
4039 [(set (f64 FPR64:$Rd),
4040 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
4041 let Inst{23-22} = 0b01; // 64-bit size flag
4045 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm, SDNode node> {
4046 def Hrr : BaseTwoOperandFPData<opcode, FPR16, asm,
4047 [(set FPR16:$Rd, (fneg (node FPR16:$Rn, (f16 FPR16:$Rm))))]> {
4048 let Inst{23-22} = 0b11; // 16-bit size flag
4049 let Predicates = [HasFullFP16];
4052 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
4053 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
4054 let Inst{23-22} = 0b00; // 32-bit size flag
4057 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
4058 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
4059 let Inst{23-22} = 0b01; // 64-bit size flag
4065 // Three operand floating point data processing
4068 class BaseThreeOperandFPData<bit isNegated, bit isSub,
4069 RegisterClass regtype, string asm, list<dag> pat>
4070 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
4071 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
4072 Sched<[WriteFMul]> {
4077 let Inst{31-24} = 0b00011111;
4078 let Inst{21} = isNegated;
4079 let Inst{20-16} = Rm;
4080 let Inst{15} = isSub;
4081 let Inst{14-10} = Ra;
4086 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
4087 SDPatternOperator node> {
4088 def Hrrr : BaseThreeOperandFPData<isNegated, isSub, FPR16, asm,
4090 (node (f16 FPR16:$Rn), (f16 FPR16:$Rm), (f16 FPR16:$Ra)))]> {
4091 let Inst{23-22} = 0b11; // 16-bit size flag
4092 let Predicates = [HasFullFP16];
4095 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
4097 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
4098 let Inst{23-22} = 0b00; // 32-bit size flag
4101 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
4103 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
4104 let Inst{23-22} = 0b01; // 64-bit size flag
4109 // Floating point data comparisons
4112 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4113 class BaseOneOperandFPComparison<bit signalAllNans,
4114 RegisterClass regtype, string asm,
4116 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
4117 Sched<[WriteFCmp]> {
4119 let Inst{31-24} = 0b00011110;
4122 let Inst{15-10} = 0b001000;
4124 let Inst{4} = signalAllNans;
4125 let Inst{3-0} = 0b1000;
4127 // Rm should be 0b00000 canonically, but we need to accept any value.
4128 let PostEncoderMethod = "fixOneOperandFPComparison";
4131 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4132 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
4133 string asm, list<dag> pat>
4134 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
4135 Sched<[WriteFCmp]> {
4138 let Inst{31-24} = 0b00011110;
4140 let Inst{20-16} = Rm;
4141 let Inst{15-10} = 0b001000;
4143 let Inst{4} = signalAllNans;
4144 let Inst{3-0} = 0b0000;
4147 multiclass FPComparison<bit signalAllNans, string asm,
4148 SDPatternOperator OpNode = null_frag> {
4149 let Defs = [NZCV] in {
4150 def Hrr : BaseTwoOperandFPComparison<signalAllNans, FPR16, asm,
4151 [(OpNode FPR16:$Rn, (f16 FPR16:$Rm)), (implicit NZCV)]> {
4152 let Inst{23-22} = 0b11;
4153 let Predicates = [HasFullFP16];
4156 def Hri : BaseOneOperandFPComparison<signalAllNans, FPR16, asm,
4157 [(OpNode (f16 FPR16:$Rn), fpimm0), (implicit NZCV)]> {
4158 let Inst{23-22} = 0b11;
4159 let Predicates = [HasFullFP16];
4162 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
4163 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
4164 let Inst{23-22} = 0b00;
4167 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
4168 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
4169 let Inst{23-22} = 0b00;
4172 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
4173 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
4174 let Inst{23-22} = 0b01;
4177 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
4178 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
4179 let Inst{23-22} = 0b01;
4185 // Floating point conditional comparisons
4188 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4189 class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
4190 string mnemonic, list<dag> pat>
4191 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
4192 mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "", pat>,
4193 Sched<[WriteFCmp]> {
4202 let Inst{31-24} = 0b00011110;
4204 let Inst{20-16} = Rm;
4205 let Inst{15-12} = cond;
4206 let Inst{11-10} = 0b01;
4208 let Inst{4} = signalAllNans;
4209 let Inst{3-0} = nzcv;
4212 multiclass FPCondComparison<bit signalAllNans, string mnemonic,
4213 SDPatternOperator OpNode = null_frag> {
4214 def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic, []> {
4215 let Inst{23-22} = 0b11;
4216 let Predicates = [HasFullFP16];
4219 def Srr : BaseFPCondComparison<signalAllNans, FPR32, mnemonic,
4220 [(set NZCV, (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm), (i32 imm:$nzcv),
4221 (i32 imm:$cond), NZCV))]> {
4222 let Inst{23-22} = 0b00;
4225 def Drr : BaseFPCondComparison<signalAllNans, FPR64, mnemonic,
4226 [(set NZCV, (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm), (i32 imm:$nzcv),
4227 (i32 imm:$cond), NZCV))]> {
4228 let Inst{23-22} = 0b01;
4233 // Floating point conditional select
4236 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
4237 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
4238 asm, "\t$Rd, $Rn, $Rm, $cond", "",
4240 (AArch64csel (vt regtype:$Rn), regtype:$Rm,
4241 (i32 imm:$cond), NZCV))]>,
4248 let Inst{31-24} = 0b00011110;
4250 let Inst{20-16} = Rm;
4251 let Inst{15-12} = cond;
4252 let Inst{11-10} = 0b11;
4257 multiclass FPCondSelect<string asm> {
4258 let Uses = [NZCV] in {
4259 def Hrrr : BaseFPCondSelect<FPR16, f16, asm> {
4260 let Inst{23-22} = 0b11;
4261 let Predicates = [HasFullFP16];
4264 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
4265 let Inst{23-22} = 0b00;
4268 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
4269 let Inst{23-22} = 0b01;
4275 // Floating move immediate
4278 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
4279 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
4280 [(set regtype:$Rd, fpimmtype:$imm)]>,
4281 Sched<[WriteFImm]> {
4284 let Inst{31-24} = 0b00011110;
4286 let Inst{20-13} = imm;
4287 let Inst{12-5} = 0b10000000;
4291 multiclass FPMoveImmediate<string asm> {
4292 def Hi : BaseFPMoveImmediate<FPR16, fpimm16, asm> {
4293 let Inst{23-22} = 0b11;
4294 let Predicates = [HasFullFP16];
4297 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
4298 let Inst{23-22} = 0b00;
4301 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
4302 let Inst{23-22} = 0b01;
4305 } // end of 'let Predicates = [HasFPARMv8]'
4307 //----------------------------------------------------------------------------
4309 //----------------------------------------------------------------------------
4311 let Predicates = [HasNEON] in {
4313 //----------------------------------------------------------------------------
4314 // AdvSIMD three register vector instructions
4315 //----------------------------------------------------------------------------
4317 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4318 class BaseSIMDThreeSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4319 RegisterOperand regtype, string asm, string kind,
4321 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4322 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4323 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
4331 let Inst{28-24} = 0b01110;
4332 let Inst{23-22} = size;
4334 let Inst{20-16} = Rm;
4335 let Inst{15-11} = opcode;
4341 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4342 class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4343 RegisterOperand regtype, string asm, string kind,
4345 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4346 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4347 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4355 let Inst{28-24} = 0b01110;
4356 let Inst{23-22} = size;
4358 let Inst{20-16} = Rm;
4359 let Inst{15-11} = opcode;
4365 // All operand sizes distinguished in the encoding.
4366 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
4367 SDPatternOperator OpNode> {
4368 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4370 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4371 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4373 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4374 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4376 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4377 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4379 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4380 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4382 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4383 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4385 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4386 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b11, opc, V128,
4388 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4391 // As above, but D sized elements unsupported.
4392 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
4393 SDPatternOperator OpNode> {
4394 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4396 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4397 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4399 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4400 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4402 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4403 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4405 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4406 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4408 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4409 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4411 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4414 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
4415 SDPatternOperator OpNode> {
4416 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
4418 [(set (v8i8 V64:$dst),
4419 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4420 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
4422 [(set (v16i8 V128:$dst),
4423 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4424 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b01, opc, V64,
4426 [(set (v4i16 V64:$dst),
4427 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4428 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b01, opc, V128,
4430 [(set (v8i16 V128:$dst),
4431 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4432 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b10, opc, V64,
4434 [(set (v2i32 V64:$dst),
4435 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4436 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b10, opc, V128,
4438 [(set (v4i32 V128:$dst),
4439 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4442 // As above, but only B sized elements supported.
4443 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
4444 SDPatternOperator OpNode> {
4445 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4447 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4448 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4450 [(set (v16i8 V128:$Rd),
4451 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4454 // As above, but only S and D sized floating point elements supported.
4455 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<5> opc,
4456 string asm, SDPatternOperator OpNode> {
4457 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4459 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4460 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4462 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4463 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4465 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4468 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<5> opc,
4470 SDPatternOperator OpNode> {
4471 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4473 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4474 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4476 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4477 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4479 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4482 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<5> opc,
4483 string asm, SDPatternOperator OpNode> {
4484 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0}, opc, V64,
4486 [(set (v2f32 V64:$dst),
4487 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4488 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0}, opc, V128,
4490 [(set (v4f32 V128:$dst),
4491 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4492 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,1}, opc, V128,
4494 [(set (v2f64 V128:$dst),
4495 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4498 // As above, but D and B sized elements unsupported.
4499 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
4500 SDPatternOperator OpNode> {
4501 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4503 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4504 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4506 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4507 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4509 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4510 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4512 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4515 // Logical three vector ops share opcode bits, and only use B sized elements.
4516 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
4517 SDPatternOperator OpNode = null_frag> {
4518 def v8i8 : BaseSIMDThreeSameVector<0, U, size, 0b00011, V64,
4520 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4521 def v16i8 : BaseSIMDThreeSameVector<1, U, size, 0b00011, V128,
4523 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4525 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
4526 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4527 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
4528 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4529 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
4530 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4532 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
4533 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4534 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
4535 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4536 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
4537 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4540 multiclass SIMDLogicalThreeVectorTied<bit U, bits<2> size,
4541 string asm, SDPatternOperator OpNode> {
4542 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, size, 0b00011, V64,
4544 [(set (v8i8 V64:$dst),
4545 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4546 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, size, 0b00011, V128,
4548 [(set (v16i8 V128:$dst),
4549 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4550 (v16i8 V128:$Rm)))]>;
4552 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
4554 (!cast<Instruction>(NAME#"v8i8")
4555 V64:$LHS, V64:$MHS, V64:$RHS)>;
4556 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
4558 (!cast<Instruction>(NAME#"v8i8")
4559 V64:$LHS, V64:$MHS, V64:$RHS)>;
4560 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
4562 (!cast<Instruction>(NAME#"v8i8")
4563 V64:$LHS, V64:$MHS, V64:$RHS)>;
4565 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
4566 (v8i16 V128:$RHS))),
4567 (!cast<Instruction>(NAME#"v16i8")
4568 V128:$LHS, V128:$MHS, V128:$RHS)>;
4569 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
4570 (v4i32 V128:$RHS))),
4571 (!cast<Instruction>(NAME#"v16i8")
4572 V128:$LHS, V128:$MHS, V128:$RHS)>;
4573 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
4574 (v2i64 V128:$RHS))),
4575 (!cast<Instruction>(NAME#"v16i8")
4576 V128:$LHS, V128:$MHS, V128:$RHS)>;
4580 //----------------------------------------------------------------------------
4581 // AdvSIMD two register vector instructions.
4582 //----------------------------------------------------------------------------
4584 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4585 class BaseSIMDTwoSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4586 RegisterOperand regtype, string asm, string dstkind,
4587 string srckind, list<dag> pattern>
4588 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4589 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4590 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4597 let Inst{28-24} = 0b01110;
4598 let Inst{23-22} = size;
4599 let Inst{21-17} = 0b10000;
4600 let Inst{16-12} = opcode;
4601 let Inst{11-10} = 0b10;
4606 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4607 class BaseSIMDTwoSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4608 RegisterOperand regtype, string asm, string dstkind,
4609 string srckind, list<dag> pattern>
4610 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4611 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4612 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4619 let Inst{28-24} = 0b01110;
4620 let Inst{23-22} = size;
4621 let Inst{21-17} = 0b10000;
4622 let Inst{16-12} = opcode;
4623 let Inst{11-10} = 0b10;
4628 // Supports B, H, and S element sizes.
4629 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
4630 SDPatternOperator OpNode> {
4631 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4633 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4634 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4635 asm, ".16b", ".16b",
4636 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4637 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4639 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4640 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4642 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4643 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4645 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4646 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4648 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4651 class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size,
4652 RegisterOperand regtype, string asm, string dstkind,
4653 string srckind, string amount>
4654 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4655 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4656 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4662 let Inst{29-24} = 0b101110;
4663 let Inst{23-22} = size;
4664 let Inst{21-10} = 0b100001001110;
4669 multiclass SIMDVectorLShiftLongBySizeBHS {
4670 let hasSideEffects = 0 in {
4671 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4672 "shll", ".8h", ".8b", "8">;
4673 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4674 "shll2", ".8h", ".16b", "8">;
4675 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4676 "shll", ".4s", ".4h", "16">;
4677 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4678 "shll2", ".4s", ".8h", "16">;
4679 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
4680 "shll", ".2d", ".2s", "32">;
4681 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4682 "shll2", ".2d", ".4s", "32">;
4686 // Supports all element sizes.
4687 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4688 SDPatternOperator OpNode> {
4689 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4691 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4692 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4694 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4695 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4697 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4698 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4700 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4701 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4703 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4704 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4706 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4709 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4710 SDPatternOperator OpNode> {
4711 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4713 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4715 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4717 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4718 (v16i8 V128:$Rn)))]>;
4719 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4721 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4722 (v4i16 V64:$Rn)))]>;
4723 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4725 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4726 (v8i16 V128:$Rn)))]>;
4727 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4729 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4730 (v2i32 V64:$Rn)))]>;
4731 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4733 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4734 (v4i32 V128:$Rn)))]>;
4737 // Supports all element sizes, except 1xD.
4738 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4739 SDPatternOperator OpNode> {
4740 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4742 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4743 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4744 asm, ".16b", ".16b",
4745 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4746 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4748 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4749 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4751 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4752 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4754 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4755 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4757 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4758 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, V128,
4760 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4763 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4764 SDPatternOperator OpNode = null_frag> {
4765 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4767 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4768 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4769 asm, ".16b", ".16b",
4770 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4771 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4773 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4774 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4776 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4777 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4779 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4780 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4782 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4783 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, V128,
4785 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4789 // Supports only B element sizes.
4790 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4791 SDPatternOperator OpNode> {
4792 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, V64,
4794 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4795 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, V128,
4796 asm, ".16b", ".16b",
4797 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4801 // Supports only B and H element sizes.
4802 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4803 SDPatternOperator OpNode> {
4804 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4806 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4807 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4808 asm, ".16b", ".16b",
4809 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4810 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4812 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4813 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4815 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4818 // Supports only S and D element sizes, uses high bit of the size field
4819 // as an extra opcode bit.
4820 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4821 SDPatternOperator OpNode> {
4822 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4824 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4825 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4827 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4828 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4830 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4833 // Supports only S element size.
4834 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4835 SDPatternOperator OpNode> {
4836 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4838 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4839 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4841 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4845 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4846 SDPatternOperator OpNode> {
4847 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4849 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4850 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4852 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4853 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4855 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4858 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4859 SDPatternOperator OpNode> {
4860 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4862 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4863 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4865 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4866 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4868 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4872 class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4873 RegisterOperand inreg, RegisterOperand outreg,
4874 string asm, string outkind, string inkind,
4876 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4877 "{\t$Rd" # outkind # ", $Rn" # inkind #
4878 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4885 let Inst{28-24} = 0b01110;
4886 let Inst{23-22} = size;
4887 let Inst{21-17} = 0b10000;
4888 let Inst{16-12} = opcode;
4889 let Inst{11-10} = 0b10;
4894 class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4895 RegisterOperand inreg, RegisterOperand outreg,
4896 string asm, string outkind, string inkind,
4898 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4899 "{\t$Rd" # outkind # ", $Rn" # inkind #
4900 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4907 let Inst{28-24} = 0b01110;
4908 let Inst{23-22} = size;
4909 let Inst{21-17} = 0b10000;
4910 let Inst{16-12} = opcode;
4911 let Inst{11-10} = 0b10;
4916 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4917 SDPatternOperator OpNode> {
4918 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4920 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4921 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4922 asm#"2", ".16b", ".8h", []>;
4923 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4925 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4926 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4927 asm#"2", ".8h", ".4s", []>;
4928 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4930 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4931 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4932 asm#"2", ".4s", ".2d", []>;
4934 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4935 (!cast<Instruction>(NAME # "v16i8")
4936 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4937 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4938 (!cast<Instruction>(NAME # "v8i16")
4939 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4940 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4941 (!cast<Instruction>(NAME # "v4i32")
4942 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4945 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4946 RegisterOperand regtype,
4947 string asm, string kind, string zero,
4948 ValueType dty, ValueType sty, SDNode OpNode>
4949 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4950 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
4951 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
4952 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4959 let Inst{28-24} = 0b01110;
4960 let Inst{23-22} = size;
4961 let Inst{21-17} = 0b10000;
4962 let Inst{16-12} = opcode;
4963 let Inst{11-10} = 0b10;
4968 // Comparisons support all element sizes, except 1xD.
4969 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
4971 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4973 v8i8, v8i8, OpNode>;
4974 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4976 v16i8, v16i8, OpNode>;
4977 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
4979 v4i16, v4i16, OpNode>;
4980 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
4982 v8i16, v8i16, OpNode>;
4983 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
4985 v2i32, v2i32, OpNode>;
4986 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
4988 v4i32, v4i32, OpNode>;
4989 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
4991 v2i64, v2i64, OpNode>;
4994 // FP Comparisons support only S and D element sizes.
4995 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
4996 string asm, SDNode OpNode> {
4998 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
5000 v2i32, v2f32, OpNode>;
5001 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
5003 v4i32, v4f32, OpNode>;
5004 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
5006 v2i64, v2f64, OpNode>;
5008 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
5009 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
5010 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
5011 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
5012 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
5013 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
5014 def : InstAlias<asm # ".2s\t$Vd, $Vn, #0",
5015 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
5016 def : InstAlias<asm # ".4s\t$Vd, $Vn, #0",
5017 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
5018 def : InstAlias<asm # ".2d\t$Vd, $Vn, #0",
5019 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
5022 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5023 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
5024 RegisterOperand outtype, RegisterOperand intype,
5025 string asm, string VdTy, string VnTy,
5027 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
5028 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
5035 let Inst{28-24} = 0b01110;
5036 let Inst{23-22} = size;
5037 let Inst{21-17} = 0b10000;
5038 let Inst{16-12} = opcode;
5039 let Inst{11-10} = 0b10;
5044 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
5045 RegisterOperand outtype, RegisterOperand intype,
5046 string asm, string VdTy, string VnTy,
5048 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
5049 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
5056 let Inst{28-24} = 0b01110;
5057 let Inst{23-22} = size;
5058 let Inst{21-17} = 0b10000;
5059 let Inst{16-12} = opcode;
5060 let Inst{11-10} = 0b10;
5065 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
5066 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
5067 asm, ".4s", ".4h", []>;
5068 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
5069 asm#"2", ".4s", ".8h", []>;
5070 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
5071 asm, ".2d", ".2s", []>;
5072 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
5073 asm#"2", ".2d", ".4s", []>;
5076 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
5077 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
5078 asm, ".4h", ".4s", []>;
5079 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
5080 asm#"2", ".8h", ".4s", []>;
5081 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
5082 asm, ".2s", ".2d", []>;
5083 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
5084 asm#"2", ".4s", ".2d", []>;
5087 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
5089 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
5091 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
5092 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
5093 asm#"2", ".4s", ".2d", []>;
5095 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
5096 (!cast<Instruction>(NAME # "v4f32")
5097 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
5100 //----------------------------------------------------------------------------
5101 // AdvSIMD three register different-size vector instructions.
5102 //----------------------------------------------------------------------------
5104 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5105 class BaseSIMDDifferentThreeVector<bit U, bits<3> size, bits<4> opcode,
5106 RegisterOperand outtype, RegisterOperand intype1,
5107 RegisterOperand intype2, string asm,
5108 string outkind, string inkind1, string inkind2,
5110 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
5111 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
5112 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
5118 let Inst{30} = size{0};
5120 let Inst{28-24} = 0b01110;
5121 let Inst{23-22} = size{2-1};
5123 let Inst{20-16} = Rm;
5124 let Inst{15-12} = opcode;
5125 let Inst{11-10} = 0b00;
5130 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5131 class BaseSIMDDifferentThreeVectorTied<bit U, bits<3> size, bits<4> opcode,
5132 RegisterOperand outtype, RegisterOperand intype1,
5133 RegisterOperand intype2, string asm,
5134 string outkind, string inkind1, string inkind2,
5136 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
5137 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
5138 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
5144 let Inst{30} = size{0};
5146 let Inst{28-24} = 0b01110;
5147 let Inst{23-22} = size{2-1};
5149 let Inst{20-16} = Rm;
5150 let Inst{15-12} = opcode;
5151 let Inst{11-10} = 0b00;
5156 // FIXME: TableGen doesn't know how to deal with expanded types that also
5157 // change the element count (in this case, placing the results in
5158 // the high elements of the result register rather than the low
5159 // elements). Until that's fixed, we can't code-gen those.
5160 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
5162 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5164 asm, ".8b", ".8h", ".8h",
5165 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5166 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5168 asm#"2", ".16b", ".8h", ".8h",
5170 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5172 asm, ".4h", ".4s", ".4s",
5173 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5174 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5176 asm#"2", ".8h", ".4s", ".4s",
5178 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5180 asm, ".2s", ".2d", ".2d",
5181 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5182 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5184 asm#"2", ".4s", ".2d", ".2d",
5188 // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in
5189 // a version attached to an instruction.
5190 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
5192 (!cast<Instruction>(NAME # "v8i16_v16i8")
5193 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5194 V128:$Rn, V128:$Rm)>;
5195 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
5197 (!cast<Instruction>(NAME # "v4i32_v8i16")
5198 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5199 V128:$Rn, V128:$Rm)>;
5200 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
5202 (!cast<Instruction>(NAME # "v2i64_v4i32")
5203 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5204 V128:$Rn, V128:$Rm)>;
5207 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
5209 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5211 asm, ".8h", ".8b", ".8b",
5212 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5213 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5215 asm#"2", ".8h", ".16b", ".16b", []>;
5216 let Predicates = [HasCrypto] in {
5217 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
5219 asm, ".1q", ".1d", ".1d", []>;
5220 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
5222 asm#"2", ".1q", ".2d", ".2d", []>;
5225 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
5226 (v8i8 (extract_high_v16i8 V128:$Rm)))),
5227 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
5230 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
5231 SDPatternOperator OpNode> {
5232 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5234 asm, ".4s", ".4h", ".4h",
5235 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5236 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5238 asm#"2", ".4s", ".8h", ".8h",
5239 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5240 (extract_high_v8i16 V128:$Rm)))]>;
5241 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5243 asm, ".2d", ".2s", ".2s",
5244 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5245 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5247 asm#"2", ".2d", ".4s", ".4s",
5248 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5249 (extract_high_v4i32 V128:$Rm)))]>;
5252 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
5253 SDPatternOperator OpNode = null_frag> {
5254 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5256 asm, ".8h", ".8b", ".8b",
5257 [(set (v8i16 V128:$Rd),
5258 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
5259 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5261 asm#"2", ".8h", ".16b", ".16b",
5262 [(set (v8i16 V128:$Rd),
5263 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5264 (extract_high_v16i8 V128:$Rm)))))]>;
5265 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5267 asm, ".4s", ".4h", ".4h",
5268 [(set (v4i32 V128:$Rd),
5269 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
5270 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5272 asm#"2", ".4s", ".8h", ".8h",
5273 [(set (v4i32 V128:$Rd),
5274 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5275 (extract_high_v8i16 V128:$Rm)))))]>;
5276 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5278 asm, ".2d", ".2s", ".2s",
5279 [(set (v2i64 V128:$Rd),
5280 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
5281 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5283 asm#"2", ".2d", ".4s", ".4s",
5284 [(set (v2i64 V128:$Rd),
5285 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5286 (extract_high_v4i32 V128:$Rm)))))]>;
5289 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
5291 SDPatternOperator OpNode> {
5292 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5294 asm, ".8h", ".8b", ".8b",
5295 [(set (v8i16 V128:$dst),
5296 (add (v8i16 V128:$Rd),
5297 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
5298 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5300 asm#"2", ".8h", ".16b", ".16b",
5301 [(set (v8i16 V128:$dst),
5302 (add (v8i16 V128:$Rd),
5303 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5304 (extract_high_v16i8 V128:$Rm))))))]>;
5305 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5307 asm, ".4s", ".4h", ".4h",
5308 [(set (v4i32 V128:$dst),
5309 (add (v4i32 V128:$Rd),
5310 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
5311 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5313 asm#"2", ".4s", ".8h", ".8h",
5314 [(set (v4i32 V128:$dst),
5315 (add (v4i32 V128:$Rd),
5316 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5317 (extract_high_v8i16 V128:$Rm))))))]>;
5318 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5320 asm, ".2d", ".2s", ".2s",
5321 [(set (v2i64 V128:$dst),
5322 (add (v2i64 V128:$Rd),
5323 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
5324 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5326 asm#"2", ".2d", ".4s", ".4s",
5327 [(set (v2i64 V128:$dst),
5328 (add (v2i64 V128:$Rd),
5329 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5330 (extract_high_v4i32 V128:$Rm))))))]>;
5333 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
5334 SDPatternOperator OpNode = null_frag> {
5335 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5337 asm, ".8h", ".8b", ".8b",
5338 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5339 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5341 asm#"2", ".8h", ".16b", ".16b",
5342 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5343 (extract_high_v16i8 V128:$Rm)))]>;
5344 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5346 asm, ".4s", ".4h", ".4h",
5347 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5348 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5350 asm#"2", ".4s", ".8h", ".8h",
5351 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5352 (extract_high_v8i16 V128:$Rm)))]>;
5353 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5355 asm, ".2d", ".2s", ".2s",
5356 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5357 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5359 asm#"2", ".2d", ".4s", ".4s",
5360 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5361 (extract_high_v4i32 V128:$Rm)))]>;
5364 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
5366 SDPatternOperator OpNode> {
5367 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5369 asm, ".8h", ".8b", ".8b",
5370 [(set (v8i16 V128:$dst),
5371 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5372 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5374 asm#"2", ".8h", ".16b", ".16b",
5375 [(set (v8i16 V128:$dst),
5376 (OpNode (v8i16 V128:$Rd),
5377 (extract_high_v16i8 V128:$Rn),
5378 (extract_high_v16i8 V128:$Rm)))]>;
5379 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5381 asm, ".4s", ".4h", ".4h",
5382 [(set (v4i32 V128:$dst),
5383 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5384 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5386 asm#"2", ".4s", ".8h", ".8h",
5387 [(set (v4i32 V128:$dst),
5388 (OpNode (v4i32 V128:$Rd),
5389 (extract_high_v8i16 V128:$Rn),
5390 (extract_high_v8i16 V128:$Rm)))]>;
5391 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5393 asm, ".2d", ".2s", ".2s",
5394 [(set (v2i64 V128:$dst),
5395 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5396 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5398 asm#"2", ".2d", ".4s", ".4s",
5399 [(set (v2i64 V128:$dst),
5400 (OpNode (v2i64 V128:$Rd),
5401 (extract_high_v4i32 V128:$Rn),
5402 (extract_high_v4i32 V128:$Rm)))]>;
5405 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
5406 SDPatternOperator Accum> {
5407 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5409 asm, ".4s", ".4h", ".4h",
5410 [(set (v4i32 V128:$dst),
5411 (Accum (v4i32 V128:$Rd),
5412 (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
5413 (v4i16 V64:$Rm)))))]>;
5414 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5416 asm#"2", ".4s", ".8h", ".8h",
5417 [(set (v4i32 V128:$dst),
5418 (Accum (v4i32 V128:$Rd),
5419 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
5420 (extract_high_v8i16 V128:$Rm)))))]>;
5421 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5423 asm, ".2d", ".2s", ".2s",
5424 [(set (v2i64 V128:$dst),
5425 (Accum (v2i64 V128:$Rd),
5426 (v2i64 (int_aarch64_neon_sqdmull (v2i32 V64:$Rn),
5427 (v2i32 V64:$Rm)))))]>;
5428 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5430 asm#"2", ".2d", ".4s", ".4s",
5431 [(set (v2i64 V128:$dst),
5432 (Accum (v2i64 V128:$Rd),
5433 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
5434 (extract_high_v4i32 V128:$Rm)))))]>;
5437 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
5438 SDPatternOperator OpNode> {
5439 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5441 asm, ".8h", ".8h", ".8b",
5442 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5443 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5445 asm#"2", ".8h", ".8h", ".16b",
5446 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5447 (extract_high_v16i8 V128:$Rm)))]>;
5448 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5450 asm, ".4s", ".4s", ".4h",
5451 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5452 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5454 asm#"2", ".4s", ".4s", ".8h",
5455 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5456 (extract_high_v8i16 V128:$Rm)))]>;
5457 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5459 asm, ".2d", ".2d", ".2s",
5460 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5461 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5463 asm#"2", ".2d", ".2d", ".4s",
5464 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5465 (extract_high_v4i32 V128:$Rm)))]>;
5468 //----------------------------------------------------------------------------
5469 // AdvSIMD bitwise extract from vector
5470 //----------------------------------------------------------------------------
5472 class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
5473 string asm, string kind>
5474 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5475 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5476 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5477 [(set (vty regtype:$Rd),
5478 (AArch64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
5485 let Inst{30} = size;
5486 let Inst{29-21} = 0b101110000;
5487 let Inst{20-16} = Rm;
5489 let Inst{14-11} = imm;
5496 multiclass SIMDBitwiseExtract<string asm> {
5497 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
5500 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
5503 //----------------------------------------------------------------------------
5504 // AdvSIMD zip vector
5505 //----------------------------------------------------------------------------
5507 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
5508 string asm, string kind, SDNode OpNode, ValueType valty>
5509 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5510 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5511 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5512 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5518 let Inst{30} = size{0};
5519 let Inst{29-24} = 0b001110;
5520 let Inst{23-22} = size{2-1};
5522 let Inst{20-16} = Rm;
5524 let Inst{14-12} = opc;
5525 let Inst{11-10} = 0b10;
5530 multiclass SIMDZipVector<bits<3>opc, string asm,
5532 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
5533 asm, ".8b", OpNode, v8i8>;
5534 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5535 asm, ".16b", OpNode, v16i8>;
5536 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
5537 asm, ".4h", OpNode, v4i16>;
5538 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5539 asm, ".8h", OpNode, v8i16>;
5540 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
5541 asm, ".2s", OpNode, v2i32>;
5542 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5543 asm, ".4s", OpNode, v4i32>;
5544 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5545 asm, ".2d", OpNode, v2i64>;
5547 def : Pat<(v4f16 (OpNode V64:$Rn, V64:$Rm)),
5548 (!cast<Instruction>(NAME#"v4i16") V64:$Rn, V64:$Rm)>;
5549 def : Pat<(v8f16 (OpNode V128:$Rn, V128:$Rm)),
5550 (!cast<Instruction>(NAME#"v8i16") V128:$Rn, V128:$Rm)>;
5551 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
5552 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
5553 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5554 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5555 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5556 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
5559 //----------------------------------------------------------------------------
5560 // AdvSIMD three register scalar instructions
5561 //----------------------------------------------------------------------------
5563 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5564 class BaseSIMDThreeScalar<bit U, bits<2> size, bits<5> opcode,
5565 RegisterClass regtype, string asm,
5567 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5568 "\t$Rd, $Rn, $Rm", "", pattern>,
5573 let Inst{31-30} = 0b01;
5575 let Inst{28-24} = 0b11110;
5576 let Inst{23-22} = size;
5578 let Inst{20-16} = Rm;
5579 let Inst{15-11} = opcode;
5585 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5586 class BaseSIMDThreeScalarTied<bit U, bits<2> size, bit R, bits<5> opcode,
5587 dag oops, dag iops, string asm,
5589 : I<oops, iops, asm, "\t$Rd, $Rn, $Rm", "$Rd = $dst", pattern>,
5594 let Inst{31-30} = 0b01;
5596 let Inst{28-24} = 0b11110;
5597 let Inst{23-22} = size;
5599 let Inst{20-16} = Rm;
5600 let Inst{15-11} = opcode;
5606 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
5607 SDPatternOperator OpNode> {
5608 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5609 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5612 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
5613 SDPatternOperator OpNode> {
5614 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5615 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5616 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
5617 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5618 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5620 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5621 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
5622 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
5623 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5626 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
5627 SDPatternOperator OpNode> {
5628 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
5629 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5630 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5633 multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm,
5634 SDPatternOperator OpNode = null_frag> {
5635 def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst),
5636 (ins FPR32:$Rd, FPR32:$Rn, FPR32:$Rm),
5638 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
5639 (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
5643 multiclass SIMDThreeScalarSD<bit U, bit S, bits<5> opc, string asm,
5644 SDPatternOperator OpNode = null_frag> {
5645 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5646 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5647 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5648 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5649 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5652 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5653 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5656 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<5> opc, string asm,
5657 SDPatternOperator OpNode = null_frag> {
5658 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5659 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5660 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5661 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5662 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5665 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5666 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5669 class BaseSIMDThreeScalarMixed<bit U, bits<2> size, bits<5> opcode,
5670 dag oops, dag iops, string asm, string cstr, list<dag> pat>
5671 : I<oops, iops, asm,
5672 "\t$Rd, $Rn, $Rm", cstr, pat>,
5677 let Inst{31-30} = 0b01;
5679 let Inst{28-24} = 0b11110;
5680 let Inst{23-22} = size;
5682 let Inst{20-16} = Rm;
5683 let Inst{15-11} = opcode;
5689 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5690 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
5691 SDPatternOperator OpNode = null_frag> {
5692 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5694 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
5695 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5697 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
5698 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5701 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5702 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
5703 SDPatternOperator OpNode = null_frag> {
5704 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5706 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5707 asm, "$Rd = $dst", []>;
5708 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5710 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5712 [(set (i64 FPR64:$dst),
5713 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5716 //----------------------------------------------------------------------------
5717 // AdvSIMD two register scalar instructions
5718 //----------------------------------------------------------------------------
5720 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5721 class BaseSIMDTwoScalar<bit U, bits<2> size, bits<5> opcode,
5722 RegisterClass regtype, RegisterClass regtype2,
5723 string asm, list<dag> pat>
5724 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5725 "\t$Rd, $Rn", "", pat>,
5729 let Inst{31-30} = 0b01;
5731 let Inst{28-24} = 0b11110;
5732 let Inst{23-22} = size;
5733 let Inst{21-17} = 0b10000;
5734 let Inst{16-12} = opcode;
5735 let Inst{11-10} = 0b10;
5740 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5741 class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
5742 RegisterClass regtype, RegisterClass regtype2,
5743 string asm, list<dag> pat>
5744 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5745 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5749 let Inst{31-30} = 0b01;
5751 let Inst{28-24} = 0b11110;
5752 let Inst{23-22} = size;
5753 let Inst{21-17} = 0b10000;
5754 let Inst{16-12} = opcode;
5755 let Inst{11-10} = 0b10;
5761 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5762 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
5763 RegisterClass regtype, string asm, string zero>
5764 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5765 "\t$Rd, $Rn, #" # zero, "", []>,
5769 let Inst{31-30} = 0b01;
5771 let Inst{28-24} = 0b11110;
5772 let Inst{23-22} = size;
5773 let Inst{21-17} = 0b10000;
5774 let Inst{16-12} = opcode;
5775 let Inst{11-10} = 0b10;
5780 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
5781 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5782 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5786 let Inst{31-17} = 0b011111100110000;
5787 let Inst{16-12} = opcode;
5788 let Inst{11-10} = 0b10;
5793 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5794 SDPatternOperator OpNode> {
5795 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
5797 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5798 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5801 multiclass SIMDFPCmpTwoScalar<bit U, bit S, bits<5> opc, string asm,
5802 SDPatternOperator OpNode> {
5803 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
5804 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
5806 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5807 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5808 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5809 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5811 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5812 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5815 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5816 SDPatternOperator OpNode = null_frag> {
5817 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5818 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5820 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5821 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5824 multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm> {
5825 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,[]>;
5826 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5829 multiclass SIMDTwoScalarCVTSD<bit U, bit S, bits<5> opc, string asm,
5830 SDPatternOperator OpNode> {
5831 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,
5832 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5833 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5834 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5837 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5838 SDPatternOperator OpNode = null_frag> {
5839 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5840 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5841 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5842 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5843 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5844 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5845 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5848 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5849 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5852 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5854 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5855 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5856 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5857 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5858 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5859 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5860 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5863 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5864 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5869 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5870 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5871 SDPatternOperator OpNode = null_frag> {
5872 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
5873 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5874 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
5875 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5878 //----------------------------------------------------------------------------
5879 // AdvSIMD scalar pairwise instructions
5880 //----------------------------------------------------------------------------
5882 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5883 class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
5884 RegisterOperand regtype, RegisterOperand vectype,
5885 string asm, string kind>
5886 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5887 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5891 let Inst{31-30} = 0b01;
5893 let Inst{28-24} = 0b11110;
5894 let Inst{23-22} = size;
5895 let Inst{21-17} = 0b11000;
5896 let Inst{16-12} = opcode;
5897 let Inst{11-10} = 0b10;
5902 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
5903 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
5907 multiclass SIMDFPPairwiseScalar<bit U, bit S, bits<5> opc, string asm> {
5908 def v2i32p : BaseSIMDPairwiseScalar<U, {S,0}, opc, FPR32Op, V64,
5910 def v2i64p : BaseSIMDPairwiseScalar<U, {S,1}, opc, FPR64Op, V128,
5914 //----------------------------------------------------------------------------
5915 // AdvSIMD across lanes instructions
5916 //----------------------------------------------------------------------------
5918 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5919 class BaseSIMDAcrossLanes<bit Q, bit U, bits<2> size, bits<5> opcode,
5920 RegisterClass regtype, RegisterOperand vectype,
5921 string asm, string kind, list<dag> pattern>
5922 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5923 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5930 let Inst{28-24} = 0b01110;
5931 let Inst{23-22} = size;
5932 let Inst{21-17} = 0b11000;
5933 let Inst{16-12} = opcode;
5934 let Inst{11-10} = 0b10;
5939 multiclass SIMDAcrossLanesBHS<bit U, bits<5> opcode,
5941 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5943 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5945 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
5947 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
5949 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
5953 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
5954 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5956 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5958 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
5960 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
5962 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
5966 multiclass SIMDAcrossLanesS<bits<5> opcode, bit sz1, string asm,
5968 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
5970 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5973 //----------------------------------------------------------------------------
5974 // AdvSIMD INS/DUP instructions
5975 //----------------------------------------------------------------------------
5977 // FIXME: There has got to be a better way to factor these. ugh.
5979 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
5980 string operands, string constraints, list<dag> pattern>
5981 : I<outs, ins, asm, operands, constraints, pattern>,
5988 let Inst{28-21} = 0b01110000;
5995 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5996 RegisterOperand vecreg, RegisterClass regtype>
5997 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5998 "{\t$Rd" # size # ", $Rn" #
5999 "|" # size # "\t$Rd, $Rn}", "",
6000 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
6001 let Inst{20-16} = imm5;
6002 let Inst{14-11} = 0b0001;
6005 class SIMDDupFromElement<bit Q, string dstkind, string srckind,
6006 ValueType vectype, ValueType insreg,
6007 RegisterOperand vecreg, Operand idxtype,
6008 ValueType elttype, SDNode OpNode>
6009 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
6010 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
6011 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
6012 [(set (vectype vecreg:$Rd),
6013 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
6014 let Inst{14-11} = 0b0000;
6017 class SIMDDup64FromElement
6018 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
6019 VectorIndexD, i64, AArch64duplane64> {
6022 let Inst{19-16} = 0b1000;
6025 class SIMDDup32FromElement<bit Q, string size, ValueType vectype,
6026 RegisterOperand vecreg>
6027 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
6028 VectorIndexS, i64, AArch64duplane32> {
6030 let Inst{20-19} = idx;
6031 let Inst{18-16} = 0b100;
6034 class SIMDDup16FromElement<bit Q, string size, ValueType vectype,
6035 RegisterOperand vecreg>
6036 : SIMDDupFromElement<Q, size, ".h", vectype, v8i16, vecreg,
6037 VectorIndexH, i64, AArch64duplane16> {
6039 let Inst{20-18} = idx;
6040 let Inst{17-16} = 0b10;
6043 class SIMDDup8FromElement<bit Q, string size, ValueType vectype,
6044 RegisterOperand vecreg>
6045 : SIMDDupFromElement<Q, size, ".b", vectype, v16i8, vecreg,
6046 VectorIndexB, i64, AArch64duplane8> {
6048 let Inst{20-17} = idx;
6052 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
6053 Operand idxtype, string asm, list<dag> pattern>
6054 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
6055 "{\t$Rd, $Rn" # size # "$idx" #
6056 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
6057 let Inst{14-11} = imm4;
6060 class SIMDSMov<bit Q, string size, RegisterClass regtype,
6062 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
6063 class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
6065 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
6066 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
6068 class SIMDMovAlias<string asm, string size, Instruction inst,
6069 RegisterClass regtype, Operand idxtype>
6070 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
6071 "|" # size # "\t$dst, $src$idx}",
6072 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
6075 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
6077 let Inst{20-17} = idx;
6080 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
6082 let Inst{20-17} = idx;
6085 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
6087 let Inst{20-18} = idx;
6088 let Inst{17-16} = 0b10;
6090 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
6092 let Inst{20-18} = idx;
6093 let Inst{17-16} = 0b10;
6095 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
6097 let Inst{20-19} = idx;
6098 let Inst{18-16} = 0b100;
6103 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
6105 let Inst{20-17} = idx;
6108 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
6110 let Inst{20-18} = idx;
6111 let Inst{17-16} = 0b10;
6113 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
6115 let Inst{20-19} = idx;
6116 let Inst{18-16} = 0b100;
6118 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
6121 let Inst{19-16} = 0b1000;
6123 def : SIMDMovAlias<"mov", ".s",
6124 !cast<Instruction>(NAME#"vi32"),
6125 GPR32, VectorIndexS>;
6126 def : SIMDMovAlias<"mov", ".d",
6127 !cast<Instruction>(NAME#"vi64"),
6128 GPR64, VectorIndexD>;
6131 class SIMDInsFromMain<string size, ValueType vectype,
6132 RegisterClass regtype, Operand idxtype>
6133 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
6134 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
6135 "{\t$Rd" # size # "$idx, $Rn" #
6136 "|" # size # "\t$Rd$idx, $Rn}",
6139 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
6140 let Inst{14-11} = 0b0011;
6143 class SIMDInsFromElement<string size, ValueType vectype,
6144 ValueType elttype, Operand idxtype>
6145 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
6146 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
6147 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
6148 "|" # size # "\t$Rd$idx, $Rn$idx2}",
6153 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
6156 class SIMDInsMainMovAlias<string size, Instruction inst,
6157 RegisterClass regtype, Operand idxtype>
6158 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
6159 "|" # size #"\t$dst$idx, $src}",
6160 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
6161 class SIMDInsElementMovAlias<string size, Instruction inst,
6163 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
6164 # "|" # size #"\t$dst$idx, $src$idx2}",
6165 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
6168 multiclass SIMDIns {
6169 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
6171 let Inst{20-17} = idx;
6174 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
6176 let Inst{20-18} = idx;
6177 let Inst{17-16} = 0b10;
6179 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
6181 let Inst{20-19} = idx;
6182 let Inst{18-16} = 0b100;
6184 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
6187 let Inst{19-16} = 0b1000;
6190 def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> {
6193 let Inst{20-17} = idx;
6195 let Inst{14-11} = idx2;
6197 def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> {
6200 let Inst{20-18} = idx;
6201 let Inst{17-16} = 0b10;
6202 let Inst{14-12} = idx2;
6205 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
6208 let Inst{20-19} = idx;
6209 let Inst{18-16} = 0b100;
6210 let Inst{14-13} = idx2;
6211 let Inst{12-11} = {?,?};
6213 def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> {
6217 let Inst{19-16} = 0b1000;
6218 let Inst{14} = idx2;
6219 let Inst{13-11} = {?,?,?};
6222 // For all forms of the INS instruction, the "mov" mnemonic is the
6223 // preferred alias. Why they didn't just call the instruction "mov" in
6224 // the first place is a very good question indeed...
6225 def : SIMDInsMainMovAlias<".b", !cast<Instruction>(NAME#"vi8gpr"),
6226 GPR32, VectorIndexB>;
6227 def : SIMDInsMainMovAlias<".h", !cast<Instruction>(NAME#"vi16gpr"),
6228 GPR32, VectorIndexH>;
6229 def : SIMDInsMainMovAlias<".s", !cast<Instruction>(NAME#"vi32gpr"),
6230 GPR32, VectorIndexS>;
6231 def : SIMDInsMainMovAlias<".d", !cast<Instruction>(NAME#"vi64gpr"),
6232 GPR64, VectorIndexD>;
6234 def : SIMDInsElementMovAlias<".b", !cast<Instruction>(NAME#"vi8lane"),
6236 def : SIMDInsElementMovAlias<".h", !cast<Instruction>(NAME#"vi16lane"),
6238 def : SIMDInsElementMovAlias<".s", !cast<Instruction>(NAME#"vi32lane"),
6240 def : SIMDInsElementMovAlias<".d", !cast<Instruction>(NAME#"vi64lane"),
6244 //----------------------------------------------------------------------------
6246 //----------------------------------------------------------------------------
6248 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6249 class BaseSIMDTableLookup<bit Q, bits<2> len, bit op, RegisterOperand vectype,
6250 RegisterOperand listtype, string asm, string kind>
6251 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
6252 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
6259 let Inst{29-21} = 0b001110000;
6260 let Inst{20-16} = Vm;
6262 let Inst{14-13} = len;
6264 let Inst{11-10} = 0b00;
6269 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6270 class BaseSIMDTableLookupTied<bit Q, bits<2> len, bit op, RegisterOperand vectype,
6271 RegisterOperand listtype, string asm, string kind>
6272 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
6273 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
6280 let Inst{29-21} = 0b001110000;
6281 let Inst{20-16} = Vm;
6283 let Inst{14-13} = len;
6285 let Inst{11-10} = 0b00;
6290 class SIMDTableLookupAlias<string asm, Instruction inst,
6291 RegisterOperand vectype, RegisterOperand listtype>
6292 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
6293 (inst vectype:$dst, listtype:$lst, vectype:$index), 0>;
6295 multiclass SIMDTableLookup<bit op, string asm> {
6296 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
6298 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
6300 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
6302 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
6304 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
6306 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
6308 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
6310 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
6313 def : SIMDTableLookupAlias<asm # ".8b",
6314 !cast<Instruction>(NAME#"v8i8One"),
6315 V64, VecListOne128>;
6316 def : SIMDTableLookupAlias<asm # ".8b",
6317 !cast<Instruction>(NAME#"v8i8Two"),
6318 V64, VecListTwo128>;
6319 def : SIMDTableLookupAlias<asm # ".8b",
6320 !cast<Instruction>(NAME#"v8i8Three"),
6321 V64, VecListThree128>;
6322 def : SIMDTableLookupAlias<asm # ".8b",
6323 !cast<Instruction>(NAME#"v8i8Four"),
6324 V64, VecListFour128>;
6325 def : SIMDTableLookupAlias<asm # ".16b",
6326 !cast<Instruction>(NAME#"v16i8One"),
6327 V128, VecListOne128>;
6328 def : SIMDTableLookupAlias<asm # ".16b",
6329 !cast<Instruction>(NAME#"v16i8Two"),
6330 V128, VecListTwo128>;
6331 def : SIMDTableLookupAlias<asm # ".16b",
6332 !cast<Instruction>(NAME#"v16i8Three"),
6333 V128, VecListThree128>;
6334 def : SIMDTableLookupAlias<asm # ".16b",
6335 !cast<Instruction>(NAME#"v16i8Four"),
6336 V128, VecListFour128>;
6339 multiclass SIMDTableLookupTied<bit op, string asm> {
6340 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
6342 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
6344 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
6346 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
6348 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
6350 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
6352 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
6354 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
6357 def : SIMDTableLookupAlias<asm # ".8b",
6358 !cast<Instruction>(NAME#"v8i8One"),
6359 V64, VecListOne128>;
6360 def : SIMDTableLookupAlias<asm # ".8b",
6361 !cast<Instruction>(NAME#"v8i8Two"),
6362 V64, VecListTwo128>;
6363 def : SIMDTableLookupAlias<asm # ".8b",
6364 !cast<Instruction>(NAME#"v8i8Three"),
6365 V64, VecListThree128>;
6366 def : SIMDTableLookupAlias<asm # ".8b",
6367 !cast<Instruction>(NAME#"v8i8Four"),
6368 V64, VecListFour128>;
6369 def : SIMDTableLookupAlias<asm # ".16b",
6370 !cast<Instruction>(NAME#"v16i8One"),
6371 V128, VecListOne128>;
6372 def : SIMDTableLookupAlias<asm # ".16b",
6373 !cast<Instruction>(NAME#"v16i8Two"),
6374 V128, VecListTwo128>;
6375 def : SIMDTableLookupAlias<asm # ".16b",
6376 !cast<Instruction>(NAME#"v16i8Three"),
6377 V128, VecListThree128>;
6378 def : SIMDTableLookupAlias<asm # ".16b",
6379 !cast<Instruction>(NAME#"v16i8Four"),
6380 V128, VecListFour128>;
6384 //----------------------------------------------------------------------------
6385 // AdvSIMD scalar CPY
6386 //----------------------------------------------------------------------------
6387 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6388 class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
6389 string kind, Operand idxtype>
6390 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
6391 "{\t$dst, $src" # kind # "$idx" #
6392 "|\t$dst, $src$idx}", "", []>,
6396 let Inst{31-21} = 0b01011110000;
6397 let Inst{15-10} = 0b000001;
6398 let Inst{9-5} = src;
6399 let Inst{4-0} = dst;
6402 class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
6403 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
6404 : InstAlias<asm # "{\t$dst, $src" # size # "$index" #
6405 # "|\t$dst, $src$index}",
6406 (inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
6409 multiclass SIMDScalarCPY<string asm> {
6410 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
6412 let Inst{20-17} = idx;
6415 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
6417 let Inst{20-18} = idx;
6418 let Inst{17-16} = 0b10;
6420 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
6422 let Inst{20-19} = idx;
6423 let Inst{18-16} = 0b100;
6425 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
6428 let Inst{19-16} = 0b1000;
6431 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
6432 VectorIndexD:$idx)))),
6433 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
6435 // 'DUP' mnemonic aliases.
6436 def : SIMDScalarCPYAlias<"dup", ".b",
6437 !cast<Instruction>(NAME#"i8"),
6438 FPR8, V128, VectorIndexB>;
6439 def : SIMDScalarCPYAlias<"dup", ".h",
6440 !cast<Instruction>(NAME#"i16"),
6441 FPR16, V128, VectorIndexH>;
6442 def : SIMDScalarCPYAlias<"dup", ".s",
6443 !cast<Instruction>(NAME#"i32"),
6444 FPR32, V128, VectorIndexS>;
6445 def : SIMDScalarCPYAlias<"dup", ".d",
6446 !cast<Instruction>(NAME#"i64"),
6447 FPR64, V128, VectorIndexD>;
6450 //----------------------------------------------------------------------------
6451 // AdvSIMD modified immediate instructions
6452 //----------------------------------------------------------------------------
6454 class BaseSIMDModifiedImm<bit Q, bit op, dag oops, dag iops,
6455 string asm, string op_string,
6456 string cstr, list<dag> pattern>
6457 : I<oops, iops, asm, op_string, cstr, pattern>,
6464 let Inst{28-19} = 0b0111100000;
6465 let Inst{18-16} = imm8{7-5};
6466 let Inst{11-10} = 0b01;
6467 let Inst{9-5} = imm8{4-0};
6471 class BaseSIMDModifiedImmVector<bit Q, bit op, RegisterOperand vectype,
6472 Operand immtype, dag opt_shift_iop,
6473 string opt_shift, string asm, string kind,
6475 : BaseSIMDModifiedImm<Q, op, (outs vectype:$Rd),
6476 !con((ins immtype:$imm8), opt_shift_iop), asm,
6477 "{\t$Rd" # kind # ", $imm8" # opt_shift #
6478 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6480 let DecoderMethod = "DecodeModImmInstruction";
6483 class BaseSIMDModifiedImmVectorTied<bit Q, bit op, RegisterOperand vectype,
6484 Operand immtype, dag opt_shift_iop,
6485 string opt_shift, string asm, string kind,
6487 : BaseSIMDModifiedImm<Q, op, (outs vectype:$dst),
6488 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
6489 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
6490 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6491 "$Rd = $dst", pattern> {
6492 let DecoderMethod = "DecodeModImmTiedInstruction";
6495 class BaseSIMDModifiedImmVectorShift<bit Q, bit op, bits<2> b15_b12,
6496 RegisterOperand vectype, string asm,
6497 string kind, list<dag> pattern>
6498 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6499 (ins logical_vec_shift:$shift),
6500 "$shift", asm, kind, pattern> {
6502 let Inst{15} = b15_b12{1};
6503 let Inst{14-13} = shift;
6504 let Inst{12} = b15_b12{0};
6507 class BaseSIMDModifiedImmVectorShiftTied<bit Q, bit op, bits<2> b15_b12,
6508 RegisterOperand vectype, string asm,
6509 string kind, list<dag> pattern>
6510 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6511 (ins logical_vec_shift:$shift),
6512 "$shift", asm, kind, pattern> {
6514 let Inst{15} = b15_b12{1};
6515 let Inst{14-13} = shift;
6516 let Inst{12} = b15_b12{0};
6520 class BaseSIMDModifiedImmVectorShiftHalf<bit Q, bit op, bits<2> b15_b12,
6521 RegisterOperand vectype, string asm,
6522 string kind, list<dag> pattern>
6523 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6524 (ins logical_vec_hw_shift:$shift),
6525 "$shift", asm, kind, pattern> {
6527 let Inst{15} = b15_b12{1};
6529 let Inst{13} = shift{0};
6530 let Inst{12} = b15_b12{0};
6533 class BaseSIMDModifiedImmVectorShiftHalfTied<bit Q, bit op, bits<2> b15_b12,
6534 RegisterOperand vectype, string asm,
6535 string kind, list<dag> pattern>
6536 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6537 (ins logical_vec_hw_shift:$shift),
6538 "$shift", asm, kind, pattern> {
6540 let Inst{15} = b15_b12{1};
6542 let Inst{13} = shift{0};
6543 let Inst{12} = b15_b12{0};
6546 multiclass SIMDModifiedImmVectorShift<bit op, bits<2> hw_cmode, bits<2> w_cmode,
6548 def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64,
6550 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
6553 def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64,
6555 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
6559 multiclass SIMDModifiedImmVectorShiftTied<bit op, bits<2> hw_cmode,
6560 bits<2> w_cmode, string asm,
6562 def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64,
6564 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6566 (i32 imm:$shift)))]>;
6567 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
6569 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6571 (i32 imm:$shift)))]>;
6573 def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64,
6575 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6577 (i32 imm:$shift)))]>;
6578 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
6580 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6582 (i32 imm:$shift)))]>;
6585 class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
6586 RegisterOperand vectype, string asm,
6587 string kind, list<dag> pattern>
6588 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6589 (ins move_vec_shift:$shift),
6590 "$shift", asm, kind, pattern> {
6592 let Inst{15-13} = cmode{3-1};
6593 let Inst{12} = shift;
6596 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bits<4> cmode,
6597 RegisterOperand vectype,
6598 Operand imm_type, string asm,
6599 string kind, list<dag> pattern>
6600 : BaseSIMDModifiedImmVector<Q, op, vectype, imm_type, (ins), "",
6601 asm, kind, pattern> {
6602 let Inst{15-12} = cmode;
6605 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
6607 : BaseSIMDModifiedImm<Q, op, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6608 "\t$Rd, $imm8", "", pattern> {
6609 let Inst{15-12} = cmode;
6610 let DecoderMethod = "DecodeModImmInstruction";
6613 //----------------------------------------------------------------------------
6614 // AdvSIMD indexed element
6615 //----------------------------------------------------------------------------
6617 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6618 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6619 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6620 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6621 string apple_kind, string dst_kind, string lhs_kind,
6622 string rhs_kind, list<dag> pattern>
6623 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6625 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6626 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6635 let Inst{28} = Scalar;
6636 let Inst{27-24} = 0b1111;
6637 let Inst{23-22} = size;
6638 // Bit 21 must be set by the derived class.
6639 let Inst{20-16} = Rm;
6640 let Inst{15-12} = opc;
6641 // Bit 11 must be set by the derived class.
6647 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6648 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6649 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6650 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6651 string apple_kind, string dst_kind, string lhs_kind,
6652 string rhs_kind, list<dag> pattern>
6653 : I<(outs dst_reg:$dst),
6654 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6655 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6656 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6665 let Inst{28} = Scalar;
6666 let Inst{27-24} = 0b1111;
6667 let Inst{23-22} = size;
6668 // Bit 21 must be set by the derived class.
6669 let Inst{20-16} = Rm;
6670 let Inst{15-12} = opc;
6671 // Bit 11 must be set by the derived class.
6677 multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
6678 SDPatternOperator OpNode> {
6679 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6682 asm, ".2s", ".2s", ".2s", ".s",
6683 [(set (v2f32 V64:$Rd),
6684 (OpNode (v2f32 V64:$Rn),
6685 (v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6687 let Inst{11} = idx{1};
6688 let Inst{21} = idx{0};
6691 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6694 asm, ".4s", ".4s", ".4s", ".s",
6695 [(set (v4f32 V128:$Rd),
6696 (OpNode (v4f32 V128:$Rn),
6697 (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6699 let Inst{11} = idx{1};
6700 let Inst{21} = idx{0};
6703 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
6706 asm, ".2d", ".2d", ".2d", ".d",
6707 [(set (v2f64 V128:$Rd),
6708 (OpNode (v2f64 V128:$Rn),
6709 (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
6711 let Inst{11} = idx{0};
6715 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6716 FPR32Op, FPR32Op, V128, VectorIndexS,
6717 asm, ".s", "", "", ".s",
6718 [(set (f32 FPR32Op:$Rd),
6719 (OpNode (f32 FPR32Op:$Rn),
6720 (f32 (vector_extract (v4f32 V128:$Rm),
6721 VectorIndexS:$idx))))]> {
6723 let Inst{11} = idx{1};
6724 let Inst{21} = idx{0};
6727 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6728 FPR64Op, FPR64Op, V128, VectorIndexD,
6729 asm, ".d", "", "", ".d",
6730 [(set (f64 FPR64Op:$Rd),
6731 (OpNode (f64 FPR64Op:$Rn),
6732 (f64 (vector_extract (v2f64 V128:$Rm),
6733 VectorIndexD:$idx))))]> {
6735 let Inst{11} = idx{0};
6740 multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
6741 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
6742 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6743 (AArch64duplane32 (v4f32 V128:$Rm),
6744 VectorIndexS:$idx))),
6745 (!cast<Instruction>(INST # v2i32_indexed)
6746 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6747 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6748 (AArch64dup (f32 FPR32Op:$Rm)))),
6749 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6750 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6753 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
6754 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6755 (AArch64duplane32 (v4f32 V128:$Rm),
6756 VectorIndexS:$idx))),
6757 (!cast<Instruction>(INST # "v4i32_indexed")
6758 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6759 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6760 (AArch64dup (f32 FPR32Op:$Rm)))),
6761 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6762 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6764 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
6765 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6766 (AArch64duplane64 (v2f64 V128:$Rm),
6767 VectorIndexD:$idx))),
6768 (!cast<Instruction>(INST # "v2i64_indexed")
6769 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6770 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6771 (AArch64dup (f64 FPR64Op:$Rm)))),
6772 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6773 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
6775 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
6776 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6777 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6778 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6779 V128:$Rm, VectorIndexS:$idx)>;
6780 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6781 (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))),
6782 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6783 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
6785 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
6786 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6787 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6788 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6789 V128:$Rm, VectorIndexD:$idx)>;
6792 multiclass SIMDFPIndexedTied<bit U, bits<4> opc, string asm> {
6793 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6795 asm, ".2s", ".2s", ".2s", ".s", []> {
6797 let Inst{11} = idx{1};
6798 let Inst{21} = idx{0};
6801 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6804 asm, ".4s", ".4s", ".4s", ".s", []> {
6806 let Inst{11} = idx{1};
6807 let Inst{21} = idx{0};
6810 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6813 asm, ".2d", ".2d", ".2d", ".d", []> {
6815 let Inst{11} = idx{0};
6820 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6821 FPR32Op, FPR32Op, V128, VectorIndexS,
6822 asm, ".s", "", "", ".s", []> {
6824 let Inst{11} = idx{1};
6825 let Inst{21} = idx{0};
6828 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
6829 FPR64Op, FPR64Op, V128, VectorIndexD,
6830 asm, ".d", "", "", ".d", []> {
6832 let Inst{11} = idx{0};
6837 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
6838 SDPatternOperator OpNode> {
6839 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
6840 V128_lo, VectorIndexH,
6841 asm, ".4h", ".4h", ".4h", ".h",
6842 [(set (v4i16 V64:$Rd),
6843 (OpNode (v4i16 V64:$Rn),
6844 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6846 let Inst{11} = idx{2};
6847 let Inst{21} = idx{1};
6848 let Inst{20} = idx{0};
6851 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6853 V128_lo, VectorIndexH,
6854 asm, ".8h", ".8h", ".8h", ".h",
6855 [(set (v8i16 V128:$Rd),
6856 (OpNode (v8i16 V128:$Rn),
6857 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6859 let Inst{11} = idx{2};
6860 let Inst{21} = idx{1};
6861 let Inst{20} = idx{0};
6864 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6867 asm, ".2s", ".2s", ".2s", ".s",
6868 [(set (v2i32 V64:$Rd),
6869 (OpNode (v2i32 V64:$Rn),
6870 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6872 let Inst{11} = idx{1};
6873 let Inst{21} = idx{0};
6876 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6879 asm, ".4s", ".4s", ".4s", ".s",
6880 [(set (v4i32 V128:$Rd),
6881 (OpNode (v4i32 V128:$Rn),
6882 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6884 let Inst{11} = idx{1};
6885 let Inst{21} = idx{0};
6888 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6889 FPR16Op, FPR16Op, V128_lo, VectorIndexH,
6890 asm, ".h", "", "", ".h", []> {
6892 let Inst{11} = idx{2};
6893 let Inst{21} = idx{1};
6894 let Inst{20} = idx{0};
6897 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6898 FPR32Op, FPR32Op, V128, VectorIndexS,
6899 asm, ".s", "", "", ".s",
6900 [(set (i32 FPR32Op:$Rd),
6901 (OpNode FPR32Op:$Rn,
6902 (i32 (vector_extract (v4i32 V128:$Rm),
6903 VectorIndexS:$idx))))]> {
6905 let Inst{11} = idx{1};
6906 let Inst{21} = idx{0};
6910 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
6911 SDPatternOperator OpNode> {
6912 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6914 V128_lo, VectorIndexH,
6915 asm, ".4h", ".4h", ".4h", ".h",
6916 [(set (v4i16 V64:$Rd),
6917 (OpNode (v4i16 V64:$Rn),
6918 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6920 let Inst{11} = idx{2};
6921 let Inst{21} = idx{1};
6922 let Inst{20} = idx{0};
6925 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6927 V128_lo, VectorIndexH,
6928 asm, ".8h", ".8h", ".8h", ".h",
6929 [(set (v8i16 V128:$Rd),
6930 (OpNode (v8i16 V128:$Rn),
6931 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6933 let Inst{11} = idx{2};
6934 let Inst{21} = idx{1};
6935 let Inst{20} = idx{0};
6938 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6941 asm, ".2s", ".2s", ".2s", ".s",
6942 [(set (v2i32 V64:$Rd),
6943 (OpNode (v2i32 V64:$Rn),
6944 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6946 let Inst{11} = idx{1};
6947 let Inst{21} = idx{0};
6950 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6953 asm, ".4s", ".4s", ".4s", ".s",
6954 [(set (v4i32 V128:$Rd),
6955 (OpNode (v4i32 V128:$Rn),
6956 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6958 let Inst{11} = idx{1};
6959 let Inst{21} = idx{0};
6963 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
6964 SDPatternOperator OpNode> {
6965 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
6966 V128_lo, VectorIndexH,
6967 asm, ".4h", ".4h", ".4h", ".h",
6968 [(set (v4i16 V64:$dst),
6969 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6970 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6972 let Inst{11} = idx{2};
6973 let Inst{21} = idx{1};
6974 let Inst{20} = idx{0};
6977 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6979 V128_lo, VectorIndexH,
6980 asm, ".8h", ".8h", ".8h", ".h",
6981 [(set (v8i16 V128:$dst),
6982 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6983 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6985 let Inst{11} = idx{2};
6986 let Inst{21} = idx{1};
6987 let Inst{20} = idx{0};
6990 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6993 asm, ".2s", ".2s", ".2s", ".s",
6994 [(set (v2i32 V64:$dst),
6995 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6996 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6998 let Inst{11} = idx{1};
6999 let Inst{21} = idx{0};
7002 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
7005 asm, ".4s", ".4s", ".4s", ".s",
7006 [(set (v4i32 V128:$dst),
7007 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7008 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7010 let Inst{11} = idx{1};
7011 let Inst{21} = idx{0};
7015 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
7016 SDPatternOperator OpNode> {
7017 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
7019 V128_lo, VectorIndexH,
7020 asm, ".4s", ".4s", ".4h", ".h",
7021 [(set (v4i32 V128:$Rd),
7022 (OpNode (v4i16 V64:$Rn),
7023 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
7025 let Inst{11} = idx{2};
7026 let Inst{21} = idx{1};
7027 let Inst{20} = idx{0};
7030 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7032 V128_lo, VectorIndexH,
7033 asm#"2", ".4s", ".4s", ".8h", ".h",
7034 [(set (v4i32 V128:$Rd),
7035 (OpNode (extract_high_v8i16 V128:$Rn),
7036 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
7037 VectorIndexH:$idx))))]> {
7040 let Inst{11} = idx{2};
7041 let Inst{21} = idx{1};
7042 let Inst{20} = idx{0};
7045 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
7048 asm, ".2d", ".2d", ".2s", ".s",
7049 [(set (v2i64 V128:$Rd),
7050 (OpNode (v2i32 V64:$Rn),
7051 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7053 let Inst{11} = idx{1};
7054 let Inst{21} = idx{0};
7057 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
7060 asm#"2", ".2d", ".2d", ".4s", ".s",
7061 [(set (v2i64 V128:$Rd),
7062 (OpNode (extract_high_v4i32 V128:$Rn),
7063 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
7064 VectorIndexS:$idx))))]> {
7066 let Inst{11} = idx{1};
7067 let Inst{21} = idx{0};
7070 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
7071 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
7072 asm, ".h", "", "", ".h", []> {
7074 let Inst{11} = idx{2};
7075 let Inst{21} = idx{1};
7076 let Inst{20} = idx{0};
7079 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
7080 FPR64Op, FPR32Op, V128, VectorIndexS,
7081 asm, ".s", "", "", ".s", []> {
7083 let Inst{11} = idx{1};
7084 let Inst{21} = idx{0};
7088 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
7089 SDPatternOperator Accum> {
7090 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
7092 V128_lo, VectorIndexH,
7093 asm, ".4s", ".4s", ".4h", ".h",
7094 [(set (v4i32 V128:$dst),
7095 (Accum (v4i32 V128:$Rd),
7096 (v4i32 (int_aarch64_neon_sqdmull
7098 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
7099 VectorIndexH:$idx))))))]> {
7101 let Inst{11} = idx{2};
7102 let Inst{21} = idx{1};
7103 let Inst{20} = idx{0};
7106 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
7107 // intermediate EXTRACT_SUBREG would be untyped.
7108 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
7109 (i32 (vector_extract (v4i32
7110 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
7111 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
7112 VectorIndexH:$idx)))),
7115 (!cast<Instruction>(NAME # v4i16_indexed)
7116 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
7117 V128_lo:$Rm, VectorIndexH:$idx),
7120 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
7122 V128_lo, VectorIndexH,
7123 asm#"2", ".4s", ".4s", ".8h", ".h",
7124 [(set (v4i32 V128:$dst),
7125 (Accum (v4i32 V128:$Rd),
7126 (v4i32 (int_aarch64_neon_sqdmull
7127 (extract_high_v8i16 V128:$Rn),
7129 (AArch64duplane16 (v8i16 V128_lo:$Rm),
7130 VectorIndexH:$idx))))))]> {
7132 let Inst{11} = idx{2};
7133 let Inst{21} = idx{1};
7134 let Inst{20} = idx{0};
7137 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
7140 asm, ".2d", ".2d", ".2s", ".s",
7141 [(set (v2i64 V128:$dst),
7142 (Accum (v2i64 V128:$Rd),
7143 (v2i64 (int_aarch64_neon_sqdmull
7145 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
7146 VectorIndexS:$idx))))))]> {
7148 let Inst{11} = idx{1};
7149 let Inst{21} = idx{0};
7152 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
7155 asm#"2", ".2d", ".2d", ".4s", ".s",
7156 [(set (v2i64 V128:$dst),
7157 (Accum (v2i64 V128:$Rd),
7158 (v2i64 (int_aarch64_neon_sqdmull
7159 (extract_high_v4i32 V128:$Rn),
7161 (AArch64duplane32 (v4i32 V128:$Rm),
7162 VectorIndexS:$idx))))))]> {
7164 let Inst{11} = idx{1};
7165 let Inst{21} = idx{0};
7168 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
7169 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
7170 asm, ".h", "", "", ".h", []> {
7172 let Inst{11} = idx{2};
7173 let Inst{21} = idx{1};
7174 let Inst{20} = idx{0};
7178 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
7179 FPR64Op, FPR32Op, V128, VectorIndexS,
7180 asm, ".s", "", "", ".s",
7181 [(set (i64 FPR64Op:$dst),
7182 (Accum (i64 FPR64Op:$Rd),
7183 (i64 (int_aarch64_neon_sqdmulls_scalar
7185 (i32 (vector_extract (v4i32 V128:$Rm),
7186 VectorIndexS:$idx))))))]> {
7189 let Inst{11} = idx{1};
7190 let Inst{21} = idx{0};
7194 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
7195 SDPatternOperator OpNode> {
7196 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
7197 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
7199 V128_lo, VectorIndexH,
7200 asm, ".4s", ".4s", ".4h", ".h",
7201 [(set (v4i32 V128:$Rd),
7202 (OpNode (v4i16 V64:$Rn),
7203 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
7205 let Inst{11} = idx{2};
7206 let Inst{21} = idx{1};
7207 let Inst{20} = idx{0};
7210 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7212 V128_lo, VectorIndexH,
7213 asm#"2", ".4s", ".4s", ".8h", ".h",
7214 [(set (v4i32 V128:$Rd),
7215 (OpNode (extract_high_v8i16 V128:$Rn),
7216 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
7217 VectorIndexH:$idx))))]> {
7220 let Inst{11} = idx{2};
7221 let Inst{21} = idx{1};
7222 let Inst{20} = idx{0};
7225 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
7228 asm, ".2d", ".2d", ".2s", ".s",
7229 [(set (v2i64 V128:$Rd),
7230 (OpNode (v2i32 V64:$Rn),
7231 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7233 let Inst{11} = idx{1};
7234 let Inst{21} = idx{0};
7237 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
7240 asm#"2", ".2d", ".2d", ".4s", ".s",
7241 [(set (v2i64 V128:$Rd),
7242 (OpNode (extract_high_v4i32 V128:$Rn),
7243 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
7244 VectorIndexS:$idx))))]> {
7246 let Inst{11} = idx{1};
7247 let Inst{21} = idx{0};
7252 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
7253 SDPatternOperator OpNode> {
7254 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
7255 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
7257 V128_lo, VectorIndexH,
7258 asm, ".4s", ".4s", ".4h", ".h",
7259 [(set (v4i32 V128:$dst),
7260 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
7261 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
7263 let Inst{11} = idx{2};
7264 let Inst{21} = idx{1};
7265 let Inst{20} = idx{0};
7268 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
7270 V128_lo, VectorIndexH,
7271 asm#"2", ".4s", ".4s", ".8h", ".h",
7272 [(set (v4i32 V128:$dst),
7273 (OpNode (v4i32 V128:$Rd),
7274 (extract_high_v8i16 V128:$Rn),
7275 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
7276 VectorIndexH:$idx))))]> {
7278 let Inst{11} = idx{2};
7279 let Inst{21} = idx{1};
7280 let Inst{20} = idx{0};
7283 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
7286 asm, ".2d", ".2d", ".2s", ".s",
7287 [(set (v2i64 V128:$dst),
7288 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
7289 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7291 let Inst{11} = idx{1};
7292 let Inst{21} = idx{0};
7295 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
7298 asm#"2", ".2d", ".2d", ".4s", ".s",
7299 [(set (v2i64 V128:$dst),
7300 (OpNode (v2i64 V128:$Rd),
7301 (extract_high_v4i32 V128:$Rn),
7302 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
7303 VectorIndexS:$idx))))]> {
7305 let Inst{11} = idx{1};
7306 let Inst{21} = idx{0};
7311 //----------------------------------------------------------------------------
7312 // AdvSIMD scalar shift by immediate
7313 //----------------------------------------------------------------------------
7315 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7316 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
7317 RegisterClass regtype1, RegisterClass regtype2,
7318 Operand immtype, string asm, list<dag> pattern>
7319 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
7320 asm, "\t$Rd, $Rn, $imm", "", pattern>,
7325 let Inst{31-30} = 0b01;
7327 let Inst{28-23} = 0b111110;
7328 let Inst{22-16} = fixed_imm;
7329 let Inst{15-11} = opc;
7335 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7336 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
7337 RegisterClass regtype1, RegisterClass regtype2,
7338 Operand immtype, string asm, list<dag> pattern>
7339 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
7340 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
7345 let Inst{31-30} = 0b01;
7347 let Inst{28-23} = 0b111110;
7348 let Inst{22-16} = fixed_imm;
7349 let Inst{15-11} = opc;
7356 multiclass SIMDScalarRShiftSD<bit U, bits<5> opc, string asm> {
7357 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7358 FPR32, FPR32, vecshiftR32, asm, []> {
7359 let Inst{20-16} = imm{4-0};
7362 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7363 FPR64, FPR64, vecshiftR64, asm, []> {
7364 let Inst{21-16} = imm{5-0};
7368 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
7369 SDPatternOperator OpNode> {
7370 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7371 FPR64, FPR64, vecshiftR64, asm,
7372 [(set (i64 FPR64:$Rd),
7373 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
7374 let Inst{21-16} = imm{5-0};
7377 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
7378 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
7381 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
7382 SDPatternOperator OpNode = null_frag> {
7383 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7384 FPR64, FPR64, vecshiftR64, asm,
7385 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7386 (i32 vecshiftR64:$imm)))]> {
7387 let Inst{21-16} = imm{5-0};
7390 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7391 (i32 vecshiftR64:$imm))),
7392 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7396 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
7397 SDPatternOperator OpNode> {
7398 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7399 FPR64, FPR64, vecshiftL64, asm,
7400 [(set (v1i64 FPR64:$Rd),
7401 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7402 let Inst{21-16} = imm{5-0};
7406 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7407 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
7408 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7409 FPR64, FPR64, vecshiftL64, asm, []> {
7410 let Inst{21-16} = imm{5-0};
7414 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7415 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
7416 SDPatternOperator OpNode = null_frag> {
7417 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7418 FPR8, FPR16, vecshiftR8, asm, []> {
7419 let Inst{18-16} = imm{2-0};
7422 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7423 FPR16, FPR32, vecshiftR16, asm, []> {
7424 let Inst{19-16} = imm{3-0};
7427 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7428 FPR32, FPR64, vecshiftR32, asm,
7429 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7430 let Inst{20-16} = imm{4-0};
7434 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
7435 SDPatternOperator OpNode> {
7436 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7437 FPR8, FPR8, vecshiftL8, asm, []> {
7438 let Inst{18-16} = imm{2-0};
7441 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7442 FPR16, FPR16, vecshiftL16, asm, []> {
7443 let Inst{19-16} = imm{3-0};
7446 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7447 FPR32, FPR32, vecshiftL32, asm,
7448 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7449 let Inst{20-16} = imm{4-0};
7452 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7453 FPR64, FPR64, vecshiftL64, asm,
7454 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7455 let Inst{21-16} = imm{5-0};
7458 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
7459 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
7462 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
7463 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7464 FPR8, FPR8, vecshiftR8, asm, []> {
7465 let Inst{18-16} = imm{2-0};
7468 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7469 FPR16, FPR16, vecshiftR16, asm, []> {
7470 let Inst{19-16} = imm{3-0};
7473 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7474 FPR32, FPR32, vecshiftR32, asm, []> {
7475 let Inst{20-16} = imm{4-0};
7478 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7479 FPR64, FPR64, vecshiftR64, asm, []> {
7480 let Inst{21-16} = imm{5-0};
7484 //----------------------------------------------------------------------------
7485 // AdvSIMD vector x indexed element
7486 //----------------------------------------------------------------------------
7488 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7489 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7490 RegisterOperand dst_reg, RegisterOperand src_reg,
7492 string asm, string dst_kind, string src_kind,
7494 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7495 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7496 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7503 let Inst{28-23} = 0b011110;
7504 let Inst{22-16} = fixed_imm;
7505 let Inst{15-11} = opc;
7511 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7512 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7513 RegisterOperand vectype1, RegisterOperand vectype2,
7515 string asm, string dst_kind, string src_kind,
7517 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7518 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7519 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7526 let Inst{28-23} = 0b011110;
7527 let Inst{22-16} = fixed_imm;
7528 let Inst{15-11} = opc;
7534 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
7536 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7537 V64, V64, vecshiftR32,
7539 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7541 let Inst{20-16} = imm;
7544 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7545 V128, V128, vecshiftR32,
7547 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7549 let Inst{20-16} = imm;
7552 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7553 V128, V128, vecshiftR64,
7555 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7557 let Inst{21-16} = imm;
7561 multiclass SIMDVectorRShiftSDToFP<bit U, bits<5> opc, string asm,
7563 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7564 V64, V64, vecshiftR32,
7566 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7568 let Inst{20-16} = imm;
7571 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7572 V128, V128, vecshiftR32,
7574 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7576 let Inst{20-16} = imm;
7579 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7580 V128, V128, vecshiftR64,
7582 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7584 let Inst{21-16} = imm;
7588 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
7589 SDPatternOperator OpNode> {
7590 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7591 V64, V128, vecshiftR16Narrow,
7593 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7595 let Inst{18-16} = imm;
7598 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7599 V128, V128, vecshiftR16Narrow,
7600 asm#"2", ".16b", ".8h", []> {
7602 let Inst{18-16} = imm;
7603 let hasSideEffects = 0;
7606 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7607 V64, V128, vecshiftR32Narrow,
7609 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7611 let Inst{19-16} = imm;
7614 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7615 V128, V128, vecshiftR32Narrow,
7616 asm#"2", ".8h", ".4s", []> {
7618 let Inst{19-16} = imm;
7619 let hasSideEffects = 0;
7622 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7623 V64, V128, vecshiftR64Narrow,
7625 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7627 let Inst{20-16} = imm;
7630 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7631 V128, V128, vecshiftR64Narrow,
7632 asm#"2", ".4s", ".2d", []> {
7634 let Inst{20-16} = imm;
7635 let hasSideEffects = 0;
7638 // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions
7639 // themselves, so put them here instead.
7641 // Patterns involving what's effectively an insert high and a normal
7642 // intrinsic, represented by CONCAT_VECTORS.
7643 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7644 vecshiftR16Narrow:$imm)),
7645 (!cast<Instruction>(NAME # "v16i8_shift")
7646 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7647 V128:$Rn, vecshiftR16Narrow:$imm)>;
7648 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7649 vecshiftR32Narrow:$imm)),
7650 (!cast<Instruction>(NAME # "v8i16_shift")
7651 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7652 V128:$Rn, vecshiftR32Narrow:$imm)>;
7653 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7654 vecshiftR64Narrow:$imm)),
7655 (!cast<Instruction>(NAME # "v4i32_shift")
7656 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7657 V128:$Rn, vecshiftR64Narrow:$imm)>;
7660 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
7661 SDPatternOperator OpNode> {
7662 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7663 V64, V64, vecshiftL8,
7665 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7666 (i32 vecshiftL8:$imm)))]> {
7668 let Inst{18-16} = imm;
7671 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7672 V128, V128, vecshiftL8,
7673 asm, ".16b", ".16b",
7674 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7675 (i32 vecshiftL8:$imm)))]> {
7677 let Inst{18-16} = imm;
7680 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7681 V64, V64, vecshiftL16,
7683 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7684 (i32 vecshiftL16:$imm)))]> {
7686 let Inst{19-16} = imm;
7689 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7690 V128, V128, vecshiftL16,
7692 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7693 (i32 vecshiftL16:$imm)))]> {
7695 let Inst{19-16} = imm;
7698 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7699 V64, V64, vecshiftL32,
7701 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7702 (i32 vecshiftL32:$imm)))]> {
7704 let Inst{20-16} = imm;
7707 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7708 V128, V128, vecshiftL32,
7710 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7711 (i32 vecshiftL32:$imm)))]> {
7713 let Inst{20-16} = imm;
7716 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7717 V128, V128, vecshiftL64,
7719 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7720 (i32 vecshiftL64:$imm)))]> {
7722 let Inst{21-16} = imm;
7726 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
7727 SDPatternOperator OpNode> {
7728 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7729 V64, V64, vecshiftR8,
7731 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7732 (i32 vecshiftR8:$imm)))]> {
7734 let Inst{18-16} = imm;
7737 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7738 V128, V128, vecshiftR8,
7739 asm, ".16b", ".16b",
7740 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7741 (i32 vecshiftR8:$imm)))]> {
7743 let Inst{18-16} = imm;
7746 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7747 V64, V64, vecshiftR16,
7749 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7750 (i32 vecshiftR16:$imm)))]> {
7752 let Inst{19-16} = imm;
7755 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7756 V128, V128, vecshiftR16,
7758 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7759 (i32 vecshiftR16:$imm)))]> {
7761 let Inst{19-16} = imm;
7764 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7765 V64, V64, vecshiftR32,
7767 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7768 (i32 vecshiftR32:$imm)))]> {
7770 let Inst{20-16} = imm;
7773 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7774 V128, V128, vecshiftR32,
7776 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7777 (i32 vecshiftR32:$imm)))]> {
7779 let Inst{20-16} = imm;
7782 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7783 V128, V128, vecshiftR64,
7785 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7786 (i32 vecshiftR64:$imm)))]> {
7788 let Inst{21-16} = imm;
7792 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
7793 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
7794 SDPatternOperator OpNode = null_frag> {
7795 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7796 V64, V64, vecshiftR8, asm, ".8b", ".8b",
7797 [(set (v8i8 V64:$dst),
7798 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7799 (i32 vecshiftR8:$imm)))]> {
7801 let Inst{18-16} = imm;
7804 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7805 V128, V128, vecshiftR8, asm, ".16b", ".16b",
7806 [(set (v16i8 V128:$dst),
7807 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7808 (i32 vecshiftR8:$imm)))]> {
7810 let Inst{18-16} = imm;
7813 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7814 V64, V64, vecshiftR16, asm, ".4h", ".4h",
7815 [(set (v4i16 V64:$dst),
7816 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7817 (i32 vecshiftR16:$imm)))]> {
7819 let Inst{19-16} = imm;
7822 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7823 V128, V128, vecshiftR16, asm, ".8h", ".8h",
7824 [(set (v8i16 V128:$dst),
7825 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7826 (i32 vecshiftR16:$imm)))]> {
7828 let Inst{19-16} = imm;
7831 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7832 V64, V64, vecshiftR32, asm, ".2s", ".2s",
7833 [(set (v2i32 V64:$dst),
7834 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7835 (i32 vecshiftR32:$imm)))]> {
7837 let Inst{20-16} = imm;
7840 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7841 V128, V128, vecshiftR32, asm, ".4s", ".4s",
7842 [(set (v4i32 V128:$dst),
7843 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7844 (i32 vecshiftR32:$imm)))]> {
7846 let Inst{20-16} = imm;
7849 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7850 V128, V128, vecshiftR64,
7851 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
7852 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7853 (i32 vecshiftR64:$imm)))]> {
7855 let Inst{21-16} = imm;
7859 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
7860 SDPatternOperator OpNode = null_frag> {
7861 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7862 V64, V64, vecshiftL8,
7864 [(set (v8i8 V64:$dst),
7865 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7866 (i32 vecshiftL8:$imm)))]> {
7868 let Inst{18-16} = imm;
7871 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7872 V128, V128, vecshiftL8,
7873 asm, ".16b", ".16b",
7874 [(set (v16i8 V128:$dst),
7875 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7876 (i32 vecshiftL8:$imm)))]> {
7878 let Inst{18-16} = imm;
7881 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7882 V64, V64, vecshiftL16,
7884 [(set (v4i16 V64:$dst),
7885 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7886 (i32 vecshiftL16:$imm)))]> {
7888 let Inst{19-16} = imm;
7891 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7892 V128, V128, vecshiftL16,
7894 [(set (v8i16 V128:$dst),
7895 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7896 (i32 vecshiftL16:$imm)))]> {
7898 let Inst{19-16} = imm;
7901 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7902 V64, V64, vecshiftL32,
7904 [(set (v2i32 V64:$dst),
7905 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7906 (i32 vecshiftL32:$imm)))]> {
7908 let Inst{20-16} = imm;
7911 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7912 V128, V128, vecshiftL32,
7914 [(set (v4i32 V128:$dst),
7915 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7916 (i32 vecshiftL32:$imm)))]> {
7918 let Inst{20-16} = imm;
7921 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7922 V128, V128, vecshiftL64,
7924 [(set (v2i64 V128:$dst),
7925 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7926 (i32 vecshiftL64:$imm)))]> {
7928 let Inst{21-16} = imm;
7932 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
7933 SDPatternOperator OpNode> {
7934 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7935 V128, V64, vecshiftL8, asm, ".8h", ".8b",
7936 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7938 let Inst{18-16} = imm;
7941 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7942 V128, V128, vecshiftL8,
7943 asm#"2", ".8h", ".16b",
7944 [(set (v8i16 V128:$Rd),
7945 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7947 let Inst{18-16} = imm;
7950 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7951 V128, V64, vecshiftL16, asm, ".4s", ".4h",
7952 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7954 let Inst{19-16} = imm;
7957 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7958 V128, V128, vecshiftL16,
7959 asm#"2", ".4s", ".8h",
7960 [(set (v4i32 V128:$Rd),
7961 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7964 let Inst{19-16} = imm;
7967 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7968 V128, V64, vecshiftL32, asm, ".2d", ".2s",
7969 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7971 let Inst{20-16} = imm;
7974 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7975 V128, V128, vecshiftL32,
7976 asm#"2", ".2d", ".4s",
7977 [(set (v2i64 V128:$Rd),
7978 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7980 let Inst{20-16} = imm;
7986 // Vector load/store
7988 // SIMD ldX/stX no-index memory references don't allow the optional
7989 // ", #0" constant and handle post-indexing explicitly, so we use
7990 // a more specialized parse method for them. Otherwise, it's the same as
7991 // the general GPR64sp handling.
7993 class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
7994 string asm, dag oops, dag iops, list<dag> pattern>
7995 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
8000 let Inst{29-23} = 0b0011000;
8002 let Inst{21-16} = 0b000000;
8003 let Inst{15-12} = opcode;
8004 let Inst{11-10} = size;
8009 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
8010 string asm, dag oops, dag iops>
8011 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
8017 let Inst{29-23} = 0b0011001;
8020 let Inst{20-16} = Xm;
8021 let Inst{15-12} = opcode;
8022 let Inst{11-10} = size;
8027 // The immediate form of AdvSIMD post-indexed addressing is encoded with
8028 // register post-index addressing from the zero register.
8029 multiclass SIMDLdStAliases<string asm, string layout, string Count,
8030 int Offset, int Size> {
8031 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
8032 // "ld1\t$Vt, [$Rn], #16"
8033 // may get mapped to
8034 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
8035 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8036 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
8038 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8041 // E.g. "ld1.8b { v0, v1 }, [x1], #16"
8042 // "ld1.8b\t$Vt, [$Rn], #16"
8043 // may get mapped to
8044 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
8045 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8046 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
8048 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8051 // E.g. "ld1.8b { v0, v1 }, [x1]"
8052 // "ld1\t$Vt, [$Rn]"
8053 // may get mapped to
8054 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
8055 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8056 (!cast<Instruction>(NAME # Count # "v" # layout)
8057 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8060 // E.g. "ld1.8b { v0, v1 }, [x1], x2"
8061 // "ld1\t$Vt, [$Rn], $Xm"
8062 // may get mapped to
8063 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
8064 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8065 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
8067 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8068 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8071 multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
8072 int Offset64, bits<4> opcode> {
8073 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
8074 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
8075 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
8076 (ins GPR64sp:$Rn), []>;
8077 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
8078 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
8079 (ins GPR64sp:$Rn), []>;
8080 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
8081 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
8082 (ins GPR64sp:$Rn), []>;
8083 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
8084 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
8085 (ins GPR64sp:$Rn), []>;
8086 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
8087 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
8088 (ins GPR64sp:$Rn), []>;
8089 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
8090 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
8091 (ins GPR64sp:$Rn), []>;
8092 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
8093 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
8094 (ins GPR64sp:$Rn), []>;
8097 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
8098 (outs GPR64sp:$wback,
8099 !cast<RegisterOperand>(veclist # "16b"):$Vt),
8101 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
8102 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
8103 (outs GPR64sp:$wback,
8104 !cast<RegisterOperand>(veclist # "8h"):$Vt),
8106 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
8107 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
8108 (outs GPR64sp:$wback,
8109 !cast<RegisterOperand>(veclist # "4s"):$Vt),
8111 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
8112 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
8113 (outs GPR64sp:$wback,
8114 !cast<RegisterOperand>(veclist # "2d"):$Vt),
8116 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
8117 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
8118 (outs GPR64sp:$wback,
8119 !cast<RegisterOperand>(veclist # "8b"):$Vt),
8121 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8122 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
8123 (outs GPR64sp:$wback,
8124 !cast<RegisterOperand>(veclist # "4h"):$Vt),
8126 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8127 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
8128 (outs GPR64sp:$wback,
8129 !cast<RegisterOperand>(veclist # "2s"):$Vt),
8131 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8134 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
8135 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
8136 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
8137 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
8138 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
8139 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
8140 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
8143 // Only ld1/st1 has a v1d version.
8144 multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
8145 int Offset64, bits<4> opcode> {
8146 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
8147 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
8148 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
8150 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
8151 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
8153 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
8154 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
8156 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
8157 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
8159 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
8160 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
8162 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
8163 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
8165 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
8166 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
8169 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
8170 (outs GPR64sp:$wback),
8171 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
8173 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
8174 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
8175 (outs GPR64sp:$wback),
8176 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
8178 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
8179 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
8180 (outs GPR64sp:$wback),
8181 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
8183 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
8184 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
8185 (outs GPR64sp:$wback),
8186 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
8188 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
8189 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
8190 (outs GPR64sp:$wback),
8191 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
8193 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8194 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
8195 (outs GPR64sp:$wback),
8196 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
8198 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8199 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
8200 (outs GPR64sp:$wback),
8201 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
8203 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8206 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
8207 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
8208 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
8209 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
8210 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
8211 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
8212 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
8215 multiclass BaseSIMDLd1<string Count, string asm, string veclist,
8216 int Offset128, int Offset64, bits<4> opcode>
8217 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
8219 // LD1 instructions have extra "1d" variants.
8220 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
8221 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
8222 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
8223 (ins GPR64sp:$Rn), []>;
8225 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
8226 (outs GPR64sp:$wback,
8227 !cast<RegisterOperand>(veclist # "1d"):$Vt),
8229 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8232 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
8235 multiclass BaseSIMDSt1<string Count, string asm, string veclist,
8236 int Offset128, int Offset64, bits<4> opcode>
8237 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
8239 // ST1 instructions have extra "1d" variants.
8240 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
8241 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
8242 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
8245 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
8246 (outs GPR64sp:$wback),
8247 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
8249 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8252 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
8255 multiclass SIMDLd1Multiple<string asm> {
8256 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
8257 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
8258 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
8259 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
8262 multiclass SIMDSt1Multiple<string asm> {
8263 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
8264 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
8265 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
8266 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
8269 multiclass SIMDLd2Multiple<string asm> {
8270 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
8273 multiclass SIMDSt2Multiple<string asm> {
8274 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
8277 multiclass SIMDLd3Multiple<string asm> {
8278 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
8281 multiclass SIMDSt3Multiple<string asm> {
8282 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
8285 multiclass SIMDLd4Multiple<string asm> {
8286 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
8289 multiclass SIMDSt4Multiple<string asm> {
8290 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
8294 // AdvSIMD Load/store single-element
8297 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
8298 string asm, string operands, string cst,
8299 dag oops, dag iops, list<dag> pattern>
8300 : I<oops, iops, asm, operands, cst, pattern> {
8304 let Inst{29-24} = 0b001101;
8307 let Inst{15-13} = opcode;
8312 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
8313 string asm, string operands, string cst,
8314 dag oops, dag iops, list<dag> pattern>
8315 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
8319 let Inst{29-24} = 0b001101;
8322 let Inst{15-13} = opcode;
8328 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8329 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
8331 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
8332 (outs listtype:$Vt), (ins GPR64sp:$Rn),
8336 let Inst{20-16} = 0b00000;
8338 let Inst{11-10} = size;
8340 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8341 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
8342 string asm, Operand listtype, Operand GPR64pi>
8343 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
8345 (outs GPR64sp:$wback, listtype:$Vt),
8346 (ins GPR64sp:$Rn, GPR64pi:$Xm), []> {
8350 let Inst{20-16} = Xm;
8352 let Inst{11-10} = size;
8355 multiclass SIMDLdrAliases<string asm, string layout, string Count,
8356 int Offset, int Size> {
8357 // E.g. "ld1r { v0.8b }, [x1], #1"
8358 // "ld1r.8b\t$Vt, [$Rn], #1"
8359 // may get mapped to
8360 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8361 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8362 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8364 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8367 // E.g. "ld1r.8b { v0 }, [x1], #1"
8368 // "ld1r.8b\t$Vt, [$Rn], #1"
8369 // may get mapped to
8370 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8371 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8372 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8374 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8377 // E.g. "ld1r.8b { v0 }, [x1]"
8378 // "ld1r.8b\t$Vt, [$Rn]"
8379 // may get mapped to
8380 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8381 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8382 (!cast<Instruction>(NAME # "v" # layout)
8383 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8386 // E.g. "ld1r.8b { v0 }, [x1], x2"
8387 // "ld1r.8b\t$Vt, [$Rn], $Xm"
8388 // may get mapped to
8389 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8390 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8391 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8393 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8394 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8397 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
8398 int Offset1, int Offset2, int Offset4, int Offset8> {
8399 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
8400 !cast<Operand>("VecList" # Count # "8b")>;
8401 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
8402 !cast<Operand>("VecList" # Count #"16b")>;
8403 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
8404 !cast<Operand>("VecList" # Count #"4h")>;
8405 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
8406 !cast<Operand>("VecList" # Count #"8h")>;
8407 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
8408 !cast<Operand>("VecList" # Count #"2s")>;
8409 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
8410 !cast<Operand>("VecList" # Count #"4s")>;
8411 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
8412 !cast<Operand>("VecList" # Count #"1d")>;
8413 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
8414 !cast<Operand>("VecList" # Count #"2d")>;
8416 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
8417 !cast<Operand>("VecList" # Count # "8b"),
8418 !cast<Operand>("GPR64pi" # Offset1)>;
8419 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
8420 !cast<Operand>("VecList" # Count # "16b"),
8421 !cast<Operand>("GPR64pi" # Offset1)>;
8422 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
8423 !cast<Operand>("VecList" # Count # "4h"),
8424 !cast<Operand>("GPR64pi" # Offset2)>;
8425 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
8426 !cast<Operand>("VecList" # Count # "8h"),
8427 !cast<Operand>("GPR64pi" # Offset2)>;
8428 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
8429 !cast<Operand>("VecList" # Count # "2s"),
8430 !cast<Operand>("GPR64pi" # Offset4)>;
8431 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
8432 !cast<Operand>("VecList" # Count # "4s"),
8433 !cast<Operand>("GPR64pi" # Offset4)>;
8434 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
8435 !cast<Operand>("VecList" # Count # "1d"),
8436 !cast<Operand>("GPR64pi" # Offset8)>;
8437 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
8438 !cast<Operand>("VecList" # Count # "2d"),
8439 !cast<Operand>("GPR64pi" # Offset8)>;
8441 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
8442 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
8443 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
8444 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
8445 defm : SIMDLdrAliases<asm, "2s", Count, Offset4, 64>;
8446 defm : SIMDLdrAliases<asm, "4s", Count, Offset4, 128>;
8447 defm : SIMDLdrAliases<asm, "1d", Count, Offset8, 64>;
8448 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
8451 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
8452 dag oops, dag iops, list<dag> pattern>
8453 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8455 // idx encoded in Q:S:size fields.
8457 let Inst{30} = idx{3};
8459 let Inst{20-16} = 0b00000;
8460 let Inst{12} = idx{2};
8461 let Inst{11-10} = idx{1-0};
8463 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
8464 dag oops, dag iops, list<dag> pattern>
8465 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8466 oops, iops, pattern> {
8467 // idx encoded in Q:S:size fields.
8469 let Inst{30} = idx{3};
8471 let Inst{20-16} = 0b00000;
8472 let Inst{12} = idx{2};
8473 let Inst{11-10} = idx{1-0};
8475 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
8477 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8478 "$Rn = $wback", oops, iops, []> {
8479 // idx encoded in Q:S:size fields.
8482 let Inst{30} = idx{3};
8484 let Inst{20-16} = Xm;
8485 let Inst{12} = idx{2};
8486 let Inst{11-10} = idx{1-0};
8488 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
8490 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8491 "$Rn = $wback", oops, iops, []> {
8492 // idx encoded in Q:S:size fields.
8495 let Inst{30} = idx{3};
8497 let Inst{20-16} = Xm;
8498 let Inst{12} = idx{2};
8499 let Inst{11-10} = idx{1-0};
8502 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
8503 dag oops, dag iops, list<dag> pattern>
8504 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8506 // idx encoded in Q:S:size<1> fields.
8508 let Inst{30} = idx{2};
8510 let Inst{20-16} = 0b00000;
8511 let Inst{12} = idx{1};
8512 let Inst{11} = idx{0};
8513 let Inst{10} = size;
8515 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
8516 dag oops, dag iops, list<dag> pattern>
8517 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8518 oops, iops, pattern> {
8519 // idx encoded in Q:S:size<1> fields.
8521 let Inst{30} = idx{2};
8523 let Inst{20-16} = 0b00000;
8524 let Inst{12} = idx{1};
8525 let Inst{11} = idx{0};
8526 let Inst{10} = size;
8529 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8531 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8532 "$Rn = $wback", oops, iops, []> {
8533 // idx encoded in Q:S:size<1> fields.
8536 let Inst{30} = idx{2};
8538 let Inst{20-16} = Xm;
8539 let Inst{12} = idx{1};
8540 let Inst{11} = idx{0};
8541 let Inst{10} = size;
8543 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8545 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8546 "$Rn = $wback", oops, iops, []> {
8547 // idx encoded in Q:S:size<1> fields.
8550 let Inst{30} = idx{2};
8552 let Inst{20-16} = Xm;
8553 let Inst{12} = idx{1};
8554 let Inst{11} = idx{0};
8555 let Inst{10} = size;
8557 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8558 dag oops, dag iops, list<dag> pattern>
8559 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8561 // idx encoded in Q:S fields.
8563 let Inst{30} = idx{1};
8565 let Inst{20-16} = 0b00000;
8566 let Inst{12} = idx{0};
8567 let Inst{11-10} = size;
8569 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8570 dag oops, dag iops, list<dag> pattern>
8571 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8572 oops, iops, pattern> {
8573 // idx encoded in Q:S fields.
8575 let Inst{30} = idx{1};
8577 let Inst{20-16} = 0b00000;
8578 let Inst{12} = idx{0};
8579 let Inst{11-10} = size;
8581 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
8582 string asm, dag oops, dag iops>
8583 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8584 "$Rn = $wback", oops, iops, []> {
8585 // idx encoded in Q:S fields.
8588 let Inst{30} = idx{1};
8590 let Inst{20-16} = Xm;
8591 let Inst{12} = idx{0};
8592 let Inst{11-10} = size;
8594 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8595 string asm, dag oops, dag iops>
8596 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8597 "$Rn = $wback", oops, iops, []> {
8598 // idx encoded in Q:S fields.
8601 let Inst{30} = idx{1};
8603 let Inst{20-16} = Xm;
8604 let Inst{12} = idx{0};
8605 let Inst{11-10} = size;
8607 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8608 dag oops, dag iops, list<dag> pattern>
8609 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8611 // idx encoded in Q field.
8615 let Inst{20-16} = 0b00000;
8617 let Inst{11-10} = size;
8619 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8620 dag oops, dag iops, list<dag> pattern>
8621 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8622 oops, iops, pattern> {
8623 // idx encoded in Q field.
8627 let Inst{20-16} = 0b00000;
8629 let Inst{11-10} = size;
8631 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
8632 string asm, dag oops, dag iops>
8633 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8634 "$Rn = $wback", oops, iops, []> {
8635 // idx encoded in Q field.
8640 let Inst{20-16} = Xm;
8642 let Inst{11-10} = size;
8644 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8645 string asm, dag oops, dag iops>
8646 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8647 "$Rn = $wback", oops, iops, []> {
8648 // idx encoded in Q field.
8653 let Inst{20-16} = Xm;
8655 let Inst{11-10} = size;
8658 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8659 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
8660 RegisterOperand listtype,
8661 RegisterOperand GPR64pi> {
8662 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
8663 (outs listtype:$dst),
8664 (ins listtype:$Vt, VectorIndexB:$idx,
8667 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
8668 (outs GPR64sp:$wback, listtype:$dst),
8669 (ins listtype:$Vt, VectorIndexB:$idx,
8670 GPR64sp:$Rn, GPR64pi:$Xm)>;
8672 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8673 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
8674 RegisterOperand listtype,
8675 RegisterOperand GPR64pi> {
8676 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
8677 (outs listtype:$dst),
8678 (ins listtype:$Vt, VectorIndexH:$idx,
8681 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
8682 (outs GPR64sp:$wback, listtype:$dst),
8683 (ins listtype:$Vt, VectorIndexH:$idx,
8684 GPR64sp:$Rn, GPR64pi:$Xm)>;
8686 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8687 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
8688 RegisterOperand listtype,
8689 RegisterOperand GPR64pi> {
8690 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
8691 (outs listtype:$dst),
8692 (ins listtype:$Vt, VectorIndexS:$idx,
8695 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
8696 (outs GPR64sp:$wback, listtype:$dst),
8697 (ins listtype:$Vt, VectorIndexS:$idx,
8698 GPR64sp:$Rn, GPR64pi:$Xm)>;
8700 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8701 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
8702 RegisterOperand listtype, RegisterOperand GPR64pi> {
8703 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
8704 (outs listtype:$dst),
8705 (ins listtype:$Vt, VectorIndexD:$idx,
8708 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
8709 (outs GPR64sp:$wback, listtype:$dst),
8710 (ins listtype:$Vt, VectorIndexD:$idx,
8711 GPR64sp:$Rn, GPR64pi:$Xm)>;
8713 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8714 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
8715 RegisterOperand listtype, RegisterOperand GPR64pi> {
8716 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
8717 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
8720 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
8721 (outs GPR64sp:$wback),
8722 (ins listtype:$Vt, VectorIndexB:$idx,
8723 GPR64sp:$Rn, GPR64pi:$Xm)>;
8725 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8726 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
8727 RegisterOperand listtype, RegisterOperand GPR64pi> {
8728 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
8729 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8732 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
8733 (outs GPR64sp:$wback),
8734 (ins listtype:$Vt, VectorIndexH:$idx,
8735 GPR64sp:$Rn, GPR64pi:$Xm)>;
8737 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8738 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
8739 RegisterOperand listtype, RegisterOperand GPR64pi> {
8740 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
8741 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8744 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
8745 (outs GPR64sp:$wback),
8746 (ins listtype:$Vt, VectorIndexS:$idx,
8747 GPR64sp:$Rn, GPR64pi:$Xm)>;
8749 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8750 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
8751 RegisterOperand listtype, RegisterOperand GPR64pi> {
8752 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
8753 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8756 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
8757 (outs GPR64sp:$wback),
8758 (ins listtype:$Vt, VectorIndexD:$idx,
8759 GPR64sp:$Rn, GPR64pi:$Xm)>;
8762 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
8763 string Count, int Offset, Operand idxtype> {
8764 // E.g. "ld1 { v0.8b }[0], [x1], #1"
8765 // "ld1\t$Vt, [$Rn], #1"
8766 // may get mapped to
8767 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8768 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
8769 (!cast<Instruction>(NAME # Type # "_POST")
8771 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8772 idxtype:$idx, XZR), 1>;
8774 // E.g. "ld1.8b { v0 }[0], [x1], #1"
8775 // "ld1.8b\t$Vt, [$Rn], #1"
8776 // may get mapped to
8777 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8778 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
8779 (!cast<Instruction>(NAME # Type # "_POST")
8781 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8782 idxtype:$idx, XZR), 0>;
8784 // E.g. "ld1.8b { v0 }[0], [x1]"
8785 // "ld1.8b\t$Vt, [$Rn]"
8786 // may get mapped to
8787 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8788 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
8789 (!cast<Instruction>(NAME # Type)
8790 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8791 idxtype:$idx, GPR64sp:$Rn), 0>;
8793 // E.g. "ld1.8b { v0 }[0], [x1], x2"
8794 // "ld1.8b\t$Vt, [$Rn], $Xm"
8795 // may get mapped to
8796 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8797 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
8798 (!cast<Instruction>(NAME # Type # "_POST")
8800 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8802 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8805 multiclass SIMDLdSt1SingleAliases<string asm> {
8806 defm : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
8807 defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
8808 defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
8809 defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
8812 multiclass SIMDLdSt2SingleAliases<string asm> {
8813 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
8814 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
8815 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
8816 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
8819 multiclass SIMDLdSt3SingleAliases<string asm> {
8820 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
8821 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
8822 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
8823 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
8826 multiclass SIMDLdSt4SingleAliases<string asm> {
8827 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
8828 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
8829 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
8830 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
8832 } // end of 'let Predicates = [HasNEON]'
8834 //----------------------------------------------------------------------------
8835 // AdvSIMD v8.1 Rounding Double Multiply Add/Subtract
8836 //----------------------------------------------------------------------------
8838 let Predicates = [HasNEON, HasV8_1a] in {
8840 class BaseSIMDThreeSameVectorTiedR0<bit Q, bit U, bits<2> size, bits<5> opcode,
8841 RegisterOperand regtype, string asm,
8842 string kind, list<dag> pattern>
8843 : BaseSIMDThreeSameVectorTied<Q, U, size, opcode, regtype, asm, kind,
8847 multiclass SIMDThreeSameVectorSQRDMLxHTiedHS<bit U, bits<5> opc, string asm,
8848 SDPatternOperator Accum> {
8849 def v4i16 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b01, opc, V64, asm, ".4h",
8850 [(set (v4i16 V64:$dst),
8851 (Accum (v4i16 V64:$Rd),
8852 (v4i16 (int_aarch64_neon_sqrdmulh (v4i16 V64:$Rn),
8853 (v4i16 V64:$Rm)))))]>;
8854 def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
8855 [(set (v8i16 V128:$dst),
8856 (Accum (v8i16 V128:$Rd),
8857 (v8i16 (int_aarch64_neon_sqrdmulh (v8i16 V128:$Rn),
8858 (v8i16 V128:$Rm)))))]>;
8859 def v2i32 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b10, opc, V64, asm, ".2s",
8860 [(set (v2i32 V64:$dst),
8861 (Accum (v2i32 V64:$Rd),
8862 (v2i32 (int_aarch64_neon_sqrdmulh (v2i32 V64:$Rn),
8863 (v2i32 V64:$Rm)))))]>;
8864 def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s",
8865 [(set (v4i32 V128:$dst),
8866 (Accum (v4i32 V128:$Rd),
8867 (v4i32 (int_aarch64_neon_sqrdmulh (v4i32 V128:$Rn),
8868 (v4i32 V128:$Rm)))))]>;
8871 multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
8872 SDPatternOperator Accum> {
8873 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
8874 V64, V64, V128_lo, VectorIndexH,
8875 asm, ".4h", ".4h", ".4h", ".h",
8876 [(set (v4i16 V64:$dst),
8877 (Accum (v4i16 V64:$Rd),
8878 (v4i16 (int_aarch64_neon_sqrdmulh
8880 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
8881 VectorIndexH:$idx))))))]> {
8883 let Inst{11} = idx{2};
8884 let Inst{21} = idx{1};
8885 let Inst{20} = idx{0};
8888 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
8889 V128, V128, V128_lo, VectorIndexH,
8890 asm, ".8h", ".8h", ".8h", ".h",
8891 [(set (v8i16 V128:$dst),
8892 (Accum (v8i16 V128:$Rd),
8893 (v8i16 (int_aarch64_neon_sqrdmulh
8895 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
8896 VectorIndexH:$idx))))))]> {
8898 let Inst{11} = idx{2};
8899 let Inst{21} = idx{1};
8900 let Inst{20} = idx{0};
8903 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
8904 V64, V64, V128, VectorIndexS,
8905 asm, ".2s", ".2s", ".2s", ".s",
8906 [(set (v2i32 V64:$dst),
8907 (Accum (v2i32 V64:$Rd),
8908 (v2i32 (int_aarch64_neon_sqrdmulh
8910 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
8911 VectorIndexS:$idx))))))]> {
8913 let Inst{11} = idx{1};
8914 let Inst{21} = idx{0};
8917 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but
8918 // an intermediate EXTRACT_SUBREG would be untyped.
8919 // FIXME: direct EXTRACT_SUBREG from v2i32 to i32 is illegal, that's why we
8920 // got it lowered here as (i32 vector_extract (v4i32 insert_subvector(..)))
8921 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
8922 (i32 (vector_extract
8923 (v4i32 (insert_subvector
8925 (v2i32 (int_aarch64_neon_sqrdmulh
8927 (v2i32 (AArch64duplane32
8929 VectorIndexS:$idx)))),
8933 (v2i32 (!cast<Instruction>(NAME # v2i32_indexed)
8934 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
8939 VectorIndexS:$idx)),
8942 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
8943 V128, V128, V128, VectorIndexS,
8944 asm, ".4s", ".4s", ".4s", ".s",
8945 [(set (v4i32 V128:$dst),
8946 (Accum (v4i32 V128:$Rd),
8947 (v4i32 (int_aarch64_neon_sqrdmulh
8949 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
8950 VectorIndexS:$idx))))))]> {
8952 let Inst{11} = idx{1};
8953 let Inst{21} = idx{0};
8956 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but
8957 // an intermediate EXTRACT_SUBREG would be untyped.
8958 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
8959 (i32 (vector_extract
8960 (v4i32 (int_aarch64_neon_sqrdmulh
8962 (v4i32 (AArch64duplane32
8964 VectorIndexS:$idx)))),
8967 (v4i32 (!cast<Instruction>(NAME # v4i32_indexed)
8968 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
8973 VectorIndexS:$idx)),
8976 def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
8977 FPR16Op, FPR16Op, V128_lo,
8978 VectorIndexH, asm, ".h", "", "", ".h",
8981 let Inst{11} = idx{2};
8982 let Inst{21} = idx{1};
8983 let Inst{20} = idx{0};
8986 def i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
8987 FPR32Op, FPR32Op, V128, VectorIndexS,
8988 asm, ".s", "", "", ".s",
8989 [(set (i32 FPR32Op:$dst),
8990 (Accum (i32 FPR32Op:$Rd),
8991 (i32 (int_aarch64_neon_sqrdmulh
8993 (i32 (vector_extract (v4i32 V128:$Rm),
8994 VectorIndexS:$idx))))))]> {
8996 let Inst{11} = idx{1};
8997 let Inst{21} = idx{0};
9000 } // let Predicates = [HasNeon, HasV8_1a]
9002 //----------------------------------------------------------------------------
9003 // Crypto extensions
9004 //----------------------------------------------------------------------------
9006 let Predicates = [HasCrypto] in {
9007 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
9008 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
9010 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
9014 let Inst{31-16} = 0b0100111000101000;
9015 let Inst{15-12} = opc;
9016 let Inst{11-10} = 0b10;
9021 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
9022 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
9023 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
9025 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
9026 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
9028 [(set (v16i8 V128:$dst),
9029 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
9031 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
9032 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
9033 dag oops, dag iops, list<dag> pat>
9034 : I<oops, iops, asm,
9035 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
9036 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
9041 let Inst{31-21} = 0b01011110000;
9042 let Inst{20-16} = Rm;
9044 let Inst{14-12} = opc;
9045 let Inst{11-10} = 0b00;
9050 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
9051 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
9052 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
9053 [(set (v4i32 FPR128:$dst),
9054 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
9055 (v4i32 V128:$Rm)))]>;
9057 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
9058 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
9059 (ins V128:$Rd, V128:$Rn, V128:$Rm),
9060 [(set (v4i32 V128:$dst),
9061 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
9062 (v4i32 V128:$Rm)))]>;
9064 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
9065 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
9066 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
9067 [(set (v4i32 FPR128:$dst),
9068 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
9069 (v4i32 V128:$Rm)))]>;
9071 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
9072 class SHA2OpInst<bits<4> opc, string asm, string kind,
9073 string cstr, dag oops, dag iops,
9075 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
9076 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
9080 let Inst{31-16} = 0b0101111000101000;
9081 let Inst{15-12} = opc;
9082 let Inst{11-10} = 0b10;
9087 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
9088 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
9089 (ins V128:$Rd, V128:$Rn),
9090 [(set (v4i32 V128:$dst),
9091 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
9093 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
9094 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
9095 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
9096 } // end of 'let Predicates = [HasCrypto]'
9098 //----------------------------------------------------------------------------
9099 // v8.1 atomic instructions extension:
9103 // * LDOPregister<OP>, and aliases STOPregister<OP>
9105 // Instruction encodings:
9107 // 31 30|29 24|23|22|21|20 16|15|14 10|9 5|4 0
9108 // CAS SZ |001000|1 |A |1 |Rs |R |11111 |Rn |Rt
9109 // CASP 0|SZ|001000|0 |A |1 |Rs |R |11111 |Rn |Rt
9110 // SWP SZ |111000|A |R |1 |Rs |1 |OPC|00|Rn |Rt
9111 // LD SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |Rt
9112 // ST SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |11111
9114 // Instruction syntax:
9116 // CAS{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
9117 // CAS{<order>} <Xs>, <Xt>, [<Xn|SP>]
9118 // CASP{<order>} <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>]
9119 // CASP{<order>} <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
9120 // SWP{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
9121 // SWP{<order>} <Xs>, <Xt>, [<Xn|SP>]
9122 // LD<OP>{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
9123 // LD<OP>{<order>} <Xs>, <Xt>, [<Xn|SP>]
9124 // ST<OP>{<order>}[<size>] <Ws>, [<Xn|SP>]
9125 // ST<OP>{<order>} <Xs>, [<Xn|SP>]
9127 let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
9128 class BaseCASEncoding<dag oops, dag iops, string asm, string operands,
9129 string cstr, list<dag> pattern>
9130 : I<oops, iops, asm, operands, cstr, pattern> {
9138 let Inst{31-30} = Sz;
9139 let Inst{29-24} = 0b001000;
9143 let Inst{20-16} = Rs;
9145 let Inst{14-10} = 0b11111;
9150 class BaseCAS<string order, string size, RegisterClass RC>
9151 : BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn),
9152 "cas" # order # size, "\t$Rs, $Rt, [$Rn]",
9157 multiclass CompareAndSwap<bits<1> Acq, bits<1> Rel, string order> {
9158 let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseCAS<order, "b", GPR32>;
9159 let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseCAS<order, "h", GPR32>;
9160 let Sz = 0b10, Acq = Acq, Rel = Rel in def s : BaseCAS<order, "", GPR32>;
9161 let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseCAS<order, "", GPR64>;
9164 class BaseCASP<string order, string size, RegisterOperand RC>
9165 : BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn),
9166 "casp" # order # size, "\t$Rs, $Rt, [$Rn]",
9171 multiclass CompareAndSwapPair<bits<1> Acq, bits<1> Rel, string order> {
9172 let Sz = 0b00, Acq = Acq, Rel = Rel in
9173 def s : BaseCASP<order, "", WSeqPairClassOperand>;
9174 let Sz = 0b01, Acq = Acq, Rel = Rel in
9175 def d : BaseCASP<order, "", XSeqPairClassOperand>;
9178 let Predicates = [HasV8_1a] in
9179 class BaseSWP<string order, string size, RegisterClass RC>
9180 : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "swp" # order # size,
9181 "\t$Rs, $Rt, [$Rn]","",[]> {
9186 bits<3> opc = 0b000;
9189 let Inst{31-30} = Sz;
9190 let Inst{29-24} = 0b111000;
9194 let Inst{20-16} = Rs;
9196 let Inst{14-12} = opc;
9197 let Inst{11-10} = 0b00;
9202 multiclass Swap<bits<1> Acq, bits<1> Rel, string order> {
9203 let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseSWP<order, "b", GPR32>;
9204 let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseSWP<order, "h", GPR32>;
9205 let Sz = 0b10, Acq = Acq, Rel = Rel in def s : BaseSWP<order, "", GPR32>;
9206 let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseSWP<order, "", GPR64>;
9209 let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
9210 class BaseLDOPregister<string op, string order, string size, RegisterClass RC>
9211 : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "ld" # op # order # size,
9212 "\t$Rs, $Rt, [$Rn]","",[]> {
9220 let Inst{31-30} = Sz;
9221 let Inst{29-24} = 0b111000;
9225 let Inst{20-16} = Rs;
9227 let Inst{14-12} = opc;
9228 let Inst{11-10} = 0b00;
9233 multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel,
9235 let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in
9236 def b : BaseLDOPregister<op, order, "b", GPR32>;
9237 let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in
9238 def h : BaseLDOPregister<op, order, "h", GPR32>;
9239 let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in
9240 def s : BaseLDOPregister<op, order, "", GPR32>;
9241 let Sz = 0b11, Acq = Acq, Rel = Rel, opc = opc in
9242 def d : BaseLDOPregister<op, order, "", GPR64>;
9245 let Predicates = [HasV8_1a] in
9246 class BaseSTOPregister<string asm, RegisterClass OP, Register Reg,
9248 InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn)>;
9250 multiclass STOPregister<string asm, string instr> {
9251 def : BaseSTOPregister<asm # "lb", GPR32, WZR,
9252 !cast<Instruction>(instr # "Lb")>;
9253 def : BaseSTOPregister<asm # "lh", GPR32, WZR,
9254 !cast<Instruction>(instr # "Lh")>;
9255 def : BaseSTOPregister<asm # "l", GPR32, WZR,
9256 !cast<Instruction>(instr # "Ls")>;
9257 def : BaseSTOPregister<asm # "l", GPR64, XZR,
9258 !cast<Instruction>(instr # "Ld")>;
9259 def : BaseSTOPregister<asm # "b", GPR32, WZR,
9260 !cast<Instruction>(instr # "b")>;
9261 def : BaseSTOPregister<asm # "h", GPR32, WZR,
9262 !cast<Instruction>(instr # "h")>;
9263 def : BaseSTOPregister<asm, GPR32, WZR,
9264 !cast<Instruction>(instr # "s")>;
9265 def : BaseSTOPregister<asm, GPR64, XZR,
9266 !cast<Instruction>(instr # "d")>;
9269 //----------------------------------------------------------------------------
9270 // Allow the size specifier tokens to be upper case, not just lower.
9271 def : TokenAlias<".8B", ".8b">;
9272 def : TokenAlias<".4H", ".4h">;
9273 def : TokenAlias<".2S", ".2s">;
9274 def : TokenAlias<".1D", ".1d">;
9275 def : TokenAlias<".16B", ".16b">;
9276 def : TokenAlias<".8H", ".8h">;
9277 def : TokenAlias<".4S", ".4s">;
9278 def : TokenAlias<".2D", ".2d">;
9279 def : TokenAlias<".1Q", ".1q">;
9280 def : TokenAlias<".B", ".b">;
9281 def : TokenAlias<".H", ".h">;
9282 def : TokenAlias<".S", ".s">;
9283 def : TokenAlias<".D", ".d">;
9284 def : TokenAlias<".Q", ".q">;