1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe AArch64 instructions format here
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<2> val> {
21 def PseudoFrm : Format<0>;
22 def NormalFrm : Format<1>; // Do we need any others?
24 // AArch64 Instruction Format
25 class AArch64Inst<Format f, string cstr> : Instruction {
26 field bits<32> Inst; // Instruction encoding.
27 // Mask of bits that cause an encoding to be UNPREDICTABLE.
28 // If a bit is set, then if the corresponding bit in the
29 // target encoding differs from its value in the "Inst" field,
30 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
31 field bits<32> Unpredictable = 0;
32 // SoftFail is the generic name for this field, but we alias it so
33 // as to make it more obvious what it means in ARM-land.
34 field bits<32> SoftFail = Unpredictable;
35 let Namespace = "AArch64";
37 bits<2> Form = F.Value;
39 let Constraints = cstr;
42 // Pseudo instructions (don't have encoding information)
43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
44 : AArch64Inst<PseudoFrm, cstr> {
45 dag OutOperandList = oops;
46 dag InOperandList = iops;
47 let Pattern = pattern;
48 let isCodeGenOnly = 1;
51 // Real instructions (have encoding information)
52 class EncodedI<string cstr, list<dag> pattern> : AArch64Inst<NormalFrm, cstr> {
53 let Pattern = pattern;
57 // Normal instructions
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
60 : EncodedI<cstr, pattern> {
61 dag OutOperandList = oops;
62 dag InOperandList = iops;
63 let AsmString = !strconcat(asm, operands);
66 class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
67 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
68 class UnOpFrag<dag res> : PatFrag<(ops node:$LHS), res>;
70 // Helper fragment for an extract of the high portion of a 128-bit vector.
71 def extract_high_v16i8 :
72 UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
73 def extract_high_v8i16 :
74 UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
75 def extract_high_v4i32 :
76 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
77 def extract_high_v2i64 :
78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
80 //===----------------------------------------------------------------------===//
81 // Asm Operand Classes.
84 // Shifter operand for arithmetic shifted encodings.
85 def ShifterOperand : AsmOperandClass {
89 // Shifter operand for mov immediate encodings.
90 def MovImm32ShifterOperand : AsmOperandClass {
91 let SuperClasses = [ShifterOperand];
92 let Name = "MovImm32Shifter";
93 let RenderMethod = "addShifterOperands";
94 let DiagnosticType = "InvalidMovImm32Shift";
96 def MovImm64ShifterOperand : AsmOperandClass {
97 let SuperClasses = [ShifterOperand];
98 let Name = "MovImm64Shifter";
99 let RenderMethod = "addShifterOperands";
100 let DiagnosticType = "InvalidMovImm64Shift";
103 // Shifter operand for arithmetic register shifted encodings.
104 class ArithmeticShifterOperand<int width> : AsmOperandClass {
105 let SuperClasses = [ShifterOperand];
106 let Name = "ArithmeticShifter" # width;
107 let PredicateMethod = "isArithmeticShifter<" # width # ">";
108 let RenderMethod = "addShifterOperands";
109 let DiagnosticType = "AddSubRegShift" # width;
112 def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>;
113 def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>;
115 // Shifter operand for logical register shifted encodings.
116 class LogicalShifterOperand<int width> : AsmOperandClass {
117 let SuperClasses = [ShifterOperand];
118 let Name = "LogicalShifter" # width;
119 let PredicateMethod = "isLogicalShifter<" # width # ">";
120 let RenderMethod = "addShifterOperands";
121 let DiagnosticType = "AddSubRegShift" # width;
124 def LogicalShifterOperand32 : LogicalShifterOperand<32>;
125 def LogicalShifterOperand64 : LogicalShifterOperand<64>;
127 // Shifter operand for logical vector 128/64-bit shifted encodings.
128 def LogicalVecShifterOperand : AsmOperandClass {
129 let SuperClasses = [ShifterOperand];
130 let Name = "LogicalVecShifter";
131 let RenderMethod = "addShifterOperands";
133 def LogicalVecHalfWordShifterOperand : AsmOperandClass {
134 let SuperClasses = [LogicalVecShifterOperand];
135 let Name = "LogicalVecHalfWordShifter";
136 let RenderMethod = "addShifterOperands";
139 // The "MSL" shifter on the vector MOVI instruction.
140 def MoveVecShifterOperand : AsmOperandClass {
141 let SuperClasses = [ShifterOperand];
142 let Name = "MoveVecShifter";
143 let RenderMethod = "addShifterOperands";
146 // Extend operand for arithmetic encodings.
147 def ExtendOperand : AsmOperandClass {
149 let DiagnosticType = "AddSubRegExtendLarge";
151 def ExtendOperand64 : AsmOperandClass {
152 let SuperClasses = [ExtendOperand];
153 let Name = "Extend64";
154 let DiagnosticType = "AddSubRegExtendSmall";
156 // 'extend' that's a lsl of a 64-bit register.
157 def ExtendOperandLSL64 : AsmOperandClass {
158 let SuperClasses = [ExtendOperand];
159 let Name = "ExtendLSL64";
160 let RenderMethod = "addExtend64Operands";
161 let DiagnosticType = "AddSubRegExtendLarge";
164 // 8-bit floating-point immediate encodings.
165 def FPImmOperand : AsmOperandClass {
167 let ParserMethod = "tryParseFPImm";
168 let DiagnosticType = "InvalidFPImm";
171 def CondCode : AsmOperandClass {
172 let Name = "CondCode";
173 let DiagnosticType = "InvalidCondCode";
176 // A 32-bit register pasrsed as 64-bit
177 def GPR32as64Operand : AsmOperandClass {
178 let Name = "GPR32as64";
180 def GPR32as64 : RegisterOperand<GPR32> {
181 let ParserMatchClass = GPR32as64Operand;
184 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
185 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
186 // are encoded as the eight bit value 'abcdefgh'.
187 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
190 //===----------------------------------------------------------------------===//
191 // Operand Definitions.
194 // ADR[P] instruction labels.
195 def AdrpOperand : AsmOperandClass {
196 let Name = "AdrpLabel";
197 let ParserMethod = "tryParseAdrpLabel";
198 let DiagnosticType = "InvalidLabel";
200 def adrplabel : Operand<i64> {
201 let EncoderMethod = "getAdrLabelOpValue";
202 let PrintMethod = "printAdrpLabel";
203 let ParserMatchClass = AdrpOperand;
206 def AdrOperand : AsmOperandClass {
207 let Name = "AdrLabel";
208 let ParserMethod = "tryParseAdrLabel";
209 let DiagnosticType = "InvalidLabel";
211 def adrlabel : Operand<i64> {
212 let EncoderMethod = "getAdrLabelOpValue";
213 let ParserMatchClass = AdrOperand;
216 // simm9 predicate - True if the immediate is in the range [-256, 255].
217 def SImm9Operand : AsmOperandClass {
219 let DiagnosticType = "InvalidMemoryIndexedSImm9";
221 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
222 let ParserMatchClass = SImm9Operand;
225 // simm7sN predicate - True if the immediate is a multiple of N in the range
226 // [-64 * N, 63 * N].
227 class SImm7Scaled<int Scale> : AsmOperandClass {
228 let Name = "SImm7s" # Scale;
229 let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm7";
232 def SImm7s4Operand : SImm7Scaled<4>;
233 def SImm7s8Operand : SImm7Scaled<8>;
234 def SImm7s16Operand : SImm7Scaled<16>;
236 def simm7s4 : Operand<i32> {
237 let ParserMatchClass = SImm7s4Operand;
238 let PrintMethod = "printImmScale<4>";
241 def simm7s8 : Operand<i32> {
242 let ParserMatchClass = SImm7s8Operand;
243 let PrintMethod = "printImmScale<8>";
246 def simm7s16 : Operand<i32> {
247 let ParserMatchClass = SImm7s16Operand;
248 let PrintMethod = "printImmScale<16>";
251 def am_indexed7s8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S8", []>;
252 def am_indexed7s16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S16", []>;
253 def am_indexed7s32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S32", []>;
254 def am_indexed7s64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S64", []>;
255 def am_indexed7s128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S128", []>;
257 class AsmImmRange<int Low, int High> : AsmOperandClass {
258 let Name = "Imm" # Low # "_" # High;
259 let DiagnosticType = "InvalidImm" # Low # "_" # High;
262 def Imm1_8Operand : AsmImmRange<1, 8>;
263 def Imm1_16Operand : AsmImmRange<1, 16>;
264 def Imm1_32Operand : AsmImmRange<1, 32>;
265 def Imm1_64Operand : AsmImmRange<1, 64>;
267 def MovZSymbolG3AsmOperand : AsmOperandClass {
268 let Name = "MovZSymbolG3";
269 let RenderMethod = "addImmOperands";
272 def movz_symbol_g3 : Operand<i32> {
273 let ParserMatchClass = MovZSymbolG3AsmOperand;
276 def MovZSymbolG2AsmOperand : AsmOperandClass {
277 let Name = "MovZSymbolG2";
278 let RenderMethod = "addImmOperands";
281 def movz_symbol_g2 : Operand<i32> {
282 let ParserMatchClass = MovZSymbolG2AsmOperand;
285 def MovZSymbolG1AsmOperand : AsmOperandClass {
286 let Name = "MovZSymbolG1";
287 let RenderMethod = "addImmOperands";
290 def movz_symbol_g1 : Operand<i32> {
291 let ParserMatchClass = MovZSymbolG1AsmOperand;
294 def MovZSymbolG0AsmOperand : AsmOperandClass {
295 let Name = "MovZSymbolG0";
296 let RenderMethod = "addImmOperands";
299 def movz_symbol_g0 : Operand<i32> {
300 let ParserMatchClass = MovZSymbolG0AsmOperand;
303 def MovKSymbolG3AsmOperand : AsmOperandClass {
304 let Name = "MovKSymbolG3";
305 let RenderMethod = "addImmOperands";
308 def movk_symbol_g3 : Operand<i32> {
309 let ParserMatchClass = MovKSymbolG3AsmOperand;
312 def MovKSymbolG2AsmOperand : AsmOperandClass {
313 let Name = "MovKSymbolG2";
314 let RenderMethod = "addImmOperands";
317 def movk_symbol_g2 : Operand<i32> {
318 let ParserMatchClass = MovKSymbolG2AsmOperand;
321 def MovKSymbolG1AsmOperand : AsmOperandClass {
322 let Name = "MovKSymbolG1";
323 let RenderMethod = "addImmOperands";
326 def movk_symbol_g1 : Operand<i32> {
327 let ParserMatchClass = MovKSymbolG1AsmOperand;
330 def MovKSymbolG0AsmOperand : AsmOperandClass {
331 let Name = "MovKSymbolG0";
332 let RenderMethod = "addImmOperands";
335 def movk_symbol_g0 : Operand<i32> {
336 let ParserMatchClass = MovKSymbolG0AsmOperand;
339 class fixedpoint_i32<ValueType FloatVT>
341 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
342 let EncoderMethod = "getFixedPointScaleOpValue";
343 let DecoderMethod = "DecodeFixedPointScaleImm32";
344 let ParserMatchClass = Imm1_32Operand;
347 class fixedpoint_i64<ValueType FloatVT>
349 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
350 let EncoderMethod = "getFixedPointScaleOpValue";
351 let DecoderMethod = "DecodeFixedPointScaleImm64";
352 let ParserMatchClass = Imm1_64Operand;
355 def fixedpoint_f32_i32 : fixedpoint_i32<f32>;
356 def fixedpoint_f64_i32 : fixedpoint_i32<f64>;
358 def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
359 def fixedpoint_f64_i64 : fixedpoint_i64<f64>;
361 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
362 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
364 let EncoderMethod = "getVecShiftR8OpValue";
365 let DecoderMethod = "DecodeVecShiftR8Imm";
366 let ParserMatchClass = Imm1_8Operand;
368 def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
369 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
371 let EncoderMethod = "getVecShiftR16OpValue";
372 let DecoderMethod = "DecodeVecShiftR16Imm";
373 let ParserMatchClass = Imm1_16Operand;
375 def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
376 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
378 let EncoderMethod = "getVecShiftR16OpValue";
379 let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
380 let ParserMatchClass = Imm1_8Operand;
382 def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
383 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
385 let EncoderMethod = "getVecShiftR32OpValue";
386 let DecoderMethod = "DecodeVecShiftR32Imm";
387 let ParserMatchClass = Imm1_32Operand;
389 def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
390 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
392 let EncoderMethod = "getVecShiftR32OpValue";
393 let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
394 let ParserMatchClass = Imm1_16Operand;
396 def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
397 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
399 let EncoderMethod = "getVecShiftR64OpValue";
400 let DecoderMethod = "DecodeVecShiftR64Imm";
401 let ParserMatchClass = Imm1_64Operand;
403 def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
404 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
406 let EncoderMethod = "getVecShiftR64OpValue";
407 let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
408 let ParserMatchClass = Imm1_32Operand;
411 def Imm0_7Operand : AsmImmRange<0, 7>;
412 def Imm0_15Operand : AsmImmRange<0, 15>;
413 def Imm0_31Operand : AsmImmRange<0, 31>;
414 def Imm0_63Operand : AsmImmRange<0, 63>;
416 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
417 return (((uint32_t)Imm) < 8);
419 let EncoderMethod = "getVecShiftL8OpValue";
420 let DecoderMethod = "DecodeVecShiftL8Imm";
421 let ParserMatchClass = Imm0_7Operand;
423 def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
424 return (((uint32_t)Imm) < 16);
426 let EncoderMethod = "getVecShiftL16OpValue";
427 let DecoderMethod = "DecodeVecShiftL16Imm";
428 let ParserMatchClass = Imm0_15Operand;
430 def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
431 return (((uint32_t)Imm) < 32);
433 let EncoderMethod = "getVecShiftL32OpValue";
434 let DecoderMethod = "DecodeVecShiftL32Imm";
435 let ParserMatchClass = Imm0_31Operand;
437 def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
438 return (((uint32_t)Imm) < 64);
440 let EncoderMethod = "getVecShiftL64OpValue";
441 let DecoderMethod = "DecodeVecShiftL64Imm";
442 let ParserMatchClass = Imm0_63Operand;
446 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
447 // instructions for splatting repeating bit patterns across the immediate.
448 def logical_imm32_XFORM : SDNodeXForm<imm, [{
449 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
450 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
452 def logical_imm64_XFORM : SDNodeXForm<imm, [{
453 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
454 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
457 let DiagnosticType = "LogicalSecondSource" in {
458 def LogicalImm32Operand : AsmOperandClass {
459 let Name = "LogicalImm32";
461 def LogicalImm64Operand : AsmOperandClass {
462 let Name = "LogicalImm64";
464 def LogicalImm32NotOperand : AsmOperandClass {
465 let Name = "LogicalImm32Not";
467 def LogicalImm64NotOperand : AsmOperandClass {
468 let Name = "LogicalImm64Not";
471 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
472 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 32);
473 }], logical_imm32_XFORM> {
474 let PrintMethod = "printLogicalImm32";
475 let ParserMatchClass = LogicalImm32Operand;
477 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
478 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 64);
479 }], logical_imm64_XFORM> {
480 let PrintMethod = "printLogicalImm64";
481 let ParserMatchClass = LogicalImm64Operand;
483 def logical_imm32_not : Operand<i32> {
484 let ParserMatchClass = LogicalImm32NotOperand;
486 def logical_imm64_not : Operand<i64> {
487 let ParserMatchClass = LogicalImm64NotOperand;
490 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
491 def Imm0_65535Operand : AsmImmRange<0, 65535>;
492 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
493 return ((uint32_t)Imm) < 65536;
495 let ParserMatchClass = Imm0_65535Operand;
496 let PrintMethod = "printHexImm";
499 // imm0_255 predicate - True if the immediate is in the range [0,255].
500 def Imm0_255Operand : AsmOperandClass { let Name = "Imm0_255"; }
501 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
502 return ((uint32_t)Imm) < 256;
504 let ParserMatchClass = Imm0_255Operand;
505 let PrintMethod = "printHexImm";
508 // imm0_127 predicate - True if the immediate is in the range [0,127]
509 def Imm0_127Operand : AsmImmRange<0, 127>;
510 def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
511 return ((uint32_t)Imm) < 128;
513 let ParserMatchClass = Imm0_127Operand;
514 let PrintMethod = "printHexImm";
517 // NOTE: These imm0_N operands have to be of type i64 because i64 is the size
518 // for all shift-amounts.
520 // imm0_63 predicate - True if the immediate is in the range [0,63]
521 def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
522 return ((uint64_t)Imm) < 64;
524 let ParserMatchClass = Imm0_63Operand;
527 // imm0_31 predicate - True if the immediate is in the range [0,31]
528 def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
529 return ((uint64_t)Imm) < 32;
531 let ParserMatchClass = Imm0_31Operand;
534 // True if the 32-bit immediate is in the range [0,31]
535 def imm32_0_31 : Operand<i32>, ImmLeaf<i32, [{
536 return ((uint64_t)Imm) < 32;
538 let ParserMatchClass = Imm0_31Operand;
541 // imm0_15 predicate - True if the immediate is in the range [0,15]
542 def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
543 return ((uint64_t)Imm) < 16;
545 let ParserMatchClass = Imm0_15Operand;
548 // imm0_7 predicate - True if the immediate is in the range [0,7]
549 def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
550 return ((uint64_t)Imm) < 8;
552 let ParserMatchClass = Imm0_7Operand;
555 // imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15]
556 def imm32_0_15 : Operand<i32>, ImmLeaf<i32, [{
557 return ((uint32_t)Imm) < 16;
559 let ParserMatchClass = Imm0_15Operand;
562 // An arithmetic shifter operand:
563 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
565 class arith_shift<ValueType Ty, int width> : Operand<Ty> {
566 let PrintMethod = "printShifter";
567 let ParserMatchClass = !cast<AsmOperandClass>(
568 "ArithmeticShifterOperand" # width);
571 def arith_shift32 : arith_shift<i32, 32>;
572 def arith_shift64 : arith_shift<i64, 64>;
574 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
576 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
577 let PrintMethod = "printShiftedRegister";
578 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
581 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
582 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
584 // An arithmetic shifter operand:
585 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
587 class logical_shift<int width> : Operand<i32> {
588 let PrintMethod = "printShifter";
589 let ParserMatchClass = !cast<AsmOperandClass>(
590 "LogicalShifterOperand" # width);
593 def logical_shift32 : logical_shift<32>;
594 def logical_shift64 : logical_shift<64>;
596 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
598 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
599 let PrintMethod = "printShiftedRegister";
600 let MIOperandInfo = (ops regclass, shiftop);
603 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
604 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
606 // A logical vector shifter operand:
607 // {7-6} - shift type: 00 = lsl
608 // {5-0} - imm6: #0, #8, #16, or #24
609 def logical_vec_shift : Operand<i32> {
610 let PrintMethod = "printShifter";
611 let EncoderMethod = "getVecShifterOpValue";
612 let ParserMatchClass = LogicalVecShifterOperand;
615 // A logical vector half-word shifter operand:
616 // {7-6} - shift type: 00 = lsl
617 // {5-0} - imm6: #0 or #8
618 def logical_vec_hw_shift : Operand<i32> {
619 let PrintMethod = "printShifter";
620 let EncoderMethod = "getVecShifterOpValue";
621 let ParserMatchClass = LogicalVecHalfWordShifterOperand;
624 // A vector move shifter operand:
625 // {0} - imm1: #8 or #16
626 def move_vec_shift : Operand<i32> {
627 let PrintMethod = "printShifter";
628 let EncoderMethod = "getMoveVecShifterOpValue";
629 let ParserMatchClass = MoveVecShifterOperand;
632 let DiagnosticType = "AddSubSecondSource" in {
633 def AddSubImmOperand : AsmOperandClass {
634 let Name = "AddSubImm";
635 let ParserMethod = "tryParseAddSubImm";
637 def AddSubImmNegOperand : AsmOperandClass {
638 let Name = "AddSubImmNeg";
639 let ParserMethod = "tryParseAddSubImm";
642 // An ADD/SUB immediate shifter operand:
644 // {7-6} - shift type: 00 = lsl
645 // {5-0} - imm6: #0 or #12
646 class addsub_shifted_imm<ValueType Ty>
647 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
648 let PrintMethod = "printAddSubImm";
649 let EncoderMethod = "getAddSubImmOpValue";
650 let ParserMatchClass = AddSubImmOperand;
651 let MIOperandInfo = (ops i32imm, i32imm);
654 class addsub_shifted_imm_neg<ValueType Ty>
656 let EncoderMethod = "getAddSubImmOpValue";
657 let ParserMatchClass = AddSubImmNegOperand;
658 let MIOperandInfo = (ops i32imm, i32imm);
661 def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
662 def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
663 def addsub_shifted_imm32_neg : addsub_shifted_imm_neg<i32>;
664 def addsub_shifted_imm64_neg : addsub_shifted_imm_neg<i64>;
666 class neg_addsub_shifted_imm<ValueType Ty>
667 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
668 let PrintMethod = "printAddSubImm";
669 let EncoderMethod = "getAddSubImmOpValue";
670 let ParserMatchClass = AddSubImmOperand;
671 let MIOperandInfo = (ops i32imm, i32imm);
674 def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
675 def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;
677 // An extend operand:
678 // {5-3} - extend type
680 def arith_extend : Operand<i32> {
681 let PrintMethod = "printArithExtend";
682 let ParserMatchClass = ExtendOperand;
684 def arith_extend64 : Operand<i32> {
685 let PrintMethod = "printArithExtend";
686 let ParserMatchClass = ExtendOperand64;
689 // 'extend' that's a lsl of a 64-bit register.
690 def arith_extendlsl64 : Operand<i32> {
691 let PrintMethod = "printArithExtend";
692 let ParserMatchClass = ExtendOperandLSL64;
695 class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
696 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
697 let PrintMethod = "printExtendedRegister";
698 let MIOperandInfo = (ops GPR32, arith_extend);
701 class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
702 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
703 let PrintMethod = "printExtendedRegister";
704 let MIOperandInfo = (ops GPR32, arith_extend64);
707 // Floating-point immediate.
708 def fpimm32 : Operand<f32>,
709 PatLeaf<(f32 fpimm), [{
710 return AArch64_AM::getFP32Imm(N->getValueAPF()) != -1;
711 }], SDNodeXForm<fpimm, [{
712 APFloat InVal = N->getValueAPF();
713 uint32_t enc = AArch64_AM::getFP32Imm(InVal);
714 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
716 let ParserMatchClass = FPImmOperand;
717 let PrintMethod = "printFPImmOperand";
719 def fpimm64 : Operand<f64>,
720 PatLeaf<(f64 fpimm), [{
721 return AArch64_AM::getFP64Imm(N->getValueAPF()) != -1;
722 }], SDNodeXForm<fpimm, [{
723 APFloat InVal = N->getValueAPF();
724 uint32_t enc = AArch64_AM::getFP64Imm(InVal);
725 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
727 let ParserMatchClass = FPImmOperand;
728 let PrintMethod = "printFPImmOperand";
731 def fpimm8 : Operand<i32> {
732 let ParserMatchClass = FPImmOperand;
733 let PrintMethod = "printFPImmOperand";
736 def fpimm0 : PatLeaf<(fpimm), [{
737 return N->isExactlyValue(+0.0);
740 // Vector lane operands
741 class AsmVectorIndex<string Suffix> : AsmOperandClass {
742 let Name = "VectorIndex" # Suffix;
743 let DiagnosticType = "InvalidIndex" # Suffix;
745 def VectorIndex1Operand : AsmVectorIndex<"1">;
746 def VectorIndexBOperand : AsmVectorIndex<"B">;
747 def VectorIndexHOperand : AsmVectorIndex<"H">;
748 def VectorIndexSOperand : AsmVectorIndex<"S">;
749 def VectorIndexDOperand : AsmVectorIndex<"D">;
751 def VectorIndex1 : Operand<i64>, ImmLeaf<i64, [{
752 return ((uint64_t)Imm) == 1;
754 let ParserMatchClass = VectorIndex1Operand;
755 let PrintMethod = "printVectorIndex";
756 let MIOperandInfo = (ops i64imm);
758 def VectorIndexB : Operand<i64>, ImmLeaf<i64, [{
759 return ((uint64_t)Imm) < 16;
761 let ParserMatchClass = VectorIndexBOperand;
762 let PrintMethod = "printVectorIndex";
763 let MIOperandInfo = (ops i64imm);
765 def VectorIndexH : Operand<i64>, ImmLeaf<i64, [{
766 return ((uint64_t)Imm) < 8;
768 let ParserMatchClass = VectorIndexHOperand;
769 let PrintMethod = "printVectorIndex";
770 let MIOperandInfo = (ops i64imm);
772 def VectorIndexS : Operand<i64>, ImmLeaf<i64, [{
773 return ((uint64_t)Imm) < 4;
775 let ParserMatchClass = VectorIndexSOperand;
776 let PrintMethod = "printVectorIndex";
777 let MIOperandInfo = (ops i64imm);
779 def VectorIndexD : Operand<i64>, ImmLeaf<i64, [{
780 return ((uint64_t)Imm) < 2;
782 let ParserMatchClass = VectorIndexDOperand;
783 let PrintMethod = "printVectorIndex";
784 let MIOperandInfo = (ops i64imm);
787 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
788 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
789 // are encoded as the eight bit value 'abcdefgh'.
790 def simdimmtype10 : Operand<i32>,
791 PatLeaf<(f64 fpimm), [{
792 return AArch64_AM::isAdvSIMDModImmType10(N->getValueAPF()
795 }], SDNodeXForm<fpimm, [{
796 APFloat InVal = N->getValueAPF();
797 uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
800 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
802 let ParserMatchClass = SIMDImmType10Operand;
803 let PrintMethod = "printSIMDType10Operand";
811 // Base encoding for system instruction operands.
812 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
813 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
814 list<dag> pattern = []>
815 : I<oops, iops, asm, operands, "", pattern> {
816 let Inst{31-22} = 0b1101010100;
820 // System instructions which do not have an Rt register.
821 class SimpleSystemI<bit L, dag iops, string asm, string operands,
822 list<dag> pattern = []>
823 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
824 let Inst{4-0} = 0b11111;
827 // System instructions which have an Rt register.
828 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
829 : BaseSystemI<L, oops, iops, asm, operands>,
835 // Hint instructions that take both a CRm and a 3-bit immediate.
836 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
837 // model patterns with sufficiently fine granularity
838 let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
839 class HintI<string mnemonic>
840 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#"\t$imm", "",
841 [(int_aarch64_hint imm0_127:$imm)]>,
844 let Inst{20-12} = 0b000110010;
845 let Inst{11-5} = imm;
848 // System instructions taking a single literal operand which encodes into
849 // CRm. op2 differentiates the opcodes.
850 def BarrierAsmOperand : AsmOperandClass {
851 let Name = "Barrier";
852 let ParserMethod = "tryParseBarrierOperand";
854 def barrier_op : Operand<i32> {
855 let PrintMethod = "printBarrierOption";
856 let ParserMatchClass = BarrierAsmOperand;
858 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
859 list<dag> pattern = []>
860 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
861 Sched<[WriteBarrier]> {
863 let Inst{20-12} = 0b000110011;
864 let Inst{11-8} = CRm;
868 // MRS/MSR system instructions. These have different operand classes because
869 // a different subset of registers can be accessed through each instruction.
870 def MRSSystemRegisterOperand : AsmOperandClass {
871 let Name = "MRSSystemRegister";
872 let ParserMethod = "tryParseSysReg";
873 let DiagnosticType = "MRS";
875 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
876 def mrs_sysreg_op : Operand<i32> {
877 let ParserMatchClass = MRSSystemRegisterOperand;
878 let DecoderMethod = "DecodeMRSSystemRegister";
879 let PrintMethod = "printMRSSystemRegister";
882 def MSRSystemRegisterOperand : AsmOperandClass {
883 let Name = "MSRSystemRegister";
884 let ParserMethod = "tryParseSysReg";
885 let DiagnosticType = "MSR";
887 def msr_sysreg_op : Operand<i32> {
888 let ParserMatchClass = MSRSystemRegisterOperand;
889 let DecoderMethod = "DecodeMSRSystemRegister";
890 let PrintMethod = "printMSRSystemRegister";
893 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
894 "mrs", "\t$Rt, $systemreg"> {
896 let Inst{20-5} = systemreg;
899 // FIXME: Some of these def NZCV, others don't. Best way to model that?
900 // Explicitly modeling each of the system register as a register class
901 // would do it, but feels like overkill at this point.
902 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
903 "msr", "\t$systemreg, $Rt"> {
905 let Inst{20-5} = systemreg;
908 def SystemPStateFieldOperand : AsmOperandClass {
909 let Name = "SystemPStateField";
910 let ParserMethod = "tryParseSysReg";
912 def pstatefield_op : Operand<i32> {
913 let ParserMatchClass = SystemPStateFieldOperand;
914 let PrintMethod = "printSystemPStateField";
919 : SimpleSystemI<0, (ins pstatefield_op:$pstate_field, imm0_15:$imm),
920 "msr", "\t$pstate_field, $imm">,
924 let Inst{20-19} = 0b00;
925 let Inst{18-16} = pstatefield{5-3};
926 let Inst{15-12} = 0b0100;
927 let Inst{11-8} = imm;
928 let Inst{7-5} = pstatefield{2-0};
930 let DecoderMethod = "DecodeSystemPStateInstruction";
931 // MSRpstateI aliases with MSRI. When the MSRpstateI decoder method returns
932 // Fail the decoder should attempt to decode the instruction as MSRI.
933 let hasCompleteDecoder = 0;
936 // SYS and SYSL generic system instructions.
937 def SysCRAsmOperand : AsmOperandClass {
939 let ParserMethod = "tryParseSysCROperand";
942 def sys_cr_op : Operand<i32> {
943 let PrintMethod = "printSysCROperand";
944 let ParserMatchClass = SysCRAsmOperand;
947 class SystemXtI<bit L, string asm>
948 : RtSystemI<L, (outs),
949 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
950 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
955 let Inst{20-19} = 0b01;
956 let Inst{18-16} = op1;
957 let Inst{15-12} = Cn;
962 class SystemLXtI<bit L, string asm>
963 : RtSystemI<L, (outs),
964 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
965 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
970 let Inst{20-19} = 0b01;
971 let Inst{18-16} = op1;
972 let Inst{15-12} = Cn;
978 // Branch (register) instructions:
986 // otherwise UNDEFINED
987 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
988 string operands, list<dag> pattern>
989 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
990 let Inst{31-25} = 0b1101011;
991 let Inst{24-21} = opc;
992 let Inst{20-16} = 0b11111;
993 let Inst{15-10} = 0b000000;
994 let Inst{4-0} = 0b00000;
997 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
998 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1003 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
1004 class SpecialReturn<bits<4> opc, string asm>
1005 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
1006 let Inst{9-5} = 0b11111;
1010 // Conditional branch instruction.
1014 // 4-bit immediate. Pretty-printed as <cc>
1015 def ccode : Operand<i32> {
1016 let PrintMethod = "printCondCode";
1017 let ParserMatchClass = CondCode;
1019 def inv_ccode : Operand<i32> {
1020 // AL and NV are invalid in the aliases which use inv_ccode
1021 let PrintMethod = "printInverseCondCode";
1022 let ParserMatchClass = CondCode;
1023 let MCOperandPredicate = [{
1024 return MCOp.isImm() &&
1025 MCOp.getImm() != AArch64CC::AL &&
1026 MCOp.getImm() != AArch64CC::NV;
1030 // Conditional branch target. 19-bit immediate. The low two bits of the target
1031 // offset are implied zero and so are not part of the immediate.
1032 def PCRelLabel19Operand : AsmOperandClass {
1033 let Name = "PCRelLabel19";
1034 let DiagnosticType = "InvalidLabel";
1036 def am_brcond : Operand<OtherVT> {
1037 let EncoderMethod = "getCondBranchTargetOpValue";
1038 let DecoderMethod = "DecodePCRelLabel19";
1039 let PrintMethod = "printAlignedLabel";
1040 let ParserMatchClass = PCRelLabel19Operand;
1043 class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
1044 "b", ".$cond\t$target", "",
1045 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
1048 let isTerminator = 1;
1053 let Inst{31-24} = 0b01010100;
1054 let Inst{23-5} = target;
1056 let Inst{3-0} = cond;
1060 // Compare-and-branch instructions.
1062 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
1063 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
1064 asm, "\t$Rt, $target", "",
1065 [(node regtype:$Rt, bb:$target)]>,
1068 let isTerminator = 1;
1072 let Inst{30-25} = 0b011010;
1074 let Inst{23-5} = target;
1078 multiclass CmpBranch<bit op, string asm, SDNode node> {
1079 def W : BaseCmpBranch<GPR32, op, asm, node> {
1082 def X : BaseCmpBranch<GPR64, op, asm, node> {
1088 // Test-bit-and-branch instructions.
1090 // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
1091 // the target offset are implied zero and so are not part of the immediate.
1092 def BranchTarget14Operand : AsmOperandClass {
1093 let Name = "BranchTarget14";
1095 def am_tbrcond : Operand<OtherVT> {
1096 let EncoderMethod = "getTestBranchTargetOpValue";
1097 let PrintMethod = "printAlignedLabel";
1098 let ParserMatchClass = BranchTarget14Operand;
1101 // AsmOperand classes to emit (or not) special diagnostics
1102 def TBZImm0_31Operand : AsmOperandClass {
1103 let Name = "TBZImm0_31";
1104 let PredicateMethod = "isImm0_31";
1105 let RenderMethod = "addImm0_31Operands";
1107 def TBZImm32_63Operand : AsmOperandClass {
1108 let Name = "Imm32_63";
1109 let DiagnosticType = "InvalidImm0_63";
1112 class tbz_imm0_31<AsmOperandClass matcher> : Operand<i64>, ImmLeaf<i64, [{
1113 return (((uint32_t)Imm) < 32);
1115 let ParserMatchClass = matcher;
1118 def tbz_imm0_31_diag : tbz_imm0_31<Imm0_31Operand>;
1119 def tbz_imm0_31_nodiag : tbz_imm0_31<TBZImm0_31Operand>;
1121 def tbz_imm32_63 : Operand<i64>, ImmLeaf<i64, [{
1122 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
1124 let ParserMatchClass = TBZImm32_63Operand;
1127 class BaseTestBranch<RegisterClass regtype, Operand immtype,
1128 bit op, string asm, SDNode node>
1129 : I<(outs), (ins regtype:$Rt, immtype:$bit_off, am_tbrcond:$target),
1130 asm, "\t$Rt, $bit_off, $target", "",
1131 [(node regtype:$Rt, immtype:$bit_off, bb:$target)]>,
1134 let isTerminator = 1;
1140 let Inst{30-25} = 0b011011;
1142 let Inst{23-19} = bit_off{4-0};
1143 let Inst{18-5} = target;
1146 let DecoderMethod = "DecodeTestAndBranch";
1149 multiclass TestBranch<bit op, string asm, SDNode node> {
1150 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1154 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1158 // Alias X-reg with 0-31 imm to W-Reg.
1159 def : InstAlias<asm # "\t$Rd, $imm, $target",
1160 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1161 tbz_imm0_31_nodiag:$imm, am_tbrcond:$target), 0>;
1162 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1163 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1164 tbz_imm0_31_diag:$imm, bb:$target)>;
1168 // Unconditional branch (immediate) instructions.
1170 def BranchTarget26Operand : AsmOperandClass {
1171 let Name = "BranchTarget26";
1172 let DiagnosticType = "InvalidLabel";
1174 def am_b_target : Operand<OtherVT> {
1175 let EncoderMethod = "getBranchTargetOpValue";
1176 let PrintMethod = "printAlignedLabel";
1177 let ParserMatchClass = BranchTarget26Operand;
1179 def am_bl_target : Operand<i64> {
1180 let EncoderMethod = "getBranchTargetOpValue";
1181 let PrintMethod = "printAlignedLabel";
1182 let ParserMatchClass = BranchTarget26Operand;
1185 class BImm<bit op, dag iops, string asm, list<dag> pattern>
1186 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
1189 let Inst{30-26} = 0b00101;
1190 let Inst{25-0} = addr;
1192 let DecoderMethod = "DecodeUnconditionalBranch";
1195 class BranchImm<bit op, string asm, list<dag> pattern>
1196 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
1197 class CallImm<bit op, string asm, list<dag> pattern>
1198 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
1201 // Basic one-operand data processing instructions.
1204 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1205 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1206 SDPatternOperator node>
1207 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1208 [(set regtype:$Rd, (node regtype:$Rn))]>,
1209 Sched<[WriteI, ReadI]> {
1213 let Inst{30-13} = 0b101101011000000000;
1214 let Inst{12-10} = opc;
1219 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1220 multiclass OneOperandData<bits<3> opc, string asm,
1221 SDPatternOperator node = null_frag> {
1222 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1226 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1231 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1232 : BaseOneOperandData<opc, GPR32, asm, node> {
1236 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1237 : BaseOneOperandData<opc, GPR64, asm, node> {
1242 // Basic two-operand data processing instructions.
1244 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1246 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1247 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1248 Sched<[WriteI, ReadI, ReadI]> {
1253 let Inst{30} = isSub;
1254 let Inst{28-21} = 0b11010000;
1255 let Inst{20-16} = Rm;
1256 let Inst{15-10} = 0;
1261 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1263 : BaseBaseAddSubCarry<isSub, regtype, asm,
1264 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1266 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1268 : BaseBaseAddSubCarry<isSub, regtype, asm,
1269 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1274 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1275 SDNode OpNode, SDNode OpNode_setflags> {
1276 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1280 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1286 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1291 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1298 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1299 SDPatternOperator OpNode>
1300 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1301 asm, "\t$Rd, $Rn, $Rm", "",
1302 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1306 let Inst{30-21} = 0b0011010110;
1307 let Inst{20-16} = Rm;
1308 let Inst{15-14} = 0b00;
1309 let Inst{13-10} = opc;
1314 class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
1315 SDPatternOperator OpNode>
1316 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
1317 let Inst{10} = isSigned;
1320 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
1321 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1322 Sched<[WriteID32, ReadID, ReadID]> {
1325 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1326 Sched<[WriteID64, ReadID, ReadID]> {
1331 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1332 SDPatternOperator OpNode = null_frag>
1333 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
1334 Sched<[WriteIS, ReadI]> {
1335 let Inst{11-10} = shift_type;
1338 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1339 def Wr : BaseShift<shift_type, GPR32, asm> {
1343 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1347 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1348 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1349 (EXTRACT_SUBREG i64:$Rm, sub_32))>;
1351 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1352 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1354 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1355 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1357 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1358 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1361 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
1362 : InstAlias<asm#"\t$dst, $src1, $src2",
1363 (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;
1365 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1366 RegisterClass addtype, string asm,
1368 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1369 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1374 let Inst{30-24} = 0b0011011;
1375 let Inst{23-21} = opc;
1376 let Inst{20-16} = Rm;
1377 let Inst{15} = isSub;
1378 let Inst{14-10} = Ra;
1383 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1384 // MADD/MSUB generation is decided by MachineCombiner.cpp
1385 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1386 [/*(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))*/]>,
1387 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1391 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1392 [/*(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))*/]>,
1393 Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> {
1398 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1399 SDNode AccNode, SDNode ExtNode>
1400 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1401 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1402 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1403 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1407 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1408 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1409 asm, "\t$Rd, $Rn, $Rm", "",
1410 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1411 Sched<[WriteIM64, ReadIM, ReadIM]> {
1415 let Inst{31-24} = 0b10011011;
1416 let Inst{23-21} = opc;
1417 let Inst{20-16} = Rm;
1422 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
1423 // (i.e. all bits 1) but is ignored by the processor.
1424 let PostEncoderMethod = "fixMulHigh";
1427 class MulAccumWAlias<string asm, Instruction inst>
1428 : InstAlias<asm#"\t$dst, $src1, $src2",
1429 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1430 class MulAccumXAlias<string asm, Instruction inst>
1431 : InstAlias<asm#"\t$dst, $src1, $src2",
1432 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1433 class WideMulAccumAlias<string asm, Instruction inst>
1434 : InstAlias<asm#"\t$dst, $src1, $src2",
1435 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1437 class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
1438 SDPatternOperator OpNode, string asm>
1439 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1440 asm, "\t$Rd, $Rn, $Rm", "",
1441 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1442 Sched<[WriteISReg, ReadI, ReadISReg]> {
1448 let Inst{30-21} = 0b0011010110;
1449 let Inst{20-16} = Rm;
1450 let Inst{15-13} = 0b010;
1452 let Inst{11-10} = sz;
1455 let Predicates = [HasCRC];
1459 // Address generation.
1462 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
1463 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1468 let Inst{31} = page;
1469 let Inst{30-29} = label{1-0};
1470 let Inst{28-24} = 0b10000;
1471 let Inst{23-5} = label{20-2};
1474 let DecoderMethod = "DecodeAdrInstruction";
1481 def movimm32_imm : Operand<i32> {
1482 let ParserMatchClass = Imm0_65535Operand;
1483 let EncoderMethod = "getMoveWideImmOpValue";
1484 let PrintMethod = "printHexImm";
1486 def movimm32_shift : Operand<i32> {
1487 let PrintMethod = "printShifter";
1488 let ParserMatchClass = MovImm32ShifterOperand;
1490 def movimm64_shift : Operand<i32> {
1491 let PrintMethod = "printShifter";
1492 let ParserMatchClass = MovImm64ShifterOperand;
1495 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1496 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1498 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1499 asm, "\t$Rd, $imm$shift", "", []>,
1504 let Inst{30-29} = opc;
1505 let Inst{28-23} = 0b100101;
1506 let Inst{22-21} = shift{5-4};
1507 let Inst{20-5} = imm;
1510 let DecoderMethod = "DecodeMoveImmInstruction";
1513 multiclass MoveImmediate<bits<2> opc, string asm> {
1514 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1518 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1523 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1524 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1526 : I<(outs regtype:$Rd),
1527 (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
1528 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1529 Sched<[WriteI, ReadI]> {
1533 let Inst{30-29} = opc;
1534 let Inst{28-23} = 0b100101;
1535 let Inst{22-21} = shift{5-4};
1536 let Inst{20-5} = imm;
1539 let DecoderMethod = "DecodeMoveImmInstruction";
1542 multiclass InsertImmediate<bits<2> opc, string asm> {
1543 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1547 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1556 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1557 RegisterClass srcRegtype, addsub_shifted_imm immtype,
1558 string asm, SDPatternOperator OpNode>
1559 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1560 asm, "\t$Rd, $Rn, $imm", "",
1561 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1562 Sched<[WriteI, ReadI]> {
1566 let Inst{30} = isSub;
1567 let Inst{29} = setFlags;
1568 let Inst{28-24} = 0b10001;
1569 let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
1570 let Inst{21-10} = imm{11-0};
1573 let DecoderMethod = "DecodeBaseAddSubImm";
1576 class BaseAddSubRegPseudo<RegisterClass regtype,
1577 SDPatternOperator OpNode>
1578 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1579 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1580 Sched<[WriteI, ReadI, ReadI]>;
1582 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1583 arith_shifted_reg shifted_regtype, string asm,
1584 SDPatternOperator OpNode>
1585 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1586 asm, "\t$Rd, $Rn, $Rm", "",
1587 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1588 Sched<[WriteISReg, ReadI, ReadISReg]> {
1589 // The operands are in order to match the 'addr' MI operands, so we
1590 // don't need an encoder method and by-name matching. Just use the default
1591 // in-order handling. Since we're using by-order, make sure the names
1597 let Inst{30} = isSub;
1598 let Inst{29} = setFlags;
1599 let Inst{28-24} = 0b01011;
1600 let Inst{23-22} = shift{7-6};
1602 let Inst{20-16} = src2;
1603 let Inst{15-10} = shift{5-0};
1604 let Inst{9-5} = src1;
1605 let Inst{4-0} = dst;
1607 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1610 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1611 RegisterClass src1Regtype, Operand src2Regtype,
1612 string asm, SDPatternOperator OpNode>
1613 : I<(outs dstRegtype:$R1),
1614 (ins src1Regtype:$R2, src2Regtype:$R3),
1615 asm, "\t$R1, $R2, $R3", "",
1616 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
1617 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1622 let Inst{30} = isSub;
1623 let Inst{29} = setFlags;
1624 let Inst{28-24} = 0b01011;
1625 let Inst{23-21} = 0b001;
1626 let Inst{20-16} = Rm;
1627 let Inst{15-13} = ext{5-3};
1628 let Inst{12-10} = ext{2-0};
1632 let DecoderMethod = "DecodeAddSubERegInstruction";
1635 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1636 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1637 RegisterClass src1Regtype, RegisterClass src2Regtype,
1638 Operand ext_op, string asm>
1639 : I<(outs dstRegtype:$Rd),
1640 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1641 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1642 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1647 let Inst{30} = isSub;
1648 let Inst{29} = setFlags;
1649 let Inst{28-24} = 0b01011;
1650 let Inst{23-21} = 0b001;
1651 let Inst{20-16} = Rm;
1652 let Inst{15} = ext{5};
1653 let Inst{12-10} = ext{2-0};
1657 let DecoderMethod = "DecodeAddSubERegInstruction";
1660 // Aliases for register+register add/subtract.
1661 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
1662 RegisterClass src1Regtype, RegisterClass src2Regtype,
1664 : InstAlias<asm#"\t$dst, $src1, $src2",
1665 (inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
1668 multiclass AddSub<bit isSub, string mnemonic, string alias,
1669 SDPatternOperator OpNode = null_frag> {
1670 let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1671 // Add/Subtract immediate
1672 // Increase the weight of the immediate variant to try to match it before
1673 // the extended register variant.
1674 // We used to match the register variant before the immediate when the
1675 // register argument could be implicitly zero-extended.
1676 let AddedComplexity = 6 in
1677 def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1681 let AddedComplexity = 6 in
1682 def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1687 // Add/Subtract register - Only used for CodeGen
1688 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1689 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1691 // Add/Subtract shifted register
1692 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1696 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1702 // Add/Subtract extended register
1703 let AddedComplexity = 1, hasSideEffects = 0 in {
1704 def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1705 arith_extended_reg32<i32>, mnemonic, OpNode> {
1708 def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1709 arith_extended_reg32to64<i64>, mnemonic, OpNode> {
1714 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1715 arith_extendlsl64, mnemonic> {
1716 // UXTX and SXTX only.
1717 let Inst{14-13} = 0b11;
1721 // add Rd, Rb, -imm -> sub Rd, Rn, imm
1722 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1723 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32sp:$Rn,
1724 addsub_shifted_imm32_neg:$imm), 0>;
1725 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1726 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64sp:$Rn,
1727 addsub_shifted_imm64_neg:$imm), 0>;
1729 // Register/register aliases with no shift when SP is not used.
1730 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1731 GPR32, GPR32, GPR32, 0>;
1732 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1733 GPR64, GPR64, GPR64, 0>;
1735 // Register/register aliases with no shift when either the destination or
1736 // first source register is SP.
1737 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1738 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1739 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1740 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
1741 def : AddSubRegAlias<mnemonic,
1742 !cast<Instruction>(NAME#"Xrx64"),
1743 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1744 def : AddSubRegAlias<mnemonic,
1745 !cast<Instruction>(NAME#"Xrx64"),
1746 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1749 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
1750 string alias, string cmpAlias> {
1751 let isCompare = 1, Defs = [NZCV] in {
1752 // Add/Subtract immediate
1753 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1757 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1762 // Add/Subtract register
1763 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1764 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1766 // Add/Subtract shifted register
1767 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1771 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1776 // Add/Subtract extended register
1777 let AddedComplexity = 1 in {
1778 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1779 arith_extended_reg32<i32>, mnemonic, OpNode> {
1782 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1783 arith_extended_reg32<i64>, mnemonic, OpNode> {
1788 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1789 arith_extendlsl64, mnemonic> {
1790 // UXTX and SXTX only.
1791 let Inst{14-13} = 0b11;
1796 // Support negative immediates, e.g. adds Rd, Rn, -imm -> subs Rd, Rn, imm
1797 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1798 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32sp:$Rn,
1799 addsub_shifted_imm32_neg:$imm), 0>;
1800 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1801 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64sp:$Rn,
1802 addsub_shifted_imm64_neg:$imm), 0>;
1805 def : InstAlias<cmp#"\t$src, $imm", (!cast<Instruction>(NAME#"Wri")
1806 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm), 5>;
1807 def : InstAlias<cmp#"\t$src, $imm", (!cast<Instruction>(NAME#"Xri")
1808 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
1809 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
1810 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1811 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
1812 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1813 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
1814 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
1815 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
1816 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
1817 def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
1818 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
1820 // Support negative immediates, e.g. cmp Rn, -imm -> cmn Rn, imm
1821 def : InstAlias<cmpAlias#"\t$src, $imm", (!cast<Instruction>(NAME#"Wri")
1822 WZR, GPR32sp:$src, addsub_shifted_imm32_neg:$imm), 0>;
1823 def : InstAlias<cmpAlias#"\t$src, $imm", (!cast<Instruction>(NAME#"Xri")
1824 XZR, GPR64sp:$src, addsub_shifted_imm64_neg:$imm), 0>;
1826 // Compare shorthands
1827 def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrs")
1828 WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
1829 def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrs")
1830 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
1831 def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrx")
1832 WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
1833 def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrx64")
1834 XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;
1836 // Register/register aliases with no shift when SP is not used.
1837 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1838 GPR32, GPR32, GPR32, 0>;
1839 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1840 GPR64, GPR64, GPR64, 0>;
1842 // Register/register aliases with no shift when the first source register
1844 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1845 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
1846 def : AddSubRegAlias<mnemonic,
1847 !cast<Instruction>(NAME#"Xrx64"),
1848 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
1854 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1856 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
1858 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1860 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1861 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1862 Sched<[WriteExtr, ReadExtrHi]> {
1868 let Inst{30-23} = 0b00100111;
1870 let Inst{20-16} = Rm;
1871 let Inst{15-10} = imm;
1876 multiclass ExtractImm<string asm> {
1877 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1879 (AArch64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1882 // imm<5> must be zero.
1885 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1887 (AArch64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1898 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1899 class BaseBitfieldImm<bits<2> opc,
1900 RegisterClass regtype, Operand imm_type, string asm>
1901 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1902 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1903 Sched<[WriteIS, ReadI]> {
1909 let Inst{30-29} = opc;
1910 let Inst{28-23} = 0b100110;
1911 let Inst{21-16} = immr;
1912 let Inst{15-10} = imms;
1917 multiclass BitfieldImm<bits<2> opc, string asm> {
1918 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1921 // imms<5> and immr<5> must be zero, else ReservedValue().
1925 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1931 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1932 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
1933 RegisterClass regtype, Operand imm_type, string asm>
1934 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1936 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1937 Sched<[WriteIS, ReadI]> {
1943 let Inst{30-29} = opc;
1944 let Inst{28-23} = 0b100110;
1945 let Inst{21-16} = immr;
1946 let Inst{15-10} = imms;
1951 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
1952 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
1955 // imms<5> and immr<5> must be zero, else ReservedValue().
1959 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
1969 // Logical (immediate)
1970 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
1971 RegisterClass sregtype, Operand imm_type, string asm,
1973 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
1974 asm, "\t$Rd, $Rn, $imm", "", pattern>,
1975 Sched<[WriteI, ReadI]> {
1979 let Inst{30-29} = opc;
1980 let Inst{28-23} = 0b100100;
1981 let Inst{22} = imm{12};
1982 let Inst{21-16} = imm{11-6};
1983 let Inst{15-10} = imm{5-0};
1987 let DecoderMethod = "DecodeLogicalImmInstruction";
1990 // Logical (shifted register)
1991 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
1992 logical_shifted_reg shifted_regtype, string asm,
1994 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1995 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1996 Sched<[WriteISReg, ReadI, ReadISReg]> {
1997 // The operands are in order to match the 'addr' MI operands, so we
1998 // don't need an encoder method and by-name matching. Just use the default
1999 // in-order handling. Since we're using by-order, make sure the names
2005 let Inst{30-29} = opc;
2006 let Inst{28-24} = 0b01010;
2007 let Inst{23-22} = shift{7-6};
2009 let Inst{20-16} = src2;
2010 let Inst{15-10} = shift{5-0};
2011 let Inst{9-5} = src1;
2012 let Inst{4-0} = dst;
2014 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
2017 // Aliases for register+register logical instructions.
2018 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
2019 : InstAlias<asm#"\t$dst, $src1, $src2",
2020 (inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
2022 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
2024 let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in
2025 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
2026 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
2027 logical_imm32:$imm))]> {
2029 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
2031 let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in
2032 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
2033 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
2034 logical_imm64:$imm))]> {
2038 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2039 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
2040 logical_imm32_not:$imm), 0>;
2041 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2042 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
2043 logical_imm64_not:$imm), 0>;
2046 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode,
2048 let isCompare = 1, Defs = [NZCV] in {
2049 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
2050 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
2052 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
2054 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
2055 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
2058 } // end Defs = [NZCV]
2060 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2061 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
2062 logical_imm32_not:$imm), 0>;
2063 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2064 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
2065 logical_imm64_not:$imm), 0>;
2068 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
2069 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2070 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2071 Sched<[WriteI, ReadI, ReadI]>;
2073 // Split from LogicalImm as not all instructions have both.
2074 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
2075 SDPatternOperator OpNode> {
2076 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2077 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2078 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2081 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2082 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2083 logical_shifted_reg32:$Rm))]> {
2086 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2087 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2088 logical_shifted_reg64:$Rm))]> {
2092 def : LogicalRegAlias<mnemonic,
2093 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2094 def : LogicalRegAlias<mnemonic,
2095 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2098 // Split from LogicalReg to allow setting NZCV Defs
2099 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
2100 SDPatternOperator OpNode = null_frag> {
2101 let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
2102 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2103 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2105 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2106 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2109 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2110 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2115 def : LogicalRegAlias<mnemonic,
2116 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2117 def : LogicalRegAlias<mnemonic,
2118 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2122 // Conditionally set flags
2125 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2126 class BaseCondComparisonImm<bit op, RegisterClass regtype, ImmLeaf immtype,
2127 string mnemonic, SDNode OpNode>
2128 : I<(outs), (ins regtype:$Rn, immtype:$imm, imm32_0_15:$nzcv, ccode:$cond),
2129 mnemonic, "\t$Rn, $imm, $nzcv, $cond", "",
2130 [(set NZCV, (OpNode regtype:$Rn, immtype:$imm, (i32 imm:$nzcv),
2131 (i32 imm:$cond), NZCV))]>,
2132 Sched<[WriteI, ReadI]> {
2142 let Inst{29-21} = 0b111010010;
2143 let Inst{20-16} = imm;
2144 let Inst{15-12} = cond;
2145 let Inst{11-10} = 0b10;
2148 let Inst{3-0} = nzcv;
2151 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2152 class BaseCondComparisonReg<bit op, RegisterClass regtype, string mnemonic,
2154 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
2155 mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "",
2156 [(set NZCV, (OpNode regtype:$Rn, regtype:$Rm, (i32 imm:$nzcv),
2157 (i32 imm:$cond), NZCV))]>,
2158 Sched<[WriteI, ReadI, ReadI]> {
2168 let Inst{29-21} = 0b111010010;
2169 let Inst{20-16} = Rm;
2170 let Inst{15-12} = cond;
2171 let Inst{11-10} = 0b00;
2174 let Inst{3-0} = nzcv;
2177 multiclass CondComparison<bit op, string mnemonic, SDNode OpNode> {
2178 // immediate operand variants
2179 def Wi : BaseCondComparisonImm<op, GPR32, imm32_0_31, mnemonic, OpNode> {
2182 def Xi : BaseCondComparisonImm<op, GPR64, imm0_31, mnemonic, OpNode> {
2185 // register operand variants
2186 def Wr : BaseCondComparisonReg<op, GPR32, mnemonic, OpNode> {
2189 def Xr : BaseCondComparisonReg<op, GPR64, mnemonic, OpNode> {
2195 // Conditional select
2198 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
2199 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2200 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2202 (AArch64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
2203 Sched<[WriteI, ReadI, ReadI]> {
2212 let Inst{29-21} = 0b011010100;
2213 let Inst{20-16} = Rm;
2214 let Inst{15-12} = cond;
2215 let Inst{11-10} = op2;
2220 multiclass CondSelect<bit op, bits<2> op2, string asm> {
2221 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
2224 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
2229 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
2231 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2232 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2234 (AArch64csel regtype:$Rn, (frag regtype:$Rm),
2235 (i32 imm:$cond), NZCV))]>,
2236 Sched<[WriteI, ReadI, ReadI]> {
2245 let Inst{29-21} = 0b011010100;
2246 let Inst{20-16} = Rm;
2247 let Inst{15-12} = cond;
2248 let Inst{11-10} = op2;
2253 def inv_cond_XFORM : SDNodeXForm<imm, [{
2254 AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue());
2255 return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), SDLoc(N),
2259 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
2260 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
2263 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
2267 def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2268 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2269 (inv_cond_XFORM imm:$cond))>;
2271 def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2272 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2273 (inv_cond_XFORM imm:$cond))>;
2277 // Special Mask Value
2279 def maski8_or_more : Operand<i32>,
2280 ImmLeaf<i32, [{ return (Imm & 0xff) == 0xff; }]> {
2282 def maski16_or_more : Operand<i32>,
2283 ImmLeaf<i32, [{ return (Imm & 0xffff) == 0xffff; }]> {
2291 // (unsigned immediate)
2292 // Indexed for 8-bit registers. offset is in range [0,4095].
2293 def am_indexed8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []>;
2294 def am_indexed16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []>;
2295 def am_indexed32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []>;
2296 def am_indexed64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []>;
2297 def am_indexed128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []>;
2299 class UImm12OffsetOperand<int Scale> : AsmOperandClass {
2300 let Name = "UImm12Offset" # Scale;
2301 let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">";
2302 let PredicateMethod = "isUImm12Offset<" # Scale # ">";
2303 let DiagnosticType = "InvalidMemoryIndexed" # Scale;
2306 def UImm12OffsetScale1Operand : UImm12OffsetOperand<1>;
2307 def UImm12OffsetScale2Operand : UImm12OffsetOperand<2>;
2308 def UImm12OffsetScale4Operand : UImm12OffsetOperand<4>;
2309 def UImm12OffsetScale8Operand : UImm12OffsetOperand<8>;
2310 def UImm12OffsetScale16Operand : UImm12OffsetOperand<16>;
2312 class uimm12_scaled<int Scale> : Operand<i64> {
2313 let ParserMatchClass
2314 = !cast<AsmOperandClass>("UImm12OffsetScale" # Scale # "Operand");
2316 = "getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale" # Scale # ">";
2317 let PrintMethod = "printUImm12Offset<" # Scale # ">";
2320 def uimm12s1 : uimm12_scaled<1>;
2321 def uimm12s2 : uimm12_scaled<2>;
2322 def uimm12s4 : uimm12_scaled<4>;
2323 def uimm12s8 : uimm12_scaled<8>;
2324 def uimm12s16 : uimm12_scaled<16>;
2326 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2327 string asm, list<dag> pattern>
2328 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2334 let Inst{31-30} = sz;
2335 let Inst{29-27} = 0b111;
2337 let Inst{25-24} = 0b01;
2338 let Inst{23-22} = opc;
2339 let Inst{21-10} = offset;
2343 let DecoderMethod = "DecodeUnsignedLdStInstruction";
2346 multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2347 Operand indextype, string asm, list<dag> pattern> {
2348 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2349 def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
2350 (ins GPR64sp:$Rn, indextype:$offset),
2354 def : InstAlias<asm # "\t$Rt, [$Rn]",
2355 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2358 multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2359 Operand indextype, string asm, list<dag> pattern> {
2360 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2361 def ui : BaseLoadStoreUI<sz, V, opc, (outs),
2362 (ins regtype:$Rt, GPR64sp:$Rn, indextype:$offset),
2366 def : InstAlias<asm # "\t$Rt, [$Rn]",
2367 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2370 def PrefetchOperand : AsmOperandClass {
2371 let Name = "Prefetch";
2372 let ParserMethod = "tryParsePrefetch";
2374 def prfop : Operand<i32> {
2375 let PrintMethod = "printPrefetchOp";
2376 let ParserMatchClass = PrefetchOperand;
2379 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2380 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2381 : BaseLoadStoreUI<sz, V, opc,
2382 (outs), (ins prfop:$Rt, GPR64sp:$Rn, uimm12s8:$offset),
2390 // Load literal address: 19-bit immediate. The low two bits of the target
2391 // offset are implied zero and so are not part of the immediate.
2392 def am_ldrlit : Operand<OtherVT> {
2393 let EncoderMethod = "getLoadLiteralOpValue";
2394 let DecoderMethod = "DecodePCRelLabel19";
2395 let PrintMethod = "printAlignedLabel";
2396 let ParserMatchClass = PCRelLabel19Operand;
2399 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2400 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2401 : I<(outs regtype:$Rt), (ins am_ldrlit:$label),
2402 asm, "\t$Rt, $label", "", []>,
2406 let Inst{31-30} = opc;
2407 let Inst{29-27} = 0b011;
2409 let Inst{25-24} = 0b00;
2410 let Inst{23-5} = label;
2414 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2415 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2416 : I<(outs), (ins prfop:$Rt, am_ldrlit:$label),
2417 asm, "\t$Rt, $label", "", pat>,
2421 let Inst{31-30} = opc;
2422 let Inst{29-27} = 0b011;
2424 let Inst{25-24} = 0b00;
2425 let Inst{23-5} = label;
2430 // Load/store register offset
2433 def ro_Xindexed8 : ComplexPattern<i64, 4, "SelectAddrModeXRO<8>", []>;
2434 def ro_Xindexed16 : ComplexPattern<i64, 4, "SelectAddrModeXRO<16>", []>;
2435 def ro_Xindexed32 : ComplexPattern<i64, 4, "SelectAddrModeXRO<32>", []>;
2436 def ro_Xindexed64 : ComplexPattern<i64, 4, "SelectAddrModeXRO<64>", []>;
2437 def ro_Xindexed128 : ComplexPattern<i64, 4, "SelectAddrModeXRO<128>", []>;
2439 def ro_Windexed8 : ComplexPattern<i64, 4, "SelectAddrModeWRO<8>", []>;
2440 def ro_Windexed16 : ComplexPattern<i64, 4, "SelectAddrModeWRO<16>", []>;
2441 def ro_Windexed32 : ComplexPattern<i64, 4, "SelectAddrModeWRO<32>", []>;
2442 def ro_Windexed64 : ComplexPattern<i64, 4, "SelectAddrModeWRO<64>", []>;
2443 def ro_Windexed128 : ComplexPattern<i64, 4, "SelectAddrModeWRO<128>", []>;
2445 class MemExtendOperand<string Reg, int Width> : AsmOperandClass {
2446 let Name = "Mem" # Reg # "Extend" # Width;
2447 let PredicateMethod = "isMem" # Reg # "Extend<" # Width # ">";
2448 let RenderMethod = "addMemExtendOperands";
2449 let DiagnosticType = "InvalidMemory" # Reg # "Extend" # Width;
2452 def MemWExtend8Operand : MemExtendOperand<"W", 8> {
2453 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2454 // the trivial shift.
2455 let RenderMethod = "addMemExtend8Operands";
2457 def MemWExtend16Operand : MemExtendOperand<"W", 16>;
2458 def MemWExtend32Operand : MemExtendOperand<"W", 32>;
2459 def MemWExtend64Operand : MemExtendOperand<"W", 64>;
2460 def MemWExtend128Operand : MemExtendOperand<"W", 128>;
2462 def MemXExtend8Operand : MemExtendOperand<"X", 8> {
2463 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2464 // the trivial shift.
2465 let RenderMethod = "addMemExtend8Operands";
2467 def MemXExtend16Operand : MemExtendOperand<"X", 16>;
2468 def MemXExtend32Operand : MemExtendOperand<"X", 32>;
2469 def MemXExtend64Operand : MemExtendOperand<"X", 64>;
2470 def MemXExtend128Operand : MemExtendOperand<"X", 128>;
2472 class ro_extend<AsmOperandClass ParserClass, string Reg, int Width>
2474 let ParserMatchClass = ParserClass;
2475 let PrintMethod = "printMemExtend<'" # Reg # "', " # Width # ">";
2476 let DecoderMethod = "DecodeMemExtend";
2477 let EncoderMethod = "getMemExtendOpValue";
2478 let MIOperandInfo = (ops i32imm:$signed, i32imm:$doshift);
2481 def ro_Wextend8 : ro_extend<MemWExtend8Operand, "w", 8>;
2482 def ro_Wextend16 : ro_extend<MemWExtend16Operand, "w", 16>;
2483 def ro_Wextend32 : ro_extend<MemWExtend32Operand, "w", 32>;
2484 def ro_Wextend64 : ro_extend<MemWExtend64Operand, "w", 64>;
2485 def ro_Wextend128 : ro_extend<MemWExtend128Operand, "w", 128>;
2487 def ro_Xextend8 : ro_extend<MemXExtend8Operand, "x", 8>;
2488 def ro_Xextend16 : ro_extend<MemXExtend16Operand, "x", 16>;
2489 def ro_Xextend32 : ro_extend<MemXExtend32Operand, "x", 32>;
2490 def ro_Xextend64 : ro_extend<MemXExtend64Operand, "x", 64>;
2491 def ro_Xextend128 : ro_extend<MemXExtend128Operand, "x", 128>;
2493 class ROAddrMode<ComplexPattern windex, ComplexPattern xindex,
2494 Operand wextend, Operand xextend> {
2495 // CodeGen-level pattern covering the entire addressing mode.
2496 ComplexPattern Wpat = windex;
2497 ComplexPattern Xpat = xindex;
2499 // Asm-level Operand covering the valid "uxtw #3" style syntax.
2500 Operand Wext = wextend;
2501 Operand Xext = xextend;
2504 def ro8 : ROAddrMode<ro_Windexed8, ro_Xindexed8, ro_Wextend8, ro_Xextend8>;
2505 def ro16 : ROAddrMode<ro_Windexed16, ro_Xindexed16, ro_Wextend16, ro_Xextend16>;
2506 def ro32 : ROAddrMode<ro_Windexed32, ro_Xindexed32, ro_Wextend32, ro_Xextend32>;
2507 def ro64 : ROAddrMode<ro_Windexed64, ro_Xindexed64, ro_Wextend64, ro_Xextend64>;
2508 def ro128 : ROAddrMode<ro_Windexed128, ro_Xindexed128, ro_Wextend128,
2511 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2512 string asm, dag ins, dag outs, list<dag> pat>
2513 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2518 let Inst{31-30} = sz;
2519 let Inst{29-27} = 0b111;
2521 let Inst{25-24} = 0b00;
2522 let Inst{23-22} = opc;
2524 let Inst{20-16} = Rm;
2525 let Inst{15} = extend{1}; // sign extend Rm?
2527 let Inst{12} = extend{0}; // do shift?
2528 let Inst{11-10} = 0b10;
2533 class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
2534 : InstAlias<asm # "\t$Rt, [$Rn, $Rm]",
2535 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2537 multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2538 string asm, ValueType Ty, SDPatternOperator loadop> {
2539 let AddedComplexity = 10 in
2540 def roW : LoadStore8RO<sz, V, opc, regtype, asm,
2542 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2543 [(set (Ty regtype:$Rt),
2544 (loadop (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2545 ro_Wextend8:$extend)))]>,
2546 Sched<[WriteLDIdx, ReadAdrBase]> {
2550 let AddedComplexity = 10 in
2551 def roX : LoadStore8RO<sz, V, opc, regtype, asm,
2553 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2554 [(set (Ty regtype:$Rt),
2555 (loadop (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2556 ro_Xextend8:$extend)))]>,
2557 Sched<[WriteLDIdx, ReadAdrBase]> {
2561 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2564 multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2565 string asm, ValueType Ty, SDPatternOperator storeop> {
2566 let AddedComplexity = 10 in
2567 def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2568 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2569 [(storeop (Ty regtype:$Rt),
2570 (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2571 ro_Wextend8:$extend))]>,
2572 Sched<[WriteSTIdx, ReadAdrBase]> {
2576 let AddedComplexity = 10 in
2577 def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2578 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2579 [(storeop (Ty regtype:$Rt),
2580 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2581 ro_Xextend8:$extend))]>,
2582 Sched<[WriteSTIdx, ReadAdrBase]> {
2586 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2589 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2590 string asm, dag ins, dag outs, list<dag> pat>
2591 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2596 let Inst{31-30} = sz;
2597 let Inst{29-27} = 0b111;
2599 let Inst{25-24} = 0b00;
2600 let Inst{23-22} = opc;
2602 let Inst{20-16} = Rm;
2603 let Inst{15} = extend{1}; // sign extend Rm?
2605 let Inst{12} = extend{0}; // do shift?
2606 let Inst{11-10} = 0b10;
2611 multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2612 string asm, ValueType Ty, SDPatternOperator loadop> {
2613 let AddedComplexity = 10 in
2614 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2615 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2616 [(set (Ty regtype:$Rt),
2617 (loadop (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2618 ro_Wextend16:$extend)))]>,
2619 Sched<[WriteLDIdx, ReadAdrBase]> {
2623 let AddedComplexity = 10 in
2624 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2625 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2626 [(set (Ty regtype:$Rt),
2627 (loadop (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2628 ro_Xextend16:$extend)))]>,
2629 Sched<[WriteLDIdx, ReadAdrBase]> {
2633 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2636 multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2637 string asm, ValueType Ty, SDPatternOperator storeop> {
2638 let AddedComplexity = 10 in
2639 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2640 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2641 [(storeop (Ty regtype:$Rt),
2642 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2643 ro_Wextend16:$extend))]>,
2644 Sched<[WriteSTIdx, ReadAdrBase]> {
2648 let AddedComplexity = 10 in
2649 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2650 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2651 [(storeop (Ty regtype:$Rt),
2652 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2653 ro_Xextend16:$extend))]>,
2654 Sched<[WriteSTIdx, ReadAdrBase]> {
2658 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2661 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2662 string asm, dag ins, dag outs, list<dag> pat>
2663 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2668 let Inst{31-30} = sz;
2669 let Inst{29-27} = 0b111;
2671 let Inst{25-24} = 0b00;
2672 let Inst{23-22} = opc;
2674 let Inst{20-16} = Rm;
2675 let Inst{15} = extend{1}; // sign extend Rm?
2677 let Inst{12} = extend{0}; // do shift?
2678 let Inst{11-10} = 0b10;
2683 multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2684 string asm, ValueType Ty, SDPatternOperator loadop> {
2685 let AddedComplexity = 10 in
2686 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2687 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2688 [(set (Ty regtype:$Rt),
2689 (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2690 ro_Wextend32:$extend)))]>,
2691 Sched<[WriteLDIdx, ReadAdrBase]> {
2695 let AddedComplexity = 10 in
2696 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2697 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2698 [(set (Ty regtype:$Rt),
2699 (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2700 ro_Xextend32:$extend)))]>,
2701 Sched<[WriteLDIdx, ReadAdrBase]> {
2705 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2708 multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2709 string asm, ValueType Ty, SDPatternOperator storeop> {
2710 let AddedComplexity = 10 in
2711 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2712 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2713 [(storeop (Ty regtype:$Rt),
2714 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2715 ro_Wextend32:$extend))]>,
2716 Sched<[WriteSTIdx, ReadAdrBase]> {
2720 let AddedComplexity = 10 in
2721 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2722 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2723 [(storeop (Ty regtype:$Rt),
2724 (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2725 ro_Xextend32:$extend))]>,
2726 Sched<[WriteSTIdx, ReadAdrBase]> {
2730 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2733 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2734 string asm, dag ins, dag outs, list<dag> pat>
2735 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2740 let Inst{31-30} = sz;
2741 let Inst{29-27} = 0b111;
2743 let Inst{25-24} = 0b00;
2744 let Inst{23-22} = opc;
2746 let Inst{20-16} = Rm;
2747 let Inst{15} = extend{1}; // sign extend Rm?
2749 let Inst{12} = extend{0}; // do shift?
2750 let Inst{11-10} = 0b10;
2755 multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2756 string asm, ValueType Ty, SDPatternOperator loadop> {
2757 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2758 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2759 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2760 [(set (Ty regtype:$Rt),
2761 (loadop (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2762 ro_Wextend64:$extend)))]>,
2763 Sched<[WriteLDIdx, ReadAdrBase]> {
2767 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2768 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2769 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2770 [(set (Ty regtype:$Rt),
2771 (loadop (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2772 ro_Xextend64:$extend)))]>,
2773 Sched<[WriteLDIdx, ReadAdrBase]> {
2777 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2780 multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2781 string asm, ValueType Ty, SDPatternOperator storeop> {
2782 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2783 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2784 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2785 [(storeop (Ty regtype:$Rt),
2786 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2787 ro_Wextend64:$extend))]>,
2788 Sched<[WriteSTIdx, ReadAdrBase]> {
2792 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2793 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2794 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2795 [(storeop (Ty regtype:$Rt),
2796 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2797 ro_Xextend64:$extend))]>,
2798 Sched<[WriteSTIdx, ReadAdrBase]> {
2802 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2805 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2806 string asm, dag ins, dag outs, list<dag> pat>
2807 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2812 let Inst{31-30} = sz;
2813 let Inst{29-27} = 0b111;
2815 let Inst{25-24} = 0b00;
2816 let Inst{23-22} = opc;
2818 let Inst{20-16} = Rm;
2819 let Inst{15} = extend{1}; // sign extend Rm?
2821 let Inst{12} = extend{0}; // do shift?
2822 let Inst{11-10} = 0b10;
2827 multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2828 string asm, ValueType Ty, SDPatternOperator loadop> {
2829 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2830 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2831 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2832 [(set (Ty regtype:$Rt),
2833 (loadop (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2834 ro_Wextend128:$extend)))]>,
2835 Sched<[WriteLDIdx, ReadAdrBase]> {
2839 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2840 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2841 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2842 [(set (Ty regtype:$Rt),
2843 (loadop (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2844 ro_Xextend128:$extend)))]>,
2845 Sched<[WriteLDIdx, ReadAdrBase]> {
2849 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2852 multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2853 string asm, ValueType Ty, SDPatternOperator storeop> {
2854 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2855 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2856 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2857 [(storeop (Ty regtype:$Rt),
2858 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2859 ro_Wextend128:$extend))]>,
2860 Sched<[WriteSTIdx, ReadAdrBase]> {
2864 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2865 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2866 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2867 [(storeop (Ty regtype:$Rt),
2868 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2869 ro_Xextend128:$extend))]>,
2870 Sched<[WriteSTIdx, ReadAdrBase]> {
2874 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2877 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2878 class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
2879 string asm, list<dag> pat>
2880 : I<outs, ins, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat>,
2886 let Inst{31-30} = sz;
2887 let Inst{29-27} = 0b111;
2889 let Inst{25-24} = 0b00;
2890 let Inst{23-22} = opc;
2892 let Inst{20-16} = Rm;
2893 let Inst{15} = extend{1}; // sign extend Rm?
2895 let Inst{12} = extend{0}; // do shift?
2896 let Inst{11-10} = 0b10;
2901 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
2902 def roW : BasePrefetchRO<sz, V, opc, (outs),
2903 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2904 asm, [(AArch64Prefetch imm:$Rt,
2905 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2906 ro_Wextend64:$extend))]> {
2910 def roX : BasePrefetchRO<sz, V, opc, (outs),
2911 (ins prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2912 asm, [(AArch64Prefetch imm:$Rt,
2913 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2914 ro_Xextend64:$extend))]> {
2918 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
2919 (!cast<Instruction>(NAME # "roX") prfop:$Rt,
2920 GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2924 // Load/store unscaled immediate
2927 def am_unscaled8 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
2928 def am_unscaled16 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled16", []>;
2929 def am_unscaled32 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
2930 def am_unscaled64 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
2931 def am_unscaled128 :ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
2933 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2934 string asm, list<dag> pattern>
2935 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2939 let Inst{31-30} = sz;
2940 let Inst{29-27} = 0b111;
2942 let Inst{25-24} = 0b00;
2943 let Inst{23-22} = opc;
2945 let Inst{20-12} = offset;
2946 let Inst{11-10} = 0b00;
2950 let DecoderMethod = "DecodeSignedLdStInstruction";
2953 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2954 string asm, list<dag> pattern> {
2955 let AddedComplexity = 1 in // try this before LoadUI
2956 def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
2957 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
2960 def : InstAlias<asm # "\t$Rt, [$Rn]",
2961 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2964 multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2965 string asm, list<dag> pattern> {
2966 let AddedComplexity = 1 in // try this before StoreUI
2967 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2968 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2972 def : InstAlias<asm # "\t$Rt, [$Rn]",
2973 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2976 multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
2978 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2979 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2980 (ins prfop:$Rt, GPR64sp:$Rn, simm9:$offset),
2984 def : InstAlias<asm # "\t$Rt, [$Rn]",
2985 (!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>;
2989 // Load/store unscaled immediate, unprivileged
2992 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2993 dag oops, dag iops, string asm>
2994 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", []> {
2998 let Inst{31-30} = sz;
2999 let Inst{29-27} = 0b111;
3001 let Inst{25-24} = 0b00;
3002 let Inst{23-22} = opc;
3004 let Inst{20-12} = offset;
3005 let Inst{11-10} = 0b10;
3009 let DecoderMethod = "DecodeSignedLdStInstruction";
3012 multiclass LoadUnprivileged<bits<2> sz, bit V, bits<2> opc,
3013 RegisterClass regtype, string asm> {
3014 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in
3015 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs regtype:$Rt),
3016 (ins GPR64sp:$Rn, simm9:$offset), asm>,
3019 def : InstAlias<asm # "\t$Rt, [$Rn]",
3020 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
3023 multiclass StoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
3024 RegisterClass regtype, string asm> {
3025 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
3026 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs),
3027 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3031 def : InstAlias<asm # "\t$Rt, [$Rn]",
3032 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
3036 // Load/store pre-indexed
3039 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3040 string asm, string cstr, list<dag> pat>
3041 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]!", cstr, pat> {
3045 let Inst{31-30} = sz;
3046 let Inst{29-27} = 0b111;
3048 let Inst{25-24} = 0;
3049 let Inst{23-22} = opc;
3051 let Inst{20-12} = offset;
3052 let Inst{11-10} = 0b11;
3056 let DecoderMethod = "DecodeSignedLdStInstruction";
3059 let hasSideEffects = 0 in {
3060 let mayStore = 0, mayLoad = 1 in
3061 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3063 : BaseLoadStorePreIdx<sz, V, opc,
3064 (outs GPR64sp:$wback, regtype:$Rt),
3065 (ins GPR64sp:$Rn, simm9:$offset), asm,
3066 "$Rn = $wback,@earlyclobber $wback", []>,
3067 Sched<[WriteLD, WriteAdr]>;
3069 let mayStore = 1, mayLoad = 0 in
3070 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3071 string asm, SDPatternOperator storeop, ValueType Ty>
3072 : BaseLoadStorePreIdx<sz, V, opc,
3073 (outs GPR64sp:$wback),
3074 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3075 asm, "$Rn = $wback,@earlyclobber $wback",
3076 [(set GPR64sp:$wback,
3077 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3078 Sched<[WriteAdr, WriteST]>;
3079 } // hasSideEffects = 0
3082 // Load/store post-indexed
3085 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3086 string asm, string cstr, list<dag> pat>
3087 : I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
3091 let Inst{31-30} = sz;
3092 let Inst{29-27} = 0b111;
3094 let Inst{25-24} = 0b00;
3095 let Inst{23-22} = opc;
3097 let Inst{20-12} = offset;
3098 let Inst{11-10} = 0b01;
3102 let DecoderMethod = "DecodeSignedLdStInstruction";
3105 let hasSideEffects = 0 in {
3106 let mayStore = 0, mayLoad = 1 in
3107 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3109 : BaseLoadStorePostIdx<sz, V, opc,
3110 (outs GPR64sp:$wback, regtype:$Rt),
3111 (ins GPR64sp:$Rn, simm9:$offset),
3112 asm, "$Rn = $wback,@earlyclobber $wback", []>,
3113 Sched<[WriteLD, WriteI]>;
3115 let mayStore = 1, mayLoad = 0 in
3116 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3117 string asm, SDPatternOperator storeop, ValueType Ty>
3118 : BaseLoadStorePostIdx<sz, V, opc,
3119 (outs GPR64sp:$wback),
3120 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3121 asm, "$Rn = $wback,@earlyclobber $wback",
3122 [(set GPR64sp:$wback,
3123 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3124 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
3125 } // hasSideEffects = 0
3132 // (indexed, offset)
3134 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
3136 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3141 let Inst{31-30} = opc;
3142 let Inst{29-27} = 0b101;
3144 let Inst{25-23} = 0b010;
3146 let Inst{21-15} = offset;
3147 let Inst{14-10} = Rt2;
3151 let DecoderMethod = "DecodePairLdStInstruction";
3154 multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
3155 Operand indextype, string asm> {
3156 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3157 def i : BaseLoadStorePairOffset<opc, V, 1,
3158 (outs regtype:$Rt, regtype:$Rt2),
3159 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3160 Sched<[WriteLD, WriteLDHi]>;
3162 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3163 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3168 multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
3169 Operand indextype, string asm> {
3170 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
3171 def i : BaseLoadStorePairOffset<opc, V, 0, (outs),
3172 (ins regtype:$Rt, regtype:$Rt2,
3173 GPR64sp:$Rn, indextype:$offset),
3177 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3178 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3183 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3185 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
3190 let Inst{31-30} = opc;
3191 let Inst{29-27} = 0b101;
3193 let Inst{25-23} = 0b011;
3195 let Inst{21-15} = offset;
3196 let Inst{14-10} = Rt2;
3200 let DecoderMethod = "DecodePairLdStInstruction";
3203 let hasSideEffects = 0 in {
3204 let mayStore = 0, mayLoad = 1 in
3205 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3206 Operand indextype, string asm>
3207 : BaseLoadStorePairPreIdx<opc, V, 1,
3208 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3209 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3210 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3212 let mayStore = 1, mayLoad = 0 in
3213 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3214 Operand indextype, string asm>
3215 : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
3216 (ins regtype:$Rt, regtype:$Rt2,
3217 GPR64sp:$Rn, indextype:$offset),
3219 Sched<[WriteAdr, WriteSTP]>;
3220 } // hasSideEffects = 0
3224 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3226 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback,@earlyclobber $wback", []> {
3231 let Inst{31-30} = opc;
3232 let Inst{29-27} = 0b101;
3234 let Inst{25-23} = 0b001;
3236 let Inst{21-15} = offset;
3237 let Inst{14-10} = Rt2;
3241 let DecoderMethod = "DecodePairLdStInstruction";
3244 let hasSideEffects = 0 in {
3245 let mayStore = 0, mayLoad = 1 in
3246 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3247 Operand idxtype, string asm>
3248 : BaseLoadStorePairPostIdx<opc, V, 1,
3249 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3250 (ins GPR64sp:$Rn, idxtype:$offset), asm>,
3251 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3253 let mayStore = 1, mayLoad = 0 in
3254 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3255 Operand idxtype, string asm>
3256 : BaseLoadStorePairPostIdx<opc, V, 0, (outs GPR64sp:$wback),
3257 (ins regtype:$Rt, regtype:$Rt2,
3258 GPR64sp:$Rn, idxtype:$offset),
3260 Sched<[WriteAdr, WriteSTP]>;
3261 } // hasSideEffects = 0
3265 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
3267 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3272 let Inst{31-30} = opc;
3273 let Inst{29-27} = 0b101;
3275 let Inst{25-23} = 0b000;
3277 let Inst{21-15} = offset;
3278 let Inst{14-10} = Rt2;
3282 let DecoderMethod = "DecodePairLdStInstruction";
3285 multiclass LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3286 Operand indextype, string asm> {
3287 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3288 def i : BaseLoadStorePairNoAlloc<opc, V, 1,
3289 (outs regtype:$Rt, regtype:$Rt2),
3290 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3291 Sched<[WriteLD, WriteLDHi]>;
3294 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3295 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3299 multiclass StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3300 Operand indextype, string asm> {
3301 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in
3302 def i : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
3303 (ins regtype:$Rt, regtype:$Rt2,
3304 GPR64sp:$Rn, indextype:$offset),
3308 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3309 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3314 // Load/store exclusive
3317 // True exclusive operations write to and/or read from the system's exclusive
3318 // monitors, which as far as a compiler is concerned can be modelled as a
3319 // random shared memory address. Hence LoadExclusive mayStore.
3321 // Since these instructions have the undefined register bits set to 1 in
3322 // their canonical form, we need a post encoder method to set those bits
3323 // to 1 when encoding these instructions. We do this using the
3324 // fixLoadStoreExclusive function. This function has template parameters:
3326 // fixLoadStoreExclusive<int hasRs, int hasRt2>
3328 // hasRs indicates that the instruction uses the Rs field, so we won't set
3329 // it to 1 (and the same for Rt2). We don't need template parameters for
3330 // the other register fields since Rt and Rn are always used.
3332 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
3333 class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3334 dag oops, dag iops, string asm, string operands>
3335 : I<oops, iops, asm, operands, "", []> {
3336 let Inst{31-30} = sz;
3337 let Inst{29-24} = 0b001000;
3343 let DecoderMethod = "DecodeExclusiveLdStInstruction";
3346 // Neither Rs nor Rt2 operands.
3347 class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3348 dag oops, dag iops, string asm, string operands>
3349 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
3352 let Inst{20-16} = 0b11111;
3353 let Unpredictable{20-16} = 0b11111;
3354 let Inst{14-10} = 0b11111;
3355 let Unpredictable{14-10} = 0b11111;
3359 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
3362 // Simple load acquires don't set the exclusive monitor
3363 let mayLoad = 1, mayStore = 0 in
3364 class LoadAcquire<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3365 RegisterClass regtype, string asm>
3366 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3367 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3370 class LoadExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3371 RegisterClass regtype, string asm>
3372 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3373 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3376 class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3377 RegisterClass regtype, string asm>
3378 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3379 (outs regtype:$Rt, regtype:$Rt2),
3380 (ins GPR64sp0:$Rn), asm,
3381 "\t$Rt, $Rt2, [$Rn]">,
3382 Sched<[WriteLD, WriteLDHi]> {
3386 let Inst{14-10} = Rt2;
3390 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
3393 // Simple store release operations do not check the exclusive monitor.
3394 let mayLoad = 0, mayStore = 1 in
3395 class StoreRelease<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3396 RegisterClass regtype, string asm>
3397 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs),
3398 (ins regtype:$Rt, GPR64sp0:$Rn),
3399 asm, "\t$Rt, [$Rn]">,
3402 let mayLoad = 1, mayStore = 1 in
3403 class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3404 RegisterClass regtype, string asm>
3405 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
3406 (ins regtype:$Rt, GPR64sp0:$Rn),
3407 asm, "\t$Ws, $Rt, [$Rn]">,
3412 let Inst{20-16} = Ws;
3416 let Constraints = "@earlyclobber $Ws";
3417 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
3420 class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3421 RegisterClass regtype, string asm>
3422 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3424 (ins regtype:$Rt, regtype:$Rt2, GPR64sp0:$Rn),
3425 asm, "\t$Ws, $Rt, $Rt2, [$Rn]">,
3431 let Inst{20-16} = Ws;
3432 let Inst{14-10} = Rt2;
3436 let Constraints = "@earlyclobber $Ws";
3440 // Exception generation
3443 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3444 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
3445 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
3448 let Inst{31-24} = 0b11010100;
3449 let Inst{23-21} = op1;
3450 let Inst{20-5} = imm;
3451 let Inst{4-2} = 0b000;
3455 let Predicates = [HasFPARMv8] in {
3458 // Floating point to integer conversion
3461 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
3462 RegisterClass srcType, RegisterClass dstType,
3463 string asm, list<dag> pattern>
3464 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3465 asm, "\t$Rd, $Rn", "", pattern>,
3466 Sched<[WriteFCvt]> {
3469 let Inst{30-29} = 0b00;
3470 let Inst{28-24} = 0b11110;
3471 let Inst{23-22} = type;
3473 let Inst{20-19} = rmode;
3474 let Inst{18-16} = opcode;
3475 let Inst{15-10} = 0;
3480 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3481 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
3482 RegisterClass srcType, RegisterClass dstType,
3483 Operand immType, string asm, list<dag> pattern>
3484 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3485 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3486 Sched<[WriteFCvt]> {
3490 let Inst{30-29} = 0b00;
3491 let Inst{28-24} = 0b11110;
3492 let Inst{23-22} = type;
3494 let Inst{20-19} = rmode;
3495 let Inst{18-16} = opcode;
3496 let Inst{15-10} = scale;
3501 multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
3502 SDPatternOperator OpN> {
3503 // Unscaled single-precision to 32-bit
3504 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3505 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3506 let Inst{31} = 0; // 32-bit GPR flag
3509 // Unscaled single-precision to 64-bit
3510 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3511 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3512 let Inst{31} = 1; // 64-bit GPR flag
3515 // Unscaled double-precision to 32-bit
3516 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3517 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3518 let Inst{31} = 0; // 32-bit GPR flag
3521 // Unscaled double-precision to 64-bit
3522 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3523 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3524 let Inst{31} = 1; // 64-bit GPR flag
3528 multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
3529 SDPatternOperator OpN> {
3530 // Scaled single-precision to 32-bit
3531 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3532 fixedpoint_f32_i32, asm,
3533 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3534 fixedpoint_f32_i32:$scale)))]> {
3535 let Inst{31} = 0; // 32-bit GPR flag
3539 // Scaled single-precision to 64-bit
3540 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3541 fixedpoint_f32_i64, asm,
3542 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3543 fixedpoint_f32_i64:$scale)))]> {
3544 let Inst{31} = 1; // 64-bit GPR flag
3547 // Scaled double-precision to 32-bit
3548 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3549 fixedpoint_f64_i32, asm,
3550 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3551 fixedpoint_f64_i32:$scale)))]> {
3552 let Inst{31} = 0; // 32-bit GPR flag
3556 // Scaled double-precision to 64-bit
3557 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3558 fixedpoint_f64_i64, asm,
3559 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3560 fixedpoint_f64_i64:$scale)))]> {
3561 let Inst{31} = 1; // 64-bit GPR flag
3566 // Integer to floating point conversion
3569 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
3570 class BaseIntegerToFP<bit isUnsigned,
3571 RegisterClass srcType, RegisterClass dstType,
3572 Operand immType, string asm, list<dag> pattern>
3573 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3574 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3575 Sched<[WriteFCvt]> {
3579 let Inst{30-23} = 0b00111100;
3580 let Inst{21-17} = 0b00001;
3581 let Inst{16} = isUnsigned;
3582 let Inst{15-10} = scale;
3587 class BaseIntegerToFPUnscaled<bit isUnsigned,
3588 RegisterClass srcType, RegisterClass dstType,
3589 ValueType dvt, string asm, SDNode node>
3590 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3591 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3592 Sched<[WriteFCvt]> {
3596 let Inst{30-23} = 0b00111100;
3597 let Inst{21-17} = 0b10001;
3598 let Inst{16} = isUnsigned;
3599 let Inst{15-10} = 0b000000;
3604 multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
3606 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3607 let Inst{31} = 0; // 32-bit GPR flag
3608 let Inst{22} = 0; // 32-bit FPR flag
3611 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3612 let Inst{31} = 0; // 32-bit GPR flag
3613 let Inst{22} = 1; // 64-bit FPR flag
3616 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3617 let Inst{31} = 1; // 64-bit GPR flag
3618 let Inst{22} = 0; // 32-bit FPR flag
3621 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3622 let Inst{31} = 1; // 64-bit GPR flag
3623 let Inst{22} = 1; // 64-bit FPR flag
3627 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
3629 (fdiv (node GPR32:$Rn),
3630 fixedpoint_f32_i32:$scale))]> {
3631 let Inst{31} = 0; // 32-bit GPR flag
3632 let Inst{22} = 0; // 32-bit FPR flag
3636 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
3638 (fdiv (node GPR32:$Rn),
3639 fixedpoint_f64_i32:$scale))]> {
3640 let Inst{31} = 0; // 32-bit GPR flag
3641 let Inst{22} = 1; // 64-bit FPR flag
3645 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
3647 (fdiv (node GPR64:$Rn),
3648 fixedpoint_f32_i64:$scale))]> {
3649 let Inst{31} = 1; // 64-bit GPR flag
3650 let Inst{22} = 0; // 32-bit FPR flag
3653 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
3655 (fdiv (node GPR64:$Rn),
3656 fixedpoint_f64_i64:$scale))]> {
3657 let Inst{31} = 1; // 64-bit GPR flag
3658 let Inst{22} = 1; // 64-bit FPR flag
3663 // Unscaled integer <-> floating point conversion (i.e. FMOV)
3666 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3667 class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
3668 RegisterClass srcType, RegisterClass dstType,
3670 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3671 // We use COPY_TO_REGCLASS for these bitconvert operations.
3672 // copyPhysReg() expands the resultant COPY instructions after
3673 // regalloc is done. This gives greater freedom for the allocator
3674 // and related passes (coalescing, copy propagation, et. al.) to
3675 // be more effective.
3676 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3677 Sched<[WriteFCopy]> {
3680 let Inst{30-23} = 0b00111100;
3682 let Inst{20-19} = rmode;
3683 let Inst{18-16} = opcode;
3684 let Inst{15-10} = 0b000000;
3689 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3690 class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
3691 RegisterClass srcType, RegisterOperand dstType, string asm,
3693 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3694 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3695 Sched<[WriteFCopy]> {
3698 let Inst{30-23} = 0b00111101;
3700 let Inst{20-19} = rmode;
3701 let Inst{18-16} = opcode;
3702 let Inst{15-10} = 0b000000;
3706 let DecoderMethod = "DecodeFMOVLaneInstruction";
3709 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3710 class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
3711 RegisterOperand srcType, RegisterClass dstType, string asm,
3713 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3714 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3715 Sched<[WriteFCopy]> {
3718 let Inst{30-23} = 0b00111101;
3720 let Inst{20-19} = rmode;
3721 let Inst{18-16} = opcode;
3722 let Inst{15-10} = 0b000000;
3726 let DecoderMethod = "DecodeFMOVLaneInstruction";
3731 multiclass UnscaledConversion<string asm> {
3732 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3733 let Inst{31} = 0; // 32-bit GPR flag
3734 let Inst{22} = 0; // 32-bit FPR flag
3737 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3738 let Inst{31} = 1; // 64-bit GPR flag
3739 let Inst{22} = 1; // 64-bit FPR flag
3742 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3743 let Inst{31} = 0; // 32-bit GPR flag
3744 let Inst{22} = 0; // 32-bit FPR flag
3747 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3748 let Inst{31} = 1; // 64-bit GPR flag
3749 let Inst{22} = 1; // 64-bit FPR flag
3752 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3758 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3766 // Floating point conversion
3769 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
3770 RegisterClass srcType, string asm, list<dag> pattern>
3771 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3772 Sched<[WriteFCvt]> {
3775 let Inst{31-24} = 0b00011110;
3776 let Inst{23-22} = type;
3777 let Inst{21-17} = 0b10001;
3778 let Inst{16-15} = opcode;
3779 let Inst{14-10} = 0b10000;
3784 multiclass FPConversion<string asm> {
3785 // Double-precision to Half-precision
3786 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
3787 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3789 // Double-precision to Single-precision
3790 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3791 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3793 // Half-precision to Double-precision
3794 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
3795 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3797 // Half-precision to Single-precision
3798 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3799 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3801 // Single-precision to Double-precision
3802 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3803 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3805 // Single-precision to Half-precision
3806 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
3807 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3811 // Single operand floating point data processing
3814 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3815 class BaseSingleOperandFPData<bits<4> opcode, RegisterClass regtype,
3816 ValueType vt, string asm, SDPatternOperator node>
3817 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3818 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3822 let Inst{31-23} = 0b000111100;
3823 let Inst{21-19} = 0b100;
3824 let Inst{18-15} = opcode;
3825 let Inst{14-10} = 0b10000;
3830 multiclass SingleOperandFPData<bits<4> opcode, string asm,
3831 SDPatternOperator node = null_frag> {
3832 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
3833 let Inst{22} = 0; // 32-bit size flag
3836 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
3837 let Inst{22} = 1; // 64-bit size flag
3842 // Two operand floating point data processing
3845 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3846 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
3847 string asm, list<dag> pat>
3848 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3849 asm, "\t$Rd, $Rn, $Rm", "", pat>,
3854 let Inst{31-23} = 0b000111100;
3856 let Inst{20-16} = Rm;
3857 let Inst{15-12} = opcode;
3858 let Inst{11-10} = 0b10;
3863 multiclass TwoOperandFPData<bits<4> opcode, string asm,
3864 SDPatternOperator node = null_frag> {
3865 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3866 [(set (f32 FPR32:$Rd),
3867 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
3868 let Inst{22} = 0; // 32-bit size flag
3871 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3872 [(set (f64 FPR64:$Rd),
3873 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
3874 let Inst{22} = 1; // 64-bit size flag
3878 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm, SDNode node> {
3879 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3880 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
3881 let Inst{22} = 0; // 32-bit size flag
3884 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3885 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
3886 let Inst{22} = 1; // 64-bit size flag
3892 // Three operand floating point data processing
3895 class BaseThreeOperandFPData<bit isNegated, bit isSub,
3896 RegisterClass regtype, string asm, list<dag> pat>
3897 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
3898 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
3899 Sched<[WriteFMul]> {
3904 let Inst{31-23} = 0b000111110;
3905 let Inst{21} = isNegated;
3906 let Inst{20-16} = Rm;
3907 let Inst{15} = isSub;
3908 let Inst{14-10} = Ra;
3913 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
3914 SDPatternOperator node> {
3915 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
3917 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
3918 let Inst{22} = 0; // 32-bit size flag
3921 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
3923 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
3924 let Inst{22} = 1; // 64-bit size flag
3929 // Floating point data comparisons
3932 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3933 class BaseOneOperandFPComparison<bit signalAllNans,
3934 RegisterClass regtype, string asm,
3936 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
3937 Sched<[WriteFCmp]> {
3939 let Inst{31-23} = 0b000111100;
3942 let Inst{15-10} = 0b001000;
3944 let Inst{4} = signalAllNans;
3945 let Inst{3-0} = 0b1000;
3947 // Rm should be 0b00000 canonically, but we need to accept any value.
3948 let PostEncoderMethod = "fixOneOperandFPComparison";
3951 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3952 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
3953 string asm, list<dag> pat>
3954 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
3955 Sched<[WriteFCmp]> {
3958 let Inst{31-23} = 0b000111100;
3960 let Inst{20-16} = Rm;
3961 let Inst{15-10} = 0b001000;
3963 let Inst{4} = signalAllNans;
3964 let Inst{3-0} = 0b0000;
3967 multiclass FPComparison<bit signalAllNans, string asm,
3968 SDPatternOperator OpNode = null_frag> {
3969 let Defs = [NZCV] in {
3970 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
3971 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
3975 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
3976 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
3980 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
3981 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
3985 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
3986 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
3993 // Floating point conditional comparisons
3996 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3997 class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
3998 string mnemonic, list<dag> pat>
3999 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
4000 mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "", pat>,
4001 Sched<[WriteFCmp]> {
4010 let Inst{31-23} = 0b000111100;
4012 let Inst{20-16} = Rm;
4013 let Inst{15-12} = cond;
4014 let Inst{11-10} = 0b01;
4016 let Inst{4} = signalAllNans;
4017 let Inst{3-0} = nzcv;
4020 multiclass FPCondComparison<bit signalAllNans, string mnemonic,
4021 SDPatternOperator OpNode = null_frag> {
4022 def Srr : BaseFPCondComparison<signalAllNans, FPR32, mnemonic,
4023 [(set NZCV, (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm), (i32 imm:$nzcv),
4024 (i32 imm:$cond), NZCV))]> {
4027 def Drr : BaseFPCondComparison<signalAllNans, FPR64, mnemonic,
4028 [(set NZCV, (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm), (i32 imm:$nzcv),
4029 (i32 imm:$cond), NZCV))]> {
4035 // Floating point conditional select
4038 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
4039 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
4040 asm, "\t$Rd, $Rn, $Rm, $cond", "",
4042 (AArch64csel (vt regtype:$Rn), regtype:$Rm,
4043 (i32 imm:$cond), NZCV))]>,
4050 let Inst{31-23} = 0b000111100;
4052 let Inst{20-16} = Rm;
4053 let Inst{15-12} = cond;
4054 let Inst{11-10} = 0b11;
4059 multiclass FPCondSelect<string asm> {
4060 let Uses = [NZCV] in {
4061 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
4065 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
4072 // Floating move immediate
4075 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
4076 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
4077 [(set regtype:$Rd, fpimmtype:$imm)]>,
4078 Sched<[WriteFImm]> {
4081 let Inst{31-23} = 0b000111100;
4083 let Inst{20-13} = imm;
4084 let Inst{12-5} = 0b10000000;
4088 multiclass FPMoveImmediate<string asm> {
4089 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
4093 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
4097 } // end of 'let Predicates = [HasFPARMv8]'
4099 //----------------------------------------------------------------------------
4101 //----------------------------------------------------------------------------
4103 let Predicates = [HasNEON] in {
4105 //----------------------------------------------------------------------------
4106 // AdvSIMD three register vector instructions
4107 //----------------------------------------------------------------------------
4109 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4110 class BaseSIMDThreeSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4111 RegisterOperand regtype, string asm, string kind,
4113 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4114 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4115 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
4123 let Inst{28-24} = 0b01110;
4124 let Inst{23-22} = size;
4126 let Inst{20-16} = Rm;
4127 let Inst{15-11} = opcode;
4133 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4134 class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4135 RegisterOperand regtype, string asm, string kind,
4137 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4138 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4139 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4147 let Inst{28-24} = 0b01110;
4148 let Inst{23-22} = size;
4150 let Inst{20-16} = Rm;
4151 let Inst{15-11} = opcode;
4157 // All operand sizes distinguished in the encoding.
4158 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
4159 SDPatternOperator OpNode> {
4160 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4162 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4163 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4165 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4166 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4168 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4169 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4171 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4172 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4174 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4175 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4177 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4178 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b11, opc, V128,
4180 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4183 // As above, but D sized elements unsupported.
4184 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
4185 SDPatternOperator OpNode> {
4186 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4188 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4189 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4191 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4192 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4194 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4195 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4197 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4198 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4200 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4201 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4203 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4206 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
4207 SDPatternOperator OpNode> {
4208 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
4210 [(set (v8i8 V64:$dst),
4211 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4212 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
4214 [(set (v16i8 V128:$dst),
4215 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4216 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b01, opc, V64,
4218 [(set (v4i16 V64:$dst),
4219 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4220 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b01, opc, V128,
4222 [(set (v8i16 V128:$dst),
4223 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4224 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b10, opc, V64,
4226 [(set (v2i32 V64:$dst),
4227 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4228 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b10, opc, V128,
4230 [(set (v4i32 V128:$dst),
4231 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4234 // As above, but only B sized elements supported.
4235 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
4236 SDPatternOperator OpNode> {
4237 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4239 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4240 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4242 [(set (v16i8 V128:$Rd),
4243 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4246 // As above, but only S and D sized floating point elements supported.
4247 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<5> opc,
4248 string asm, SDPatternOperator OpNode> {
4249 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4251 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4252 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4254 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4255 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4257 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4260 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<5> opc,
4262 SDPatternOperator OpNode> {
4263 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4265 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4266 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4268 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4269 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4271 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4274 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<5> opc,
4275 string asm, SDPatternOperator OpNode> {
4276 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0}, opc, V64,
4278 [(set (v2f32 V64:$dst),
4279 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4280 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0}, opc, V128,
4282 [(set (v4f32 V128:$dst),
4283 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4284 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,1}, opc, V128,
4286 [(set (v2f64 V128:$dst),
4287 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4290 // As above, but D and B sized elements unsupported.
4291 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
4292 SDPatternOperator OpNode> {
4293 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4295 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4296 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4298 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4299 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4301 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4302 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4304 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4307 // Logical three vector ops share opcode bits, and only use B sized elements.
4308 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
4309 SDPatternOperator OpNode = null_frag> {
4310 def v8i8 : BaseSIMDThreeSameVector<0, U, size, 0b00011, V64,
4312 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4313 def v16i8 : BaseSIMDThreeSameVector<1, U, size, 0b00011, V128,
4315 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4317 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
4318 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4319 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
4320 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4321 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
4322 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4324 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
4325 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4326 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
4327 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4328 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
4329 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4332 multiclass SIMDLogicalThreeVectorTied<bit U, bits<2> size,
4333 string asm, SDPatternOperator OpNode> {
4334 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, size, 0b00011, V64,
4336 [(set (v8i8 V64:$dst),
4337 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4338 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, size, 0b00011, V128,
4340 [(set (v16i8 V128:$dst),
4341 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4342 (v16i8 V128:$Rm)))]>;
4344 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
4346 (!cast<Instruction>(NAME#"v8i8")
4347 V64:$LHS, V64:$MHS, V64:$RHS)>;
4348 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
4350 (!cast<Instruction>(NAME#"v8i8")
4351 V64:$LHS, V64:$MHS, V64:$RHS)>;
4352 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
4354 (!cast<Instruction>(NAME#"v8i8")
4355 V64:$LHS, V64:$MHS, V64:$RHS)>;
4357 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
4358 (v8i16 V128:$RHS))),
4359 (!cast<Instruction>(NAME#"v16i8")
4360 V128:$LHS, V128:$MHS, V128:$RHS)>;
4361 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
4362 (v4i32 V128:$RHS))),
4363 (!cast<Instruction>(NAME#"v16i8")
4364 V128:$LHS, V128:$MHS, V128:$RHS)>;
4365 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
4366 (v2i64 V128:$RHS))),
4367 (!cast<Instruction>(NAME#"v16i8")
4368 V128:$LHS, V128:$MHS, V128:$RHS)>;
4372 //----------------------------------------------------------------------------
4373 // AdvSIMD two register vector instructions.
4374 //----------------------------------------------------------------------------
4376 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4377 class BaseSIMDTwoSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4378 RegisterOperand regtype, string asm, string dstkind,
4379 string srckind, list<dag> pattern>
4380 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4381 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4382 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4389 let Inst{28-24} = 0b01110;
4390 let Inst{23-22} = size;
4391 let Inst{21-17} = 0b10000;
4392 let Inst{16-12} = opcode;
4393 let Inst{11-10} = 0b10;
4398 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4399 class BaseSIMDTwoSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4400 RegisterOperand regtype, string asm, string dstkind,
4401 string srckind, list<dag> pattern>
4402 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4403 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4404 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4411 let Inst{28-24} = 0b01110;
4412 let Inst{23-22} = size;
4413 let Inst{21-17} = 0b10000;
4414 let Inst{16-12} = opcode;
4415 let Inst{11-10} = 0b10;
4420 // Supports B, H, and S element sizes.
4421 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
4422 SDPatternOperator OpNode> {
4423 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4425 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4426 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4427 asm, ".16b", ".16b",
4428 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4429 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4431 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4432 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4434 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4435 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4437 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4438 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4440 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4443 class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size,
4444 RegisterOperand regtype, string asm, string dstkind,
4445 string srckind, string amount>
4446 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4447 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4448 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4454 let Inst{29-24} = 0b101110;
4455 let Inst{23-22} = size;
4456 let Inst{21-10} = 0b100001001110;
4461 multiclass SIMDVectorLShiftLongBySizeBHS {
4462 let hasSideEffects = 0 in {
4463 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4464 "shll", ".8h", ".8b", "8">;
4465 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4466 "shll2", ".8h", ".16b", "8">;
4467 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4468 "shll", ".4s", ".4h", "16">;
4469 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4470 "shll2", ".4s", ".8h", "16">;
4471 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
4472 "shll", ".2d", ".2s", "32">;
4473 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4474 "shll2", ".2d", ".4s", "32">;
4478 // Supports all element sizes.
4479 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4480 SDPatternOperator OpNode> {
4481 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4483 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4484 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4486 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4487 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4489 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4490 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4492 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4493 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4495 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4496 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4498 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4501 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4502 SDPatternOperator OpNode> {
4503 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4505 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4507 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4509 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4510 (v16i8 V128:$Rn)))]>;
4511 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4513 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4514 (v4i16 V64:$Rn)))]>;
4515 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4517 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4518 (v8i16 V128:$Rn)))]>;
4519 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4521 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4522 (v2i32 V64:$Rn)))]>;
4523 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4525 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4526 (v4i32 V128:$Rn)))]>;
4529 // Supports all element sizes, except 1xD.
4530 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4531 SDPatternOperator OpNode> {
4532 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4534 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4535 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4536 asm, ".16b", ".16b",
4537 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4538 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4540 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4541 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4543 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4544 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4546 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4547 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4549 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4550 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, V128,
4552 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4555 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4556 SDPatternOperator OpNode = null_frag> {
4557 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4559 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4560 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4561 asm, ".16b", ".16b",
4562 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4563 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4565 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4566 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4568 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4569 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4571 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4572 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4574 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4575 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, V128,
4577 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4581 // Supports only B element sizes.
4582 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4583 SDPatternOperator OpNode> {
4584 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, V64,
4586 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4587 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, V128,
4588 asm, ".16b", ".16b",
4589 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4593 // Supports only B and H element sizes.
4594 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4595 SDPatternOperator OpNode> {
4596 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4598 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4599 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4600 asm, ".16b", ".16b",
4601 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4602 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4604 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4605 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4607 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4610 // Supports only S and D element sizes, uses high bit of the size field
4611 // as an extra opcode bit.
4612 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4613 SDPatternOperator OpNode> {
4614 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4616 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4617 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4619 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4620 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4622 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4625 // Supports only S element size.
4626 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4627 SDPatternOperator OpNode> {
4628 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4630 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4631 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4633 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4637 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4638 SDPatternOperator OpNode> {
4639 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4641 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4642 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4644 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4645 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4647 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4650 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4651 SDPatternOperator OpNode> {
4652 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4654 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4655 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4657 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4658 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4660 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4664 class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4665 RegisterOperand inreg, RegisterOperand outreg,
4666 string asm, string outkind, string inkind,
4668 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4669 "{\t$Rd" # outkind # ", $Rn" # inkind #
4670 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4677 let Inst{28-24} = 0b01110;
4678 let Inst{23-22} = size;
4679 let Inst{21-17} = 0b10000;
4680 let Inst{16-12} = opcode;
4681 let Inst{11-10} = 0b10;
4686 class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4687 RegisterOperand inreg, RegisterOperand outreg,
4688 string asm, string outkind, string inkind,
4690 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4691 "{\t$Rd" # outkind # ", $Rn" # inkind #
4692 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4699 let Inst{28-24} = 0b01110;
4700 let Inst{23-22} = size;
4701 let Inst{21-17} = 0b10000;
4702 let Inst{16-12} = opcode;
4703 let Inst{11-10} = 0b10;
4708 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4709 SDPatternOperator OpNode> {
4710 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4712 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4713 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4714 asm#"2", ".16b", ".8h", []>;
4715 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4717 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4718 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4719 asm#"2", ".8h", ".4s", []>;
4720 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4722 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4723 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4724 asm#"2", ".4s", ".2d", []>;
4726 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4727 (!cast<Instruction>(NAME # "v16i8")
4728 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4729 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4730 (!cast<Instruction>(NAME # "v8i16")
4731 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4732 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4733 (!cast<Instruction>(NAME # "v4i32")
4734 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4737 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4738 RegisterOperand regtype,
4739 string asm, string kind, string zero,
4740 ValueType dty, ValueType sty, SDNode OpNode>
4741 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4742 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
4743 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
4744 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4751 let Inst{28-24} = 0b01110;
4752 let Inst{23-22} = size;
4753 let Inst{21-17} = 0b10000;
4754 let Inst{16-12} = opcode;
4755 let Inst{11-10} = 0b10;
4760 // Comparisons support all element sizes, except 1xD.
4761 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
4763 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4765 v8i8, v8i8, OpNode>;
4766 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4768 v16i8, v16i8, OpNode>;
4769 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
4771 v4i16, v4i16, OpNode>;
4772 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
4774 v8i16, v8i16, OpNode>;
4775 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
4777 v2i32, v2i32, OpNode>;
4778 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
4780 v4i32, v4i32, OpNode>;
4781 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
4783 v2i64, v2i64, OpNode>;
4786 // FP Comparisons support only S and D element sizes.
4787 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
4788 string asm, SDNode OpNode> {
4790 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
4792 v2i32, v2f32, OpNode>;
4793 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
4795 v4i32, v4f32, OpNode>;
4796 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
4798 v2i64, v2f64, OpNode>;
4800 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
4801 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4802 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
4803 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4804 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
4805 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4806 def : InstAlias<asm # ".2s\t$Vd, $Vn, #0",
4807 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4808 def : InstAlias<asm # ".4s\t$Vd, $Vn, #0",
4809 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4810 def : InstAlias<asm # ".2d\t$Vd, $Vn, #0",
4811 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4814 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4815 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4816 RegisterOperand outtype, RegisterOperand intype,
4817 string asm, string VdTy, string VnTy,
4819 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
4820 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
4827 let Inst{28-24} = 0b01110;
4828 let Inst{23-22} = size;
4829 let Inst{21-17} = 0b10000;
4830 let Inst{16-12} = opcode;
4831 let Inst{11-10} = 0b10;
4836 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4837 RegisterOperand outtype, RegisterOperand intype,
4838 string asm, string VdTy, string VnTy,
4840 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
4841 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
4848 let Inst{28-24} = 0b01110;
4849 let Inst{23-22} = size;
4850 let Inst{21-17} = 0b10000;
4851 let Inst{16-12} = opcode;
4852 let Inst{11-10} = 0b10;
4857 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
4858 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
4859 asm, ".4s", ".4h", []>;
4860 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
4861 asm#"2", ".4s", ".8h", []>;
4862 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
4863 asm, ".2d", ".2s", []>;
4864 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
4865 asm#"2", ".2d", ".4s", []>;
4868 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
4869 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
4870 asm, ".4h", ".4s", []>;
4871 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
4872 asm#"2", ".8h", ".4s", []>;
4873 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4874 asm, ".2s", ".2d", []>;
4875 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4876 asm#"2", ".4s", ".2d", []>;
4879 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
4881 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4883 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4884 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4885 asm#"2", ".4s", ".2d", []>;
4887 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
4888 (!cast<Instruction>(NAME # "v4f32")
4889 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4892 //----------------------------------------------------------------------------
4893 // AdvSIMD three register different-size vector instructions.
4894 //----------------------------------------------------------------------------
4896 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4897 class BaseSIMDDifferentThreeVector<bit U, bits<3> size, bits<4> opcode,
4898 RegisterOperand outtype, RegisterOperand intype1,
4899 RegisterOperand intype2, string asm,
4900 string outkind, string inkind1, string inkind2,
4902 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
4903 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4904 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
4910 let Inst{30} = size{0};
4912 let Inst{28-24} = 0b01110;
4913 let Inst{23-22} = size{2-1};
4915 let Inst{20-16} = Rm;
4916 let Inst{15-12} = opcode;
4917 let Inst{11-10} = 0b00;
4922 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4923 class BaseSIMDDifferentThreeVectorTied<bit U, bits<3> size, bits<4> opcode,
4924 RegisterOperand outtype, RegisterOperand intype1,
4925 RegisterOperand intype2, string asm,
4926 string outkind, string inkind1, string inkind2,
4928 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
4929 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4930 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4936 let Inst{30} = size{0};
4938 let Inst{28-24} = 0b01110;
4939 let Inst{23-22} = size{2-1};
4941 let Inst{20-16} = Rm;
4942 let Inst{15-12} = opcode;
4943 let Inst{11-10} = 0b00;
4948 // FIXME: TableGen doesn't know how to deal with expanded types that also
4949 // change the element count (in this case, placing the results in
4950 // the high elements of the result register rather than the low
4951 // elements). Until that's fixed, we can't code-gen those.
4952 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
4954 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4956 asm, ".8b", ".8h", ".8h",
4957 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4958 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4960 asm#"2", ".16b", ".8h", ".8h",
4962 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4964 asm, ".4h", ".4s", ".4s",
4965 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4966 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4968 asm#"2", ".8h", ".4s", ".4s",
4970 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4972 asm, ".2s", ".2d", ".2d",
4973 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4974 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4976 asm#"2", ".4s", ".2d", ".2d",
4980 // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in
4981 // a version attached to an instruction.
4982 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
4984 (!cast<Instruction>(NAME # "v8i16_v16i8")
4985 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4986 V128:$Rn, V128:$Rm)>;
4987 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
4989 (!cast<Instruction>(NAME # "v4i32_v8i16")
4990 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4991 V128:$Rn, V128:$Rm)>;
4992 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
4994 (!cast<Instruction>(NAME # "v2i64_v4i32")
4995 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4996 V128:$Rn, V128:$Rm)>;
4999 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
5001 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5003 asm, ".8h", ".8b", ".8b",
5004 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5005 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5007 asm#"2", ".8h", ".16b", ".16b", []>;
5008 let Predicates = [HasCrypto] in {
5009 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
5011 asm, ".1q", ".1d", ".1d", []>;
5012 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
5014 asm#"2", ".1q", ".2d", ".2d", []>;
5017 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
5018 (v8i8 (extract_high_v16i8 V128:$Rm)))),
5019 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
5022 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
5023 SDPatternOperator OpNode> {
5024 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5026 asm, ".4s", ".4h", ".4h",
5027 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5028 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5030 asm#"2", ".4s", ".8h", ".8h",
5031 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5032 (extract_high_v8i16 V128:$Rm)))]>;
5033 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5035 asm, ".2d", ".2s", ".2s",
5036 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5037 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5039 asm#"2", ".2d", ".4s", ".4s",
5040 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5041 (extract_high_v4i32 V128:$Rm)))]>;
5044 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
5045 SDPatternOperator OpNode = null_frag> {
5046 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5048 asm, ".8h", ".8b", ".8b",
5049 [(set (v8i16 V128:$Rd),
5050 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
5051 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5053 asm#"2", ".8h", ".16b", ".16b",
5054 [(set (v8i16 V128:$Rd),
5055 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5056 (extract_high_v16i8 V128:$Rm)))))]>;
5057 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5059 asm, ".4s", ".4h", ".4h",
5060 [(set (v4i32 V128:$Rd),
5061 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
5062 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5064 asm#"2", ".4s", ".8h", ".8h",
5065 [(set (v4i32 V128:$Rd),
5066 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5067 (extract_high_v8i16 V128:$Rm)))))]>;
5068 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5070 asm, ".2d", ".2s", ".2s",
5071 [(set (v2i64 V128:$Rd),
5072 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
5073 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5075 asm#"2", ".2d", ".4s", ".4s",
5076 [(set (v2i64 V128:$Rd),
5077 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5078 (extract_high_v4i32 V128:$Rm)))))]>;
5081 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
5083 SDPatternOperator OpNode> {
5084 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5086 asm, ".8h", ".8b", ".8b",
5087 [(set (v8i16 V128:$dst),
5088 (add (v8i16 V128:$Rd),
5089 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
5090 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5092 asm#"2", ".8h", ".16b", ".16b",
5093 [(set (v8i16 V128:$dst),
5094 (add (v8i16 V128:$Rd),
5095 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5096 (extract_high_v16i8 V128:$Rm))))))]>;
5097 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5099 asm, ".4s", ".4h", ".4h",
5100 [(set (v4i32 V128:$dst),
5101 (add (v4i32 V128:$Rd),
5102 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
5103 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5105 asm#"2", ".4s", ".8h", ".8h",
5106 [(set (v4i32 V128:$dst),
5107 (add (v4i32 V128:$Rd),
5108 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5109 (extract_high_v8i16 V128:$Rm))))))]>;
5110 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5112 asm, ".2d", ".2s", ".2s",
5113 [(set (v2i64 V128:$dst),
5114 (add (v2i64 V128:$Rd),
5115 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
5116 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5118 asm#"2", ".2d", ".4s", ".4s",
5119 [(set (v2i64 V128:$dst),
5120 (add (v2i64 V128:$Rd),
5121 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5122 (extract_high_v4i32 V128:$Rm))))))]>;
5125 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
5126 SDPatternOperator OpNode = null_frag> {
5127 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5129 asm, ".8h", ".8b", ".8b",
5130 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5131 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5133 asm#"2", ".8h", ".16b", ".16b",
5134 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5135 (extract_high_v16i8 V128:$Rm)))]>;
5136 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5138 asm, ".4s", ".4h", ".4h",
5139 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5140 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5142 asm#"2", ".4s", ".8h", ".8h",
5143 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5144 (extract_high_v8i16 V128:$Rm)))]>;
5145 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5147 asm, ".2d", ".2s", ".2s",
5148 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5149 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5151 asm#"2", ".2d", ".4s", ".4s",
5152 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5153 (extract_high_v4i32 V128:$Rm)))]>;
5156 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
5158 SDPatternOperator OpNode> {
5159 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5161 asm, ".8h", ".8b", ".8b",
5162 [(set (v8i16 V128:$dst),
5163 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5164 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5166 asm#"2", ".8h", ".16b", ".16b",
5167 [(set (v8i16 V128:$dst),
5168 (OpNode (v8i16 V128:$Rd),
5169 (extract_high_v16i8 V128:$Rn),
5170 (extract_high_v16i8 V128:$Rm)))]>;
5171 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5173 asm, ".4s", ".4h", ".4h",
5174 [(set (v4i32 V128:$dst),
5175 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5176 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5178 asm#"2", ".4s", ".8h", ".8h",
5179 [(set (v4i32 V128:$dst),
5180 (OpNode (v4i32 V128:$Rd),
5181 (extract_high_v8i16 V128:$Rn),
5182 (extract_high_v8i16 V128:$Rm)))]>;
5183 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5185 asm, ".2d", ".2s", ".2s",
5186 [(set (v2i64 V128:$dst),
5187 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5188 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5190 asm#"2", ".2d", ".4s", ".4s",
5191 [(set (v2i64 V128:$dst),
5192 (OpNode (v2i64 V128:$Rd),
5193 (extract_high_v4i32 V128:$Rn),
5194 (extract_high_v4i32 V128:$Rm)))]>;
5197 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
5198 SDPatternOperator Accum> {
5199 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5201 asm, ".4s", ".4h", ".4h",
5202 [(set (v4i32 V128:$dst),
5203 (Accum (v4i32 V128:$Rd),
5204 (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
5205 (v4i16 V64:$Rm)))))]>;
5206 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5208 asm#"2", ".4s", ".8h", ".8h",
5209 [(set (v4i32 V128:$dst),
5210 (Accum (v4i32 V128:$Rd),
5211 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
5212 (extract_high_v8i16 V128:$Rm)))))]>;
5213 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5215 asm, ".2d", ".2s", ".2s",
5216 [(set (v2i64 V128:$dst),
5217 (Accum (v2i64 V128:$Rd),
5218 (v2i64 (int_aarch64_neon_sqdmull (v2i32 V64:$Rn),
5219 (v2i32 V64:$Rm)))))]>;
5220 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5222 asm#"2", ".2d", ".4s", ".4s",
5223 [(set (v2i64 V128:$dst),
5224 (Accum (v2i64 V128:$Rd),
5225 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
5226 (extract_high_v4i32 V128:$Rm)))))]>;
5229 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
5230 SDPatternOperator OpNode> {
5231 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5233 asm, ".8h", ".8h", ".8b",
5234 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5235 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5237 asm#"2", ".8h", ".8h", ".16b",
5238 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5239 (extract_high_v16i8 V128:$Rm)))]>;
5240 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5242 asm, ".4s", ".4s", ".4h",
5243 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5244 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5246 asm#"2", ".4s", ".4s", ".8h",
5247 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5248 (extract_high_v8i16 V128:$Rm)))]>;
5249 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5251 asm, ".2d", ".2d", ".2s",
5252 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5253 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5255 asm#"2", ".2d", ".2d", ".4s",
5256 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5257 (extract_high_v4i32 V128:$Rm)))]>;
5260 //----------------------------------------------------------------------------
5261 // AdvSIMD bitwise extract from vector
5262 //----------------------------------------------------------------------------
5264 class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
5265 string asm, string kind>
5266 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5267 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5268 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5269 [(set (vty regtype:$Rd),
5270 (AArch64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
5277 let Inst{30} = size;
5278 let Inst{29-21} = 0b101110000;
5279 let Inst{20-16} = Rm;
5281 let Inst{14-11} = imm;
5288 multiclass SIMDBitwiseExtract<string asm> {
5289 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
5292 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
5295 //----------------------------------------------------------------------------
5296 // AdvSIMD zip vector
5297 //----------------------------------------------------------------------------
5299 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
5300 string asm, string kind, SDNode OpNode, ValueType valty>
5301 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5302 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5303 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5304 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5310 let Inst{30} = size{0};
5311 let Inst{29-24} = 0b001110;
5312 let Inst{23-22} = size{2-1};
5314 let Inst{20-16} = Rm;
5316 let Inst{14-12} = opc;
5317 let Inst{11-10} = 0b10;
5322 multiclass SIMDZipVector<bits<3>opc, string asm,
5324 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
5325 asm, ".8b", OpNode, v8i8>;
5326 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5327 asm, ".16b", OpNode, v16i8>;
5328 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
5329 asm, ".4h", OpNode, v4i16>;
5330 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5331 asm, ".8h", OpNode, v8i16>;
5332 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
5333 asm, ".2s", OpNode, v2i32>;
5334 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5335 asm, ".4s", OpNode, v4i32>;
5336 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5337 asm, ".2d", OpNode, v2i64>;
5339 def : Pat<(v4f16 (OpNode V64:$Rn, V64:$Rm)),
5340 (!cast<Instruction>(NAME#"v4i16") V64:$Rn, V64:$Rm)>;
5341 def : Pat<(v8f16 (OpNode V128:$Rn, V128:$Rm)),
5342 (!cast<Instruction>(NAME#"v8i16") V128:$Rn, V128:$Rm)>;
5343 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
5344 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
5345 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5346 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5347 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5348 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
5351 //----------------------------------------------------------------------------
5352 // AdvSIMD three register scalar instructions
5353 //----------------------------------------------------------------------------
5355 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5356 class BaseSIMDThreeScalar<bit U, bits<2> size, bits<5> opcode,
5357 RegisterClass regtype, string asm,
5359 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5360 "\t$Rd, $Rn, $Rm", "", pattern>,
5365 let Inst{31-30} = 0b01;
5367 let Inst{28-24} = 0b11110;
5368 let Inst{23-22} = size;
5370 let Inst{20-16} = Rm;
5371 let Inst{15-11} = opcode;
5377 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5378 class BaseSIMDThreeScalarTied<bit U, bits<2> size, bit R, bits<5> opcode,
5379 dag oops, dag iops, string asm,
5381 : I<oops, iops, asm, "\t$Rd, $Rn, $Rm", "$Rd = $dst", pattern>,
5386 let Inst{31-30} = 0b01;
5388 let Inst{28-24} = 0b11110;
5389 let Inst{23-22} = size;
5391 let Inst{20-16} = Rm;
5392 let Inst{15-11} = opcode;
5398 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
5399 SDPatternOperator OpNode> {
5400 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5401 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5404 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
5405 SDPatternOperator OpNode> {
5406 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5407 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5408 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
5409 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5410 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5412 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5413 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
5414 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
5415 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5418 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
5419 SDPatternOperator OpNode> {
5420 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
5421 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5422 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5425 multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm,
5426 SDPatternOperator OpNode = null_frag> {
5427 def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst),
5428 (ins FPR32:$Rd, FPR32:$Rn, FPR32:$Rm),
5430 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
5431 (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
5435 multiclass SIMDThreeScalarSD<bit U, bit S, bits<5> opc, string asm,
5436 SDPatternOperator OpNode = null_frag> {
5437 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5438 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5439 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5440 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5441 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5444 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5445 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5448 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<5> opc, string asm,
5449 SDPatternOperator OpNode = null_frag> {
5450 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5451 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5452 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5453 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5454 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5457 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5458 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5461 class BaseSIMDThreeScalarMixed<bit U, bits<2> size, bits<5> opcode,
5462 dag oops, dag iops, string asm, string cstr, list<dag> pat>
5463 : I<oops, iops, asm,
5464 "\t$Rd, $Rn, $Rm", cstr, pat>,
5469 let Inst{31-30} = 0b01;
5471 let Inst{28-24} = 0b11110;
5472 let Inst{23-22} = size;
5474 let Inst{20-16} = Rm;
5475 let Inst{15-11} = opcode;
5481 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5482 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
5483 SDPatternOperator OpNode = null_frag> {
5484 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5486 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
5487 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5489 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
5490 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5493 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5494 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
5495 SDPatternOperator OpNode = null_frag> {
5496 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5498 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5499 asm, "$Rd = $dst", []>;
5500 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5502 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5504 [(set (i64 FPR64:$dst),
5505 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5508 //----------------------------------------------------------------------------
5509 // AdvSIMD two register scalar instructions
5510 //----------------------------------------------------------------------------
5512 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5513 class BaseSIMDTwoScalar<bit U, bits<2> size, bits<5> opcode,
5514 RegisterClass regtype, RegisterClass regtype2,
5515 string asm, list<dag> pat>
5516 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5517 "\t$Rd, $Rn", "", pat>,
5521 let Inst{31-30} = 0b01;
5523 let Inst{28-24} = 0b11110;
5524 let Inst{23-22} = size;
5525 let Inst{21-17} = 0b10000;
5526 let Inst{16-12} = opcode;
5527 let Inst{11-10} = 0b10;
5532 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5533 class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
5534 RegisterClass regtype, RegisterClass regtype2,
5535 string asm, list<dag> pat>
5536 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5537 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5541 let Inst{31-30} = 0b01;
5543 let Inst{28-24} = 0b11110;
5544 let Inst{23-22} = size;
5545 let Inst{21-17} = 0b10000;
5546 let Inst{16-12} = opcode;
5547 let Inst{11-10} = 0b10;
5553 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5554 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
5555 RegisterClass regtype, string asm, string zero>
5556 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5557 "\t$Rd, $Rn, #" # zero, "", []>,
5561 let Inst{31-30} = 0b01;
5563 let Inst{28-24} = 0b11110;
5564 let Inst{23-22} = size;
5565 let Inst{21-17} = 0b10000;
5566 let Inst{16-12} = opcode;
5567 let Inst{11-10} = 0b10;
5572 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
5573 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5574 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5578 let Inst{31-17} = 0b011111100110000;
5579 let Inst{16-12} = opcode;
5580 let Inst{11-10} = 0b10;
5585 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5586 SDPatternOperator OpNode> {
5587 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
5589 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5590 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5593 multiclass SIMDFPCmpTwoScalar<bit U, bit S, bits<5> opc, string asm,
5594 SDPatternOperator OpNode> {
5595 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
5596 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
5598 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5599 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5600 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5601 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5603 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5604 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5607 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5608 SDPatternOperator OpNode = null_frag> {
5609 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5610 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5612 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5613 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5616 multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm> {
5617 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,[]>;
5618 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5621 multiclass SIMDTwoScalarCVTSD<bit U, bit S, bits<5> opc, string asm,
5622 SDPatternOperator OpNode> {
5623 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,
5624 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5625 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5626 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5629 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5630 SDPatternOperator OpNode = null_frag> {
5631 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5632 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5633 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5634 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5635 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5636 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5637 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5640 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5641 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5644 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5646 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5647 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5648 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5649 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5650 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5651 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5652 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5655 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5656 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5661 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5662 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5663 SDPatternOperator OpNode = null_frag> {
5664 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
5665 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5666 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
5667 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5670 //----------------------------------------------------------------------------
5671 // AdvSIMD scalar pairwise instructions
5672 //----------------------------------------------------------------------------
5674 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5675 class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
5676 RegisterOperand regtype, RegisterOperand vectype,
5677 string asm, string kind>
5678 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5679 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5683 let Inst{31-30} = 0b01;
5685 let Inst{28-24} = 0b11110;
5686 let Inst{23-22} = size;
5687 let Inst{21-17} = 0b11000;
5688 let Inst{16-12} = opcode;
5689 let Inst{11-10} = 0b10;
5694 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
5695 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
5699 multiclass SIMDFPPairwiseScalar<bit U, bit S, bits<5> opc, string asm> {
5700 def v2i32p : BaseSIMDPairwiseScalar<U, {S,0}, opc, FPR32Op, V64,
5702 def v2i64p : BaseSIMDPairwiseScalar<U, {S,1}, opc, FPR64Op, V128,
5706 //----------------------------------------------------------------------------
5707 // AdvSIMD across lanes instructions
5708 //----------------------------------------------------------------------------
5710 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5711 class BaseSIMDAcrossLanes<bit Q, bit U, bits<2> size, bits<5> opcode,
5712 RegisterClass regtype, RegisterOperand vectype,
5713 string asm, string kind, list<dag> pattern>
5714 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5715 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5722 let Inst{28-24} = 0b01110;
5723 let Inst{23-22} = size;
5724 let Inst{21-17} = 0b11000;
5725 let Inst{16-12} = opcode;
5726 let Inst{11-10} = 0b10;
5731 multiclass SIMDAcrossLanesBHS<bit U, bits<5> opcode,
5733 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5735 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5737 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
5739 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
5741 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
5745 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
5746 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5748 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5750 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
5752 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
5754 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
5758 multiclass SIMDAcrossLanesS<bits<5> opcode, bit sz1, string asm,
5760 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
5762 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5765 //----------------------------------------------------------------------------
5766 // AdvSIMD INS/DUP instructions
5767 //----------------------------------------------------------------------------
5769 // FIXME: There has got to be a better way to factor these. ugh.
5771 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
5772 string operands, string constraints, list<dag> pattern>
5773 : I<outs, ins, asm, operands, constraints, pattern>,
5780 let Inst{28-21} = 0b01110000;
5787 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5788 RegisterOperand vecreg, RegisterClass regtype>
5789 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5790 "{\t$Rd" # size # ", $Rn" #
5791 "|" # size # "\t$Rd, $Rn}", "",
5792 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
5793 let Inst{20-16} = imm5;
5794 let Inst{14-11} = 0b0001;
5797 class SIMDDupFromElement<bit Q, string dstkind, string srckind,
5798 ValueType vectype, ValueType insreg,
5799 RegisterOperand vecreg, Operand idxtype,
5800 ValueType elttype, SDNode OpNode>
5801 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
5802 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
5803 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
5804 [(set (vectype vecreg:$Rd),
5805 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
5806 let Inst{14-11} = 0b0000;
5809 class SIMDDup64FromElement
5810 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
5811 VectorIndexD, i64, AArch64duplane64> {
5814 let Inst{19-16} = 0b1000;
5817 class SIMDDup32FromElement<bit Q, string size, ValueType vectype,
5818 RegisterOperand vecreg>
5819 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
5820 VectorIndexS, i64, AArch64duplane32> {
5822 let Inst{20-19} = idx;
5823 let Inst{18-16} = 0b100;
5826 class SIMDDup16FromElement<bit Q, string size, ValueType vectype,
5827 RegisterOperand vecreg>
5828 : SIMDDupFromElement<Q, size, ".h", vectype, v8i16, vecreg,
5829 VectorIndexH, i64, AArch64duplane16> {
5831 let Inst{20-18} = idx;
5832 let Inst{17-16} = 0b10;
5835 class SIMDDup8FromElement<bit Q, string size, ValueType vectype,
5836 RegisterOperand vecreg>
5837 : SIMDDupFromElement<Q, size, ".b", vectype, v16i8, vecreg,
5838 VectorIndexB, i64, AArch64duplane8> {
5840 let Inst{20-17} = idx;
5844 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
5845 Operand idxtype, string asm, list<dag> pattern>
5846 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
5847 "{\t$Rd, $Rn" # size # "$idx" #
5848 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
5849 let Inst{14-11} = imm4;
5852 class SIMDSMov<bit Q, string size, RegisterClass regtype,
5854 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
5855 class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
5857 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
5858 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
5860 class SIMDMovAlias<string asm, string size, Instruction inst,
5861 RegisterClass regtype, Operand idxtype>
5862 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
5863 "|" # size # "\t$dst, $src$idx}",
5864 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
5867 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
5869 let Inst{20-17} = idx;
5872 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
5874 let Inst{20-17} = idx;
5877 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
5879 let Inst{20-18} = idx;
5880 let Inst{17-16} = 0b10;
5882 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
5884 let Inst{20-18} = idx;
5885 let Inst{17-16} = 0b10;
5887 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
5889 let Inst{20-19} = idx;
5890 let Inst{18-16} = 0b100;
5895 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
5897 let Inst{20-17} = idx;
5900 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
5902 let Inst{20-18} = idx;
5903 let Inst{17-16} = 0b10;
5905 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
5907 let Inst{20-19} = idx;
5908 let Inst{18-16} = 0b100;
5910 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
5913 let Inst{19-16} = 0b1000;
5915 def : SIMDMovAlias<"mov", ".s",
5916 !cast<Instruction>(NAME#"vi32"),
5917 GPR32, VectorIndexS>;
5918 def : SIMDMovAlias<"mov", ".d",
5919 !cast<Instruction>(NAME#"vi64"),
5920 GPR64, VectorIndexD>;
5923 class SIMDInsFromMain<string size, ValueType vectype,
5924 RegisterClass regtype, Operand idxtype>
5925 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
5926 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
5927 "{\t$Rd" # size # "$idx, $Rn" #
5928 "|" # size # "\t$Rd$idx, $Rn}",
5931 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
5932 let Inst{14-11} = 0b0011;
5935 class SIMDInsFromElement<string size, ValueType vectype,
5936 ValueType elttype, Operand idxtype>
5937 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
5938 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
5939 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
5940 "|" # size # "\t$Rd$idx, $Rn$idx2}",
5945 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
5948 class SIMDInsMainMovAlias<string size, Instruction inst,
5949 RegisterClass regtype, Operand idxtype>
5950 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
5951 "|" # size #"\t$dst$idx, $src}",
5952 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
5953 class SIMDInsElementMovAlias<string size, Instruction inst,
5955 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
5956 # "|" # size #"\t$dst$idx, $src$idx2}",
5957 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
5960 multiclass SIMDIns {
5961 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
5963 let Inst{20-17} = idx;
5966 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
5968 let Inst{20-18} = idx;
5969 let Inst{17-16} = 0b10;
5971 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
5973 let Inst{20-19} = idx;
5974 let Inst{18-16} = 0b100;
5976 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
5979 let Inst{19-16} = 0b1000;
5982 def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> {
5985 let Inst{20-17} = idx;
5987 let Inst{14-11} = idx2;
5989 def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> {
5992 let Inst{20-18} = idx;
5993 let Inst{17-16} = 0b10;
5994 let Inst{14-12} = idx2;
5997 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
6000 let Inst{20-19} = idx;
6001 let Inst{18-16} = 0b100;
6002 let Inst{14-13} = idx2;
6003 let Inst{12-11} = {?,?};
6005 def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> {
6009 let Inst{19-16} = 0b1000;
6010 let Inst{14} = idx2;
6011 let Inst{13-11} = {?,?,?};
6014 // For all forms of the INS instruction, the "mov" mnemonic is the
6015 // preferred alias. Why they didn't just call the instruction "mov" in
6016 // the first place is a very good question indeed...
6017 def : SIMDInsMainMovAlias<".b", !cast<Instruction>(NAME#"vi8gpr"),
6018 GPR32, VectorIndexB>;
6019 def : SIMDInsMainMovAlias<".h", !cast<Instruction>(NAME#"vi16gpr"),
6020 GPR32, VectorIndexH>;
6021 def : SIMDInsMainMovAlias<".s", !cast<Instruction>(NAME#"vi32gpr"),
6022 GPR32, VectorIndexS>;
6023 def : SIMDInsMainMovAlias<".d", !cast<Instruction>(NAME#"vi64gpr"),
6024 GPR64, VectorIndexD>;
6026 def : SIMDInsElementMovAlias<".b", !cast<Instruction>(NAME#"vi8lane"),
6028 def : SIMDInsElementMovAlias<".h", !cast<Instruction>(NAME#"vi16lane"),
6030 def : SIMDInsElementMovAlias<".s", !cast<Instruction>(NAME#"vi32lane"),
6032 def : SIMDInsElementMovAlias<".d", !cast<Instruction>(NAME#"vi64lane"),
6036 //----------------------------------------------------------------------------
6038 //----------------------------------------------------------------------------
6040 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6041 class BaseSIMDTableLookup<bit Q, bits<2> len, bit op, RegisterOperand vectype,
6042 RegisterOperand listtype, string asm, string kind>
6043 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
6044 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
6051 let Inst{29-21} = 0b001110000;
6052 let Inst{20-16} = Vm;
6054 let Inst{14-13} = len;
6056 let Inst{11-10} = 0b00;
6061 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6062 class BaseSIMDTableLookupTied<bit Q, bits<2> len, bit op, RegisterOperand vectype,
6063 RegisterOperand listtype, string asm, string kind>
6064 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
6065 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
6072 let Inst{29-21} = 0b001110000;
6073 let Inst{20-16} = Vm;
6075 let Inst{14-13} = len;
6077 let Inst{11-10} = 0b00;
6082 class SIMDTableLookupAlias<string asm, Instruction inst,
6083 RegisterOperand vectype, RegisterOperand listtype>
6084 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
6085 (inst vectype:$dst, listtype:$lst, vectype:$index), 0>;
6087 multiclass SIMDTableLookup<bit op, string asm> {
6088 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
6090 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
6092 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
6094 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
6096 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
6098 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
6100 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
6102 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
6105 def : SIMDTableLookupAlias<asm # ".8b",
6106 !cast<Instruction>(NAME#"v8i8One"),
6107 V64, VecListOne128>;
6108 def : SIMDTableLookupAlias<asm # ".8b",
6109 !cast<Instruction>(NAME#"v8i8Two"),
6110 V64, VecListTwo128>;
6111 def : SIMDTableLookupAlias<asm # ".8b",
6112 !cast<Instruction>(NAME#"v8i8Three"),
6113 V64, VecListThree128>;
6114 def : SIMDTableLookupAlias<asm # ".8b",
6115 !cast<Instruction>(NAME#"v8i8Four"),
6116 V64, VecListFour128>;
6117 def : SIMDTableLookupAlias<asm # ".16b",
6118 !cast<Instruction>(NAME#"v16i8One"),
6119 V128, VecListOne128>;
6120 def : SIMDTableLookupAlias<asm # ".16b",
6121 !cast<Instruction>(NAME#"v16i8Two"),
6122 V128, VecListTwo128>;
6123 def : SIMDTableLookupAlias<asm # ".16b",
6124 !cast<Instruction>(NAME#"v16i8Three"),
6125 V128, VecListThree128>;
6126 def : SIMDTableLookupAlias<asm # ".16b",
6127 !cast<Instruction>(NAME#"v16i8Four"),
6128 V128, VecListFour128>;
6131 multiclass SIMDTableLookupTied<bit op, string asm> {
6132 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
6134 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
6136 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
6138 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
6140 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
6142 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
6144 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
6146 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
6149 def : SIMDTableLookupAlias<asm # ".8b",
6150 !cast<Instruction>(NAME#"v8i8One"),
6151 V64, VecListOne128>;
6152 def : SIMDTableLookupAlias<asm # ".8b",
6153 !cast<Instruction>(NAME#"v8i8Two"),
6154 V64, VecListTwo128>;
6155 def : SIMDTableLookupAlias<asm # ".8b",
6156 !cast<Instruction>(NAME#"v8i8Three"),
6157 V64, VecListThree128>;
6158 def : SIMDTableLookupAlias<asm # ".8b",
6159 !cast<Instruction>(NAME#"v8i8Four"),
6160 V64, VecListFour128>;
6161 def : SIMDTableLookupAlias<asm # ".16b",
6162 !cast<Instruction>(NAME#"v16i8One"),
6163 V128, VecListOne128>;
6164 def : SIMDTableLookupAlias<asm # ".16b",
6165 !cast<Instruction>(NAME#"v16i8Two"),
6166 V128, VecListTwo128>;
6167 def : SIMDTableLookupAlias<asm # ".16b",
6168 !cast<Instruction>(NAME#"v16i8Three"),
6169 V128, VecListThree128>;
6170 def : SIMDTableLookupAlias<asm # ".16b",
6171 !cast<Instruction>(NAME#"v16i8Four"),
6172 V128, VecListFour128>;
6176 //----------------------------------------------------------------------------
6177 // AdvSIMD scalar CPY
6178 //----------------------------------------------------------------------------
6179 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6180 class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
6181 string kind, Operand idxtype>
6182 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
6183 "{\t$dst, $src" # kind # "$idx" #
6184 "|\t$dst, $src$idx}", "", []>,
6188 let Inst{31-21} = 0b01011110000;
6189 let Inst{15-10} = 0b000001;
6190 let Inst{9-5} = src;
6191 let Inst{4-0} = dst;
6194 class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
6195 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
6196 : InstAlias<asm # "{\t$dst, $src" # size # "$index" #
6197 # "|\t$dst, $src$index}",
6198 (inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
6201 multiclass SIMDScalarCPY<string asm> {
6202 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
6204 let Inst{20-17} = idx;
6207 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
6209 let Inst{20-18} = idx;
6210 let Inst{17-16} = 0b10;
6212 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
6214 let Inst{20-19} = idx;
6215 let Inst{18-16} = 0b100;
6217 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
6220 let Inst{19-16} = 0b1000;
6223 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
6224 VectorIndexD:$idx)))),
6225 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
6227 // 'DUP' mnemonic aliases.
6228 def : SIMDScalarCPYAlias<"dup", ".b",
6229 !cast<Instruction>(NAME#"i8"),
6230 FPR8, V128, VectorIndexB>;
6231 def : SIMDScalarCPYAlias<"dup", ".h",
6232 !cast<Instruction>(NAME#"i16"),
6233 FPR16, V128, VectorIndexH>;
6234 def : SIMDScalarCPYAlias<"dup", ".s",
6235 !cast<Instruction>(NAME#"i32"),
6236 FPR32, V128, VectorIndexS>;
6237 def : SIMDScalarCPYAlias<"dup", ".d",
6238 !cast<Instruction>(NAME#"i64"),
6239 FPR64, V128, VectorIndexD>;
6242 //----------------------------------------------------------------------------
6243 // AdvSIMD modified immediate instructions
6244 //----------------------------------------------------------------------------
6246 class BaseSIMDModifiedImm<bit Q, bit op, dag oops, dag iops,
6247 string asm, string op_string,
6248 string cstr, list<dag> pattern>
6249 : I<oops, iops, asm, op_string, cstr, pattern>,
6256 let Inst{28-19} = 0b0111100000;
6257 let Inst{18-16} = imm8{7-5};
6258 let Inst{11-10} = 0b01;
6259 let Inst{9-5} = imm8{4-0};
6263 class BaseSIMDModifiedImmVector<bit Q, bit op, RegisterOperand vectype,
6264 Operand immtype, dag opt_shift_iop,
6265 string opt_shift, string asm, string kind,
6267 : BaseSIMDModifiedImm<Q, op, (outs vectype:$Rd),
6268 !con((ins immtype:$imm8), opt_shift_iop), asm,
6269 "{\t$Rd" # kind # ", $imm8" # opt_shift #
6270 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6272 let DecoderMethod = "DecodeModImmInstruction";
6275 class BaseSIMDModifiedImmVectorTied<bit Q, bit op, RegisterOperand vectype,
6276 Operand immtype, dag opt_shift_iop,
6277 string opt_shift, string asm, string kind,
6279 : BaseSIMDModifiedImm<Q, op, (outs vectype:$dst),
6280 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
6281 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
6282 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6283 "$Rd = $dst", pattern> {
6284 let DecoderMethod = "DecodeModImmTiedInstruction";
6287 class BaseSIMDModifiedImmVectorShift<bit Q, bit op, bits<2> b15_b12,
6288 RegisterOperand vectype, string asm,
6289 string kind, list<dag> pattern>
6290 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6291 (ins logical_vec_shift:$shift),
6292 "$shift", asm, kind, pattern> {
6294 let Inst{15} = b15_b12{1};
6295 let Inst{14-13} = shift;
6296 let Inst{12} = b15_b12{0};
6299 class BaseSIMDModifiedImmVectorShiftTied<bit Q, bit op, bits<2> b15_b12,
6300 RegisterOperand vectype, string asm,
6301 string kind, list<dag> pattern>
6302 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6303 (ins logical_vec_shift:$shift),
6304 "$shift", asm, kind, pattern> {
6306 let Inst{15} = b15_b12{1};
6307 let Inst{14-13} = shift;
6308 let Inst{12} = b15_b12{0};
6312 class BaseSIMDModifiedImmVectorShiftHalf<bit Q, bit op, bits<2> b15_b12,
6313 RegisterOperand vectype, string asm,
6314 string kind, list<dag> pattern>
6315 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6316 (ins logical_vec_hw_shift:$shift),
6317 "$shift", asm, kind, pattern> {
6319 let Inst{15} = b15_b12{1};
6321 let Inst{13} = shift{0};
6322 let Inst{12} = b15_b12{0};
6325 class BaseSIMDModifiedImmVectorShiftHalfTied<bit Q, bit op, bits<2> b15_b12,
6326 RegisterOperand vectype, string asm,
6327 string kind, list<dag> pattern>
6328 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6329 (ins logical_vec_hw_shift:$shift),
6330 "$shift", asm, kind, pattern> {
6332 let Inst{15} = b15_b12{1};
6334 let Inst{13} = shift{0};
6335 let Inst{12} = b15_b12{0};
6338 multiclass SIMDModifiedImmVectorShift<bit op, bits<2> hw_cmode, bits<2> w_cmode,
6340 def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64,
6342 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
6345 def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64,
6347 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
6351 multiclass SIMDModifiedImmVectorShiftTied<bit op, bits<2> hw_cmode,
6352 bits<2> w_cmode, string asm,
6354 def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64,
6356 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6358 (i32 imm:$shift)))]>;
6359 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
6361 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6363 (i32 imm:$shift)))]>;
6365 def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64,
6367 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6369 (i32 imm:$shift)))]>;
6370 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
6372 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6374 (i32 imm:$shift)))]>;
6377 class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
6378 RegisterOperand vectype, string asm,
6379 string kind, list<dag> pattern>
6380 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6381 (ins move_vec_shift:$shift),
6382 "$shift", asm, kind, pattern> {
6384 let Inst{15-13} = cmode{3-1};
6385 let Inst{12} = shift;
6388 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bits<4> cmode,
6389 RegisterOperand vectype,
6390 Operand imm_type, string asm,
6391 string kind, list<dag> pattern>
6392 : BaseSIMDModifiedImmVector<Q, op, vectype, imm_type, (ins), "",
6393 asm, kind, pattern> {
6394 let Inst{15-12} = cmode;
6397 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
6399 : BaseSIMDModifiedImm<Q, op, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6400 "\t$Rd, $imm8", "", pattern> {
6401 let Inst{15-12} = cmode;
6402 let DecoderMethod = "DecodeModImmInstruction";
6405 //----------------------------------------------------------------------------
6406 // AdvSIMD indexed element
6407 //----------------------------------------------------------------------------
6409 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6410 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6411 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6412 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6413 string apple_kind, string dst_kind, string lhs_kind,
6414 string rhs_kind, list<dag> pattern>
6415 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6417 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6418 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6427 let Inst{28} = Scalar;
6428 let Inst{27-24} = 0b1111;
6429 let Inst{23-22} = size;
6430 // Bit 21 must be set by the derived class.
6431 let Inst{20-16} = Rm;
6432 let Inst{15-12} = opc;
6433 // Bit 11 must be set by the derived class.
6439 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6440 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6441 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6442 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6443 string apple_kind, string dst_kind, string lhs_kind,
6444 string rhs_kind, list<dag> pattern>
6445 : I<(outs dst_reg:$dst),
6446 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6447 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6448 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6457 let Inst{28} = Scalar;
6458 let Inst{27-24} = 0b1111;
6459 let Inst{23-22} = size;
6460 // Bit 21 must be set by the derived class.
6461 let Inst{20-16} = Rm;
6462 let Inst{15-12} = opc;
6463 // Bit 11 must be set by the derived class.
6469 multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
6470 SDPatternOperator OpNode> {
6471 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6474 asm, ".2s", ".2s", ".2s", ".s",
6475 [(set (v2f32 V64:$Rd),
6476 (OpNode (v2f32 V64:$Rn),
6477 (v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6479 let Inst{11} = idx{1};
6480 let Inst{21} = idx{0};
6483 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6486 asm, ".4s", ".4s", ".4s", ".s",
6487 [(set (v4f32 V128:$Rd),
6488 (OpNode (v4f32 V128:$Rn),
6489 (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6491 let Inst{11} = idx{1};
6492 let Inst{21} = idx{0};
6495 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
6498 asm, ".2d", ".2d", ".2d", ".d",
6499 [(set (v2f64 V128:$Rd),
6500 (OpNode (v2f64 V128:$Rn),
6501 (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
6503 let Inst{11} = idx{0};
6507 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6508 FPR32Op, FPR32Op, V128, VectorIndexS,
6509 asm, ".s", "", "", ".s",
6510 [(set (f32 FPR32Op:$Rd),
6511 (OpNode (f32 FPR32Op:$Rn),
6512 (f32 (vector_extract (v4f32 V128:$Rm),
6513 VectorIndexS:$idx))))]> {
6515 let Inst{11} = idx{1};
6516 let Inst{21} = idx{0};
6519 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6520 FPR64Op, FPR64Op, V128, VectorIndexD,
6521 asm, ".d", "", "", ".d",
6522 [(set (f64 FPR64Op:$Rd),
6523 (OpNode (f64 FPR64Op:$Rn),
6524 (f64 (vector_extract (v2f64 V128:$Rm),
6525 VectorIndexD:$idx))))]> {
6527 let Inst{11} = idx{0};
6532 multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
6533 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
6534 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6535 (AArch64duplane32 (v4f32 V128:$Rm),
6536 VectorIndexS:$idx))),
6537 (!cast<Instruction>(INST # v2i32_indexed)
6538 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6539 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6540 (AArch64dup (f32 FPR32Op:$Rm)))),
6541 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6542 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6545 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
6546 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6547 (AArch64duplane32 (v4f32 V128:$Rm),
6548 VectorIndexS:$idx))),
6549 (!cast<Instruction>(INST # "v4i32_indexed")
6550 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6551 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6552 (AArch64dup (f32 FPR32Op:$Rm)))),
6553 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6554 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6556 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
6557 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6558 (AArch64duplane64 (v2f64 V128:$Rm),
6559 VectorIndexD:$idx))),
6560 (!cast<Instruction>(INST # "v2i64_indexed")
6561 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6562 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6563 (AArch64dup (f64 FPR64Op:$Rm)))),
6564 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6565 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
6567 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
6568 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6569 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6570 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6571 V128:$Rm, VectorIndexS:$idx)>;
6572 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6573 (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))),
6574 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6575 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
6577 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
6578 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6579 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6580 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6581 V128:$Rm, VectorIndexD:$idx)>;
6584 multiclass SIMDFPIndexedTied<bit U, bits<4> opc, string asm> {
6585 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6587 asm, ".2s", ".2s", ".2s", ".s", []> {
6589 let Inst{11} = idx{1};
6590 let Inst{21} = idx{0};
6593 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6596 asm, ".4s", ".4s", ".4s", ".s", []> {
6598 let Inst{11} = idx{1};
6599 let Inst{21} = idx{0};
6602 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6605 asm, ".2d", ".2d", ".2d", ".d", []> {
6607 let Inst{11} = idx{0};
6612 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6613 FPR32Op, FPR32Op, V128, VectorIndexS,
6614 asm, ".s", "", "", ".s", []> {
6616 let Inst{11} = idx{1};
6617 let Inst{21} = idx{0};
6620 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
6621 FPR64Op, FPR64Op, V128, VectorIndexD,
6622 asm, ".d", "", "", ".d", []> {
6624 let Inst{11} = idx{0};
6629 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
6630 SDPatternOperator OpNode> {
6631 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
6632 V128_lo, VectorIndexH,
6633 asm, ".4h", ".4h", ".4h", ".h",
6634 [(set (v4i16 V64:$Rd),
6635 (OpNode (v4i16 V64:$Rn),
6636 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6638 let Inst{11} = idx{2};
6639 let Inst{21} = idx{1};
6640 let Inst{20} = idx{0};
6643 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6645 V128_lo, VectorIndexH,
6646 asm, ".8h", ".8h", ".8h", ".h",
6647 [(set (v8i16 V128:$Rd),
6648 (OpNode (v8i16 V128:$Rn),
6649 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6651 let Inst{11} = idx{2};
6652 let Inst{21} = idx{1};
6653 let Inst{20} = idx{0};
6656 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6659 asm, ".2s", ".2s", ".2s", ".s",
6660 [(set (v2i32 V64:$Rd),
6661 (OpNode (v2i32 V64:$Rn),
6662 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6664 let Inst{11} = idx{1};
6665 let Inst{21} = idx{0};
6668 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6671 asm, ".4s", ".4s", ".4s", ".s",
6672 [(set (v4i32 V128:$Rd),
6673 (OpNode (v4i32 V128:$Rn),
6674 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6676 let Inst{11} = idx{1};
6677 let Inst{21} = idx{0};
6680 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6681 FPR16Op, FPR16Op, V128_lo, VectorIndexH,
6682 asm, ".h", "", "", ".h", []> {
6684 let Inst{11} = idx{2};
6685 let Inst{21} = idx{1};
6686 let Inst{20} = idx{0};
6689 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6690 FPR32Op, FPR32Op, V128, VectorIndexS,
6691 asm, ".s", "", "", ".s",
6692 [(set (i32 FPR32Op:$Rd),
6693 (OpNode FPR32Op:$Rn,
6694 (i32 (vector_extract (v4i32 V128:$Rm),
6695 VectorIndexS:$idx))))]> {
6697 let Inst{11} = idx{1};
6698 let Inst{21} = idx{0};
6702 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
6703 SDPatternOperator OpNode> {
6704 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6706 V128_lo, VectorIndexH,
6707 asm, ".4h", ".4h", ".4h", ".h",
6708 [(set (v4i16 V64:$Rd),
6709 (OpNode (v4i16 V64:$Rn),
6710 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6712 let Inst{11} = idx{2};
6713 let Inst{21} = idx{1};
6714 let Inst{20} = idx{0};
6717 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6719 V128_lo, VectorIndexH,
6720 asm, ".8h", ".8h", ".8h", ".h",
6721 [(set (v8i16 V128:$Rd),
6722 (OpNode (v8i16 V128:$Rn),
6723 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6725 let Inst{11} = idx{2};
6726 let Inst{21} = idx{1};
6727 let Inst{20} = idx{0};
6730 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6733 asm, ".2s", ".2s", ".2s", ".s",
6734 [(set (v2i32 V64:$Rd),
6735 (OpNode (v2i32 V64:$Rn),
6736 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6738 let Inst{11} = idx{1};
6739 let Inst{21} = idx{0};
6742 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6745 asm, ".4s", ".4s", ".4s", ".s",
6746 [(set (v4i32 V128:$Rd),
6747 (OpNode (v4i32 V128:$Rn),
6748 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6750 let Inst{11} = idx{1};
6751 let Inst{21} = idx{0};
6755 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
6756 SDPatternOperator OpNode> {
6757 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
6758 V128_lo, VectorIndexH,
6759 asm, ".4h", ".4h", ".4h", ".h",
6760 [(set (v4i16 V64:$dst),
6761 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6762 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6764 let Inst{11} = idx{2};
6765 let Inst{21} = idx{1};
6766 let Inst{20} = idx{0};
6769 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6771 V128_lo, VectorIndexH,
6772 asm, ".8h", ".8h", ".8h", ".h",
6773 [(set (v8i16 V128:$dst),
6774 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6775 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6777 let Inst{11} = idx{2};
6778 let Inst{21} = idx{1};
6779 let Inst{20} = idx{0};
6782 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6785 asm, ".2s", ".2s", ".2s", ".s",
6786 [(set (v2i32 V64:$dst),
6787 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6788 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6790 let Inst{11} = idx{1};
6791 let Inst{21} = idx{0};
6794 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6797 asm, ".4s", ".4s", ".4s", ".s",
6798 [(set (v4i32 V128:$dst),
6799 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
6800 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6802 let Inst{11} = idx{1};
6803 let Inst{21} = idx{0};
6807 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
6808 SDPatternOperator OpNode> {
6809 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6811 V128_lo, VectorIndexH,
6812 asm, ".4s", ".4s", ".4h", ".h",
6813 [(set (v4i32 V128:$Rd),
6814 (OpNode (v4i16 V64:$Rn),
6815 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6817 let Inst{11} = idx{2};
6818 let Inst{21} = idx{1};
6819 let Inst{20} = idx{0};
6822 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6824 V128_lo, VectorIndexH,
6825 asm#"2", ".4s", ".4s", ".8h", ".h",
6826 [(set (v4i32 V128:$Rd),
6827 (OpNode (extract_high_v8i16 V128:$Rn),
6828 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6829 VectorIndexH:$idx))))]> {
6832 let Inst{11} = idx{2};
6833 let Inst{21} = idx{1};
6834 let Inst{20} = idx{0};
6837 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6840 asm, ".2d", ".2d", ".2s", ".s",
6841 [(set (v2i64 V128:$Rd),
6842 (OpNode (v2i32 V64:$Rn),
6843 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6845 let Inst{11} = idx{1};
6846 let Inst{21} = idx{0};
6849 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6852 asm#"2", ".2d", ".2d", ".4s", ".s",
6853 [(set (v2i64 V128:$Rd),
6854 (OpNode (extract_high_v4i32 V128:$Rn),
6855 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6856 VectorIndexS:$idx))))]> {
6858 let Inst{11} = idx{1};
6859 let Inst{21} = idx{0};
6862 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6863 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6864 asm, ".h", "", "", ".h", []> {
6866 let Inst{11} = idx{2};
6867 let Inst{21} = idx{1};
6868 let Inst{20} = idx{0};
6871 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6872 FPR64Op, FPR32Op, V128, VectorIndexS,
6873 asm, ".s", "", "", ".s", []> {
6875 let Inst{11} = idx{1};
6876 let Inst{21} = idx{0};
6880 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
6881 SDPatternOperator Accum> {
6882 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6884 V128_lo, VectorIndexH,
6885 asm, ".4s", ".4s", ".4h", ".h",
6886 [(set (v4i32 V128:$dst),
6887 (Accum (v4i32 V128:$Rd),
6888 (v4i32 (int_aarch64_neon_sqdmull
6890 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6891 VectorIndexH:$idx))))))]> {
6893 let Inst{11} = idx{2};
6894 let Inst{21} = idx{1};
6895 let Inst{20} = idx{0};
6898 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
6899 // intermediate EXTRACT_SUBREG would be untyped.
6900 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
6901 (i32 (vector_extract (v4i32
6902 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
6903 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6904 VectorIndexH:$idx)))),
6907 (!cast<Instruction>(NAME # v4i16_indexed)
6908 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
6909 V128_lo:$Rm, VectorIndexH:$idx),
6912 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6914 V128_lo, VectorIndexH,
6915 asm#"2", ".4s", ".4s", ".8h", ".h",
6916 [(set (v4i32 V128:$dst),
6917 (Accum (v4i32 V128:$Rd),
6918 (v4i32 (int_aarch64_neon_sqdmull
6919 (extract_high_v8i16 V128:$Rn),
6921 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6922 VectorIndexH:$idx))))))]> {
6924 let Inst{11} = idx{2};
6925 let Inst{21} = idx{1};
6926 let Inst{20} = idx{0};
6929 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6932 asm, ".2d", ".2d", ".2s", ".s",
6933 [(set (v2i64 V128:$dst),
6934 (Accum (v2i64 V128:$Rd),
6935 (v2i64 (int_aarch64_neon_sqdmull
6937 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
6938 VectorIndexS:$idx))))))]> {
6940 let Inst{11} = idx{1};
6941 let Inst{21} = idx{0};
6944 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6947 asm#"2", ".2d", ".2d", ".4s", ".s",
6948 [(set (v2i64 V128:$dst),
6949 (Accum (v2i64 V128:$Rd),
6950 (v2i64 (int_aarch64_neon_sqdmull
6951 (extract_high_v4i32 V128:$Rn),
6953 (AArch64duplane32 (v4i32 V128:$Rm),
6954 VectorIndexS:$idx))))))]> {
6956 let Inst{11} = idx{1};
6957 let Inst{21} = idx{0};
6960 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
6961 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6962 asm, ".h", "", "", ".h", []> {
6964 let Inst{11} = idx{2};
6965 let Inst{21} = idx{1};
6966 let Inst{20} = idx{0};
6970 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6971 FPR64Op, FPR32Op, V128, VectorIndexS,
6972 asm, ".s", "", "", ".s",
6973 [(set (i64 FPR64Op:$dst),
6974 (Accum (i64 FPR64Op:$Rd),
6975 (i64 (int_aarch64_neon_sqdmulls_scalar
6977 (i32 (vector_extract (v4i32 V128:$Rm),
6978 VectorIndexS:$idx))))))]> {
6981 let Inst{11} = idx{1};
6982 let Inst{21} = idx{0};
6986 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
6987 SDPatternOperator OpNode> {
6988 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6989 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6991 V128_lo, VectorIndexH,
6992 asm, ".4s", ".4s", ".4h", ".h",
6993 [(set (v4i32 V128:$Rd),
6994 (OpNode (v4i16 V64:$Rn),
6995 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6997 let Inst{11} = idx{2};
6998 let Inst{21} = idx{1};
6999 let Inst{20} = idx{0};
7002 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
7004 V128_lo, VectorIndexH,
7005 asm#"2", ".4s", ".4s", ".8h", ".h",
7006 [(set (v4i32 V128:$Rd),
7007 (OpNode (extract_high_v8i16 V128:$Rn),
7008 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
7009 VectorIndexH:$idx))))]> {
7012 let Inst{11} = idx{2};
7013 let Inst{21} = idx{1};
7014 let Inst{20} = idx{0};
7017 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
7020 asm, ".2d", ".2d", ".2s", ".s",
7021 [(set (v2i64 V128:$Rd),
7022 (OpNode (v2i32 V64:$Rn),
7023 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7025 let Inst{11} = idx{1};
7026 let Inst{21} = idx{0};
7029 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
7032 asm#"2", ".2d", ".2d", ".4s", ".s",
7033 [(set (v2i64 V128:$Rd),
7034 (OpNode (extract_high_v4i32 V128:$Rn),
7035 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
7036 VectorIndexS:$idx))))]> {
7038 let Inst{11} = idx{1};
7039 let Inst{21} = idx{0};
7044 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
7045 SDPatternOperator OpNode> {
7046 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
7047 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
7049 V128_lo, VectorIndexH,
7050 asm, ".4s", ".4s", ".4h", ".h",
7051 [(set (v4i32 V128:$dst),
7052 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
7053 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
7055 let Inst{11} = idx{2};
7056 let Inst{21} = idx{1};
7057 let Inst{20} = idx{0};
7060 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
7062 V128_lo, VectorIndexH,
7063 asm#"2", ".4s", ".4s", ".8h", ".h",
7064 [(set (v4i32 V128:$dst),
7065 (OpNode (v4i32 V128:$Rd),
7066 (extract_high_v8i16 V128:$Rn),
7067 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
7068 VectorIndexH:$idx))))]> {
7070 let Inst{11} = idx{2};
7071 let Inst{21} = idx{1};
7072 let Inst{20} = idx{0};
7075 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
7078 asm, ".2d", ".2d", ".2s", ".s",
7079 [(set (v2i64 V128:$dst),
7080 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
7081 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7083 let Inst{11} = idx{1};
7084 let Inst{21} = idx{0};
7087 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
7090 asm#"2", ".2d", ".2d", ".4s", ".s",
7091 [(set (v2i64 V128:$dst),
7092 (OpNode (v2i64 V128:$Rd),
7093 (extract_high_v4i32 V128:$Rn),
7094 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
7095 VectorIndexS:$idx))))]> {
7097 let Inst{11} = idx{1};
7098 let Inst{21} = idx{0};
7103 //----------------------------------------------------------------------------
7104 // AdvSIMD scalar shift by immediate
7105 //----------------------------------------------------------------------------
7107 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7108 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
7109 RegisterClass regtype1, RegisterClass regtype2,
7110 Operand immtype, string asm, list<dag> pattern>
7111 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
7112 asm, "\t$Rd, $Rn, $imm", "", pattern>,
7117 let Inst{31-30} = 0b01;
7119 let Inst{28-23} = 0b111110;
7120 let Inst{22-16} = fixed_imm;
7121 let Inst{15-11} = opc;
7127 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7128 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
7129 RegisterClass regtype1, RegisterClass regtype2,
7130 Operand immtype, string asm, list<dag> pattern>
7131 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
7132 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
7137 let Inst{31-30} = 0b01;
7139 let Inst{28-23} = 0b111110;
7140 let Inst{22-16} = fixed_imm;
7141 let Inst{15-11} = opc;
7148 multiclass SIMDScalarRShiftSD<bit U, bits<5> opc, string asm> {
7149 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7150 FPR32, FPR32, vecshiftR32, asm, []> {
7151 let Inst{20-16} = imm{4-0};
7154 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7155 FPR64, FPR64, vecshiftR64, asm, []> {
7156 let Inst{21-16} = imm{5-0};
7160 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
7161 SDPatternOperator OpNode> {
7162 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7163 FPR64, FPR64, vecshiftR64, asm,
7164 [(set (i64 FPR64:$Rd),
7165 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
7166 let Inst{21-16} = imm{5-0};
7169 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
7170 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
7173 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
7174 SDPatternOperator OpNode = null_frag> {
7175 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7176 FPR64, FPR64, vecshiftR64, asm,
7177 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7178 (i32 vecshiftR64:$imm)))]> {
7179 let Inst{21-16} = imm{5-0};
7182 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7183 (i32 vecshiftR64:$imm))),
7184 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7188 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
7189 SDPatternOperator OpNode> {
7190 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7191 FPR64, FPR64, vecshiftL64, asm,
7192 [(set (v1i64 FPR64:$Rd),
7193 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7194 let Inst{21-16} = imm{5-0};
7198 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7199 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
7200 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7201 FPR64, FPR64, vecshiftL64, asm, []> {
7202 let Inst{21-16} = imm{5-0};
7206 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7207 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
7208 SDPatternOperator OpNode = null_frag> {
7209 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7210 FPR8, FPR16, vecshiftR8, asm, []> {
7211 let Inst{18-16} = imm{2-0};
7214 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7215 FPR16, FPR32, vecshiftR16, asm, []> {
7216 let Inst{19-16} = imm{3-0};
7219 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7220 FPR32, FPR64, vecshiftR32, asm,
7221 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7222 let Inst{20-16} = imm{4-0};
7226 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
7227 SDPatternOperator OpNode> {
7228 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7229 FPR8, FPR8, vecshiftL8, asm, []> {
7230 let Inst{18-16} = imm{2-0};
7233 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7234 FPR16, FPR16, vecshiftL16, asm, []> {
7235 let Inst{19-16} = imm{3-0};
7238 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7239 FPR32, FPR32, vecshiftL32, asm,
7240 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7241 let Inst{20-16} = imm{4-0};
7244 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7245 FPR64, FPR64, vecshiftL64, asm,
7246 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7247 let Inst{21-16} = imm{5-0};
7250 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
7251 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
7254 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
7255 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7256 FPR8, FPR8, vecshiftR8, asm, []> {
7257 let Inst{18-16} = imm{2-0};
7260 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7261 FPR16, FPR16, vecshiftR16, asm, []> {
7262 let Inst{19-16} = imm{3-0};
7265 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7266 FPR32, FPR32, vecshiftR32, asm, []> {
7267 let Inst{20-16} = imm{4-0};
7270 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7271 FPR64, FPR64, vecshiftR64, asm, []> {
7272 let Inst{21-16} = imm{5-0};
7276 //----------------------------------------------------------------------------
7277 // AdvSIMD vector x indexed element
7278 //----------------------------------------------------------------------------
7280 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7281 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7282 RegisterOperand dst_reg, RegisterOperand src_reg,
7284 string asm, string dst_kind, string src_kind,
7286 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7287 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7288 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7295 let Inst{28-23} = 0b011110;
7296 let Inst{22-16} = fixed_imm;
7297 let Inst{15-11} = opc;
7303 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7304 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7305 RegisterOperand vectype1, RegisterOperand vectype2,
7307 string asm, string dst_kind, string src_kind,
7309 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7310 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7311 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7318 let Inst{28-23} = 0b011110;
7319 let Inst{22-16} = fixed_imm;
7320 let Inst{15-11} = opc;
7326 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
7328 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7329 V64, V64, vecshiftR32,
7331 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7333 let Inst{20-16} = imm;
7336 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7337 V128, V128, vecshiftR32,
7339 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7341 let Inst{20-16} = imm;
7344 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7345 V128, V128, vecshiftR64,
7347 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7349 let Inst{21-16} = imm;
7353 multiclass SIMDVectorRShiftSDToFP<bit U, bits<5> opc, string asm,
7355 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7356 V64, V64, vecshiftR32,
7358 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7360 let Inst{20-16} = imm;
7363 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7364 V128, V128, vecshiftR32,
7366 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7368 let Inst{20-16} = imm;
7371 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7372 V128, V128, vecshiftR64,
7374 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7376 let Inst{21-16} = imm;
7380 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
7381 SDPatternOperator OpNode> {
7382 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7383 V64, V128, vecshiftR16Narrow,
7385 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7387 let Inst{18-16} = imm;
7390 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7391 V128, V128, vecshiftR16Narrow,
7392 asm#"2", ".16b", ".8h", []> {
7394 let Inst{18-16} = imm;
7395 let hasSideEffects = 0;
7398 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7399 V64, V128, vecshiftR32Narrow,
7401 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7403 let Inst{19-16} = imm;
7406 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7407 V128, V128, vecshiftR32Narrow,
7408 asm#"2", ".8h", ".4s", []> {
7410 let Inst{19-16} = imm;
7411 let hasSideEffects = 0;
7414 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7415 V64, V128, vecshiftR64Narrow,
7417 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7419 let Inst{20-16} = imm;
7422 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7423 V128, V128, vecshiftR64Narrow,
7424 asm#"2", ".4s", ".2d", []> {
7426 let Inst{20-16} = imm;
7427 let hasSideEffects = 0;
7430 // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions
7431 // themselves, so put them here instead.
7433 // Patterns involving what's effectively an insert high and a normal
7434 // intrinsic, represented by CONCAT_VECTORS.
7435 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7436 vecshiftR16Narrow:$imm)),
7437 (!cast<Instruction>(NAME # "v16i8_shift")
7438 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7439 V128:$Rn, vecshiftR16Narrow:$imm)>;
7440 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7441 vecshiftR32Narrow:$imm)),
7442 (!cast<Instruction>(NAME # "v8i16_shift")
7443 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7444 V128:$Rn, vecshiftR32Narrow:$imm)>;
7445 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7446 vecshiftR64Narrow:$imm)),
7447 (!cast<Instruction>(NAME # "v4i32_shift")
7448 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7449 V128:$Rn, vecshiftR64Narrow:$imm)>;
7452 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
7453 SDPatternOperator OpNode> {
7454 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7455 V64, V64, vecshiftL8,
7457 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7458 (i32 vecshiftL8:$imm)))]> {
7460 let Inst{18-16} = imm;
7463 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7464 V128, V128, vecshiftL8,
7465 asm, ".16b", ".16b",
7466 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7467 (i32 vecshiftL8:$imm)))]> {
7469 let Inst{18-16} = imm;
7472 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7473 V64, V64, vecshiftL16,
7475 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7476 (i32 vecshiftL16:$imm)))]> {
7478 let Inst{19-16} = imm;
7481 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7482 V128, V128, vecshiftL16,
7484 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7485 (i32 vecshiftL16:$imm)))]> {
7487 let Inst{19-16} = imm;
7490 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7491 V64, V64, vecshiftL32,
7493 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7494 (i32 vecshiftL32:$imm)))]> {
7496 let Inst{20-16} = imm;
7499 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7500 V128, V128, vecshiftL32,
7502 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7503 (i32 vecshiftL32:$imm)))]> {
7505 let Inst{20-16} = imm;
7508 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7509 V128, V128, vecshiftL64,
7511 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7512 (i32 vecshiftL64:$imm)))]> {
7514 let Inst{21-16} = imm;
7518 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
7519 SDPatternOperator OpNode> {
7520 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7521 V64, V64, vecshiftR8,
7523 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7524 (i32 vecshiftR8:$imm)))]> {
7526 let Inst{18-16} = imm;
7529 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7530 V128, V128, vecshiftR8,
7531 asm, ".16b", ".16b",
7532 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7533 (i32 vecshiftR8:$imm)))]> {
7535 let Inst{18-16} = imm;
7538 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7539 V64, V64, vecshiftR16,
7541 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7542 (i32 vecshiftR16:$imm)))]> {
7544 let Inst{19-16} = imm;
7547 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7548 V128, V128, vecshiftR16,
7550 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7551 (i32 vecshiftR16:$imm)))]> {
7553 let Inst{19-16} = imm;
7556 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7557 V64, V64, vecshiftR32,
7559 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7560 (i32 vecshiftR32:$imm)))]> {
7562 let Inst{20-16} = imm;
7565 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7566 V128, V128, vecshiftR32,
7568 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7569 (i32 vecshiftR32:$imm)))]> {
7571 let Inst{20-16} = imm;
7574 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7575 V128, V128, vecshiftR64,
7577 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7578 (i32 vecshiftR64:$imm)))]> {
7580 let Inst{21-16} = imm;
7584 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
7585 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
7586 SDPatternOperator OpNode = null_frag> {
7587 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7588 V64, V64, vecshiftR8, asm, ".8b", ".8b",
7589 [(set (v8i8 V64:$dst),
7590 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7591 (i32 vecshiftR8:$imm)))]> {
7593 let Inst{18-16} = imm;
7596 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7597 V128, V128, vecshiftR8, asm, ".16b", ".16b",
7598 [(set (v16i8 V128:$dst),
7599 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7600 (i32 vecshiftR8:$imm)))]> {
7602 let Inst{18-16} = imm;
7605 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7606 V64, V64, vecshiftR16, asm, ".4h", ".4h",
7607 [(set (v4i16 V64:$dst),
7608 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7609 (i32 vecshiftR16:$imm)))]> {
7611 let Inst{19-16} = imm;
7614 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7615 V128, V128, vecshiftR16, asm, ".8h", ".8h",
7616 [(set (v8i16 V128:$dst),
7617 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7618 (i32 vecshiftR16:$imm)))]> {
7620 let Inst{19-16} = imm;
7623 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7624 V64, V64, vecshiftR32, asm, ".2s", ".2s",
7625 [(set (v2i32 V64:$dst),
7626 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7627 (i32 vecshiftR32:$imm)))]> {
7629 let Inst{20-16} = imm;
7632 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7633 V128, V128, vecshiftR32, asm, ".4s", ".4s",
7634 [(set (v4i32 V128:$dst),
7635 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7636 (i32 vecshiftR32:$imm)))]> {
7638 let Inst{20-16} = imm;
7641 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7642 V128, V128, vecshiftR64,
7643 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
7644 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7645 (i32 vecshiftR64:$imm)))]> {
7647 let Inst{21-16} = imm;
7651 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
7652 SDPatternOperator OpNode = null_frag> {
7653 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7654 V64, V64, vecshiftL8,
7656 [(set (v8i8 V64:$dst),
7657 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7658 (i32 vecshiftL8:$imm)))]> {
7660 let Inst{18-16} = imm;
7663 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7664 V128, V128, vecshiftL8,
7665 asm, ".16b", ".16b",
7666 [(set (v16i8 V128:$dst),
7667 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7668 (i32 vecshiftL8:$imm)))]> {
7670 let Inst{18-16} = imm;
7673 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7674 V64, V64, vecshiftL16,
7676 [(set (v4i16 V64:$dst),
7677 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7678 (i32 vecshiftL16:$imm)))]> {
7680 let Inst{19-16} = imm;
7683 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7684 V128, V128, vecshiftL16,
7686 [(set (v8i16 V128:$dst),
7687 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7688 (i32 vecshiftL16:$imm)))]> {
7690 let Inst{19-16} = imm;
7693 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7694 V64, V64, vecshiftL32,
7696 [(set (v2i32 V64:$dst),
7697 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7698 (i32 vecshiftL32:$imm)))]> {
7700 let Inst{20-16} = imm;
7703 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7704 V128, V128, vecshiftL32,
7706 [(set (v4i32 V128:$dst),
7707 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7708 (i32 vecshiftL32:$imm)))]> {
7710 let Inst{20-16} = imm;
7713 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7714 V128, V128, vecshiftL64,
7716 [(set (v2i64 V128:$dst),
7717 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7718 (i32 vecshiftL64:$imm)))]> {
7720 let Inst{21-16} = imm;
7724 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
7725 SDPatternOperator OpNode> {
7726 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7727 V128, V64, vecshiftL8, asm, ".8h", ".8b",
7728 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7730 let Inst{18-16} = imm;
7733 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7734 V128, V128, vecshiftL8,
7735 asm#"2", ".8h", ".16b",
7736 [(set (v8i16 V128:$Rd),
7737 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7739 let Inst{18-16} = imm;
7742 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7743 V128, V64, vecshiftL16, asm, ".4s", ".4h",
7744 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7746 let Inst{19-16} = imm;
7749 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7750 V128, V128, vecshiftL16,
7751 asm#"2", ".4s", ".8h",
7752 [(set (v4i32 V128:$Rd),
7753 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7756 let Inst{19-16} = imm;
7759 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7760 V128, V64, vecshiftL32, asm, ".2d", ".2s",
7761 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7763 let Inst{20-16} = imm;
7766 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7767 V128, V128, vecshiftL32,
7768 asm#"2", ".2d", ".4s",
7769 [(set (v2i64 V128:$Rd),
7770 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7772 let Inst{20-16} = imm;
7778 // Vector load/store
7780 // SIMD ldX/stX no-index memory references don't allow the optional
7781 // ", #0" constant and handle post-indexing explicitly, so we use
7782 // a more specialized parse method for them. Otherwise, it's the same as
7783 // the general GPR64sp handling.
7785 class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
7786 string asm, dag oops, dag iops, list<dag> pattern>
7787 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
7792 let Inst{29-23} = 0b0011000;
7794 let Inst{21-16} = 0b000000;
7795 let Inst{15-12} = opcode;
7796 let Inst{11-10} = size;
7801 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
7802 string asm, dag oops, dag iops>
7803 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
7809 let Inst{29-23} = 0b0011001;
7812 let Inst{20-16} = Xm;
7813 let Inst{15-12} = opcode;
7814 let Inst{11-10} = size;
7819 // The immediate form of AdvSIMD post-indexed addressing is encoded with
7820 // register post-index addressing from the zero register.
7821 multiclass SIMDLdStAliases<string asm, string layout, string Count,
7822 int Offset, int Size> {
7823 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
7824 // "ld1\t$Vt, [$Rn], #16"
7825 // may get mapped to
7826 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
7827 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
7828 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7830 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7833 // E.g. "ld1.8b { v0, v1 }, [x1], #16"
7834 // "ld1.8b\t$Vt, [$Rn], #16"
7835 // may get mapped to
7836 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
7837 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
7838 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7840 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7843 // E.g. "ld1.8b { v0, v1 }, [x1]"
7844 // "ld1\t$Vt, [$Rn]"
7845 // may get mapped to
7846 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
7847 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
7848 (!cast<Instruction>(NAME # Count # "v" # layout)
7849 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7852 // E.g. "ld1.8b { v0, v1 }, [x1], x2"
7853 // "ld1\t$Vt, [$Rn], $Xm"
7854 // may get mapped to
7855 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
7856 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
7857 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7859 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7860 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7863 multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
7864 int Offset64, bits<4> opcode> {
7865 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7866 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
7867 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
7868 (ins GPR64sp:$Rn), []>;
7869 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
7870 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
7871 (ins GPR64sp:$Rn), []>;
7872 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
7873 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
7874 (ins GPR64sp:$Rn), []>;
7875 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
7876 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
7877 (ins GPR64sp:$Rn), []>;
7878 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
7879 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
7880 (ins GPR64sp:$Rn), []>;
7881 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
7882 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
7883 (ins GPR64sp:$Rn), []>;
7884 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
7885 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
7886 (ins GPR64sp:$Rn), []>;
7889 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
7890 (outs GPR64sp:$wback,
7891 !cast<RegisterOperand>(veclist # "16b"):$Vt),
7893 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7894 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
7895 (outs GPR64sp:$wback,
7896 !cast<RegisterOperand>(veclist # "8h"):$Vt),
7898 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7899 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
7900 (outs GPR64sp:$wback,
7901 !cast<RegisterOperand>(veclist # "4s"):$Vt),
7903 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7904 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
7905 (outs GPR64sp:$wback,
7906 !cast<RegisterOperand>(veclist # "2d"):$Vt),
7908 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7909 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
7910 (outs GPR64sp:$wback,
7911 !cast<RegisterOperand>(veclist # "8b"):$Vt),
7913 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7914 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
7915 (outs GPR64sp:$wback,
7916 !cast<RegisterOperand>(veclist # "4h"):$Vt),
7918 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7919 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
7920 (outs GPR64sp:$wback,
7921 !cast<RegisterOperand>(veclist # "2s"):$Vt),
7923 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7926 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7927 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7928 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7929 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7930 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7931 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7932 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7935 // Only ld1/st1 has a v1d version.
7936 multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
7937 int Offset64, bits<4> opcode> {
7938 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
7939 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
7940 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7942 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
7943 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7945 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
7946 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7948 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
7949 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7951 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
7952 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7954 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
7955 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7957 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
7958 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7961 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
7962 (outs GPR64sp:$wback),
7963 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7965 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7966 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
7967 (outs GPR64sp:$wback),
7968 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7970 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7971 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
7972 (outs GPR64sp:$wback),
7973 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7975 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7976 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
7977 (outs GPR64sp:$wback),
7978 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7980 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7981 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
7982 (outs GPR64sp:$wback),
7983 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7985 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7986 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
7987 (outs GPR64sp:$wback),
7988 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7990 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7991 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
7992 (outs GPR64sp:$wback),
7993 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7995 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7998 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7999 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
8000 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
8001 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
8002 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
8003 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
8004 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
8007 multiclass BaseSIMDLd1<string Count, string asm, string veclist,
8008 int Offset128, int Offset64, bits<4> opcode>
8009 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
8011 // LD1 instructions have extra "1d" variants.
8012 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
8013 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
8014 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
8015 (ins GPR64sp:$Rn), []>;
8017 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
8018 (outs GPR64sp:$wback,
8019 !cast<RegisterOperand>(veclist # "1d"):$Vt),
8021 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8024 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
8027 multiclass BaseSIMDSt1<string Count, string asm, string veclist,
8028 int Offset128, int Offset64, bits<4> opcode>
8029 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
8031 // ST1 instructions have extra "1d" variants.
8032 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
8033 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
8034 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
8037 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
8038 (outs GPR64sp:$wback),
8039 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
8041 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8044 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
8047 multiclass SIMDLd1Multiple<string asm> {
8048 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
8049 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
8050 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
8051 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
8054 multiclass SIMDSt1Multiple<string asm> {
8055 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
8056 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
8057 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
8058 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
8061 multiclass SIMDLd2Multiple<string asm> {
8062 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
8065 multiclass SIMDSt2Multiple<string asm> {
8066 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
8069 multiclass SIMDLd3Multiple<string asm> {
8070 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
8073 multiclass SIMDSt3Multiple<string asm> {
8074 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
8077 multiclass SIMDLd4Multiple<string asm> {
8078 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
8081 multiclass SIMDSt4Multiple<string asm> {
8082 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
8086 // AdvSIMD Load/store single-element
8089 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
8090 string asm, string operands, string cst,
8091 dag oops, dag iops, list<dag> pattern>
8092 : I<oops, iops, asm, operands, cst, pattern> {
8096 let Inst{29-24} = 0b001101;
8099 let Inst{15-13} = opcode;
8104 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
8105 string asm, string operands, string cst,
8106 dag oops, dag iops, list<dag> pattern>
8107 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
8111 let Inst{29-24} = 0b001101;
8114 let Inst{15-13} = opcode;
8120 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8121 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
8123 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
8124 (outs listtype:$Vt), (ins GPR64sp:$Rn),
8128 let Inst{20-16} = 0b00000;
8130 let Inst{11-10} = size;
8132 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8133 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
8134 string asm, Operand listtype, Operand GPR64pi>
8135 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
8137 (outs GPR64sp:$wback, listtype:$Vt),
8138 (ins GPR64sp:$Rn, GPR64pi:$Xm), []> {
8142 let Inst{20-16} = Xm;
8144 let Inst{11-10} = size;
8147 multiclass SIMDLdrAliases<string asm, string layout, string Count,
8148 int Offset, int Size> {
8149 // E.g. "ld1r { v0.8b }, [x1], #1"
8150 // "ld1r.8b\t$Vt, [$Rn], #1"
8151 // may get mapped to
8152 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8153 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8154 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8156 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8159 // E.g. "ld1r.8b { v0 }, [x1], #1"
8160 // "ld1r.8b\t$Vt, [$Rn], #1"
8161 // may get mapped to
8162 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8163 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8164 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8166 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8169 // E.g. "ld1r.8b { v0 }, [x1]"
8170 // "ld1r.8b\t$Vt, [$Rn]"
8171 // may get mapped to
8172 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8173 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8174 (!cast<Instruction>(NAME # "v" # layout)
8175 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8178 // E.g. "ld1r.8b { v0 }, [x1], x2"
8179 // "ld1r.8b\t$Vt, [$Rn], $Xm"
8180 // may get mapped to
8181 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8182 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8183 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8185 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8186 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8189 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
8190 int Offset1, int Offset2, int Offset4, int Offset8> {
8191 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
8192 !cast<Operand>("VecList" # Count # "8b")>;
8193 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
8194 !cast<Operand>("VecList" # Count #"16b")>;
8195 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
8196 !cast<Operand>("VecList" # Count #"4h")>;
8197 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
8198 !cast<Operand>("VecList" # Count #"8h")>;
8199 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
8200 !cast<Operand>("VecList" # Count #"2s")>;
8201 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
8202 !cast<Operand>("VecList" # Count #"4s")>;
8203 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
8204 !cast<Operand>("VecList" # Count #"1d")>;
8205 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
8206 !cast<Operand>("VecList" # Count #"2d")>;
8208 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
8209 !cast<Operand>("VecList" # Count # "8b"),
8210 !cast<Operand>("GPR64pi" # Offset1)>;
8211 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
8212 !cast<Operand>("VecList" # Count # "16b"),
8213 !cast<Operand>("GPR64pi" # Offset1)>;
8214 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
8215 !cast<Operand>("VecList" # Count # "4h"),
8216 !cast<Operand>("GPR64pi" # Offset2)>;
8217 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
8218 !cast<Operand>("VecList" # Count # "8h"),
8219 !cast<Operand>("GPR64pi" # Offset2)>;
8220 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
8221 !cast<Operand>("VecList" # Count # "2s"),
8222 !cast<Operand>("GPR64pi" # Offset4)>;
8223 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
8224 !cast<Operand>("VecList" # Count # "4s"),
8225 !cast<Operand>("GPR64pi" # Offset4)>;
8226 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
8227 !cast<Operand>("VecList" # Count # "1d"),
8228 !cast<Operand>("GPR64pi" # Offset8)>;
8229 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
8230 !cast<Operand>("VecList" # Count # "2d"),
8231 !cast<Operand>("GPR64pi" # Offset8)>;
8233 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
8234 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
8235 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
8236 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
8237 defm : SIMDLdrAliases<asm, "2s", Count, Offset4, 64>;
8238 defm : SIMDLdrAliases<asm, "4s", Count, Offset4, 128>;
8239 defm : SIMDLdrAliases<asm, "1d", Count, Offset8, 64>;
8240 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
8243 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
8244 dag oops, dag iops, list<dag> pattern>
8245 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8247 // idx encoded in Q:S:size fields.
8249 let Inst{30} = idx{3};
8251 let Inst{20-16} = 0b00000;
8252 let Inst{12} = idx{2};
8253 let Inst{11-10} = idx{1-0};
8255 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
8256 dag oops, dag iops, list<dag> pattern>
8257 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8258 oops, iops, pattern> {
8259 // idx encoded in Q:S:size fields.
8261 let Inst{30} = idx{3};
8263 let Inst{20-16} = 0b00000;
8264 let Inst{12} = idx{2};
8265 let Inst{11-10} = idx{1-0};
8267 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
8269 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8270 "$Rn = $wback", oops, iops, []> {
8271 // idx encoded in Q:S:size fields.
8274 let Inst{30} = idx{3};
8276 let Inst{20-16} = Xm;
8277 let Inst{12} = idx{2};
8278 let Inst{11-10} = idx{1-0};
8280 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
8282 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8283 "$Rn = $wback", oops, iops, []> {
8284 // idx encoded in Q:S:size fields.
8287 let Inst{30} = idx{3};
8289 let Inst{20-16} = Xm;
8290 let Inst{12} = idx{2};
8291 let Inst{11-10} = idx{1-0};
8294 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
8295 dag oops, dag iops, list<dag> pattern>
8296 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8298 // idx encoded in Q:S:size<1> fields.
8300 let Inst{30} = idx{2};
8302 let Inst{20-16} = 0b00000;
8303 let Inst{12} = idx{1};
8304 let Inst{11} = idx{0};
8305 let Inst{10} = size;
8307 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
8308 dag oops, dag iops, list<dag> pattern>
8309 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8310 oops, iops, pattern> {
8311 // idx encoded in Q:S:size<1> fields.
8313 let Inst{30} = idx{2};
8315 let Inst{20-16} = 0b00000;
8316 let Inst{12} = idx{1};
8317 let Inst{11} = idx{0};
8318 let Inst{10} = size;
8321 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8323 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8324 "$Rn = $wback", oops, iops, []> {
8325 // idx encoded in Q:S:size<1> fields.
8328 let Inst{30} = idx{2};
8330 let Inst{20-16} = Xm;
8331 let Inst{12} = idx{1};
8332 let Inst{11} = idx{0};
8333 let Inst{10} = size;
8335 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8337 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8338 "$Rn = $wback", oops, iops, []> {
8339 // idx encoded in Q:S:size<1> fields.
8342 let Inst{30} = idx{2};
8344 let Inst{20-16} = Xm;
8345 let Inst{12} = idx{1};
8346 let Inst{11} = idx{0};
8347 let Inst{10} = size;
8349 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8350 dag oops, dag iops, list<dag> pattern>
8351 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8353 // idx encoded in Q:S fields.
8355 let Inst{30} = idx{1};
8357 let Inst{20-16} = 0b00000;
8358 let Inst{12} = idx{0};
8359 let Inst{11-10} = size;
8361 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8362 dag oops, dag iops, list<dag> pattern>
8363 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8364 oops, iops, pattern> {
8365 // idx encoded in Q:S fields.
8367 let Inst{30} = idx{1};
8369 let Inst{20-16} = 0b00000;
8370 let Inst{12} = idx{0};
8371 let Inst{11-10} = size;
8373 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
8374 string asm, dag oops, dag iops>
8375 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8376 "$Rn = $wback", oops, iops, []> {
8377 // idx encoded in Q:S fields.
8380 let Inst{30} = idx{1};
8382 let Inst{20-16} = Xm;
8383 let Inst{12} = idx{0};
8384 let Inst{11-10} = size;
8386 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8387 string asm, dag oops, dag iops>
8388 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8389 "$Rn = $wback", oops, iops, []> {
8390 // idx encoded in Q:S fields.
8393 let Inst{30} = idx{1};
8395 let Inst{20-16} = Xm;
8396 let Inst{12} = idx{0};
8397 let Inst{11-10} = size;
8399 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8400 dag oops, dag iops, list<dag> pattern>
8401 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8403 // idx encoded in Q field.
8407 let Inst{20-16} = 0b00000;
8409 let Inst{11-10} = size;
8411 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8412 dag oops, dag iops, list<dag> pattern>
8413 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8414 oops, iops, pattern> {
8415 // idx encoded in Q field.
8419 let Inst{20-16} = 0b00000;
8421 let Inst{11-10} = size;
8423 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
8424 string asm, dag oops, dag iops>
8425 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8426 "$Rn = $wback", oops, iops, []> {
8427 // idx encoded in Q field.
8432 let Inst{20-16} = Xm;
8434 let Inst{11-10} = size;
8436 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8437 string asm, dag oops, dag iops>
8438 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8439 "$Rn = $wback", oops, iops, []> {
8440 // idx encoded in Q field.
8445 let Inst{20-16} = Xm;
8447 let Inst{11-10} = size;
8450 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8451 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
8452 RegisterOperand listtype,
8453 RegisterOperand GPR64pi> {
8454 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
8455 (outs listtype:$dst),
8456 (ins listtype:$Vt, VectorIndexB:$idx,
8459 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
8460 (outs GPR64sp:$wback, listtype:$dst),
8461 (ins listtype:$Vt, VectorIndexB:$idx,
8462 GPR64sp:$Rn, GPR64pi:$Xm)>;
8464 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8465 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
8466 RegisterOperand listtype,
8467 RegisterOperand GPR64pi> {
8468 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
8469 (outs listtype:$dst),
8470 (ins listtype:$Vt, VectorIndexH:$idx,
8473 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
8474 (outs GPR64sp:$wback, listtype:$dst),
8475 (ins listtype:$Vt, VectorIndexH:$idx,
8476 GPR64sp:$Rn, GPR64pi:$Xm)>;
8478 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8479 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
8480 RegisterOperand listtype,
8481 RegisterOperand GPR64pi> {
8482 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
8483 (outs listtype:$dst),
8484 (ins listtype:$Vt, VectorIndexS:$idx,
8487 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
8488 (outs GPR64sp:$wback, listtype:$dst),
8489 (ins listtype:$Vt, VectorIndexS:$idx,
8490 GPR64sp:$Rn, GPR64pi:$Xm)>;
8492 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8493 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
8494 RegisterOperand listtype, RegisterOperand GPR64pi> {
8495 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
8496 (outs listtype:$dst),
8497 (ins listtype:$Vt, VectorIndexD:$idx,
8500 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
8501 (outs GPR64sp:$wback, listtype:$dst),
8502 (ins listtype:$Vt, VectorIndexD:$idx,
8503 GPR64sp:$Rn, GPR64pi:$Xm)>;
8505 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8506 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
8507 RegisterOperand listtype, RegisterOperand GPR64pi> {
8508 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
8509 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
8512 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
8513 (outs GPR64sp:$wback),
8514 (ins listtype:$Vt, VectorIndexB:$idx,
8515 GPR64sp:$Rn, GPR64pi:$Xm)>;
8517 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8518 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
8519 RegisterOperand listtype, RegisterOperand GPR64pi> {
8520 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
8521 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8524 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
8525 (outs GPR64sp:$wback),
8526 (ins listtype:$Vt, VectorIndexH:$idx,
8527 GPR64sp:$Rn, GPR64pi:$Xm)>;
8529 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8530 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
8531 RegisterOperand listtype, RegisterOperand GPR64pi> {
8532 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
8533 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8536 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
8537 (outs GPR64sp:$wback),
8538 (ins listtype:$Vt, VectorIndexS:$idx,
8539 GPR64sp:$Rn, GPR64pi:$Xm)>;
8541 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8542 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
8543 RegisterOperand listtype, RegisterOperand GPR64pi> {
8544 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
8545 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8548 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
8549 (outs GPR64sp:$wback),
8550 (ins listtype:$Vt, VectorIndexD:$idx,
8551 GPR64sp:$Rn, GPR64pi:$Xm)>;
8554 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
8555 string Count, int Offset, Operand idxtype> {
8556 // E.g. "ld1 { v0.8b }[0], [x1], #1"
8557 // "ld1\t$Vt, [$Rn], #1"
8558 // may get mapped to
8559 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8560 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
8561 (!cast<Instruction>(NAME # Type # "_POST")
8563 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8564 idxtype:$idx, XZR), 1>;
8566 // E.g. "ld1.8b { v0 }[0], [x1], #1"
8567 // "ld1.8b\t$Vt, [$Rn], #1"
8568 // may get mapped to
8569 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8570 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
8571 (!cast<Instruction>(NAME # Type # "_POST")
8573 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8574 idxtype:$idx, XZR), 0>;
8576 // E.g. "ld1.8b { v0 }[0], [x1]"
8577 // "ld1.8b\t$Vt, [$Rn]"
8578 // may get mapped to
8579 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8580 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
8581 (!cast<Instruction>(NAME # Type)
8582 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8583 idxtype:$idx, GPR64sp:$Rn), 0>;
8585 // E.g. "ld1.8b { v0 }[0], [x1], x2"
8586 // "ld1.8b\t$Vt, [$Rn], $Xm"
8587 // may get mapped to
8588 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8589 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
8590 (!cast<Instruction>(NAME # Type # "_POST")
8592 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8594 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8597 multiclass SIMDLdSt1SingleAliases<string asm> {
8598 defm : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
8599 defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
8600 defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
8601 defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
8604 multiclass SIMDLdSt2SingleAliases<string asm> {
8605 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
8606 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
8607 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
8608 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
8611 multiclass SIMDLdSt3SingleAliases<string asm> {
8612 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
8613 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
8614 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
8615 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
8618 multiclass SIMDLdSt4SingleAliases<string asm> {
8619 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
8620 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
8621 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
8622 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
8624 } // end of 'let Predicates = [HasNEON]'
8626 //----------------------------------------------------------------------------
8627 // AdvSIMD v8.1 Rounding Double Multiply Add/Subtract
8628 //----------------------------------------------------------------------------
8630 let Predicates = [HasNEON, HasV8_1a] in {
8632 class BaseSIMDThreeSameVectorTiedR0<bit Q, bit U, bits<2> size, bits<5> opcode,
8633 RegisterOperand regtype, string asm,
8634 string kind, list<dag> pattern>
8635 : BaseSIMDThreeSameVectorTied<Q, U, size, opcode, regtype, asm, kind,
8639 multiclass SIMDThreeSameVectorSQRDMLxHTiedHS<bit U, bits<5> opc, string asm,
8640 SDPatternOperator Accum> {
8641 def v4i16 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b01, opc, V64, asm, ".4h",
8642 [(set (v4i16 V64:$dst),
8643 (Accum (v4i16 V64:$Rd),
8644 (v4i16 (int_aarch64_neon_sqrdmulh (v4i16 V64:$Rn),
8645 (v4i16 V64:$Rm)))))]>;
8646 def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
8647 [(set (v8i16 V128:$dst),
8648 (Accum (v8i16 V128:$Rd),
8649 (v8i16 (int_aarch64_neon_sqrdmulh (v8i16 V128:$Rn),
8650 (v8i16 V128:$Rm)))))]>;
8651 def v2i32 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b10, opc, V64, asm, ".2s",
8652 [(set (v2i32 V64:$dst),
8653 (Accum (v2i32 V64:$Rd),
8654 (v2i32 (int_aarch64_neon_sqrdmulh (v2i32 V64:$Rn),
8655 (v2i32 V64:$Rm)))))]>;
8656 def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s",
8657 [(set (v4i32 V128:$dst),
8658 (Accum (v4i32 V128:$Rd),
8659 (v4i32 (int_aarch64_neon_sqrdmulh (v4i32 V128:$Rn),
8660 (v4i32 V128:$Rm)))))]>;
8663 multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
8664 SDPatternOperator Accum> {
8665 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
8666 V64, V64, V128_lo, VectorIndexH,
8667 asm, ".4h", ".4h", ".4h", ".h",
8668 [(set (v4i16 V64:$dst),
8669 (Accum (v4i16 V64:$Rd),
8670 (v4i16 (int_aarch64_neon_sqrdmulh
8672 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
8673 VectorIndexH:$idx))))))]> {
8675 let Inst{11} = idx{2};
8676 let Inst{21} = idx{1};
8677 let Inst{20} = idx{0};
8680 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
8681 V128, V128, V128_lo, VectorIndexH,
8682 asm, ".8h", ".8h", ".8h", ".h",
8683 [(set (v8i16 V128:$dst),
8684 (Accum (v8i16 V128:$Rd),
8685 (v8i16 (int_aarch64_neon_sqrdmulh
8687 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
8688 VectorIndexH:$idx))))))]> {
8690 let Inst{11} = idx{2};
8691 let Inst{21} = idx{1};
8692 let Inst{20} = idx{0};
8695 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
8696 V64, V64, V128, VectorIndexS,
8697 asm, ".2s", ".2s", ".2s", ".s",
8698 [(set (v2i32 V64:$dst),
8699 (Accum (v2i32 V64:$Rd),
8700 (v2i32 (int_aarch64_neon_sqrdmulh
8702 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
8703 VectorIndexS:$idx))))))]> {
8705 let Inst{11} = idx{1};
8706 let Inst{21} = idx{0};
8709 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but
8710 // an intermediate EXTRACT_SUBREG would be untyped.
8711 // FIXME: direct EXTRACT_SUBREG from v2i32 to i32 is illegal, that's why we
8712 // got it lowered here as (i32 vector_extract (v4i32 insert_subvector(..)))
8713 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
8714 (i32 (vector_extract
8715 (v4i32 (insert_subvector
8717 (v2i32 (int_aarch64_neon_sqrdmulh
8719 (v2i32 (AArch64duplane32
8721 VectorIndexS:$idx)))),
8725 (v2i32 (!cast<Instruction>(NAME # v2i32_indexed)
8726 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
8731 VectorIndexS:$idx)),
8734 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
8735 V128, V128, V128, VectorIndexS,
8736 asm, ".4s", ".4s", ".4s", ".s",
8737 [(set (v4i32 V128:$dst),
8738 (Accum (v4i32 V128:$Rd),
8739 (v4i32 (int_aarch64_neon_sqrdmulh
8741 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
8742 VectorIndexS:$idx))))))]> {
8744 let Inst{11} = idx{1};
8745 let Inst{21} = idx{0};
8748 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but
8749 // an intermediate EXTRACT_SUBREG would be untyped.
8750 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
8751 (i32 (vector_extract
8752 (v4i32 (int_aarch64_neon_sqrdmulh
8754 (v4i32 (AArch64duplane32
8756 VectorIndexS:$idx)))),
8759 (v4i32 (!cast<Instruction>(NAME # v4i32_indexed)
8760 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
8765 VectorIndexS:$idx)),
8768 def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
8769 FPR16Op, FPR16Op, V128_lo,
8770 VectorIndexH, asm, ".h", "", "", ".h",
8773 let Inst{11} = idx{2};
8774 let Inst{21} = idx{1};
8775 let Inst{20} = idx{0};
8778 def i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
8779 FPR32Op, FPR32Op, V128, VectorIndexS,
8780 asm, ".s", "", "", ".s",
8781 [(set (i32 FPR32Op:$dst),
8782 (Accum (i32 FPR32Op:$Rd),
8783 (i32 (int_aarch64_neon_sqrdmulh
8785 (i32 (vector_extract (v4i32 V128:$Rm),
8786 VectorIndexS:$idx))))))]> {
8788 let Inst{11} = idx{1};
8789 let Inst{21} = idx{0};
8792 } // let Predicates = [HasNeon, HasV8_1a]
8794 //----------------------------------------------------------------------------
8795 // Crypto extensions
8796 //----------------------------------------------------------------------------
8798 let Predicates = [HasCrypto] in {
8799 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8800 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
8802 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
8806 let Inst{31-16} = 0b0100111000101000;
8807 let Inst{15-12} = opc;
8808 let Inst{11-10} = 0b10;
8813 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
8814 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
8815 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
8817 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
8818 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
8820 [(set (v16i8 V128:$dst),
8821 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
8823 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8824 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
8825 dag oops, dag iops, list<dag> pat>
8826 : I<oops, iops, asm,
8827 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
8828 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
8833 let Inst{31-21} = 0b01011110000;
8834 let Inst{20-16} = Rm;
8836 let Inst{14-12} = opc;
8837 let Inst{11-10} = 0b00;
8842 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
8843 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8844 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
8845 [(set (v4i32 FPR128:$dst),
8846 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
8847 (v4i32 V128:$Rm)))]>;
8849 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
8850 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
8851 (ins V128:$Rd, V128:$Rn, V128:$Rm),
8852 [(set (v4i32 V128:$dst),
8853 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8854 (v4i32 V128:$Rm)))]>;
8856 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
8857 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8858 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
8859 [(set (v4i32 FPR128:$dst),
8860 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
8861 (v4i32 V128:$Rm)))]>;
8863 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8864 class SHA2OpInst<bits<4> opc, string asm, string kind,
8865 string cstr, dag oops, dag iops,
8867 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
8868 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
8872 let Inst{31-16} = 0b0101111000101000;
8873 let Inst{15-12} = opc;
8874 let Inst{11-10} = 0b10;
8879 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
8880 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
8881 (ins V128:$Rd, V128:$Rn),
8882 [(set (v4i32 V128:$dst),
8883 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
8885 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
8886 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
8887 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
8888 } // end of 'let Predicates = [HasCrypto]'
8890 //----------------------------------------------------------------------------
8891 // v8.1 atomic instructions extension:
8895 // * LDOPregister<OP>, and aliases STOPregister<OP>
8897 // Instruction encodings:
8899 // 31 30|29 24|23|22|21|20 16|15|14 10|9 5|4 0
8900 // CAS SZ |001000|1 |A |1 |Rs |R |11111 |Rn |Rt
8901 // CASP 0|SZ|001000|0 |A |1 |Rs |R |11111 |Rn |Rt
8902 // SWP SZ |111000|A |R |1 |Rs |1 |OPC|00|Rn |Rt
8903 // LD SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |Rt
8904 // ST SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |11111
8906 // Instruction syntax:
8908 // CAS{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
8909 // CAS{<order>} <Xs>, <Xt>, [<Xn|SP>]
8910 // CASP{<order>} <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>]
8911 // CASP{<order>} <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
8912 // SWP{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
8913 // SWP{<order>} <Xs>, <Xt>, [<Xn|SP>]
8914 // LD<OP>{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
8915 // LD<OP>{<order>} <Xs>, <Xt>, [<Xn|SP>]
8916 // ST<OP>{<order>}[<size>] <Ws>, [<Xn|SP>]
8917 // ST<OP>{<order>} <Xs>, [<Xn|SP>]
8919 let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
8920 class BaseCASEncoding<dag oops, dag iops, string asm, string operands,
8921 string cstr, list<dag> pattern>
8922 : I<oops, iops, asm, operands, cstr, pattern> {
8930 let Inst{31-30} = Sz;
8931 let Inst{29-24} = 0b001000;
8935 let Inst{20-16} = Rs;
8937 let Inst{14-10} = 0b11111;
8942 class BaseCAS<string order, string size, RegisterClass RC>
8943 : BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn),
8944 "cas" # order # size, "\t$Rs, $Rt, [$Rn]",
8949 multiclass CompareAndSwap<bits<1> Acq, bits<1> Rel, string order> {
8950 let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseCAS<order, "b", GPR32>;
8951 let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseCAS<order, "h", GPR32>;
8952 let Sz = 0b10, Acq = Acq, Rel = Rel in def s : BaseCAS<order, "", GPR32>;
8953 let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseCAS<order, "", GPR64>;
8956 class BaseCASP<string order, string size, RegisterOperand RC>
8957 : BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn),
8958 "casp" # order # size, "\t$Rs, $Rt, [$Rn]",
8963 multiclass CompareAndSwapPair<bits<1> Acq, bits<1> Rel, string order> {
8964 let Sz = 0b00, Acq = Acq, Rel = Rel in
8965 def s : BaseCASP<order, "", WSeqPairClassOperand>;
8966 let Sz = 0b01, Acq = Acq, Rel = Rel in
8967 def d : BaseCASP<order, "", XSeqPairClassOperand>;
8970 let Predicates = [HasV8_1a] in
8971 class BaseSWP<string order, string size, RegisterClass RC>
8972 : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "swp" # order # size,
8973 "\t$Rs, $Rt, [$Rn]","",[]> {
8978 bits<3> opc = 0b000;
8981 let Inst{31-30} = Sz;
8982 let Inst{29-24} = 0b111000;
8986 let Inst{20-16} = Rs;
8988 let Inst{14-12} = opc;
8989 let Inst{11-10} = 0b00;
8994 multiclass Swap<bits<1> Acq, bits<1> Rel, string order> {
8995 let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseSWP<order, "b", GPR32>;
8996 let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseSWP<order, "h", GPR32>;
8997 let Sz = 0b10, Acq = Acq, Rel = Rel in def s : BaseSWP<order, "", GPR32>;
8998 let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseSWP<order, "", GPR64>;
9001 let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
9002 class BaseLDOPregister<string op, string order, string size, RegisterClass RC>
9003 : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "ld" # op # order # size,
9004 "\t$Rs, $Rt, [$Rn]","",[]> {
9012 let Inst{31-30} = Sz;
9013 let Inst{29-24} = 0b111000;
9017 let Inst{20-16} = Rs;
9019 let Inst{14-12} = opc;
9020 let Inst{11-10} = 0b00;
9025 multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel,
9027 let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in
9028 def b : BaseLDOPregister<op, order, "b", GPR32>;
9029 let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in
9030 def h : BaseLDOPregister<op, order, "h", GPR32>;
9031 let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in
9032 def s : BaseLDOPregister<op, order, "", GPR32>;
9033 let Sz = 0b11, Acq = Acq, Rel = Rel, opc = opc in
9034 def d : BaseLDOPregister<op, order, "", GPR64>;
9037 let Predicates = [HasV8_1a] in
9038 class BaseSTOPregister<string asm, RegisterClass OP, Register Reg,
9040 InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn)>;
9042 multiclass STOPregister<string asm, string instr> {
9043 def : BaseSTOPregister<asm # "lb", GPR32, WZR,
9044 !cast<Instruction>(instr # "Lb")>;
9045 def : BaseSTOPregister<asm # "lh", GPR32, WZR,
9046 !cast<Instruction>(instr # "Lh")>;
9047 def : BaseSTOPregister<asm # "l", GPR32, WZR,
9048 !cast<Instruction>(instr # "Ls")>;
9049 def : BaseSTOPregister<asm # "l", GPR64, XZR,
9050 !cast<Instruction>(instr # "Ld")>;
9051 def : BaseSTOPregister<asm # "b", GPR32, WZR,
9052 !cast<Instruction>(instr # "b")>;
9053 def : BaseSTOPregister<asm # "h", GPR32, WZR,
9054 !cast<Instruction>(instr # "h")>;
9055 def : BaseSTOPregister<asm, GPR32, WZR,
9056 !cast<Instruction>(instr # "s")>;
9057 def : BaseSTOPregister<asm, GPR64, XZR,
9058 !cast<Instruction>(instr # "d")>;
9061 //----------------------------------------------------------------------------
9062 // Allow the size specifier tokens to be upper case, not just lower.
9063 def : TokenAlias<".8B", ".8b">;
9064 def : TokenAlias<".4H", ".4h">;
9065 def : TokenAlias<".2S", ".2s">;
9066 def : TokenAlias<".1D", ".1d">;
9067 def : TokenAlias<".16B", ".16b">;
9068 def : TokenAlias<".8H", ".8h">;
9069 def : TokenAlias<".4S", ".4s">;
9070 def : TokenAlias<".2D", ".2d">;
9071 def : TokenAlias<".1Q", ".1q">;
9072 def : TokenAlias<".B", ".b">;
9073 def : TokenAlias<".H", ".h">;
9074 def : TokenAlias<".S", ".s">;
9075 def : TokenAlias<".D", ".d">;
9076 def : TokenAlias<".Q", ".q">;