1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/IR/Instruction.h"
22 #include "llvm/Target/TargetLowering.h"
26 namespace AArch64ISD {
28 enum NodeType : unsigned {
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
31 CALL, // Function call.
33 // Produces the full sequence of instructions for getting the thread pointer
34 // offset of a variable into X0, using the TLSDesc model.
36 ADRP, // Page address of a TargetGlobalAddress operand.
37 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
38 LOADgot, // Load from automatically generated descriptor (e.g. Global
39 // Offset Table, TLS record).
40 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
41 BRCOND, // Conditional branch instruction; "b.cond".
43 FCSEL, // Conditional move instruction.
44 CSINV, // Conditional select invert.
45 CSNEG, // Conditional select negate.
46 CSINC, // Conditional select increment.
48 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
52 SBC, // adc, sbc instructions
54 // Arithmetic instructions which write flags.
61 // Conditional compares. Operands: left,right,falsecc,cc,flags
66 // Floating point comparison
69 // Floating point max and min instructions.
76 // Scalar-to-vector duplication
83 // Vector immedate moves
92 // Vector immediate ops
96 // Vector bit select: similar to ISD::VSELECT but not all bits within an
97 // element must be identical.
100 // Vector arithmetic negation
115 // Vector shift by scalar
120 // Vector shift by scalar (again)
127 // Vector comparisons
137 // Vector zero comparisons
149 // Vector across-lanes addition
150 // Only the lower result lane is defined.
154 // Vector across-lanes min/max
155 // Only the lower result lane is defined.
161 // Vector bitwise negation
164 // Vector bitwise selection
167 // Compare-and-branch
176 // Custom prefetch handling
179 // {s|u}int to FP within a FP register.
183 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
184 /// world w.r.t vectors; which causes additional REV instructions to be
185 /// generated to compensate for the byte-swapping. But sometimes we do
186 /// need to re-interpret the data in SIMD vector registers in big-endian
187 /// mode without emitting such REV instructions.
193 // NEON Load/Store with post-increment base updates
194 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
219 } // end namespace AArch64ISD
221 class AArch64Subtarget;
222 class AArch64TargetMachine;
224 class AArch64TargetLowering : public TargetLowering {
225 bool RequireStrictAlign;
228 explicit AArch64TargetLowering(const TargetMachine &TM,
229 const AArch64Subtarget &STI);
231 /// Selects the correct CCAssignFn for a given CallingConvention value.
232 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
234 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
235 /// Mask are known to be either zero or one and return them in the
236 /// KnownZero/KnownOne bitsets.
237 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
238 APInt &KnownOne, const SelectionDAG &DAG,
239 unsigned Depth = 0) const override;
241 MVT getScalarShiftAmountTy(EVT LHSTy) const override;
243 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
244 /// unaligned memory accesses of the specified type.
245 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
247 bool *Fast = nullptr) const override {
248 if (RequireStrictAlign)
250 // FIXME: True for Cyclone, but not necessary others.
256 /// LowerOperation - Provide custom lowering hooks for some operations.
257 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
259 const char *getTargetNodeName(unsigned Opcode) const override;
261 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
263 /// getFunctionAlignment - Return the Log2 alignment of this function.
264 unsigned getFunctionAlignment(const Function *F) const;
266 /// Returns true if a cast between SrcAS and DestAS is a noop.
267 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
268 // Addrspacecasts are always noops.
272 /// createFastISel - This method returns a target specific FastISel object,
273 /// or null if the target does not support "fast" ISel.
274 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
275 const TargetLibraryInfo *libInfo) const override;
277 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
279 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
281 /// isShuffleMaskLegal - Return true if the given shuffle mask can be
282 /// codegen'd directly, or if it should be stack expanded.
283 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
285 /// getSetCCResultType - Return the ISD::SETCC ValueType
286 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
288 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
290 MachineBasicBlock *EmitF128CSEL(MachineInstr *MI,
291 MachineBasicBlock *BB) const;
294 EmitInstrWithCustomInserter(MachineInstr *MI,
295 MachineBasicBlock *MBB) const override;
297 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
298 unsigned Intrinsic) const override;
300 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
301 bool isTruncateFree(EVT VT1, EVT VT2) const override;
303 bool isProfitableToHoist(Instruction *I) const override;
305 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
306 bool isZExtFree(EVT VT1, EVT VT2) const override;
307 bool isZExtFree(SDValue Val, EVT VT2) const override;
309 bool hasPairedLoad(Type *LoadedType,
310 unsigned &RequiredAligment) const override;
311 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
313 bool isLegalAddImmediate(int64_t) const override;
314 bool isLegalICmpImmediate(int64_t) const override;
316 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
317 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
318 MachineFunction &MF) const override;
320 /// isLegalAddressingMode - Return true if the addressing mode represented
321 /// by AM is legal for this target, for a load/store of the specified type.
322 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty,
323 unsigned AS) const override;
325 /// \brief Return the cost of the scaling factor used in the addressing
326 /// mode represented by AM for this target, for a load/store
327 /// of the specified type.
328 /// If the AM is supported, the return value must be >= 0.
329 /// If the AM is not supported, it returns a negative value.
330 int getScalingFactorCost(const AddrMode &AM, Type *Ty,
331 unsigned AS) const override;
333 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
334 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
335 /// expanded to FMAs when this method returns true, otherwise fmuladd is
336 /// expanded to fmul + fadd.
337 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
339 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
341 /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
342 bool isDesirableToCommuteWithShift(const SDNode *N) const override;
344 /// \brief Returns true if it is beneficial to convert a load of a constant
345 /// to just the constant itself.
346 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
347 Type *Ty) const override;
349 bool hasLoadLinkedStoreConditional() const override;
350 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
351 AtomicOrdering Ord) const override;
352 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
353 Value *Addr, AtomicOrdering Ord) const override;
355 bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
356 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
357 TargetLoweringBase::AtomicRMWExpansionKind
358 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
360 bool useLoadStackGuardNode() const override;
361 TargetLoweringBase::LegalizeTypeAction
362 getPreferredVectorAction(EVT VT) const override;
365 bool isExtFreeImpl(const Instruction *Ext) const override;
367 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
368 /// make the right decision when generating code for different targets.
369 const AArch64Subtarget *Subtarget;
371 void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT);
372 void addDRTypeForNEON(MVT VT);
373 void addQRTypeForNEON(MVT VT);
376 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
377 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
379 SmallVectorImpl<SDValue> &InVals) const override;
381 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
382 SmallVectorImpl<SDValue> &InVals) const override;
384 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
385 CallingConv::ID CallConv, bool isVarArg,
386 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
387 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
388 bool isThisReturn, SDValue ThisVal) const;
390 bool isEligibleForTailCallOptimization(
391 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
392 bool isCalleeStructRet, bool isCallerStructRet,
393 const SmallVectorImpl<ISD::OutputArg> &Outs,
394 const SmallVectorImpl<SDValue> &OutVals,
395 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
397 /// Finds the incoming stack arguments which overlap the given fixed stack
398 /// object and incorporates their load into the current chain. This prevents
399 /// an upcoming store from clobbering the stack argument before it's used.
400 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
401 MachineFrameInfo *MFI, int ClobberedFI) const;
403 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
405 bool IsTailCallConvention(CallingConv::ID CallCC) const;
407 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
408 SDValue &Chain) const;
410 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
412 const SmallVectorImpl<ISD::OutputArg> &Outs,
413 LLVMContext &Context) const override;
415 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
416 const SmallVectorImpl<ISD::OutputArg> &Outs,
417 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
418 SelectionDAG &DAG) const override;
420 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
421 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
425 SelectionDAG &DAG) const;
426 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
427 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
428 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
429 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
430 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
431 SDValue TVal, SDValue FVal, SDLoc dl,
432 SelectionDAG &DAG) const;
433 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
434 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
435 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
441 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
442 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
443 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
445 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
446 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
447 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
448 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
449 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
450 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
451 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
452 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
453 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
454 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
455 RTLIB::Libcall Call) const;
456 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
457 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
458 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
459 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
460 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
461 SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
462 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
463 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
464 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
466 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
467 std::vector<SDNode *> *Created) const override;
468 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
471 getConstraintType(const std::string &Constraint) const override;
472 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
474 /// Examine constraint string and operand type and determine a weight value.
475 /// The operand object must already have been set up with the operand type.
477 getSingleConstraintMatchWeight(AsmOperandInfo &info,
478 const char *constraint) const override;
480 std::pair<unsigned, const TargetRegisterClass *>
481 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
482 const std::string &Constraint,
483 MVT VT) const override;
484 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
485 std::vector<SDValue> &Ops,
486 SelectionDAG &DAG) const override;
488 unsigned getInlineAsmMemConstraint(
489 const std::string &ConstraintCode) const override {
490 if (ConstraintCode == "Q")
491 return InlineAsm::Constraint_Q;
492 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
493 // followed by llvm_unreachable so we'll leave them unimplemented in
494 // the backend for now.
495 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
498 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
499 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
500 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
501 ISD::MemIndexedMode &AM, bool &IsInc,
502 SelectionDAG &DAG) const;
503 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
504 ISD::MemIndexedMode &AM,
505 SelectionDAG &DAG) const override;
506 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
507 SDValue &Offset, ISD::MemIndexedMode &AM,
508 SelectionDAG &DAG) const override;
510 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
511 SelectionDAG &DAG) const override;
513 bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
514 CallingConv::ID CallConv,
515 bool isVarArg) const override;
517 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
521 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
522 const TargetLibraryInfo *libInfo);
523 } // end namespace AArch64
525 } // end namespace llvm