1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64PerfectShuffle.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64MachineFunctionInfo.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
46 static cl::opt<AlignMode>
47 Align(cl::desc("Load/store alignment support"),
48 cl::Hidden, cl::init(NoStrictAlign),
50 clEnumValN(StrictAlign, "aarch64-strict-align",
51 "Disallow all unaligned memory accesses"),
52 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
53 "Allow unaligned memory accesses"),
56 // Place holder until extr generation is tested fully.
58 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
59 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
63 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
64 cl::desc("Allow AArch64 SLI/SRI formation"),
67 //===----------------------------------------------------------------------===//
68 // AArch64 Lowering public interface.
69 //===----------------------------------------------------------------------===//
70 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
71 if (TT.isOSBinFormatMachO())
72 return new AArch64_MachoTargetObjectFile();
74 return new AArch64_ELFTargetObjectFile();
77 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
78 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
79 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
81 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
82 // we have to make something up. Arbitrarily, choose ZeroOrOne.
83 setBooleanContents(ZeroOrOneBooleanContent);
84 // When comparing vectors the result sets the different elements in the
85 // vector to all-one or all-zero.
86 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
88 // Set up the register classes.
89 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
90 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
92 if (Subtarget->hasFPARMv8()) {
93 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
94 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
95 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
96 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
99 if (Subtarget->hasNEON()) {
100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
101 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
102 // Someone set us up the NEON.
103 addDRTypeForNEON(MVT::v2f32);
104 addDRTypeForNEON(MVT::v8i8);
105 addDRTypeForNEON(MVT::v4i16);
106 addDRTypeForNEON(MVT::v2i32);
107 addDRTypeForNEON(MVT::v1i64);
108 addDRTypeForNEON(MVT::v1f64);
110 addQRTypeForNEON(MVT::v4f32);
111 addQRTypeForNEON(MVT::v2f64);
112 addQRTypeForNEON(MVT::v16i8);
113 addQRTypeForNEON(MVT::v8i16);
114 addQRTypeForNEON(MVT::v4i32);
115 addQRTypeForNEON(MVT::v2i64);
118 // Compute derived properties from the register classes
119 computeRegisterProperties();
121 // Provide all sorts of operation actions
122 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
123 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
130 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
131 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
132 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
133 setOperationAction(ISD::SELECT, MVT::i32, Custom);
134 setOperationAction(ISD::SELECT, MVT::i64, Custom);
135 setOperationAction(ISD::SELECT, MVT::f32, Custom);
136 setOperationAction(ISD::SELECT, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
141 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
142 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
144 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
145 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
146 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::FREM, MVT::f32, Expand);
149 setOperationAction(ISD::FREM, MVT::f64, Expand);
150 setOperationAction(ISD::FREM, MVT::f80, Expand);
152 // Custom lowering hooks are needed for XOR
153 // to fold it into CSINC/CSINV.
154 setOperationAction(ISD::XOR, MVT::i32, Custom);
155 setOperationAction(ISD::XOR, MVT::i64, Custom);
157 // Virtually no operation on f128 is legal, but LLVM can't expand them when
158 // there's a valid register class, so we need custom operations in most cases.
159 setOperationAction(ISD::FABS, MVT::f128, Expand);
160 setOperationAction(ISD::FADD, MVT::f128, Custom);
161 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
162 setOperationAction(ISD::FCOS, MVT::f128, Expand);
163 setOperationAction(ISD::FDIV, MVT::f128, Custom);
164 setOperationAction(ISD::FMA, MVT::f128, Expand);
165 setOperationAction(ISD::FMUL, MVT::f128, Custom);
166 setOperationAction(ISD::FNEG, MVT::f128, Expand);
167 setOperationAction(ISD::FPOW, MVT::f128, Expand);
168 setOperationAction(ISD::FREM, MVT::f128, Expand);
169 setOperationAction(ISD::FRINT, MVT::f128, Expand);
170 setOperationAction(ISD::FSIN, MVT::f128, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
172 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
173 setOperationAction(ISD::FSUB, MVT::f128, Custom);
174 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
176 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
177 setOperationAction(ISD::SELECT, MVT::f128, Custom);
178 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
179 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
181 // Lowering for many of the conversions is actually specified by the non-f128
182 // type. The LowerXXX function will be trivial when f128 isn't involved.
183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
184 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
185 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
186 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
190 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
191 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
196 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
198 // Variable arguments.
199 setOperationAction(ISD::VASTART, MVT::Other, Custom);
200 setOperationAction(ISD::VAARG, MVT::Other, Custom);
201 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
202 setOperationAction(ISD::VAEND, MVT::Other, Expand);
204 // Variable-sized objects.
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
209 // Exception handling.
210 // FIXME: These are guesses. Has this been defined yet?
211 setExceptionPointerRegister(AArch64::X0);
212 setExceptionSelectorRegister(AArch64::X1);
214 // Constant pool entries
215 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
218 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
220 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
221 setOperationAction(ISD::ADDC, MVT::i32, Custom);
222 setOperationAction(ISD::ADDE, MVT::i32, Custom);
223 setOperationAction(ISD::SUBC, MVT::i32, Custom);
224 setOperationAction(ISD::SUBE, MVT::i32, Custom);
225 setOperationAction(ISD::ADDC, MVT::i64, Custom);
226 setOperationAction(ISD::ADDE, MVT::i64, Custom);
227 setOperationAction(ISD::SUBC, MVT::i64, Custom);
228 setOperationAction(ISD::SUBE, MVT::i64, Custom);
230 // AArch64 lacks both left-rotate and popcount instructions.
231 setOperationAction(ISD::ROTL, MVT::i32, Expand);
232 setOperationAction(ISD::ROTL, MVT::i64, Expand);
234 // AArch64 doesn't have {U|S}MUL_LOHI.
235 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
236 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
239 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
240 // counterparts, which AArch64 supports directly.
241 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
243 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
244 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
246 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
247 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
249 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
250 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
251 setOperationAction(ISD::SREM, MVT::i32, Expand);
252 setOperationAction(ISD::SREM, MVT::i64, Expand);
253 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::UREM, MVT::i32, Expand);
256 setOperationAction(ISD::UREM, MVT::i64, Expand);
258 // Custom lower Add/Sub/Mul with overflow.
259 setOperationAction(ISD::SADDO, MVT::i32, Custom);
260 setOperationAction(ISD::SADDO, MVT::i64, Custom);
261 setOperationAction(ISD::UADDO, MVT::i32, Custom);
262 setOperationAction(ISD::UADDO, MVT::i64, Custom);
263 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
264 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
265 setOperationAction(ISD::USUBO, MVT::i32, Custom);
266 setOperationAction(ISD::USUBO, MVT::i64, Custom);
267 setOperationAction(ISD::SMULO, MVT::i32, Custom);
268 setOperationAction(ISD::SMULO, MVT::i64, Custom);
269 setOperationAction(ISD::UMULO, MVT::i32, Custom);
270 setOperationAction(ISD::UMULO, MVT::i64, Custom);
272 setOperationAction(ISD::FSIN, MVT::f32, Expand);
273 setOperationAction(ISD::FSIN, MVT::f64, Expand);
274 setOperationAction(ISD::FCOS, MVT::f32, Expand);
275 setOperationAction(ISD::FCOS, MVT::f64, Expand);
276 setOperationAction(ISD::FPOW, MVT::f32, Expand);
277 setOperationAction(ISD::FPOW, MVT::f64, Expand);
278 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
279 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
281 // AArch64 has implementations of a lot of rounding-like FP operations.
282 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
283 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
284 MVT Ty = RoundingTypes[I];
285 setOperationAction(ISD::FFLOOR, Ty, Legal);
286 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
287 setOperationAction(ISD::FCEIL, Ty, Legal);
288 setOperationAction(ISD::FRINT, Ty, Legal);
289 setOperationAction(ISD::FTRUNC, Ty, Legal);
290 setOperationAction(ISD::FROUND, Ty, Legal);
293 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
295 if (Subtarget->isTargetMachO()) {
296 // For iOS, we don't want to the normal expansion of a libcall to
297 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
299 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
300 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
302 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
303 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
306 // AArch64 does not have floating-point extending loads, i1 sign-extending
307 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
308 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
309 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
310 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
312 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
313 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
314 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
315 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
316 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
317 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
318 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
319 // Indexed loads and stores are supported.
320 for (unsigned im = (unsigned)ISD::PRE_INC;
321 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
322 setIndexedLoadAction(im, MVT::i8, Legal);
323 setIndexedLoadAction(im, MVT::i16, Legal);
324 setIndexedLoadAction(im, MVT::i32, Legal);
325 setIndexedLoadAction(im, MVT::i64, Legal);
326 setIndexedLoadAction(im, MVT::f64, Legal);
327 setIndexedLoadAction(im, MVT::f32, Legal);
328 setIndexedStoreAction(im, MVT::i8, Legal);
329 setIndexedStoreAction(im, MVT::i16, Legal);
330 setIndexedStoreAction(im, MVT::i32, Legal);
331 setIndexedStoreAction(im, MVT::i64, Legal);
332 setIndexedStoreAction(im, MVT::f64, Legal);
333 setIndexedStoreAction(im, MVT::f32, Legal);
337 setOperationAction(ISD::TRAP, MVT::Other, Legal);
339 // We combine OR nodes for bitfield operations.
340 setTargetDAGCombine(ISD::OR);
342 // Vector add and sub nodes may conceal a high-half opportunity.
343 // Also, try to fold ADD into CSINC/CSINV..
344 setTargetDAGCombine(ISD::ADD);
345 setTargetDAGCombine(ISD::SUB);
347 setTargetDAGCombine(ISD::XOR);
348 setTargetDAGCombine(ISD::SINT_TO_FP);
349 setTargetDAGCombine(ISD::UINT_TO_FP);
351 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
353 setTargetDAGCombine(ISD::ANY_EXTEND);
354 setTargetDAGCombine(ISD::ZERO_EXTEND);
355 setTargetDAGCombine(ISD::SIGN_EXTEND);
356 setTargetDAGCombine(ISD::BITCAST);
357 setTargetDAGCombine(ISD::CONCAT_VECTORS);
358 setTargetDAGCombine(ISD::STORE);
360 setTargetDAGCombine(ISD::MUL);
362 setTargetDAGCombine(ISD::SELECT);
363 setTargetDAGCombine(ISD::VSELECT);
365 setTargetDAGCombine(ISD::INTRINSIC_VOID);
366 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
367 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
369 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
370 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
371 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
373 setStackPointerRegisterToSaveRestore(AArch64::SP);
375 setSchedulingPreference(Sched::Hybrid);
378 MaskAndBranchFoldingIsLegal = true;
380 setMinFunctionAlignment(2);
382 RequireStrictAlign = (Align == StrictAlign);
384 setHasExtractBitsInsn(true);
386 if (Subtarget->hasNEON()) {
387 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
388 // silliness like this:
389 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
390 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
391 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
392 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
393 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
394 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
395 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
396 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
397 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
398 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
399 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
400 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
401 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
402 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
403 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
404 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
405 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
406 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
407 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
408 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
409 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
410 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
411 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
412 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
413 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
415 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
416 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
417 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
418 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
419 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
421 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
423 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
424 // elements smaller than i32, so promote the input to i32 first.
425 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
426 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
427 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
428 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
429 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
430 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
431 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
432 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
433 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
435 // AArch64 doesn't have MUL.2d:
436 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
437 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
438 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
439 // Likewise, narrowing and extending vector loads/stores aren't handled
441 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
442 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
444 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
447 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
448 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
449 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
450 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
452 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
454 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
455 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
456 setTruncStoreAction((MVT::SimpleValueType)VT,
457 (MVT::SimpleValueType)InnerVT, Expand);
458 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
459 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
460 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
463 // AArch64 has implementations of a lot of rounding-like FP operations.
464 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
465 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
466 MVT Ty = RoundingVecTypes[I];
467 setOperationAction(ISD::FFLOOR, Ty, Legal);
468 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
469 setOperationAction(ISD::FCEIL, Ty, Legal);
470 setOperationAction(ISD::FRINT, Ty, Legal);
471 setOperationAction(ISD::FTRUNC, Ty, Legal);
472 setOperationAction(ISD::FROUND, Ty, Legal);
477 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
478 if (VT == MVT::v2f32) {
479 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
480 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
482 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
483 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
484 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
485 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
486 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
488 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
489 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
492 // Mark vector float intrinsics as expand.
493 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
494 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
495 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
496 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
497 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
498 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
499 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
500 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
501 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
502 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
505 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
506 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
507 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
508 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
509 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
510 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
511 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
512 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
513 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
514 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
515 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
516 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
518 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
519 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
520 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
521 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
523 // CNT supports only B element sizes.
524 if (VT != MVT::v8i8 && VT != MVT::v16i8)
525 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
527 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
528 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
529 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
530 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
531 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
533 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
534 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
536 if (Subtarget->isLittleEndian()) {
537 for (unsigned im = (unsigned)ISD::PRE_INC;
538 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
539 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
540 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
545 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
546 addRegisterClass(VT, &AArch64::FPR64RegClass);
547 addTypeForNEON(VT, MVT::v2i32);
550 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
551 addRegisterClass(VT, &AArch64::FPR128RegClass);
552 addTypeForNEON(VT, MVT::v4i32);
555 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
558 return VT.changeVectorElementTypeToInteger();
561 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
562 /// Mask are known to be either zero or one and return them in the
563 /// KnownZero/KnownOne bitsets.
564 void AArch64TargetLowering::computeKnownBitsForTargetNode(
565 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
566 const SelectionDAG &DAG, unsigned Depth) const {
567 switch (Op.getOpcode()) {
570 case AArch64ISD::CSEL: {
571 APInt KnownZero2, KnownOne2;
572 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
573 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
574 KnownZero &= KnownZero2;
575 KnownOne &= KnownOne2;
578 case ISD::INTRINSIC_W_CHAIN: {
579 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
580 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
583 case Intrinsic::aarch64_ldaxr:
584 case Intrinsic::aarch64_ldxr: {
585 unsigned BitWidth = KnownOne.getBitWidth();
586 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
587 unsigned MemBits = VT.getScalarType().getSizeInBits();
588 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
594 case ISD::INTRINSIC_WO_CHAIN:
595 case ISD::INTRINSIC_VOID: {
596 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
600 case Intrinsic::aarch64_neon_umaxv:
601 case Intrinsic::aarch64_neon_uminv: {
602 // Figure out the datatype of the vector operand. The UMINV instruction
603 // will zero extend the result, so we can mark as known zero all the
604 // bits larger than the element datatype. 32-bit or larget doesn't need
605 // this as those are legal types and will be handled by isel directly.
606 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
607 unsigned BitWidth = KnownZero.getBitWidth();
608 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
609 assert(BitWidth >= 8 && "Unexpected width!");
610 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
612 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
613 assert(BitWidth >= 16 && "Unexpected width!");
614 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
624 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
628 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
629 // FIXME: On AArch64, this depends on the type.
630 // Basically, the addressable offsets are o to 4095 * Ty.getSizeInBytes().
631 // and the offset has to be a multiple of the related size in bytes.
636 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
637 const TargetLibraryInfo *libInfo) const {
638 return AArch64::createFastISel(funcInfo, libInfo);
641 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
645 case AArch64ISD::CALL: return "AArch64ISD::CALL";
646 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
647 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
648 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
649 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
650 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
651 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
652 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
653 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
654 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
655 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
656 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
657 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
658 case AArch64ISD::ADC: return "AArch64ISD::ADC";
659 case AArch64ISD::SBC: return "AArch64ISD::SBC";
660 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
661 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
662 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
663 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
664 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
665 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
666 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
667 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
668 case AArch64ISD::DUP: return "AArch64ISD::DUP";
669 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
670 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
671 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
672 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
673 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
674 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
675 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
676 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
677 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
678 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
679 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
680 case AArch64ISD::BICi: return "AArch64ISD::BICi";
681 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
682 case AArch64ISD::BSL: return "AArch64ISD::BSL";
683 case AArch64ISD::NEG: return "AArch64ISD::NEG";
684 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
685 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
686 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
687 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
688 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
689 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
690 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
691 case AArch64ISD::REV16: return "AArch64ISD::REV16";
692 case AArch64ISD::REV32: return "AArch64ISD::REV32";
693 case AArch64ISD::REV64: return "AArch64ISD::REV64";
694 case AArch64ISD::EXT: return "AArch64ISD::EXT";
695 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
696 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
697 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
698 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
699 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
700 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
701 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
702 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
703 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
704 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
705 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
706 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
707 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
708 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
709 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
710 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
711 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
712 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
713 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
714 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
715 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
716 case AArch64ISD::NOT: return "AArch64ISD::NOT";
717 case AArch64ISD::BIT: return "AArch64ISD::BIT";
718 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
719 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
720 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
721 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
722 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
723 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
724 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
725 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
726 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
727 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
728 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
729 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
730 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
731 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
732 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
733 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
734 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
735 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
736 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
737 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
738 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
739 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
740 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
741 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
742 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
743 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
744 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
745 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
746 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
747 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
748 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
749 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
750 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
751 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
752 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
753 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
758 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
759 MachineBasicBlock *MBB) const {
760 // We materialise the F128CSEL pseudo-instruction as some control flow and a
764 // [... previous instrs leading to comparison ...]
770 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
772 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
773 MachineFunction *MF = MBB->getParent();
774 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
775 DebugLoc DL = MI->getDebugLoc();
776 MachineFunction::iterator It = MBB;
779 unsigned DestReg = MI->getOperand(0).getReg();
780 unsigned IfTrueReg = MI->getOperand(1).getReg();
781 unsigned IfFalseReg = MI->getOperand(2).getReg();
782 unsigned CondCode = MI->getOperand(3).getImm();
783 bool NZCVKilled = MI->getOperand(4).isKill();
785 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
786 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
787 MF->insert(It, TrueBB);
788 MF->insert(It, EndBB);
790 // Transfer rest of current basic-block to EndBB
791 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
793 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
795 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
796 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
797 MBB->addSuccessor(TrueBB);
798 MBB->addSuccessor(EndBB);
800 // TrueBB falls through to the end.
801 TrueBB->addSuccessor(EndBB);
804 TrueBB->addLiveIn(AArch64::NZCV);
805 EndBB->addLiveIn(AArch64::NZCV);
808 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
814 MI->eraseFromParent();
819 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
820 MachineBasicBlock *BB) const {
821 switch (MI->getOpcode()) {
826 assert(0 && "Unexpected instruction for custom inserter!");
829 case AArch64::F128CSEL:
830 return EmitF128CSEL(MI, BB);
832 case TargetOpcode::STACKMAP:
833 case TargetOpcode::PATCHPOINT:
834 return emitPatchPoint(MI, BB);
836 llvm_unreachable("Unexpected instruction for custom inserter!");
839 //===----------------------------------------------------------------------===//
840 // AArch64 Lowering private implementation.
841 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
845 //===----------------------------------------------------------------------===//
847 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
849 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
852 llvm_unreachable("Unknown condition code!");
854 return AArch64CC::NE;
856 return AArch64CC::EQ;
858 return AArch64CC::GT;
860 return AArch64CC::GE;
862 return AArch64CC::LT;
864 return AArch64CC::LE;
866 return AArch64CC::HI;
868 return AArch64CC::HS;
870 return AArch64CC::LO;
872 return AArch64CC::LS;
876 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
877 static void changeFPCCToAArch64CC(ISD::CondCode CC,
878 AArch64CC::CondCode &CondCode,
879 AArch64CC::CondCode &CondCode2) {
880 CondCode2 = AArch64CC::AL;
883 llvm_unreachable("Unknown FP condition!");
886 CondCode = AArch64CC::EQ;
890 CondCode = AArch64CC::GT;
894 CondCode = AArch64CC::GE;
897 CondCode = AArch64CC::MI;
900 CondCode = AArch64CC::LS;
903 CondCode = AArch64CC::MI;
904 CondCode2 = AArch64CC::GT;
907 CondCode = AArch64CC::VC;
910 CondCode = AArch64CC::VS;
913 CondCode = AArch64CC::EQ;
914 CondCode2 = AArch64CC::VS;
917 CondCode = AArch64CC::HI;
920 CondCode = AArch64CC::PL;
924 CondCode = AArch64CC::LT;
928 CondCode = AArch64CC::LE;
932 CondCode = AArch64CC::NE;
937 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
938 /// CC usable with the vector instructions. Fewer operations are available
939 /// without a real NZCV register, so we have to use less efficient combinations
940 /// to get the same effect.
941 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
942 AArch64CC::CondCode &CondCode,
943 AArch64CC::CondCode &CondCode2,
948 // Mostly the scalar mappings work fine.
949 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
952 Invert = true; // Fallthrough
954 CondCode = AArch64CC::MI;
955 CondCode2 = AArch64CC::GE;
962 // All of the compare-mask comparisons are ordered, but we can switch
963 // between the two by a double inversion. E.g. ULE == !OGT.
965 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
970 static bool isLegalArithImmed(uint64_t C) {
971 // Matches AArch64DAGToDAGISel::SelectArithImmed().
972 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
975 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
976 SDLoc dl, SelectionDAG &DAG) {
977 EVT VT = LHS.getValueType();
979 if (VT.isFloatingPoint())
980 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
982 // The CMP instruction is just an alias for SUBS, and representing it as
983 // SUBS means that it's possible to get CSE with subtract operations.
984 // A later phase can perform the optimization of setting the destination
985 // register to WZR/XZR if it ends up being unused.
986 unsigned Opcode = AArch64ISD::SUBS;
988 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
989 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
990 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
991 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
992 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
993 // can be set differently by this operation. It comes down to whether
994 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
995 // everything is fine. If not then the optimization is wrong. Thus general
996 // comparisons are only valid if op2 != 0.
998 // So, finally, the only LLVM-native comparisons that don't mention C and V
999 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1000 // the absence of information about op2.
1001 Opcode = AArch64ISD::ADDS;
1002 RHS = RHS.getOperand(1);
1003 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1004 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1005 !isUnsignedIntSetCC(CC)) {
1006 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1007 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1008 // of the signed comparisons.
1009 Opcode = AArch64ISD::ANDS;
1010 RHS = LHS.getOperand(1);
1011 LHS = LHS.getOperand(0);
1014 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1018 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1019 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1020 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1021 EVT VT = RHS.getValueType();
1022 uint64_t C = RHSC->getZExtValue();
1023 if (!isLegalArithImmed(C)) {
1024 // Constant does not fit, try adjusting it by one?
1030 if ((VT == MVT::i32 && C != 0x80000000 &&
1031 isLegalArithImmed((uint32_t)(C - 1))) ||
1032 (VT == MVT::i64 && C != 0x80000000ULL &&
1033 isLegalArithImmed(C - 1ULL))) {
1034 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1035 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1036 RHS = DAG.getConstant(C, VT);
1041 if ((VT == MVT::i32 && C != 0 &&
1042 isLegalArithImmed((uint32_t)(C - 1))) ||
1043 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1044 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1045 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1046 RHS = DAG.getConstant(C, VT);
1051 if ((VT == MVT::i32 && C != 0x7fffffff &&
1052 isLegalArithImmed((uint32_t)(C + 1))) ||
1053 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1054 isLegalArithImmed(C + 1ULL))) {
1055 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1056 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1057 RHS = DAG.getConstant(C, VT);
1062 if ((VT == MVT::i32 && C != 0xffffffff &&
1063 isLegalArithImmed((uint32_t)(C + 1))) ||
1064 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1065 isLegalArithImmed(C + 1ULL))) {
1066 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1067 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1068 RHS = DAG.getConstant(C, VT);
1075 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1076 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
1077 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1081 static std::pair<SDValue, SDValue>
1082 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1083 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1084 "Unsupported value type");
1085 SDValue Value, Overflow;
1087 SDValue LHS = Op.getOperand(0);
1088 SDValue RHS = Op.getOperand(1);
1090 switch (Op.getOpcode()) {
1092 llvm_unreachable("Unknown overflow instruction!");
1094 Opc = AArch64ISD::ADDS;
1098 Opc = AArch64ISD::ADDS;
1102 Opc = AArch64ISD::SUBS;
1106 Opc = AArch64ISD::SUBS;
1109 // Multiply needs a little bit extra work.
1113 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1114 if (Op.getValueType() == MVT::i32) {
1115 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1116 // For a 32 bit multiply with overflow check we want the instruction
1117 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1118 // need to generate the following pattern:
1119 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1120 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1121 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1122 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1123 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1124 DAG.getConstant(0, MVT::i64));
1125 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1126 // operation. We need to clear out the upper 32 bits, because we used a
1127 // widening multiply that wrote all 64 bits. In the end this should be a
1129 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1131 // The signed overflow check requires more than just a simple check for
1132 // any bit set in the upper 32 bits of the result. These bits could be
1133 // just the sign bits of a negative number. To perform the overflow
1134 // check we have to arithmetic shift right the 32nd bit of the result by
1135 // 31 bits. Then we compare the result to the upper 32 bits.
1136 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1137 DAG.getConstant(32, MVT::i64));
1138 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1139 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1140 DAG.getConstant(31, MVT::i64));
1141 // It is important that LowerBits is last, otherwise the arithmetic
1142 // shift will not be folded into the compare (SUBS).
1143 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1144 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1147 // The overflow check for unsigned multiply is easy. We only need to
1148 // check if any of the upper 32 bits are set. This can be done with a
1149 // CMP (shifted register). For that we need to generate the following
1151 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1152 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1153 DAG.getConstant(32, MVT::i64));
1154 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1156 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1157 UpperBits).getValue(1);
1161 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1162 // For the 64 bit multiply
1163 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1165 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1166 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1167 DAG.getConstant(63, MVT::i64));
1168 // It is important that LowerBits is last, otherwise the arithmetic
1169 // shift will not be folded into the compare (SUBS).
1170 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1171 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1174 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1175 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1177 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1178 UpperBits).getValue(1);
1185 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1187 // Emit the AArch64 operation with overflow check.
1188 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1189 Overflow = Value.getValue(1);
1191 return std::make_pair(Value, Overflow);
1194 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1195 RTLIB::Libcall Call) const {
1196 SmallVector<SDValue, 2> Ops;
1197 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1198 Ops.push_back(Op.getOperand(i));
1200 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1204 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1205 SDValue Sel = Op.getOperand(0);
1206 SDValue Other = Op.getOperand(1);
1208 // If neither operand is a SELECT_CC, give up.
1209 if (Sel.getOpcode() != ISD::SELECT_CC)
1210 std::swap(Sel, Other);
1211 if (Sel.getOpcode() != ISD::SELECT_CC)
1214 // The folding we want to perform is:
1215 // (xor x, (select_cc a, b, cc, 0, -1) )
1217 // (csel x, (xor x, -1), cc ...)
1219 // The latter will get matched to a CSINV instruction.
1221 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1222 SDValue LHS = Sel.getOperand(0);
1223 SDValue RHS = Sel.getOperand(1);
1224 SDValue TVal = Sel.getOperand(2);
1225 SDValue FVal = Sel.getOperand(3);
1228 // FIXME: This could be generalized to non-integer comparisons.
1229 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1232 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1233 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1235 // The the values aren't constants, this isn't the pattern we're looking for.
1236 if (!CFVal || !CTVal)
1239 // We can commute the SELECT_CC by inverting the condition. This
1240 // might be needed to make this fit into a CSINV pattern.
1241 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1242 std::swap(TVal, FVal);
1243 std::swap(CTVal, CFVal);
1244 CC = ISD::getSetCCInverse(CC, true);
1247 // If the constants line up, perform the transform!
1248 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1250 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1253 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1254 DAG.getConstant(-1ULL, Other.getValueType()));
1256 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1263 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1264 EVT VT = Op.getValueType();
1266 // Let legalize expand this if it isn't a legal type yet.
1267 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1270 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1273 bool ExtraOp = false;
1274 switch (Op.getOpcode()) {
1276 assert(0 && "Invalid code");
1278 Opc = AArch64ISD::ADDS;
1281 Opc = AArch64ISD::SUBS;
1284 Opc = AArch64ISD::ADCS;
1288 Opc = AArch64ISD::SBCS;
1294 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1295 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1299 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1300 // Let legalize expand this if it isn't a legal type yet.
1301 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1304 AArch64CC::CondCode CC;
1305 // The actual operation that sets the overflow or carry flag.
1306 SDValue Value, Overflow;
1307 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1309 // We use 0 and 1 as false and true values.
1310 SDValue TVal = DAG.getConstant(1, MVT::i32);
1311 SDValue FVal = DAG.getConstant(0, MVT::i32);
1313 // We use an inverted condition, because the conditional select is inverted
1314 // too. This will allow it to be selected to a single instruction:
1315 // CSINC Wd, WZR, WZR, invert(cond).
1316 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1317 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1320 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1321 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1324 // Prefetch operands are:
1325 // 1: Address to prefetch
1327 // 3: int locality (0 = no locality ... 3 = extreme locality)
1328 // 4: bool isDataCache
1329 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1331 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1332 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1333 // The data thing is not used.
1334 // unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1336 bool IsStream = !Locality;
1337 // When the locality number is set
1339 // The front-end should have filtered out the out-of-range values
1340 assert(Locality <= 3 && "Prefetch locality out-of-range");
1341 // The locality degree is the opposite of the cache speed.
1342 // Put the number the other way around.
1343 // The encoding starts at 0 for level 1
1344 Locality = 3 - Locality;
1347 // built the mask value encoding the expected behavior.
1348 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1349 (Locality << 1) | // Cache level bits
1350 (unsigned)IsStream; // Stream bit
1351 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1352 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1355 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1356 SelectionDAG &DAG) const {
1357 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1360 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1362 return LowerF128Call(Op, DAG, LC);
1365 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1366 SelectionDAG &DAG) const {
1367 if (Op.getOperand(0).getValueType() != MVT::f128) {
1368 // It's legal except when f128 is involved
1373 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1375 // FP_ROUND node has a second operand indicating whether it is known to be
1376 // precise. That doesn't take part in the LibCall so we can't directly use
1378 SDValue SrcVal = Op.getOperand(0);
1379 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1380 /*isSigned*/ false, SDLoc(Op)).first;
1383 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1384 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1385 // Any additional optimization in this function should be recorded
1386 // in the cost tables.
1387 EVT InVT = Op.getOperand(0).getValueType();
1388 EVT VT = Op.getValueType();
1390 // FP_TO_XINT conversion from the same type are legal.
1391 if (VT.getSizeInBits() == InVT.getSizeInBits())
1394 if (InVT == MVT::v2f64 || InVT == MVT::v4f32) {
1397 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1399 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1400 } else if (InVT == MVT::v2f32) {
1402 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
1403 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1406 // Type changing conversions are illegal.
1410 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1411 SelectionDAG &DAG) const {
1412 if (Op.getOperand(0).getValueType().isVector())
1413 return LowerVectorFP_TO_INT(Op, DAG);
1415 if (Op.getOperand(0).getValueType() != MVT::f128) {
1416 // It's legal except when f128 is involved
1421 if (Op.getOpcode() == ISD::FP_TO_SINT)
1422 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1424 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1426 SmallVector<SDValue, 2> Ops;
1427 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1428 Ops.push_back(Op.getOperand(i));
1430 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1434 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1435 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1436 // Any additional optimization in this function should be recorded
1437 // in the cost tables.
1438 EVT VT = Op.getValueType();
1440 SDValue In = Op.getOperand(0);
1441 EVT InVT = In.getValueType();
1443 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1445 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1446 InVT.getVectorNumElements());
1447 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1448 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1451 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1453 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1454 EVT CastVT = VT.changeVectorElementTypeToInteger();
1455 In = DAG.getNode(CastOpc, dl, CastVT, In);
1456 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1462 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1463 SelectionDAG &DAG) const {
1464 if (Op.getValueType().isVector())
1465 return LowerVectorINT_TO_FP(Op, DAG);
1467 // i128 conversions are libcalls.
1468 if (Op.getOperand(0).getValueType() == MVT::i128)
1471 // Other conversions are legal, unless it's to the completely software-based
1473 if (Op.getValueType() != MVT::f128)
1477 if (Op.getOpcode() == ISD::SINT_TO_FP)
1478 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1480 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1482 return LowerF128Call(Op, DAG, LC);
1485 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1486 SelectionDAG &DAG) const {
1487 // For iOS, we want to call an alternative entry point: __sincos_stret,
1488 // which returns the values in two S / D registers.
1490 SDValue Arg = Op.getOperand(0);
1491 EVT ArgVT = Arg.getValueType();
1492 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1499 Entry.isSExt = false;
1500 Entry.isZExt = false;
1501 Args.push_back(Entry);
1503 const char *LibcallName =
1504 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1505 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1507 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1508 TargetLowering::CallLoweringInfo CLI(DAG);
1509 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1510 .setCallee(CallingConv::Fast, RetTy, Callee, &Args, 0);
1512 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1513 return CallResult.first;
1516 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1517 SelectionDAG &DAG) const {
1518 switch (Op.getOpcode()) {
1520 llvm_unreachable("unimplemented operand");
1522 case ISD::GlobalAddress:
1523 return LowerGlobalAddress(Op, DAG);
1524 case ISD::GlobalTLSAddress:
1525 return LowerGlobalTLSAddress(Op, DAG);
1527 return LowerSETCC(Op, DAG);
1529 return LowerBR_CC(Op, DAG);
1531 return LowerSELECT(Op, DAG);
1532 case ISD::SELECT_CC:
1533 return LowerSELECT_CC(Op, DAG);
1534 case ISD::JumpTable:
1535 return LowerJumpTable(Op, DAG);
1536 case ISD::ConstantPool:
1537 return LowerConstantPool(Op, DAG);
1538 case ISD::BlockAddress:
1539 return LowerBlockAddress(Op, DAG);
1541 return LowerVASTART(Op, DAG);
1543 return LowerVACOPY(Op, DAG);
1545 return LowerVAARG(Op, DAG);
1550 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1557 return LowerXALUO(Op, DAG);
1559 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1561 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1563 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1565 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1567 return LowerFP_ROUND(Op, DAG);
1568 case ISD::FP_EXTEND:
1569 return LowerFP_EXTEND(Op, DAG);
1570 case ISD::FRAMEADDR:
1571 return LowerFRAMEADDR(Op, DAG);
1572 case ISD::RETURNADDR:
1573 return LowerRETURNADDR(Op, DAG);
1574 case ISD::INSERT_VECTOR_ELT:
1575 return LowerINSERT_VECTOR_ELT(Op, DAG);
1576 case ISD::EXTRACT_VECTOR_ELT:
1577 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1578 case ISD::BUILD_VECTOR:
1579 return LowerBUILD_VECTOR(Op, DAG);
1580 case ISD::VECTOR_SHUFFLE:
1581 return LowerVECTOR_SHUFFLE(Op, DAG);
1582 case ISD::EXTRACT_SUBVECTOR:
1583 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1587 return LowerVectorSRA_SRL_SHL(Op, DAG);
1588 case ISD::SHL_PARTS:
1589 return LowerShiftLeftParts(Op, DAG);
1590 case ISD::SRL_PARTS:
1591 case ISD::SRA_PARTS:
1592 return LowerShiftRightParts(Op, DAG);
1594 return LowerCTPOP(Op, DAG);
1595 case ISD::FCOPYSIGN:
1596 return LowerFCOPYSIGN(Op, DAG);
1598 return LowerVectorAND(Op, DAG);
1600 return LowerVectorOR(Op, DAG);
1602 return LowerXOR(Op, DAG);
1604 return LowerPREFETCH(Op, DAG);
1605 case ISD::SINT_TO_FP:
1606 case ISD::UINT_TO_FP:
1607 return LowerINT_TO_FP(Op, DAG);
1608 case ISD::FP_TO_SINT:
1609 case ISD::FP_TO_UINT:
1610 return LowerFP_TO_INT(Op, DAG);
1612 return LowerFSINCOS(Op, DAG);
1616 /// getFunctionAlignment - Return the Log2 alignment of this function.
1617 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1621 //===----------------------------------------------------------------------===//
1622 // Calling Convention Implementation
1623 //===----------------------------------------------------------------------===//
1625 #include "AArch64GenCallingConv.inc"
1627 /// Selects the correct CCAssignFn for a the given CallingConvention
1629 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1630 bool IsVarArg) const {
1633 llvm_unreachable("Unsupported calling convention.");
1634 case CallingConv::WebKit_JS:
1635 return CC_AArch64_WebKit_JS;
1636 case CallingConv::C:
1637 case CallingConv::Fast:
1638 if (!Subtarget->isTargetDarwin())
1639 return CC_AArch64_AAPCS;
1640 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1644 SDValue AArch64TargetLowering::LowerFormalArguments(
1645 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1646 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1647 SmallVectorImpl<SDValue> &InVals) const {
1648 MachineFunction &MF = DAG.getMachineFunction();
1649 MachineFrameInfo *MFI = MF.getFrameInfo();
1651 // Assign locations to all of the incoming arguments.
1652 SmallVector<CCValAssign, 16> ArgLocs;
1653 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1654 getTargetMachine(), ArgLocs, *DAG.getContext());
1656 // At this point, Ins[].VT may already be promoted to i32. To correctly
1657 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1658 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1659 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1660 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1662 unsigned NumArgs = Ins.size();
1663 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1664 unsigned CurArgIdx = 0;
1665 for (unsigned i = 0; i != NumArgs; ++i) {
1666 MVT ValVT = Ins[i].VT;
1667 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1668 CurArgIdx = Ins[i].OrigArgIndex;
1670 // Get type of the original argument.
1671 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1672 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1673 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1674 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1676 else if (ActualMVT == MVT::i16)
1679 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1681 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1682 assert(!Res && "Call operand has unhandled type");
1685 assert(ArgLocs.size() == Ins.size());
1686 SmallVector<SDValue, 16> ArgValues;
1687 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1688 CCValAssign &VA = ArgLocs[i];
1690 if (Ins[i].Flags.isByVal()) {
1691 // Byval is used for HFAs in the PCS, but the system should work in a
1692 // non-compliant manner for larger structs.
1693 EVT PtrTy = getPointerTy();
1694 int Size = Ins[i].Flags.getByValSize();
1695 unsigned NumRegs = (Size + 7) / 8;
1697 // FIXME: This works on big-endian for composite byvals, which are the common
1698 // case. It should also work for fundamental types too.
1700 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1701 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1702 InVals.push_back(FrameIdxN);
1707 if (VA.isRegLoc()) {
1708 // Arguments stored in registers.
1709 EVT RegVT = VA.getLocVT();
1712 const TargetRegisterClass *RC;
1714 if (RegVT == MVT::i32)
1715 RC = &AArch64::GPR32RegClass;
1716 else if (RegVT == MVT::i64)
1717 RC = &AArch64::GPR64RegClass;
1718 else if (RegVT == MVT::f32)
1719 RC = &AArch64::FPR32RegClass;
1720 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1721 RC = &AArch64::FPR64RegClass;
1722 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1723 RC = &AArch64::FPR128RegClass;
1725 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1727 // Transform the arguments in physical registers into virtual ones.
1728 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1729 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1731 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1732 // to 64 bits. Insert an assert[sz]ext to capture this, then
1733 // truncate to the right size.
1734 switch (VA.getLocInfo()) {
1736 llvm_unreachable("Unknown loc info!");
1737 case CCValAssign::Full:
1739 case CCValAssign::BCvt:
1740 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1742 case CCValAssign::AExt:
1743 case CCValAssign::SExt:
1744 case CCValAssign::ZExt:
1745 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1746 // nodes after our lowering.
1747 assert(RegVT == Ins[i].VT && "incorrect register location selected");
1751 InVals.push_back(ArgValue);
1753 } else { // VA.isRegLoc()
1754 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1755 unsigned ArgOffset = VA.getLocMemOffset();
1756 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1758 uint32_t BEAlign = 0;
1759 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1760 BEAlign = 8 - ArgSize;
1762 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1764 // Create load nodes to retrieve arguments from the stack.
1765 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1768 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1769 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1770 MVT MemVT = VA.getValVT();
1772 switch (VA.getLocInfo()) {
1775 case CCValAssign::BCvt:
1776 MemVT = VA.getLocVT();
1778 case CCValAssign::SExt:
1779 ExtType = ISD::SEXTLOAD;
1781 case CCValAssign::ZExt:
1782 ExtType = ISD::ZEXTLOAD;
1784 case CCValAssign::AExt:
1785 ExtType = ISD::EXTLOAD;
1789 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1790 MachinePointerInfo::getFixedStack(FI),
1791 MemVT, false, false, false, nullptr);
1793 InVals.push_back(ArgValue);
1799 if (!Subtarget->isTargetDarwin()) {
1800 // The AAPCS variadic function ABI is identical to the non-variadic
1801 // one. As a result there may be more arguments in registers and we should
1802 // save them for future reference.
1803 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1806 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1807 // This will point to the next argument passed via stack.
1808 unsigned StackOffset = CCInfo.getNextStackOffset();
1809 // We currently pass all varargs at 8-byte alignment.
1810 StackOffset = ((StackOffset + 7) & ~7);
1811 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1814 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1815 unsigned StackArgSize = CCInfo.getNextStackOffset();
1816 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1817 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1818 // This is a non-standard ABI so by fiat I say we're allowed to make full
1819 // use of the stack area to be popped, which must be aligned to 16 bytes in
1821 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1823 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1824 // a multiple of 16.
1825 FuncInfo->setArgumentStackToRestore(StackArgSize);
1827 // This realignment carries over to the available bytes below. Our own
1828 // callers will guarantee the space is free by giving an aligned value to
1831 // Even if we're not expected to free up the space, it's useful to know how
1832 // much is there while considering tail calls (because we can reuse it).
1833 FuncInfo->setBytesInStackArgArea(StackArgSize);
1838 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1839 SelectionDAG &DAG, SDLoc DL,
1840 SDValue &Chain) const {
1841 MachineFunction &MF = DAG.getMachineFunction();
1842 MachineFrameInfo *MFI = MF.getFrameInfo();
1843 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1845 SmallVector<SDValue, 8> MemOps;
1847 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
1848 AArch64::X3, AArch64::X4, AArch64::X5,
1849 AArch64::X6, AArch64::X7 };
1850 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1851 unsigned FirstVariadicGPR =
1852 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1854 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1856 if (GPRSaveSize != 0) {
1857 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1859 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1861 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1862 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
1863 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1865 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1866 MachinePointerInfo::getStack(i * 8), false, false, 0);
1867 MemOps.push_back(Store);
1868 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1869 DAG.getConstant(8, getPointerTy()));
1872 FuncInfo->setVarArgsGPRIndex(GPRIdx);
1873 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1875 if (Subtarget->hasFPARMv8()) {
1876 static const MCPhysReg FPRArgRegs[] = {
1877 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1878 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
1879 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
1880 unsigned FirstVariadicFPR =
1881 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
1883 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1885 if (FPRSaveSize != 0) {
1886 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1888 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1890 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1891 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
1892 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1895 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1896 MachinePointerInfo::getStack(i * 16), false, false, 0);
1897 MemOps.push_back(Store);
1898 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1899 DAG.getConstant(16, getPointerTy()));
1902 FuncInfo->setVarArgsFPRIndex(FPRIdx);
1903 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
1906 if (!MemOps.empty()) {
1907 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1911 /// LowerCallResult - Lower the result values of a call into the
1912 /// appropriate copies out of appropriate physical registers.
1913 SDValue AArch64TargetLowering::LowerCallResult(
1914 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1915 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1916 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1917 SDValue ThisVal) const {
1918 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
1919 ? RetCC_AArch64_WebKit_JS
1920 : RetCC_AArch64_AAPCS;
1921 // Assign locations to each value returned by this call.
1922 SmallVector<CCValAssign, 16> RVLocs;
1923 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1924 getTargetMachine(), RVLocs, *DAG.getContext());
1925 CCInfo.AnalyzeCallResult(Ins, RetCC);
1927 // Copy all of the result registers out of their specified physreg.
1928 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1929 CCValAssign VA = RVLocs[i];
1931 // Pass 'this' value directly from the argument to return value, to avoid
1932 // reg unit interference
1933 if (i == 0 && isThisReturn) {
1934 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
1935 "unexpected return calling convention register assignment");
1936 InVals.push_back(ThisVal);
1941 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
1942 Chain = Val.getValue(1);
1943 InFlag = Val.getValue(2);
1945 switch (VA.getLocInfo()) {
1947 llvm_unreachable("Unknown loc info!");
1948 case CCValAssign::Full:
1950 case CCValAssign::BCvt:
1951 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1955 InVals.push_back(Val);
1961 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
1962 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
1963 bool isCalleeStructRet, bool isCallerStructRet,
1964 const SmallVectorImpl<ISD::OutputArg> &Outs,
1965 const SmallVectorImpl<SDValue> &OutVals,
1966 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1967 // For CallingConv::C this function knows whether the ABI needs
1968 // changing. That's not true for other conventions so they will have to opt in
1970 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1973 const MachineFunction &MF = DAG.getMachineFunction();
1974 const Function *CallerF = MF.getFunction();
1975 CallingConv::ID CallerCC = CallerF->getCallingConv();
1976 bool CCMatch = CallerCC == CalleeCC;
1978 // Byval parameters hand the function a pointer directly into the stack area
1979 // we want to reuse during a tail call. Working around this *is* possible (see
1980 // X86) but less efficient and uglier in LowerCall.
1981 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1982 e = CallerF->arg_end();
1984 if (i->hasByValAttr())
1987 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1988 if (IsTailCallConvention(CalleeCC) && CCMatch)
1993 // Now we search for cases where we can use a tail call without changing the
1994 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1997 // I want anyone implementing a new calling convention to think long and hard
1998 // about this assert.
1999 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2000 "Unexpected variadic calling convention");
2002 if (isVarArg && !Outs.empty()) {
2003 // At least two cases here: if caller is fastcc then we can't have any
2004 // memory arguments (we'd be expected to clean up the stack afterwards). If
2005 // caller is C then we could potentially use its argument area.
2007 // FIXME: for now we take the most conservative of these in both cases:
2008 // disallow all variadic memory operands.
2009 SmallVector<CCValAssign, 16> ArgLocs;
2010 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2011 getTargetMachine(), ArgLocs, *DAG.getContext());
2013 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2014 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2015 if (!ArgLocs[i].isRegLoc())
2019 // If the calling conventions do not match, then we'd better make sure the
2020 // results are returned in the same way as what the caller expects.
2022 SmallVector<CCValAssign, 16> RVLocs1;
2023 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2024 getTargetMachine(), RVLocs1, *DAG.getContext());
2025 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2027 SmallVector<CCValAssign, 16> RVLocs2;
2028 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2029 getTargetMachine(), RVLocs2, *DAG.getContext());
2030 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2032 if (RVLocs1.size() != RVLocs2.size())
2034 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2035 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2037 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2039 if (RVLocs1[i].isRegLoc()) {
2040 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2043 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2049 // Nothing more to check if the callee is taking no arguments
2053 SmallVector<CCValAssign, 16> ArgLocs;
2054 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2055 getTargetMachine(), ArgLocs, *DAG.getContext());
2057 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2059 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2061 // If the stack arguments for this call would fit into our own save area then
2062 // the call can be made tail.
2063 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2066 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2068 MachineFrameInfo *MFI,
2069 int ClobberedFI) const {
2070 SmallVector<SDValue, 8> ArgChains;
2071 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2072 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2074 // Include the original chain at the beginning of the list. When this is
2075 // used by target LowerCall hooks, this helps legalize find the
2076 // CALLSEQ_BEGIN node.
2077 ArgChains.push_back(Chain);
2079 // Add a chain value for each stack argument corresponding
2080 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2081 UE = DAG.getEntryNode().getNode()->use_end();
2083 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2084 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2085 if (FI->getIndex() < 0) {
2086 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2087 int64_t InLastByte = InFirstByte;
2088 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2090 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2091 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2092 ArgChains.push_back(SDValue(L, 1));
2095 // Build a tokenfactor for all the chains.
2096 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2099 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2100 bool TailCallOpt) const {
2101 return CallCC == CallingConv::Fast && TailCallOpt;
2104 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2105 return CallCC == CallingConv::Fast;
2108 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2109 /// and add input and output parameter nodes.
2111 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2112 SmallVectorImpl<SDValue> &InVals) const {
2113 SelectionDAG &DAG = CLI.DAG;
2115 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2116 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2117 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2118 SDValue Chain = CLI.Chain;
2119 SDValue Callee = CLI.Callee;
2120 bool &IsTailCall = CLI.IsTailCall;
2121 CallingConv::ID CallConv = CLI.CallConv;
2122 bool IsVarArg = CLI.IsVarArg;
2124 MachineFunction &MF = DAG.getMachineFunction();
2125 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2126 bool IsThisReturn = false;
2128 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2129 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2130 bool IsSibCall = false;
2133 // Check if it's really possible to do a tail call.
2134 IsTailCall = isEligibleForTailCallOptimization(
2135 Callee, CallConv, IsVarArg, IsStructRet,
2136 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2137 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2138 report_fatal_error("failed to perform tail call elimination on a call "
2139 "site marked musttail");
2141 // A sibling call is one where we're under the usual C ABI and not planning
2142 // to change that but can still do a tail call:
2143 if (!TailCallOpt && IsTailCall)
2150 // Analyze operands of the call, assigning locations to each operand.
2151 SmallVector<CCValAssign, 16> ArgLocs;
2152 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2153 getTargetMachine(), ArgLocs, *DAG.getContext());
2156 // Handle fixed and variable vector arguments differently.
2157 // Variable vector arguments always go into memory.
2158 unsigned NumArgs = Outs.size();
2160 for (unsigned i = 0; i != NumArgs; ++i) {
2161 MVT ArgVT = Outs[i].VT;
2162 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2163 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2164 /*IsVarArg=*/ !Outs[i].IsFixed);
2165 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2166 assert(!Res && "Call operand has unhandled type");
2170 // At this point, Outs[].VT may already be promoted to i32. To correctly
2171 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2172 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2173 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2174 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2176 unsigned NumArgs = Outs.size();
2177 for (unsigned i = 0; i != NumArgs; ++i) {
2178 MVT ValVT = Outs[i].VT;
2179 // Get type of the original argument.
2180 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2181 /*AllowUnknown*/ true);
2182 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2183 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2184 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2185 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2187 else if (ActualMVT == MVT::i16)
2190 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2191 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2192 assert(!Res && "Call operand has unhandled type");
2197 // Get a count of how many bytes are to be pushed on the stack.
2198 unsigned NumBytes = CCInfo.getNextStackOffset();
2201 // Since we're not changing the ABI to make this a tail call, the memory
2202 // operands are already available in the caller's incoming argument space.
2206 // FPDiff is the byte offset of the call's argument area from the callee's.
2207 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2208 // by this amount for a tail call. In a sibling call it must be 0 because the
2209 // caller will deallocate the entire stack and the callee still expects its
2210 // arguments to begin at SP+0. Completely unused for non-tail calls.
2213 if (IsTailCall && !IsSibCall) {
2214 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2216 // Since callee will pop argument stack as a tail call, we must keep the
2217 // popped size 16-byte aligned.
2218 NumBytes = RoundUpToAlignment(NumBytes, 16);
2220 // FPDiff will be negative if this tail call requires more space than we
2221 // would automatically have in our incoming argument space. Positive if we
2222 // can actually shrink the stack.
2223 FPDiff = NumReusableBytes - NumBytes;
2225 // The stack pointer must be 16-byte aligned at all times it's used for a
2226 // memory operation, which in practice means at *all* times and in
2227 // particular across call boundaries. Therefore our own arguments started at
2228 // a 16-byte aligned SP and the delta applied for the tail call should
2229 // satisfy the same constraint.
2230 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2233 // Adjust the stack pointer for the new arguments...
2234 // These operations are automatically eliminated by the prolog/epilog pass
2237 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2239 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2241 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2242 SmallVector<SDValue, 8> MemOpChains;
2244 // Walk the register/memloc assignments, inserting copies/loads.
2245 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2246 ++i, ++realArgIdx) {
2247 CCValAssign &VA = ArgLocs[i];
2248 SDValue Arg = OutVals[realArgIdx];
2249 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2251 // Promote the value if needed.
2252 switch (VA.getLocInfo()) {
2254 llvm_unreachable("Unknown loc info!");
2255 case CCValAssign::Full:
2257 case CCValAssign::SExt:
2258 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2260 case CCValAssign::ZExt:
2261 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2263 case CCValAssign::AExt:
2264 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2265 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2266 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2267 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2269 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2271 case CCValAssign::BCvt:
2272 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2274 case CCValAssign::FPExt:
2275 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2279 if (VA.isRegLoc()) {
2280 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2281 assert(VA.getLocVT() == MVT::i64 &&
2282 "unexpected calling convention register assignment");
2283 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2284 "unexpected use of 'returned'");
2285 IsThisReturn = true;
2287 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2289 assert(VA.isMemLoc());
2292 MachinePointerInfo DstInfo;
2294 // FIXME: This works on big-endian for composite byvals, which are the
2295 // common case. It should also work for fundamental types too.
2296 uint32_t BEAlign = 0;
2297 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2298 : VA.getLocVT().getSizeInBits();
2299 OpSize = (OpSize + 7) / 8;
2300 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2302 BEAlign = 8 - OpSize;
2304 unsigned LocMemOffset = VA.getLocMemOffset();
2305 int32_t Offset = LocMemOffset + BEAlign;
2306 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2307 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2310 Offset = Offset + FPDiff;
2311 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2313 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2314 DstInfo = MachinePointerInfo::getFixedStack(FI);
2316 // Make sure any stack arguments overlapping with where we're storing
2317 // are loaded before this eventual operation. Otherwise they'll be
2319 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2321 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2323 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2324 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2327 if (Outs[i].Flags.isByVal()) {
2329 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2330 SDValue Cpy = DAG.getMemcpy(
2331 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2332 /*isVolatile = */ false,
2333 /*alwaysInline = */ false, DstInfo, MachinePointerInfo());
2335 MemOpChains.push_back(Cpy);
2337 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2338 // promoted to a legal register type i32, we should truncate Arg back to
2340 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2341 VA.getValVT() == MVT::i16)
2342 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2345 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2346 MemOpChains.push_back(Store);
2351 if (!MemOpChains.empty())
2352 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2354 // Build a sequence of copy-to-reg nodes chained together with token chain
2355 // and flag operands which copy the outgoing args into the appropriate regs.
2357 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2358 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2359 RegsToPass[i].second, InFlag);
2360 InFlag = Chain.getValue(1);
2363 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2364 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2365 // node so that legalize doesn't hack it.
2366 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2367 Subtarget->isTargetMachO()) {
2368 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2369 const GlobalValue *GV = G->getGlobal();
2370 bool InternalLinkage = GV->hasInternalLinkage();
2371 if (InternalLinkage)
2372 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2374 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2376 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2378 } else if (ExternalSymbolSDNode *S =
2379 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2380 const char *Sym = S->getSymbol();
2382 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2383 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2385 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2386 const GlobalValue *GV = G->getGlobal();
2387 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2388 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2389 const char *Sym = S->getSymbol();
2390 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2393 // We don't usually want to end the call-sequence here because we would tidy
2394 // the frame up *after* the call, however in the ABI-changing tail-call case
2395 // we've carefully laid out the parameters so that when sp is reset they'll be
2396 // in the correct location.
2397 if (IsTailCall && !IsSibCall) {
2398 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2399 DAG.getIntPtrConstant(0, true), InFlag, DL);
2400 InFlag = Chain.getValue(1);
2403 std::vector<SDValue> Ops;
2404 Ops.push_back(Chain);
2405 Ops.push_back(Callee);
2408 // Each tail call may have to adjust the stack by a different amount, so
2409 // this information must travel along with the operation for eventual
2410 // consumption by emitEpilogue.
2411 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2414 // Add argument registers to the end of the list so that they are known live
2416 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2417 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2418 RegsToPass[i].second.getValueType()));
2420 // Add a register mask operand representing the call-preserved registers.
2421 const uint32_t *Mask;
2422 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2423 const AArch64RegisterInfo *ARI =
2424 static_cast<const AArch64RegisterInfo *>(TRI);
2426 // For 'this' returns, use the X0-preserving mask if applicable
2427 Mask = ARI->getThisReturnPreservedMask(CallConv);
2429 IsThisReturn = false;
2430 Mask = ARI->getCallPreservedMask(CallConv);
2433 Mask = ARI->getCallPreservedMask(CallConv);
2435 assert(Mask && "Missing call preserved mask for calling convention");
2436 Ops.push_back(DAG.getRegisterMask(Mask));
2438 if (InFlag.getNode())
2439 Ops.push_back(InFlag);
2441 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2443 // If we're doing a tall call, use a TC_RETURN here rather than an
2444 // actual call instruction.
2446 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2448 // Returns a chain and a flag for retval copy to use.
2449 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2450 InFlag = Chain.getValue(1);
2452 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2453 ? RoundUpToAlignment(NumBytes, 16)
2456 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2457 DAG.getIntPtrConstant(CalleePopBytes, true),
2460 InFlag = Chain.getValue(1);
2462 // Handle result values, copying them out of physregs into vregs that we
2464 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2465 InVals, IsThisReturn,
2466 IsThisReturn ? OutVals[0] : SDValue());
2469 bool AArch64TargetLowering::CanLowerReturn(
2470 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2471 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2472 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2473 ? RetCC_AArch64_WebKit_JS
2474 : RetCC_AArch64_AAPCS;
2475 SmallVector<CCValAssign, 16> RVLocs;
2476 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2477 return CCInfo.CheckReturn(Outs, RetCC);
2481 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2483 const SmallVectorImpl<ISD::OutputArg> &Outs,
2484 const SmallVectorImpl<SDValue> &OutVals,
2485 SDLoc DL, SelectionDAG &DAG) const {
2486 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2487 ? RetCC_AArch64_WebKit_JS
2488 : RetCC_AArch64_AAPCS;
2489 SmallVector<CCValAssign, 16> RVLocs;
2490 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2491 getTargetMachine(), RVLocs, *DAG.getContext());
2492 CCInfo.AnalyzeReturn(Outs, RetCC);
2494 // Copy the result values into the output registers.
2496 SmallVector<SDValue, 4> RetOps(1, Chain);
2497 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2498 ++i, ++realRVLocIdx) {
2499 CCValAssign &VA = RVLocs[i];
2500 assert(VA.isRegLoc() && "Can only return in registers!");
2501 SDValue Arg = OutVals[realRVLocIdx];
2503 switch (VA.getLocInfo()) {
2505 llvm_unreachable("Unknown loc info!");
2506 case CCValAssign::Full:
2507 if (Outs[i].ArgVT == MVT::i1) {
2508 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2509 // value. This is strictly redundant on Darwin (which uses "zeroext
2510 // i1"), but will be optimised out before ISel.
2511 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2512 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2515 case CCValAssign::BCvt:
2516 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2520 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2521 Flag = Chain.getValue(1);
2522 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2525 RetOps[0] = Chain; // Update chain.
2527 // Add the flag if we have it.
2529 RetOps.push_back(Flag);
2531 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2534 //===----------------------------------------------------------------------===//
2535 // Other Lowering Code
2536 //===----------------------------------------------------------------------===//
2538 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2539 SelectionDAG &DAG) const {
2540 EVT PtrVT = getPointerTy();
2542 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2543 unsigned char OpFlags =
2544 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2546 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2547 "unexpected offset in global node");
2549 // This also catched the large code model case for Darwin.
2550 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2551 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2552 // FIXME: Once remat is capable of dealing with instructions with register
2553 // operands, expand this into two nodes instead of using a wrapper node.
2554 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2557 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2558 const unsigned char MO_NC = AArch64II::MO_NC;
2560 AArch64ISD::WrapperLarge, DL, PtrVT,
2561 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2562 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2563 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2564 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2566 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2567 // the only correct model on Darwin.
2568 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2569 OpFlags | AArch64II::MO_PAGE);
2570 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2571 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2573 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2574 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2578 /// \brief Convert a TLS address reference into the correct sequence of loads
2579 /// and calls to compute the variable's address (for Darwin, currently) and
2580 /// return an SDValue containing the final node.
2582 /// Darwin only has one TLS scheme which must be capable of dealing with the
2583 /// fully general situation, in the worst case. This means:
2584 /// + "extern __thread" declaration.
2585 /// + Defined in a possibly unknown dynamic library.
2587 /// The general system is that each __thread variable has a [3 x i64] descriptor
2588 /// which contains information used by the runtime to calculate the address. The
2589 /// only part of this the compiler needs to know about is the first xword, which
2590 /// contains a function pointer that must be called with the address of the
2591 /// entire descriptor in "x0".
2593 /// Since this descriptor may be in a different unit, in general even the
2594 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2596 /// adrp x0, _var@TLVPPAGE
2597 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2598 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2599 /// ; the function pointer
2600 /// blr x1 ; Uses descriptor address in x0
2601 /// ; Address of _var is now in x0.
2603 /// If the address of _var's descriptor *is* known to the linker, then it can
2604 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2605 /// a slight efficiency gain.
2607 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2608 SelectionDAG &DAG) const {
2609 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2612 MVT PtrVT = getPointerTy();
2613 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2616 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2617 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2619 // The first entry in the descriptor is a function pointer that we must call
2620 // to obtain the address of the variable.
2621 SDValue Chain = DAG.getEntryNode();
2622 SDValue FuncTLVGet =
2623 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2624 false, true, true, 8);
2625 Chain = FuncTLVGet.getValue(1);
2627 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2628 MFI->setAdjustsStack(true);
2630 // TLS calls preserve all registers except those that absolutely must be
2631 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2633 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2634 const AArch64RegisterInfo *ARI =
2635 static_cast<const AArch64RegisterInfo *>(TRI);
2636 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2638 // Finally, we can make the call. This is just a degenerate version of a
2639 // normal AArch64 call node: x0 takes the address of the descriptor, and
2640 // returns the address of the variable in this thread.
2641 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2643 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2644 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2645 DAG.getRegisterMask(Mask), Chain.getValue(1));
2646 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2649 /// When accessing thread-local variables under either the general-dynamic or
2650 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2651 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2652 /// is a function pointer to carry out the resolution. This function takes the
2653 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2654 /// other registers (except LR, NZCV) are preserved.
2656 /// Thus, the ideal call sequence on AArch64 is:
2658 /// adrp x0, :tlsdesc:thread_var
2659 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2660 /// add x0, x0, :tlsdesc_lo12:thread_var
2661 /// .tlsdesccall thread_var
2663 /// (TPIDR_EL0 offset now in x0).
2665 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2666 /// relocation to help the linker relax this sequence if it turns out to be too
2669 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2671 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2672 SDValue DescAddr, SDLoc DL,
2673 SelectionDAG &DAG) const {
2674 EVT PtrVT = getPointerTy();
2676 // The function we need to call is simply the first entry in the GOT for this
2677 // descriptor, load it in preparation.
2678 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2680 // TLS calls preserve all registers except those that absolutely must be
2681 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2683 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2684 const AArch64RegisterInfo *ARI =
2685 static_cast<const AArch64RegisterInfo *>(TRI);
2686 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2688 // The function takes only one argument: the address of the descriptor itself
2690 SDValue Glue, Chain;
2691 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2692 Glue = Chain.getValue(1);
2694 // We're now ready to populate the argument list, as with a normal call:
2695 SmallVector<SDValue, 6> Ops;
2696 Ops.push_back(Chain);
2697 Ops.push_back(Func);
2698 Ops.push_back(SymAddr);
2699 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2700 Ops.push_back(DAG.getRegisterMask(Mask));
2701 Ops.push_back(Glue);
2703 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2704 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2705 Glue = Chain.getValue(1);
2707 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2711 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2712 SelectionDAG &DAG) const {
2713 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2714 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2715 "ELF TLS only supported in small memory model");
2716 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2718 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2721 EVT PtrVT = getPointerTy();
2723 const GlobalValue *GV = GA->getGlobal();
2725 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2727 if (Model == TLSModel::LocalExec) {
2728 SDValue HiVar = DAG.getTargetGlobalAddress(
2729 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2730 SDValue LoVar = DAG.getTargetGlobalAddress(
2732 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2734 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2735 DAG.getTargetConstant(16, MVT::i32)),
2737 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2738 DAG.getTargetConstant(0, MVT::i32)),
2740 } else if (Model == TLSModel::InitialExec) {
2741 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2742 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2743 } else if (Model == TLSModel::LocalDynamic) {
2744 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2745 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2746 // the beginning of the module's TLS region, followed by a DTPREL offset
2749 // These accesses will need deduplicating if there's more than one.
2750 AArch64FunctionInfo *MFI =
2751 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2752 MFI->incNumLocalDynamicTLSAccesses();
2754 // Accesses used in this sequence go via the TLS descriptor which lives in
2755 // the GOT. Prepare an address we can use to handle this.
2756 SDValue HiDesc = DAG.getTargetExternalSymbol(
2757 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2758 SDValue LoDesc = DAG.getTargetExternalSymbol(
2759 "_TLS_MODULE_BASE_", PtrVT,
2760 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2762 // First argument to the descriptor call is the address of the descriptor
2764 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2765 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2767 // The call needs a relocation too for linker relaxation. It doesn't make
2768 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2770 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2773 // Now we can calculate the offset from TPIDR_EL0 to this module's
2774 // thread-local area.
2775 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2777 // Now use :dtprel_whatever: operations to calculate this variable's offset
2778 // in its thread-storage area.
2779 SDValue HiVar = DAG.getTargetGlobalAddress(
2780 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2781 SDValue LoVar = DAG.getTargetGlobalAddress(
2782 GV, DL, MVT::i64, 0,
2783 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2786 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2787 DAG.getTargetConstant(16, MVT::i32)),
2790 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2791 DAG.getTargetConstant(0, MVT::i32)),
2794 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2795 } else if (Model == TLSModel::GeneralDynamic) {
2796 // Accesses used in this sequence go via the TLS descriptor which lives in
2797 // the GOT. Prepare an address we can use to handle this.
2798 SDValue HiDesc = DAG.getTargetGlobalAddress(
2799 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2800 SDValue LoDesc = DAG.getTargetGlobalAddress(
2802 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2804 // First argument to the descriptor call is the address of the descriptor
2806 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2807 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2809 // The call needs a relocation too for linker relaxation. It doesn't make
2810 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2813 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2815 // Finally we can make a call to calculate the offset from tpidr_el0.
2816 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2818 llvm_unreachable("Unsupported ELF TLS access model");
2820 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2823 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2824 SelectionDAG &DAG) const {
2825 if (Subtarget->isTargetDarwin())
2826 return LowerDarwinGlobalTLSAddress(Op, DAG);
2827 else if (Subtarget->isTargetELF())
2828 return LowerELFGlobalTLSAddress(Op, DAG);
2830 llvm_unreachable("Unexpected platform trying to use TLS");
2832 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2833 SDValue Chain = Op.getOperand(0);
2834 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2835 SDValue LHS = Op.getOperand(2);
2836 SDValue RHS = Op.getOperand(3);
2837 SDValue Dest = Op.getOperand(4);
2840 // Handle f128 first, since lowering it will result in comparing the return
2841 // value of a libcall against zero, which is just what the rest of LowerBR_CC
2842 // is expecting to deal with.
2843 if (LHS.getValueType() == MVT::f128) {
2844 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2846 // If softenSetCCOperands returned a scalar, we need to compare the result
2847 // against zero to select between true and false values.
2848 if (!RHS.getNode()) {
2849 RHS = DAG.getConstant(0, LHS.getValueType());
2854 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2856 unsigned Opc = LHS.getOpcode();
2857 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2858 cast<ConstantSDNode>(RHS)->isOne() &&
2859 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2860 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2861 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2862 "Unexpected condition code.");
2863 // Only lower legal XALUO ops.
2864 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
2867 // The actual operation with overflow check.
2868 AArch64CC::CondCode OFCC;
2869 SDValue Value, Overflow;
2870 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
2872 if (CC == ISD::SETNE)
2873 OFCC = getInvertedCondCode(OFCC);
2874 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
2876 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2880 if (LHS.getValueType().isInteger()) {
2881 assert((LHS.getValueType() == RHS.getValueType()) &&
2882 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
2884 // If the RHS of the comparison is zero, we can potentially fold this
2885 // to a specialized branch.
2886 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
2887 if (RHSC && RHSC->getZExtValue() == 0) {
2888 if (CC == ISD::SETEQ) {
2889 // See if we can use a TBZ to fold in an AND as well.
2890 // TBZ has a smaller branch displacement than CBZ. If the offset is
2891 // out of bounds, a late MI-layer pass rewrites branches.
2892 // 403.gcc is an example that hits this case.
2893 if (LHS.getOpcode() == ISD::AND &&
2894 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2895 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2896 SDValue Test = LHS.getOperand(0);
2897 uint64_t Mask = LHS.getConstantOperandVal(1);
2899 // TBZ only operates on i64's, but the ext should be free.
2900 if (Test.getValueType() == MVT::i32)
2901 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2903 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
2904 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2907 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
2908 } else if (CC == ISD::SETNE) {
2909 // See if we can use a TBZ to fold in an AND as well.
2910 // TBZ has a smaller branch displacement than CBZ. If the offset is
2911 // out of bounds, a late MI-layer pass rewrites branches.
2912 // 403.gcc is an example that hits this case.
2913 if (LHS.getOpcode() == ISD::AND &&
2914 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2915 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2916 SDValue Test = LHS.getOperand(0);
2917 uint64_t Mask = LHS.getConstantOperandVal(1);
2919 // TBNZ only operates on i64's, but the ext should be free.
2920 if (Test.getValueType() == MVT::i32)
2921 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2923 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
2924 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2927 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
2932 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2933 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2937 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2939 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
2940 // clean. Some of them require two branches to implement.
2941 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2942 AArch64CC::CondCode CC1, CC2;
2943 changeFPCCToAArch64CC(CC, CC1, CC2);
2944 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
2946 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2947 if (CC2 != AArch64CC::AL) {
2948 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
2949 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
2956 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
2957 SelectionDAG &DAG) const {
2958 EVT VT = Op.getValueType();
2961 SDValue In1 = Op.getOperand(0);
2962 SDValue In2 = Op.getOperand(1);
2963 EVT SrcVT = In2.getValueType();
2965 if (SrcVT == MVT::f32 && VT == MVT::f64)
2966 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
2967 else if (SrcVT == MVT::f64 && VT == MVT::f32)
2968 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
2970 // FIXME: Src type is different, bail out for now. Can VT really be a
2977 SDValue EltMask, VecVal1, VecVal2;
2978 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
2981 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
2983 if (!VT.isVector()) {
2984 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2985 DAG.getUNDEF(VecVT), In1);
2986 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2987 DAG.getUNDEF(VecVT), In2);
2989 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
2990 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
2992 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
2996 // We want to materialize a mask with the the high bit set, but the AdvSIMD
2997 // immediate moves cannot materialize that in a single instruction for
2998 // 64-bit elements. Instead, materialize zero and then negate it.
2999 EltMask = DAG.getConstant(0, EltVT);
3001 if (!VT.isVector()) {
3002 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3003 DAG.getUNDEF(VecVT), In1);
3004 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3005 DAG.getUNDEF(VecVT), In2);
3007 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3008 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3011 llvm_unreachable("Invalid type for copysign!");
3014 std::vector<SDValue> BuildVectorOps;
3015 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3016 BuildVectorOps.push_back(EltMask);
3018 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3020 // If we couldn't materialize the mask above, then the mask vector will be
3021 // the zero vector, and we need to negate it here.
3022 if (VT == MVT::f64 || VT == MVT::v2f64) {
3023 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3024 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3025 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3029 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3032 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3033 else if (VT == MVT::f64)
3034 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3036 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3039 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3040 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3041 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3044 // While there is no integer popcount instruction, it can
3045 // be more efficiently lowered to the following sequence that uses
3046 // AdvSIMD registers/instructions as long as the copies to/from
3047 // the AdvSIMD registers are cheap.
3048 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3049 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3050 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3051 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3052 SDValue Val = Op.getOperand(0);
3054 EVT VT = Op.getValueType();
3055 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3058 if (VT == MVT::i32) {
3059 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3060 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3063 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3066 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3067 SDValue UaddLV = DAG.getNode(
3068 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3069 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3072 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3076 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3078 if (Op.getValueType().isVector())
3079 return LowerVSETCC(Op, DAG);
3081 SDValue LHS = Op.getOperand(0);
3082 SDValue RHS = Op.getOperand(1);
3083 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3086 // We chose ZeroOrOneBooleanContents, so use zero and one.
3087 EVT VT = Op.getValueType();
3088 SDValue TVal = DAG.getConstant(1, VT);
3089 SDValue FVal = DAG.getConstant(0, VT);
3091 // Handle f128 first, since one possible outcome is a normal integer
3092 // comparison which gets picked up by the next if statement.
3093 if (LHS.getValueType() == MVT::f128) {
3094 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3096 // If softenSetCCOperands returned a scalar, use it.
3097 if (!RHS.getNode()) {
3098 assert(LHS.getValueType() == Op.getValueType() &&
3099 "Unexpected setcc expansion!");
3104 if (LHS.getValueType().isInteger()) {
3107 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3109 // Note that we inverted the condition above, so we reverse the order of
3110 // the true and false operands here. This will allow the setcc to be
3111 // matched to a single CSINC instruction.
3112 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3115 // Now we know we're dealing with FP values.
3116 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3118 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3119 // and do the comparison.
3120 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3122 AArch64CC::CondCode CC1, CC2;
3123 changeFPCCToAArch64CC(CC, CC1, CC2);
3124 if (CC2 == AArch64CC::AL) {
3125 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3126 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3128 // Note that we inverted the condition above, so we reverse the order of
3129 // the true and false operands here. This will allow the setcc to be
3130 // matched to a single CSINC instruction.
3131 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3133 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3134 // totally clean. Some of them require two CSELs to implement. As is in
3135 // this case, we emit the first CSEL and then emit a second using the output
3136 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3138 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3139 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3141 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3143 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3144 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3148 /// A SELECT_CC operation is really some kind of max or min if both values being
3149 /// compared are, in some sense, equal to the results in either case. However,
3150 /// it is permissible to compare f32 values and produce directly extended f64
3153 /// Extending the comparison operands would also be allowed, but is less likely
3154 /// to happen in practice since their use is right here. Note that truncate
3155 /// operations would *not* be semantically equivalent.
3156 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3160 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3161 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3162 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3163 Result.getValueType() == MVT::f64) {
3165 APFloat CmpVal = CCmp->getValueAPF();
3166 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3167 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3170 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3173 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3174 SelectionDAG &DAG) const {
3175 SDValue CC = Op->getOperand(0);
3176 SDValue TVal = Op->getOperand(1);
3177 SDValue FVal = Op->getOperand(2);
3180 unsigned Opc = CC.getOpcode();
3181 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3183 if (CC.getResNo() == 1 &&
3184 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3185 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3186 // Only lower legal XALUO ops.
3187 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3190 AArch64CC::CondCode OFCC;
3191 SDValue Value, Overflow;
3192 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3193 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3195 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3199 if (CC.getOpcode() == ISD::SETCC)
3200 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3201 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3203 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3207 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3208 SelectionDAG &DAG) const {
3209 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3210 SDValue LHS = Op.getOperand(0);
3211 SDValue RHS = Op.getOperand(1);
3212 SDValue TVal = Op.getOperand(2);
3213 SDValue FVal = Op.getOperand(3);
3216 // Handle f128 first, because it will result in a comparison of some RTLIB
3217 // call result against zero.
3218 if (LHS.getValueType() == MVT::f128) {
3219 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3221 // If softenSetCCOperands returned a scalar, we need to compare the result
3222 // against zero to select between true and false values.
3223 if (!RHS.getNode()) {
3224 RHS = DAG.getConstant(0, LHS.getValueType());
3229 // Handle integers first.
3230 if (LHS.getValueType().isInteger()) {
3231 assert((LHS.getValueType() == RHS.getValueType()) &&
3232 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3234 unsigned Opcode = AArch64ISD::CSEL;
3236 // If both the TVal and the FVal are constants, see if we can swap them in
3237 // order to for a CSINV or CSINC out of them.
3238 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3239 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3241 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3242 std::swap(TVal, FVal);
3243 std::swap(CTVal, CFVal);
3244 CC = ISD::getSetCCInverse(CC, true);
3245 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3246 std::swap(TVal, FVal);
3247 std::swap(CTVal, CFVal);
3248 CC = ISD::getSetCCInverse(CC, true);
3249 } else if (TVal.getOpcode() == ISD::XOR) {
3250 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3251 // with a CSINV rather than a CSEL.
3252 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3254 if (CVal && CVal->isAllOnesValue()) {
3255 std::swap(TVal, FVal);
3256 std::swap(CTVal, CFVal);
3257 CC = ISD::getSetCCInverse(CC, true);
3259 } else if (TVal.getOpcode() == ISD::SUB) {
3260 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3261 // that we can match with a CSNEG rather than a CSEL.
3262 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3264 if (CVal && CVal->isNullValue()) {
3265 std::swap(TVal, FVal);
3266 std::swap(CTVal, CFVal);
3267 CC = ISD::getSetCCInverse(CC, true);
3269 } else if (CTVal && CFVal) {
3270 const int64_t TrueVal = CTVal->getSExtValue();
3271 const int64_t FalseVal = CFVal->getSExtValue();
3274 // If both TVal and FVal are constants, see if FVal is the
3275 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3276 // instead of a CSEL in that case.
3277 if (TrueVal == ~FalseVal) {
3278 Opcode = AArch64ISD::CSINV;
3279 } else if (TrueVal == -FalseVal) {
3280 Opcode = AArch64ISD::CSNEG;
3281 } else if (TVal.getValueType() == MVT::i32) {
3282 // If our operands are only 32-bit wide, make sure we use 32-bit
3283 // arithmetic for the check whether we can use CSINC. This ensures that
3284 // the addition in the check will wrap around properly in case there is
3285 // an overflow (which would not be the case if we do the check with
3286 // 64-bit arithmetic).
3287 const uint32_t TrueVal32 = CTVal->getZExtValue();
3288 const uint32_t FalseVal32 = CFVal->getZExtValue();
3290 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3291 Opcode = AArch64ISD::CSINC;
3293 if (TrueVal32 > FalseVal32) {
3297 // 64-bit check whether we can use CSINC.
3298 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3299 Opcode = AArch64ISD::CSINC;
3301 if (TrueVal > FalseVal) {
3306 // Swap TVal and FVal if necessary.
3308 std::swap(TVal, FVal);
3309 std::swap(CTVal, CFVal);
3310 CC = ISD::getSetCCInverse(CC, true);
3313 if (Opcode != AArch64ISD::CSEL) {
3314 // Drop FVal since we can get its value by simply inverting/negating
3321 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3323 EVT VT = Op.getValueType();
3324 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3327 // Now we know we're dealing with FP values.
3328 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3329 assert(LHS.getValueType() == RHS.getValueType());
3330 EVT VT = Op.getValueType();
3332 // Try to match this select into a max/min operation, which have dedicated
3333 // opcode in the instruction set.
3334 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3336 if (getTargetMachine().Options.NoNaNsFPMath) {
3337 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3338 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3339 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3340 CC = ISD::getSetCCSwappedOperands(CC);
3341 std::swap(MinMaxLHS, MinMaxRHS);
3344 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3345 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3355 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3363 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3369 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3370 // and do the comparison.
3371 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3373 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3374 // clean. Some of them require two CSELs to implement.
3375 AArch64CC::CondCode CC1, CC2;
3376 changeFPCCToAArch64CC(CC, CC1, CC2);
3377 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3378 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3380 // If we need a second CSEL, emit it, using the output of the first as the
3381 // RHS. We're effectively OR'ing the two CC's together.
3382 if (CC2 != AArch64CC::AL) {
3383 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3384 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3387 // Otherwise, return the output of the first CSEL.
3391 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3392 SelectionDAG &DAG) const {
3393 // Jump table entries as PC relative offsets. No additional tweaking
3394 // is necessary here. Just get the address of the jump table.
3395 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3396 EVT PtrVT = getPointerTy();
3399 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3400 !Subtarget->isTargetMachO()) {
3401 const unsigned char MO_NC = AArch64II::MO_NC;
3403 AArch64ISD::WrapperLarge, DL, PtrVT,
3404 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3405 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3406 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3407 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3408 AArch64II::MO_G0 | MO_NC));
3412 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3413 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3414 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3415 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3416 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3419 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3420 SelectionDAG &DAG) const {
3421 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3422 EVT PtrVT = getPointerTy();
3425 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3426 // Use the GOT for the large code model on iOS.
3427 if (Subtarget->isTargetMachO()) {
3428 SDValue GotAddr = DAG.getTargetConstantPool(
3429 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3431 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3434 const unsigned char MO_NC = AArch64II::MO_NC;
3436 AArch64ISD::WrapperLarge, DL, PtrVT,
3437 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3438 CP->getOffset(), AArch64II::MO_G3),
3439 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3440 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3441 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3442 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3443 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3444 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3446 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3447 // ELF, the only valid one on Darwin.
3449 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3450 CP->getOffset(), AArch64II::MO_PAGE);
3451 SDValue Lo = DAG.getTargetConstantPool(
3452 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3453 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3455 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3456 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3460 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3461 SelectionDAG &DAG) const {
3462 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3463 EVT PtrVT = getPointerTy();
3465 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3466 !Subtarget->isTargetMachO()) {
3467 const unsigned char MO_NC = AArch64II::MO_NC;
3469 AArch64ISD::WrapperLarge, DL, PtrVT,
3470 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3471 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3472 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3473 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3475 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3476 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3478 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3479 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3483 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3484 SelectionDAG &DAG) const {
3485 AArch64FunctionInfo *FuncInfo =
3486 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3490 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3491 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3492 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3493 MachinePointerInfo(SV), false, false, 0);
3496 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3497 SelectionDAG &DAG) const {
3498 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3499 // Standard, section B.3.
3500 MachineFunction &MF = DAG.getMachineFunction();
3501 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3504 SDValue Chain = Op.getOperand(0);
3505 SDValue VAList = Op.getOperand(1);
3506 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3507 SmallVector<SDValue, 4> MemOps;
3509 // void *__stack at offset 0
3511 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3512 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3513 MachinePointerInfo(SV), false, false, 8));
3515 // void *__gr_top at offset 8
3516 int GPRSize = FuncInfo->getVarArgsGPRSize();
3518 SDValue GRTop, GRTopAddr;
3520 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3521 DAG.getConstant(8, getPointerTy()));
3523 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3524 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3525 DAG.getConstant(GPRSize, getPointerTy()));
3527 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3528 MachinePointerInfo(SV, 8), false, false, 8));
3531 // void *__vr_top at offset 16
3532 int FPRSize = FuncInfo->getVarArgsFPRSize();
3534 SDValue VRTop, VRTopAddr;
3535 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3536 DAG.getConstant(16, getPointerTy()));
3538 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3539 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3540 DAG.getConstant(FPRSize, getPointerTy()));
3542 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3543 MachinePointerInfo(SV, 16), false, false, 8));
3546 // int __gr_offs at offset 24
3547 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3548 DAG.getConstant(24, getPointerTy()));
3549 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3550 GROffsAddr, MachinePointerInfo(SV, 24), false,
3553 // int __vr_offs at offset 28
3554 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3555 DAG.getConstant(28, getPointerTy()));
3556 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3557 VROffsAddr, MachinePointerInfo(SV, 28), false,
3560 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3563 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3564 SelectionDAG &DAG) const {
3565 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3566 : LowerAAPCS_VASTART(Op, DAG);
3569 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3570 SelectionDAG &DAG) const {
3571 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3573 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3574 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3575 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3577 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3578 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3579 8, false, false, MachinePointerInfo(DestSV),
3580 MachinePointerInfo(SrcSV));
3583 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3584 assert(Subtarget->isTargetDarwin() &&
3585 "automatic va_arg instruction only works on Darwin");
3587 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3588 EVT VT = Op.getValueType();
3590 SDValue Chain = Op.getOperand(0);
3591 SDValue Addr = Op.getOperand(1);
3592 unsigned Align = Op.getConstantOperandVal(3);
3594 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3595 MachinePointerInfo(V), false, false, false, 0);
3596 Chain = VAList.getValue(1);
3599 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3600 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3601 DAG.getConstant(Align - 1, getPointerTy()));
3602 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3603 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3606 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3607 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3609 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3610 // up to 64 bits. At the very least, we have to increase the striding of the
3611 // vaargs list to match this, and for FP values we need to introduce
3612 // FP_ROUND nodes as well.
3613 if (VT.isInteger() && !VT.isVector())
3615 bool NeedFPTrunc = false;
3616 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3621 // Increment the pointer, VAList, to the next vaarg
3622 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3623 DAG.getConstant(ArgSize, getPointerTy()));
3624 // Store the incremented VAList to the legalized pointer
3625 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3628 // Load the actual argument out of the pointer VAList
3630 // Load the value as an f64.
3631 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3632 MachinePointerInfo(), false, false, false, 0);
3633 // Round the value down to an f32.
3634 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3635 DAG.getIntPtrConstant(1));
3636 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3637 // Merge the rounded value with the chain output of the load.
3638 return DAG.getMergeValues(Ops, DL);
3641 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3645 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3646 SelectionDAG &DAG) const {
3647 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3648 MFI->setFrameAddressIsTaken(true);
3650 EVT VT = Op.getValueType();
3652 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3654 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3656 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3657 MachinePointerInfo(), false, false, false, 0);
3661 // FIXME? Maybe this could be a TableGen attribute on some registers and
3662 // this table could be generated automatically from RegInfo.
3663 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3665 unsigned Reg = StringSwitch<unsigned>(RegName)
3666 .Case("sp", AArch64::SP)
3670 report_fatal_error("Invalid register name global variable");
3673 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3674 SelectionDAG &DAG) const {
3675 MachineFunction &MF = DAG.getMachineFunction();
3676 MachineFrameInfo *MFI = MF.getFrameInfo();
3677 MFI->setReturnAddressIsTaken(true);
3679 EVT VT = Op.getValueType();
3681 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3683 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3684 SDValue Offset = DAG.getConstant(8, getPointerTy());
3685 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3686 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3687 MachinePointerInfo(), false, false, false, 0);
3690 // Return LR, which contains the return address. Mark it an implicit live-in.
3691 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3692 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3695 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3696 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3697 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3698 SelectionDAG &DAG) const {
3699 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3700 EVT VT = Op.getValueType();
3701 unsigned VTBits = VT.getSizeInBits();
3703 SDValue ShOpLo = Op.getOperand(0);
3704 SDValue ShOpHi = Op.getOperand(1);
3705 SDValue ShAmt = Op.getOperand(2);
3707 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3709 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3711 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3712 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3713 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3714 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3715 DAG.getConstant(VTBits, MVT::i64));
3716 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3718 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3719 ISD::SETGE, dl, DAG);
3720 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3722 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3723 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3725 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3727 // AArch64 shifts larger than the register width are wrapped rather than
3728 // clamped, so we can't just emit "hi >> x".
3729 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3730 SDValue TrueValHi = Opc == ISD::SRA
3731 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3732 DAG.getConstant(VTBits - 1, MVT::i64))
3733 : DAG.getConstant(0, VT);
3735 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3737 SDValue Ops[2] = { Lo, Hi };
3738 return DAG.getMergeValues(Ops, dl);
3741 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3742 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3743 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3744 SelectionDAG &DAG) const {
3745 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3746 EVT VT = Op.getValueType();
3747 unsigned VTBits = VT.getSizeInBits();
3749 SDValue ShOpLo = Op.getOperand(0);
3750 SDValue ShOpHi = Op.getOperand(1);
3751 SDValue ShAmt = Op.getOperand(2);
3754 assert(Op.getOpcode() == ISD::SHL_PARTS);
3755 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3756 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3757 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3758 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3759 DAG.getConstant(VTBits, MVT::i64));
3760 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3761 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3763 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3765 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3766 ISD::SETGE, dl, DAG);
3767 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3769 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3771 // AArch64 shifts of larger than register sizes are wrapped rather than
3772 // clamped, so we can't just emit "lo << a" if a is too big.
3773 SDValue TrueValLo = DAG.getConstant(0, VT);
3774 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3776 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3778 SDValue Ops[2] = { Lo, Hi };
3779 return DAG.getMergeValues(Ops, dl);
3782 bool AArch64TargetLowering::isOffsetFoldingLegal(
3783 const GlobalAddressSDNode *GA) const {
3784 // The AArch64 target doesn't support folding offsets into global addresses.
3788 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3789 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3790 // FIXME: We should be able to handle f128 as well with a clever lowering.
3791 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3795 return AArch64_AM::getFP64Imm(Imm) != -1;
3796 else if (VT == MVT::f32)
3797 return AArch64_AM::getFP32Imm(Imm) != -1;
3801 //===----------------------------------------------------------------------===//
3802 // AArch64 Optimization Hooks
3803 //===----------------------------------------------------------------------===//
3805 //===----------------------------------------------------------------------===//
3806 // AArch64 Inline Assembly Support
3807 //===----------------------------------------------------------------------===//
3809 // Table of Constraints
3810 // TODO: This is the current set of constraints supported by ARM for the
3811 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3813 // r - A general register
3814 // w - An FP/SIMD register of some size in the range v0-v31
3815 // x - An FP/SIMD register of some size in the range v0-v15
3816 // I - Constant that can be used with an ADD instruction
3817 // J - Constant that can be used with a SUB instruction
3818 // K - Constant that can be used with a 32-bit logical instruction
3819 // L - Constant that can be used with a 64-bit logical instruction
3820 // M - Constant that can be used as a 32-bit MOV immediate
3821 // N - Constant that can be used as a 64-bit MOV immediate
3822 // Q - A memory reference with base register and no offset
3823 // S - A symbolic address
3824 // Y - Floating point constant zero
3825 // Z - Integer constant zero
3827 // Note that general register operands will be output using their 64-bit x
3828 // register name, whatever the size of the variable, unless the asm operand
3829 // is prefixed by the %w modifier. Floating-point and SIMD register operands
3830 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
3833 /// getConstraintType - Given a constraint letter, return the type of
3834 /// constraint it is for this target.
3835 AArch64TargetLowering::ConstraintType
3836 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
3837 if (Constraint.size() == 1) {
3838 switch (Constraint[0]) {
3845 return C_RegisterClass;
3846 // An address with a single base register. Due to the way we
3847 // currently handle addresses it is the same as 'r'.
3852 return TargetLowering::getConstraintType(Constraint);
3855 /// Examine constraint type and operand type and determine a weight value.
3856 /// This object must already have been set up with the operand type
3857 /// and the current alternative constraint selected.
3858 TargetLowering::ConstraintWeight
3859 AArch64TargetLowering::getSingleConstraintMatchWeight(
3860 AsmOperandInfo &info, const char *constraint) const {
3861 ConstraintWeight weight = CW_Invalid;
3862 Value *CallOperandVal = info.CallOperandVal;
3863 // If we don't have a value, we can't do a match,
3864 // but allow it at the lowest weight.
3865 if (!CallOperandVal)
3867 Type *type = CallOperandVal->getType();
3868 // Look at the constraint type.
3869 switch (*constraint) {
3871 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3875 if (type->isFloatingPointTy() || type->isVectorTy())
3876 weight = CW_Register;
3879 weight = CW_Constant;
3885 std::pair<unsigned, const TargetRegisterClass *>
3886 AArch64TargetLowering::getRegForInlineAsmConstraint(
3887 const std::string &Constraint, MVT VT) const {
3888 if (Constraint.size() == 1) {
3889 switch (Constraint[0]) {
3891 if (VT.getSizeInBits() == 64)
3892 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
3893 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
3896 return std::make_pair(0U, &AArch64::FPR32RegClass);
3897 if (VT.getSizeInBits() == 64)
3898 return std::make_pair(0U, &AArch64::FPR64RegClass);
3899 if (VT.getSizeInBits() == 128)
3900 return std::make_pair(0U, &AArch64::FPR128RegClass);
3902 // The instructions that this constraint is designed for can
3903 // only take 128-bit registers so just use that regclass.
3905 if (VT.getSizeInBits() == 128)
3906 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
3910 if (StringRef("{cc}").equals_lower(Constraint))
3911 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
3913 // Use the default implementation in TargetLowering to convert the register
3914 // constraint into a member of a register class.
3915 std::pair<unsigned, const TargetRegisterClass *> Res;
3916 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3918 // Not found as a standard register?
3920 unsigned Size = Constraint.size();
3921 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
3922 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
3923 const std::string Reg =
3924 std::string(&Constraint[2], &Constraint[Size - 1]);
3925 int RegNo = atoi(Reg.c_str());
3926 if (RegNo >= 0 && RegNo <= 31) {
3927 // v0 - v31 are aliases of q0 - q31.
3928 // By default we'll emit v0-v31 for this unless there's a modifier where
3929 // we'll emit the correct register as well.
3930 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
3931 Res.second = &AArch64::FPR128RegClass;
3939 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3940 /// vector. If it is invalid, don't add anything to Ops.
3941 void AArch64TargetLowering::LowerAsmOperandForConstraint(
3942 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
3943 SelectionDAG &DAG) const {
3946 // Currently only support length 1 constraints.
3947 if (Constraint.length() != 1)
3950 char ConstraintLetter = Constraint[0];
3951 switch (ConstraintLetter) {
3955 // This set of constraints deal with valid constants for various instructions.
3956 // Validate and return a target constant for them if we can.
3958 // 'z' maps to xzr or wzr so it needs an input of 0.
3959 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3960 if (!C || C->getZExtValue() != 0)
3963 if (Op.getValueType() == MVT::i64)
3964 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
3966 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
3976 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3980 // Grab the value and do some validation.
3981 uint64_t CVal = C->getZExtValue();
3982 switch (ConstraintLetter) {
3983 // The I constraint applies only to simple ADD or SUB immediate operands:
3984 // i.e. 0 to 4095 with optional shift by 12
3985 // The J constraint applies only to ADD or SUB immediates that would be
3986 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
3987 // instruction [or vice versa], in other words -1 to -4095 with optional
3988 // left shift by 12.
3990 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
3994 uint64_t NVal = -C->getSExtValue();
3995 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal))
3999 // The K and L constraints apply *only* to logical immediates, including
4000 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4001 // been removed and MOV should be used). So these constraints have to
4002 // distinguish between bit patterns that are valid 32-bit or 64-bit
4003 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4004 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4007 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4011 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4014 // The M and N constraints are a superset of K and L respectively, for use
4015 // with the MOV (immediate) alias. As well as the logical immediates they
4016 // also match 32 or 64-bit immediates that can be loaded either using a
4017 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4018 // (M) or 64-bit 0x1234000000000000 (N) etc.
4019 // As a note some of this code is liberally stolen from the asm parser.
4021 if (!isUInt<32>(CVal))
4023 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4025 if ((CVal & 0xFFFF) == CVal)
4027 if ((CVal & 0xFFFF0000ULL) == CVal)
4029 uint64_t NCVal = ~(uint32_t)CVal;
4030 if ((NCVal & 0xFFFFULL) == NCVal)
4032 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4037 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4039 if ((CVal & 0xFFFFULL) == CVal)
4041 if ((CVal & 0xFFFF0000ULL) == CVal)
4043 if ((CVal & 0xFFFF00000000ULL) == CVal)
4045 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4047 uint64_t NCVal = ~CVal;
4048 if ((NCVal & 0xFFFFULL) == NCVal)
4050 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4052 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4054 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4062 // All assembler immediates are 64-bit integers.
4063 Result = DAG.getTargetConstant(CVal, MVT::i64);
4067 if (Result.getNode()) {
4068 Ops.push_back(Result);
4072 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4075 //===----------------------------------------------------------------------===//
4076 // AArch64 Advanced SIMD Support
4077 //===----------------------------------------------------------------------===//
4079 /// WidenVector - Given a value in the V64 register class, produce the
4080 /// equivalent value in the V128 register class.
4081 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4082 EVT VT = V64Reg.getValueType();
4083 unsigned NarrowSize = VT.getVectorNumElements();
4084 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4085 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4088 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4089 V64Reg, DAG.getConstant(0, MVT::i32));
4092 /// getExtFactor - Determine the adjustment factor for the position when
4093 /// generating an "extract from vector registers" instruction.
4094 static unsigned getExtFactor(SDValue &V) {
4095 EVT EltType = V.getValueType().getVectorElementType();
4096 return EltType.getSizeInBits() / 8;
4099 /// NarrowVector - Given a value in the V128 register class, produce the
4100 /// equivalent value in the V64 register class.
4101 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4102 EVT VT = V128Reg.getValueType();
4103 unsigned WideSize = VT.getVectorNumElements();
4104 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4105 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4108 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4111 // Gather data to see if the operation can be modelled as a
4112 // shuffle in combination with VEXTs.
4113 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4114 SelectionDAG &DAG) const {
4116 EVT VT = Op.getValueType();
4117 unsigned NumElts = VT.getVectorNumElements();
4119 SmallVector<SDValue, 2> SourceVecs;
4120 SmallVector<unsigned, 2> MinElts;
4121 SmallVector<unsigned, 2> MaxElts;
4123 for (unsigned i = 0; i < NumElts; ++i) {
4124 SDValue V = Op.getOperand(i);
4125 if (V.getOpcode() == ISD::UNDEF)
4127 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4128 // A shuffle can only come from building a vector from various
4129 // elements of other vectors.
4133 // Record this extraction against the appropriate vector if possible...
4134 SDValue SourceVec = V.getOperand(0);
4135 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4136 bool FoundSource = false;
4137 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4138 if (SourceVecs[j] == SourceVec) {
4139 if (MinElts[j] > EltNo)
4141 if (MaxElts[j] < EltNo)
4148 // Or record a new source if not...
4150 SourceVecs.push_back(SourceVec);
4151 MinElts.push_back(EltNo);
4152 MaxElts.push_back(EltNo);
4156 // Currently only do something sane when at most two source vectors
4158 if (SourceVecs.size() > 2)
4161 SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4162 int VEXTOffsets[2] = { 0, 0 };
4164 // This loop extracts the usage patterns of the source vectors
4165 // and prepares appropriate SDValues for a shuffle if possible.
4166 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4167 if (SourceVecs[i].getValueType() == VT) {
4168 // No VEXT necessary
4169 ShuffleSrcs[i] = SourceVecs[i];
4172 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4173 // We can pad out the smaller vector for free, so if it's part of a
4175 ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, SourceVecs[i],
4176 DAG.getUNDEF(SourceVecs[i].getValueType()));
4180 // Don't attempt to extract subvectors from BUILD_VECTOR sources
4181 // that expand or trunc the original value.
4182 // TODO: We can try to bitcast and ANY_EXTEND the result but
4183 // we need to consider the cost of vector ANY_EXTEND, and the
4184 // legality of all the types.
4185 if (SourceVecs[i].getValueType().getVectorElementType() !=
4186 VT.getVectorElementType())
4189 // Since only 64-bit and 128-bit vectors are legal on ARM and
4190 // we've eliminated the other cases...
4191 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2 * NumElts &&
4192 "unexpected vector sizes in ReconstructShuffle");
4194 if (MaxElts[i] - MinElts[i] >= NumElts) {
4195 // Span too large for a VEXT to cope
4199 if (MinElts[i] >= NumElts) {
4200 // The extraction can just take the second half
4201 VEXTOffsets[i] = NumElts;
4203 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
4204 DAG.getIntPtrConstant(NumElts));
4205 } else if (MaxElts[i] < NumElts) {
4206 // The extraction can just take the first half
4208 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4209 SourceVecs[i], DAG.getIntPtrConstant(0));
4211 // An actual VEXT is needed
4212 VEXTOffsets[i] = MinElts[i];
4213 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4214 SourceVecs[i], DAG.getIntPtrConstant(0));
4216 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
4217 DAG.getIntPtrConstant(NumElts));
4218 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1);
4219 ShuffleSrcs[i] = DAG.getNode(AArch64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2,
4220 DAG.getConstant(Imm, MVT::i32));
4224 SmallVector<int, 8> Mask;
4226 for (unsigned i = 0; i < NumElts; ++i) {
4227 SDValue Entry = Op.getOperand(i);
4228 if (Entry.getOpcode() == ISD::UNDEF) {
4233 SDValue ExtractVec = Entry.getOperand(0);
4235 cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
4236 if (ExtractVec == SourceVecs[0]) {
4237 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4239 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4243 // Final check before we try to produce nonsense...
4244 if (isShuffleMaskLegal(Mask, VT))
4245 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4251 // check if an EXT instruction can handle the shuffle mask when the
4252 // vector sources of the shuffle are the same.
4253 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4254 unsigned NumElts = VT.getVectorNumElements();
4256 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4262 // If this is a VEXT shuffle, the immediate value is the index of the first
4263 // element. The other shuffle indices must be the successive elements after
4265 unsigned ExpectedElt = Imm;
4266 for (unsigned i = 1; i < NumElts; ++i) {
4267 // Increment the expected index. If it wraps around, just follow it
4268 // back to index zero and keep going.
4270 if (ExpectedElt == NumElts)
4274 continue; // ignore UNDEF indices
4275 if (ExpectedElt != static_cast<unsigned>(M[i]))
4282 // check if an EXT instruction can handle the shuffle mask when the
4283 // vector sources of the shuffle are different.
4284 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4286 // Look for the first non-undef element.
4287 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4288 [](int Elt) {return Elt >= 0;});
4290 // Benefit form APInt to handle overflow when calculating expected element.
4291 unsigned NumElts = VT.getVectorNumElements();
4292 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4293 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4294 // The following shuffle indices must be the successive elements after the
4295 // first real element.
4296 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4297 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4298 if (FirstWrongElt != M.end())
4301 // The index of an EXT is the first element if it is not UNDEF.
4302 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4303 // value of the first element. E.g.
4304 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4305 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4306 // ExpectedElt is the last mask index plus 1.
4307 Imm = ExpectedElt.getZExtValue();
4309 // There are two difference cases requiring to reverse input vectors.
4310 // For example, for vector <4 x i32> we have the following cases,
4311 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4312 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4313 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4314 // to reverse two input vectors.
4323 /// isREVMask - Check if a vector shuffle corresponds to a REV
4324 /// instruction with the specified blocksize. (The order of the elements
4325 /// within each block of the vector is reversed.)
4326 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4327 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4328 "Only possible block sizes for REV are: 16, 32, 64");
4330 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4334 unsigned NumElts = VT.getVectorNumElements();
4335 unsigned BlockElts = M[0] + 1;
4336 // If the first shuffle index is UNDEF, be optimistic.
4338 BlockElts = BlockSize / EltSz;
4340 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4343 for (unsigned i = 0; i < NumElts; ++i) {
4345 continue; // ignore UNDEF indices
4346 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4353 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4354 unsigned NumElts = VT.getVectorNumElements();
4355 WhichResult = (M[0] == 0 ? 0 : 1);
4356 unsigned Idx = WhichResult * NumElts / 2;
4357 for (unsigned i = 0; i != NumElts; i += 2) {
4358 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4359 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4367 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4368 unsigned NumElts = VT.getVectorNumElements();
4369 WhichResult = (M[0] == 0 ? 0 : 1);
4370 for (unsigned i = 0; i != NumElts; ++i) {
4372 continue; // ignore UNDEF indices
4373 if ((unsigned)M[i] != 2 * i + WhichResult)
4380 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4381 unsigned NumElts = VT.getVectorNumElements();
4382 WhichResult = (M[0] == 0 ? 0 : 1);
4383 for (unsigned i = 0; i < NumElts; i += 2) {
4384 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4385 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4391 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4392 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4393 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4394 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4395 unsigned NumElts = VT.getVectorNumElements();
4396 WhichResult = (M[0] == 0 ? 0 : 1);
4397 unsigned Idx = WhichResult * NumElts / 2;
4398 for (unsigned i = 0; i != NumElts; i += 2) {
4399 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4400 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4408 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4409 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4410 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4411 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4412 unsigned Half = VT.getVectorNumElements() / 2;
4413 WhichResult = (M[0] == 0 ? 0 : 1);
4414 for (unsigned j = 0; j != 2; ++j) {
4415 unsigned Idx = WhichResult;
4416 for (unsigned i = 0; i != Half; ++i) {
4417 int MIdx = M[i + j * Half];
4418 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4427 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4428 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4429 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4430 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4431 unsigned NumElts = VT.getVectorNumElements();
4432 WhichResult = (M[0] == 0 ? 0 : 1);
4433 for (unsigned i = 0; i < NumElts; i += 2) {
4434 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4435 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4441 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4442 bool &DstIsLeft, int &Anomaly) {
4443 if (M.size() != static_cast<size_t>(NumInputElements))
4446 int NumLHSMatch = 0, NumRHSMatch = 0;
4447 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4449 for (int i = 0; i < NumInputElements; ++i) {
4459 LastLHSMismatch = i;
4461 if (M[i] == i + NumInputElements)
4464 LastRHSMismatch = i;
4467 if (NumLHSMatch == NumInputElements - 1) {
4469 Anomaly = LastLHSMismatch;
4471 } else if (NumRHSMatch == NumInputElements - 1) {
4473 Anomaly = LastRHSMismatch;
4480 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4481 if (VT.getSizeInBits() != 128)
4484 unsigned NumElts = VT.getVectorNumElements();
4486 for (int I = 0, E = NumElts / 2; I != E; I++) {
4491 int Offset = NumElts / 2;
4492 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4493 if (Mask[I] != I + SplitLHS * Offset)
4500 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4502 EVT VT = Op.getValueType();
4503 SDValue V0 = Op.getOperand(0);
4504 SDValue V1 = Op.getOperand(1);
4505 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4507 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4508 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4511 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4513 if (!isConcatMask(Mask, VT, SplitV0))
4516 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4517 VT.getVectorNumElements() / 2);
4519 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4520 DAG.getConstant(0, MVT::i64));
4522 if (V1.getValueType().getSizeInBits() == 128) {
4523 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4524 DAG.getConstant(0, MVT::i64));
4526 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4529 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4530 /// the specified operations to build the shuffle.
4531 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4532 SDValue RHS, SelectionDAG &DAG,
4534 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4535 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4536 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4539 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4548 OP_VUZPL, // VUZP, left result
4549 OP_VUZPR, // VUZP, right result
4550 OP_VZIPL, // VZIP, left result
4551 OP_VZIPR, // VZIP, right result
4552 OP_VTRNL, // VTRN, left result
4553 OP_VTRNR // VTRN, right result
4556 if (OpNum == OP_COPY) {
4557 if (LHSID == (1 * 9 + 2) * 9 + 3)
4559 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4563 SDValue OpLHS, OpRHS;
4564 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4565 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4566 EVT VT = OpLHS.getValueType();
4570 llvm_unreachable("Unknown shuffle opcode!");
4572 // VREV divides the vector in half and swaps within the half.
4573 if (VT.getVectorElementType() == MVT::i32 ||
4574 VT.getVectorElementType() == MVT::f32)
4575 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4576 // vrev <4 x i16> -> REV32
4577 if (VT.getVectorElementType() == MVT::i16)
4578 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4579 // vrev <4 x i8> -> REV16
4580 assert(VT.getVectorElementType() == MVT::i8);
4581 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4586 EVT EltTy = VT.getVectorElementType();
4588 if (EltTy == MVT::i8)
4589 Opcode = AArch64ISD::DUPLANE8;
4590 else if (EltTy == MVT::i16)
4591 Opcode = AArch64ISD::DUPLANE16;
4592 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4593 Opcode = AArch64ISD::DUPLANE32;
4594 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4595 Opcode = AArch64ISD::DUPLANE64;
4597 llvm_unreachable("Invalid vector element type?");
4599 if (VT.getSizeInBits() == 64)
4600 OpLHS = WidenVector(OpLHS, DAG);
4601 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4602 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4607 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4608 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4609 DAG.getConstant(Imm, MVT::i32));
4612 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4615 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4618 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4621 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4624 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4627 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4632 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4633 SelectionDAG &DAG) {
4634 // Check to see if we can use the TBL instruction.
4635 SDValue V1 = Op.getOperand(0);
4636 SDValue V2 = Op.getOperand(1);
4639 EVT EltVT = Op.getValueType().getVectorElementType();
4640 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4642 SmallVector<SDValue, 8> TBLMask;
4643 for (int Val : ShuffleMask) {
4644 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4645 unsigned Offset = Byte + Val * BytesPerElt;
4646 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4650 MVT IndexVT = MVT::v8i8;
4651 unsigned IndexLen = 8;
4652 if (Op.getValueType().getSizeInBits() == 128) {
4653 IndexVT = MVT::v16i8;
4657 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4658 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4661 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4663 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4664 Shuffle = DAG.getNode(
4665 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4666 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4667 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4668 makeArrayRef(TBLMask.data(), IndexLen)));
4670 if (IndexLen == 8) {
4671 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4672 Shuffle = DAG.getNode(
4673 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4674 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4675 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4676 makeArrayRef(TBLMask.data(), IndexLen)));
4678 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4679 // cannot currently represent the register constraints on the input
4681 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4682 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4683 // &TBLMask[0], IndexLen));
4684 Shuffle = DAG.getNode(
4685 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4686 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4687 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4688 makeArrayRef(TBLMask.data(), IndexLen)));
4691 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4694 static unsigned getDUPLANEOp(EVT EltType) {
4695 if (EltType == MVT::i8)
4696 return AArch64ISD::DUPLANE8;
4697 if (EltType == MVT::i16)
4698 return AArch64ISD::DUPLANE16;
4699 if (EltType == MVT::i32 || EltType == MVT::f32)
4700 return AArch64ISD::DUPLANE32;
4701 if (EltType == MVT::i64 || EltType == MVT::f64)
4702 return AArch64ISD::DUPLANE64;
4704 llvm_unreachable("Invalid vector element type?");
4707 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4708 SelectionDAG &DAG) const {
4710 EVT VT = Op.getValueType();
4712 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4714 // Convert shuffles that are directly supported on NEON to target-specific
4715 // DAG nodes, instead of keeping them as shuffles and matching them again
4716 // during code selection. This is more efficient and avoids the possibility
4717 // of inconsistencies between legalization and selection.
4718 ArrayRef<int> ShuffleMask = SVN->getMask();
4720 SDValue V1 = Op.getOperand(0);
4721 SDValue V2 = Op.getOperand(1);
4723 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4724 V1.getValueType().getSimpleVT())) {
4725 int Lane = SVN->getSplatIndex();
4726 // If this is undef splat, generate it via "just" vdup, if possible.
4730 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4731 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4733 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4734 // constant. If so, we can just reference the lane's definition directly.
4735 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4736 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4737 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4739 // Otherwise, duplicate from the lane of the input vector.
4740 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4742 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4743 // to make a vector of the same size as this SHUFFLE. We can ignore the
4744 // extract entirely, and canonicalise the concat using WidenVector.
4745 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4746 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4747 V1 = V1.getOperand(0);
4748 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4749 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4750 Lane -= Idx * VT.getVectorNumElements() / 2;
4751 V1 = WidenVector(V1.getOperand(Idx), DAG);
4752 } else if (VT.getSizeInBits() == 64)
4753 V1 = WidenVector(V1, DAG);
4755 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4758 if (isREVMask(ShuffleMask, VT, 64))
4759 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4760 if (isREVMask(ShuffleMask, VT, 32))
4761 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4762 if (isREVMask(ShuffleMask, VT, 16))
4763 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
4765 bool ReverseEXT = false;
4767 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4770 Imm *= getExtFactor(V1);
4771 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
4772 DAG.getConstant(Imm, MVT::i32));
4773 } else if (V2->getOpcode() == ISD::UNDEF &&
4774 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4775 Imm *= getExtFactor(V1);
4776 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
4777 DAG.getConstant(Imm, MVT::i32));
4780 unsigned WhichResult;
4781 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4782 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4783 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4785 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4786 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4787 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4789 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4790 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4791 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4794 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4795 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4796 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4798 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4799 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4800 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4802 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4803 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4804 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4807 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
4808 if (Concat.getNode())
4813 int NumInputElements = V1.getValueType().getVectorNumElements();
4814 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
4815 SDValue DstVec = DstIsLeft ? V1 : V2;
4816 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
4818 SDValue SrcVec = V1;
4819 int SrcLane = ShuffleMask[Anomaly];
4820 if (SrcLane >= NumInputElements) {
4822 SrcLane -= VT.getVectorNumElements();
4824 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
4826 EVT ScalarVT = VT.getVectorElementType();
4827 if (ScalarVT.getSizeInBits() < 32)
4828 ScalarVT = MVT::i32;
4831 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
4832 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
4836 // If the shuffle is not directly supported and it has 4 elements, use
4837 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4838 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned PFIndexes[4];
4841 for (unsigned i = 0; i != 4; ++i) {
4842 if (ShuffleMask[i] < 0)
4845 PFIndexes[i] = ShuffleMask[i];
4848 // Compute the index in the perfect shuffle table.
4849 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
4850 PFIndexes[2] * 9 + PFIndexes[3];
4851 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4852 unsigned Cost = (PFEntry >> 30);
4855 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4858 return GenerateTBL(Op, ShuffleMask, DAG);
4861 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
4863 EVT VT = BVN->getValueType(0);
4864 APInt SplatBits, SplatUndef;
4865 unsigned SplatBitSize;
4867 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4868 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
4870 for (unsigned i = 0; i < NumSplats; ++i) {
4871 CnstBits <<= SplatBitSize;
4872 UndefBits <<= SplatBitSize;
4873 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
4874 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
4883 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
4884 SelectionDAG &DAG) const {
4885 BuildVectorSDNode *BVN =
4886 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
4887 SDValue LHS = Op.getOperand(0);
4889 EVT VT = Op.getValueType();
4894 APInt CnstBits(VT.getSizeInBits(), 0);
4895 APInt UndefBits(VT.getSizeInBits(), 0);
4896 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
4897 // We only have BIC vector immediate instruction, which is and-not.
4898 CnstBits = ~CnstBits;
4900 // We make use of a little bit of goto ickiness in order to avoid having to
4901 // duplicate the immediate matching logic for the undef toggled case.
4902 bool SecondTry = false;
4905 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
4906 CnstBits = CnstBits.zextOrTrunc(64);
4907 uint64_t CnstVal = CnstBits.getZExtValue();
4909 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
4910 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
4911 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4912 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4913 DAG.getConstant(CnstVal, MVT::i32),
4914 DAG.getConstant(0, MVT::i32));
4915 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4918 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
4919 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
4920 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4921 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4922 DAG.getConstant(CnstVal, MVT::i32),
4923 DAG.getConstant(8, MVT::i32));
4924 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4927 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
4928 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
4929 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4930 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4931 DAG.getConstant(CnstVal, MVT::i32),
4932 DAG.getConstant(16, MVT::i32));
4933 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4936 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
4937 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
4938 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4939 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4940 DAG.getConstant(CnstVal, MVT::i32),
4941 DAG.getConstant(24, MVT::i32));
4942 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4945 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
4946 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
4947 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4948 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4949 DAG.getConstant(CnstVal, MVT::i32),
4950 DAG.getConstant(0, MVT::i32));
4951 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4954 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
4955 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
4956 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4957 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4958 DAG.getConstant(CnstVal, MVT::i32),
4959 DAG.getConstant(8, MVT::i32));
4960 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4967 CnstBits = ~UndefBits;
4971 // We can always fall back to a non-immediate AND.
4976 // Specialized code to quickly find if PotentialBVec is a BuildVector that
4977 // consists of only the same constant int value, returned in reference arg
4979 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
4980 uint64_t &ConstVal) {
4981 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
4984 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
4987 EVT VT = Bvec->getValueType(0);
4988 unsigned NumElts = VT.getVectorNumElements();
4989 for (unsigned i = 1; i < NumElts; ++i)
4990 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
4992 ConstVal = FirstElt->getZExtValue();
4996 static unsigned getIntrinsicID(const SDNode *N) {
4997 unsigned Opcode = N->getOpcode();
5000 return Intrinsic::not_intrinsic;
5001 case ISD::INTRINSIC_WO_CHAIN: {
5002 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5003 if (IID < Intrinsic::num_intrinsics)
5005 return Intrinsic::not_intrinsic;
5010 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5011 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5012 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5013 // Also, logical shift right -> sri, with the same structure.
5014 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5015 EVT VT = N->getValueType(0);
5022 // Is the first op an AND?
5023 const SDValue And = N->getOperand(0);
5024 if (And.getOpcode() != ISD::AND)
5027 // Is the second op an shl or lshr?
5028 SDValue Shift = N->getOperand(1);
5029 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5030 // or AArch64ISD::VLSHR vector, #shift
5031 unsigned ShiftOpc = Shift.getOpcode();
5032 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5034 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5036 // Is the shift amount constant?
5037 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5041 // Is the and mask vector all constant?
5043 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5046 // Is C1 == ~C2, taking into account how much one can shift elements of a
5048 uint64_t C2 = C2node->getZExtValue();
5049 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5050 if (C2 > ElemSizeInBits)
5052 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5053 if ((C1 & ElemMask) != (~C2 & ElemMask))
5056 SDValue X = And.getOperand(0);
5057 SDValue Y = Shift.getOperand(0);
5060 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5062 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5063 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5065 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5066 DEBUG(N->dump(&DAG));
5067 DEBUG(dbgs() << "into: \n");
5068 DEBUG(ResultSLI->dump(&DAG));
5074 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5075 SelectionDAG &DAG) const {
5076 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5077 if (EnableAArch64SlrGeneration) {
5078 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5083 BuildVectorSDNode *BVN =
5084 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5085 SDValue LHS = Op.getOperand(1);
5087 EVT VT = Op.getValueType();
5089 // OR commutes, so try swapping the operands.
5091 LHS = Op.getOperand(0);
5092 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5097 APInt CnstBits(VT.getSizeInBits(), 0);
5098 APInt UndefBits(VT.getSizeInBits(), 0);
5099 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5100 // We make use of a little bit of goto ickiness in order to avoid having to
5101 // duplicate the immediate matching logic for the undef toggled case.
5102 bool SecondTry = false;
5105 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5106 CnstBits = CnstBits.zextOrTrunc(64);
5107 uint64_t CnstVal = CnstBits.getZExtValue();
5109 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5110 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5111 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5112 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5113 DAG.getConstant(CnstVal, MVT::i32),
5114 DAG.getConstant(0, MVT::i32));
5115 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5118 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5119 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5120 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5121 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5122 DAG.getConstant(CnstVal, MVT::i32),
5123 DAG.getConstant(8, MVT::i32));
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5127 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5128 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5129 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5130 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5131 DAG.getConstant(CnstVal, MVT::i32),
5132 DAG.getConstant(16, MVT::i32));
5133 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5136 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5137 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5138 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5139 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5140 DAG.getConstant(CnstVal, MVT::i32),
5141 DAG.getConstant(24, MVT::i32));
5142 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5145 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5146 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5147 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5148 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5149 DAG.getConstant(CnstVal, MVT::i32),
5150 DAG.getConstant(0, MVT::i32));
5151 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5154 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5155 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5156 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5157 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5158 DAG.getConstant(CnstVal, MVT::i32),
5159 DAG.getConstant(8, MVT::i32));
5160 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5167 CnstBits = UndefBits;
5171 // We can always fall back to a non-immediate OR.
5176 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5177 SelectionDAG &DAG) const {
5178 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5180 EVT VT = Op.getValueType();
5182 APInt CnstBits(VT.getSizeInBits(), 0);
5183 APInt UndefBits(VT.getSizeInBits(), 0);
5184 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5185 // We make use of a little bit of goto ickiness in order to avoid having to
5186 // duplicate the immediate matching logic for the undef toggled case.
5187 bool SecondTry = false;
5190 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5191 CnstBits = CnstBits.zextOrTrunc(64);
5192 uint64_t CnstVal = CnstBits.getZExtValue();
5194 // Certain magic vector constants (used to express things like NOT
5195 // and NEG) are passed through unmodified. This allows codegen patterns
5196 // for these operations to match. Special-purpose patterns will lower
5197 // these immediates to MOVIs if it proves necessary.
5198 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5201 // The many faces of MOVI...
5202 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5203 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5204 if (VT.getSizeInBits() == 128) {
5205 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5206 DAG.getConstant(CnstVal, MVT::i32));
5207 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5210 // Support the V64 version via subregister insertion.
5211 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5212 DAG.getConstant(CnstVal, MVT::i32));
5213 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5216 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5217 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5218 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5219 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5220 DAG.getConstant(CnstVal, MVT::i32),
5221 DAG.getConstant(0, MVT::i32));
5222 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5225 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5226 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5227 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5228 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5229 DAG.getConstant(CnstVal, MVT::i32),
5230 DAG.getConstant(8, MVT::i32));
5231 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5234 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5235 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5236 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5237 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5238 DAG.getConstant(CnstVal, MVT::i32),
5239 DAG.getConstant(16, MVT::i32));
5240 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5243 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5244 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5245 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5246 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5247 DAG.getConstant(CnstVal, MVT::i32),
5248 DAG.getConstant(24, MVT::i32));
5249 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5252 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5253 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5254 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5255 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5256 DAG.getConstant(CnstVal, MVT::i32),
5257 DAG.getConstant(0, MVT::i32));
5258 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5261 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5262 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5263 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5264 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5265 DAG.getConstant(CnstVal, MVT::i32),
5266 DAG.getConstant(8, MVT::i32));
5267 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5270 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5271 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5272 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5273 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5274 DAG.getConstant(CnstVal, MVT::i32),
5275 DAG.getConstant(264, MVT::i32));
5276 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5279 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5280 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5281 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5282 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5283 DAG.getConstant(CnstVal, MVT::i32),
5284 DAG.getConstant(272, MVT::i32));
5285 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5288 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5289 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5290 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5291 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5292 DAG.getConstant(CnstVal, MVT::i32));
5293 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5296 // The few faces of FMOV...
5297 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5298 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5299 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5300 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5301 DAG.getConstant(CnstVal, MVT::i32));
5302 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5305 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5306 VT.getSizeInBits() == 128) {
5307 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5308 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5309 DAG.getConstant(CnstVal, MVT::i32));
5310 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5313 // The many faces of MVNI...
5315 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5316 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5317 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5318 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5319 DAG.getConstant(CnstVal, MVT::i32),
5320 DAG.getConstant(0, MVT::i32));
5321 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5324 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5325 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5326 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5327 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5328 DAG.getConstant(CnstVal, MVT::i32),
5329 DAG.getConstant(8, MVT::i32));
5330 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5333 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5334 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5335 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5336 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5337 DAG.getConstant(CnstVal, MVT::i32),
5338 DAG.getConstant(16, MVT::i32));
5339 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5342 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5343 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5344 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5345 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5346 DAG.getConstant(CnstVal, MVT::i32),
5347 DAG.getConstant(24, MVT::i32));
5348 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5351 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5352 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5353 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5354 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5355 DAG.getConstant(CnstVal, MVT::i32),
5356 DAG.getConstant(0, MVT::i32));
5357 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5360 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5361 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5362 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5363 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5364 DAG.getConstant(CnstVal, MVT::i32),
5365 DAG.getConstant(8, MVT::i32));
5366 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5369 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5370 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5371 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5372 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5373 DAG.getConstant(CnstVal, MVT::i32),
5374 DAG.getConstant(264, MVT::i32));
5375 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5378 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5379 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5380 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5381 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5382 DAG.getConstant(CnstVal, MVT::i32),
5383 DAG.getConstant(272, MVT::i32));
5384 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5391 CnstBits = UndefBits;
5396 // Scan through the operands to find some interesting properties we can
5398 // 1) If only one value is used, we can use a DUP, or
5399 // 2) if only the low element is not undef, we can just insert that, or
5400 // 3) if only one constant value is used (w/ some non-constant lanes),
5401 // we can splat the constant value into the whole vector then fill
5402 // in the non-constant lanes.
5403 // 4) FIXME: If different constant values are used, but we can intelligently
5404 // select the values we'll be overwriting for the non-constant
5405 // lanes such that we can directly materialize the vector
5406 // some other way (MOVI, e.g.), we can be sneaky.
5407 unsigned NumElts = VT.getVectorNumElements();
5408 bool isOnlyLowElement = true;
5409 bool usesOnlyOneValue = true;
5410 bool usesOnlyOneConstantValue = true;
5411 bool isConstant = true;
5412 unsigned NumConstantLanes = 0;
5414 SDValue ConstantValue;
5415 for (unsigned i = 0; i < NumElts; ++i) {
5416 SDValue V = Op.getOperand(i);
5417 if (V.getOpcode() == ISD::UNDEF)
5420 isOnlyLowElement = false;
5421 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5424 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5426 if (!ConstantValue.getNode())
5428 else if (ConstantValue != V)
5429 usesOnlyOneConstantValue = false;
5432 if (!Value.getNode())
5434 else if (V != Value)
5435 usesOnlyOneValue = false;
5438 if (!Value.getNode())
5439 return DAG.getUNDEF(VT);
5441 if (isOnlyLowElement)
5442 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5444 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5445 // i32 and try again.
5446 if (usesOnlyOneValue) {
5448 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5449 Value.getValueType() != VT)
5450 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5452 // This is actually a DUPLANExx operation, which keeps everything vectory.
5454 // DUPLANE works on 128-bit vectors, widen it if necessary.
5455 SDValue Lane = Value.getOperand(1);
5456 Value = Value.getOperand(0);
5457 if (Value.getValueType().getSizeInBits() == 64)
5458 Value = WidenVector(Value, DAG);
5460 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5461 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5464 if (VT.getVectorElementType().isFloatingPoint()) {
5465 SmallVector<SDValue, 8> Ops;
5467 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5468 for (unsigned i = 0; i < NumElts; ++i)
5469 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5470 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5471 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5472 Val = LowerBUILD_VECTOR(Val, DAG);
5474 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5478 // If there was only one constant value used and for more than one lane,
5479 // start by splatting that value, then replace the non-constant lanes. This
5480 // is better than the default, which will perform a separate initialization
5482 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5483 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5484 // Now insert the non-constant lanes.
5485 for (unsigned i = 0; i < NumElts; ++i) {
5486 SDValue V = Op.getOperand(i);
5487 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5488 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5489 // Note that type legalization likely mucked about with the VT of the
5490 // source operand, so we may have to convert it here before inserting.
5491 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5497 // If all elements are constants and the case above didn't get hit, fall back
5498 // to the default expansion, which will generate a load from the constant
5503 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5505 SDValue shuffle = ReconstructShuffle(Op, DAG);
5506 if (shuffle != SDValue())
5510 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5511 // know the default expansion would otherwise fall back on something even
5512 // worse. For a vector with one or two non-undef values, that's
5513 // scalar_to_vector for the elements followed by a shuffle (provided the
5514 // shuffle is valid for the target) and materialization element by element
5515 // on the stack followed by a load for everything else.
5516 if (!isConstant && !usesOnlyOneValue) {
5517 SDValue Vec = DAG.getUNDEF(VT);
5518 SDValue Op0 = Op.getOperand(0);
5519 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5521 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5522 // a) Avoid a RMW dependency on the full vector register, and
5523 // b) Allow the register coalescer to fold away the copy if the
5524 // value is already in an S or D register.
5525 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5526 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5528 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5529 DAG.getTargetConstant(SubIdx, MVT::i32));
5530 Vec = SDValue(N, 0);
5533 for (; i < NumElts; ++i) {
5534 SDValue V = Op.getOperand(i);
5535 if (V.getOpcode() == ISD::UNDEF)
5537 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5538 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5543 // Just use the default expansion. We failed to find a better alternative.
5547 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5548 SelectionDAG &DAG) const {
5549 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5551 // Check for non-constant lane.
5552 if (!isa<ConstantSDNode>(Op.getOperand(2)))
5555 EVT VT = Op.getOperand(0).getValueType();
5557 // Insertion/extraction are legal for V128 types.
5558 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5559 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5562 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5563 VT != MVT::v1i64 && VT != MVT::v2f32)
5566 // For V64 types, we perform insertion by expanding the value
5567 // to a V128 type and perform the insertion on that.
5569 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5570 EVT WideTy = WideVec.getValueType();
5572 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5573 Op.getOperand(1), Op.getOperand(2));
5574 // Re-narrow the resultant vector.
5575 return NarrowVector(Node, DAG);
5579 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5580 SelectionDAG &DAG) const {
5581 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5583 // Check for non-constant lane.
5584 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5587 EVT VT = Op.getOperand(0).getValueType();
5589 // Insertion/extraction are legal for V128 types.
5590 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5591 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5594 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5595 VT != MVT::v1i64 && VT != MVT::v2f32)
5598 // For V64 types, we perform extraction by expanding the value
5599 // to a V128 type and perform the extraction on that.
5601 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5602 EVT WideTy = WideVec.getValueType();
5604 EVT ExtrTy = WideTy.getVectorElementType();
5605 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5608 // For extractions, we just return the result directly.
5609 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5613 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5614 SelectionDAG &DAG) const {
5615 EVT VT = Op.getOperand(0).getValueType();
5621 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5624 unsigned Val = Cst->getZExtValue();
5626 unsigned Size = Op.getValueType().getSizeInBits();
5630 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5633 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5636 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5639 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5642 llvm_unreachable("Unexpected vector type in extract_subvector!");
5645 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5647 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5653 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5655 if (VT.getVectorNumElements() == 4 &&
5656 (VT.is128BitVector() || VT.is64BitVector())) {
5657 unsigned PFIndexes[4];
5658 for (unsigned i = 0; i != 4; ++i) {
5662 PFIndexes[i] = M[i];
5665 // Compute the index in the perfect shuffle table.
5666 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5667 PFIndexes[2] * 9 + PFIndexes[3];
5668 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5669 unsigned Cost = (PFEntry >> 30);
5677 unsigned DummyUnsigned;
5679 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5680 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5681 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5682 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5683 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5684 isZIPMask(M, VT, DummyUnsigned) ||
5685 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5686 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5687 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5688 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5689 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5692 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5693 /// operand of a vector shift operation, where all the elements of the
5694 /// build_vector must have the same constant integer value.
5695 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5696 // Ignore bit_converts.
5697 while (Op.getOpcode() == ISD::BITCAST)
5698 Op = Op.getOperand(0);
5699 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5700 APInt SplatBits, SplatUndef;
5701 unsigned SplatBitSize;
5703 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5704 HasAnyUndefs, ElementBits) ||
5705 SplatBitSize > ElementBits)
5707 Cnt = SplatBits.getSExtValue();
5711 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5712 /// operand of a vector shift left operation. That value must be in the range:
5713 /// 0 <= Value < ElementBits for a left shift; or
5714 /// 0 <= Value <= ElementBits for a long left shift.
5715 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5716 assert(VT.isVector() && "vector shift count is not a vector type");
5717 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5718 if (!getVShiftImm(Op, ElementBits, Cnt))
5720 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5723 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5724 /// operand of a vector shift right operation. For a shift opcode, the value
5725 /// is positive, but for an intrinsic the value count must be negative. The
5726 /// absolute value must be in the range:
5727 /// 1 <= |Value| <= ElementBits for a right shift; or
5728 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5729 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5731 assert(VT.isVector() && "vector shift count is not a vector type");
5732 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5733 if (!getVShiftImm(Op, ElementBits, Cnt))
5737 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
5740 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
5741 SelectionDAG &DAG) const {
5742 EVT VT = Op.getValueType();
5746 if (!Op.getOperand(1).getValueType().isVector())
5748 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5750 switch (Op.getOpcode()) {
5752 llvm_unreachable("unexpected shift opcode");
5755 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5756 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5757 DAG.getConstant(Cnt, MVT::i32));
5758 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5759 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
5760 Op.getOperand(0), Op.getOperand(1));
5763 // Right shift immediate
5764 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5767 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
5768 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5769 DAG.getConstant(Cnt, MVT::i32));
5772 // Right shift register. Note, there is not a shift right register
5773 // instruction, but the shift left register instruction takes a signed
5774 // value, where negative numbers specify a right shift.
5775 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
5776 : Intrinsic::aarch64_neon_ushl;
5777 // negate the shift amount
5778 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
5779 SDValue NegShiftLeft =
5780 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5781 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
5782 return NegShiftLeft;
5788 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
5789 AArch64CC::CondCode CC, bool NoNans, EVT VT,
5790 SDLoc dl, SelectionDAG &DAG) {
5791 EVT SrcVT = LHS.getValueType();
5793 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
5794 APInt CnstBits(VT.getSizeInBits(), 0);
5795 APInt UndefBits(VT.getSizeInBits(), 0);
5796 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
5797 bool IsZero = IsCnst && (CnstBits == 0);
5799 if (SrcVT.getVectorElementType().isFloatingPoint()) {
5803 case AArch64CC::NE: {
5806 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5808 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5809 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
5813 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5814 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5817 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
5818 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
5821 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
5822 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
5825 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
5826 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
5830 // If we ignore NaNs then we can use to the MI implementation.
5834 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
5835 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
5842 case AArch64CC::NE: {
5845 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5847 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5848 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
5852 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5853 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5856 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
5857 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
5860 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
5861 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
5864 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
5865 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
5867 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
5869 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
5872 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
5873 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
5875 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
5877 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
5881 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
5882 SelectionDAG &DAG) const {
5883 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5884 SDValue LHS = Op.getOperand(0);
5885 SDValue RHS = Op.getOperand(1);
5888 if (LHS.getValueType().getVectorElementType().isInteger()) {
5889 assert(LHS.getValueType() == RHS.getValueType());
5890 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
5891 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
5895 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
5896 LHS.getValueType().getVectorElementType() == MVT::f64);
5898 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5899 // clean. Some of them require two branches to implement.
5900 AArch64CC::CondCode CC1, CC2;
5902 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
5904 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
5906 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
5910 if (CC2 != AArch64CC::AL) {
5912 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
5913 if (!Cmp2.getNode())
5916 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
5920 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
5925 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5926 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5927 /// specified in the intrinsic calls.
5928 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5930 unsigned Intrinsic) const {
5931 switch (Intrinsic) {
5932 case Intrinsic::aarch64_neon_ld2:
5933 case Intrinsic::aarch64_neon_ld3:
5934 case Intrinsic::aarch64_neon_ld4:
5935 case Intrinsic::aarch64_neon_ld1x2:
5936 case Intrinsic::aarch64_neon_ld1x3:
5937 case Intrinsic::aarch64_neon_ld1x4:
5938 case Intrinsic::aarch64_neon_ld2lane:
5939 case Intrinsic::aarch64_neon_ld3lane:
5940 case Intrinsic::aarch64_neon_ld4lane:
5941 case Intrinsic::aarch64_neon_ld2r:
5942 case Intrinsic::aarch64_neon_ld3r:
5943 case Intrinsic::aarch64_neon_ld4r: {
5944 Info.opc = ISD::INTRINSIC_W_CHAIN;
5945 // Conservatively set memVT to the entire set of vectors loaded.
5946 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5947 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5948 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5951 Info.vol = false; // volatile loads with NEON intrinsics not supported
5952 Info.readMem = true;
5953 Info.writeMem = false;
5956 case Intrinsic::aarch64_neon_st2:
5957 case Intrinsic::aarch64_neon_st3:
5958 case Intrinsic::aarch64_neon_st4:
5959 case Intrinsic::aarch64_neon_st1x2:
5960 case Intrinsic::aarch64_neon_st1x3:
5961 case Intrinsic::aarch64_neon_st1x4:
5962 case Intrinsic::aarch64_neon_st2lane:
5963 case Intrinsic::aarch64_neon_st3lane:
5964 case Intrinsic::aarch64_neon_st4lane: {
5965 Info.opc = ISD::INTRINSIC_VOID;
5966 // Conservatively set memVT to the entire set of vectors stored.
5967 unsigned NumElts = 0;
5968 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5969 Type *ArgTy = I.getArgOperand(ArgI)->getType();
5970 if (!ArgTy->isVectorTy())
5972 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
5974 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5975 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5978 Info.vol = false; // volatile stores with NEON intrinsics not supported
5979 Info.readMem = false;
5980 Info.writeMem = true;
5983 case Intrinsic::aarch64_ldaxr:
5984 case Intrinsic::aarch64_ldxr: {
5985 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
5986 Info.opc = ISD::INTRINSIC_W_CHAIN;
5987 Info.memVT = MVT::getVT(PtrTy->getElementType());
5988 Info.ptrVal = I.getArgOperand(0);
5990 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
5992 Info.readMem = true;
5993 Info.writeMem = false;
5996 case Intrinsic::aarch64_stlxr:
5997 case Intrinsic::aarch64_stxr: {
5998 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
5999 Info.opc = ISD::INTRINSIC_W_CHAIN;
6000 Info.memVT = MVT::getVT(PtrTy->getElementType());
6001 Info.ptrVal = I.getArgOperand(1);
6003 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6005 Info.readMem = false;
6006 Info.writeMem = true;
6009 case Intrinsic::aarch64_ldaxp:
6010 case Intrinsic::aarch64_ldxp: {
6011 Info.opc = ISD::INTRINSIC_W_CHAIN;
6012 Info.memVT = MVT::i128;
6013 Info.ptrVal = I.getArgOperand(0);
6017 Info.readMem = true;
6018 Info.writeMem = false;
6021 case Intrinsic::aarch64_stlxp:
6022 case Intrinsic::aarch64_stxp: {
6023 Info.opc = ISD::INTRINSIC_W_CHAIN;
6024 Info.memVT = MVT::i128;
6025 Info.ptrVal = I.getArgOperand(2);
6029 Info.readMem = false;
6030 Info.writeMem = true;
6040 // Truncations from 64-bit GPR to 32-bit GPR is free.
6041 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6042 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6044 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6045 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6046 return NumBits1 > NumBits2;
6048 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6049 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6051 unsigned NumBits1 = VT1.getSizeInBits();
6052 unsigned NumBits2 = VT2.getSizeInBits();
6053 return NumBits1 > NumBits2;
6056 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6058 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6059 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6061 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6062 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6063 return NumBits1 == 32 && NumBits2 == 64;
6065 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6066 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6068 unsigned NumBits1 = VT1.getSizeInBits();
6069 unsigned NumBits2 = VT2.getSizeInBits();
6070 return NumBits1 == 32 && NumBits2 == 64;
6073 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6074 EVT VT1 = Val.getValueType();
6075 if (isZExtFree(VT1, VT2)) {
6079 if (Val.getOpcode() != ISD::LOAD)
6082 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6083 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6084 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6085 VT1.getSizeInBits() <= 32);
6088 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6089 unsigned &RequiredAligment) const {
6090 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6092 // Cyclone supports unaligned accesses.
6093 RequiredAligment = 0;
6094 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6095 return NumBits == 32 || NumBits == 64;
6098 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6099 unsigned &RequiredAligment) const {
6100 if (!LoadedType.isSimple() ||
6101 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6103 // Cyclone supports unaligned accesses.
6104 RequiredAligment = 0;
6105 unsigned NumBits = LoadedType.getSizeInBits();
6106 return NumBits == 32 || NumBits == 64;
6109 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6110 unsigned AlignCheck) {
6111 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6112 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6115 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6116 unsigned SrcAlign, bool IsMemset,
6119 MachineFunction &MF) const {
6120 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6121 // instruction to materialize the v2i64 zero and one store (with restrictive
6122 // addressing mode). Just do two i64 store of zero-registers.
6124 const Function *F = MF.getFunction();
6125 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6126 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6127 Attribute::NoImplicitFloat) &&
6128 (memOpAlign(SrcAlign, DstAlign, 16) ||
6129 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6132 return Size >= 8 ? MVT::i64 : MVT::i32;
6135 // 12-bit optionally shifted immediates are legal for adds.
6136 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6137 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6142 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6143 // immediates is the same as for an add or a sub.
6144 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6147 return isLegalAddImmediate(Immed);
6150 /// isLegalAddressingMode - Return true if the addressing mode represented
6151 /// by AM is legal for this target, for a load/store of the specified type.
6152 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6154 // AArch64 has five basic addressing modes:
6156 // reg + 9-bit signed offset
6157 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6159 // reg + SIZE_IN_BYTES * reg
6161 // No global is ever allowed as a base.
6165 // No reg+reg+imm addressing.
6166 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6169 // check reg + imm case:
6170 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6171 uint64_t NumBytes = 0;
6172 if (Ty->isSized()) {
6173 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6174 NumBytes = NumBits / 8;
6175 if (!isPowerOf2_64(NumBits))
6180 int64_t Offset = AM.BaseOffs;
6182 // 9-bit signed offset
6183 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6186 // 12-bit unsigned offset
6187 unsigned shift = Log2_64(NumBytes);
6188 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6189 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6190 (Offset >> shift) << shift == Offset)
6195 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6197 if (!AM.Scale || AM.Scale == 1 ||
6198 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6203 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6205 // Scaling factors are not free at all.
6206 // Operands | Rt Latency
6207 // -------------------------------------------
6209 // -------------------------------------------
6210 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6211 // Rt, [Xn, Wm, <extend> #imm] |
6212 if (isLegalAddressingMode(AM, Ty))
6213 // Scale represents reg2 * scale, thus account for 1 if
6214 // it is not equal to 0 or 1.
6215 return AM.Scale != 0 && AM.Scale != 1;
6219 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6220 VT = VT.getScalarType();
6225 switch (VT.getSimpleVT().SimpleTy) {
6237 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6238 // LR is a callee-save register, but we must treat it as clobbered by any call
6239 // site. Hence we include LR in the scratch registers, which are in turn added
6240 // as implicit-defs for stackmaps and patchpoints.
6241 static const MCPhysReg ScratchRegs[] = {
6242 AArch64::X16, AArch64::X17, AArch64::LR, 0
6248 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6249 EVT VT = N->getValueType(0);
6250 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6251 // it with shift to let it be lowered to UBFX.
6252 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6253 isa<ConstantSDNode>(N->getOperand(1))) {
6254 uint64_t TruncMask = N->getConstantOperandVal(1);
6255 if (isMask_64(TruncMask) &&
6256 N->getOperand(0).getOpcode() == ISD::SRL &&
6257 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6263 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6265 assert(Ty->isIntegerTy());
6267 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6271 int64_t Val = Imm.getSExtValue();
6272 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6275 if ((int64_t)Val < 0)
6278 Val &= (1LL << 32) - 1;
6280 unsigned LZ = countLeadingZeros((uint64_t)Val);
6281 unsigned Shift = (63 - LZ) / 16;
6282 // MOVZ is free so return true for one or fewer MOVK.
6283 return (Shift < 3) ? true : false;
6286 // Generate SUBS and CSEL for integer abs.
6287 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6288 EVT VT = N->getValueType(0);
6290 SDValue N0 = N->getOperand(0);
6291 SDValue N1 = N->getOperand(1);
6294 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6295 // and change it to SUB and CSEL.
6296 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6297 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6298 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6299 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6300 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6301 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6303 // Generate SUBS & CSEL.
6305 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6306 N0.getOperand(0), DAG.getConstant(0, VT));
6307 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6308 DAG.getConstant(AArch64CC::PL, MVT::i32),
6309 SDValue(Cmp.getNode(), 1));
6314 // performXorCombine - Attempts to handle integer ABS.
6315 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6316 TargetLowering::DAGCombinerInfo &DCI,
6317 const AArch64Subtarget *Subtarget) {
6318 if (DCI.isBeforeLegalizeOps())
6321 return performIntegerAbsCombine(N, DAG);
6324 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6325 TargetLowering::DAGCombinerInfo &DCI,
6326 const AArch64Subtarget *Subtarget) {
6327 if (DCI.isBeforeLegalizeOps())
6330 // Multiplication of a power of two plus/minus one can be done more
6331 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6332 // future CPUs have a cheaper MADD instruction, this may need to be
6333 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6334 // 64-bit is 5 cycles, so this is always a win.
6335 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6336 APInt Value = C->getAPIntValue();
6337 EVT VT = N->getValueType(0);
6338 APInt VM1 = Value - 1;
6339 if (VM1.isPowerOf2()) {
6340 // Multiplying by one more than a power of two, replace with a shift
6342 SDValue ShiftedVal =
6343 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6344 DAG.getConstant(VM1.logBase2(), MVT::i64));
6345 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6347 APInt VP1 = Value + 1;
6348 if (VP1.isPowerOf2()) {
6349 // Multiplying by one less than a power of two, replace with a shift
6351 SDValue ShiftedVal =
6352 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6353 DAG.getConstant(VP1.logBase2(), MVT::i64));
6354 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6360 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6361 EVT VT = N->getValueType(0);
6362 if (VT != MVT::f32 && VT != MVT::f64)
6364 // Only optimize when the source and destination types have the same width.
6365 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6368 // If the result of an integer load is only used by an integer-to-float
6369 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6370 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6371 SDValue N0 = N->getOperand(0);
6372 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6373 // Do not change the width of a volatile load.
6374 !cast<LoadSDNode>(N0)->isVolatile()) {
6375 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6376 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6377 LN0->getPointerInfo(), LN0->isVolatile(),
6378 LN0->isNonTemporal(), LN0->isInvariant(),
6379 LN0->getAlignment());
6381 // Make sure successors of the original load stay after it by updating them
6382 // to use the new Chain.
6383 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6386 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6387 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6393 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6394 /// searches for and classifies those shifts.
6395 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6397 if (N.getOpcode() == ISD::SHL)
6399 else if (N.getOpcode() == ISD::SRL)
6404 if (!isa<ConstantSDNode>(N.getOperand(1)))
6407 ShiftAmount = N->getConstantOperandVal(1);
6408 Src = N->getOperand(0);
6412 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6413 /// registers viewed as a high/low pair. This function looks for the pattern:
6414 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6415 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6417 static SDValue tryCombineToEXTR(SDNode *N,
6418 TargetLowering::DAGCombinerInfo &DCI) {
6419 SelectionDAG &DAG = DCI.DAG;
6421 EVT VT = N->getValueType(0);
6423 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6425 if (VT != MVT::i32 && VT != MVT::i64)
6429 uint32_t ShiftLHS = 0;
6431 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6435 uint32_t ShiftRHS = 0;
6437 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6440 // If they're both trying to come from the high part of the register, they're
6441 // not really an EXTR.
6442 if (LHSFromHi == RHSFromHi)
6445 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6449 std::swap(LHS, RHS);
6450 std::swap(ShiftLHS, ShiftRHS);
6453 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6454 DAG.getConstant(ShiftRHS, MVT::i64));
6457 static SDValue tryCombineToBSL(SDNode *N,
6458 TargetLowering::DAGCombinerInfo &DCI) {
6459 EVT VT = N->getValueType(0);
6460 SelectionDAG &DAG = DCI.DAG;
6466 SDValue N0 = N->getOperand(0);
6467 if (N0.getOpcode() != ISD::AND)
6470 SDValue N1 = N->getOperand(1);
6471 if (N1.getOpcode() != ISD::AND)
6474 // We only have to look for constant vectors here since the general, variable
6475 // case can be handled in TableGen.
6476 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6477 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6478 for (int i = 1; i >= 0; --i)
6479 for (int j = 1; j >= 0; --j) {
6480 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6481 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6485 bool FoundMatch = true;
6486 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6487 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6488 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6490 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6497 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6498 N0->getOperand(1 - i), N1->getOperand(1 - j));
6504 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6505 const AArch64Subtarget *Subtarget) {
6506 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6507 if (!EnableAArch64ExtrGeneration)
6509 SelectionDAG &DAG = DCI.DAG;
6510 EVT VT = N->getValueType(0);
6512 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6515 SDValue Res = tryCombineToEXTR(N, DCI);
6519 Res = tryCombineToBSL(N, DCI);
6526 static SDValue performBitcastCombine(SDNode *N,
6527 TargetLowering::DAGCombinerInfo &DCI,
6528 SelectionDAG &DAG) {
6529 // Wait 'til after everything is legalized to try this. That way we have
6530 // legal vector types and such.
6531 if (DCI.isBeforeLegalizeOps())
6534 // Remove extraneous bitcasts around an extract_subvector.
6536 // (v4i16 (bitconvert
6537 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6539 // (extract_subvector ((v8i16 ...), (i64 4)))
6541 // Only interested in 64-bit vectors as the ultimate result.
6542 EVT VT = N->getValueType(0);
6545 if (VT.getSimpleVT().getSizeInBits() != 64)
6547 // Is the operand an extract_subvector starting at the beginning or halfway
6548 // point of the vector? A low half may also come through as an
6549 // EXTRACT_SUBREG, so look for that, too.
6550 SDValue Op0 = N->getOperand(0);
6551 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6552 !(Op0->isMachineOpcode() &&
6553 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6555 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6556 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6557 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6559 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6560 if (idx != AArch64::dsub)
6562 // The dsub reference is equivalent to a lane zero subvector reference.
6565 // Look through the bitcast of the input to the extract.
6566 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6568 SDValue Source = Op0->getOperand(0)->getOperand(0);
6569 // If the source type has twice the number of elements as our destination
6570 // type, we know this is an extract of the high or low half of the vector.
6571 EVT SVT = Source->getValueType(0);
6572 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6575 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6577 // Create the simplified form to just extract the low or high half of the
6578 // vector directly rather than bothering with the bitcasts.
6580 unsigned NumElements = VT.getVectorNumElements();
6582 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6583 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6585 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6586 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6592 static SDValue performConcatVectorsCombine(SDNode *N,
6593 TargetLowering::DAGCombinerInfo &DCI,
6594 SelectionDAG &DAG) {
6595 // Wait 'til after everything is legalized to try this. That way we have
6596 // legal vector types and such.
6597 if (DCI.isBeforeLegalizeOps())
6601 EVT VT = N->getValueType(0);
6603 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6604 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6605 // canonicalise to that.
6606 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6607 assert(VT.getVectorElementType().getSizeInBits() == 64);
6608 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6609 WidenVector(N->getOperand(0), DAG),
6610 DAG.getConstant(0, MVT::i64));
6613 // Canonicalise concat_vectors so that the right-hand vector has as few
6614 // bit-casts as possible before its real operation. The primary matching
6615 // destination for these operations will be the narrowing "2" instructions,
6616 // which depend on the operation being performed on this right-hand vector.
6618 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
6620 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
6622 SDValue Op1 = N->getOperand(1);
6623 if (Op1->getOpcode() != ISD::BITCAST)
6625 SDValue RHS = Op1->getOperand(0);
6626 MVT RHSTy = RHS.getValueType().getSimpleVT();
6627 // If the RHS is not a vector, this is not the pattern we're looking for.
6628 if (!RHSTy.isVector())
6631 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
6633 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
6634 RHSTy.getVectorNumElements() * 2);
6636 ISD::BITCAST, dl, VT,
6637 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
6638 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
6641 static SDValue tryCombineFixedPointConvert(SDNode *N,
6642 TargetLowering::DAGCombinerInfo &DCI,
6643 SelectionDAG &DAG) {
6644 // Wait 'til after everything is legalized to try this. That way we have
6645 // legal vector types and such.
6646 if (DCI.isBeforeLegalizeOps())
6648 // Transform a scalar conversion of a value from a lane extract into a
6649 // lane extract of a vector conversion. E.g., from foo1 to foo2:
6650 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
6651 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
6653 // The second form interacts better with instruction selection and the
6654 // register allocator to avoid cross-class register copies that aren't
6655 // coalescable due to a lane reference.
6657 // Check the operand and see if it originates from a lane extract.
6658 SDValue Op1 = N->getOperand(1);
6659 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6660 // Yep, no additional predication needed. Perform the transform.
6661 SDValue IID = N->getOperand(0);
6662 SDValue Shift = N->getOperand(2);
6663 SDValue Vec = Op1.getOperand(0);
6664 SDValue Lane = Op1.getOperand(1);
6665 EVT ResTy = N->getValueType(0);
6669 // The vector width should be 128 bits by the time we get here, even
6670 // if it started as 64 bits (the extract_vector handling will have
6672 assert(Vec.getValueType().getSizeInBits() == 128 &&
6673 "unexpected vector size on extract_vector_elt!");
6674 if (Vec.getValueType() == MVT::v4i32)
6675 VecResTy = MVT::v4f32;
6676 else if (Vec.getValueType() == MVT::v2i64)
6677 VecResTy = MVT::v2f64;
6679 assert(0 && "unexpected vector type!");
6682 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
6683 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
6688 // AArch64 high-vector "long" operations are formed by performing the non-high
6689 // version on an extract_subvector of each operand which gets the high half:
6691 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
6693 // However, there are cases which don't have an extract_high explicitly, but
6694 // have another operation that can be made compatible with one for free. For
6697 // (dupv64 scalar) --> (extract_high (dup128 scalar))
6699 // This routine does the actual conversion of such DUPs, once outer routines
6700 // have determined that everything else is in order.
6701 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
6702 // We can handle most types of duplicate, but the lane ones have an extra
6703 // operand saying *which* lane, so we need to know.
6705 switch (N.getOpcode()) {
6706 case AArch64ISD::DUP:
6709 case AArch64ISD::DUPLANE8:
6710 case AArch64ISD::DUPLANE16:
6711 case AArch64ISD::DUPLANE32:
6712 case AArch64ISD::DUPLANE64:
6719 MVT NarrowTy = N.getSimpleValueType();
6720 if (!NarrowTy.is64BitVector())
6723 MVT ElementTy = NarrowTy.getVectorElementType();
6724 unsigned NumElems = NarrowTy.getVectorNumElements();
6725 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
6729 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
6732 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
6734 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
6735 NewDUP, DAG.getConstant(NumElems, MVT::i64));
6738 static bool isEssentiallyExtractSubvector(SDValue N) {
6739 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
6742 return N.getOpcode() == ISD::BITCAST &&
6743 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
6746 /// \brief Helper structure to keep track of ISD::SET_CC operands.
6747 struct GenericSetCCInfo {
6748 const SDValue *Opnd0;
6749 const SDValue *Opnd1;
6753 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
6754 struct AArch64SetCCInfo {
6756 AArch64CC::CondCode CC;
6759 /// \brief Helper structure to keep track of SetCC information.
6761 GenericSetCCInfo Generic;
6762 AArch64SetCCInfo AArch64;
6765 /// \brief Helper structure to be able to read SetCC information. If set to
6766 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
6767 /// GenericSetCCInfo.
6768 struct SetCCInfoAndKind {
6773 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
6775 /// AArch64 lowered one.
6776 /// \p SetCCInfo is filled accordingly.
6777 /// \post SetCCInfo is meanginfull only when this function returns true.
6778 /// \return True when Op is a kind of SET_CC operation.
6779 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
6780 // If this is a setcc, this is straight forward.
6781 if (Op.getOpcode() == ISD::SETCC) {
6782 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
6783 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
6784 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6785 SetCCInfo.IsAArch64 = false;
6788 // Otherwise, check if this is a matching csel instruction.
6792 if (Op.getOpcode() != AArch64ISD::CSEL)
6794 // Set the information about the operands.
6795 // TODO: we want the operands of the Cmp not the csel
6796 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
6797 SetCCInfo.IsAArch64 = true;
6798 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
6799 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
6801 // Check that the operands matches the constraints:
6802 // (1) Both operands must be constants.
6803 // (2) One must be 1 and the other must be 0.
6804 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
6805 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6808 if (!TValue || !FValue)
6812 if (!TValue->isOne()) {
6813 // Update the comparison when we are interested in !cc.
6814 std::swap(TValue, FValue);
6815 SetCCInfo.Info.AArch64.CC =
6816 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
6818 return TValue->isOne() && FValue->isNullValue();
6821 // Returns true if Op is setcc or zext of setcc.
6822 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
6823 if (isSetCC(Op, Info))
6825 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
6826 isSetCC(Op->getOperand(0), Info));
6829 // The folding we want to perform is:
6830 // (add x, [zext] (setcc cc ...) )
6832 // (csel x, (add x, 1), !cc ...)
6834 // The latter will get matched to a CSINC instruction.
6835 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
6836 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
6837 SDValue LHS = Op->getOperand(0);
6838 SDValue RHS = Op->getOperand(1);
6839 SetCCInfoAndKind InfoAndKind;
6841 // If neither operand is a SET_CC, give up.
6842 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
6843 std::swap(LHS, RHS);
6844 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
6848 // FIXME: This could be generatized to work for FP comparisons.
6849 EVT CmpVT = InfoAndKind.IsAArch64
6850 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
6851 : InfoAndKind.Info.Generic.Opnd0->getValueType();
6852 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
6858 if (InfoAndKind.IsAArch64) {
6859 CCVal = DAG.getConstant(
6860 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
6861 Cmp = *InfoAndKind.Info.AArch64.Cmp;
6863 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
6864 *InfoAndKind.Info.Generic.Opnd1,
6865 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
6868 EVT VT = Op->getValueType(0);
6869 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
6870 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
6873 // The basic add/sub long vector instructions have variants with "2" on the end
6874 // which act on the high-half of their inputs. They are normally matched by
6877 // (add (zeroext (extract_high LHS)),
6878 // (zeroext (extract_high RHS)))
6879 // -> uaddl2 vD, vN, vM
6881 // However, if one of the extracts is something like a duplicate, this
6882 // instruction can still be used profitably. This function puts the DAG into a
6883 // more appropriate form for those patterns to trigger.
6884 static SDValue performAddSubLongCombine(SDNode *N,
6885 TargetLowering::DAGCombinerInfo &DCI,
6886 SelectionDAG &DAG) {
6887 if (DCI.isBeforeLegalizeOps())
6890 MVT VT = N->getSimpleValueType(0);
6891 if (!VT.is128BitVector()) {
6892 if (N->getOpcode() == ISD::ADD)
6893 return performSetccAddFolding(N, DAG);
6897 // Make sure both branches are extended in the same way.
6898 SDValue LHS = N->getOperand(0);
6899 SDValue RHS = N->getOperand(1);
6900 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
6901 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
6902 LHS.getOpcode() != RHS.getOpcode())
6905 unsigned ExtType = LHS.getOpcode();
6907 // It's not worth doing if at least one of the inputs isn't already an
6908 // extract, but we don't know which it'll be so we have to try both.
6909 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
6910 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
6914 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
6915 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
6916 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
6920 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
6923 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
6926 // Massage DAGs which we can use the high-half "long" operations on into
6927 // something isel will recognize better. E.g.
6929 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
6930 // (aarch64_neon_umull (extract_high (v2i64 vec)))
6931 // (extract_high (v2i64 (dup128 scalar)))))
6933 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
6934 TargetLowering::DAGCombinerInfo &DCI,
6935 SelectionDAG &DAG) {
6936 if (DCI.isBeforeLegalizeOps())
6939 SDValue LHS = N->getOperand(1);
6940 SDValue RHS = N->getOperand(2);
6941 assert(LHS.getValueType().is64BitVector() &&
6942 RHS.getValueType().is64BitVector() &&
6943 "unexpected shape for long operation");
6945 // Either node could be a DUP, but it's not worth doing both of them (you'd
6946 // just as well use the non-high version) so look for a corresponding extract
6947 // operation on the other "wing".
6948 if (isEssentiallyExtractSubvector(LHS)) {
6949 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
6952 } else if (isEssentiallyExtractSubvector(RHS)) {
6953 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
6958 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
6959 N->getOperand(0), LHS, RHS);
6962 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
6963 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
6964 unsigned ElemBits = ElemTy.getSizeInBits();
6966 int64_t ShiftAmount;
6967 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
6968 APInt SplatValue, SplatUndef;
6969 unsigned SplatBitSize;
6971 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
6972 HasAnyUndefs, ElemBits) ||
6973 SplatBitSize != ElemBits)
6976 ShiftAmount = SplatValue.getSExtValue();
6977 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
6978 ShiftAmount = CVN->getSExtValue();
6986 llvm_unreachable("Unknown shift intrinsic");
6987 case Intrinsic::aarch64_neon_sqshl:
6988 Opcode = AArch64ISD::SQSHL_I;
6989 IsRightShift = false;
6991 case Intrinsic::aarch64_neon_uqshl:
6992 Opcode = AArch64ISD::UQSHL_I;
6993 IsRightShift = false;
6995 case Intrinsic::aarch64_neon_srshl:
6996 Opcode = AArch64ISD::SRSHR_I;
6997 IsRightShift = true;
6999 case Intrinsic::aarch64_neon_urshl:
7000 Opcode = AArch64ISD::URSHR_I;
7001 IsRightShift = true;
7003 case Intrinsic::aarch64_neon_sqshlu:
7004 Opcode = AArch64ISD::SQSHLU_I;
7005 IsRightShift = false;
7009 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7010 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7011 DAG.getConstant(-ShiftAmount, MVT::i32));
7012 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount <= ElemBits)
7013 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7014 DAG.getConstant(ShiftAmount, MVT::i32));
7019 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7020 // the intrinsics must be legal and take an i32, this means there's almost
7021 // certainly going to be a zext in the DAG which we can eliminate.
7022 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7023 SDValue AndN = N->getOperand(2);
7024 if (AndN.getOpcode() != ISD::AND)
7027 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7028 if (!CMask || CMask->getZExtValue() != Mask)
7031 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7032 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7035 static SDValue performIntrinsicCombine(SDNode *N,
7036 TargetLowering::DAGCombinerInfo &DCI,
7037 const AArch64Subtarget *Subtarget) {
7038 SelectionDAG &DAG = DCI.DAG;
7039 unsigned IID = getIntrinsicID(N);
7043 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7044 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7045 return tryCombineFixedPointConvert(N, DCI, DAG);
7047 case Intrinsic::aarch64_neon_fmax:
7048 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7049 N->getOperand(1), N->getOperand(2));
7050 case Intrinsic::aarch64_neon_fmin:
7051 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7052 N->getOperand(1), N->getOperand(2));
7053 case Intrinsic::aarch64_neon_smull:
7054 case Intrinsic::aarch64_neon_umull:
7055 case Intrinsic::aarch64_neon_pmull:
7056 case Intrinsic::aarch64_neon_sqdmull:
7057 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7058 case Intrinsic::aarch64_neon_sqshl:
7059 case Intrinsic::aarch64_neon_uqshl:
7060 case Intrinsic::aarch64_neon_sqshlu:
7061 case Intrinsic::aarch64_neon_srshl:
7062 case Intrinsic::aarch64_neon_urshl:
7063 return tryCombineShiftImm(IID, N, DAG);
7064 case Intrinsic::aarch64_crc32b:
7065 case Intrinsic::aarch64_crc32cb:
7066 return tryCombineCRC32(0xff, N, DAG);
7067 case Intrinsic::aarch64_crc32h:
7068 case Intrinsic::aarch64_crc32ch:
7069 return tryCombineCRC32(0xffff, N, DAG);
7074 static SDValue performExtendCombine(SDNode *N,
7075 TargetLowering::DAGCombinerInfo &DCI,
7076 SelectionDAG &DAG) {
7077 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7078 // we can convert that DUP into another extract_high (of a bigger DUP), which
7079 // helps the backend to decide that an sabdl2 would be useful, saving a real
7080 // extract_high operation.
7081 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7082 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7083 SDNode *ABDNode = N->getOperand(0).getNode();
7084 unsigned IID = getIntrinsicID(ABDNode);
7085 if (IID == Intrinsic::aarch64_neon_sabd ||
7086 IID == Intrinsic::aarch64_neon_uabd) {
7087 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7088 if (!NewABD.getNode())
7091 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7096 // This is effectively a custom type legalization for AArch64.
7098 // Type legalization will split an extend of a small, legal, type to a larger
7099 // illegal type by first splitting the destination type, often creating
7100 // illegal source types, which then get legalized in isel-confusing ways,
7101 // leading to really terrible codegen. E.g.,
7102 // %result = v8i32 sext v8i8 %value
7104 // %losrc = extract_subreg %value, ...
7105 // %hisrc = extract_subreg %value, ...
7106 // %lo = v4i32 sext v4i8 %losrc
7107 // %hi = v4i32 sext v4i8 %hisrc
7108 // Things go rapidly downhill from there.
7110 // For AArch64, the [sz]ext vector instructions can only go up one element
7111 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7112 // take two instructions.
7114 // This implies that the most efficient way to do the extend from v8i8
7115 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7116 // the normal splitting to happen for the v8i16->v8i32.
7118 // This is pre-legalization to catch some cases where the default
7119 // type legalization will create ill-tempered code.
7120 if (!DCI.isBeforeLegalizeOps())
7123 // We're only interested in cleaning things up for non-legal vector types
7124 // here. If both the source and destination are legal, things will just
7125 // work naturally without any fiddling.
7126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7127 EVT ResVT = N->getValueType(0);
7128 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7130 // If the vector type isn't a simple VT, it's beyond the scope of what
7131 // we're worried about here. Let legalization do its thing and hope for
7133 if (!ResVT.isSimple())
7136 SDValue Src = N->getOperand(0);
7137 MVT SrcVT = Src->getValueType(0).getSimpleVT();
7138 // If the source VT is a 64-bit vector, we can play games and get the
7139 // better results we want.
7140 if (SrcVT.getSizeInBits() != 64)
7143 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7144 unsigned ElementCount = SrcVT.getVectorNumElements();
7145 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7147 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7149 // Now split the rest of the operation into two halves, each with a 64
7153 unsigned NumElements = ResVT.getVectorNumElements();
7154 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7155 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7156 ResVT.getVectorElementType(), NumElements / 2);
7158 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7159 LoVT.getVectorNumElements());
7160 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7161 DAG.getIntPtrConstant(0));
7162 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7163 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7164 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7165 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7167 // Now combine the parts back together so we still have a single result
7168 // like the combiner expects.
7169 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7172 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7173 /// value. The load store optimizer pass will merge them to store pair stores.
7174 /// This has better performance than a splat of the scalar followed by a split
7175 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7176 /// followed by an ext.b and two stores.
7177 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7178 SDValue StVal = St->getValue();
7179 EVT VT = StVal.getValueType();
7181 // Don't replace floating point stores, they possibly won't be transformed to
7182 // stp because of the store pair suppress pass.
7183 if (VT.isFloatingPoint())
7186 // Check for insert vector elements.
7187 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7190 // We can express a splat as store pair(s) for 2 or 4 elements.
7191 unsigned NumVecElts = VT.getVectorNumElements();
7192 if (NumVecElts != 4 && NumVecElts != 2)
7194 SDValue SplatVal = StVal.getOperand(1);
7195 unsigned RemainInsertElts = NumVecElts - 1;
7197 // Check that this is a splat.
7198 while (--RemainInsertElts) {
7199 SDValue NextInsertElt = StVal.getOperand(0);
7200 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7202 if (NextInsertElt.getOperand(1) != SplatVal)
7204 StVal = NextInsertElt;
7206 unsigned OrigAlignment = St->getAlignment();
7207 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7208 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7210 // Create scalar stores. This is at least as good as the code sequence for a
7211 // split unaligned store wich is a dup.s, ext.b, and two stores.
7212 // Most of the time the three stores should be replaced by store pair
7213 // instructions (stp).
7215 SDValue BasePtr = St->getBasePtr();
7217 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7218 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7220 unsigned Offset = EltOffset;
7221 while (--NumVecElts) {
7222 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7223 DAG.getConstant(Offset, MVT::i64));
7224 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7225 St->getPointerInfo(), St->isVolatile(),
7226 St->isNonTemporal(), Alignment);
7227 Offset += EltOffset;
7232 static SDValue performSTORECombine(SDNode *N,
7233 TargetLowering::DAGCombinerInfo &DCI,
7235 const AArch64Subtarget *Subtarget) {
7236 if (!DCI.isBeforeLegalize())
7239 StoreSDNode *S = cast<StoreSDNode>(N);
7240 if (S->isVolatile())
7243 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7244 // page boundries. We want to split such stores.
7245 if (!Subtarget->isCyclone())
7248 // Don't split at Oz.
7249 MachineFunction &MF = DAG.getMachineFunction();
7250 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7251 AttributeSet::FunctionIndex, Attribute::MinSize);
7255 SDValue StVal = S->getValue();
7256 EVT VT = StVal.getValueType();
7258 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7259 // those up regresses performance on micro-benchmarks and olden/bh.
7260 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7263 // Split unaligned 16B stores. They are terrible for performance.
7264 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7265 // extensions can use this to mark that it does not want splitting to happen
7266 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7267 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7268 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7269 S->getAlignment() <= 2)
7272 // If we get a splat of a scalar convert this vector store to a store of
7273 // scalars. They will be merged into store pairs thereby removing two
7275 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7276 if (ReplacedSplat != SDValue())
7277 return ReplacedSplat;
7280 unsigned NumElts = VT.getVectorNumElements() / 2;
7281 // Split VT into two.
7283 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7284 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7285 DAG.getIntPtrConstant(0));
7286 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7287 DAG.getIntPtrConstant(NumElts));
7288 SDValue BasePtr = S->getBasePtr();
7290 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7291 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7292 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7293 DAG.getConstant(8, MVT::i64));
7294 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7295 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7299 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7300 /// post-increment LD1R.
7301 static SDValue performPostLD1Combine(SDNode *N,
7302 TargetLowering::DAGCombinerInfo &DCI,
7304 if (DCI.isBeforeLegalizeOps())
7307 SelectionDAG &DAG = DCI.DAG;
7308 EVT VT = N->getValueType(0);
7310 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7311 SDNode *LD = N->getOperand(LoadIdx).getNode();
7312 // If it is not LOAD, can not do such combine.
7313 if (LD->getOpcode() != ISD::LOAD)
7316 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7317 EVT MemVT = LoadSDN->getMemoryVT();
7318 // Check if memory operand is the same type as the vector element.
7319 if (MemVT != VT.getVectorElementType())
7322 // Check if there are other uses. If so, do not combine as it will introduce
7324 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7326 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7332 SDValue Addr = LD->getOperand(1);
7333 SDValue Vector = N->getOperand(0);
7334 // Search for a use of the address operand that is an increment.
7335 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7336 Addr.getNode()->use_end(); UI != UE; ++UI) {
7338 if (User->getOpcode() != ISD::ADD
7339 || UI.getUse().getResNo() != Addr.getResNo())
7342 // Check that the add is independent of the load. Otherwise, folding it
7343 // would create a cycle.
7344 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7346 // Also check that add is not used in the vector operand. This would also
7348 if (User->isPredecessorOf(Vector.getNode()))
7351 // If the increment is a constant, it must match the memory ref size.
7352 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7353 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7354 uint32_t IncVal = CInc->getZExtValue();
7355 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7356 if (IncVal != NumBytes)
7358 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7361 SmallVector<SDValue, 8> Ops;
7362 Ops.push_back(LD->getOperand(0)); // Chain
7364 Ops.push_back(Vector); // The vector to be inserted
7365 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7367 Ops.push_back(Addr);
7370 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7371 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, 3));
7372 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7373 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7375 LoadSDN->getMemOperand());
7378 std::vector<SDValue> NewResults;
7379 NewResults.push_back(SDValue(LD, 0)); // The result of load
7380 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7381 DCI.CombineTo(LD, NewResults);
7382 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7383 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7390 /// Target-specific DAG combine function for NEON load/store intrinsics
7391 /// to merge base address updates.
7392 static SDValue performNEONPostLDSTCombine(SDNode *N,
7393 TargetLowering::DAGCombinerInfo &DCI,
7394 SelectionDAG &DAG) {
7395 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7398 unsigned AddrOpIdx = N->getNumOperands() - 1;
7399 SDValue Addr = N->getOperand(AddrOpIdx);
7401 // Search for a use of the address operand that is an increment.
7402 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7403 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7405 if (User->getOpcode() != ISD::ADD ||
7406 UI.getUse().getResNo() != Addr.getResNo())
7409 // Check that the add is independent of the load/store. Otherwise, folding
7410 // it would create a cycle.
7411 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7414 // Find the new opcode for the updating load/store.
7415 bool IsStore = false;
7416 bool IsLaneOp = false;
7417 bool IsDupOp = false;
7418 unsigned NewOpc = 0;
7419 unsigned NumVecs = 0;
7420 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7422 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7423 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7425 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7427 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7429 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7430 NumVecs = 2; IsStore = true; break;
7431 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7432 NumVecs = 3; IsStore = true; break;
7433 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7434 NumVecs = 4; IsStore = true; break;
7435 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7437 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7439 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7441 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7442 NumVecs = 2; IsStore = true; break;
7443 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7444 NumVecs = 3; IsStore = true; break;
7445 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7446 NumVecs = 4; IsStore = true; break;
7447 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7448 NumVecs = 2; IsDupOp = true; break;
7449 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7450 NumVecs = 3; IsDupOp = true; break;
7451 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7452 NumVecs = 4; IsDupOp = true; break;
7453 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7454 NumVecs = 2; IsLaneOp = true; break;
7455 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7456 NumVecs = 3; IsLaneOp = true; break;
7457 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7458 NumVecs = 4; IsLaneOp = true; break;
7459 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7460 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7461 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7462 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7463 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7464 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7469 VecTy = N->getOperand(2).getValueType();
7471 VecTy = N->getValueType(0);
7473 // If the increment is a constant, it must match the memory ref size.
7474 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7475 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7476 uint32_t IncVal = CInc->getZExtValue();
7477 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7478 if (IsLaneOp || IsDupOp)
7479 NumBytes /= VecTy.getVectorNumElements();
7480 if (IncVal != NumBytes)
7482 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7484 SmallVector<SDValue, 8> Ops;
7485 Ops.push_back(N->getOperand(0)); // Incoming chain
7486 // Load lane and store have vector list as input.
7487 if (IsLaneOp || IsStore)
7488 for (unsigned i = 2; i < AddrOpIdx; ++i)
7489 Ops.push_back(N->getOperand(i));
7490 Ops.push_back(Addr); // Base register
7495 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7497 for (n = 0; n < NumResultVecs; ++n)
7499 Tys[n++] = MVT::i64; // Type of write back register
7500 Tys[n] = MVT::Other; // Type of the chain
7501 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs + 2));
7503 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7504 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7505 MemInt->getMemoryVT(),
7506 MemInt->getMemOperand());
7509 std::vector<SDValue> NewResults;
7510 for (unsigned i = 0; i < NumResultVecs; ++i) {
7511 NewResults.push_back(SDValue(UpdN.getNode(), i));
7513 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7514 DCI.CombineTo(N, NewResults);
7515 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7522 // Optimize compare with zero and branch.
7523 static SDValue performBRCONDCombine(SDNode *N,
7524 TargetLowering::DAGCombinerInfo &DCI,
7525 SelectionDAG &DAG) {
7526 SDValue Chain = N->getOperand(0);
7527 SDValue Dest = N->getOperand(1);
7528 SDValue CCVal = N->getOperand(2);
7529 SDValue Cmp = N->getOperand(3);
7531 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7532 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7533 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7536 unsigned CmpOpc = Cmp.getOpcode();
7537 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
7540 // Only attempt folding if there is only one use of the flag and no use of the
7542 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7545 SDValue LHS = Cmp.getOperand(0);
7546 SDValue RHS = Cmp.getOperand(1);
7548 assert(LHS.getValueType() == RHS.getValueType() &&
7549 "Expected the value type to be the same for both operands!");
7550 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7553 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7554 std::swap(LHS, RHS);
7556 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7559 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7560 LHS.getOpcode() == ISD::SRL)
7563 // Fold the compare into the branch instruction.
7565 if (CC == AArch64CC::EQ)
7566 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7568 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7570 // Do not add new nodes to DAG combiner worklist.
7571 DCI.CombineTo(N, BR, false);
7576 // vselect (v1i1 setcc) ->
7577 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7578 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7579 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7581 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7582 SDValue N0 = N->getOperand(0);
7583 EVT CCVT = N0.getValueType();
7585 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7586 CCVT.getVectorElementType() != MVT::i1)
7589 EVT ResVT = N->getValueType(0);
7590 EVT CmpVT = N0.getOperand(0).getValueType();
7591 // Only combine when the result type is of the same size as the compared
7593 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7596 SDValue IfTrue = N->getOperand(1);
7597 SDValue IfFalse = N->getOperand(2);
7599 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7600 N0.getOperand(0), N0.getOperand(1),
7601 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7602 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7606 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7607 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7608 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7609 /// with a vector one followed by a DUP shuffle on the result.
7610 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7611 SDValue N0 = N->getOperand(0);
7612 EVT ResVT = N->getValueType(0);
7614 if (!N->getOperand(1).getValueType().isVector())
7617 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7622 EVT SrcVT = N0.getOperand(0).getValueType();
7623 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
7624 ResVT.getSizeInBits() / SrcVT.getSizeInBits());
7625 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
7627 // First perform a vector comparison, where lane 0 is the one we're interested
7630 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
7632 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
7633 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7635 // Now duplicate the comparison mask we want across all other lanes.
7636 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
7637 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
7638 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),
7641 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
7644 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
7645 DAGCombinerInfo &DCI) const {
7646 SelectionDAG &DAG = DCI.DAG;
7647 switch (N->getOpcode()) {
7652 return performAddSubLongCombine(N, DCI, DAG);
7654 return performXorCombine(N, DAG, DCI, Subtarget);
7656 return performMulCombine(N, DAG, DCI, Subtarget);
7657 case ISD::SINT_TO_FP:
7658 case ISD::UINT_TO_FP:
7659 return performIntToFpCombine(N, DAG);
7661 return performORCombine(N, DCI, Subtarget);
7662 case ISD::INTRINSIC_WO_CHAIN:
7663 return performIntrinsicCombine(N, DCI, Subtarget);
7664 case ISD::ANY_EXTEND:
7665 case ISD::ZERO_EXTEND:
7666 case ISD::SIGN_EXTEND:
7667 return performExtendCombine(N, DCI, DAG);
7669 return performBitcastCombine(N, DCI, DAG);
7670 case ISD::CONCAT_VECTORS:
7671 return performConcatVectorsCombine(N, DCI, DAG);
7673 return performSelectCombine(N, DAG);
7675 return performVSelectCombine(N, DCI.DAG);
7677 return performSTORECombine(N, DCI, DAG, Subtarget);
7678 case AArch64ISD::BRCOND:
7679 return performBRCONDCombine(N, DCI, DAG);
7680 case AArch64ISD::DUP:
7681 return performPostLD1Combine(N, DCI, false);
7682 case ISD::INSERT_VECTOR_ELT:
7683 return performPostLD1Combine(N, DCI, true);
7684 case ISD::INTRINSIC_VOID:
7685 case ISD::INTRINSIC_W_CHAIN:
7686 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7687 case Intrinsic::aarch64_neon_ld2:
7688 case Intrinsic::aarch64_neon_ld3:
7689 case Intrinsic::aarch64_neon_ld4:
7690 case Intrinsic::aarch64_neon_ld1x2:
7691 case Intrinsic::aarch64_neon_ld1x3:
7692 case Intrinsic::aarch64_neon_ld1x4:
7693 case Intrinsic::aarch64_neon_ld2lane:
7694 case Intrinsic::aarch64_neon_ld3lane:
7695 case Intrinsic::aarch64_neon_ld4lane:
7696 case Intrinsic::aarch64_neon_ld2r:
7697 case Intrinsic::aarch64_neon_ld3r:
7698 case Intrinsic::aarch64_neon_ld4r:
7699 case Intrinsic::aarch64_neon_st2:
7700 case Intrinsic::aarch64_neon_st3:
7701 case Intrinsic::aarch64_neon_st4:
7702 case Intrinsic::aarch64_neon_st1x2:
7703 case Intrinsic::aarch64_neon_st1x3:
7704 case Intrinsic::aarch64_neon_st1x4:
7705 case Intrinsic::aarch64_neon_st2lane:
7706 case Intrinsic::aarch64_neon_st3lane:
7707 case Intrinsic::aarch64_neon_st4lane:
7708 return performNEONPostLDSTCombine(N, DCI, DAG);
7716 // Check if the return value is used as only a return value, as otherwise
7717 // we can't perform a tail-call. In particular, we need to check for
7718 // target ISD nodes that are returns and any other "odd" constructs
7719 // that the generic analysis code won't necessarily catch.
7720 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
7721 SDValue &Chain) const {
7722 if (N->getNumValues() != 1)
7724 if (!N->hasNUsesOfValue(1, 0))
7727 SDValue TCChain = Chain;
7728 SDNode *Copy = *N->use_begin();
7729 if (Copy->getOpcode() == ISD::CopyToReg) {
7730 // If the copy has a glue operand, we conservatively assume it isn't safe to
7731 // perform a tail call.
7732 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
7735 TCChain = Copy->getOperand(0);
7736 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
7739 bool HasRet = false;
7740 for (SDNode *Node : Copy->uses()) {
7741 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
7753 // Return whether the an instruction can potentially be optimized to a tail
7754 // call. This will cause the optimizers to attempt to move, or duplicate,
7755 // return instructions to help enable tail call optimizations for this
7757 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
7758 if (!CI->isTailCall())
7764 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
7766 ISD::MemIndexedMode &AM,
7768 SelectionDAG &DAG) const {
7769 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
7772 Base = Op->getOperand(0);
7773 // All of the indexed addressing mode instructions take a signed
7774 // 9 bit immediate offset.
7775 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
7776 int64_t RHSC = (int64_t)RHS->getZExtValue();
7777 if (RHSC >= 256 || RHSC <= -256)
7779 IsInc = (Op->getOpcode() == ISD::ADD);
7780 Offset = Op->getOperand(1);
7786 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7788 ISD::MemIndexedMode &AM,
7789 SelectionDAG &DAG) const {
7792 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7793 VT = LD->getMemoryVT();
7794 Ptr = LD->getBasePtr();
7795 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7796 VT = ST->getMemoryVT();
7797 Ptr = ST->getBasePtr();
7802 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
7804 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
7808 bool AArch64TargetLowering::getPostIndexedAddressParts(
7809 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
7810 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
7813 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7814 VT = LD->getMemoryVT();
7815 Ptr = LD->getBasePtr();
7816 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7817 VT = ST->getMemoryVT();
7818 Ptr = ST->getBasePtr();
7823 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
7825 // Post-indexing updates the base, so it's not a valid transform
7826 // if that's not the same as the load's pointer.
7829 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
7833 void AArch64TargetLowering::ReplaceNodeResults(
7834 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
7835 switch (N->getOpcode()) {
7837 llvm_unreachable("Don't know how to custom expand this");
7838 case ISD::FP_TO_UINT:
7839 case ISD::FP_TO_SINT:
7840 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
7841 // Let normal code take care of it by not adding anything to Results.
7846 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
7847 // Loads and stores less than 128-bits are already atomic; ones above that
7848 // are doomed anyway, so defer to the default libcall and blame the OS when
7850 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
7851 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
7852 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
7853 return LI->getType()->getPrimitiveSizeInBits() == 128;
7855 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
7856 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
7859 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
7860 AtomicOrdering Ord) const {
7861 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7862 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
7864 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7866 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
7867 // intrinsic must return {i64, i64} and we have to recombine them into a
7868 // single i128 here.
7869 if (ValTy->getPrimitiveSizeInBits() == 128) {
7871 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
7872 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
7874 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7875 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
7877 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
7878 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
7879 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
7880 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
7881 return Builder.CreateOr(
7882 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
7885 Type *Tys[] = { Addr->getType() };
7887 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
7888 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
7890 return Builder.CreateTruncOrBitCast(
7891 Builder.CreateCall(Ldxr, Addr),
7892 cast<PointerType>(Addr->getType())->getElementType());
7895 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
7896 Value *Val, Value *Addr,
7897 AtomicOrdering Ord) const {
7898 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7900 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7902 // Since the intrinsics must have legal type, the i128 intrinsics take two
7903 // parameters: "i64, i64". We must marshal Val into the appropriate form
7905 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
7907 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
7908 Function *Stxr = Intrinsic::getDeclaration(M, Int);
7909 Type *Int64Ty = Type::getInt64Ty(M->getContext());
7911 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
7912 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
7913 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7914 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
7918 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
7919 Type *Tys[] = { Addr->getType() };
7920 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
7922 return Builder.CreateCall2(
7923 Stxr, Builder.CreateZExtOrBitCast(
7924 Val, Stxr->getFunctionType()->getParamType(0)),