1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "aarch64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
49 static cl::opt<AlignMode>
50 Align(cl::desc("Load/store alignment support"),
51 cl::Hidden, cl::init(NoStrictAlign),
53 clEnumValN(StrictAlign, "aarch64-strict-align",
54 "Disallow all unaligned memory accesses"),
55 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
56 "Allow unaligned memory accesses"),
59 // Place holder until extr generation is tested fully.
61 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
62 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
66 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
67 cl::desc("Allow AArch64 SLI/SRI formation"),
70 // FIXME: The necessary dtprel relocations don't seem to be supported
71 // well in the GNU bfd and gold linkers at the moment. Therefore, by
72 // default, for now, fall back to GeneralDynamic code generation.
73 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
74 "aarch64-elf-ldtls-generation", cl::Hidden,
75 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
78 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
79 const AArch64Subtarget &STI)
80 : TargetLowering(TM), Subtarget(&STI) {
82 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
83 // we have to make something up. Arbitrarily, choose ZeroOrOne.
84 setBooleanContents(ZeroOrOneBooleanContent);
85 // When comparing vectors the result sets the different elements in the
86 // vector to all-one or all-zero.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // Set up the register classes.
90 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
91 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
93 if (Subtarget->hasFPARMv8()) {
94 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
95 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
96 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
97 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
100 if (Subtarget->hasNEON()) {
101 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
102 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
103 // Someone set us up the NEON.
104 addDRTypeForNEON(MVT::v2f32);
105 addDRTypeForNEON(MVT::v8i8);
106 addDRTypeForNEON(MVT::v4i16);
107 addDRTypeForNEON(MVT::v2i32);
108 addDRTypeForNEON(MVT::v1i64);
109 addDRTypeForNEON(MVT::v1f64);
110 addDRTypeForNEON(MVT::v4f16);
112 addQRTypeForNEON(MVT::v4f32);
113 addQRTypeForNEON(MVT::v2f64);
114 addQRTypeForNEON(MVT::v16i8);
115 addQRTypeForNEON(MVT::v8i16);
116 addQRTypeForNEON(MVT::v4i32);
117 addQRTypeForNEON(MVT::v2i64);
118 addQRTypeForNEON(MVT::v8f16);
121 // Compute derived properties from the register classes
122 computeRegisterProperties(Subtarget->getRegisterInfo());
124 // Provide all sorts of operation actions
125 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
126 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 setOperationAction(ISD::SETCC, MVT::i64, Custom);
129 setOperationAction(ISD::SETCC, MVT::f32, Custom);
130 setOperationAction(ISD::SETCC, MVT::f64, Custom);
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
132 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
134 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
136 setOperationAction(ISD::SELECT, MVT::i32, Custom);
137 setOperationAction(ISD::SELECT, MVT::i64, Custom);
138 setOperationAction(ISD::SELECT, MVT::f32, Custom);
139 setOperationAction(ISD::SELECT, MVT::f64, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
145 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
147 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
151 setOperationAction(ISD::FREM, MVT::f32, Expand);
152 setOperationAction(ISD::FREM, MVT::f64, Expand);
153 setOperationAction(ISD::FREM, MVT::f80, Expand);
155 // Custom lowering hooks are needed for XOR
156 // to fold it into CSINC/CSINV.
157 setOperationAction(ISD::XOR, MVT::i32, Custom);
158 setOperationAction(ISD::XOR, MVT::i64, Custom);
160 // Virtually no operation on f128 is legal, but LLVM can't expand them when
161 // there's a valid register class, so we need custom operations in most cases.
162 setOperationAction(ISD::FABS, MVT::f128, Expand);
163 setOperationAction(ISD::FADD, MVT::f128, Custom);
164 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
165 setOperationAction(ISD::FCOS, MVT::f128, Expand);
166 setOperationAction(ISD::FDIV, MVT::f128, Custom);
167 setOperationAction(ISD::FMA, MVT::f128, Expand);
168 setOperationAction(ISD::FMUL, MVT::f128, Custom);
169 setOperationAction(ISD::FNEG, MVT::f128, Expand);
170 setOperationAction(ISD::FPOW, MVT::f128, Expand);
171 setOperationAction(ISD::FREM, MVT::f128, Expand);
172 setOperationAction(ISD::FRINT, MVT::f128, Expand);
173 setOperationAction(ISD::FSIN, MVT::f128, Expand);
174 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
175 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
176 setOperationAction(ISD::FSUB, MVT::f128, Custom);
177 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
178 setOperationAction(ISD::SETCC, MVT::f128, Custom);
179 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
180 setOperationAction(ISD::SELECT, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
182 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
184 // Lowering for many of the conversions is actually specified by the non-f128
185 // type. The LowerXXX function will be trivial when f128 isn't involved.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
192 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
198 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
201 // Variable arguments.
202 setOperationAction(ISD::VASTART, MVT::Other, Custom);
203 setOperationAction(ISD::VAARG, MVT::Other, Custom);
204 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
205 setOperationAction(ISD::VAEND, MVT::Other, Expand);
207 // Variable-sized objects.
208 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
209 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
210 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
212 // Exception handling.
213 // FIXME: These are guesses. Has this been defined yet?
214 setExceptionPointerRegister(AArch64::X0);
215 setExceptionSelectorRegister(AArch64::X1);
217 // Constant pool entries
218 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
221 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
223 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
224 setOperationAction(ISD::ADDC, MVT::i32, Custom);
225 setOperationAction(ISD::ADDE, MVT::i32, Custom);
226 setOperationAction(ISD::SUBC, MVT::i32, Custom);
227 setOperationAction(ISD::SUBE, MVT::i32, Custom);
228 setOperationAction(ISD::ADDC, MVT::i64, Custom);
229 setOperationAction(ISD::ADDE, MVT::i64, Custom);
230 setOperationAction(ISD::SUBC, MVT::i64, Custom);
231 setOperationAction(ISD::SUBE, MVT::i64, Custom);
233 // AArch64 lacks both left-rotate and popcount instructions.
234 setOperationAction(ISD::ROTL, MVT::i32, Expand);
235 setOperationAction(ISD::ROTL, MVT::i64, Expand);
237 // AArch64 doesn't have {U|S}MUL_LOHI.
238 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
239 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
242 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
243 // counterparts, which AArch64 supports directly.
244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
245 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
247 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
249 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
250 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
252 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
253 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
254 setOperationAction(ISD::SREM, MVT::i32, Expand);
255 setOperationAction(ISD::SREM, MVT::i64, Expand);
256 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
258 setOperationAction(ISD::UREM, MVT::i32, Expand);
259 setOperationAction(ISD::UREM, MVT::i64, Expand);
261 // Custom lower Add/Sub/Mul with overflow.
262 setOperationAction(ISD::SADDO, MVT::i32, Custom);
263 setOperationAction(ISD::SADDO, MVT::i64, Custom);
264 setOperationAction(ISD::UADDO, MVT::i32, Custom);
265 setOperationAction(ISD::UADDO, MVT::i64, Custom);
266 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
268 setOperationAction(ISD::USUBO, MVT::i32, Custom);
269 setOperationAction(ISD::USUBO, MVT::i64, Custom);
270 setOperationAction(ISD::SMULO, MVT::i32, Custom);
271 setOperationAction(ISD::SMULO, MVT::i64, Custom);
272 setOperationAction(ISD::UMULO, MVT::i32, Custom);
273 setOperationAction(ISD::UMULO, MVT::i64, Custom);
275 setOperationAction(ISD::FSIN, MVT::f32, Expand);
276 setOperationAction(ISD::FSIN, MVT::f64, Expand);
277 setOperationAction(ISD::FCOS, MVT::f32, Expand);
278 setOperationAction(ISD::FCOS, MVT::f64, Expand);
279 setOperationAction(ISD::FPOW, MVT::f32, Expand);
280 setOperationAction(ISD::FPOW, MVT::f64, Expand);
281 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
284 // f16 is a storage-only type, always promote it to f32.
285 setOperationAction(ISD::SETCC, MVT::f16, Promote);
286 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
287 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
288 setOperationAction(ISD::SELECT, MVT::f16, Promote);
289 setOperationAction(ISD::FADD, MVT::f16, Promote);
290 setOperationAction(ISD::FSUB, MVT::f16, Promote);
291 setOperationAction(ISD::FMUL, MVT::f16, Promote);
292 setOperationAction(ISD::FDIV, MVT::f16, Promote);
293 setOperationAction(ISD::FREM, MVT::f16, Promote);
294 setOperationAction(ISD::FMA, MVT::f16, Promote);
295 setOperationAction(ISD::FNEG, MVT::f16, Promote);
296 setOperationAction(ISD::FABS, MVT::f16, Promote);
297 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
298 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
299 setOperationAction(ISD::FCOS, MVT::f16, Promote);
300 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
301 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
302 setOperationAction(ISD::FPOW, MVT::f16, Promote);
303 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
304 setOperationAction(ISD::FRINT, MVT::f16, Promote);
305 setOperationAction(ISD::FSIN, MVT::f16, Promote);
306 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
307 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
308 setOperationAction(ISD::FEXP, MVT::f16, Promote);
309 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
310 setOperationAction(ISD::FLOG, MVT::f16, Promote);
311 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
312 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
313 setOperationAction(ISD::FROUND, MVT::f16, Promote);
314 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
315 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
316 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
318 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
320 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
321 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
322 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
323 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
324 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
325 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
326 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
327 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
328 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
329 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
330 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
331 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
333 // Expand all other v4f16 operations.
334 // FIXME: We could generate better code by promoting some operations to
336 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
337 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
338 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
339 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
340 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
341 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
342 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
343 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
344 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
345 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
346 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
347 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
348 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
349 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
350 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
351 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
352 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
353 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
354 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
355 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
356 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
357 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
358 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
359 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
360 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
361 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
364 // v8f16 is also a storage-only type, so expand it.
365 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
366 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
367 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
368 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
369 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
370 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
371 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
372 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
373 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
374 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
375 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
376 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
377 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
378 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
379 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
380 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
381 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
382 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
383 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
384 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
385 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
386 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
387 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
388 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
389 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
390 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
391 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
392 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
393 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
394 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
395 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
397 // AArch64 has implementations of a lot of rounding-like FP operations.
398 for (MVT Ty : {MVT::f32, MVT::f64}) {
399 setOperationAction(ISD::FFLOOR, Ty, Legal);
400 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
401 setOperationAction(ISD::FCEIL, Ty, Legal);
402 setOperationAction(ISD::FRINT, Ty, Legal);
403 setOperationAction(ISD::FTRUNC, Ty, Legal);
404 setOperationAction(ISD::FROUND, Ty, Legal);
407 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
409 if (Subtarget->isTargetMachO()) {
410 // For iOS, we don't want to the normal expansion of a libcall to
411 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
413 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
414 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
416 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
417 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
420 // Make floating-point constants legal for the large code model, so they don't
421 // become loads from the constant pool.
422 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
423 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
424 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
427 // AArch64 does not have floating-point extending loads, i1 sign-extending
428 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
429 for (MVT VT : MVT::fp_valuetypes()) {
430 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
435 for (MVT VT : MVT::integer_valuetypes())
436 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
438 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
439 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
440 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
441 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
442 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
443 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
444 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
446 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
447 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
449 // Indexed loads and stores are supported.
450 for (unsigned im = (unsigned)ISD::PRE_INC;
451 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
452 setIndexedLoadAction(im, MVT::i8, Legal);
453 setIndexedLoadAction(im, MVT::i16, Legal);
454 setIndexedLoadAction(im, MVT::i32, Legal);
455 setIndexedLoadAction(im, MVT::i64, Legal);
456 setIndexedLoadAction(im, MVT::f64, Legal);
457 setIndexedLoadAction(im, MVT::f32, Legal);
458 setIndexedStoreAction(im, MVT::i8, Legal);
459 setIndexedStoreAction(im, MVT::i16, Legal);
460 setIndexedStoreAction(im, MVT::i32, Legal);
461 setIndexedStoreAction(im, MVT::i64, Legal);
462 setIndexedStoreAction(im, MVT::f64, Legal);
463 setIndexedStoreAction(im, MVT::f32, Legal);
467 setOperationAction(ISD::TRAP, MVT::Other, Legal);
469 // We combine OR nodes for bitfield operations.
470 setTargetDAGCombine(ISD::OR);
472 // Vector add and sub nodes may conceal a high-half opportunity.
473 // Also, try to fold ADD into CSINC/CSINV..
474 setTargetDAGCombine(ISD::ADD);
475 setTargetDAGCombine(ISD::SUB);
477 setTargetDAGCombine(ISD::XOR);
478 setTargetDAGCombine(ISD::SINT_TO_FP);
479 setTargetDAGCombine(ISD::UINT_TO_FP);
481 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
483 setTargetDAGCombine(ISD::ANY_EXTEND);
484 setTargetDAGCombine(ISD::ZERO_EXTEND);
485 setTargetDAGCombine(ISD::SIGN_EXTEND);
486 setTargetDAGCombine(ISD::BITCAST);
487 setTargetDAGCombine(ISD::CONCAT_VECTORS);
488 setTargetDAGCombine(ISD::STORE);
490 setTargetDAGCombine(ISD::MUL);
492 setTargetDAGCombine(ISD::SELECT);
493 setTargetDAGCombine(ISD::VSELECT);
495 setTargetDAGCombine(ISD::INTRINSIC_VOID);
496 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
497 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
499 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
500 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
501 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
503 setStackPointerRegisterToSaveRestore(AArch64::SP);
505 setSchedulingPreference(Sched::Hybrid);
508 MaskAndBranchFoldingIsLegal = true;
509 EnableExtLdPromotion = true;
511 setMinFunctionAlignment(2);
513 RequireStrictAlign = (Align == StrictAlign);
515 setHasExtractBitsInsn(true);
517 if (Subtarget->hasNEON()) {
518 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
519 // silliness like this:
520 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
521 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
522 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
523 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
524 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
525 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
526 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
527 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
528 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
529 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
530 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
531 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
532 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
533 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
534 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
535 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
536 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
537 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
538 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
539 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
540 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
541 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
542 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
543 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
544 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
546 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
547 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
548 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
549 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
550 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
552 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
554 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
555 // elements smaller than i32, so promote the input to i32 first.
556 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
557 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
558 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
560 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
561 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
562 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
563 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
564 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
566 // AArch64 doesn't have MUL.2d:
567 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
568 // Custom handling for some quad-vector types to detect MULL.
569 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
570 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
571 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
573 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
574 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
575 // Likewise, narrowing and extending vector loads/stores aren't handled
577 for (MVT VT : MVT::vector_valuetypes()) {
578 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
580 setOperationAction(ISD::MULHS, VT, Expand);
581 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
582 setOperationAction(ISD::MULHU, VT, Expand);
583 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
585 setOperationAction(ISD::BSWAP, VT, Expand);
587 for (MVT InnerVT : MVT::vector_valuetypes()) {
588 setTruncStoreAction(VT, InnerVT, Expand);
589 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
590 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
591 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
595 // AArch64 has implementations of a lot of rounding-like FP operations.
596 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
597 setOperationAction(ISD::FFLOOR, Ty, Legal);
598 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
599 setOperationAction(ISD::FCEIL, Ty, Legal);
600 setOperationAction(ISD::FRINT, Ty, Legal);
601 setOperationAction(ISD::FTRUNC, Ty, Legal);
602 setOperationAction(ISD::FROUND, Ty, Legal);
606 // Prefer likely predicted branches to selects on out-of-order cores.
607 if (Subtarget->isCortexA57())
608 PredictableSelectIsExpensive = true;
611 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
612 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
613 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
614 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
616 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
617 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
618 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
619 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
620 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
622 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
623 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
626 // Mark vector float intrinsics as expand.
627 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
628 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
629 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
630 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
631 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
632 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
633 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
634 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
635 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
636 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
639 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
640 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
641 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
642 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
643 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
644 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
645 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
646 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
647 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
648 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
649 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
650 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
652 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
653 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
654 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
655 for (MVT InnerVT : MVT::all_valuetypes())
656 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
658 // CNT supports only B element sizes.
659 if (VT != MVT::v8i8 && VT != MVT::v16i8)
660 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
662 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
663 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
664 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
665 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
666 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
668 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
669 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
671 if (Subtarget->isLittleEndian()) {
672 for (unsigned im = (unsigned)ISD::PRE_INC;
673 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
674 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
675 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
680 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
681 addRegisterClass(VT, &AArch64::FPR64RegClass);
682 addTypeForNEON(VT, MVT::v2i32);
685 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
686 addRegisterClass(VT, &AArch64::FPR128RegClass);
687 addTypeForNEON(VT, MVT::v4i32);
690 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
693 return VT.changeVectorElementTypeToInteger();
696 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
697 /// Mask are known to be either zero or one and return them in the
698 /// KnownZero/KnownOne bitsets.
699 void AArch64TargetLowering::computeKnownBitsForTargetNode(
700 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
701 const SelectionDAG &DAG, unsigned Depth) const {
702 switch (Op.getOpcode()) {
705 case AArch64ISD::CSEL: {
706 APInt KnownZero2, KnownOne2;
707 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
708 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
709 KnownZero &= KnownZero2;
710 KnownOne &= KnownOne2;
713 case ISD::INTRINSIC_W_CHAIN: {
714 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
715 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
718 case Intrinsic::aarch64_ldaxr:
719 case Intrinsic::aarch64_ldxr: {
720 unsigned BitWidth = KnownOne.getBitWidth();
721 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
722 unsigned MemBits = VT.getScalarType().getSizeInBits();
723 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
729 case ISD::INTRINSIC_WO_CHAIN:
730 case ISD::INTRINSIC_VOID: {
731 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
735 case Intrinsic::aarch64_neon_umaxv:
736 case Intrinsic::aarch64_neon_uminv: {
737 // Figure out the datatype of the vector operand. The UMINV instruction
738 // will zero extend the result, so we can mark as known zero all the
739 // bits larger than the element datatype. 32-bit or larget doesn't need
740 // this as those are legal types and will be handled by isel directly.
741 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
742 unsigned BitWidth = KnownZero.getBitWidth();
743 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
744 assert(BitWidth >= 8 && "Unexpected width!");
745 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
747 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
748 assert(BitWidth >= 16 && "Unexpected width!");
749 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
759 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
764 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
765 const TargetLibraryInfo *libInfo) const {
766 return AArch64::createFastISel(funcInfo, libInfo);
769 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
773 case AArch64ISD::CALL: return "AArch64ISD::CALL";
774 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
775 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
776 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
777 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
778 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
779 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
780 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
781 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
782 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
783 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
784 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
785 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
786 case AArch64ISD::ADC: return "AArch64ISD::ADC";
787 case AArch64ISD::SBC: return "AArch64ISD::SBC";
788 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
789 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
790 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
791 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
792 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
793 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
794 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
795 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
796 case AArch64ISD::DUP: return "AArch64ISD::DUP";
797 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
798 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
799 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
800 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
801 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
802 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
803 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
804 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
805 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
806 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
807 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
808 case AArch64ISD::BICi: return "AArch64ISD::BICi";
809 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
810 case AArch64ISD::BSL: return "AArch64ISD::BSL";
811 case AArch64ISD::NEG: return "AArch64ISD::NEG";
812 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
813 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
814 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
815 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
816 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
817 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
818 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
819 case AArch64ISD::REV16: return "AArch64ISD::REV16";
820 case AArch64ISD::REV32: return "AArch64ISD::REV32";
821 case AArch64ISD::REV64: return "AArch64ISD::REV64";
822 case AArch64ISD::EXT: return "AArch64ISD::EXT";
823 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
824 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
825 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
826 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
827 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
828 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
829 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
830 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
831 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
832 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
833 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
834 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
835 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
836 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
837 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
838 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
839 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
840 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
841 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
842 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
843 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
844 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
845 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
846 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
847 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
848 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
849 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
850 case AArch64ISD::NOT: return "AArch64ISD::NOT";
851 case AArch64ISD::BIT: return "AArch64ISD::BIT";
852 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
853 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
854 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
855 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
856 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
857 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
858 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
859 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
860 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
861 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
862 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
863 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
864 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
865 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
866 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
867 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
868 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
869 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
870 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
871 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
872 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
873 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
874 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
875 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
876 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
877 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
878 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
879 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
880 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
881 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
882 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
883 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
884 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
885 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
886 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
887 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
888 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
889 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
890 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
895 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
896 MachineBasicBlock *MBB) const {
897 // We materialise the F128CSEL pseudo-instruction as some control flow and a
901 // [... previous instrs leading to comparison ...]
907 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
909 MachineFunction *MF = MBB->getParent();
910 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
911 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
912 DebugLoc DL = MI->getDebugLoc();
913 MachineFunction::iterator It = MBB;
916 unsigned DestReg = MI->getOperand(0).getReg();
917 unsigned IfTrueReg = MI->getOperand(1).getReg();
918 unsigned IfFalseReg = MI->getOperand(2).getReg();
919 unsigned CondCode = MI->getOperand(3).getImm();
920 bool NZCVKilled = MI->getOperand(4).isKill();
922 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
923 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
924 MF->insert(It, TrueBB);
925 MF->insert(It, EndBB);
927 // Transfer rest of current basic-block to EndBB
928 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
930 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
932 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
933 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
934 MBB->addSuccessor(TrueBB);
935 MBB->addSuccessor(EndBB);
937 // TrueBB falls through to the end.
938 TrueBB->addSuccessor(EndBB);
941 TrueBB->addLiveIn(AArch64::NZCV);
942 EndBB->addLiveIn(AArch64::NZCV);
945 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
951 MI->eraseFromParent();
956 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
957 MachineBasicBlock *BB) const {
958 switch (MI->getOpcode()) {
963 llvm_unreachable("Unexpected instruction for custom inserter!");
965 case AArch64::F128CSEL:
966 return EmitF128CSEL(MI, BB);
968 case TargetOpcode::STACKMAP:
969 case TargetOpcode::PATCHPOINT:
970 return emitPatchPoint(MI, BB);
974 //===----------------------------------------------------------------------===//
975 // AArch64 Lowering private implementation.
976 //===----------------------------------------------------------------------===//
978 //===----------------------------------------------------------------------===//
980 //===----------------------------------------------------------------------===//
982 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
984 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
987 llvm_unreachable("Unknown condition code!");
989 return AArch64CC::NE;
991 return AArch64CC::EQ;
993 return AArch64CC::GT;
995 return AArch64CC::GE;
997 return AArch64CC::LT;
999 return AArch64CC::LE;
1001 return AArch64CC::HI;
1003 return AArch64CC::HS;
1005 return AArch64CC::LO;
1007 return AArch64CC::LS;
1011 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1012 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1013 AArch64CC::CondCode &CondCode,
1014 AArch64CC::CondCode &CondCode2) {
1015 CondCode2 = AArch64CC::AL;
1018 llvm_unreachable("Unknown FP condition!");
1021 CondCode = AArch64CC::EQ;
1025 CondCode = AArch64CC::GT;
1029 CondCode = AArch64CC::GE;
1032 CondCode = AArch64CC::MI;
1035 CondCode = AArch64CC::LS;
1038 CondCode = AArch64CC::MI;
1039 CondCode2 = AArch64CC::GT;
1042 CondCode = AArch64CC::VC;
1045 CondCode = AArch64CC::VS;
1048 CondCode = AArch64CC::EQ;
1049 CondCode2 = AArch64CC::VS;
1052 CondCode = AArch64CC::HI;
1055 CondCode = AArch64CC::PL;
1059 CondCode = AArch64CC::LT;
1063 CondCode = AArch64CC::LE;
1067 CondCode = AArch64CC::NE;
1072 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1073 /// CC usable with the vector instructions. Fewer operations are available
1074 /// without a real NZCV register, so we have to use less efficient combinations
1075 /// to get the same effect.
1076 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1077 AArch64CC::CondCode &CondCode,
1078 AArch64CC::CondCode &CondCode2,
1083 // Mostly the scalar mappings work fine.
1084 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1087 Invert = true; // Fallthrough
1089 CondCode = AArch64CC::MI;
1090 CondCode2 = AArch64CC::GE;
1097 // All of the compare-mask comparisons are ordered, but we can switch
1098 // between the two by a double inversion. E.g. ULE == !OGT.
1100 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1105 static bool isLegalArithImmed(uint64_t C) {
1106 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1107 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1110 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1111 SDLoc dl, SelectionDAG &DAG) {
1112 EVT VT = LHS.getValueType();
1114 if (VT.isFloatingPoint())
1115 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1117 // The CMP instruction is just an alias for SUBS, and representing it as
1118 // SUBS means that it's possible to get CSE with subtract operations.
1119 // A later phase can perform the optimization of setting the destination
1120 // register to WZR/XZR if it ends up being unused.
1121 unsigned Opcode = AArch64ISD::SUBS;
1123 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1124 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1125 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1126 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1127 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1128 // can be set differently by this operation. It comes down to whether
1129 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1130 // everything is fine. If not then the optimization is wrong. Thus general
1131 // comparisons are only valid if op2 != 0.
1133 // So, finally, the only LLVM-native comparisons that don't mention C and V
1134 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1135 // the absence of information about op2.
1136 Opcode = AArch64ISD::ADDS;
1137 RHS = RHS.getOperand(1);
1138 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1139 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1140 !isUnsignedIntSetCC(CC)) {
1141 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1142 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1143 // of the signed comparisons.
1144 Opcode = AArch64ISD::ANDS;
1145 RHS = LHS.getOperand(1);
1146 LHS = LHS.getOperand(0);
1149 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1153 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1154 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1156 AArch64CC::CondCode AArch64CC;
1157 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1158 EVT VT = RHS.getValueType();
1159 uint64_t C = RHSC->getZExtValue();
1160 if (!isLegalArithImmed(C)) {
1161 // Constant does not fit, try adjusting it by one?
1167 if ((VT == MVT::i32 && C != 0x80000000 &&
1168 isLegalArithImmed((uint32_t)(C - 1))) ||
1169 (VT == MVT::i64 && C != 0x80000000ULL &&
1170 isLegalArithImmed(C - 1ULL))) {
1171 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1172 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1173 RHS = DAG.getConstant(C, VT);
1178 if ((VT == MVT::i32 && C != 0 &&
1179 isLegalArithImmed((uint32_t)(C - 1))) ||
1180 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1181 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1182 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1183 RHS = DAG.getConstant(C, VT);
1188 if ((VT == MVT::i32 && C != INT32_MAX &&
1189 isLegalArithImmed((uint32_t)(C + 1))) ||
1190 (VT == MVT::i64 && C != INT64_MAX &&
1191 isLegalArithImmed(C + 1ULL))) {
1192 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1193 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1194 RHS = DAG.getConstant(C, VT);
1199 if ((VT == MVT::i32 && C != UINT32_MAX &&
1200 isLegalArithImmed((uint32_t)(C + 1))) ||
1201 (VT == MVT::i64 && C != UINT64_MAX &&
1202 isLegalArithImmed(C + 1ULL))) {
1203 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1204 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1205 RHS = DAG.getConstant(C, VT);
1211 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1212 // For the i8 operand, the largest immediate is 255, so this can be easily
1213 // encoded in the compare instruction. For the i16 operand, however, the
1214 // largest immediate cannot be encoded in the compare.
1215 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1216 // constant. For example,
1218 // ldrh w0, [x0, #0]
1221 // ldrsh w0, [x0, #0]
1223 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1224 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1225 // both the LHS and RHS are truely zero extended and to make sure the
1226 // transformation is profitable.
1227 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1228 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1229 isa<LoadSDNode>(LHS)) {
1230 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1231 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1232 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1233 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1234 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1236 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1237 DAG.getValueType(MVT::i16));
1238 Cmp = emitComparison(SExt,
1239 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1241 AArch64CC = changeIntCCToAArch64CC(CC);
1242 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1248 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1249 AArch64CC = changeIntCCToAArch64CC(CC);
1250 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1254 static std::pair<SDValue, SDValue>
1255 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1256 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1257 "Unsupported value type");
1258 SDValue Value, Overflow;
1260 SDValue LHS = Op.getOperand(0);
1261 SDValue RHS = Op.getOperand(1);
1263 switch (Op.getOpcode()) {
1265 llvm_unreachable("Unknown overflow instruction!");
1267 Opc = AArch64ISD::ADDS;
1271 Opc = AArch64ISD::ADDS;
1275 Opc = AArch64ISD::SUBS;
1279 Opc = AArch64ISD::SUBS;
1282 // Multiply needs a little bit extra work.
1286 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1287 if (Op.getValueType() == MVT::i32) {
1288 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1289 // For a 32 bit multiply with overflow check we want the instruction
1290 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1291 // need to generate the following pattern:
1292 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1293 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1294 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1295 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1296 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1297 DAG.getConstant(0, MVT::i64));
1298 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1299 // operation. We need to clear out the upper 32 bits, because we used a
1300 // widening multiply that wrote all 64 bits. In the end this should be a
1302 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1304 // The signed overflow check requires more than just a simple check for
1305 // any bit set in the upper 32 bits of the result. These bits could be
1306 // just the sign bits of a negative number. To perform the overflow
1307 // check we have to arithmetic shift right the 32nd bit of the result by
1308 // 31 bits. Then we compare the result to the upper 32 bits.
1309 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1310 DAG.getConstant(32, MVT::i64));
1311 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1312 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1313 DAG.getConstant(31, MVT::i64));
1314 // It is important that LowerBits is last, otherwise the arithmetic
1315 // shift will not be folded into the compare (SUBS).
1316 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1317 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1320 // The overflow check for unsigned multiply is easy. We only need to
1321 // check if any of the upper 32 bits are set. This can be done with a
1322 // CMP (shifted register). For that we need to generate the following
1324 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1325 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1326 DAG.getConstant(32, MVT::i64));
1327 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1329 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1330 UpperBits).getValue(1);
1334 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1335 // For the 64 bit multiply
1336 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1338 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1339 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1340 DAG.getConstant(63, MVT::i64));
1341 // It is important that LowerBits is last, otherwise the arithmetic
1342 // shift will not be folded into the compare (SUBS).
1343 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1344 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1347 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1348 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1350 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1351 UpperBits).getValue(1);
1358 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1360 // Emit the AArch64 operation with overflow check.
1361 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1362 Overflow = Value.getValue(1);
1364 return std::make_pair(Value, Overflow);
1367 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1368 RTLIB::Libcall Call) const {
1369 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1370 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1374 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1375 SDValue Sel = Op.getOperand(0);
1376 SDValue Other = Op.getOperand(1);
1378 // If neither operand is a SELECT_CC, give up.
1379 if (Sel.getOpcode() != ISD::SELECT_CC)
1380 std::swap(Sel, Other);
1381 if (Sel.getOpcode() != ISD::SELECT_CC)
1384 // The folding we want to perform is:
1385 // (xor x, (select_cc a, b, cc, 0, -1) )
1387 // (csel x, (xor x, -1), cc ...)
1389 // The latter will get matched to a CSINV instruction.
1391 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1392 SDValue LHS = Sel.getOperand(0);
1393 SDValue RHS = Sel.getOperand(1);
1394 SDValue TVal = Sel.getOperand(2);
1395 SDValue FVal = Sel.getOperand(3);
1398 // FIXME: This could be generalized to non-integer comparisons.
1399 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1402 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1403 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1405 // The the values aren't constants, this isn't the pattern we're looking for.
1406 if (!CFVal || !CTVal)
1409 // We can commute the SELECT_CC by inverting the condition. This
1410 // might be needed to make this fit into a CSINV pattern.
1411 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1412 std::swap(TVal, FVal);
1413 std::swap(CTVal, CFVal);
1414 CC = ISD::getSetCCInverse(CC, true);
1417 // If the constants line up, perform the transform!
1418 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1420 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1423 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1424 DAG.getConstant(-1ULL, Other.getValueType()));
1426 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1433 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1434 EVT VT = Op.getValueType();
1436 // Let legalize expand this if it isn't a legal type yet.
1437 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1440 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1443 bool ExtraOp = false;
1444 switch (Op.getOpcode()) {
1446 llvm_unreachable("Invalid code");
1448 Opc = AArch64ISD::ADDS;
1451 Opc = AArch64ISD::SUBS;
1454 Opc = AArch64ISD::ADCS;
1458 Opc = AArch64ISD::SBCS;
1464 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1465 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1469 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1470 // Let legalize expand this if it isn't a legal type yet.
1471 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1474 AArch64CC::CondCode CC;
1475 // The actual operation that sets the overflow or carry flag.
1476 SDValue Value, Overflow;
1477 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1479 // We use 0 and 1 as false and true values.
1480 SDValue TVal = DAG.getConstant(1, MVT::i32);
1481 SDValue FVal = DAG.getConstant(0, MVT::i32);
1483 // We use an inverted condition, because the conditional select is inverted
1484 // too. This will allow it to be selected to a single instruction:
1485 // CSINC Wd, WZR, WZR, invert(cond).
1486 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1487 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1490 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1491 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1494 // Prefetch operands are:
1495 // 1: Address to prefetch
1497 // 3: int locality (0 = no locality ... 3 = extreme locality)
1498 // 4: bool isDataCache
1499 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1501 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1502 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1503 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1505 bool IsStream = !Locality;
1506 // When the locality number is set
1508 // The front-end should have filtered out the out-of-range values
1509 assert(Locality <= 3 && "Prefetch locality out-of-range");
1510 // The locality degree is the opposite of the cache speed.
1511 // Put the number the other way around.
1512 // The encoding starts at 0 for level 1
1513 Locality = 3 - Locality;
1516 // built the mask value encoding the expected behavior.
1517 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1518 (!IsData << 3) | // IsDataCache bit
1519 (Locality << 1) | // Cache level bits
1520 (unsigned)IsStream; // Stream bit
1521 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1522 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1525 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1526 SelectionDAG &DAG) const {
1527 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1530 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1532 return LowerF128Call(Op, DAG, LC);
1535 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1536 SelectionDAG &DAG) const {
1537 if (Op.getOperand(0).getValueType() != MVT::f128) {
1538 // It's legal except when f128 is involved
1543 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1545 // FP_ROUND node has a second operand indicating whether it is known to be
1546 // precise. That doesn't take part in the LibCall so we can't directly use
1548 SDValue SrcVal = Op.getOperand(0);
1549 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1550 /*isSigned*/ false, SDLoc(Op)).first;
1553 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1554 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1555 // Any additional optimization in this function should be recorded
1556 // in the cost tables.
1557 EVT InVT = Op.getOperand(0).getValueType();
1558 EVT VT = Op.getValueType();
1560 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1563 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1565 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1568 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1571 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1572 VT.getVectorNumElements());
1573 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1574 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1577 // Type changing conversions are illegal.
1581 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1582 SelectionDAG &DAG) const {
1583 if (Op.getOperand(0).getValueType().isVector())
1584 return LowerVectorFP_TO_INT(Op, DAG);
1586 // f16 conversions are promoted to f32.
1587 if (Op.getOperand(0).getValueType() == MVT::f16) {
1590 Op.getOpcode(), dl, Op.getValueType(),
1591 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1594 if (Op.getOperand(0).getValueType() != MVT::f128) {
1595 // It's legal except when f128 is involved
1600 if (Op.getOpcode() == ISD::FP_TO_SINT)
1601 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1603 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1605 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1606 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1610 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1611 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1612 // Any additional optimization in this function should be recorded
1613 // in the cost tables.
1614 EVT VT = Op.getValueType();
1616 SDValue In = Op.getOperand(0);
1617 EVT InVT = In.getValueType();
1619 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1621 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1622 InVT.getVectorNumElements());
1623 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1624 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1627 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1629 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1630 EVT CastVT = VT.changeVectorElementTypeToInteger();
1631 In = DAG.getNode(CastOpc, dl, CastVT, In);
1632 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1638 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1639 SelectionDAG &DAG) const {
1640 if (Op.getValueType().isVector())
1641 return LowerVectorINT_TO_FP(Op, DAG);
1643 // f16 conversions are promoted to f32.
1644 if (Op.getValueType() == MVT::f16) {
1647 ISD::FP_ROUND, dl, MVT::f16,
1648 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1649 DAG.getIntPtrConstant(0));
1652 // i128 conversions are libcalls.
1653 if (Op.getOperand(0).getValueType() == MVT::i128)
1656 // Other conversions are legal, unless it's to the completely software-based
1658 if (Op.getValueType() != MVT::f128)
1662 if (Op.getOpcode() == ISD::SINT_TO_FP)
1663 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1665 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1667 return LowerF128Call(Op, DAG, LC);
1670 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1671 SelectionDAG &DAG) const {
1672 // For iOS, we want to call an alternative entry point: __sincos_stret,
1673 // which returns the values in two S / D registers.
1675 SDValue Arg = Op.getOperand(0);
1676 EVT ArgVT = Arg.getValueType();
1677 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1684 Entry.isSExt = false;
1685 Entry.isZExt = false;
1686 Args.push_back(Entry);
1688 const char *LibcallName =
1689 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1690 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1692 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1693 TargetLowering::CallLoweringInfo CLI(DAG);
1694 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1695 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1697 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1698 return CallResult.first;
1701 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1702 if (Op.getValueType() != MVT::f16)
1705 assert(Op.getOperand(0).getValueType() == MVT::i16);
1708 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1709 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1711 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1712 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1716 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1717 if (OrigVT.getSizeInBits() >= 64)
1720 assert(OrigVT.isSimple() && "Expecting a simple value type");
1722 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1723 switch (OrigSimpleTy) {
1724 default: llvm_unreachable("Unexpected Vector Type");
1733 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1736 unsigned ExtOpcode) {
1737 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1738 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1739 // 64-bits we need to insert a new extension so that it will be 64-bits.
1740 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1741 if (OrigTy.getSizeInBits() >= 64)
1744 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1745 EVT NewVT = getExtensionTo64Bits(OrigTy);
1747 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1750 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1752 EVT VT = N->getValueType(0);
1754 if (N->getOpcode() != ISD::BUILD_VECTOR)
1757 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1758 SDNode *Elt = N->getOperand(i).getNode();
1759 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1760 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1761 unsigned HalfSize = EltSize / 2;
1763 if (!isIntN(HalfSize, C->getSExtValue()))
1766 if (!isUIntN(HalfSize, C->getZExtValue()))
1777 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1778 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1779 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1780 N->getOperand(0)->getValueType(0),
1784 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1785 EVT VT = N->getValueType(0);
1786 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1787 unsigned NumElts = VT.getVectorNumElements();
1788 MVT TruncVT = MVT::getIntegerVT(EltSize);
1789 SmallVector<SDValue, 8> Ops;
1790 for (unsigned i = 0; i != NumElts; ++i) {
1791 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1792 const APInt &CInt = C->getAPIntValue();
1793 // Element types smaller than 32 bits are not legal, so use i32 elements.
1794 // The values are implicitly truncated so sext vs. zext doesn't matter.
1795 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
1797 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
1798 MVT::getVectorVT(TruncVT, NumElts), Ops);
1801 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1802 if (N->getOpcode() == ISD::SIGN_EXTEND)
1804 if (isExtendedBUILD_VECTOR(N, DAG, true))
1809 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1810 if (N->getOpcode() == ISD::ZERO_EXTEND)
1812 if (isExtendedBUILD_VECTOR(N, DAG, false))
1817 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1818 unsigned Opcode = N->getOpcode();
1819 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1820 SDNode *N0 = N->getOperand(0).getNode();
1821 SDNode *N1 = N->getOperand(1).getNode();
1822 return N0->hasOneUse() && N1->hasOneUse() &&
1823 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1828 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1829 unsigned Opcode = N->getOpcode();
1830 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1831 SDNode *N0 = N->getOperand(0).getNode();
1832 SDNode *N1 = N->getOperand(1).getNode();
1833 return N0->hasOneUse() && N1->hasOneUse() &&
1834 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1839 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1840 // Multiplications are only custom-lowered for 128-bit vectors so that
1841 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1842 EVT VT = Op.getValueType();
1843 assert(VT.is128BitVector() && VT.isInteger() &&
1844 "unexpected type for custom-lowering ISD::MUL");
1845 SDNode *N0 = Op.getOperand(0).getNode();
1846 SDNode *N1 = Op.getOperand(1).getNode();
1847 unsigned NewOpc = 0;
1849 bool isN0SExt = isSignExtended(N0, DAG);
1850 bool isN1SExt = isSignExtended(N1, DAG);
1851 if (isN0SExt && isN1SExt)
1852 NewOpc = AArch64ISD::SMULL;
1854 bool isN0ZExt = isZeroExtended(N0, DAG);
1855 bool isN1ZExt = isZeroExtended(N1, DAG);
1856 if (isN0ZExt && isN1ZExt)
1857 NewOpc = AArch64ISD::UMULL;
1858 else if (isN1SExt || isN1ZExt) {
1859 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1860 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1861 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1862 NewOpc = AArch64ISD::SMULL;
1864 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1865 NewOpc = AArch64ISD::UMULL;
1867 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1869 NewOpc = AArch64ISD::UMULL;
1875 if (VT == MVT::v2i64)
1876 // Fall through to expand this. It is not legal.
1879 // Other vector multiplications are legal.
1884 // Legalize to a S/UMULL instruction
1887 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1889 Op0 = skipExtensionForVectorMULL(N0, DAG);
1890 assert(Op0.getValueType().is64BitVector() &&
1891 Op1.getValueType().is64BitVector() &&
1892 "unexpected types for extended operands to VMULL");
1893 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1895 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1896 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1897 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1898 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1899 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1900 EVT Op1VT = Op1.getValueType();
1901 return DAG.getNode(N0->getOpcode(), DL, VT,
1902 DAG.getNode(NewOpc, DL, VT,
1903 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1904 DAG.getNode(NewOpc, DL, VT,
1905 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1908 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1909 SelectionDAG &DAG) const {
1910 switch (Op.getOpcode()) {
1912 llvm_unreachable("unimplemented operand");
1915 return LowerBITCAST(Op, DAG);
1916 case ISD::GlobalAddress:
1917 return LowerGlobalAddress(Op, DAG);
1918 case ISD::GlobalTLSAddress:
1919 return LowerGlobalTLSAddress(Op, DAG);
1921 return LowerSETCC(Op, DAG);
1923 return LowerBR_CC(Op, DAG);
1925 return LowerSELECT(Op, DAG);
1926 case ISD::SELECT_CC:
1927 return LowerSELECT_CC(Op, DAG);
1928 case ISD::JumpTable:
1929 return LowerJumpTable(Op, DAG);
1930 case ISD::ConstantPool:
1931 return LowerConstantPool(Op, DAG);
1932 case ISD::BlockAddress:
1933 return LowerBlockAddress(Op, DAG);
1935 return LowerVASTART(Op, DAG);
1937 return LowerVACOPY(Op, DAG);
1939 return LowerVAARG(Op, DAG);
1944 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1951 return LowerXALUO(Op, DAG);
1953 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1955 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1957 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1959 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1961 return LowerFP_ROUND(Op, DAG);
1962 case ISD::FP_EXTEND:
1963 return LowerFP_EXTEND(Op, DAG);
1964 case ISD::FRAMEADDR:
1965 return LowerFRAMEADDR(Op, DAG);
1966 case ISD::RETURNADDR:
1967 return LowerRETURNADDR(Op, DAG);
1968 case ISD::INSERT_VECTOR_ELT:
1969 return LowerINSERT_VECTOR_ELT(Op, DAG);
1970 case ISD::EXTRACT_VECTOR_ELT:
1971 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1972 case ISD::BUILD_VECTOR:
1973 return LowerBUILD_VECTOR(Op, DAG);
1974 case ISD::VECTOR_SHUFFLE:
1975 return LowerVECTOR_SHUFFLE(Op, DAG);
1976 case ISD::EXTRACT_SUBVECTOR:
1977 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1981 return LowerVectorSRA_SRL_SHL(Op, DAG);
1982 case ISD::SHL_PARTS:
1983 return LowerShiftLeftParts(Op, DAG);
1984 case ISD::SRL_PARTS:
1985 case ISD::SRA_PARTS:
1986 return LowerShiftRightParts(Op, DAG);
1988 return LowerCTPOP(Op, DAG);
1989 case ISD::FCOPYSIGN:
1990 return LowerFCOPYSIGN(Op, DAG);
1992 return LowerVectorAND(Op, DAG);
1994 return LowerVectorOR(Op, DAG);
1996 return LowerXOR(Op, DAG);
1998 return LowerPREFETCH(Op, DAG);
1999 case ISD::SINT_TO_FP:
2000 case ISD::UINT_TO_FP:
2001 return LowerINT_TO_FP(Op, DAG);
2002 case ISD::FP_TO_SINT:
2003 case ISD::FP_TO_UINT:
2004 return LowerFP_TO_INT(Op, DAG);
2006 return LowerFSINCOS(Op, DAG);
2008 return LowerMUL(Op, DAG);
2012 /// getFunctionAlignment - Return the Log2 alignment of this function.
2013 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2017 //===----------------------------------------------------------------------===//
2018 // Calling Convention Implementation
2019 //===----------------------------------------------------------------------===//
2021 #include "AArch64GenCallingConv.inc"
2023 /// Selects the correct CCAssignFn for a given CallingConvention value.
2024 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2025 bool IsVarArg) const {
2028 llvm_unreachable("Unsupported calling convention.");
2029 case CallingConv::WebKit_JS:
2030 return CC_AArch64_WebKit_JS;
2031 case CallingConv::GHC:
2032 return CC_AArch64_GHC;
2033 case CallingConv::C:
2034 case CallingConv::Fast:
2035 if (!Subtarget->isTargetDarwin())
2036 return CC_AArch64_AAPCS;
2037 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2041 SDValue AArch64TargetLowering::LowerFormalArguments(
2042 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2043 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2044 SmallVectorImpl<SDValue> &InVals) const {
2045 MachineFunction &MF = DAG.getMachineFunction();
2046 MachineFrameInfo *MFI = MF.getFrameInfo();
2048 // Assign locations to all of the incoming arguments.
2049 SmallVector<CCValAssign, 16> ArgLocs;
2050 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2053 // At this point, Ins[].VT may already be promoted to i32. To correctly
2054 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2055 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2056 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2057 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2059 unsigned NumArgs = Ins.size();
2060 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2061 unsigned CurArgIdx = 0;
2062 for (unsigned i = 0; i != NumArgs; ++i) {
2063 MVT ValVT = Ins[i].VT;
2064 if (Ins[i].isOrigArg()) {
2065 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2066 CurArgIdx = Ins[i].getOrigArgIndex();
2068 // Get type of the original argument.
2069 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2070 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2071 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2072 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2074 else if (ActualMVT == MVT::i16)
2077 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2079 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2080 assert(!Res && "Call operand has unhandled type");
2083 assert(ArgLocs.size() == Ins.size());
2084 SmallVector<SDValue, 16> ArgValues;
2085 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2086 CCValAssign &VA = ArgLocs[i];
2088 if (Ins[i].Flags.isByVal()) {
2089 // Byval is used for HFAs in the PCS, but the system should work in a
2090 // non-compliant manner for larger structs.
2091 EVT PtrTy = getPointerTy();
2092 int Size = Ins[i].Flags.getByValSize();
2093 unsigned NumRegs = (Size + 7) / 8;
2095 // FIXME: This works on big-endian for composite byvals, which are the common
2096 // case. It should also work for fundamental types too.
2098 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2099 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2100 InVals.push_back(FrameIdxN);
2105 if (VA.isRegLoc()) {
2106 // Arguments stored in registers.
2107 EVT RegVT = VA.getLocVT();
2110 const TargetRegisterClass *RC;
2112 if (RegVT == MVT::i32)
2113 RC = &AArch64::GPR32RegClass;
2114 else if (RegVT == MVT::i64)
2115 RC = &AArch64::GPR64RegClass;
2116 else if (RegVT == MVT::f16)
2117 RC = &AArch64::FPR16RegClass;
2118 else if (RegVT == MVT::f32)
2119 RC = &AArch64::FPR32RegClass;
2120 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2121 RC = &AArch64::FPR64RegClass;
2122 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2123 RC = &AArch64::FPR128RegClass;
2125 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2127 // Transform the arguments in physical registers into virtual ones.
2128 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2129 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2131 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2132 // to 64 bits. Insert an assert[sz]ext to capture this, then
2133 // truncate to the right size.
2134 switch (VA.getLocInfo()) {
2136 llvm_unreachable("Unknown loc info!");
2137 case CCValAssign::Full:
2139 case CCValAssign::BCvt:
2140 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2142 case CCValAssign::AExt:
2143 case CCValAssign::SExt:
2144 case CCValAssign::ZExt:
2145 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2146 // nodes after our lowering.
2147 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2151 InVals.push_back(ArgValue);
2153 } else { // VA.isRegLoc()
2154 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2155 unsigned ArgOffset = VA.getLocMemOffset();
2156 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2158 uint32_t BEAlign = 0;
2159 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2160 !Ins[i].Flags.isInConsecutiveRegs())
2161 BEAlign = 8 - ArgSize;
2163 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2165 // Create load nodes to retrieve arguments from the stack.
2166 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2169 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2170 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2171 MVT MemVT = VA.getValVT();
2173 switch (VA.getLocInfo()) {
2176 case CCValAssign::BCvt:
2177 MemVT = VA.getLocVT();
2179 case CCValAssign::SExt:
2180 ExtType = ISD::SEXTLOAD;
2182 case CCValAssign::ZExt:
2183 ExtType = ISD::ZEXTLOAD;
2185 case CCValAssign::AExt:
2186 ExtType = ISD::EXTLOAD;
2190 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2191 MachinePointerInfo::getFixedStack(FI),
2192 MemVT, false, false, false, 0);
2194 InVals.push_back(ArgValue);
2200 if (!Subtarget->isTargetDarwin()) {
2201 // The AAPCS variadic function ABI is identical to the non-variadic
2202 // one. As a result there may be more arguments in registers and we should
2203 // save them for future reference.
2204 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2207 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2208 // This will point to the next argument passed via stack.
2209 unsigned StackOffset = CCInfo.getNextStackOffset();
2210 // We currently pass all varargs at 8-byte alignment.
2211 StackOffset = ((StackOffset + 7) & ~7);
2212 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2215 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2216 unsigned StackArgSize = CCInfo.getNextStackOffset();
2217 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2218 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2219 // This is a non-standard ABI so by fiat I say we're allowed to make full
2220 // use of the stack area to be popped, which must be aligned to 16 bytes in
2222 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2224 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2225 // a multiple of 16.
2226 FuncInfo->setArgumentStackToRestore(StackArgSize);
2228 // This realignment carries over to the available bytes below. Our own
2229 // callers will guarantee the space is free by giving an aligned value to
2232 // Even if we're not expected to free up the space, it's useful to know how
2233 // much is there while considering tail calls (because we can reuse it).
2234 FuncInfo->setBytesInStackArgArea(StackArgSize);
2239 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2240 SelectionDAG &DAG, SDLoc DL,
2241 SDValue &Chain) const {
2242 MachineFunction &MF = DAG.getMachineFunction();
2243 MachineFrameInfo *MFI = MF.getFrameInfo();
2244 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2246 SmallVector<SDValue, 8> MemOps;
2248 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2249 AArch64::X3, AArch64::X4, AArch64::X5,
2250 AArch64::X6, AArch64::X7 };
2251 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2252 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2254 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2256 if (GPRSaveSize != 0) {
2257 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2259 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2261 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2262 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2263 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2265 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2266 MachinePointerInfo::getStack(i * 8), false, false, 0);
2267 MemOps.push_back(Store);
2268 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2269 DAG.getConstant(8, getPointerTy()));
2272 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2273 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2275 if (Subtarget->hasFPARMv8()) {
2276 static const MCPhysReg FPRArgRegs[] = {
2277 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2278 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2279 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2280 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2282 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2284 if (FPRSaveSize != 0) {
2285 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2287 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2289 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2290 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2291 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2294 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2295 MachinePointerInfo::getStack(i * 16), false, false, 0);
2296 MemOps.push_back(Store);
2297 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2298 DAG.getConstant(16, getPointerTy()));
2301 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2302 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2305 if (!MemOps.empty()) {
2306 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2310 /// LowerCallResult - Lower the result values of a call into the
2311 /// appropriate copies out of appropriate physical registers.
2312 SDValue AArch64TargetLowering::LowerCallResult(
2313 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2314 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2315 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2316 SDValue ThisVal) const {
2317 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2318 ? RetCC_AArch64_WebKit_JS
2319 : RetCC_AArch64_AAPCS;
2320 // Assign locations to each value returned by this call.
2321 SmallVector<CCValAssign, 16> RVLocs;
2322 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2324 CCInfo.AnalyzeCallResult(Ins, RetCC);
2326 // Copy all of the result registers out of their specified physreg.
2327 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2328 CCValAssign VA = RVLocs[i];
2330 // Pass 'this' value directly from the argument to return value, to avoid
2331 // reg unit interference
2332 if (i == 0 && isThisReturn) {
2333 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2334 "unexpected return calling convention register assignment");
2335 InVals.push_back(ThisVal);
2340 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2341 Chain = Val.getValue(1);
2342 InFlag = Val.getValue(2);
2344 switch (VA.getLocInfo()) {
2346 llvm_unreachable("Unknown loc info!");
2347 case CCValAssign::Full:
2349 case CCValAssign::BCvt:
2350 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2354 InVals.push_back(Val);
2360 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2361 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2362 bool isCalleeStructRet, bool isCallerStructRet,
2363 const SmallVectorImpl<ISD::OutputArg> &Outs,
2364 const SmallVectorImpl<SDValue> &OutVals,
2365 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2366 // For CallingConv::C this function knows whether the ABI needs
2367 // changing. That's not true for other conventions so they will have to opt in
2369 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2372 const MachineFunction &MF = DAG.getMachineFunction();
2373 const Function *CallerF = MF.getFunction();
2374 CallingConv::ID CallerCC = CallerF->getCallingConv();
2375 bool CCMatch = CallerCC == CalleeCC;
2377 // Byval parameters hand the function a pointer directly into the stack area
2378 // we want to reuse during a tail call. Working around this *is* possible (see
2379 // X86) but less efficient and uglier in LowerCall.
2380 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2381 e = CallerF->arg_end();
2383 if (i->hasByValAttr())
2386 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2387 if (IsTailCallConvention(CalleeCC) && CCMatch)
2392 // Externally-defined functions with weak linkage should not be
2393 // tail-called on AArch64 when the OS does not support dynamic
2394 // pre-emption of symbols, as the AAELF spec requires normal calls
2395 // to undefined weak functions to be replaced with a NOP or jump to the
2396 // next instruction. The behaviour of branch instructions in this
2397 // situation (as used for tail calls) is implementation-defined, so we
2398 // cannot rely on the linker replacing the tail call with a return.
2399 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2400 const GlobalValue *GV = G->getGlobal();
2401 const Triple TT(getTargetMachine().getTargetTriple());
2402 if (GV->hasExternalWeakLinkage() &&
2403 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2407 // Now we search for cases where we can use a tail call without changing the
2408 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2411 // I want anyone implementing a new calling convention to think long and hard
2412 // about this assert.
2413 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2414 "Unexpected variadic calling convention");
2416 if (isVarArg && !Outs.empty()) {
2417 // At least two cases here: if caller is fastcc then we can't have any
2418 // memory arguments (we'd be expected to clean up the stack afterwards). If
2419 // caller is C then we could potentially use its argument area.
2421 // FIXME: for now we take the most conservative of these in both cases:
2422 // disallow all variadic memory operands.
2423 SmallVector<CCValAssign, 16> ArgLocs;
2424 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2427 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2428 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2429 if (!ArgLocs[i].isRegLoc())
2433 // If the calling conventions do not match, then we'd better make sure the
2434 // results are returned in the same way as what the caller expects.
2436 SmallVector<CCValAssign, 16> RVLocs1;
2437 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2439 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2441 SmallVector<CCValAssign, 16> RVLocs2;
2442 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2444 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2446 if (RVLocs1.size() != RVLocs2.size())
2448 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2449 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2451 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2453 if (RVLocs1[i].isRegLoc()) {
2454 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2457 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2463 // Nothing more to check if the callee is taking no arguments
2467 SmallVector<CCValAssign, 16> ArgLocs;
2468 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2471 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2473 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2475 // If the stack arguments for this call would fit into our own save area then
2476 // the call can be made tail.
2477 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2480 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2482 MachineFrameInfo *MFI,
2483 int ClobberedFI) const {
2484 SmallVector<SDValue, 8> ArgChains;
2485 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2486 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2488 // Include the original chain at the beginning of the list. When this is
2489 // used by target LowerCall hooks, this helps legalize find the
2490 // CALLSEQ_BEGIN node.
2491 ArgChains.push_back(Chain);
2493 // Add a chain value for each stack argument corresponding
2494 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2495 UE = DAG.getEntryNode().getNode()->use_end();
2497 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2498 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2499 if (FI->getIndex() < 0) {
2500 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2501 int64_t InLastByte = InFirstByte;
2502 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2504 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2505 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2506 ArgChains.push_back(SDValue(L, 1));
2509 // Build a tokenfactor for all the chains.
2510 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2513 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2514 bool TailCallOpt) const {
2515 return CallCC == CallingConv::Fast && TailCallOpt;
2518 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2519 return CallCC == CallingConv::Fast;
2522 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2523 /// and add input and output parameter nodes.
2525 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2526 SmallVectorImpl<SDValue> &InVals) const {
2527 SelectionDAG &DAG = CLI.DAG;
2529 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2530 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2531 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2532 SDValue Chain = CLI.Chain;
2533 SDValue Callee = CLI.Callee;
2534 bool &IsTailCall = CLI.IsTailCall;
2535 CallingConv::ID CallConv = CLI.CallConv;
2536 bool IsVarArg = CLI.IsVarArg;
2538 MachineFunction &MF = DAG.getMachineFunction();
2539 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2540 bool IsThisReturn = false;
2542 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2543 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2544 bool IsSibCall = false;
2547 // Check if it's really possible to do a tail call.
2548 IsTailCall = isEligibleForTailCallOptimization(
2549 Callee, CallConv, IsVarArg, IsStructRet,
2550 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2551 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2552 report_fatal_error("failed to perform tail call elimination on a call "
2553 "site marked musttail");
2555 // A sibling call is one where we're under the usual C ABI and not planning
2556 // to change that but can still do a tail call:
2557 if (!TailCallOpt && IsTailCall)
2564 // Analyze operands of the call, assigning locations to each operand.
2565 SmallVector<CCValAssign, 16> ArgLocs;
2566 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2570 // Handle fixed and variable vector arguments differently.
2571 // Variable vector arguments always go into memory.
2572 unsigned NumArgs = Outs.size();
2574 for (unsigned i = 0; i != NumArgs; ++i) {
2575 MVT ArgVT = Outs[i].VT;
2576 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2577 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2578 /*IsVarArg=*/ !Outs[i].IsFixed);
2579 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2580 assert(!Res && "Call operand has unhandled type");
2584 // At this point, Outs[].VT may already be promoted to i32. To correctly
2585 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2586 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2587 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2588 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2590 unsigned NumArgs = Outs.size();
2591 for (unsigned i = 0; i != NumArgs; ++i) {
2592 MVT ValVT = Outs[i].VT;
2593 // Get type of the original argument.
2594 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2595 /*AllowUnknown*/ true);
2596 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2597 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2598 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2599 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2601 else if (ActualMVT == MVT::i16)
2604 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2605 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2606 assert(!Res && "Call operand has unhandled type");
2611 // Get a count of how many bytes are to be pushed on the stack.
2612 unsigned NumBytes = CCInfo.getNextStackOffset();
2615 // Since we're not changing the ABI to make this a tail call, the memory
2616 // operands are already available in the caller's incoming argument space.
2620 // FPDiff is the byte offset of the call's argument area from the callee's.
2621 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2622 // by this amount for a tail call. In a sibling call it must be 0 because the
2623 // caller will deallocate the entire stack and the callee still expects its
2624 // arguments to begin at SP+0. Completely unused for non-tail calls.
2627 if (IsTailCall && !IsSibCall) {
2628 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2630 // Since callee will pop argument stack as a tail call, we must keep the
2631 // popped size 16-byte aligned.
2632 NumBytes = RoundUpToAlignment(NumBytes, 16);
2634 // FPDiff will be negative if this tail call requires more space than we
2635 // would automatically have in our incoming argument space. Positive if we
2636 // can actually shrink the stack.
2637 FPDiff = NumReusableBytes - NumBytes;
2639 // The stack pointer must be 16-byte aligned at all times it's used for a
2640 // memory operation, which in practice means at *all* times and in
2641 // particular across call boundaries. Therefore our own arguments started at
2642 // a 16-byte aligned SP and the delta applied for the tail call should
2643 // satisfy the same constraint.
2644 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2647 // Adjust the stack pointer for the new arguments...
2648 // These operations are automatically eliminated by the prolog/epilog pass
2651 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2653 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2655 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2656 SmallVector<SDValue, 8> MemOpChains;
2658 // Walk the register/memloc assignments, inserting copies/loads.
2659 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2660 ++i, ++realArgIdx) {
2661 CCValAssign &VA = ArgLocs[i];
2662 SDValue Arg = OutVals[realArgIdx];
2663 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2665 // Promote the value if needed.
2666 switch (VA.getLocInfo()) {
2668 llvm_unreachable("Unknown loc info!");
2669 case CCValAssign::Full:
2671 case CCValAssign::SExt:
2672 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2674 case CCValAssign::ZExt:
2675 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2677 case CCValAssign::AExt:
2678 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2679 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2680 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2681 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2683 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2685 case CCValAssign::BCvt:
2686 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2688 case CCValAssign::FPExt:
2689 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2693 if (VA.isRegLoc()) {
2694 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2695 assert(VA.getLocVT() == MVT::i64 &&
2696 "unexpected calling convention register assignment");
2697 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2698 "unexpected use of 'returned'");
2699 IsThisReturn = true;
2701 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2703 assert(VA.isMemLoc());
2706 MachinePointerInfo DstInfo;
2708 // FIXME: This works on big-endian for composite byvals, which are the
2709 // common case. It should also work for fundamental types too.
2710 uint32_t BEAlign = 0;
2711 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2712 : VA.getValVT().getSizeInBits();
2713 OpSize = (OpSize + 7) / 8;
2714 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2715 !Flags.isInConsecutiveRegs()) {
2717 BEAlign = 8 - OpSize;
2719 unsigned LocMemOffset = VA.getLocMemOffset();
2720 int32_t Offset = LocMemOffset + BEAlign;
2721 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2722 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2725 Offset = Offset + FPDiff;
2726 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2728 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2729 DstInfo = MachinePointerInfo::getFixedStack(FI);
2731 // Make sure any stack arguments overlapping with where we're storing
2732 // are loaded before this eventual operation. Otherwise they'll be
2734 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2736 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2738 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2739 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2742 if (Outs[i].Flags.isByVal()) {
2744 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2745 SDValue Cpy = DAG.getMemcpy(
2746 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2747 /*isVol = */ false, /*AlwaysInline = */ false,
2748 /*isTailCall = */ false,
2749 DstInfo, MachinePointerInfo());
2751 MemOpChains.push_back(Cpy);
2753 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2754 // promoted to a legal register type i32, we should truncate Arg back to
2756 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2757 VA.getValVT() == MVT::i16)
2758 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2761 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2762 MemOpChains.push_back(Store);
2767 if (!MemOpChains.empty())
2768 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2770 // Build a sequence of copy-to-reg nodes chained together with token chain
2771 // and flag operands which copy the outgoing args into the appropriate regs.
2773 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2774 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2775 RegsToPass[i].second, InFlag);
2776 InFlag = Chain.getValue(1);
2779 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2780 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2781 // node so that legalize doesn't hack it.
2782 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2783 Subtarget->isTargetMachO()) {
2784 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2785 const GlobalValue *GV = G->getGlobal();
2786 bool InternalLinkage = GV->hasInternalLinkage();
2787 if (InternalLinkage)
2788 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2790 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2792 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2794 } else if (ExternalSymbolSDNode *S =
2795 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2796 const char *Sym = S->getSymbol();
2798 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2799 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2801 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2802 const GlobalValue *GV = G->getGlobal();
2803 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2804 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2805 const char *Sym = S->getSymbol();
2806 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2809 // We don't usually want to end the call-sequence here because we would tidy
2810 // the frame up *after* the call, however in the ABI-changing tail-call case
2811 // we've carefully laid out the parameters so that when sp is reset they'll be
2812 // in the correct location.
2813 if (IsTailCall && !IsSibCall) {
2814 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2815 DAG.getIntPtrConstant(0, true), InFlag, DL);
2816 InFlag = Chain.getValue(1);
2819 std::vector<SDValue> Ops;
2820 Ops.push_back(Chain);
2821 Ops.push_back(Callee);
2824 // Each tail call may have to adjust the stack by a different amount, so
2825 // this information must travel along with the operation for eventual
2826 // consumption by emitEpilogue.
2827 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2830 // Add argument registers to the end of the list so that they are known live
2832 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2833 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2834 RegsToPass[i].second.getValueType()));
2836 // Add a register mask operand representing the call-preserved registers.
2837 const uint32_t *Mask;
2838 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2840 // For 'this' returns, use the X0-preserving mask if applicable
2841 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
2843 IsThisReturn = false;
2844 Mask = TRI->getCallPreservedMask(MF, CallConv);
2847 Mask = TRI->getCallPreservedMask(MF, CallConv);
2849 assert(Mask && "Missing call preserved mask for calling convention");
2850 Ops.push_back(DAG.getRegisterMask(Mask));
2852 if (InFlag.getNode())
2853 Ops.push_back(InFlag);
2855 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2857 // If we're doing a tall call, use a TC_RETURN here rather than an
2858 // actual call instruction.
2860 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2862 // Returns a chain and a flag for retval copy to use.
2863 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2864 InFlag = Chain.getValue(1);
2866 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2867 ? RoundUpToAlignment(NumBytes, 16)
2870 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2871 DAG.getIntPtrConstant(CalleePopBytes, true),
2874 InFlag = Chain.getValue(1);
2876 // Handle result values, copying them out of physregs into vregs that we
2878 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2879 InVals, IsThisReturn,
2880 IsThisReturn ? OutVals[0] : SDValue());
2883 bool AArch64TargetLowering::CanLowerReturn(
2884 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2885 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2886 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2887 ? RetCC_AArch64_WebKit_JS
2888 : RetCC_AArch64_AAPCS;
2889 SmallVector<CCValAssign, 16> RVLocs;
2890 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2891 return CCInfo.CheckReturn(Outs, RetCC);
2895 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2897 const SmallVectorImpl<ISD::OutputArg> &Outs,
2898 const SmallVectorImpl<SDValue> &OutVals,
2899 SDLoc DL, SelectionDAG &DAG) const {
2900 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2901 ? RetCC_AArch64_WebKit_JS
2902 : RetCC_AArch64_AAPCS;
2903 SmallVector<CCValAssign, 16> RVLocs;
2904 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2906 CCInfo.AnalyzeReturn(Outs, RetCC);
2908 // Copy the result values into the output registers.
2910 SmallVector<SDValue, 4> RetOps(1, Chain);
2911 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2912 ++i, ++realRVLocIdx) {
2913 CCValAssign &VA = RVLocs[i];
2914 assert(VA.isRegLoc() && "Can only return in registers!");
2915 SDValue Arg = OutVals[realRVLocIdx];
2917 switch (VA.getLocInfo()) {
2919 llvm_unreachable("Unknown loc info!");
2920 case CCValAssign::Full:
2921 if (Outs[i].ArgVT == MVT::i1) {
2922 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2923 // value. This is strictly redundant on Darwin (which uses "zeroext
2924 // i1"), but will be optimised out before ISel.
2925 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2926 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2929 case CCValAssign::BCvt:
2930 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2934 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2935 Flag = Chain.getValue(1);
2936 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2939 RetOps[0] = Chain; // Update chain.
2941 // Add the flag if we have it.
2943 RetOps.push_back(Flag);
2945 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2948 //===----------------------------------------------------------------------===//
2949 // Other Lowering Code
2950 //===----------------------------------------------------------------------===//
2952 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2953 SelectionDAG &DAG) const {
2954 EVT PtrVT = getPointerTy();
2956 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2957 const GlobalValue *GV = GN->getGlobal();
2958 unsigned char OpFlags =
2959 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2961 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2962 "unexpected offset in global node");
2964 // This also catched the large code model case for Darwin.
2965 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2966 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2967 // FIXME: Once remat is capable of dealing with instructions with register
2968 // operands, expand this into two nodes instead of using a wrapper node.
2969 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2972 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2973 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2974 "use of MO_CONSTPOOL only supported on small model");
2975 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2976 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2977 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2978 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2979 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2980 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
2981 MachinePointerInfo::getConstantPool(),
2982 /*isVolatile=*/ false,
2983 /*isNonTemporal=*/ true,
2984 /*isInvariant=*/ true, 8);
2985 if (GN->getOffset() != 0)
2986 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
2987 DAG.getConstant(GN->getOffset(), PtrVT));
2991 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2992 const unsigned char MO_NC = AArch64II::MO_NC;
2994 AArch64ISD::WrapperLarge, DL, PtrVT,
2995 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2996 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2997 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2998 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3000 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3001 // the only correct model on Darwin.
3002 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3003 OpFlags | AArch64II::MO_PAGE);
3004 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3005 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3007 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3008 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3012 /// \brief Convert a TLS address reference into the correct sequence of loads
3013 /// and calls to compute the variable's address (for Darwin, currently) and
3014 /// return an SDValue containing the final node.
3016 /// Darwin only has one TLS scheme which must be capable of dealing with the
3017 /// fully general situation, in the worst case. This means:
3018 /// + "extern __thread" declaration.
3019 /// + Defined in a possibly unknown dynamic library.
3021 /// The general system is that each __thread variable has a [3 x i64] descriptor
3022 /// which contains information used by the runtime to calculate the address. The
3023 /// only part of this the compiler needs to know about is the first xword, which
3024 /// contains a function pointer that must be called with the address of the
3025 /// entire descriptor in "x0".
3027 /// Since this descriptor may be in a different unit, in general even the
3028 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3030 /// adrp x0, _var@TLVPPAGE
3031 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3032 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3033 /// ; the function pointer
3034 /// blr x1 ; Uses descriptor address in x0
3035 /// ; Address of _var is now in x0.
3037 /// If the address of _var's descriptor *is* known to the linker, then it can
3038 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3039 /// a slight efficiency gain.
3041 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3042 SelectionDAG &DAG) const {
3043 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3046 MVT PtrVT = getPointerTy();
3047 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3050 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3051 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3053 // The first entry in the descriptor is a function pointer that we must call
3054 // to obtain the address of the variable.
3055 SDValue Chain = DAG.getEntryNode();
3056 SDValue FuncTLVGet =
3057 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3058 false, true, true, 8);
3059 Chain = FuncTLVGet.getValue(1);
3061 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3062 MFI->setAdjustsStack(true);
3064 // TLS calls preserve all registers except those that absolutely must be
3065 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3067 const uint32_t *Mask =
3068 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3070 // Finally, we can make the call. This is just a degenerate version of a
3071 // normal AArch64 call node: x0 takes the address of the descriptor, and
3072 // returns the address of the variable in this thread.
3073 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3075 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3076 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3077 DAG.getRegisterMask(Mask), Chain.getValue(1));
3078 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3081 /// When accessing thread-local variables under either the general-dynamic or
3082 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3083 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3084 /// is a function pointer to carry out the resolution.
3086 /// The sequence is:
3087 /// adrp x0, :tlsdesc:var
3088 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3089 /// add x0, x0, #:tlsdesc_lo12:var
3090 /// .tlsdesccall var
3092 /// (TPIDR_EL0 offset now in x0)
3094 /// The above sequence must be produced unscheduled, to enable the linker to
3095 /// optimize/relax this sequence.
3096 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3097 /// above sequence, and expanded really late in the compilation flow, to ensure
3098 /// the sequence is produced as per above.
3099 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3100 SelectionDAG &DAG) const {
3101 EVT PtrVT = getPointerTy();
3103 SDValue Chain = DAG.getEntryNode();
3104 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3106 SmallVector<SDValue, 2> Ops;
3107 Ops.push_back(Chain);
3108 Ops.push_back(SymAddr);
3110 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3111 SDValue Glue = Chain.getValue(1);
3113 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3117 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3118 SelectionDAG &DAG) const {
3119 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3120 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3121 "ELF TLS only supported in small memory model");
3122 // Different choices can be made for the maximum size of the TLS area for a
3123 // module. For the small address model, the default TLS size is 16MiB and the
3124 // maximum TLS size is 4GiB.
3125 // FIXME: add -mtls-size command line option and make it control the 16MiB
3126 // vs. 4GiB code sequence generation.
3127 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3129 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3130 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3131 if (Model == TLSModel::LocalDynamic)
3132 Model = TLSModel::GeneralDynamic;
3136 EVT PtrVT = getPointerTy();
3138 const GlobalValue *GV = GA->getGlobal();
3140 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3142 if (Model == TLSModel::LocalExec) {
3143 SDValue HiVar = DAG.getTargetGlobalAddress(
3144 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3145 SDValue LoVar = DAG.getTargetGlobalAddress(
3147 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3149 SDValue TPWithOff_lo =
3150 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3151 HiVar, DAG.getTargetConstant(0, MVT::i32)),
3154 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3155 LoVar, DAG.getTargetConstant(0, MVT::i32)),
3158 } else if (Model == TLSModel::InitialExec) {
3159 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3160 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3161 } else if (Model == TLSModel::LocalDynamic) {
3162 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3163 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3164 // the beginning of the module's TLS region, followed by a DTPREL offset
3167 // These accesses will need deduplicating if there's more than one.
3168 AArch64FunctionInfo *MFI =
3169 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3170 MFI->incNumLocalDynamicTLSAccesses();
3172 // The call needs a relocation too for linker relaxation. It doesn't make
3173 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3175 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3178 // Now we can calculate the offset from TPIDR_EL0 to this module's
3179 // thread-local area.
3180 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3182 // Now use :dtprel_whatever: operations to calculate this variable's offset
3183 // in its thread-storage area.
3184 SDValue HiVar = DAG.getTargetGlobalAddress(
3185 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3186 SDValue LoVar = DAG.getTargetGlobalAddress(
3187 GV, DL, MVT::i64, 0,
3188 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3190 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3191 DAG.getTargetConstant(0, MVT::i32)),
3193 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3194 DAG.getTargetConstant(0, MVT::i32)),
3196 } else if (Model == TLSModel::GeneralDynamic) {
3197 // The call needs a relocation too for linker relaxation. It doesn't make
3198 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3201 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3203 // Finally we can make a call to calculate the offset from tpidr_el0.
3204 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3206 llvm_unreachable("Unsupported ELF TLS access model");
3208 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3211 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3212 SelectionDAG &DAG) const {
3213 if (Subtarget->isTargetDarwin())
3214 return LowerDarwinGlobalTLSAddress(Op, DAG);
3215 else if (Subtarget->isTargetELF())
3216 return LowerELFGlobalTLSAddress(Op, DAG);
3218 llvm_unreachable("Unexpected platform trying to use TLS");
3220 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3221 SDValue Chain = Op.getOperand(0);
3222 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3223 SDValue LHS = Op.getOperand(2);
3224 SDValue RHS = Op.getOperand(3);
3225 SDValue Dest = Op.getOperand(4);
3228 // Handle f128 first, since lowering it will result in comparing the return
3229 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3230 // is expecting to deal with.
3231 if (LHS.getValueType() == MVT::f128) {
3232 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3234 // If softenSetCCOperands returned a scalar, we need to compare the result
3235 // against zero to select between true and false values.
3236 if (!RHS.getNode()) {
3237 RHS = DAG.getConstant(0, LHS.getValueType());
3242 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3244 unsigned Opc = LHS.getOpcode();
3245 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3246 cast<ConstantSDNode>(RHS)->isOne() &&
3247 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3248 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3249 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3250 "Unexpected condition code.");
3251 // Only lower legal XALUO ops.
3252 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3255 // The actual operation with overflow check.
3256 AArch64CC::CondCode OFCC;
3257 SDValue Value, Overflow;
3258 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3260 if (CC == ISD::SETNE)
3261 OFCC = getInvertedCondCode(OFCC);
3262 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3264 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3268 if (LHS.getValueType().isInteger()) {
3269 assert((LHS.getValueType() == RHS.getValueType()) &&
3270 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3272 // If the RHS of the comparison is zero, we can potentially fold this
3273 // to a specialized branch.
3274 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3275 if (RHSC && RHSC->getZExtValue() == 0) {
3276 if (CC == ISD::SETEQ) {
3277 // See if we can use a TBZ to fold in an AND as well.
3278 // TBZ has a smaller branch displacement than CBZ. If the offset is
3279 // out of bounds, a late MI-layer pass rewrites branches.
3280 // 403.gcc is an example that hits this case.
3281 if (LHS.getOpcode() == ISD::AND &&
3282 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3283 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3284 SDValue Test = LHS.getOperand(0);
3285 uint64_t Mask = LHS.getConstantOperandVal(1);
3286 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3287 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3290 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3291 } else if (CC == ISD::SETNE) {
3292 // See if we can use a TBZ to fold in an AND as well.
3293 // TBZ has a smaller branch displacement than CBZ. If the offset is
3294 // out of bounds, a late MI-layer pass rewrites branches.
3295 // 403.gcc is an example that hits this case.
3296 if (LHS.getOpcode() == ISD::AND &&
3297 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3298 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3299 SDValue Test = LHS.getOperand(0);
3300 uint64_t Mask = LHS.getConstantOperandVal(1);
3301 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3302 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3305 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3306 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3307 // Don't combine AND since emitComparison converts the AND to an ANDS
3308 // (a.k.a. TST) and the test in the test bit and branch instruction
3309 // becomes redundant. This would also increase register pressure.
3310 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3311 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3312 DAG.getConstant(Mask, MVT::i64), Dest);
3315 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3316 LHS.getOpcode() != ISD::AND) {
3317 // Don't combine AND since emitComparison converts the AND to an ANDS
3318 // (a.k.a. TST) and the test in the test bit and branch instruction
3319 // becomes redundant. This would also increase register pressure.
3320 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3321 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3322 DAG.getConstant(Mask, MVT::i64), Dest);
3326 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3327 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3331 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3333 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3334 // clean. Some of them require two branches to implement.
3335 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3336 AArch64CC::CondCode CC1, CC2;
3337 changeFPCCToAArch64CC(CC, CC1, CC2);
3338 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3340 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3341 if (CC2 != AArch64CC::AL) {
3342 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3343 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3350 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3351 SelectionDAG &DAG) const {
3352 EVT VT = Op.getValueType();
3355 SDValue In1 = Op.getOperand(0);
3356 SDValue In2 = Op.getOperand(1);
3357 EVT SrcVT = In2.getValueType();
3359 if (SrcVT == MVT::f32 && VT == MVT::f64)
3360 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3361 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3362 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3364 // FIXME: Src type is different, bail out for now. Can VT really be a
3372 SDValue VecVal1, VecVal2;
3373 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3376 EltMask = 0x80000000ULL;
3378 if (!VT.isVector()) {
3379 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3380 DAG.getUNDEF(VecVT), In1);
3381 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3382 DAG.getUNDEF(VecVT), In2);
3384 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3385 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3387 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3391 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3392 // immediate moves cannot materialize that in a single instruction for
3393 // 64-bit elements. Instead, materialize zero and then negate it.
3396 if (!VT.isVector()) {
3397 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3398 DAG.getUNDEF(VecVT), In1);
3399 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3400 DAG.getUNDEF(VecVT), In2);
3402 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3403 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3406 llvm_unreachable("Invalid type for copysign!");
3409 SDValue BuildVec = DAG.getConstant(EltMask, VecVT);
3411 // If we couldn't materialize the mask above, then the mask vector will be
3412 // the zero vector, and we need to negate it here.
3413 if (VT == MVT::f64 || VT == MVT::v2f64) {
3414 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3415 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3416 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3420 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3423 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3424 else if (VT == MVT::f64)
3425 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3427 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3430 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3431 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3432 Attribute::NoImplicitFloat))
3435 if (!Subtarget->hasNEON())
3438 // While there is no integer popcount instruction, it can
3439 // be more efficiently lowered to the following sequence that uses
3440 // AdvSIMD registers/instructions as long as the copies to/from
3441 // the AdvSIMD registers are cheap.
3442 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3443 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3444 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3445 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3446 SDValue Val = Op.getOperand(0);
3448 EVT VT = Op.getValueType();
3451 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3452 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3454 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3455 SDValue UaddLV = DAG.getNode(
3456 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3457 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3460 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3464 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3466 if (Op.getValueType().isVector())
3467 return LowerVSETCC(Op, DAG);
3469 SDValue LHS = Op.getOperand(0);
3470 SDValue RHS = Op.getOperand(1);
3471 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3474 // We chose ZeroOrOneBooleanContents, so use zero and one.
3475 EVT VT = Op.getValueType();
3476 SDValue TVal = DAG.getConstant(1, VT);
3477 SDValue FVal = DAG.getConstant(0, VT);
3479 // Handle f128 first, since one possible outcome is a normal integer
3480 // comparison which gets picked up by the next if statement.
3481 if (LHS.getValueType() == MVT::f128) {
3482 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3484 // If softenSetCCOperands returned a scalar, use it.
3485 if (!RHS.getNode()) {
3486 assert(LHS.getValueType() == Op.getValueType() &&
3487 "Unexpected setcc expansion!");
3492 if (LHS.getValueType().isInteger()) {
3495 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3497 // Note that we inverted the condition above, so we reverse the order of
3498 // the true and false operands here. This will allow the setcc to be
3499 // matched to a single CSINC instruction.
3500 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3503 // Now we know we're dealing with FP values.
3504 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3506 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3507 // and do the comparison.
3508 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3510 AArch64CC::CondCode CC1, CC2;
3511 changeFPCCToAArch64CC(CC, CC1, CC2);
3512 if (CC2 == AArch64CC::AL) {
3513 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3514 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3516 // Note that we inverted the condition above, so we reverse the order of
3517 // the true and false operands here. This will allow the setcc to be
3518 // matched to a single CSINC instruction.
3519 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3521 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3522 // totally clean. Some of them require two CSELs to implement. As is in
3523 // this case, we emit the first CSEL and then emit a second using the output
3524 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3526 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3527 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3529 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3531 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3532 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3536 /// A SELECT_CC operation is really some kind of max or min if both values being
3537 /// compared are, in some sense, equal to the results in either case. However,
3538 /// it is permissible to compare f32 values and produce directly extended f64
3541 /// Extending the comparison operands would also be allowed, but is less likely
3542 /// to happen in practice since their use is right here. Note that truncate
3543 /// operations would *not* be semantically equivalent.
3544 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3548 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3549 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3550 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3551 Result.getValueType() == MVT::f64) {
3553 APFloat CmpVal = CCmp->getValueAPF();
3554 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3555 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3558 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3561 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3562 SDValue RHS, SDValue TVal,
3563 SDValue FVal, SDLoc dl,
3564 SelectionDAG &DAG) const {
3565 // Handle f128 first, because it will result in a comparison of some RTLIB
3566 // call result against zero.
3567 if (LHS.getValueType() == MVT::f128) {
3568 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3570 // If softenSetCCOperands returned a scalar, we need to compare the result
3571 // against zero to select between true and false values.
3572 if (!RHS.getNode()) {
3573 RHS = DAG.getConstant(0, LHS.getValueType());
3578 // Handle integers first.
3579 if (LHS.getValueType().isInteger()) {
3580 assert((LHS.getValueType() == RHS.getValueType()) &&
3581 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3583 unsigned Opcode = AArch64ISD::CSEL;
3585 // If both the TVal and the FVal are constants, see if we can swap them in
3586 // order to for a CSINV or CSINC out of them.
3587 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3588 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3590 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3591 std::swap(TVal, FVal);
3592 std::swap(CTVal, CFVal);
3593 CC = ISD::getSetCCInverse(CC, true);
3594 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3595 std::swap(TVal, FVal);
3596 std::swap(CTVal, CFVal);
3597 CC = ISD::getSetCCInverse(CC, true);
3598 } else if (TVal.getOpcode() == ISD::XOR) {
3599 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3600 // with a CSINV rather than a CSEL.
3601 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3603 if (CVal && CVal->isAllOnesValue()) {
3604 std::swap(TVal, FVal);
3605 std::swap(CTVal, CFVal);
3606 CC = ISD::getSetCCInverse(CC, true);
3608 } else if (TVal.getOpcode() == ISD::SUB) {
3609 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3610 // that we can match with a CSNEG rather than a CSEL.
3611 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3613 if (CVal && CVal->isNullValue()) {
3614 std::swap(TVal, FVal);
3615 std::swap(CTVal, CFVal);
3616 CC = ISD::getSetCCInverse(CC, true);
3618 } else if (CTVal && CFVal) {
3619 const int64_t TrueVal = CTVal->getSExtValue();
3620 const int64_t FalseVal = CFVal->getSExtValue();
3623 // If both TVal and FVal are constants, see if FVal is the
3624 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3625 // instead of a CSEL in that case.
3626 if (TrueVal == ~FalseVal) {
3627 Opcode = AArch64ISD::CSINV;
3628 } else if (TrueVal == -FalseVal) {
3629 Opcode = AArch64ISD::CSNEG;
3630 } else if (TVal.getValueType() == MVT::i32) {
3631 // If our operands are only 32-bit wide, make sure we use 32-bit
3632 // arithmetic for the check whether we can use CSINC. This ensures that
3633 // the addition in the check will wrap around properly in case there is
3634 // an overflow (which would not be the case if we do the check with
3635 // 64-bit arithmetic).
3636 const uint32_t TrueVal32 = CTVal->getZExtValue();
3637 const uint32_t FalseVal32 = CFVal->getZExtValue();
3639 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3640 Opcode = AArch64ISD::CSINC;
3642 if (TrueVal32 > FalseVal32) {
3646 // 64-bit check whether we can use CSINC.
3647 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3648 Opcode = AArch64ISD::CSINC;
3650 if (TrueVal > FalseVal) {
3655 // Swap TVal and FVal if necessary.
3657 std::swap(TVal, FVal);
3658 std::swap(CTVal, CFVal);
3659 CC = ISD::getSetCCInverse(CC, true);
3662 if (Opcode != AArch64ISD::CSEL) {
3663 // Drop FVal since we can get its value by simply inverting/negating
3670 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3672 EVT VT = TVal.getValueType();
3673 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3676 // Now we know we're dealing with FP values.
3677 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3678 assert(LHS.getValueType() == RHS.getValueType());
3679 EVT VT = TVal.getValueType();
3681 // Try to match this select into a max/min operation, which have dedicated
3682 // opcode in the instruction set.
3683 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3685 if (getTargetMachine().Options.NoNaNsFPMath) {
3686 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3687 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3688 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3689 CC = ISD::getSetCCSwappedOperands(CC);
3690 std::swap(MinMaxLHS, MinMaxRHS);
3693 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3694 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3704 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3712 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3718 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3719 // and do the comparison.
3720 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3722 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3723 // clean. Some of them require two CSELs to implement.
3724 AArch64CC::CondCode CC1, CC2;
3725 changeFPCCToAArch64CC(CC, CC1, CC2);
3726 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3727 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3729 // If we need a second CSEL, emit it, using the output of the first as the
3730 // RHS. We're effectively OR'ing the two CC's together.
3731 if (CC2 != AArch64CC::AL) {
3732 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3733 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3736 // Otherwise, return the output of the first CSEL.
3740 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3741 SelectionDAG &DAG) const {
3742 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3743 SDValue LHS = Op.getOperand(0);
3744 SDValue RHS = Op.getOperand(1);
3745 SDValue TVal = Op.getOperand(2);
3746 SDValue FVal = Op.getOperand(3);
3748 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3751 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3752 SelectionDAG &DAG) const {
3753 SDValue CCVal = Op->getOperand(0);
3754 SDValue TVal = Op->getOperand(1);
3755 SDValue FVal = Op->getOperand(2);
3758 unsigned Opc = CCVal.getOpcode();
3759 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3761 if (CCVal.getResNo() == 1 &&
3762 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3763 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3764 // Only lower legal XALUO ops.
3765 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
3768 AArch64CC::CondCode OFCC;
3769 SDValue Value, Overflow;
3770 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
3771 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3773 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3777 // Lower it the same way as we would lower a SELECT_CC node.
3780 if (CCVal.getOpcode() == ISD::SETCC) {
3781 LHS = CCVal.getOperand(0);
3782 RHS = CCVal.getOperand(1);
3783 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
3786 RHS = DAG.getConstant(0, CCVal.getValueType());
3789 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3792 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3793 SelectionDAG &DAG) const {
3794 // Jump table entries as PC relative offsets. No additional tweaking
3795 // is necessary here. Just get the address of the jump table.
3796 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3797 EVT PtrVT = getPointerTy();
3800 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3801 !Subtarget->isTargetMachO()) {
3802 const unsigned char MO_NC = AArch64II::MO_NC;
3804 AArch64ISD::WrapperLarge, DL, PtrVT,
3805 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3806 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3807 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3808 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3809 AArch64II::MO_G0 | MO_NC));
3813 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3814 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3815 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3816 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3817 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3820 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3821 SelectionDAG &DAG) const {
3822 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3823 EVT PtrVT = getPointerTy();
3826 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3827 // Use the GOT for the large code model on iOS.
3828 if (Subtarget->isTargetMachO()) {
3829 SDValue GotAddr = DAG.getTargetConstantPool(
3830 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3832 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3835 const unsigned char MO_NC = AArch64II::MO_NC;
3837 AArch64ISD::WrapperLarge, DL, PtrVT,
3838 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3839 CP->getOffset(), AArch64II::MO_G3),
3840 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3841 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3842 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3843 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3844 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3845 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3847 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3848 // ELF, the only valid one on Darwin.
3850 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3851 CP->getOffset(), AArch64II::MO_PAGE);
3852 SDValue Lo = DAG.getTargetConstantPool(
3853 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3854 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3856 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3857 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3861 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3862 SelectionDAG &DAG) const {
3863 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3864 EVT PtrVT = getPointerTy();
3866 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3867 !Subtarget->isTargetMachO()) {
3868 const unsigned char MO_NC = AArch64II::MO_NC;
3870 AArch64ISD::WrapperLarge, DL, PtrVT,
3871 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3872 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3873 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3874 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3876 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3877 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3879 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3880 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3884 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3885 SelectionDAG &DAG) const {
3886 AArch64FunctionInfo *FuncInfo =
3887 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3891 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3892 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3893 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3894 MachinePointerInfo(SV), false, false, 0);
3897 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3898 SelectionDAG &DAG) const {
3899 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3900 // Standard, section B.3.
3901 MachineFunction &MF = DAG.getMachineFunction();
3902 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3905 SDValue Chain = Op.getOperand(0);
3906 SDValue VAList = Op.getOperand(1);
3907 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3908 SmallVector<SDValue, 4> MemOps;
3910 // void *__stack at offset 0
3912 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3913 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3914 MachinePointerInfo(SV), false, false, 8));
3916 // void *__gr_top at offset 8
3917 int GPRSize = FuncInfo->getVarArgsGPRSize();
3919 SDValue GRTop, GRTopAddr;
3921 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3922 DAG.getConstant(8, getPointerTy()));
3924 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3925 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3926 DAG.getConstant(GPRSize, getPointerTy()));
3928 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3929 MachinePointerInfo(SV, 8), false, false, 8));
3932 // void *__vr_top at offset 16
3933 int FPRSize = FuncInfo->getVarArgsFPRSize();
3935 SDValue VRTop, VRTopAddr;
3936 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3937 DAG.getConstant(16, getPointerTy()));
3939 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3940 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3941 DAG.getConstant(FPRSize, getPointerTy()));
3943 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3944 MachinePointerInfo(SV, 16), false, false, 8));
3947 // int __gr_offs at offset 24
3948 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3949 DAG.getConstant(24, getPointerTy()));
3950 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3951 GROffsAddr, MachinePointerInfo(SV, 24), false,
3954 // int __vr_offs at offset 28
3955 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3956 DAG.getConstant(28, getPointerTy()));
3957 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3958 VROffsAddr, MachinePointerInfo(SV, 28), false,
3961 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3964 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3965 SelectionDAG &DAG) const {
3966 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3967 : LowerAAPCS_VASTART(Op, DAG);
3970 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3971 SelectionDAG &DAG) const {
3972 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3974 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3975 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3976 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3978 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3979 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3980 8, false, false, false, MachinePointerInfo(DestSV),
3981 MachinePointerInfo(SrcSV));
3984 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3985 assert(Subtarget->isTargetDarwin() &&
3986 "automatic va_arg instruction only works on Darwin");
3988 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3989 EVT VT = Op.getValueType();
3991 SDValue Chain = Op.getOperand(0);
3992 SDValue Addr = Op.getOperand(1);
3993 unsigned Align = Op.getConstantOperandVal(3);
3995 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3996 MachinePointerInfo(V), false, false, false, 0);
3997 Chain = VAList.getValue(1);
4000 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
4001 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4002 DAG.getConstant(Align - 1, getPointerTy()));
4003 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
4004 DAG.getConstant(-(int64_t)Align, getPointerTy()));
4007 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4008 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
4010 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4011 // up to 64 bits. At the very least, we have to increase the striding of the
4012 // vaargs list to match this, and for FP values we need to introduce
4013 // FP_ROUND nodes as well.
4014 if (VT.isInteger() && !VT.isVector())
4016 bool NeedFPTrunc = false;
4017 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4022 // Increment the pointer, VAList, to the next vaarg
4023 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4024 DAG.getConstant(ArgSize, getPointerTy()));
4025 // Store the incremented VAList to the legalized pointer
4026 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4029 // Load the actual argument out of the pointer VAList
4031 // Load the value as an f64.
4032 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4033 MachinePointerInfo(), false, false, false, 0);
4034 // Round the value down to an f32.
4035 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4036 DAG.getIntPtrConstant(1));
4037 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4038 // Merge the rounded value with the chain output of the load.
4039 return DAG.getMergeValues(Ops, DL);
4042 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4046 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4047 SelectionDAG &DAG) const {
4048 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4049 MFI->setFrameAddressIsTaken(true);
4051 EVT VT = Op.getValueType();
4053 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4055 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4057 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4058 MachinePointerInfo(), false, false, false, 0);
4062 // FIXME? Maybe this could be a TableGen attribute on some registers and
4063 // this table could be generated automatically from RegInfo.
4064 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4066 unsigned Reg = StringSwitch<unsigned>(RegName)
4067 .Case("sp", AArch64::SP)
4071 report_fatal_error("Invalid register name global variable");
4074 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4075 SelectionDAG &DAG) const {
4076 MachineFunction &MF = DAG.getMachineFunction();
4077 MachineFrameInfo *MFI = MF.getFrameInfo();
4078 MFI->setReturnAddressIsTaken(true);
4080 EVT VT = Op.getValueType();
4082 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4084 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4085 SDValue Offset = DAG.getConstant(8, getPointerTy());
4086 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4087 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4088 MachinePointerInfo(), false, false, false, 0);
4091 // Return LR, which contains the return address. Mark it an implicit live-in.
4092 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4093 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4096 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4097 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4098 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4099 SelectionDAG &DAG) const {
4100 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4101 EVT VT = Op.getValueType();
4102 unsigned VTBits = VT.getSizeInBits();
4104 SDValue ShOpLo = Op.getOperand(0);
4105 SDValue ShOpHi = Op.getOperand(1);
4106 SDValue ShAmt = Op.getOperand(2);
4108 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4110 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4112 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4113 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4114 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4115 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4116 DAG.getConstant(VTBits, MVT::i64));
4117 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4119 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4120 ISD::SETGE, dl, DAG);
4121 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4123 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4124 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4126 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4128 // AArch64 shifts larger than the register width are wrapped rather than
4129 // clamped, so we can't just emit "hi >> x".
4130 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4131 SDValue TrueValHi = Opc == ISD::SRA
4132 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4133 DAG.getConstant(VTBits - 1, MVT::i64))
4134 : DAG.getConstant(0, VT);
4136 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4138 SDValue Ops[2] = { Lo, Hi };
4139 return DAG.getMergeValues(Ops, dl);
4142 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4143 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4144 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4145 SelectionDAG &DAG) const {
4146 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4147 EVT VT = Op.getValueType();
4148 unsigned VTBits = VT.getSizeInBits();
4150 SDValue ShOpLo = Op.getOperand(0);
4151 SDValue ShOpHi = Op.getOperand(1);
4152 SDValue ShAmt = Op.getOperand(2);
4155 assert(Op.getOpcode() == ISD::SHL_PARTS);
4156 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4157 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4158 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4159 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4160 DAG.getConstant(VTBits, MVT::i64));
4161 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4162 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4164 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4166 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4167 ISD::SETGE, dl, DAG);
4168 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4170 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4172 // AArch64 shifts of larger than register sizes are wrapped rather than
4173 // clamped, so we can't just emit "lo << a" if a is too big.
4174 SDValue TrueValLo = DAG.getConstant(0, VT);
4175 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4177 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4179 SDValue Ops[2] = { Lo, Hi };
4180 return DAG.getMergeValues(Ops, dl);
4183 bool AArch64TargetLowering::isOffsetFoldingLegal(
4184 const GlobalAddressSDNode *GA) const {
4185 // The AArch64 target doesn't support folding offsets into global addresses.
4189 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4190 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4191 // FIXME: We should be able to handle f128 as well with a clever lowering.
4192 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4196 return AArch64_AM::getFP64Imm(Imm) != -1;
4197 else if (VT == MVT::f32)
4198 return AArch64_AM::getFP32Imm(Imm) != -1;
4202 //===----------------------------------------------------------------------===//
4203 // AArch64 Optimization Hooks
4204 //===----------------------------------------------------------------------===//
4206 //===----------------------------------------------------------------------===//
4207 // AArch64 Inline Assembly Support
4208 //===----------------------------------------------------------------------===//
4210 // Table of Constraints
4211 // TODO: This is the current set of constraints supported by ARM for the
4212 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4214 // r - A general register
4215 // w - An FP/SIMD register of some size in the range v0-v31
4216 // x - An FP/SIMD register of some size in the range v0-v15
4217 // I - Constant that can be used with an ADD instruction
4218 // J - Constant that can be used with a SUB instruction
4219 // K - Constant that can be used with a 32-bit logical instruction
4220 // L - Constant that can be used with a 64-bit logical instruction
4221 // M - Constant that can be used as a 32-bit MOV immediate
4222 // N - Constant that can be used as a 64-bit MOV immediate
4223 // Q - A memory reference with base register and no offset
4224 // S - A symbolic address
4225 // Y - Floating point constant zero
4226 // Z - Integer constant zero
4228 // Note that general register operands will be output using their 64-bit x
4229 // register name, whatever the size of the variable, unless the asm operand
4230 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4231 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4234 /// getConstraintType - Given a constraint letter, return the type of
4235 /// constraint it is for this target.
4236 AArch64TargetLowering::ConstraintType
4237 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4238 if (Constraint.size() == 1) {
4239 switch (Constraint[0]) {
4246 return C_RegisterClass;
4247 // An address with a single base register. Due to the way we
4248 // currently handle addresses it is the same as 'r'.
4253 return TargetLowering::getConstraintType(Constraint);
4256 /// Examine constraint type and operand type and determine a weight value.
4257 /// This object must already have been set up with the operand type
4258 /// and the current alternative constraint selected.
4259 TargetLowering::ConstraintWeight
4260 AArch64TargetLowering::getSingleConstraintMatchWeight(
4261 AsmOperandInfo &info, const char *constraint) const {
4262 ConstraintWeight weight = CW_Invalid;
4263 Value *CallOperandVal = info.CallOperandVal;
4264 // If we don't have a value, we can't do a match,
4265 // but allow it at the lowest weight.
4266 if (!CallOperandVal)
4268 Type *type = CallOperandVal->getType();
4269 // Look at the constraint type.
4270 switch (*constraint) {
4272 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4276 if (type->isFloatingPointTy() || type->isVectorTy())
4277 weight = CW_Register;
4280 weight = CW_Constant;
4286 std::pair<unsigned, const TargetRegisterClass *>
4287 AArch64TargetLowering::getRegForInlineAsmConstraint(
4288 const TargetRegisterInfo *TRI, const std::string &Constraint,
4290 if (Constraint.size() == 1) {
4291 switch (Constraint[0]) {
4293 if (VT.getSizeInBits() == 64)
4294 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4295 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4298 return std::make_pair(0U, &AArch64::FPR32RegClass);
4299 if (VT.getSizeInBits() == 64)
4300 return std::make_pair(0U, &AArch64::FPR64RegClass);
4301 if (VT.getSizeInBits() == 128)
4302 return std::make_pair(0U, &AArch64::FPR128RegClass);
4304 // The instructions that this constraint is designed for can
4305 // only take 128-bit registers so just use that regclass.
4307 if (VT.getSizeInBits() == 128)
4308 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4312 if (StringRef("{cc}").equals_lower(Constraint))
4313 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4315 // Use the default implementation in TargetLowering to convert the register
4316 // constraint into a member of a register class.
4317 std::pair<unsigned, const TargetRegisterClass *> Res;
4318 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4320 // Not found as a standard register?
4322 unsigned Size = Constraint.size();
4323 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4324 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4325 const std::string Reg =
4326 std::string(&Constraint[2], &Constraint[Size - 1]);
4327 int RegNo = atoi(Reg.c_str());
4328 if (RegNo >= 0 && RegNo <= 31) {
4329 // v0 - v31 are aliases of q0 - q31.
4330 // By default we'll emit v0-v31 for this unless there's a modifier where
4331 // we'll emit the correct register as well.
4332 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4333 Res.second = &AArch64::FPR128RegClass;
4341 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4342 /// vector. If it is invalid, don't add anything to Ops.
4343 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4344 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4345 SelectionDAG &DAG) const {
4348 // Currently only support length 1 constraints.
4349 if (Constraint.length() != 1)
4352 char ConstraintLetter = Constraint[0];
4353 switch (ConstraintLetter) {
4357 // This set of constraints deal with valid constants for various instructions.
4358 // Validate and return a target constant for them if we can.
4360 // 'z' maps to xzr or wzr so it needs an input of 0.
4361 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4362 if (!C || C->getZExtValue() != 0)
4365 if (Op.getValueType() == MVT::i64)
4366 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4368 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4378 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4382 // Grab the value and do some validation.
4383 uint64_t CVal = C->getZExtValue();
4384 switch (ConstraintLetter) {
4385 // The I constraint applies only to simple ADD or SUB immediate operands:
4386 // i.e. 0 to 4095 with optional shift by 12
4387 // The J constraint applies only to ADD or SUB immediates that would be
4388 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4389 // instruction [or vice versa], in other words -1 to -4095 with optional
4390 // left shift by 12.
4392 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4396 uint64_t NVal = -C->getSExtValue();
4397 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4398 CVal = C->getSExtValue();
4403 // The K and L constraints apply *only* to logical immediates, including
4404 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4405 // been removed and MOV should be used). So these constraints have to
4406 // distinguish between bit patterns that are valid 32-bit or 64-bit
4407 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4408 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4411 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4415 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4418 // The M and N constraints are a superset of K and L respectively, for use
4419 // with the MOV (immediate) alias. As well as the logical immediates they
4420 // also match 32 or 64-bit immediates that can be loaded either using a
4421 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4422 // (M) or 64-bit 0x1234000000000000 (N) etc.
4423 // As a note some of this code is liberally stolen from the asm parser.
4425 if (!isUInt<32>(CVal))
4427 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4429 if ((CVal & 0xFFFF) == CVal)
4431 if ((CVal & 0xFFFF0000ULL) == CVal)
4433 uint64_t NCVal = ~(uint32_t)CVal;
4434 if ((NCVal & 0xFFFFULL) == NCVal)
4436 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4441 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4443 if ((CVal & 0xFFFFULL) == CVal)
4445 if ((CVal & 0xFFFF0000ULL) == CVal)
4447 if ((CVal & 0xFFFF00000000ULL) == CVal)
4449 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4451 uint64_t NCVal = ~CVal;
4452 if ((NCVal & 0xFFFFULL) == NCVal)
4454 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4456 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4458 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4466 // All assembler immediates are 64-bit integers.
4467 Result = DAG.getTargetConstant(CVal, MVT::i64);
4471 if (Result.getNode()) {
4472 Ops.push_back(Result);
4476 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4479 //===----------------------------------------------------------------------===//
4480 // AArch64 Advanced SIMD Support
4481 //===----------------------------------------------------------------------===//
4483 /// WidenVector - Given a value in the V64 register class, produce the
4484 /// equivalent value in the V128 register class.
4485 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4486 EVT VT = V64Reg.getValueType();
4487 unsigned NarrowSize = VT.getVectorNumElements();
4488 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4489 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4492 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4493 V64Reg, DAG.getConstant(0, MVT::i32));
4496 /// getExtFactor - Determine the adjustment factor for the position when
4497 /// generating an "extract from vector registers" instruction.
4498 static unsigned getExtFactor(SDValue &V) {
4499 EVT EltType = V.getValueType().getVectorElementType();
4500 return EltType.getSizeInBits() / 8;
4503 /// NarrowVector - Given a value in the V128 register class, produce the
4504 /// equivalent value in the V64 register class.
4505 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4506 EVT VT = V128Reg.getValueType();
4507 unsigned WideSize = VT.getVectorNumElements();
4508 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4509 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4512 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4515 // Gather data to see if the operation can be modelled as a
4516 // shuffle in combination with VEXTs.
4517 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4518 SelectionDAG &DAG) const {
4519 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4521 EVT VT = Op.getValueType();
4522 unsigned NumElts = VT.getVectorNumElements();
4524 struct ShuffleSourceInfo {
4529 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4530 // be compatible with the shuffle we intend to construct. As a result
4531 // ShuffleVec will be some sliding window into the original Vec.
4534 // Code should guarantee that element i in Vec starts at element "WindowBase
4535 // + i * WindowScale in ShuffleVec".
4539 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4540 ShuffleSourceInfo(SDValue Vec)
4541 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4545 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4547 SmallVector<ShuffleSourceInfo, 2> Sources;
4548 for (unsigned i = 0; i < NumElts; ++i) {
4549 SDValue V = Op.getOperand(i);
4550 if (V.getOpcode() == ISD::UNDEF)
4552 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4553 // A shuffle can only come from building a vector from various
4554 // elements of other vectors.
4558 // Add this element source to the list if it's not already there.
4559 SDValue SourceVec = V.getOperand(0);
4560 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4561 if (Source == Sources.end())
4562 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4564 // Update the minimum and maximum lane number seen.
4565 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4566 Source->MinElt = std::min(Source->MinElt, EltNo);
4567 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4570 // Currently only do something sane when at most two source vectors
4572 if (Sources.size() > 2)
4575 // Find out the smallest element size among result and two sources, and use
4576 // it as element size to build the shuffle_vector.
4577 EVT SmallestEltTy = VT.getVectorElementType();
4578 for (auto &Source : Sources) {
4579 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4580 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4581 SmallestEltTy = SrcEltTy;
4584 unsigned ResMultiplier =
4585 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4586 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4587 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4589 // If the source vector is too wide or too narrow, we may nevertheless be able
4590 // to construct a compatible shuffle either by concatenating it with UNDEF or
4591 // extracting a suitable range of elements.
4592 for (auto &Src : Sources) {
4593 EVT SrcVT = Src.ShuffleVec.getValueType();
4595 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4598 // This stage of the search produces a source with the same element type as
4599 // the original, but with a total width matching the BUILD_VECTOR output.
4600 EVT EltVT = SrcVT.getVectorElementType();
4601 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4602 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4604 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4605 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4606 // We can pad out the smaller vector for free, so if it's part of a
4609 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4610 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4614 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4616 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4617 // Span too large for a VEXT to cope
4621 if (Src.MinElt >= NumSrcElts) {
4622 // The extraction can just take the second half
4624 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4625 DAG.getConstant(NumSrcElts, MVT::i64));
4626 Src.WindowBase = -NumSrcElts;
4627 } else if (Src.MaxElt < NumSrcElts) {
4628 // The extraction can just take the first half
4630 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4631 DAG.getConstant(0, MVT::i64));
4633 // An actual VEXT is needed
4635 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4636 DAG.getConstant(0, MVT::i64));
4638 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4639 DAG.getConstant(NumSrcElts, MVT::i64));
4640 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4642 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4643 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4644 Src.WindowBase = -Src.MinElt;
4648 // Another possible incompatibility occurs from the vector element types. We
4649 // can fix this by bitcasting the source vectors to the same type we intend
4651 for (auto &Src : Sources) {
4652 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4653 if (SrcEltTy == SmallestEltTy)
4655 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4656 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4657 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4658 Src.WindowBase *= Src.WindowScale;
4661 // Final sanity check before we try to actually produce a shuffle.
4663 for (auto Src : Sources)
4664 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4667 // The stars all align, our next step is to produce the mask for the shuffle.
4668 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4669 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4670 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4671 SDValue Entry = Op.getOperand(i);
4672 if (Entry.getOpcode() == ISD::UNDEF)
4675 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4676 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4678 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4679 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4681 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4682 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4683 VT.getVectorElementType().getSizeInBits());
4684 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4686 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4687 // starting at the appropriate offset.
4688 int *LaneMask = &Mask[i * ResMultiplier];
4690 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4691 ExtractBase += NumElts * (Src - Sources.begin());
4692 for (int j = 0; j < LanesDefined; ++j)
4693 LaneMask[j] = ExtractBase + j;
4696 // Final check before we try to produce nonsense...
4697 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4700 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4701 for (unsigned i = 0; i < Sources.size(); ++i)
4702 ShuffleOps[i] = Sources[i].ShuffleVec;
4704 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4705 ShuffleOps[1], &Mask[0]);
4706 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4709 // check if an EXT instruction can handle the shuffle mask when the
4710 // vector sources of the shuffle are the same.
4711 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4712 unsigned NumElts = VT.getVectorNumElements();
4714 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4720 // If this is a VEXT shuffle, the immediate value is the index of the first
4721 // element. The other shuffle indices must be the successive elements after
4723 unsigned ExpectedElt = Imm;
4724 for (unsigned i = 1; i < NumElts; ++i) {
4725 // Increment the expected index. If it wraps around, just follow it
4726 // back to index zero and keep going.
4728 if (ExpectedElt == NumElts)
4732 continue; // ignore UNDEF indices
4733 if (ExpectedElt != static_cast<unsigned>(M[i]))
4740 // check if an EXT instruction can handle the shuffle mask when the
4741 // vector sources of the shuffle are different.
4742 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4744 // Look for the first non-undef element.
4745 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4746 [](int Elt) {return Elt >= 0;});
4748 // Benefit form APInt to handle overflow when calculating expected element.
4749 unsigned NumElts = VT.getVectorNumElements();
4750 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4751 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4752 // The following shuffle indices must be the successive elements after the
4753 // first real element.
4754 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4755 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4756 if (FirstWrongElt != M.end())
4759 // The index of an EXT is the first element if it is not UNDEF.
4760 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4761 // value of the first element. E.g.
4762 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4763 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4764 // ExpectedElt is the last mask index plus 1.
4765 Imm = ExpectedElt.getZExtValue();
4767 // There are two difference cases requiring to reverse input vectors.
4768 // For example, for vector <4 x i32> we have the following cases,
4769 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4770 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4771 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4772 // to reverse two input vectors.
4781 /// isREVMask - Check if a vector shuffle corresponds to a REV
4782 /// instruction with the specified blocksize. (The order of the elements
4783 /// within each block of the vector is reversed.)
4784 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4785 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4786 "Only possible block sizes for REV are: 16, 32, 64");
4788 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4792 unsigned NumElts = VT.getVectorNumElements();
4793 unsigned BlockElts = M[0] + 1;
4794 // If the first shuffle index is UNDEF, be optimistic.
4796 BlockElts = BlockSize / EltSz;
4798 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4801 for (unsigned i = 0; i < NumElts; ++i) {
4803 continue; // ignore UNDEF indices
4804 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4811 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4812 unsigned NumElts = VT.getVectorNumElements();
4813 WhichResult = (M[0] == 0 ? 0 : 1);
4814 unsigned Idx = WhichResult * NumElts / 2;
4815 for (unsigned i = 0; i != NumElts; i += 2) {
4816 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4817 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4825 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4826 unsigned NumElts = VT.getVectorNumElements();
4827 WhichResult = (M[0] == 0 ? 0 : 1);
4828 for (unsigned i = 0; i != NumElts; ++i) {
4830 continue; // ignore UNDEF indices
4831 if ((unsigned)M[i] != 2 * i + WhichResult)
4838 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4839 unsigned NumElts = VT.getVectorNumElements();
4840 WhichResult = (M[0] == 0 ? 0 : 1);
4841 for (unsigned i = 0; i < NumElts; i += 2) {
4842 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4843 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4849 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4850 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4851 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4852 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4853 unsigned NumElts = VT.getVectorNumElements();
4854 WhichResult = (M[0] == 0 ? 0 : 1);
4855 unsigned Idx = WhichResult * NumElts / 2;
4856 for (unsigned i = 0; i != NumElts; i += 2) {
4857 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4858 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4866 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4867 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4868 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4869 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4870 unsigned Half = VT.getVectorNumElements() / 2;
4871 WhichResult = (M[0] == 0 ? 0 : 1);
4872 for (unsigned j = 0; j != 2; ++j) {
4873 unsigned Idx = WhichResult;
4874 for (unsigned i = 0; i != Half; ++i) {
4875 int MIdx = M[i + j * Half];
4876 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4885 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4886 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4887 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4888 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4889 unsigned NumElts = VT.getVectorNumElements();
4890 WhichResult = (M[0] == 0 ? 0 : 1);
4891 for (unsigned i = 0; i < NumElts; i += 2) {
4892 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4893 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4899 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4900 bool &DstIsLeft, int &Anomaly) {
4901 if (M.size() != static_cast<size_t>(NumInputElements))
4904 int NumLHSMatch = 0, NumRHSMatch = 0;
4905 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4907 for (int i = 0; i < NumInputElements; ++i) {
4917 LastLHSMismatch = i;
4919 if (M[i] == i + NumInputElements)
4922 LastRHSMismatch = i;
4925 if (NumLHSMatch == NumInputElements - 1) {
4927 Anomaly = LastLHSMismatch;
4929 } else if (NumRHSMatch == NumInputElements - 1) {
4931 Anomaly = LastRHSMismatch;
4938 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4939 if (VT.getSizeInBits() != 128)
4942 unsigned NumElts = VT.getVectorNumElements();
4944 for (int I = 0, E = NumElts / 2; I != E; I++) {
4949 int Offset = NumElts / 2;
4950 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4951 if (Mask[I] != I + SplitLHS * Offset)
4958 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4960 EVT VT = Op.getValueType();
4961 SDValue V0 = Op.getOperand(0);
4962 SDValue V1 = Op.getOperand(1);
4963 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4965 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4966 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4969 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4971 if (!isConcatMask(Mask, VT, SplitV0))
4974 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4975 VT.getVectorNumElements() / 2);
4977 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4978 DAG.getConstant(0, MVT::i64));
4980 if (V1.getValueType().getSizeInBits() == 128) {
4981 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4982 DAG.getConstant(0, MVT::i64));
4984 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4987 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4988 /// the specified operations to build the shuffle.
4989 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4990 SDValue RHS, SelectionDAG &DAG,
4992 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4993 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4994 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4997 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5006 OP_VUZPL, // VUZP, left result
5007 OP_VUZPR, // VUZP, right result
5008 OP_VZIPL, // VZIP, left result
5009 OP_VZIPR, // VZIP, right result
5010 OP_VTRNL, // VTRN, left result
5011 OP_VTRNR // VTRN, right result
5014 if (OpNum == OP_COPY) {
5015 if (LHSID == (1 * 9 + 2) * 9 + 3)
5017 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5021 SDValue OpLHS, OpRHS;
5022 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5023 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5024 EVT VT = OpLHS.getValueType();
5028 llvm_unreachable("Unknown shuffle opcode!");
5030 // VREV divides the vector in half and swaps within the half.
5031 if (VT.getVectorElementType() == MVT::i32 ||
5032 VT.getVectorElementType() == MVT::f32)
5033 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5034 // vrev <4 x i16> -> REV32
5035 if (VT.getVectorElementType() == MVT::i16 ||
5036 VT.getVectorElementType() == MVT::f16)
5037 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5038 // vrev <4 x i8> -> REV16
5039 assert(VT.getVectorElementType() == MVT::i8);
5040 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5045 EVT EltTy = VT.getVectorElementType();
5047 if (EltTy == MVT::i8)
5048 Opcode = AArch64ISD::DUPLANE8;
5049 else if (EltTy == MVT::i16)
5050 Opcode = AArch64ISD::DUPLANE16;
5051 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5052 Opcode = AArch64ISD::DUPLANE32;
5053 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5054 Opcode = AArch64ISD::DUPLANE64;
5056 llvm_unreachable("Invalid vector element type?");
5058 if (VT.getSizeInBits() == 64)
5059 OpLHS = WidenVector(OpLHS, DAG);
5060 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
5061 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5066 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5067 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5068 DAG.getConstant(Imm, MVT::i32));
5071 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5074 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5077 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5080 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5083 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5086 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5091 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5092 SelectionDAG &DAG) {
5093 // Check to see if we can use the TBL instruction.
5094 SDValue V1 = Op.getOperand(0);
5095 SDValue V2 = Op.getOperand(1);
5098 EVT EltVT = Op.getValueType().getVectorElementType();
5099 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5101 SmallVector<SDValue, 8> TBLMask;
5102 for (int Val : ShuffleMask) {
5103 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5104 unsigned Offset = Byte + Val * BytesPerElt;
5105 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
5109 MVT IndexVT = MVT::v8i8;
5110 unsigned IndexLen = 8;
5111 if (Op.getValueType().getSizeInBits() == 128) {
5112 IndexVT = MVT::v16i8;
5116 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5117 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5120 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5122 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5123 Shuffle = DAG.getNode(
5124 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5125 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5126 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5127 makeArrayRef(TBLMask.data(), IndexLen)));
5129 if (IndexLen == 8) {
5130 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5131 Shuffle = DAG.getNode(
5132 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5133 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5134 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5135 makeArrayRef(TBLMask.data(), IndexLen)));
5137 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5138 // cannot currently represent the register constraints on the input
5140 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5141 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5142 // &TBLMask[0], IndexLen));
5143 Shuffle = DAG.getNode(
5144 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5145 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
5146 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5147 makeArrayRef(TBLMask.data(), IndexLen)));
5150 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5153 static unsigned getDUPLANEOp(EVT EltType) {
5154 if (EltType == MVT::i8)
5155 return AArch64ISD::DUPLANE8;
5156 if (EltType == MVT::i16 || EltType == MVT::f16)
5157 return AArch64ISD::DUPLANE16;
5158 if (EltType == MVT::i32 || EltType == MVT::f32)
5159 return AArch64ISD::DUPLANE32;
5160 if (EltType == MVT::i64 || EltType == MVT::f64)
5161 return AArch64ISD::DUPLANE64;
5163 llvm_unreachable("Invalid vector element type?");
5166 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5167 SelectionDAG &DAG) const {
5169 EVT VT = Op.getValueType();
5171 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5173 // Convert shuffles that are directly supported on NEON to target-specific
5174 // DAG nodes, instead of keeping them as shuffles and matching them again
5175 // during code selection. This is more efficient and avoids the possibility
5176 // of inconsistencies between legalization and selection.
5177 ArrayRef<int> ShuffleMask = SVN->getMask();
5179 SDValue V1 = Op.getOperand(0);
5180 SDValue V2 = Op.getOperand(1);
5182 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5183 V1.getValueType().getSimpleVT())) {
5184 int Lane = SVN->getSplatIndex();
5185 // If this is undef splat, generate it via "just" vdup, if possible.
5189 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5190 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5192 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5193 // constant. If so, we can just reference the lane's definition directly.
5194 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5195 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5196 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5198 // Otherwise, duplicate from the lane of the input vector.
5199 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5201 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5202 // to make a vector of the same size as this SHUFFLE. We can ignore the
5203 // extract entirely, and canonicalise the concat using WidenVector.
5204 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5205 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5206 V1 = V1.getOperand(0);
5207 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5208 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5209 Lane -= Idx * VT.getVectorNumElements() / 2;
5210 V1 = WidenVector(V1.getOperand(Idx), DAG);
5211 } else if (VT.getSizeInBits() == 64)
5212 V1 = WidenVector(V1, DAG);
5214 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
5217 if (isREVMask(ShuffleMask, VT, 64))
5218 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5219 if (isREVMask(ShuffleMask, VT, 32))
5220 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5221 if (isREVMask(ShuffleMask, VT, 16))
5222 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5224 bool ReverseEXT = false;
5226 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5229 Imm *= getExtFactor(V1);
5230 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5231 DAG.getConstant(Imm, MVT::i32));
5232 } else if (V2->getOpcode() == ISD::UNDEF &&
5233 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5234 Imm *= getExtFactor(V1);
5235 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5236 DAG.getConstant(Imm, MVT::i32));
5239 unsigned WhichResult;
5240 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5241 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5242 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5244 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5245 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5246 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5248 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5249 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5250 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5253 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5254 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5255 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5257 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5258 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5259 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5261 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5262 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5263 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5266 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5267 if (Concat.getNode())
5272 int NumInputElements = V1.getValueType().getVectorNumElements();
5273 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5274 SDValue DstVec = DstIsLeft ? V1 : V2;
5275 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5277 SDValue SrcVec = V1;
5278 int SrcLane = ShuffleMask[Anomaly];
5279 if (SrcLane >= NumInputElements) {
5281 SrcLane -= VT.getVectorNumElements();
5283 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5285 EVT ScalarVT = VT.getVectorElementType();
5287 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5288 ScalarVT = MVT::i32;
5291 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5292 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5296 // If the shuffle is not directly supported and it has 4 elements, use
5297 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5298 unsigned NumElts = VT.getVectorNumElements();
5300 unsigned PFIndexes[4];
5301 for (unsigned i = 0; i != 4; ++i) {
5302 if (ShuffleMask[i] < 0)
5305 PFIndexes[i] = ShuffleMask[i];
5308 // Compute the index in the perfect shuffle table.
5309 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5310 PFIndexes[2] * 9 + PFIndexes[3];
5311 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5312 unsigned Cost = (PFEntry >> 30);
5315 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5318 return GenerateTBL(Op, ShuffleMask, DAG);
5321 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5323 EVT VT = BVN->getValueType(0);
5324 APInt SplatBits, SplatUndef;
5325 unsigned SplatBitSize;
5327 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5328 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5330 for (unsigned i = 0; i < NumSplats; ++i) {
5331 CnstBits <<= SplatBitSize;
5332 UndefBits <<= SplatBitSize;
5333 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5334 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5343 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5344 SelectionDAG &DAG) const {
5345 BuildVectorSDNode *BVN =
5346 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5347 SDValue LHS = Op.getOperand(0);
5349 EVT VT = Op.getValueType();
5354 APInt CnstBits(VT.getSizeInBits(), 0);
5355 APInt UndefBits(VT.getSizeInBits(), 0);
5356 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5357 // We only have BIC vector immediate instruction, which is and-not.
5358 CnstBits = ~CnstBits;
5360 // We make use of a little bit of goto ickiness in order to avoid having to
5361 // duplicate the immediate matching logic for the undef toggled case.
5362 bool SecondTry = false;
5365 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5366 CnstBits = CnstBits.zextOrTrunc(64);
5367 uint64_t CnstVal = CnstBits.getZExtValue();
5369 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5370 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5371 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5372 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5373 DAG.getConstant(CnstVal, MVT::i32),
5374 DAG.getConstant(0, MVT::i32));
5375 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5378 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5379 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5380 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5381 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5382 DAG.getConstant(CnstVal, MVT::i32),
5383 DAG.getConstant(8, MVT::i32));
5384 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5387 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5388 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5389 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5390 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5391 DAG.getConstant(CnstVal, MVT::i32),
5392 DAG.getConstant(16, MVT::i32));
5393 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5396 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5397 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5398 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5399 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5400 DAG.getConstant(CnstVal, MVT::i32),
5401 DAG.getConstant(24, MVT::i32));
5402 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5405 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5406 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5407 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5408 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5409 DAG.getConstant(CnstVal, MVT::i32),
5410 DAG.getConstant(0, MVT::i32));
5411 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5414 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5415 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5416 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5417 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5418 DAG.getConstant(CnstVal, MVT::i32),
5419 DAG.getConstant(8, MVT::i32));
5420 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5427 CnstBits = ~UndefBits;
5431 // We can always fall back to a non-immediate AND.
5436 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5437 // consists of only the same constant int value, returned in reference arg
5439 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5440 uint64_t &ConstVal) {
5441 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5444 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5447 EVT VT = Bvec->getValueType(0);
5448 unsigned NumElts = VT.getVectorNumElements();
5449 for (unsigned i = 1; i < NumElts; ++i)
5450 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5452 ConstVal = FirstElt->getZExtValue();
5456 static unsigned getIntrinsicID(const SDNode *N) {
5457 unsigned Opcode = N->getOpcode();
5460 return Intrinsic::not_intrinsic;
5461 case ISD::INTRINSIC_WO_CHAIN: {
5462 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5463 if (IID < Intrinsic::num_intrinsics)
5465 return Intrinsic::not_intrinsic;
5470 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5471 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5472 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5473 // Also, logical shift right -> sri, with the same structure.
5474 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5475 EVT VT = N->getValueType(0);
5482 // Is the first op an AND?
5483 const SDValue And = N->getOperand(0);
5484 if (And.getOpcode() != ISD::AND)
5487 // Is the second op an shl or lshr?
5488 SDValue Shift = N->getOperand(1);
5489 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5490 // or AArch64ISD::VLSHR vector, #shift
5491 unsigned ShiftOpc = Shift.getOpcode();
5492 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5494 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5496 // Is the shift amount constant?
5497 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5501 // Is the and mask vector all constant?
5503 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5506 // Is C1 == ~C2, taking into account how much one can shift elements of a
5508 uint64_t C2 = C2node->getZExtValue();
5509 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5510 if (C2 > ElemSizeInBits)
5512 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5513 if ((C1 & ElemMask) != (~C2 & ElemMask))
5516 SDValue X = And.getOperand(0);
5517 SDValue Y = Shift.getOperand(0);
5520 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5522 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5523 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5525 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5526 DEBUG(N->dump(&DAG));
5527 DEBUG(dbgs() << "into: \n");
5528 DEBUG(ResultSLI->dump(&DAG));
5534 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5535 SelectionDAG &DAG) const {
5536 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5537 if (EnableAArch64SlrGeneration) {
5538 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5543 BuildVectorSDNode *BVN =
5544 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5545 SDValue LHS = Op.getOperand(1);
5547 EVT VT = Op.getValueType();
5549 // OR commutes, so try swapping the operands.
5551 LHS = Op.getOperand(0);
5552 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5557 APInt CnstBits(VT.getSizeInBits(), 0);
5558 APInt UndefBits(VT.getSizeInBits(), 0);
5559 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5560 // We make use of a little bit of goto ickiness in order to avoid having to
5561 // duplicate the immediate matching logic for the undef toggled case.
5562 bool SecondTry = false;
5565 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5566 CnstBits = CnstBits.zextOrTrunc(64);
5567 uint64_t CnstVal = CnstBits.getZExtValue();
5569 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5570 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5571 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5572 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5573 DAG.getConstant(CnstVal, MVT::i32),
5574 DAG.getConstant(0, MVT::i32));
5575 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5578 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5579 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5580 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5581 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5582 DAG.getConstant(CnstVal, MVT::i32),
5583 DAG.getConstant(8, MVT::i32));
5584 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5587 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5588 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5589 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5590 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5591 DAG.getConstant(CnstVal, MVT::i32),
5592 DAG.getConstant(16, MVT::i32));
5593 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5596 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5597 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5598 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5599 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5600 DAG.getConstant(CnstVal, MVT::i32),
5601 DAG.getConstant(24, MVT::i32));
5602 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5605 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5606 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5607 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5608 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5609 DAG.getConstant(CnstVal, MVT::i32),
5610 DAG.getConstant(0, MVT::i32));
5611 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5614 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5615 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5616 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5617 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5618 DAG.getConstant(CnstVal, MVT::i32),
5619 DAG.getConstant(8, MVT::i32));
5620 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5627 CnstBits = UndefBits;
5631 // We can always fall back to a non-immediate OR.
5636 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5637 // be truncated to fit element width.
5638 static SDValue NormalizeBuildVector(SDValue Op,
5639 SelectionDAG &DAG) {
5640 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5642 EVT VT = Op.getValueType();
5643 EVT EltTy= VT.getVectorElementType();
5645 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5648 SmallVector<SDValue, 16> Ops;
5649 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5650 SDValue Lane = Op.getOperand(I);
5651 if (Lane.getOpcode() == ISD::Constant) {
5652 APInt LowBits(EltTy.getSizeInBits(),
5653 cast<ConstantSDNode>(Lane)->getZExtValue());
5654 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5656 Ops.push_back(Lane);
5658 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5661 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5662 SelectionDAG &DAG) const {
5664 EVT VT = Op.getValueType();
5665 Op = NormalizeBuildVector(Op, DAG);
5666 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5668 APInt CnstBits(VT.getSizeInBits(), 0);
5669 APInt UndefBits(VT.getSizeInBits(), 0);
5670 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5671 // We make use of a little bit of goto ickiness in order to avoid having to
5672 // duplicate the immediate matching logic for the undef toggled case.
5673 bool SecondTry = false;
5676 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5677 CnstBits = CnstBits.zextOrTrunc(64);
5678 uint64_t CnstVal = CnstBits.getZExtValue();
5680 // Certain magic vector constants (used to express things like NOT
5681 // and NEG) are passed through unmodified. This allows codegen patterns
5682 // for these operations to match. Special-purpose patterns will lower
5683 // these immediates to MOVIs if it proves necessary.
5684 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5687 // The many faces of MOVI...
5688 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5689 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5690 if (VT.getSizeInBits() == 128) {
5691 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5692 DAG.getConstant(CnstVal, MVT::i32));
5693 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5696 // Support the V64 version via subregister insertion.
5697 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5698 DAG.getConstant(CnstVal, MVT::i32));
5699 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5702 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5703 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5704 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5705 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5706 DAG.getConstant(CnstVal, MVT::i32),
5707 DAG.getConstant(0, MVT::i32));
5708 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5711 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5712 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5713 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5714 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5715 DAG.getConstant(CnstVal, MVT::i32),
5716 DAG.getConstant(8, MVT::i32));
5717 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5720 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5721 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5722 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5723 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5724 DAG.getConstant(CnstVal, MVT::i32),
5725 DAG.getConstant(16, MVT::i32));
5726 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5729 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5730 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5731 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5732 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5733 DAG.getConstant(CnstVal, MVT::i32),
5734 DAG.getConstant(24, MVT::i32));
5735 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5738 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5739 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5740 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5741 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5742 DAG.getConstant(CnstVal, MVT::i32),
5743 DAG.getConstant(0, MVT::i32));
5744 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5747 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5748 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5749 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5750 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5751 DAG.getConstant(CnstVal, MVT::i32),
5752 DAG.getConstant(8, MVT::i32));
5753 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5756 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5757 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5758 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5759 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5760 DAG.getConstant(CnstVal, MVT::i32),
5761 DAG.getConstant(264, MVT::i32));
5762 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5765 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5766 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5767 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5768 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5769 DAG.getConstant(CnstVal, MVT::i32),
5770 DAG.getConstant(272, MVT::i32));
5771 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5774 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5775 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5776 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5777 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5778 DAG.getConstant(CnstVal, MVT::i32));
5779 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5782 // The few faces of FMOV...
5783 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5784 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5785 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5786 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5787 DAG.getConstant(CnstVal, MVT::i32));
5788 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5791 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5792 VT.getSizeInBits() == 128) {
5793 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5794 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5795 DAG.getConstant(CnstVal, MVT::i32));
5796 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5799 // The many faces of MVNI...
5801 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5802 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5803 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5804 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5805 DAG.getConstant(CnstVal, MVT::i32),
5806 DAG.getConstant(0, MVT::i32));
5807 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5810 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5811 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5812 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5813 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5814 DAG.getConstant(CnstVal, MVT::i32),
5815 DAG.getConstant(8, MVT::i32));
5816 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5819 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5820 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5821 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5822 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5823 DAG.getConstant(CnstVal, MVT::i32),
5824 DAG.getConstant(16, MVT::i32));
5825 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5828 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5829 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5830 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5831 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5832 DAG.getConstant(CnstVal, MVT::i32),
5833 DAG.getConstant(24, MVT::i32));
5834 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5837 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5838 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5839 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5840 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5841 DAG.getConstant(CnstVal, MVT::i32),
5842 DAG.getConstant(0, MVT::i32));
5843 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5846 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5847 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5848 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5849 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5850 DAG.getConstant(CnstVal, MVT::i32),
5851 DAG.getConstant(8, MVT::i32));
5852 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5855 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5856 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5857 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5858 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5859 DAG.getConstant(CnstVal, MVT::i32),
5860 DAG.getConstant(264, MVT::i32));
5861 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5864 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5865 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5866 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5867 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5868 DAG.getConstant(CnstVal, MVT::i32),
5869 DAG.getConstant(272, MVT::i32));
5870 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5877 CnstBits = UndefBits;
5882 // Scan through the operands to find some interesting properties we can
5884 // 1) If only one value is used, we can use a DUP, or
5885 // 2) if only the low element is not undef, we can just insert that, or
5886 // 3) if only one constant value is used (w/ some non-constant lanes),
5887 // we can splat the constant value into the whole vector then fill
5888 // in the non-constant lanes.
5889 // 4) FIXME: If different constant values are used, but we can intelligently
5890 // select the values we'll be overwriting for the non-constant
5891 // lanes such that we can directly materialize the vector
5892 // some other way (MOVI, e.g.), we can be sneaky.
5893 unsigned NumElts = VT.getVectorNumElements();
5894 bool isOnlyLowElement = true;
5895 bool usesOnlyOneValue = true;
5896 bool usesOnlyOneConstantValue = true;
5897 bool isConstant = true;
5898 unsigned NumConstantLanes = 0;
5900 SDValue ConstantValue;
5901 for (unsigned i = 0; i < NumElts; ++i) {
5902 SDValue V = Op.getOperand(i);
5903 if (V.getOpcode() == ISD::UNDEF)
5906 isOnlyLowElement = false;
5907 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5910 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5912 if (!ConstantValue.getNode())
5914 else if (ConstantValue != V)
5915 usesOnlyOneConstantValue = false;
5918 if (!Value.getNode())
5920 else if (V != Value)
5921 usesOnlyOneValue = false;
5924 if (!Value.getNode())
5925 return DAG.getUNDEF(VT);
5927 if (isOnlyLowElement)
5928 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5930 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5931 // i32 and try again.
5932 if (usesOnlyOneValue) {
5934 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5935 Value.getValueType() != VT)
5936 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5938 // This is actually a DUPLANExx operation, which keeps everything vectory.
5940 // DUPLANE works on 128-bit vectors, widen it if necessary.
5941 SDValue Lane = Value.getOperand(1);
5942 Value = Value.getOperand(0);
5943 if (Value.getValueType().getSizeInBits() == 64)
5944 Value = WidenVector(Value, DAG);
5946 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5947 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5950 if (VT.getVectorElementType().isFloatingPoint()) {
5951 SmallVector<SDValue, 8> Ops;
5952 EVT EltTy = VT.getVectorElementType();
5953 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
5954 "Unsupported floating-point vector type");
5955 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
5956 for (unsigned i = 0; i < NumElts; ++i)
5957 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5958 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5959 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5960 Val = LowerBUILD_VECTOR(Val, DAG);
5962 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5966 // If there was only one constant value used and for more than one lane,
5967 // start by splatting that value, then replace the non-constant lanes. This
5968 // is better than the default, which will perform a separate initialization
5970 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5971 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5972 // Now insert the non-constant lanes.
5973 for (unsigned i = 0; i < NumElts; ++i) {
5974 SDValue V = Op.getOperand(i);
5975 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5976 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5977 // Note that type legalization likely mucked about with the VT of the
5978 // source operand, so we may have to convert it here before inserting.
5979 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5985 // If all elements are constants and the case above didn't get hit, fall back
5986 // to the default expansion, which will generate a load from the constant
5991 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5993 SDValue shuffle = ReconstructShuffle(Op, DAG);
5994 if (shuffle != SDValue())
5998 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5999 // know the default expansion would otherwise fall back on something even
6000 // worse. For a vector with one or two non-undef values, that's
6001 // scalar_to_vector for the elements followed by a shuffle (provided the
6002 // shuffle is valid for the target) and materialization element by element
6003 // on the stack followed by a load for everything else.
6004 if (!isConstant && !usesOnlyOneValue) {
6005 SDValue Vec = DAG.getUNDEF(VT);
6006 SDValue Op0 = Op.getOperand(0);
6007 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6009 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6010 // a) Avoid a RMW dependency on the full vector register, and
6011 // b) Allow the register coalescer to fold away the copy if the
6012 // value is already in an S or D register.
6013 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6014 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6016 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6017 DAG.getTargetConstant(SubIdx, MVT::i32));
6018 Vec = SDValue(N, 0);
6021 for (; i < NumElts; ++i) {
6022 SDValue V = Op.getOperand(i);
6023 if (V.getOpcode() == ISD::UNDEF)
6025 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
6026 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6031 // Just use the default expansion. We failed to find a better alternative.
6035 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6036 SelectionDAG &DAG) const {
6037 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6039 // Check for non-constant or out of range lane.
6040 EVT VT = Op.getOperand(0).getValueType();
6041 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6042 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6046 // Insertion/extraction are legal for V128 types.
6047 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6048 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6052 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6053 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6056 // For V64 types, we perform insertion by expanding the value
6057 // to a V128 type and perform the insertion on that.
6059 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6060 EVT WideTy = WideVec.getValueType();
6062 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6063 Op.getOperand(1), Op.getOperand(2));
6064 // Re-narrow the resultant vector.
6065 return NarrowVector(Node, DAG);
6069 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6070 SelectionDAG &DAG) const {
6071 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6073 // Check for non-constant or out of range lane.
6074 EVT VT = Op.getOperand(0).getValueType();
6075 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6076 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6080 // Insertion/extraction are legal for V128 types.
6081 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6082 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6086 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6087 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6090 // For V64 types, we perform extraction by expanding the value
6091 // to a V128 type and perform the extraction on that.
6093 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6094 EVT WideTy = WideVec.getValueType();
6096 EVT ExtrTy = WideTy.getVectorElementType();
6097 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6100 // For extractions, we just return the result directly.
6101 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6105 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6106 SelectionDAG &DAG) const {
6107 EVT VT = Op.getOperand(0).getValueType();
6113 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6116 unsigned Val = Cst->getZExtValue();
6118 unsigned Size = Op.getValueType().getSizeInBits();
6122 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6125 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6128 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6131 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6134 llvm_unreachable("Unexpected vector type in extract_subvector!");
6137 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6139 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6145 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6147 if (VT.getVectorNumElements() == 4 &&
6148 (VT.is128BitVector() || VT.is64BitVector())) {
6149 unsigned PFIndexes[4];
6150 for (unsigned i = 0; i != 4; ++i) {
6154 PFIndexes[i] = M[i];
6157 // Compute the index in the perfect shuffle table.
6158 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6159 PFIndexes[2] * 9 + PFIndexes[3];
6160 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6161 unsigned Cost = (PFEntry >> 30);
6169 unsigned DummyUnsigned;
6171 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6172 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6173 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6174 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6175 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6176 isZIPMask(M, VT, DummyUnsigned) ||
6177 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6178 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6179 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6180 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6181 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6184 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6185 /// operand of a vector shift operation, where all the elements of the
6186 /// build_vector must have the same constant integer value.
6187 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6188 // Ignore bit_converts.
6189 while (Op.getOpcode() == ISD::BITCAST)
6190 Op = Op.getOperand(0);
6191 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6192 APInt SplatBits, SplatUndef;
6193 unsigned SplatBitSize;
6195 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6196 HasAnyUndefs, ElementBits) ||
6197 SplatBitSize > ElementBits)
6199 Cnt = SplatBits.getSExtValue();
6203 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6204 /// operand of a vector shift left operation. That value must be in the range:
6205 /// 0 <= Value < ElementBits for a left shift; or
6206 /// 0 <= Value <= ElementBits for a long left shift.
6207 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6208 assert(VT.isVector() && "vector shift count is not a vector type");
6209 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6210 if (!getVShiftImm(Op, ElementBits, Cnt))
6212 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6215 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6216 /// operand of a vector shift right operation. For a shift opcode, the value
6217 /// is positive, but for an intrinsic the value count must be negative. The
6218 /// absolute value must be in the range:
6219 /// 1 <= |Value| <= ElementBits for a right shift; or
6220 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6221 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6223 assert(VT.isVector() && "vector shift count is not a vector type");
6224 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6225 if (!getVShiftImm(Op, ElementBits, Cnt))
6229 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6232 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6233 SelectionDAG &DAG) const {
6234 EVT VT = Op.getValueType();
6238 if (!Op.getOperand(1).getValueType().isVector())
6240 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6242 switch (Op.getOpcode()) {
6244 llvm_unreachable("unexpected shift opcode");
6247 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6248 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6249 DAG.getConstant(Cnt, MVT::i32));
6250 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6251 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6252 Op.getOperand(0), Op.getOperand(1));
6255 // Right shift immediate
6256 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6259 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6260 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6261 DAG.getConstant(Cnt, MVT::i32));
6264 // Right shift register. Note, there is not a shift right register
6265 // instruction, but the shift left register instruction takes a signed
6266 // value, where negative numbers specify a right shift.
6267 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6268 : Intrinsic::aarch64_neon_ushl;
6269 // negate the shift amount
6270 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6271 SDValue NegShiftLeft =
6272 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6273 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6274 return NegShiftLeft;
6280 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6281 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6282 SDLoc dl, SelectionDAG &DAG) {
6283 EVT SrcVT = LHS.getValueType();
6284 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6285 "function only supposed to emit natural comparisons");
6287 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6288 APInt CnstBits(VT.getSizeInBits(), 0);
6289 APInt UndefBits(VT.getSizeInBits(), 0);
6290 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6291 bool IsZero = IsCnst && (CnstBits == 0);
6293 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6297 case AArch64CC::NE: {
6300 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6302 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6303 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6307 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6308 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6311 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6312 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6315 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6316 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6319 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6320 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6324 // If we ignore NaNs then we can use to the MI implementation.
6328 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6329 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6336 case AArch64CC::NE: {
6339 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6341 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6342 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6346 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6347 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6350 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6351 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6354 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6355 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6358 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6359 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6361 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6363 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6366 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6367 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6369 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6371 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6375 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6376 SelectionDAG &DAG) const {
6377 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6378 SDValue LHS = Op.getOperand(0);
6379 SDValue RHS = Op.getOperand(1);
6380 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6383 if (LHS.getValueType().getVectorElementType().isInteger()) {
6384 assert(LHS.getValueType() == RHS.getValueType());
6385 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6387 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6388 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6391 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6392 LHS.getValueType().getVectorElementType() == MVT::f64);
6394 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6395 // clean. Some of them require two branches to implement.
6396 AArch64CC::CondCode CC1, CC2;
6398 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6400 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6402 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6406 if (CC2 != AArch64CC::AL) {
6408 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6409 if (!Cmp2.getNode())
6412 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6415 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6418 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6423 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6424 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6425 /// specified in the intrinsic calls.
6426 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6428 unsigned Intrinsic) const {
6429 switch (Intrinsic) {
6430 case Intrinsic::aarch64_neon_ld2:
6431 case Intrinsic::aarch64_neon_ld3:
6432 case Intrinsic::aarch64_neon_ld4:
6433 case Intrinsic::aarch64_neon_ld1x2:
6434 case Intrinsic::aarch64_neon_ld1x3:
6435 case Intrinsic::aarch64_neon_ld1x4:
6436 case Intrinsic::aarch64_neon_ld2lane:
6437 case Intrinsic::aarch64_neon_ld3lane:
6438 case Intrinsic::aarch64_neon_ld4lane:
6439 case Intrinsic::aarch64_neon_ld2r:
6440 case Intrinsic::aarch64_neon_ld3r:
6441 case Intrinsic::aarch64_neon_ld4r: {
6442 Info.opc = ISD::INTRINSIC_W_CHAIN;
6443 // Conservatively set memVT to the entire set of vectors loaded.
6444 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6445 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6446 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6449 Info.vol = false; // volatile loads with NEON intrinsics not supported
6450 Info.readMem = true;
6451 Info.writeMem = false;
6454 case Intrinsic::aarch64_neon_st2:
6455 case Intrinsic::aarch64_neon_st3:
6456 case Intrinsic::aarch64_neon_st4:
6457 case Intrinsic::aarch64_neon_st1x2:
6458 case Intrinsic::aarch64_neon_st1x3:
6459 case Intrinsic::aarch64_neon_st1x4:
6460 case Intrinsic::aarch64_neon_st2lane:
6461 case Intrinsic::aarch64_neon_st3lane:
6462 case Intrinsic::aarch64_neon_st4lane: {
6463 Info.opc = ISD::INTRINSIC_VOID;
6464 // Conservatively set memVT to the entire set of vectors stored.
6465 unsigned NumElts = 0;
6466 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6467 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6468 if (!ArgTy->isVectorTy())
6470 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6472 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6473 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6476 Info.vol = false; // volatile stores with NEON intrinsics not supported
6477 Info.readMem = false;
6478 Info.writeMem = true;
6481 case Intrinsic::aarch64_ldaxr:
6482 case Intrinsic::aarch64_ldxr: {
6483 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6484 Info.opc = ISD::INTRINSIC_W_CHAIN;
6485 Info.memVT = MVT::getVT(PtrTy->getElementType());
6486 Info.ptrVal = I.getArgOperand(0);
6488 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6490 Info.readMem = true;
6491 Info.writeMem = false;
6494 case Intrinsic::aarch64_stlxr:
6495 case Intrinsic::aarch64_stxr: {
6496 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6497 Info.opc = ISD::INTRINSIC_W_CHAIN;
6498 Info.memVT = MVT::getVT(PtrTy->getElementType());
6499 Info.ptrVal = I.getArgOperand(1);
6501 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6503 Info.readMem = false;
6504 Info.writeMem = true;
6507 case Intrinsic::aarch64_ldaxp:
6508 case Intrinsic::aarch64_ldxp: {
6509 Info.opc = ISD::INTRINSIC_W_CHAIN;
6510 Info.memVT = MVT::i128;
6511 Info.ptrVal = I.getArgOperand(0);
6515 Info.readMem = true;
6516 Info.writeMem = false;
6519 case Intrinsic::aarch64_stlxp:
6520 case Intrinsic::aarch64_stxp: {
6521 Info.opc = ISD::INTRINSIC_W_CHAIN;
6522 Info.memVT = MVT::i128;
6523 Info.ptrVal = I.getArgOperand(2);
6527 Info.readMem = false;
6528 Info.writeMem = true;
6538 // Truncations from 64-bit GPR to 32-bit GPR is free.
6539 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6540 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6542 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6543 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6544 return NumBits1 > NumBits2;
6546 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6547 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6549 unsigned NumBits1 = VT1.getSizeInBits();
6550 unsigned NumBits2 = VT2.getSizeInBits();
6551 return NumBits1 > NumBits2;
6554 /// Check if it is profitable to hoist instruction in then/else to if.
6555 /// Not profitable if I and it's user can form a FMA instruction
6556 /// because we prefer FMSUB/FMADD.
6557 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6558 if (I->getOpcode() != Instruction::FMul)
6561 if (I->getNumUses() != 1)
6564 Instruction *User = I->user_back();
6567 !(User->getOpcode() == Instruction::FSub ||
6568 User->getOpcode() == Instruction::FAdd))
6571 const TargetOptions &Options = getTargetMachine().Options;
6572 EVT VT = getValueType(User->getOperand(0)->getType());
6574 if (isFMAFasterThanFMulAndFAdd(VT) &&
6575 isOperationLegalOrCustom(ISD::FMA, VT) &&
6576 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6582 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6584 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6585 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6587 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6588 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6589 return NumBits1 == 32 && NumBits2 == 64;
6591 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6592 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6594 unsigned NumBits1 = VT1.getSizeInBits();
6595 unsigned NumBits2 = VT2.getSizeInBits();
6596 return NumBits1 == 32 && NumBits2 == 64;
6599 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6600 EVT VT1 = Val.getValueType();
6601 if (isZExtFree(VT1, VT2)) {
6605 if (Val.getOpcode() != ISD::LOAD)
6608 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6609 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6610 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6611 VT1.getSizeInBits() <= 32);
6614 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6615 if (isa<FPExtInst>(Ext))
6618 // Vector types are next free.
6619 if (Ext->getType()->isVectorTy())
6622 for (const Use &U : Ext->uses()) {
6623 // The extension is free if we can fold it with a left shift in an
6624 // addressing mode or an arithmetic operation: add, sub, and cmp.
6626 // Is there a shift?
6627 const Instruction *Instr = cast<Instruction>(U.getUser());
6629 // Is this a constant shift?
6630 switch (Instr->getOpcode()) {
6631 case Instruction::Shl:
6632 if (!isa<ConstantInt>(Instr->getOperand(1)))
6635 case Instruction::GetElementPtr: {
6636 gep_type_iterator GTI = gep_type_begin(Instr);
6637 std::advance(GTI, U.getOperandNo());
6639 // This extension will end up with a shift because of the scaling factor.
6640 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6641 // Get the shift amount based on the scaling factor:
6642 // log2(sizeof(IdxTy)) - log2(8).
6644 countTrailingZeros(getDataLayout()->getTypeStoreSizeInBits(IdxTy)) - 3;
6645 // Is the constant foldable in the shift of the addressing mode?
6646 // I.e., shift amount is between 1 and 4 inclusive.
6647 if (ShiftAmt == 0 || ShiftAmt > 4)
6651 case Instruction::Trunc:
6652 // Check if this is a noop.
6653 // trunc(sext ty1 to ty2) to ty1.
6654 if (Instr->getType() == Ext->getOperand(0)->getType())
6661 // At this point we can use the bfm family, so this extension is free
6667 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6668 unsigned &RequiredAligment) const {
6669 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6671 // Cyclone supports unaligned accesses.
6672 RequiredAligment = 0;
6673 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6674 return NumBits == 32 || NumBits == 64;
6677 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6678 unsigned &RequiredAligment) const {
6679 if (!LoadedType.isSimple() ||
6680 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6682 // Cyclone supports unaligned accesses.
6683 RequiredAligment = 0;
6684 unsigned NumBits = LoadedType.getSizeInBits();
6685 return NumBits == 32 || NumBits == 64;
6688 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6689 unsigned AlignCheck) {
6690 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6691 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6694 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6695 unsigned SrcAlign, bool IsMemset,
6698 MachineFunction &MF) const {
6699 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6700 // instruction to materialize the v2i64 zero and one store (with restrictive
6701 // addressing mode). Just do two i64 store of zero-registers.
6703 const Function *F = MF.getFunction();
6704 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6705 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
6706 (memOpAlign(SrcAlign, DstAlign, 16) ||
6707 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6711 (memOpAlign(SrcAlign, DstAlign, 8) ||
6712 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
6716 (memOpAlign(SrcAlign, DstAlign, 4) ||
6717 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
6723 // 12-bit optionally shifted immediates are legal for adds.
6724 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6725 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6730 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6731 // immediates is the same as for an add or a sub.
6732 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6735 return isLegalAddImmediate(Immed);
6738 /// isLegalAddressingMode - Return true if the addressing mode represented
6739 /// by AM is legal for this target, for a load/store of the specified type.
6740 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6742 // AArch64 has five basic addressing modes:
6744 // reg + 9-bit signed offset
6745 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6747 // reg + SIZE_IN_BYTES * reg
6749 // No global is ever allowed as a base.
6753 // No reg+reg+imm addressing.
6754 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6757 // check reg + imm case:
6758 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6759 uint64_t NumBytes = 0;
6760 if (Ty->isSized()) {
6761 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6762 NumBytes = NumBits / 8;
6763 if (!isPowerOf2_64(NumBits))
6768 int64_t Offset = AM.BaseOffs;
6770 // 9-bit signed offset
6771 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6774 // 12-bit unsigned offset
6775 unsigned shift = Log2_64(NumBytes);
6776 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6777 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6778 (Offset >> shift) << shift == Offset)
6783 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6785 if (!AM.Scale || AM.Scale == 1 ||
6786 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6791 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6793 // Scaling factors are not free at all.
6794 // Operands | Rt Latency
6795 // -------------------------------------------
6797 // -------------------------------------------
6798 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6799 // Rt, [Xn, Wm, <extend> #imm] |
6800 if (isLegalAddressingMode(AM, Ty))
6801 // Scale represents reg2 * scale, thus account for 1 if
6802 // it is not equal to 0 or 1.
6803 return AM.Scale != 0 && AM.Scale != 1;
6807 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6808 VT = VT.getScalarType();
6813 switch (VT.getSimpleVT().SimpleTy) {
6825 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6826 // LR is a callee-save register, but we must treat it as clobbered by any call
6827 // site. Hence we include LR in the scratch registers, which are in turn added
6828 // as implicit-defs for stackmaps and patchpoints.
6829 static const MCPhysReg ScratchRegs[] = {
6830 AArch64::X16, AArch64::X17, AArch64::LR, 0
6836 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6837 EVT VT = N->getValueType(0);
6838 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6839 // it with shift to let it be lowered to UBFX.
6840 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6841 isa<ConstantSDNode>(N->getOperand(1))) {
6842 uint64_t TruncMask = N->getConstantOperandVal(1);
6843 if (isMask_64(TruncMask) &&
6844 N->getOperand(0).getOpcode() == ISD::SRL &&
6845 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6851 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6853 assert(Ty->isIntegerTy());
6855 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6859 int64_t Val = Imm.getSExtValue();
6860 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6863 if ((int64_t)Val < 0)
6866 Val &= (1LL << 32) - 1;
6868 unsigned LZ = countLeadingZeros((uint64_t)Val);
6869 unsigned Shift = (63 - LZ) / 16;
6870 // MOVZ is free so return true for one or fewer MOVK.
6874 // Generate SUBS and CSEL for integer abs.
6875 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6876 EVT VT = N->getValueType(0);
6878 SDValue N0 = N->getOperand(0);
6879 SDValue N1 = N->getOperand(1);
6882 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6883 // and change it to SUB and CSEL.
6884 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6885 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6886 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6887 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6888 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6889 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6891 // Generate SUBS & CSEL.
6893 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6894 N0.getOperand(0), DAG.getConstant(0, VT));
6895 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6896 DAG.getConstant(AArch64CC::PL, MVT::i32),
6897 SDValue(Cmp.getNode(), 1));
6902 // performXorCombine - Attempts to handle integer ABS.
6903 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6904 TargetLowering::DAGCombinerInfo &DCI,
6905 const AArch64Subtarget *Subtarget) {
6906 if (DCI.isBeforeLegalizeOps())
6909 return performIntegerAbsCombine(N, DAG);
6913 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6915 std::vector<SDNode *> *Created) const {
6916 // fold (sdiv X, pow2)
6917 EVT VT = N->getValueType(0);
6918 if ((VT != MVT::i32 && VT != MVT::i64) ||
6919 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6923 SDValue N0 = N->getOperand(0);
6924 unsigned Lg2 = Divisor.countTrailingZeros();
6925 SDValue Zero = DAG.getConstant(0, VT);
6926 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, VT);
6928 // Add (N0 < 0) ? Pow2 - 1 : 0;
6930 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6931 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6932 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6935 Created->push_back(Cmp.getNode());
6936 Created->push_back(Add.getNode());
6937 Created->push_back(CSel.getNode());
6942 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6944 // If we're dividing by a positive value, we're done. Otherwise, we must
6945 // negate the result.
6946 if (Divisor.isNonNegative())
6950 Created->push_back(SRA.getNode());
6951 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6954 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6955 TargetLowering::DAGCombinerInfo &DCI,
6956 const AArch64Subtarget *Subtarget) {
6957 if (DCI.isBeforeLegalizeOps())
6960 // Multiplication of a power of two plus/minus one can be done more
6961 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6962 // future CPUs have a cheaper MADD instruction, this may need to be
6963 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6964 // 64-bit is 5 cycles, so this is always a win.
6965 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6966 APInt Value = C->getAPIntValue();
6967 EVT VT = N->getValueType(0);
6968 if (Value.isNonNegative()) {
6969 // (mul x, 2^N + 1) => (add (shl x, N), x)
6970 APInt VM1 = Value - 1;
6971 if (VM1.isPowerOf2()) {
6972 SDValue ShiftedVal =
6973 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6974 DAG.getConstant(VM1.logBase2(), MVT::i64));
6975 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6978 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6979 APInt VP1 = Value + 1;
6980 if (VP1.isPowerOf2()) {
6981 SDValue ShiftedVal =
6982 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6983 DAG.getConstant(VP1.logBase2(), MVT::i64));
6984 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6988 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6989 APInt VNP1 = -Value + 1;
6990 if (VNP1.isPowerOf2()) {
6991 SDValue ShiftedVal =
6992 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6993 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6994 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6997 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6998 APInt VNM1 = -Value - 1;
6999 if (VNM1.isPowerOf2()) {
7000 SDValue ShiftedVal =
7001 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
7002 DAG.getConstant(VNM1.logBase2(), MVT::i64));
7004 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
7005 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
7012 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7013 SelectionDAG &DAG) {
7014 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7015 // optimize away operation when it's from a constant.
7017 // The general transformation is:
7018 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7019 // AND(VECTOR_CMP(x,y), constant2)
7020 // constant2 = UNARYOP(constant)
7022 // Early exit if this isn't a vector operation, the operand of the
7023 // unary operation isn't a bitwise AND, or if the sizes of the operations
7025 EVT VT = N->getValueType(0);
7026 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7027 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7028 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7031 // Now check that the other operand of the AND is a constant. We could
7032 // make the transformation for non-constant splats as well, but it's unclear
7033 // that would be a benefit as it would not eliminate any operations, just
7034 // perform one more step in scalar code before moving to the vector unit.
7035 if (BuildVectorSDNode *BV =
7036 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7037 // Bail out if the vector isn't a constant.
7038 if (!BV->isConstant())
7041 // Everything checks out. Build up the new and improved node.
7043 EVT IntVT = BV->getValueType(0);
7044 // Create a new constant of the appropriate type for the transformed
7046 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7047 // The AND node needs bitcasts to/from an integer vector type around it.
7048 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7049 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7050 N->getOperand(0)->getOperand(0), MaskConst);
7051 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7058 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7059 const AArch64Subtarget *Subtarget) {
7060 // First try to optimize away the conversion when it's conditionally from
7061 // a constant. Vectors only.
7062 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
7063 if (Res != SDValue())
7066 EVT VT = N->getValueType(0);
7067 if (VT != MVT::f32 && VT != MVT::f64)
7070 // Only optimize when the source and destination types have the same width.
7071 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7074 // If the result of an integer load is only used by an integer-to-float
7075 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7076 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7077 SDValue N0 = N->getOperand(0);
7078 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7079 // Do not change the width of a volatile load.
7080 !cast<LoadSDNode>(N0)->isVolatile()) {
7081 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7082 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7083 LN0->getPointerInfo(), LN0->isVolatile(),
7084 LN0->isNonTemporal(), LN0->isInvariant(),
7085 LN0->getAlignment());
7087 // Make sure successors of the original load stay after it by updating them
7088 // to use the new Chain.
7089 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7092 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7093 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7099 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7100 /// searches for and classifies those shifts.
7101 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7103 if (N.getOpcode() == ISD::SHL)
7105 else if (N.getOpcode() == ISD::SRL)
7110 if (!isa<ConstantSDNode>(N.getOperand(1)))
7113 ShiftAmount = N->getConstantOperandVal(1);
7114 Src = N->getOperand(0);
7118 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7119 /// registers viewed as a high/low pair. This function looks for the pattern:
7120 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7121 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7123 static SDValue tryCombineToEXTR(SDNode *N,
7124 TargetLowering::DAGCombinerInfo &DCI) {
7125 SelectionDAG &DAG = DCI.DAG;
7127 EVT VT = N->getValueType(0);
7129 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7131 if (VT != MVT::i32 && VT != MVT::i64)
7135 uint32_t ShiftLHS = 0;
7137 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7141 uint32_t ShiftRHS = 0;
7143 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7146 // If they're both trying to come from the high part of the register, they're
7147 // not really an EXTR.
7148 if (LHSFromHi == RHSFromHi)
7151 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7155 std::swap(LHS, RHS);
7156 std::swap(ShiftLHS, ShiftRHS);
7159 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7160 DAG.getConstant(ShiftRHS, MVT::i64));
7163 static SDValue tryCombineToBSL(SDNode *N,
7164 TargetLowering::DAGCombinerInfo &DCI) {
7165 EVT VT = N->getValueType(0);
7166 SelectionDAG &DAG = DCI.DAG;
7172 SDValue N0 = N->getOperand(0);
7173 if (N0.getOpcode() != ISD::AND)
7176 SDValue N1 = N->getOperand(1);
7177 if (N1.getOpcode() != ISD::AND)
7180 // We only have to look for constant vectors here since the general, variable
7181 // case can be handled in TableGen.
7182 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7183 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7184 for (int i = 1; i >= 0; --i)
7185 for (int j = 1; j >= 0; --j) {
7186 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7187 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7191 bool FoundMatch = true;
7192 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7193 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7194 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7196 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7203 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7204 N0->getOperand(1 - i), N1->getOperand(1 - j));
7210 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7211 const AArch64Subtarget *Subtarget) {
7212 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7213 if (!EnableAArch64ExtrGeneration)
7215 SelectionDAG &DAG = DCI.DAG;
7216 EVT VT = N->getValueType(0);
7218 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7221 SDValue Res = tryCombineToEXTR(N, DCI);
7225 Res = tryCombineToBSL(N, DCI);
7232 static SDValue performBitcastCombine(SDNode *N,
7233 TargetLowering::DAGCombinerInfo &DCI,
7234 SelectionDAG &DAG) {
7235 // Wait 'til after everything is legalized to try this. That way we have
7236 // legal vector types and such.
7237 if (DCI.isBeforeLegalizeOps())
7240 // Remove extraneous bitcasts around an extract_subvector.
7242 // (v4i16 (bitconvert
7243 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7245 // (extract_subvector ((v8i16 ...), (i64 4)))
7247 // Only interested in 64-bit vectors as the ultimate result.
7248 EVT VT = N->getValueType(0);
7251 if (VT.getSimpleVT().getSizeInBits() != 64)
7253 // Is the operand an extract_subvector starting at the beginning or halfway
7254 // point of the vector? A low half may also come through as an
7255 // EXTRACT_SUBREG, so look for that, too.
7256 SDValue Op0 = N->getOperand(0);
7257 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7258 !(Op0->isMachineOpcode() &&
7259 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7261 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7262 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7263 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7265 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7266 if (idx != AArch64::dsub)
7268 // The dsub reference is equivalent to a lane zero subvector reference.
7271 // Look through the bitcast of the input to the extract.
7272 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7274 SDValue Source = Op0->getOperand(0)->getOperand(0);
7275 // If the source type has twice the number of elements as our destination
7276 // type, we know this is an extract of the high or low half of the vector.
7277 EVT SVT = Source->getValueType(0);
7278 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7281 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7283 // Create the simplified form to just extract the low or high half of the
7284 // vector directly rather than bothering with the bitcasts.
7286 unsigned NumElements = VT.getVectorNumElements();
7288 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
7289 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7291 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
7292 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7298 static SDValue performConcatVectorsCombine(SDNode *N,
7299 TargetLowering::DAGCombinerInfo &DCI,
7300 SelectionDAG &DAG) {
7302 EVT VT = N->getValueType(0);
7303 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7305 // Optimize concat_vectors of truncated vectors, where the intermediate
7306 // type is illegal, to avoid said illegality, e.g.,
7307 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7308 // (v2i16 (truncate (v2i64)))))
7310 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7311 // (v4i32 (bitcast (v2i64))),
7313 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7314 // on both input and result type, so we might generate worse code.
7315 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7316 if (N->getNumOperands() == 2 &&
7317 N0->getOpcode() == ISD::TRUNCATE &&
7318 N1->getOpcode() == ISD::TRUNCATE) {
7319 SDValue N00 = N0->getOperand(0);
7320 SDValue N10 = N1->getOperand(0);
7321 EVT N00VT = N00.getValueType();
7323 if (N00VT == N10.getValueType() &&
7324 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7325 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7326 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7327 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7328 for (size_t i = 0; i < Mask.size(); ++i)
7330 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7331 DAG.getVectorShuffle(
7333 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7334 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7338 // Wait 'til after everything is legalized to try this. That way we have
7339 // legal vector types and such.
7340 if (DCI.isBeforeLegalizeOps())
7343 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7344 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7345 // canonicalise to that.
7346 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7347 assert(VT.getVectorElementType().getSizeInBits() == 64);
7348 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7349 DAG.getConstant(0, MVT::i64));
7352 // Canonicalise concat_vectors so that the right-hand vector has as few
7353 // bit-casts as possible before its real operation. The primary matching
7354 // destination for these operations will be the narrowing "2" instructions,
7355 // which depend on the operation being performed on this right-hand vector.
7357 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7359 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7361 if (N1->getOpcode() != ISD::BITCAST)
7363 SDValue RHS = N1->getOperand(0);
7364 MVT RHSTy = RHS.getValueType().getSimpleVT();
7365 // If the RHS is not a vector, this is not the pattern we're looking for.
7366 if (!RHSTy.isVector())
7369 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7371 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7372 RHSTy.getVectorNumElements() * 2);
7373 return DAG.getNode(ISD::BITCAST, dl, VT,
7374 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7375 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7379 static SDValue tryCombineFixedPointConvert(SDNode *N,
7380 TargetLowering::DAGCombinerInfo &DCI,
7381 SelectionDAG &DAG) {
7382 // Wait 'til after everything is legalized to try this. That way we have
7383 // legal vector types and such.
7384 if (DCI.isBeforeLegalizeOps())
7386 // Transform a scalar conversion of a value from a lane extract into a
7387 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7388 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7389 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7391 // The second form interacts better with instruction selection and the
7392 // register allocator to avoid cross-class register copies that aren't
7393 // coalescable due to a lane reference.
7395 // Check the operand and see if it originates from a lane extract.
7396 SDValue Op1 = N->getOperand(1);
7397 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7398 // Yep, no additional predication needed. Perform the transform.
7399 SDValue IID = N->getOperand(0);
7400 SDValue Shift = N->getOperand(2);
7401 SDValue Vec = Op1.getOperand(0);
7402 SDValue Lane = Op1.getOperand(1);
7403 EVT ResTy = N->getValueType(0);
7407 // The vector width should be 128 bits by the time we get here, even
7408 // if it started as 64 bits (the extract_vector handling will have
7410 assert(Vec.getValueType().getSizeInBits() == 128 &&
7411 "unexpected vector size on extract_vector_elt!");
7412 if (Vec.getValueType() == MVT::v4i32)
7413 VecResTy = MVT::v4f32;
7414 else if (Vec.getValueType() == MVT::v2i64)
7415 VecResTy = MVT::v2f64;
7417 llvm_unreachable("unexpected vector type!");
7420 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7421 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7426 // AArch64 high-vector "long" operations are formed by performing the non-high
7427 // version on an extract_subvector of each operand which gets the high half:
7429 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7431 // However, there are cases which don't have an extract_high explicitly, but
7432 // have another operation that can be made compatible with one for free. For
7435 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7437 // This routine does the actual conversion of such DUPs, once outer routines
7438 // have determined that everything else is in order.
7439 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7440 // We can handle most types of duplicate, but the lane ones have an extra
7441 // operand saying *which* lane, so we need to know.
7443 switch (N.getOpcode()) {
7444 case AArch64ISD::DUP:
7447 case AArch64ISD::DUPLANE8:
7448 case AArch64ISD::DUPLANE16:
7449 case AArch64ISD::DUPLANE32:
7450 case AArch64ISD::DUPLANE64:
7457 MVT NarrowTy = N.getSimpleValueType();
7458 if (!NarrowTy.is64BitVector())
7461 MVT ElementTy = NarrowTy.getVectorElementType();
7462 unsigned NumElems = NarrowTy.getVectorNumElements();
7463 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7467 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7470 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7472 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7473 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7476 static bool isEssentiallyExtractSubvector(SDValue N) {
7477 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7480 return N.getOpcode() == ISD::BITCAST &&
7481 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7484 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7485 struct GenericSetCCInfo {
7486 const SDValue *Opnd0;
7487 const SDValue *Opnd1;
7491 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7492 struct AArch64SetCCInfo {
7494 AArch64CC::CondCode CC;
7497 /// \brief Helper structure to keep track of SetCC information.
7499 GenericSetCCInfo Generic;
7500 AArch64SetCCInfo AArch64;
7503 /// \brief Helper structure to be able to read SetCC information. If set to
7504 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7505 /// GenericSetCCInfo.
7506 struct SetCCInfoAndKind {
7511 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7513 /// AArch64 lowered one.
7514 /// \p SetCCInfo is filled accordingly.
7515 /// \post SetCCInfo is meanginfull only when this function returns true.
7516 /// \return True when Op is a kind of SET_CC operation.
7517 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7518 // If this is a setcc, this is straight forward.
7519 if (Op.getOpcode() == ISD::SETCC) {
7520 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7521 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7522 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7523 SetCCInfo.IsAArch64 = false;
7526 // Otherwise, check if this is a matching csel instruction.
7530 if (Op.getOpcode() != AArch64ISD::CSEL)
7532 // Set the information about the operands.
7533 // TODO: we want the operands of the Cmp not the csel
7534 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7535 SetCCInfo.IsAArch64 = true;
7536 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7537 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7539 // Check that the operands matches the constraints:
7540 // (1) Both operands must be constants.
7541 // (2) One must be 1 and the other must be 0.
7542 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7543 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7546 if (!TValue || !FValue)
7550 if (!TValue->isOne()) {
7551 // Update the comparison when we are interested in !cc.
7552 std::swap(TValue, FValue);
7553 SetCCInfo.Info.AArch64.CC =
7554 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7556 return TValue->isOne() && FValue->isNullValue();
7559 // Returns true if Op is setcc or zext of setcc.
7560 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7561 if (isSetCC(Op, Info))
7563 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7564 isSetCC(Op->getOperand(0), Info));
7567 // The folding we want to perform is:
7568 // (add x, [zext] (setcc cc ...) )
7570 // (csel x, (add x, 1), !cc ...)
7572 // The latter will get matched to a CSINC instruction.
7573 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7574 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7575 SDValue LHS = Op->getOperand(0);
7576 SDValue RHS = Op->getOperand(1);
7577 SetCCInfoAndKind InfoAndKind;
7579 // If neither operand is a SET_CC, give up.
7580 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7581 std::swap(LHS, RHS);
7582 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7586 // FIXME: This could be generatized to work for FP comparisons.
7587 EVT CmpVT = InfoAndKind.IsAArch64
7588 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7589 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7590 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7596 if (InfoAndKind.IsAArch64) {
7597 CCVal = DAG.getConstant(
7598 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7599 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7601 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7602 *InfoAndKind.Info.Generic.Opnd1,
7603 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7606 EVT VT = Op->getValueType(0);
7607 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7608 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7611 // The basic add/sub long vector instructions have variants with "2" on the end
7612 // which act on the high-half of their inputs. They are normally matched by
7615 // (add (zeroext (extract_high LHS)),
7616 // (zeroext (extract_high RHS)))
7617 // -> uaddl2 vD, vN, vM
7619 // However, if one of the extracts is something like a duplicate, this
7620 // instruction can still be used profitably. This function puts the DAG into a
7621 // more appropriate form for those patterns to trigger.
7622 static SDValue performAddSubLongCombine(SDNode *N,
7623 TargetLowering::DAGCombinerInfo &DCI,
7624 SelectionDAG &DAG) {
7625 if (DCI.isBeforeLegalizeOps())
7628 MVT VT = N->getSimpleValueType(0);
7629 if (!VT.is128BitVector()) {
7630 if (N->getOpcode() == ISD::ADD)
7631 return performSetccAddFolding(N, DAG);
7635 // Make sure both branches are extended in the same way.
7636 SDValue LHS = N->getOperand(0);
7637 SDValue RHS = N->getOperand(1);
7638 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7639 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7640 LHS.getOpcode() != RHS.getOpcode())
7643 unsigned ExtType = LHS.getOpcode();
7645 // It's not worth doing if at least one of the inputs isn't already an
7646 // extract, but we don't know which it'll be so we have to try both.
7647 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7648 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7652 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7653 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7654 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7658 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7661 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7664 // Massage DAGs which we can use the high-half "long" operations on into
7665 // something isel will recognize better. E.g.
7667 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7668 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7669 // (extract_high (v2i64 (dup128 scalar)))))
7671 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7672 TargetLowering::DAGCombinerInfo &DCI,
7673 SelectionDAG &DAG) {
7674 if (DCI.isBeforeLegalizeOps())
7677 SDValue LHS = N->getOperand(1);
7678 SDValue RHS = N->getOperand(2);
7679 assert(LHS.getValueType().is64BitVector() &&
7680 RHS.getValueType().is64BitVector() &&
7681 "unexpected shape for long operation");
7683 // Either node could be a DUP, but it's not worth doing both of them (you'd
7684 // just as well use the non-high version) so look for a corresponding extract
7685 // operation on the other "wing".
7686 if (isEssentiallyExtractSubvector(LHS)) {
7687 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7690 } else if (isEssentiallyExtractSubvector(RHS)) {
7691 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7696 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7697 N->getOperand(0), LHS, RHS);
7700 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7701 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7702 unsigned ElemBits = ElemTy.getSizeInBits();
7704 int64_t ShiftAmount;
7705 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7706 APInt SplatValue, SplatUndef;
7707 unsigned SplatBitSize;
7709 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7710 HasAnyUndefs, ElemBits) ||
7711 SplatBitSize != ElemBits)
7714 ShiftAmount = SplatValue.getSExtValue();
7715 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7716 ShiftAmount = CVN->getSExtValue();
7724 llvm_unreachable("Unknown shift intrinsic");
7725 case Intrinsic::aarch64_neon_sqshl:
7726 Opcode = AArch64ISD::SQSHL_I;
7727 IsRightShift = false;
7729 case Intrinsic::aarch64_neon_uqshl:
7730 Opcode = AArch64ISD::UQSHL_I;
7731 IsRightShift = false;
7733 case Intrinsic::aarch64_neon_srshl:
7734 Opcode = AArch64ISD::SRSHR_I;
7735 IsRightShift = true;
7737 case Intrinsic::aarch64_neon_urshl:
7738 Opcode = AArch64ISD::URSHR_I;
7739 IsRightShift = true;
7741 case Intrinsic::aarch64_neon_sqshlu:
7742 Opcode = AArch64ISD::SQSHLU_I;
7743 IsRightShift = false;
7747 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7748 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7749 DAG.getConstant(-ShiftAmount, MVT::i32));
7750 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7751 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7752 DAG.getConstant(ShiftAmount, MVT::i32));
7757 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7758 // the intrinsics must be legal and take an i32, this means there's almost
7759 // certainly going to be a zext in the DAG which we can eliminate.
7760 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7761 SDValue AndN = N->getOperand(2);
7762 if (AndN.getOpcode() != ISD::AND)
7765 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7766 if (!CMask || CMask->getZExtValue() != Mask)
7769 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7770 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7773 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
7774 SelectionDAG &DAG) {
7775 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), N->getValueType(0),
7776 DAG.getNode(Opc, SDLoc(N),
7777 N->getOperand(1).getSimpleValueType(),
7779 DAG.getConstant(0, MVT::i64));
7782 static SDValue performIntrinsicCombine(SDNode *N,
7783 TargetLowering::DAGCombinerInfo &DCI,
7784 const AArch64Subtarget *Subtarget) {
7785 SelectionDAG &DAG = DCI.DAG;
7786 unsigned IID = getIntrinsicID(N);
7790 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7791 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7792 return tryCombineFixedPointConvert(N, DCI, DAG);
7794 case Intrinsic::aarch64_neon_saddv:
7795 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
7796 case Intrinsic::aarch64_neon_uaddv:
7797 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
7798 case Intrinsic::aarch64_neon_sminv:
7799 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
7800 case Intrinsic::aarch64_neon_uminv:
7801 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
7802 case Intrinsic::aarch64_neon_smaxv:
7803 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
7804 case Intrinsic::aarch64_neon_umaxv:
7805 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
7806 case Intrinsic::aarch64_neon_fmax:
7807 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7808 N->getOperand(1), N->getOperand(2));
7809 case Intrinsic::aarch64_neon_fmin:
7810 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7811 N->getOperand(1), N->getOperand(2));
7812 case Intrinsic::aarch64_neon_smull:
7813 case Intrinsic::aarch64_neon_umull:
7814 case Intrinsic::aarch64_neon_pmull:
7815 case Intrinsic::aarch64_neon_sqdmull:
7816 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7817 case Intrinsic::aarch64_neon_sqshl:
7818 case Intrinsic::aarch64_neon_uqshl:
7819 case Intrinsic::aarch64_neon_sqshlu:
7820 case Intrinsic::aarch64_neon_srshl:
7821 case Intrinsic::aarch64_neon_urshl:
7822 return tryCombineShiftImm(IID, N, DAG);
7823 case Intrinsic::aarch64_crc32b:
7824 case Intrinsic::aarch64_crc32cb:
7825 return tryCombineCRC32(0xff, N, DAG);
7826 case Intrinsic::aarch64_crc32h:
7827 case Intrinsic::aarch64_crc32ch:
7828 return tryCombineCRC32(0xffff, N, DAG);
7833 static SDValue performExtendCombine(SDNode *N,
7834 TargetLowering::DAGCombinerInfo &DCI,
7835 SelectionDAG &DAG) {
7836 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7837 // we can convert that DUP into another extract_high (of a bigger DUP), which
7838 // helps the backend to decide that an sabdl2 would be useful, saving a real
7839 // extract_high operation.
7840 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7841 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7842 SDNode *ABDNode = N->getOperand(0).getNode();
7843 unsigned IID = getIntrinsicID(ABDNode);
7844 if (IID == Intrinsic::aarch64_neon_sabd ||
7845 IID == Intrinsic::aarch64_neon_uabd) {
7846 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7847 if (!NewABD.getNode())
7850 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7855 // This is effectively a custom type legalization for AArch64.
7857 // Type legalization will split an extend of a small, legal, type to a larger
7858 // illegal type by first splitting the destination type, often creating
7859 // illegal source types, which then get legalized in isel-confusing ways,
7860 // leading to really terrible codegen. E.g.,
7861 // %result = v8i32 sext v8i8 %value
7863 // %losrc = extract_subreg %value, ...
7864 // %hisrc = extract_subreg %value, ...
7865 // %lo = v4i32 sext v4i8 %losrc
7866 // %hi = v4i32 sext v4i8 %hisrc
7867 // Things go rapidly downhill from there.
7869 // For AArch64, the [sz]ext vector instructions can only go up one element
7870 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7871 // take two instructions.
7873 // This implies that the most efficient way to do the extend from v8i8
7874 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7875 // the normal splitting to happen for the v8i16->v8i32.
7877 // This is pre-legalization to catch some cases where the default
7878 // type legalization will create ill-tempered code.
7879 if (!DCI.isBeforeLegalizeOps())
7882 // We're only interested in cleaning things up for non-legal vector types
7883 // here. If both the source and destination are legal, things will just
7884 // work naturally without any fiddling.
7885 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7886 EVT ResVT = N->getValueType(0);
7887 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7889 // If the vector type isn't a simple VT, it's beyond the scope of what
7890 // we're worried about here. Let legalization do its thing and hope for
7892 SDValue Src = N->getOperand(0);
7893 EVT SrcVT = Src->getValueType(0);
7894 if (!ResVT.isSimple() || !SrcVT.isSimple())
7897 // If the source VT is a 64-bit vector, we can play games and get the
7898 // better results we want.
7899 if (SrcVT.getSizeInBits() != 64)
7902 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7903 unsigned ElementCount = SrcVT.getVectorNumElements();
7904 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7906 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7908 // Now split the rest of the operation into two halves, each with a 64
7912 unsigned NumElements = ResVT.getVectorNumElements();
7913 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7914 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7915 ResVT.getVectorElementType(), NumElements / 2);
7917 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7918 LoVT.getVectorNumElements());
7919 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7920 DAG.getConstant(0, MVT::i64));
7921 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7922 DAG.getConstant(InNVT.getVectorNumElements(), MVT::i64));
7923 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7924 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7926 // Now combine the parts back together so we still have a single result
7927 // like the combiner expects.
7928 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7931 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7932 /// value. The load store optimizer pass will merge them to store pair stores.
7933 /// This has better performance than a splat of the scalar followed by a split
7934 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7935 /// followed by an ext.b and two stores.
7936 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7937 SDValue StVal = St->getValue();
7938 EVT VT = StVal.getValueType();
7940 // Don't replace floating point stores, they possibly won't be transformed to
7941 // stp because of the store pair suppress pass.
7942 if (VT.isFloatingPoint())
7945 // Check for insert vector elements.
7946 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7949 // We can express a splat as store pair(s) for 2 or 4 elements.
7950 unsigned NumVecElts = VT.getVectorNumElements();
7951 if (NumVecElts != 4 && NumVecElts != 2)
7953 SDValue SplatVal = StVal.getOperand(1);
7954 unsigned RemainInsertElts = NumVecElts - 1;
7956 // Check that this is a splat.
7957 while (--RemainInsertElts) {
7958 SDValue NextInsertElt = StVal.getOperand(0);
7959 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7961 if (NextInsertElt.getOperand(1) != SplatVal)
7963 StVal = NextInsertElt;
7965 unsigned OrigAlignment = St->getAlignment();
7966 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7967 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7969 // Create scalar stores. This is at least as good as the code sequence for a
7970 // split unaligned store wich is a dup.s, ext.b, and two stores.
7971 // Most of the time the three stores should be replaced by store pair
7972 // instructions (stp).
7974 SDValue BasePtr = St->getBasePtr();
7976 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7977 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7979 unsigned Offset = EltOffset;
7980 while (--NumVecElts) {
7981 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7982 DAG.getConstant(Offset, MVT::i64));
7983 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7984 St->getPointerInfo(), St->isVolatile(),
7985 St->isNonTemporal(), Alignment);
7986 Offset += EltOffset;
7991 static SDValue performSTORECombine(SDNode *N,
7992 TargetLowering::DAGCombinerInfo &DCI,
7994 const AArch64Subtarget *Subtarget) {
7995 if (!DCI.isBeforeLegalize())
7998 StoreSDNode *S = cast<StoreSDNode>(N);
7999 if (S->isVolatile())
8002 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8003 // page boundaries. We want to split such stores.
8004 if (!Subtarget->isCyclone())
8007 // Don't split at Oz.
8008 MachineFunction &MF = DAG.getMachineFunction();
8009 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
8013 SDValue StVal = S->getValue();
8014 EVT VT = StVal.getValueType();
8016 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8017 // those up regresses performance on micro-benchmarks and olden/bh.
8018 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8021 // Split unaligned 16B stores. They are terrible for performance.
8022 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8023 // extensions can use this to mark that it does not want splitting to happen
8024 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8025 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8026 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8027 S->getAlignment() <= 2)
8030 // If we get a splat of a scalar convert this vector store to a store of
8031 // scalars. They will be merged into store pairs thereby removing two
8033 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
8034 if (ReplacedSplat != SDValue())
8035 return ReplacedSplat;
8038 unsigned NumElts = VT.getVectorNumElements() / 2;
8039 // Split VT into two.
8041 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8042 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8043 DAG.getConstant(0, MVT::i64));
8044 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8045 DAG.getConstant(NumElts, MVT::i64));
8046 SDValue BasePtr = S->getBasePtr();
8048 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8049 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8050 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8051 DAG.getConstant(8, MVT::i64));
8052 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8053 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8057 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8058 /// post-increment LD1R.
8059 static SDValue performPostLD1Combine(SDNode *N,
8060 TargetLowering::DAGCombinerInfo &DCI,
8062 if (DCI.isBeforeLegalizeOps())
8065 SelectionDAG &DAG = DCI.DAG;
8066 EVT VT = N->getValueType(0);
8068 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8069 SDNode *LD = N->getOperand(LoadIdx).getNode();
8070 // If it is not LOAD, can not do such combine.
8071 if (LD->getOpcode() != ISD::LOAD)
8074 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8075 EVT MemVT = LoadSDN->getMemoryVT();
8076 // Check if memory operand is the same type as the vector element.
8077 if (MemVT != VT.getVectorElementType())
8080 // Check if there are other uses. If so, do not combine as it will introduce
8082 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8084 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8090 SDValue Addr = LD->getOperand(1);
8091 SDValue Vector = N->getOperand(0);
8092 // Search for a use of the address operand that is an increment.
8093 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8094 Addr.getNode()->use_end(); UI != UE; ++UI) {
8096 if (User->getOpcode() != ISD::ADD
8097 || UI.getUse().getResNo() != Addr.getResNo())
8100 // Check that the add is independent of the load. Otherwise, folding it
8101 // would create a cycle.
8102 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8104 // Also check that add is not used in the vector operand. This would also
8106 if (User->isPredecessorOf(Vector.getNode()))
8109 // If the increment is a constant, it must match the memory ref size.
8110 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8111 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8112 uint32_t IncVal = CInc->getZExtValue();
8113 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8114 if (IncVal != NumBytes)
8116 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8119 SmallVector<SDValue, 8> Ops;
8120 Ops.push_back(LD->getOperand(0)); // Chain
8122 Ops.push_back(Vector); // The vector to be inserted
8123 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8125 Ops.push_back(Addr);
8128 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8129 SDVTList SDTys = DAG.getVTList(Tys);
8130 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8131 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8133 LoadSDN->getMemOperand());
8136 SmallVector<SDValue, 2> NewResults;
8137 NewResults.push_back(SDValue(LD, 0)); // The result of load
8138 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8139 DCI.CombineTo(LD, NewResults);
8140 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8141 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8148 /// Target-specific DAG combine function for NEON load/store intrinsics
8149 /// to merge base address updates.
8150 static SDValue performNEONPostLDSTCombine(SDNode *N,
8151 TargetLowering::DAGCombinerInfo &DCI,
8152 SelectionDAG &DAG) {
8153 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8156 unsigned AddrOpIdx = N->getNumOperands() - 1;
8157 SDValue Addr = N->getOperand(AddrOpIdx);
8159 // Search for a use of the address operand that is an increment.
8160 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8161 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8163 if (User->getOpcode() != ISD::ADD ||
8164 UI.getUse().getResNo() != Addr.getResNo())
8167 // Check that the add is independent of the load/store. Otherwise, folding
8168 // it would create a cycle.
8169 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8172 // Find the new opcode for the updating load/store.
8173 bool IsStore = false;
8174 bool IsLaneOp = false;
8175 bool IsDupOp = false;
8176 unsigned NewOpc = 0;
8177 unsigned NumVecs = 0;
8178 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8180 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8181 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8183 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8185 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8187 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8188 NumVecs = 2; IsStore = true; break;
8189 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8190 NumVecs = 3; IsStore = true; break;
8191 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8192 NumVecs = 4; IsStore = true; break;
8193 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8195 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8197 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8199 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8200 NumVecs = 2; IsStore = true; break;
8201 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8202 NumVecs = 3; IsStore = true; break;
8203 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8204 NumVecs = 4; IsStore = true; break;
8205 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8206 NumVecs = 2; IsDupOp = true; break;
8207 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8208 NumVecs = 3; IsDupOp = true; break;
8209 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8210 NumVecs = 4; IsDupOp = true; break;
8211 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8212 NumVecs = 2; IsLaneOp = true; break;
8213 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8214 NumVecs = 3; IsLaneOp = true; break;
8215 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8216 NumVecs = 4; IsLaneOp = true; break;
8217 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8218 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8219 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8220 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8221 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8222 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8227 VecTy = N->getOperand(2).getValueType();
8229 VecTy = N->getValueType(0);
8231 // If the increment is a constant, it must match the memory ref size.
8232 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8233 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8234 uint32_t IncVal = CInc->getZExtValue();
8235 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8236 if (IsLaneOp || IsDupOp)
8237 NumBytes /= VecTy.getVectorNumElements();
8238 if (IncVal != NumBytes)
8240 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8242 SmallVector<SDValue, 8> Ops;
8243 Ops.push_back(N->getOperand(0)); // Incoming chain
8244 // Load lane and store have vector list as input.
8245 if (IsLaneOp || IsStore)
8246 for (unsigned i = 2; i < AddrOpIdx; ++i)
8247 Ops.push_back(N->getOperand(i));
8248 Ops.push_back(Addr); // Base register
8253 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8255 for (n = 0; n < NumResultVecs; ++n)
8257 Tys[n++] = MVT::i64; // Type of write back register
8258 Tys[n] = MVT::Other; // Type of the chain
8259 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8261 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8262 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8263 MemInt->getMemoryVT(),
8264 MemInt->getMemOperand());
8267 std::vector<SDValue> NewResults;
8268 for (unsigned i = 0; i < NumResultVecs; ++i) {
8269 NewResults.push_back(SDValue(UpdN.getNode(), i));
8271 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8272 DCI.CombineTo(N, NewResults);
8273 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8280 // Checks to see if the value is the prescribed width and returns information
8281 // about its extension mode.
8283 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8284 ExtType = ISD::NON_EXTLOAD;
8285 switch(V.getNode()->getOpcode()) {
8289 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8290 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8291 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8292 ExtType = LoadNode->getExtensionType();
8297 case ISD::AssertSext: {
8298 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8299 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8300 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8301 ExtType = ISD::SEXTLOAD;
8306 case ISD::AssertZext: {
8307 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8308 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8309 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8310 ExtType = ISD::ZEXTLOAD;
8316 case ISD::TargetConstant: {
8317 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8327 // This function does a whole lot of voodoo to determine if the tests are
8328 // equivalent without and with a mask. Essentially what happens is that given a
8331 // +-------------+ +-------------+ +-------------+ +-------------+
8332 // | Input | | AddConstant | | CompConstant| | CC |
8333 // +-------------+ +-------------+ +-------------+ +-------------+
8335 // V V | +----------+
8336 // +-------------+ +----+ | |
8337 // | ADD | |0xff| | |
8338 // +-------------+ +----+ | |
8341 // +-------------+ | |
8343 // +-------------+ | |
8352 // The AND node may be safely removed for some combinations of inputs. In
8353 // particular we need to take into account the extension type of the Input,
8354 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8355 // width of the input (this can work for any width inputs, the above graph is
8356 // specific to 8 bits.
8358 // The specific equations were worked out by generating output tables for each
8359 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8360 // problem was simplified by working with 4 bit inputs, which means we only
8361 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8362 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8363 // patterns present in both extensions (0,7). For every distinct set of
8364 // AddConstant and CompConstants bit patterns we can consider the masked and
8365 // unmasked versions to be equivalent if the result of this function is true for
8366 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8369 // and w10, w8, #0x0f
8371 // cset w9, AArch64CC
8373 // cset w11, AArch64CC
8378 // Since the above function shows when the outputs are equivalent it defines
8379 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8380 // would be expensive to run during compiles. The equations below were written
8381 // in a test harness that confirmed they gave equivalent outputs to the above
8382 // for all inputs function, so they can be used determine if the removal is
8385 // isEquivalentMaskless() is the code for testing if the AND can be removed
8386 // factored out of the DAG recognition as the DAG can take several forms.
8389 bool isEquivalentMaskless(unsigned CC, unsigned width,
8390 ISD::LoadExtType ExtType, signed AddConstant,
8391 signed CompConstant) {
8392 // By being careful about our equations and only writing the in term
8393 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8394 // make them generally applicable to all bit widths.
8395 signed MaxUInt = (1 << width);
8397 // For the purposes of these comparisons sign extending the type is
8398 // equivalent to zero extending the add and displacing it by half the integer
8399 // width. Provided we are careful and make sure our equations are valid over
8400 // the whole range we can just adjust the input and avoid writing equations
8401 // for sign extended inputs.
8402 if (ExtType == ISD::SEXTLOAD)
8403 AddConstant -= (1 << (width-1));
8407 case AArch64CC::GT: {
8408 if ((AddConstant == 0) ||
8409 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8410 (AddConstant >= 0 && CompConstant < 0) ||
8411 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8415 case AArch64CC::GE: {
8416 if ((AddConstant == 0) ||
8417 (AddConstant >= 0 && CompConstant <= 0) ||
8418 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8422 case AArch64CC::LS: {
8423 if ((AddConstant >= 0 && CompConstant < 0) ||
8424 (AddConstant <= 0 && CompConstant >= -1 &&
8425 CompConstant < AddConstant + MaxUInt))
8429 case AArch64CC::MI: {
8430 if ((AddConstant == 0) ||
8431 (AddConstant > 0 && CompConstant <= 0) ||
8432 (AddConstant < 0 && CompConstant <= AddConstant))
8436 case AArch64CC::HS: {
8437 if ((AddConstant >= 0 && CompConstant <= 0) ||
8438 (AddConstant <= 0 && CompConstant >= 0 &&
8439 CompConstant <= AddConstant + MaxUInt))
8443 case AArch64CC::NE: {
8444 if ((AddConstant > 0 && CompConstant < 0) ||
8445 (AddConstant < 0 && CompConstant >= 0 &&
8446 CompConstant < AddConstant + MaxUInt) ||
8447 (AddConstant >= 0 && CompConstant >= 0 &&
8448 CompConstant >= AddConstant) ||
8449 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8458 case AArch64CC::Invalid:
8466 SDValue performCONDCombine(SDNode *N,
8467 TargetLowering::DAGCombinerInfo &DCI,
8468 SelectionDAG &DAG, unsigned CCIndex,
8469 unsigned CmpIndex) {
8470 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8471 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8472 unsigned CondOpcode = SubsNode->getOpcode();
8474 if (CondOpcode != AArch64ISD::SUBS)
8477 // There is a SUBS feeding this condition. Is it fed by a mask we can
8480 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8481 unsigned MaskBits = 0;
8483 if (AndNode->getOpcode() != ISD::AND)
8486 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8487 uint32_t CNV = CN->getZExtValue();
8490 else if (CNV == 65535)
8497 SDValue AddValue = AndNode->getOperand(0);
8499 if (AddValue.getOpcode() != ISD::ADD)
8502 // The basic dag structure is correct, grab the inputs and validate them.
8504 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8505 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8506 SDValue SubsInputValue = SubsNode->getOperand(1);
8508 // The mask is present and the provenance of all the values is a smaller type,
8509 // lets see if the mask is superfluous.
8511 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8512 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8515 ISD::LoadExtType ExtType;
8517 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8518 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8519 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8522 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8523 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8524 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8527 // The AND is not necessary, remove it.
8529 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8530 SubsNode->getValueType(1));
8531 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8533 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8534 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8536 return SDValue(N, 0);
8539 // Optimize compare with zero and branch.
8540 static SDValue performBRCONDCombine(SDNode *N,
8541 TargetLowering::DAGCombinerInfo &DCI,
8542 SelectionDAG &DAG) {
8543 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8546 SDValue Chain = N->getOperand(0);
8547 SDValue Dest = N->getOperand(1);
8548 SDValue CCVal = N->getOperand(2);
8549 SDValue Cmp = N->getOperand(3);
8551 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8552 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8553 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8556 unsigned CmpOpc = Cmp.getOpcode();
8557 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8560 // Only attempt folding if there is only one use of the flag and no use of the
8562 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8565 SDValue LHS = Cmp.getOperand(0);
8566 SDValue RHS = Cmp.getOperand(1);
8568 assert(LHS.getValueType() == RHS.getValueType() &&
8569 "Expected the value type to be the same for both operands!");
8570 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8573 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8574 std::swap(LHS, RHS);
8576 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8579 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8580 LHS.getOpcode() == ISD::SRL)
8583 // Fold the compare into the branch instruction.
8585 if (CC == AArch64CC::EQ)
8586 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8588 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8590 // Do not add new nodes to DAG combiner worklist.
8591 DCI.CombineTo(N, BR, false);
8596 // vselect (v1i1 setcc) ->
8597 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8598 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8599 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8601 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8602 SDValue N0 = N->getOperand(0);
8603 EVT CCVT = N0.getValueType();
8605 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8606 CCVT.getVectorElementType() != MVT::i1)
8609 EVT ResVT = N->getValueType(0);
8610 EVT CmpVT = N0.getOperand(0).getValueType();
8611 // Only combine when the result type is of the same size as the compared
8613 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8616 SDValue IfTrue = N->getOperand(1);
8617 SDValue IfFalse = N->getOperand(2);
8619 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8620 N0.getOperand(0), N0.getOperand(1),
8621 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8622 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8626 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8627 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8628 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8629 /// with a vector one followed by a DUP shuffle on the result.
8630 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
8631 SDValue N0 = N->getOperand(0);
8632 EVT ResVT = N->getValueType(0);
8634 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8637 // If NumMaskElts == 0, the comparison is larger than select result. The
8638 // largest real NEON comparison is 64-bits per lane, which means the result is
8639 // at most 32-bits and an illegal vector. Just bail out for now.
8640 EVT SrcVT = N0.getOperand(0).getValueType();
8642 // Don't try to do this optimization when the setcc itself has i1 operands.
8643 // There are no legal vectors of i1, so this would be pointless.
8644 if (SrcVT == MVT::i1)
8647 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8648 if (!ResVT.isVector() || NumMaskElts == 0)
8651 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8652 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8654 // First perform a vector comparison, where lane 0 is the one we're interested
8658 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8660 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8661 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8663 // Now duplicate the comparison mask we want across all other lanes.
8664 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8665 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8666 Mask = DAG.getNode(ISD::BITCAST, DL,
8667 ResVT.changeVectorElementTypeToInteger(), Mask);
8669 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8672 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8673 DAGCombinerInfo &DCI) const {
8674 SelectionDAG &DAG = DCI.DAG;
8675 switch (N->getOpcode()) {
8680 return performAddSubLongCombine(N, DCI, DAG);
8682 return performXorCombine(N, DAG, DCI, Subtarget);
8684 return performMulCombine(N, DAG, DCI, Subtarget);
8685 case ISD::SINT_TO_FP:
8686 case ISD::UINT_TO_FP:
8687 return performIntToFpCombine(N, DAG, Subtarget);
8689 return performORCombine(N, DCI, Subtarget);
8690 case ISD::INTRINSIC_WO_CHAIN:
8691 return performIntrinsicCombine(N, DCI, Subtarget);
8692 case ISD::ANY_EXTEND:
8693 case ISD::ZERO_EXTEND:
8694 case ISD::SIGN_EXTEND:
8695 return performExtendCombine(N, DCI, DAG);
8697 return performBitcastCombine(N, DCI, DAG);
8698 case ISD::CONCAT_VECTORS:
8699 return performConcatVectorsCombine(N, DCI, DAG);
8701 return performSelectCombine(N, DAG);
8703 return performVSelectCombine(N, DCI.DAG);
8705 return performSTORECombine(N, DCI, DAG, Subtarget);
8706 case AArch64ISD::BRCOND:
8707 return performBRCONDCombine(N, DCI, DAG);
8708 case AArch64ISD::CSEL:
8709 return performCONDCombine(N, DCI, DAG, 2, 3);
8710 case AArch64ISD::DUP:
8711 return performPostLD1Combine(N, DCI, false);
8712 case ISD::INSERT_VECTOR_ELT:
8713 return performPostLD1Combine(N, DCI, true);
8714 case ISD::INTRINSIC_VOID:
8715 case ISD::INTRINSIC_W_CHAIN:
8716 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8717 case Intrinsic::aarch64_neon_ld2:
8718 case Intrinsic::aarch64_neon_ld3:
8719 case Intrinsic::aarch64_neon_ld4:
8720 case Intrinsic::aarch64_neon_ld1x2:
8721 case Intrinsic::aarch64_neon_ld1x3:
8722 case Intrinsic::aarch64_neon_ld1x4:
8723 case Intrinsic::aarch64_neon_ld2lane:
8724 case Intrinsic::aarch64_neon_ld3lane:
8725 case Intrinsic::aarch64_neon_ld4lane:
8726 case Intrinsic::aarch64_neon_ld2r:
8727 case Intrinsic::aarch64_neon_ld3r:
8728 case Intrinsic::aarch64_neon_ld4r:
8729 case Intrinsic::aarch64_neon_st2:
8730 case Intrinsic::aarch64_neon_st3:
8731 case Intrinsic::aarch64_neon_st4:
8732 case Intrinsic::aarch64_neon_st1x2:
8733 case Intrinsic::aarch64_neon_st1x3:
8734 case Intrinsic::aarch64_neon_st1x4:
8735 case Intrinsic::aarch64_neon_st2lane:
8736 case Intrinsic::aarch64_neon_st3lane:
8737 case Intrinsic::aarch64_neon_st4lane:
8738 return performNEONPostLDSTCombine(N, DCI, DAG);
8746 // Check if the return value is used as only a return value, as otherwise
8747 // we can't perform a tail-call. In particular, we need to check for
8748 // target ISD nodes that are returns and any other "odd" constructs
8749 // that the generic analysis code won't necessarily catch.
8750 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8751 SDValue &Chain) const {
8752 if (N->getNumValues() != 1)
8754 if (!N->hasNUsesOfValue(1, 0))
8757 SDValue TCChain = Chain;
8758 SDNode *Copy = *N->use_begin();
8759 if (Copy->getOpcode() == ISD::CopyToReg) {
8760 // If the copy has a glue operand, we conservatively assume it isn't safe to
8761 // perform a tail call.
8762 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8765 TCChain = Copy->getOperand(0);
8766 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8769 bool HasRet = false;
8770 for (SDNode *Node : Copy->uses()) {
8771 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8783 // Return whether the an instruction can potentially be optimized to a tail
8784 // call. This will cause the optimizers to attempt to move, or duplicate,
8785 // return instructions to help enable tail call optimizations for this
8787 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8788 if (!CI->isTailCall())
8794 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8796 ISD::MemIndexedMode &AM,
8798 SelectionDAG &DAG) const {
8799 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8802 Base = Op->getOperand(0);
8803 // All of the indexed addressing mode instructions take a signed
8804 // 9 bit immediate offset.
8805 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8806 int64_t RHSC = (int64_t)RHS->getZExtValue();
8807 if (RHSC >= 256 || RHSC <= -256)
8809 IsInc = (Op->getOpcode() == ISD::ADD);
8810 Offset = Op->getOperand(1);
8816 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8818 ISD::MemIndexedMode &AM,
8819 SelectionDAG &DAG) const {
8822 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8823 VT = LD->getMemoryVT();
8824 Ptr = LD->getBasePtr();
8825 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8826 VT = ST->getMemoryVT();
8827 Ptr = ST->getBasePtr();
8832 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8834 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8838 bool AArch64TargetLowering::getPostIndexedAddressParts(
8839 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8840 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8843 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8844 VT = LD->getMemoryVT();
8845 Ptr = LD->getBasePtr();
8846 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8847 VT = ST->getMemoryVT();
8848 Ptr = ST->getBasePtr();
8853 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8855 // Post-indexing updates the base, so it's not a valid transform
8856 // if that's not the same as the load's pointer.
8859 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8863 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8864 SelectionDAG &DAG) {
8866 SDValue Op = N->getOperand(0);
8868 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
8872 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8873 DAG.getUNDEF(MVT::i32), Op,
8874 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8876 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8877 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8880 void AArch64TargetLowering::ReplaceNodeResults(
8881 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8882 switch (N->getOpcode()) {
8884 llvm_unreachable("Don't know how to custom expand this");
8886 ReplaceBITCASTResults(N, Results, DAG);
8888 case ISD::FP_TO_UINT:
8889 case ISD::FP_TO_SINT:
8890 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8891 // Let normal code take care of it by not adding anything to Results.
8896 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8900 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8901 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8902 // reciprocal if there are three or more FDIVs.
8903 return NumUsers > 2;
8906 TargetLoweringBase::LegalizeTypeAction
8907 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8908 MVT SVT = VT.getSimpleVT();
8909 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8910 // v4i16, v2i32 instead of to promote.
8911 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8912 || SVT == MVT::v1f32)
8913 return TypeWidenVector;
8915 return TargetLoweringBase::getPreferredVectorAction(VT);
8918 // Loads and stores less than 128-bits are already atomic; ones above that
8919 // are doomed anyway, so defer to the default libcall and blame the OS when
8921 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
8922 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8926 // Loads and stores less than 128-bits are already atomic; ones above that
8927 // are doomed anyway, so defer to the default libcall and blame the OS when
8929 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
8930 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8934 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
8935 TargetLoweringBase::AtomicRMWExpansionKind
8936 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
8937 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
8938 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
8939 : AtomicRMWExpansionKind::None;
8942 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
8946 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8947 AtomicOrdering Ord) const {
8948 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8949 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8950 bool IsAcquire = isAtLeastAcquire(Ord);
8952 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8953 // intrinsic must return {i64, i64} and we have to recombine them into a
8954 // single i128 here.
8955 if (ValTy->getPrimitiveSizeInBits() == 128) {
8957 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8958 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8960 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8961 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8963 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8964 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8965 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8966 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8967 return Builder.CreateOr(
8968 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8971 Type *Tys[] = { Addr->getType() };
8973 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8974 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8976 return Builder.CreateTruncOrBitCast(
8977 Builder.CreateCall(Ldxr, Addr),
8978 cast<PointerType>(Addr->getType())->getElementType());
8981 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8982 Value *Val, Value *Addr,
8983 AtomicOrdering Ord) const {
8984 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8985 bool IsRelease = isAtLeastRelease(Ord);
8987 // Since the intrinsics must have legal type, the i128 intrinsics take two
8988 // parameters: "i64, i64". We must marshal Val into the appropriate form
8990 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8992 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8993 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8994 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8996 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8997 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8998 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8999 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
9003 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9004 Type *Tys[] = { Addr->getType() };
9005 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9007 return Builder.CreateCall2(
9008 Stxr, Builder.CreateZExtOrBitCast(
9009 Val, Stxr->getFunctionType()->getParamType(0)),
9013 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9014 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9015 return Ty->isArrayTy();