1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64CallingConvention.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64PerfectShuffle.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "MCTargetDesc/AArch64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "aarch64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
49 static cl::opt<AlignMode>
50 Align(cl::desc("Load/store alignment support"),
51 cl::Hidden, cl::init(NoStrictAlign),
53 clEnumValN(StrictAlign, "aarch64-strict-align",
54 "Disallow all unaligned memory accesses"),
55 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
56 "Allow unaligned memory accesses"),
59 // Place holder until extr generation is tested fully.
61 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
62 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
66 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
67 cl::desc("Allow AArch64 SLI/SRI formation"),
70 // FIXME: The necessary dtprel relocations don't seem to be supported
71 // well in the GNU bfd and gold linkers at the moment. Therefore, by
72 // default, for now, fall back to GeneralDynamic code generation.
73 cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
74 "aarch64-elf-ldtls-generation", cl::Hidden,
75 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
78 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
79 const AArch64Subtarget &STI)
80 : TargetLowering(TM), Subtarget(&STI) {
82 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
83 // we have to make something up. Arbitrarily, choose ZeroOrOne.
84 setBooleanContents(ZeroOrOneBooleanContent);
85 // When comparing vectors the result sets the different elements in the
86 // vector to all-one or all-zero.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // Set up the register classes.
90 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
91 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
93 if (Subtarget->hasFPARMv8()) {
94 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
95 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
96 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
97 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
100 if (Subtarget->hasNEON()) {
101 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
102 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
103 // Someone set us up the NEON.
104 addDRTypeForNEON(MVT::v2f32);
105 addDRTypeForNEON(MVT::v8i8);
106 addDRTypeForNEON(MVT::v4i16);
107 addDRTypeForNEON(MVT::v2i32);
108 addDRTypeForNEON(MVT::v1i64);
109 addDRTypeForNEON(MVT::v1f64);
110 addDRTypeForNEON(MVT::v4f16);
112 addQRTypeForNEON(MVT::v4f32);
113 addQRTypeForNEON(MVT::v2f64);
114 addQRTypeForNEON(MVT::v16i8);
115 addQRTypeForNEON(MVT::v8i16);
116 addQRTypeForNEON(MVT::v4i32);
117 addQRTypeForNEON(MVT::v2i64);
118 addQRTypeForNEON(MVT::v8f16);
121 // Compute derived properties from the register classes
122 computeRegisterProperties(Subtarget->getRegisterInfo());
124 // Provide all sorts of operation actions
125 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
126 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 setOperationAction(ISD::SETCC, MVT::i64, Custom);
129 setOperationAction(ISD::SETCC, MVT::f32, Custom);
130 setOperationAction(ISD::SETCC, MVT::f64, Custom);
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
132 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
134 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
135 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
136 setOperationAction(ISD::SELECT, MVT::i32, Custom);
137 setOperationAction(ISD::SELECT, MVT::i64, Custom);
138 setOperationAction(ISD::SELECT, MVT::f32, Custom);
139 setOperationAction(ISD::SELECT, MVT::f64, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
143 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
145 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
147 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
151 setOperationAction(ISD::FREM, MVT::f32, Expand);
152 setOperationAction(ISD::FREM, MVT::f64, Expand);
153 setOperationAction(ISD::FREM, MVT::f80, Expand);
155 // Custom lowering hooks are needed for XOR
156 // to fold it into CSINC/CSINV.
157 setOperationAction(ISD::XOR, MVT::i32, Custom);
158 setOperationAction(ISD::XOR, MVT::i64, Custom);
160 // Virtually no operation on f128 is legal, but LLVM can't expand them when
161 // there's a valid register class, so we need custom operations in most cases.
162 setOperationAction(ISD::FABS, MVT::f128, Expand);
163 setOperationAction(ISD::FADD, MVT::f128, Custom);
164 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
165 setOperationAction(ISD::FCOS, MVT::f128, Expand);
166 setOperationAction(ISD::FDIV, MVT::f128, Custom);
167 setOperationAction(ISD::FMA, MVT::f128, Expand);
168 setOperationAction(ISD::FMUL, MVT::f128, Custom);
169 setOperationAction(ISD::FNEG, MVT::f128, Expand);
170 setOperationAction(ISD::FPOW, MVT::f128, Expand);
171 setOperationAction(ISD::FREM, MVT::f128, Expand);
172 setOperationAction(ISD::FRINT, MVT::f128, Expand);
173 setOperationAction(ISD::FSIN, MVT::f128, Expand);
174 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
175 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
176 setOperationAction(ISD::FSUB, MVT::f128, Custom);
177 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
178 setOperationAction(ISD::SETCC, MVT::f128, Custom);
179 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
180 setOperationAction(ISD::SELECT, MVT::f128, Custom);
181 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
182 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
184 // Lowering for many of the conversions is actually specified by the non-f128
185 // type. The LowerXXX function will be trivial when f128 isn't involved.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
191 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
192 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
197 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
198 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
199 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
201 // Variable arguments.
202 setOperationAction(ISD::VASTART, MVT::Other, Custom);
203 setOperationAction(ISD::VAARG, MVT::Other, Custom);
204 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
205 setOperationAction(ISD::VAEND, MVT::Other, Expand);
207 // Variable-sized objects.
208 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
209 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
210 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
212 // Exception handling.
213 // FIXME: These are guesses. Has this been defined yet?
214 setExceptionPointerRegister(AArch64::X0);
215 setExceptionSelectorRegister(AArch64::X1);
217 // Constant pool entries
218 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
221 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
223 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
224 setOperationAction(ISD::ADDC, MVT::i32, Custom);
225 setOperationAction(ISD::ADDE, MVT::i32, Custom);
226 setOperationAction(ISD::SUBC, MVT::i32, Custom);
227 setOperationAction(ISD::SUBE, MVT::i32, Custom);
228 setOperationAction(ISD::ADDC, MVT::i64, Custom);
229 setOperationAction(ISD::ADDE, MVT::i64, Custom);
230 setOperationAction(ISD::SUBC, MVT::i64, Custom);
231 setOperationAction(ISD::SUBE, MVT::i64, Custom);
233 // AArch64 lacks both left-rotate and popcount instructions.
234 setOperationAction(ISD::ROTL, MVT::i32, Expand);
235 setOperationAction(ISD::ROTL, MVT::i64, Expand);
237 // AArch64 doesn't have {U|S}MUL_LOHI.
238 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
239 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
242 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
243 // counterparts, which AArch64 supports directly.
244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
245 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
247 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
249 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
250 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
252 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
253 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
254 setOperationAction(ISD::SREM, MVT::i32, Expand);
255 setOperationAction(ISD::SREM, MVT::i64, Expand);
256 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
257 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
258 setOperationAction(ISD::UREM, MVT::i32, Expand);
259 setOperationAction(ISD::UREM, MVT::i64, Expand);
261 // Custom lower Add/Sub/Mul with overflow.
262 setOperationAction(ISD::SADDO, MVT::i32, Custom);
263 setOperationAction(ISD::SADDO, MVT::i64, Custom);
264 setOperationAction(ISD::UADDO, MVT::i32, Custom);
265 setOperationAction(ISD::UADDO, MVT::i64, Custom);
266 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
267 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
268 setOperationAction(ISD::USUBO, MVT::i32, Custom);
269 setOperationAction(ISD::USUBO, MVT::i64, Custom);
270 setOperationAction(ISD::SMULO, MVT::i32, Custom);
271 setOperationAction(ISD::SMULO, MVT::i64, Custom);
272 setOperationAction(ISD::UMULO, MVT::i32, Custom);
273 setOperationAction(ISD::UMULO, MVT::i64, Custom);
275 setOperationAction(ISD::FSIN, MVT::f32, Expand);
276 setOperationAction(ISD::FSIN, MVT::f64, Expand);
277 setOperationAction(ISD::FCOS, MVT::f32, Expand);
278 setOperationAction(ISD::FCOS, MVT::f64, Expand);
279 setOperationAction(ISD::FPOW, MVT::f32, Expand);
280 setOperationAction(ISD::FPOW, MVT::f64, Expand);
281 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
284 // f16 is a storage-only type, always promote it to f32.
285 setOperationAction(ISD::SETCC, MVT::f16, Promote);
286 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
287 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
288 setOperationAction(ISD::SELECT, MVT::f16, Promote);
289 setOperationAction(ISD::FADD, MVT::f16, Promote);
290 setOperationAction(ISD::FSUB, MVT::f16, Promote);
291 setOperationAction(ISD::FMUL, MVT::f16, Promote);
292 setOperationAction(ISD::FDIV, MVT::f16, Promote);
293 setOperationAction(ISD::FREM, MVT::f16, Promote);
294 setOperationAction(ISD::FMA, MVT::f16, Promote);
295 setOperationAction(ISD::FNEG, MVT::f16, Promote);
296 setOperationAction(ISD::FABS, MVT::f16, Promote);
297 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
298 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
299 setOperationAction(ISD::FCOS, MVT::f16, Promote);
300 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
301 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
302 setOperationAction(ISD::FPOW, MVT::f16, Promote);
303 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
304 setOperationAction(ISD::FRINT, MVT::f16, Promote);
305 setOperationAction(ISD::FSIN, MVT::f16, Promote);
306 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
307 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
308 setOperationAction(ISD::FEXP, MVT::f16, Promote);
309 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
310 setOperationAction(ISD::FLOG, MVT::f16, Promote);
311 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
312 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
313 setOperationAction(ISD::FROUND, MVT::f16, Promote);
314 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
315 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
316 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
318 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
320 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
321 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
322 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
323 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
324 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
325 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
326 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
327 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
328 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
329 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
330 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
331 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
333 // Expand all other v4f16 operations.
334 // FIXME: We could generate better code by promoting some operations to
336 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
337 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
338 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
339 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
340 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
341 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
342 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
343 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
344 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
345 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
346 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
347 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
348 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
349 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
350 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
351 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
352 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
353 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
354 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
355 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
356 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
357 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
358 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
359 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
360 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
361 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
364 // v8f16 is also a storage-only type, so expand it.
365 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
366 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
367 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
368 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
369 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
370 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
371 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
372 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
373 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
374 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
375 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
376 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
377 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
378 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
379 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
380 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
381 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
382 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
383 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
384 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
385 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
386 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
387 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
388 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
389 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
390 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
391 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
392 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
393 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
394 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
395 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
397 // AArch64 has implementations of a lot of rounding-like FP operations.
398 for (MVT Ty : {MVT::f32, MVT::f64}) {
399 setOperationAction(ISD::FFLOOR, Ty, Legal);
400 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
401 setOperationAction(ISD::FCEIL, Ty, Legal);
402 setOperationAction(ISD::FRINT, Ty, Legal);
403 setOperationAction(ISD::FTRUNC, Ty, Legal);
404 setOperationAction(ISD::FROUND, Ty, Legal);
407 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
409 if (Subtarget->isTargetMachO()) {
410 // For iOS, we don't want to the normal expansion of a libcall to
411 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
413 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
414 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
416 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
417 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
420 // Make floating-point constants legal for the large code model, so they don't
421 // become loads from the constant pool.
422 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
423 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
424 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
427 // AArch64 does not have floating-point extending loads, i1 sign-extending
428 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
429 for (MVT VT : MVT::fp_valuetypes()) {
430 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
435 for (MVT VT : MVT::integer_valuetypes())
436 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
438 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
439 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
440 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
441 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
442 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
443 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
444 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
446 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
447 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
449 // Indexed loads and stores are supported.
450 for (unsigned im = (unsigned)ISD::PRE_INC;
451 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
452 setIndexedLoadAction(im, MVT::i8, Legal);
453 setIndexedLoadAction(im, MVT::i16, Legal);
454 setIndexedLoadAction(im, MVT::i32, Legal);
455 setIndexedLoadAction(im, MVT::i64, Legal);
456 setIndexedLoadAction(im, MVT::f64, Legal);
457 setIndexedLoadAction(im, MVT::f32, Legal);
458 setIndexedStoreAction(im, MVT::i8, Legal);
459 setIndexedStoreAction(im, MVT::i16, Legal);
460 setIndexedStoreAction(im, MVT::i32, Legal);
461 setIndexedStoreAction(im, MVT::i64, Legal);
462 setIndexedStoreAction(im, MVT::f64, Legal);
463 setIndexedStoreAction(im, MVT::f32, Legal);
467 setOperationAction(ISD::TRAP, MVT::Other, Legal);
469 // We combine OR nodes for bitfield operations.
470 setTargetDAGCombine(ISD::OR);
472 // Vector add and sub nodes may conceal a high-half opportunity.
473 // Also, try to fold ADD into CSINC/CSINV..
474 setTargetDAGCombine(ISD::ADD);
475 setTargetDAGCombine(ISD::SUB);
477 setTargetDAGCombine(ISD::XOR);
478 setTargetDAGCombine(ISD::SINT_TO_FP);
479 setTargetDAGCombine(ISD::UINT_TO_FP);
481 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
483 setTargetDAGCombine(ISD::ANY_EXTEND);
484 setTargetDAGCombine(ISD::ZERO_EXTEND);
485 setTargetDAGCombine(ISD::SIGN_EXTEND);
486 setTargetDAGCombine(ISD::BITCAST);
487 setTargetDAGCombine(ISD::CONCAT_VECTORS);
488 setTargetDAGCombine(ISD::STORE);
490 setTargetDAGCombine(ISD::MUL);
492 setTargetDAGCombine(ISD::SELECT);
493 setTargetDAGCombine(ISD::VSELECT);
494 setTargetDAGCombine(ISD::SELECT_CC);
496 setTargetDAGCombine(ISD::INTRINSIC_VOID);
497 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
498 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
500 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
501 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
502 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
504 setStackPointerRegisterToSaveRestore(AArch64::SP);
506 setSchedulingPreference(Sched::Hybrid);
509 MaskAndBranchFoldingIsLegal = true;
510 EnableExtLdPromotion = true;
512 setMinFunctionAlignment(2);
514 RequireStrictAlign = (Align == StrictAlign);
516 setHasExtractBitsInsn(true);
518 if (Subtarget->hasNEON()) {
519 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
520 // silliness like this:
521 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
522 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
523 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
524 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
525 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
526 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
527 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
528 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
529 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
530 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
531 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
532 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
533 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
534 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
535 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
536 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
537 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
538 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
539 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
540 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
541 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
542 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
543 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
544 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
545 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
547 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
548 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
549 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
550 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
551 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
553 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
555 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
556 // elements smaller than i32, so promote the input to i32 first.
557 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
558 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
559 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
560 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
561 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
562 // -> v8f16 conversions.
563 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
564 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
565 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
566 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
567 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
568 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
569 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
570 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
571 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
572 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
573 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
574 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
575 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
577 // AArch64 doesn't have MUL.2d:
578 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
579 // Custom handling for some quad-vector types to detect MULL.
580 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
581 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
582 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
584 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
585 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
586 // Likewise, narrowing and extending vector loads/stores aren't handled
588 for (MVT VT : MVT::vector_valuetypes()) {
589 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
591 setOperationAction(ISD::MULHS, VT, Expand);
592 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
593 setOperationAction(ISD::MULHU, VT, Expand);
594 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
596 setOperationAction(ISD::BSWAP, VT, Expand);
598 for (MVT InnerVT : MVT::vector_valuetypes()) {
599 setTruncStoreAction(VT, InnerVT, Expand);
600 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
601 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
602 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
606 // AArch64 has implementations of a lot of rounding-like FP operations.
607 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
608 setOperationAction(ISD::FFLOOR, Ty, Legal);
609 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
610 setOperationAction(ISD::FCEIL, Ty, Legal);
611 setOperationAction(ISD::FRINT, Ty, Legal);
612 setOperationAction(ISD::FTRUNC, Ty, Legal);
613 setOperationAction(ISD::FROUND, Ty, Legal);
617 // Prefer likely predicted branches to selects on out-of-order cores.
618 if (Subtarget->isCortexA57())
619 PredictableSelectIsExpensive = true;
622 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
623 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
624 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
625 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
627 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
628 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
629 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
630 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
631 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
633 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
634 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
637 // Mark vector float intrinsics as expand.
638 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
639 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
640 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
641 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
642 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
643 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
644 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
645 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
646 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
647 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
650 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
651 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
652 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
653 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
654 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
655 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
656 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
657 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
658 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
659 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
660 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
661 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
663 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
664 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
665 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
666 for (MVT InnerVT : MVT::all_valuetypes())
667 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand);
669 // CNT supports only B element sizes.
670 if (VT != MVT::v8i8 && VT != MVT::v16i8)
671 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
673 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
674 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
675 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
676 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
677 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
679 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
680 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
682 if (Subtarget->isLittleEndian()) {
683 for (unsigned im = (unsigned)ISD::PRE_INC;
684 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
685 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
686 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
691 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
692 addRegisterClass(VT, &AArch64::FPR64RegClass);
693 addTypeForNEON(VT, MVT::v2i32);
696 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
697 addRegisterClass(VT, &AArch64::FPR128RegClass);
698 addTypeForNEON(VT, MVT::v4i32);
701 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
704 return VT.changeVectorElementTypeToInteger();
707 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
708 /// Mask are known to be either zero or one and return them in the
709 /// KnownZero/KnownOne bitsets.
710 void AArch64TargetLowering::computeKnownBitsForTargetNode(
711 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
712 const SelectionDAG &DAG, unsigned Depth) const {
713 switch (Op.getOpcode()) {
716 case AArch64ISD::CSEL: {
717 APInt KnownZero2, KnownOne2;
718 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
719 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
720 KnownZero &= KnownZero2;
721 KnownOne &= KnownOne2;
724 case ISD::INTRINSIC_W_CHAIN: {
725 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
726 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
729 case Intrinsic::aarch64_ldaxr:
730 case Intrinsic::aarch64_ldxr: {
731 unsigned BitWidth = KnownOne.getBitWidth();
732 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
733 unsigned MemBits = VT.getScalarType().getSizeInBits();
734 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
740 case ISD::INTRINSIC_WO_CHAIN:
741 case ISD::INTRINSIC_VOID: {
742 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
746 case Intrinsic::aarch64_neon_umaxv:
747 case Intrinsic::aarch64_neon_uminv: {
748 // Figure out the datatype of the vector operand. The UMINV instruction
749 // will zero extend the result, so we can mark as known zero all the
750 // bits larger than the element datatype. 32-bit or larget doesn't need
751 // this as those are legal types and will be handled by isel directly.
752 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
753 unsigned BitWidth = KnownZero.getBitWidth();
754 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
755 assert(BitWidth >= 8 && "Unexpected width!");
756 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
758 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
759 assert(BitWidth >= 16 && "Unexpected width!");
760 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
770 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
775 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
776 const TargetLibraryInfo *libInfo) const {
777 return AArch64::createFastISel(funcInfo, libInfo);
780 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
781 switch ((AArch64ISD::NodeType)Opcode) {
782 case AArch64ISD::FIRST_NUMBER: break;
783 case AArch64ISD::CALL: return "AArch64ISD::CALL";
784 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
785 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
786 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
787 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
788 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
789 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
790 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
791 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
792 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
793 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
794 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
795 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
796 case AArch64ISD::ADC: return "AArch64ISD::ADC";
797 case AArch64ISD::SBC: return "AArch64ISD::SBC";
798 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
799 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
800 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
801 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
802 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
803 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
804 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
805 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
806 case AArch64ISD::DUP: return "AArch64ISD::DUP";
807 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
808 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
809 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
810 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
811 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
812 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
813 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
814 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
815 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
816 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
817 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
818 case AArch64ISD::BICi: return "AArch64ISD::BICi";
819 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
820 case AArch64ISD::BSL: return "AArch64ISD::BSL";
821 case AArch64ISD::NEG: return "AArch64ISD::NEG";
822 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
823 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
824 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
825 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
826 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
827 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
828 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
829 case AArch64ISD::REV16: return "AArch64ISD::REV16";
830 case AArch64ISD::REV32: return "AArch64ISD::REV32";
831 case AArch64ISD::REV64: return "AArch64ISD::REV64";
832 case AArch64ISD::EXT: return "AArch64ISD::EXT";
833 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
834 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
835 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
836 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
837 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
838 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
839 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
840 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
841 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
842 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
843 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
844 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
845 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
846 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
847 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
848 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
849 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
850 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
851 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
852 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
853 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
854 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
855 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
856 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
857 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
858 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
859 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
860 case AArch64ISD::NOT: return "AArch64ISD::NOT";
861 case AArch64ISD::BIT: return "AArch64ISD::BIT";
862 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
863 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
864 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
865 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
866 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
867 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
868 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
869 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
870 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
871 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
872 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
873 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
874 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
875 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
876 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
877 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
878 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
879 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
880 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
881 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
882 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
883 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
884 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
885 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
886 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
887 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
888 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
889 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
890 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
891 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
892 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
893 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
894 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
895 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
896 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
897 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
898 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
899 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
900 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
901 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
907 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
908 MachineBasicBlock *MBB) const {
909 // We materialise the F128CSEL pseudo-instruction as some control flow and a
913 // [... previous instrs leading to comparison ...]
919 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
921 MachineFunction *MF = MBB->getParent();
922 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
923 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
924 DebugLoc DL = MI->getDebugLoc();
925 MachineFunction::iterator It = MBB;
928 unsigned DestReg = MI->getOperand(0).getReg();
929 unsigned IfTrueReg = MI->getOperand(1).getReg();
930 unsigned IfFalseReg = MI->getOperand(2).getReg();
931 unsigned CondCode = MI->getOperand(3).getImm();
932 bool NZCVKilled = MI->getOperand(4).isKill();
934 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
935 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
936 MF->insert(It, TrueBB);
937 MF->insert(It, EndBB);
939 // Transfer rest of current basic-block to EndBB
940 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
942 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
944 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
945 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
946 MBB->addSuccessor(TrueBB);
947 MBB->addSuccessor(EndBB);
949 // TrueBB falls through to the end.
950 TrueBB->addSuccessor(EndBB);
953 TrueBB->addLiveIn(AArch64::NZCV);
954 EndBB->addLiveIn(AArch64::NZCV);
957 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
963 MI->eraseFromParent();
968 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
969 MachineBasicBlock *BB) const {
970 switch (MI->getOpcode()) {
975 llvm_unreachable("Unexpected instruction for custom inserter!");
977 case AArch64::F128CSEL:
978 return EmitF128CSEL(MI, BB);
980 case TargetOpcode::STACKMAP:
981 case TargetOpcode::PATCHPOINT:
982 return emitPatchPoint(MI, BB);
986 //===----------------------------------------------------------------------===//
987 // AArch64 Lowering private implementation.
988 //===----------------------------------------------------------------------===//
990 //===----------------------------------------------------------------------===//
992 //===----------------------------------------------------------------------===//
994 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
996 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
999 llvm_unreachable("Unknown condition code!");
1001 return AArch64CC::NE;
1003 return AArch64CC::EQ;
1005 return AArch64CC::GT;
1007 return AArch64CC::GE;
1009 return AArch64CC::LT;
1011 return AArch64CC::LE;
1013 return AArch64CC::HI;
1015 return AArch64CC::HS;
1017 return AArch64CC::LO;
1019 return AArch64CC::LS;
1023 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1024 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1025 AArch64CC::CondCode &CondCode,
1026 AArch64CC::CondCode &CondCode2) {
1027 CondCode2 = AArch64CC::AL;
1030 llvm_unreachable("Unknown FP condition!");
1033 CondCode = AArch64CC::EQ;
1037 CondCode = AArch64CC::GT;
1041 CondCode = AArch64CC::GE;
1044 CondCode = AArch64CC::MI;
1047 CondCode = AArch64CC::LS;
1050 CondCode = AArch64CC::MI;
1051 CondCode2 = AArch64CC::GT;
1054 CondCode = AArch64CC::VC;
1057 CondCode = AArch64CC::VS;
1060 CondCode = AArch64CC::EQ;
1061 CondCode2 = AArch64CC::VS;
1064 CondCode = AArch64CC::HI;
1067 CondCode = AArch64CC::PL;
1071 CondCode = AArch64CC::LT;
1075 CondCode = AArch64CC::LE;
1079 CondCode = AArch64CC::NE;
1084 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1085 /// CC usable with the vector instructions. Fewer operations are available
1086 /// without a real NZCV register, so we have to use less efficient combinations
1087 /// to get the same effect.
1088 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1089 AArch64CC::CondCode &CondCode,
1090 AArch64CC::CondCode &CondCode2,
1095 // Mostly the scalar mappings work fine.
1096 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1099 Invert = true; // Fallthrough
1101 CondCode = AArch64CC::MI;
1102 CondCode2 = AArch64CC::GE;
1109 // All of the compare-mask comparisons are ordered, but we can switch
1110 // between the two by a double inversion. E.g. ULE == !OGT.
1112 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1117 static bool isLegalArithImmed(uint64_t C) {
1118 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1119 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1122 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1123 SDLoc dl, SelectionDAG &DAG) {
1124 EVT VT = LHS.getValueType();
1126 if (VT.isFloatingPoint())
1127 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1129 // The CMP instruction is just an alias for SUBS, and representing it as
1130 // SUBS means that it's possible to get CSE with subtract operations.
1131 // A later phase can perform the optimization of setting the destination
1132 // register to WZR/XZR if it ends up being unused.
1133 unsigned Opcode = AArch64ISD::SUBS;
1135 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1136 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1137 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1138 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1139 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1140 // can be set differently by this operation. It comes down to whether
1141 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1142 // everything is fine. If not then the optimization is wrong. Thus general
1143 // comparisons are only valid if op2 != 0.
1145 // So, finally, the only LLVM-native comparisons that don't mention C and V
1146 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1147 // the absence of information about op2.
1148 Opcode = AArch64ISD::ADDS;
1149 RHS = RHS.getOperand(1);
1150 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1151 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1152 !isUnsignedIntSetCC(CC)) {
1153 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1154 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1155 // of the signed comparisons.
1156 Opcode = AArch64ISD::ANDS;
1157 RHS = LHS.getOperand(1);
1158 LHS = LHS.getOperand(0);
1161 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1165 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1166 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1168 AArch64CC::CondCode AArch64CC;
1169 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1170 EVT VT = RHS.getValueType();
1171 uint64_t C = RHSC->getZExtValue();
1172 if (!isLegalArithImmed(C)) {
1173 // Constant does not fit, try adjusting it by one?
1179 if ((VT == MVT::i32 && C != 0x80000000 &&
1180 isLegalArithImmed((uint32_t)(C - 1))) ||
1181 (VT == MVT::i64 && C != 0x80000000ULL &&
1182 isLegalArithImmed(C - 1ULL))) {
1183 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1184 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1185 RHS = DAG.getConstant(C, dl, VT);
1190 if ((VT == MVT::i32 && C != 0 &&
1191 isLegalArithImmed((uint32_t)(C - 1))) ||
1192 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1193 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1194 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1195 RHS = DAG.getConstant(C, dl, VT);
1200 if ((VT == MVT::i32 && C != INT32_MAX &&
1201 isLegalArithImmed((uint32_t)(C + 1))) ||
1202 (VT == MVT::i64 && C != INT64_MAX &&
1203 isLegalArithImmed(C + 1ULL))) {
1204 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1205 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1206 RHS = DAG.getConstant(C, dl, VT);
1211 if ((VT == MVT::i32 && C != UINT32_MAX &&
1212 isLegalArithImmed((uint32_t)(C + 1))) ||
1213 (VT == MVT::i64 && C != UINT64_MAX &&
1214 isLegalArithImmed(C + 1ULL))) {
1215 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1216 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1217 RHS = DAG.getConstant(C, dl, VT);
1223 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1224 // For the i8 operand, the largest immediate is 255, so this can be easily
1225 // encoded in the compare instruction. For the i16 operand, however, the
1226 // largest immediate cannot be encoded in the compare.
1227 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1228 // constant. For example,
1230 // ldrh w0, [x0, #0]
1233 // ldrsh w0, [x0, #0]
1235 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1236 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1237 // both the LHS and RHS are truely zero extended and to make sure the
1238 // transformation is profitable.
1239 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1240 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1241 isa<LoadSDNode>(LHS)) {
1242 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1243 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1244 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1245 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1246 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1248 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1249 DAG.getValueType(MVT::i16));
1250 Cmp = emitComparison(SExt,
1251 DAG.getConstant(ValueofRHS, dl,
1252 RHS.getValueType()),
1254 AArch64CC = changeIntCCToAArch64CC(CC);
1255 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
1261 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1262 AArch64CC = changeIntCCToAArch64CC(CC);
1263 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
1267 static std::pair<SDValue, SDValue>
1268 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1269 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1270 "Unsupported value type");
1271 SDValue Value, Overflow;
1273 SDValue LHS = Op.getOperand(0);
1274 SDValue RHS = Op.getOperand(1);
1276 switch (Op.getOpcode()) {
1278 llvm_unreachable("Unknown overflow instruction!");
1280 Opc = AArch64ISD::ADDS;
1284 Opc = AArch64ISD::ADDS;
1288 Opc = AArch64ISD::SUBS;
1292 Opc = AArch64ISD::SUBS;
1295 // Multiply needs a little bit extra work.
1299 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1300 if (Op.getValueType() == MVT::i32) {
1301 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1302 // For a 32 bit multiply with overflow check we want the instruction
1303 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1304 // need to generate the following pattern:
1305 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1306 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1307 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1308 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1309 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1310 DAG.getConstant(0, DL, MVT::i64));
1311 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1312 // operation. We need to clear out the upper 32 bits, because we used a
1313 // widening multiply that wrote all 64 bits. In the end this should be a
1315 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1317 // The signed overflow check requires more than just a simple check for
1318 // any bit set in the upper 32 bits of the result. These bits could be
1319 // just the sign bits of a negative number. To perform the overflow
1320 // check we have to arithmetic shift right the 32nd bit of the result by
1321 // 31 bits. Then we compare the result to the upper 32 bits.
1322 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1323 DAG.getConstant(32, DL, MVT::i64));
1324 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1325 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1326 DAG.getConstant(31, DL, MVT::i64));
1327 // It is important that LowerBits is last, otherwise the arithmetic
1328 // shift will not be folded into the compare (SUBS).
1329 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1330 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1333 // The overflow check for unsigned multiply is easy. We only need to
1334 // check if any of the upper 32 bits are set. This can be done with a
1335 // CMP (shifted register). For that we need to generate the following
1337 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1338 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1339 DAG.getConstant(32, DL, MVT::i64));
1340 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1342 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1343 DAG.getConstant(0, DL, MVT::i64),
1344 UpperBits).getValue(1);
1348 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1349 // For the 64 bit multiply
1350 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1352 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1353 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1354 DAG.getConstant(63, DL, MVT::i64));
1355 // It is important that LowerBits is last, otherwise the arithmetic
1356 // shift will not be folded into the compare (SUBS).
1357 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1358 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1361 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1362 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1364 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1365 DAG.getConstant(0, DL, MVT::i64),
1366 UpperBits).getValue(1);
1373 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1375 // Emit the AArch64 operation with overflow check.
1376 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1377 Overflow = Value.getValue(1);
1379 return std::make_pair(Value, Overflow);
1382 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1383 RTLIB::Libcall Call) const {
1384 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1385 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1389 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1390 SDValue Sel = Op.getOperand(0);
1391 SDValue Other = Op.getOperand(1);
1393 // If neither operand is a SELECT_CC, give up.
1394 if (Sel.getOpcode() != ISD::SELECT_CC)
1395 std::swap(Sel, Other);
1396 if (Sel.getOpcode() != ISD::SELECT_CC)
1399 // The folding we want to perform is:
1400 // (xor x, (select_cc a, b, cc, 0, -1) )
1402 // (csel x, (xor x, -1), cc ...)
1404 // The latter will get matched to a CSINV instruction.
1406 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1407 SDValue LHS = Sel.getOperand(0);
1408 SDValue RHS = Sel.getOperand(1);
1409 SDValue TVal = Sel.getOperand(2);
1410 SDValue FVal = Sel.getOperand(3);
1413 // FIXME: This could be generalized to non-integer comparisons.
1414 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1417 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1418 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1420 // The the values aren't constants, this isn't the pattern we're looking for.
1421 if (!CFVal || !CTVal)
1424 // We can commute the SELECT_CC by inverting the condition. This
1425 // might be needed to make this fit into a CSINV pattern.
1426 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1427 std::swap(TVal, FVal);
1428 std::swap(CTVal, CFVal);
1429 CC = ISD::getSetCCInverse(CC, true);
1432 // If the constants line up, perform the transform!
1433 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1435 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1438 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1439 DAG.getConstant(-1ULL, dl, Other.getValueType()));
1441 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1448 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1449 EVT VT = Op.getValueType();
1451 // Let legalize expand this if it isn't a legal type yet.
1452 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1455 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1458 bool ExtraOp = false;
1459 switch (Op.getOpcode()) {
1461 llvm_unreachable("Invalid code");
1463 Opc = AArch64ISD::ADDS;
1466 Opc = AArch64ISD::SUBS;
1469 Opc = AArch64ISD::ADCS;
1473 Opc = AArch64ISD::SBCS;
1479 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1480 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1484 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1485 // Let legalize expand this if it isn't a legal type yet.
1486 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1490 AArch64CC::CondCode CC;
1491 // The actual operation that sets the overflow or carry flag.
1492 SDValue Value, Overflow;
1493 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1495 // We use 0 and 1 as false and true values.
1496 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1497 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
1499 // We use an inverted condition, because the conditional select is inverted
1500 // too. This will allow it to be selected to a single instruction:
1501 // CSINC Wd, WZR, WZR, invert(cond).
1502 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
1503 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
1506 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1507 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
1510 // Prefetch operands are:
1511 // 1: Address to prefetch
1513 // 3: int locality (0 = no locality ... 3 = extreme locality)
1514 // 4: bool isDataCache
1515 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1517 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1518 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1519 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1521 bool IsStream = !Locality;
1522 // When the locality number is set
1524 // The front-end should have filtered out the out-of-range values
1525 assert(Locality <= 3 && "Prefetch locality out-of-range");
1526 // The locality degree is the opposite of the cache speed.
1527 // Put the number the other way around.
1528 // The encoding starts at 0 for level 1
1529 Locality = 3 - Locality;
1532 // built the mask value encoding the expected behavior.
1533 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1534 (!IsData << 3) | // IsDataCache bit
1535 (Locality << 1) | // Cache level bits
1536 (unsigned)IsStream; // Stream bit
1537 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1538 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
1541 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1542 SelectionDAG &DAG) const {
1543 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1546 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1548 return LowerF128Call(Op, DAG, LC);
1551 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1552 SelectionDAG &DAG) const {
1553 if (Op.getOperand(0).getValueType() != MVT::f128) {
1554 // It's legal except when f128 is involved
1559 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1561 // FP_ROUND node has a second operand indicating whether it is known to be
1562 // precise. That doesn't take part in the LibCall so we can't directly use
1564 SDValue SrcVal = Op.getOperand(0);
1565 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1566 /*isSigned*/ false, SDLoc(Op)).first;
1569 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1570 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1571 // Any additional optimization in this function should be recorded
1572 // in the cost tables.
1573 EVT InVT = Op.getOperand(0).getValueType();
1574 EVT VT = Op.getValueType();
1576 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1579 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1581 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1584 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1587 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1588 VT.getVectorNumElements());
1589 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1590 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1593 // Type changing conversions are illegal.
1597 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1598 SelectionDAG &DAG) const {
1599 if (Op.getOperand(0).getValueType().isVector())
1600 return LowerVectorFP_TO_INT(Op, DAG);
1602 // f16 conversions are promoted to f32.
1603 if (Op.getOperand(0).getValueType() == MVT::f16) {
1606 Op.getOpcode(), dl, Op.getValueType(),
1607 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
1610 if (Op.getOperand(0).getValueType() != MVT::f128) {
1611 // It's legal except when f128 is involved
1616 if (Op.getOpcode() == ISD::FP_TO_SINT)
1617 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1619 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1621 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1622 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1626 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1627 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1628 // Any additional optimization in this function should be recorded
1629 // in the cost tables.
1630 EVT VT = Op.getValueType();
1632 SDValue In = Op.getOperand(0);
1633 EVT InVT = In.getValueType();
1635 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1637 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1638 InVT.getVectorNumElements());
1639 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1640 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
1643 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1645 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1646 EVT CastVT = VT.changeVectorElementTypeToInteger();
1647 In = DAG.getNode(CastOpc, dl, CastVT, In);
1648 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1654 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1655 SelectionDAG &DAG) const {
1656 if (Op.getValueType().isVector())
1657 return LowerVectorINT_TO_FP(Op, DAG);
1659 // f16 conversions are promoted to f32.
1660 if (Op.getValueType() == MVT::f16) {
1663 ISD::FP_ROUND, dl, MVT::f16,
1664 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
1665 DAG.getIntPtrConstant(0, dl));
1668 // i128 conversions are libcalls.
1669 if (Op.getOperand(0).getValueType() == MVT::i128)
1672 // Other conversions are legal, unless it's to the completely software-based
1674 if (Op.getValueType() != MVT::f128)
1678 if (Op.getOpcode() == ISD::SINT_TO_FP)
1679 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1681 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1683 return LowerF128Call(Op, DAG, LC);
1686 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1687 SelectionDAG &DAG) const {
1688 // For iOS, we want to call an alternative entry point: __sincos_stret,
1689 // which returns the values in two S / D registers.
1691 SDValue Arg = Op.getOperand(0);
1692 EVT ArgVT = Arg.getValueType();
1693 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1700 Entry.isSExt = false;
1701 Entry.isZExt = false;
1702 Args.push_back(Entry);
1704 const char *LibcallName =
1705 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1706 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1708 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1709 TargetLowering::CallLoweringInfo CLI(DAG);
1710 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1711 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1713 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1714 return CallResult.first;
1717 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1718 if (Op.getValueType() != MVT::f16)
1721 assert(Op.getOperand(0).getValueType() == MVT::i16);
1724 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1725 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1727 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1728 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
1732 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1733 if (OrigVT.getSizeInBits() >= 64)
1736 assert(OrigVT.isSimple() && "Expecting a simple value type");
1738 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1739 switch (OrigSimpleTy) {
1740 default: llvm_unreachable("Unexpected Vector Type");
1749 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1752 unsigned ExtOpcode) {
1753 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1754 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1755 // 64-bits we need to insert a new extension so that it will be 64-bits.
1756 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1757 if (OrigTy.getSizeInBits() >= 64)
1760 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1761 EVT NewVT = getExtensionTo64Bits(OrigTy);
1763 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1766 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1768 EVT VT = N->getValueType(0);
1770 if (N->getOpcode() != ISD::BUILD_VECTOR)
1773 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1774 SDNode *Elt = N->getOperand(i).getNode();
1775 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1776 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1777 unsigned HalfSize = EltSize / 2;
1779 if (!isIntN(HalfSize, C->getSExtValue()))
1782 if (!isUIntN(HalfSize, C->getZExtValue()))
1793 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1794 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1795 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1796 N->getOperand(0)->getValueType(0),
1800 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1801 EVT VT = N->getValueType(0);
1803 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1804 unsigned NumElts = VT.getVectorNumElements();
1805 MVT TruncVT = MVT::getIntegerVT(EltSize);
1806 SmallVector<SDValue, 8> Ops;
1807 for (unsigned i = 0; i != NumElts; ++i) {
1808 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1809 const APInt &CInt = C->getAPIntValue();
1810 // Element types smaller than 32 bits are not legal, so use i32 elements.
1811 // The values are implicitly truncated so sext vs. zext doesn't matter.
1812 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
1814 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1815 MVT::getVectorVT(TruncVT, NumElts), Ops);
1818 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1819 if (N->getOpcode() == ISD::SIGN_EXTEND)
1821 if (isExtendedBUILD_VECTOR(N, DAG, true))
1826 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1827 if (N->getOpcode() == ISD::ZERO_EXTEND)
1829 if (isExtendedBUILD_VECTOR(N, DAG, false))
1834 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1835 unsigned Opcode = N->getOpcode();
1836 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1837 SDNode *N0 = N->getOperand(0).getNode();
1838 SDNode *N1 = N->getOperand(1).getNode();
1839 return N0->hasOneUse() && N1->hasOneUse() &&
1840 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1845 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1846 unsigned Opcode = N->getOpcode();
1847 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1848 SDNode *N0 = N->getOperand(0).getNode();
1849 SDNode *N1 = N->getOperand(1).getNode();
1850 return N0->hasOneUse() && N1->hasOneUse() &&
1851 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1856 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1857 // Multiplications are only custom-lowered for 128-bit vectors so that
1858 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1859 EVT VT = Op.getValueType();
1860 assert(VT.is128BitVector() && VT.isInteger() &&
1861 "unexpected type for custom-lowering ISD::MUL");
1862 SDNode *N0 = Op.getOperand(0).getNode();
1863 SDNode *N1 = Op.getOperand(1).getNode();
1864 unsigned NewOpc = 0;
1866 bool isN0SExt = isSignExtended(N0, DAG);
1867 bool isN1SExt = isSignExtended(N1, DAG);
1868 if (isN0SExt && isN1SExt)
1869 NewOpc = AArch64ISD::SMULL;
1871 bool isN0ZExt = isZeroExtended(N0, DAG);
1872 bool isN1ZExt = isZeroExtended(N1, DAG);
1873 if (isN0ZExt && isN1ZExt)
1874 NewOpc = AArch64ISD::UMULL;
1875 else if (isN1SExt || isN1ZExt) {
1876 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1877 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1878 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1879 NewOpc = AArch64ISD::SMULL;
1881 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1882 NewOpc = AArch64ISD::UMULL;
1884 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1886 NewOpc = AArch64ISD::UMULL;
1892 if (VT == MVT::v2i64)
1893 // Fall through to expand this. It is not legal.
1896 // Other vector multiplications are legal.
1901 // Legalize to a S/UMULL instruction
1904 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1906 Op0 = skipExtensionForVectorMULL(N0, DAG);
1907 assert(Op0.getValueType().is64BitVector() &&
1908 Op1.getValueType().is64BitVector() &&
1909 "unexpected types for extended operands to VMULL");
1910 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1912 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1913 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1914 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1915 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1916 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1917 EVT Op1VT = Op1.getValueType();
1918 return DAG.getNode(N0->getOpcode(), DL, VT,
1919 DAG.getNode(NewOpc, DL, VT,
1920 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1921 DAG.getNode(NewOpc, DL, VT,
1922 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1925 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1926 SelectionDAG &DAG) const {
1927 switch (Op.getOpcode()) {
1929 llvm_unreachable("unimplemented operand");
1932 return LowerBITCAST(Op, DAG);
1933 case ISD::GlobalAddress:
1934 return LowerGlobalAddress(Op, DAG);
1935 case ISD::GlobalTLSAddress:
1936 return LowerGlobalTLSAddress(Op, DAG);
1938 return LowerSETCC(Op, DAG);
1940 return LowerBR_CC(Op, DAG);
1942 return LowerSELECT(Op, DAG);
1943 case ISD::SELECT_CC:
1944 return LowerSELECT_CC(Op, DAG);
1945 case ISD::JumpTable:
1946 return LowerJumpTable(Op, DAG);
1947 case ISD::ConstantPool:
1948 return LowerConstantPool(Op, DAG);
1949 case ISD::BlockAddress:
1950 return LowerBlockAddress(Op, DAG);
1952 return LowerVASTART(Op, DAG);
1954 return LowerVACOPY(Op, DAG);
1956 return LowerVAARG(Op, DAG);
1961 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1968 return LowerXALUO(Op, DAG);
1970 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1972 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1974 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1976 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1978 return LowerFP_ROUND(Op, DAG);
1979 case ISD::FP_EXTEND:
1980 return LowerFP_EXTEND(Op, DAG);
1981 case ISD::FRAMEADDR:
1982 return LowerFRAMEADDR(Op, DAG);
1983 case ISD::RETURNADDR:
1984 return LowerRETURNADDR(Op, DAG);
1985 case ISD::INSERT_VECTOR_ELT:
1986 return LowerINSERT_VECTOR_ELT(Op, DAG);
1987 case ISD::EXTRACT_VECTOR_ELT:
1988 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1989 case ISD::BUILD_VECTOR:
1990 return LowerBUILD_VECTOR(Op, DAG);
1991 case ISD::VECTOR_SHUFFLE:
1992 return LowerVECTOR_SHUFFLE(Op, DAG);
1993 case ISD::EXTRACT_SUBVECTOR:
1994 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1998 return LowerVectorSRA_SRL_SHL(Op, DAG);
1999 case ISD::SHL_PARTS:
2000 return LowerShiftLeftParts(Op, DAG);
2001 case ISD::SRL_PARTS:
2002 case ISD::SRA_PARTS:
2003 return LowerShiftRightParts(Op, DAG);
2005 return LowerCTPOP(Op, DAG);
2006 case ISD::FCOPYSIGN:
2007 return LowerFCOPYSIGN(Op, DAG);
2009 return LowerVectorAND(Op, DAG);
2011 return LowerVectorOR(Op, DAG);
2013 return LowerXOR(Op, DAG);
2015 return LowerPREFETCH(Op, DAG);
2016 case ISD::SINT_TO_FP:
2017 case ISD::UINT_TO_FP:
2018 return LowerINT_TO_FP(Op, DAG);
2019 case ISD::FP_TO_SINT:
2020 case ISD::FP_TO_UINT:
2021 return LowerFP_TO_INT(Op, DAG);
2023 return LowerFSINCOS(Op, DAG);
2025 return LowerMUL(Op, DAG);
2029 /// getFunctionAlignment - Return the Log2 alignment of this function.
2030 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
2034 //===----------------------------------------------------------------------===//
2035 // Calling Convention Implementation
2036 //===----------------------------------------------------------------------===//
2038 #include "AArch64GenCallingConv.inc"
2040 /// Selects the correct CCAssignFn for a given CallingConvention value.
2041 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2042 bool IsVarArg) const {
2045 llvm_unreachable("Unsupported calling convention.");
2046 case CallingConv::WebKit_JS:
2047 return CC_AArch64_WebKit_JS;
2048 case CallingConv::GHC:
2049 return CC_AArch64_GHC;
2050 case CallingConv::C:
2051 case CallingConv::Fast:
2052 if (!Subtarget->isTargetDarwin())
2053 return CC_AArch64_AAPCS;
2054 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2058 SDValue AArch64TargetLowering::LowerFormalArguments(
2059 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2060 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2061 SmallVectorImpl<SDValue> &InVals) const {
2062 MachineFunction &MF = DAG.getMachineFunction();
2063 MachineFrameInfo *MFI = MF.getFrameInfo();
2065 // Assign locations to all of the incoming arguments.
2066 SmallVector<CCValAssign, 16> ArgLocs;
2067 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2070 // At this point, Ins[].VT may already be promoted to i32. To correctly
2071 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2072 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2073 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2074 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2076 unsigned NumArgs = Ins.size();
2077 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2078 unsigned CurArgIdx = 0;
2079 for (unsigned i = 0; i != NumArgs; ++i) {
2080 MVT ValVT = Ins[i].VT;
2081 if (Ins[i].isOrigArg()) {
2082 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2083 CurArgIdx = Ins[i].getOrigArgIndex();
2085 // Get type of the original argument.
2086 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2087 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2088 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2089 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2091 else if (ActualMVT == MVT::i16)
2094 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2096 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2097 assert(!Res && "Call operand has unhandled type");
2100 assert(ArgLocs.size() == Ins.size());
2101 SmallVector<SDValue, 16> ArgValues;
2102 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2103 CCValAssign &VA = ArgLocs[i];
2105 if (Ins[i].Flags.isByVal()) {
2106 // Byval is used for HFAs in the PCS, but the system should work in a
2107 // non-compliant manner for larger structs.
2108 EVT PtrTy = getPointerTy();
2109 int Size = Ins[i].Flags.getByValSize();
2110 unsigned NumRegs = (Size + 7) / 8;
2112 // FIXME: This works on big-endian for composite byvals, which are the common
2113 // case. It should also work for fundamental types too.
2115 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2116 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2117 InVals.push_back(FrameIdxN);
2122 if (VA.isRegLoc()) {
2123 // Arguments stored in registers.
2124 EVT RegVT = VA.getLocVT();
2127 const TargetRegisterClass *RC;
2129 if (RegVT == MVT::i32)
2130 RC = &AArch64::GPR32RegClass;
2131 else if (RegVT == MVT::i64)
2132 RC = &AArch64::GPR64RegClass;
2133 else if (RegVT == MVT::f16)
2134 RC = &AArch64::FPR16RegClass;
2135 else if (RegVT == MVT::f32)
2136 RC = &AArch64::FPR32RegClass;
2137 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2138 RC = &AArch64::FPR64RegClass;
2139 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2140 RC = &AArch64::FPR128RegClass;
2142 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2144 // Transform the arguments in physical registers into virtual ones.
2145 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2146 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2148 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2149 // to 64 bits. Insert an assert[sz]ext to capture this, then
2150 // truncate to the right size.
2151 switch (VA.getLocInfo()) {
2153 llvm_unreachable("Unknown loc info!");
2154 case CCValAssign::Full:
2156 case CCValAssign::BCvt:
2157 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2159 case CCValAssign::AExt:
2160 case CCValAssign::SExt:
2161 case CCValAssign::ZExt:
2162 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2163 // nodes after our lowering.
2164 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2168 InVals.push_back(ArgValue);
2170 } else { // VA.isRegLoc()
2171 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2172 unsigned ArgOffset = VA.getLocMemOffset();
2173 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2175 uint32_t BEAlign = 0;
2176 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2177 !Ins[i].Flags.isInConsecutiveRegs())
2178 BEAlign = 8 - ArgSize;
2180 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2182 // Create load nodes to retrieve arguments from the stack.
2183 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2186 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2187 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2188 MVT MemVT = VA.getValVT();
2190 switch (VA.getLocInfo()) {
2193 case CCValAssign::BCvt:
2194 MemVT = VA.getLocVT();
2196 case CCValAssign::SExt:
2197 ExtType = ISD::SEXTLOAD;
2199 case CCValAssign::ZExt:
2200 ExtType = ISD::ZEXTLOAD;
2202 case CCValAssign::AExt:
2203 ExtType = ISD::EXTLOAD;
2207 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2208 MachinePointerInfo::getFixedStack(FI),
2209 MemVT, false, false, false, 0);
2211 InVals.push_back(ArgValue);
2217 if (!Subtarget->isTargetDarwin()) {
2218 // The AAPCS variadic function ABI is identical to the non-variadic
2219 // one. As a result there may be more arguments in registers and we should
2220 // save them for future reference.
2221 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2224 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2225 // This will point to the next argument passed via stack.
2226 unsigned StackOffset = CCInfo.getNextStackOffset();
2227 // We currently pass all varargs at 8-byte alignment.
2228 StackOffset = ((StackOffset + 7) & ~7);
2229 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2232 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2233 unsigned StackArgSize = CCInfo.getNextStackOffset();
2234 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2235 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2236 // This is a non-standard ABI so by fiat I say we're allowed to make full
2237 // use of the stack area to be popped, which must be aligned to 16 bytes in
2239 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2241 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2242 // a multiple of 16.
2243 FuncInfo->setArgumentStackToRestore(StackArgSize);
2245 // This realignment carries over to the available bytes below. Our own
2246 // callers will guarantee the space is free by giving an aligned value to
2249 // Even if we're not expected to free up the space, it's useful to know how
2250 // much is there while considering tail calls (because we can reuse it).
2251 FuncInfo->setBytesInStackArgArea(StackArgSize);
2256 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2257 SelectionDAG &DAG, SDLoc DL,
2258 SDValue &Chain) const {
2259 MachineFunction &MF = DAG.getMachineFunction();
2260 MachineFrameInfo *MFI = MF.getFrameInfo();
2261 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2263 SmallVector<SDValue, 8> MemOps;
2265 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2266 AArch64::X3, AArch64::X4, AArch64::X5,
2267 AArch64::X6, AArch64::X7 };
2268 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2269 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2271 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2273 if (GPRSaveSize != 0) {
2274 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2276 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2278 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2279 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2280 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2282 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2283 MachinePointerInfo::getStack(i * 8), false, false, 0);
2284 MemOps.push_back(Store);
2285 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2286 DAG.getConstant(8, DL, getPointerTy()));
2289 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2290 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2292 if (Subtarget->hasFPARMv8()) {
2293 static const MCPhysReg FPRArgRegs[] = {
2294 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2295 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2296 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2297 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2299 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2301 if (FPRSaveSize != 0) {
2302 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2304 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2306 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2307 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2308 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2311 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2312 MachinePointerInfo::getStack(i * 16), false, false, 0);
2313 MemOps.push_back(Store);
2314 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2315 DAG.getConstant(16, DL, getPointerTy()));
2318 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2319 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2322 if (!MemOps.empty()) {
2323 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2327 /// LowerCallResult - Lower the result values of a call into the
2328 /// appropriate copies out of appropriate physical registers.
2329 SDValue AArch64TargetLowering::LowerCallResult(
2330 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2331 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2332 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2333 SDValue ThisVal) const {
2334 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2335 ? RetCC_AArch64_WebKit_JS
2336 : RetCC_AArch64_AAPCS;
2337 // Assign locations to each value returned by this call.
2338 SmallVector<CCValAssign, 16> RVLocs;
2339 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2341 CCInfo.AnalyzeCallResult(Ins, RetCC);
2343 // Copy all of the result registers out of their specified physreg.
2344 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2345 CCValAssign VA = RVLocs[i];
2347 // Pass 'this' value directly from the argument to return value, to avoid
2348 // reg unit interference
2349 if (i == 0 && isThisReturn) {
2350 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2351 "unexpected return calling convention register assignment");
2352 InVals.push_back(ThisVal);
2357 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2358 Chain = Val.getValue(1);
2359 InFlag = Val.getValue(2);
2361 switch (VA.getLocInfo()) {
2363 llvm_unreachable("Unknown loc info!");
2364 case CCValAssign::Full:
2366 case CCValAssign::BCvt:
2367 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2371 InVals.push_back(Val);
2377 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2378 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2379 bool isCalleeStructRet, bool isCallerStructRet,
2380 const SmallVectorImpl<ISD::OutputArg> &Outs,
2381 const SmallVectorImpl<SDValue> &OutVals,
2382 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2383 // For CallingConv::C this function knows whether the ABI needs
2384 // changing. That's not true for other conventions so they will have to opt in
2386 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2389 const MachineFunction &MF = DAG.getMachineFunction();
2390 const Function *CallerF = MF.getFunction();
2391 CallingConv::ID CallerCC = CallerF->getCallingConv();
2392 bool CCMatch = CallerCC == CalleeCC;
2394 // Byval parameters hand the function a pointer directly into the stack area
2395 // we want to reuse during a tail call. Working around this *is* possible (see
2396 // X86) but less efficient and uglier in LowerCall.
2397 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2398 e = CallerF->arg_end();
2400 if (i->hasByValAttr())
2403 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2404 if (IsTailCallConvention(CalleeCC) && CCMatch)
2409 // Externally-defined functions with weak linkage should not be
2410 // tail-called on AArch64 when the OS does not support dynamic
2411 // pre-emption of symbols, as the AAELF spec requires normal calls
2412 // to undefined weak functions to be replaced with a NOP or jump to the
2413 // next instruction. The behaviour of branch instructions in this
2414 // situation (as used for tail calls) is implementation-defined, so we
2415 // cannot rely on the linker replacing the tail call with a return.
2416 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2417 const GlobalValue *GV = G->getGlobal();
2418 const Triple TT(getTargetMachine().getTargetTriple());
2419 if (GV->hasExternalWeakLinkage() &&
2420 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2424 // Now we search for cases where we can use a tail call without changing the
2425 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2428 // I want anyone implementing a new calling convention to think long and hard
2429 // about this assert.
2430 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2431 "Unexpected variadic calling convention");
2433 if (isVarArg && !Outs.empty()) {
2434 // At least two cases here: if caller is fastcc then we can't have any
2435 // memory arguments (we'd be expected to clean up the stack afterwards). If
2436 // caller is C then we could potentially use its argument area.
2438 // FIXME: for now we take the most conservative of these in both cases:
2439 // disallow all variadic memory operands.
2440 SmallVector<CCValAssign, 16> ArgLocs;
2441 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2444 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2445 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2446 if (!ArgLocs[i].isRegLoc())
2450 // If the calling conventions do not match, then we'd better make sure the
2451 // results are returned in the same way as what the caller expects.
2453 SmallVector<CCValAssign, 16> RVLocs1;
2454 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2456 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2458 SmallVector<CCValAssign, 16> RVLocs2;
2459 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2461 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2463 if (RVLocs1.size() != RVLocs2.size())
2465 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2466 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2468 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2470 if (RVLocs1[i].isRegLoc()) {
2471 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2474 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2480 // Nothing more to check if the callee is taking no arguments
2484 SmallVector<CCValAssign, 16> ArgLocs;
2485 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2488 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2490 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2492 // If the stack arguments for this call would fit into our own save area then
2493 // the call can be made tail.
2494 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2497 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2499 MachineFrameInfo *MFI,
2500 int ClobberedFI) const {
2501 SmallVector<SDValue, 8> ArgChains;
2502 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2503 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2505 // Include the original chain at the beginning of the list. When this is
2506 // used by target LowerCall hooks, this helps legalize find the
2507 // CALLSEQ_BEGIN node.
2508 ArgChains.push_back(Chain);
2510 // Add a chain value for each stack argument corresponding
2511 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2512 UE = DAG.getEntryNode().getNode()->use_end();
2514 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2515 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2516 if (FI->getIndex() < 0) {
2517 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2518 int64_t InLastByte = InFirstByte;
2519 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2521 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2522 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2523 ArgChains.push_back(SDValue(L, 1));
2526 // Build a tokenfactor for all the chains.
2527 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2530 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2531 bool TailCallOpt) const {
2532 return CallCC == CallingConv::Fast && TailCallOpt;
2535 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2536 return CallCC == CallingConv::Fast;
2539 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2540 /// and add input and output parameter nodes.
2542 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2543 SmallVectorImpl<SDValue> &InVals) const {
2544 SelectionDAG &DAG = CLI.DAG;
2546 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2547 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2548 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2549 SDValue Chain = CLI.Chain;
2550 SDValue Callee = CLI.Callee;
2551 bool &IsTailCall = CLI.IsTailCall;
2552 CallingConv::ID CallConv = CLI.CallConv;
2553 bool IsVarArg = CLI.IsVarArg;
2555 MachineFunction &MF = DAG.getMachineFunction();
2556 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2557 bool IsThisReturn = false;
2559 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2560 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2561 bool IsSibCall = false;
2564 // Check if it's really possible to do a tail call.
2565 IsTailCall = isEligibleForTailCallOptimization(
2566 Callee, CallConv, IsVarArg, IsStructRet,
2567 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2568 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2569 report_fatal_error("failed to perform tail call elimination on a call "
2570 "site marked musttail");
2572 // A sibling call is one where we're under the usual C ABI and not planning
2573 // to change that but can still do a tail call:
2574 if (!TailCallOpt && IsTailCall)
2581 // Analyze operands of the call, assigning locations to each operand.
2582 SmallVector<CCValAssign, 16> ArgLocs;
2583 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2587 // Handle fixed and variable vector arguments differently.
2588 // Variable vector arguments always go into memory.
2589 unsigned NumArgs = Outs.size();
2591 for (unsigned i = 0; i != NumArgs; ++i) {
2592 MVT ArgVT = Outs[i].VT;
2593 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2594 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2595 /*IsVarArg=*/ !Outs[i].IsFixed);
2596 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2597 assert(!Res && "Call operand has unhandled type");
2601 // At this point, Outs[].VT may already be promoted to i32. To correctly
2602 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2603 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2604 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2605 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2607 unsigned NumArgs = Outs.size();
2608 for (unsigned i = 0; i != NumArgs; ++i) {
2609 MVT ValVT = Outs[i].VT;
2610 // Get type of the original argument.
2611 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2612 /*AllowUnknown*/ true);
2613 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2614 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2615 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2616 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2618 else if (ActualMVT == MVT::i16)
2621 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2622 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2623 assert(!Res && "Call operand has unhandled type");
2628 // Get a count of how many bytes are to be pushed on the stack.
2629 unsigned NumBytes = CCInfo.getNextStackOffset();
2632 // Since we're not changing the ABI to make this a tail call, the memory
2633 // operands are already available in the caller's incoming argument space.
2637 // FPDiff is the byte offset of the call's argument area from the callee's.
2638 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2639 // by this amount for a tail call. In a sibling call it must be 0 because the
2640 // caller will deallocate the entire stack and the callee still expects its
2641 // arguments to begin at SP+0. Completely unused for non-tail calls.
2644 if (IsTailCall && !IsSibCall) {
2645 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2647 // Since callee will pop argument stack as a tail call, we must keep the
2648 // popped size 16-byte aligned.
2649 NumBytes = RoundUpToAlignment(NumBytes, 16);
2651 // FPDiff will be negative if this tail call requires more space than we
2652 // would automatically have in our incoming argument space. Positive if we
2653 // can actually shrink the stack.
2654 FPDiff = NumReusableBytes - NumBytes;
2656 // The stack pointer must be 16-byte aligned at all times it's used for a
2657 // memory operation, which in practice means at *all* times and in
2658 // particular across call boundaries. Therefore our own arguments started at
2659 // a 16-byte aligned SP and the delta applied for the tail call should
2660 // satisfy the same constraint.
2661 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2664 // Adjust the stack pointer for the new arguments...
2665 // These operations are automatically eliminated by the prolog/epilog pass
2667 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
2671 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2673 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2674 SmallVector<SDValue, 8> MemOpChains;
2676 // Walk the register/memloc assignments, inserting copies/loads.
2677 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2678 ++i, ++realArgIdx) {
2679 CCValAssign &VA = ArgLocs[i];
2680 SDValue Arg = OutVals[realArgIdx];
2681 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2683 // Promote the value if needed.
2684 switch (VA.getLocInfo()) {
2686 llvm_unreachable("Unknown loc info!");
2687 case CCValAssign::Full:
2689 case CCValAssign::SExt:
2690 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2692 case CCValAssign::ZExt:
2693 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2695 case CCValAssign::AExt:
2696 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2697 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2698 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2699 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2701 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2703 case CCValAssign::BCvt:
2704 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2706 case CCValAssign::FPExt:
2707 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2711 if (VA.isRegLoc()) {
2712 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2713 assert(VA.getLocVT() == MVT::i64 &&
2714 "unexpected calling convention register assignment");
2715 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2716 "unexpected use of 'returned'");
2717 IsThisReturn = true;
2719 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2721 assert(VA.isMemLoc());
2724 MachinePointerInfo DstInfo;
2726 // FIXME: This works on big-endian for composite byvals, which are the
2727 // common case. It should also work for fundamental types too.
2728 uint32_t BEAlign = 0;
2729 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2730 : VA.getValVT().getSizeInBits();
2731 OpSize = (OpSize + 7) / 8;
2732 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
2733 !Flags.isInConsecutiveRegs()) {
2735 BEAlign = 8 - OpSize;
2737 unsigned LocMemOffset = VA.getLocMemOffset();
2738 int32_t Offset = LocMemOffset + BEAlign;
2739 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2740 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2743 Offset = Offset + FPDiff;
2744 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2746 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2747 DstInfo = MachinePointerInfo::getFixedStack(FI);
2749 // Make sure any stack arguments overlapping with where we're storing
2750 // are loaded before this eventual operation. Otherwise they'll be
2752 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2754 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
2756 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2757 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2760 if (Outs[i].Flags.isByVal()) {
2762 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
2763 SDValue Cpy = DAG.getMemcpy(
2764 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2765 /*isVol = */ false, /*AlwaysInline = */ false,
2766 /*isTailCall = */ false,
2767 DstInfo, MachinePointerInfo());
2769 MemOpChains.push_back(Cpy);
2771 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2772 // promoted to a legal register type i32, we should truncate Arg back to
2774 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2775 VA.getValVT() == MVT::i16)
2776 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2779 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2780 MemOpChains.push_back(Store);
2785 if (!MemOpChains.empty())
2786 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2788 // Build a sequence of copy-to-reg nodes chained together with token chain
2789 // and flag operands which copy the outgoing args into the appropriate regs.
2791 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2792 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2793 RegsToPass[i].second, InFlag);
2794 InFlag = Chain.getValue(1);
2797 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2798 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2799 // node so that legalize doesn't hack it.
2800 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2801 Subtarget->isTargetMachO()) {
2802 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2803 const GlobalValue *GV = G->getGlobal();
2804 bool InternalLinkage = GV->hasInternalLinkage();
2805 if (InternalLinkage)
2806 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2808 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2810 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2812 } else if (ExternalSymbolSDNode *S =
2813 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2814 const char *Sym = S->getSymbol();
2816 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2817 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2819 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2820 const GlobalValue *GV = G->getGlobal();
2821 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2822 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2823 const char *Sym = S->getSymbol();
2824 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2827 // We don't usually want to end the call-sequence here because we would tidy
2828 // the frame up *after* the call, however in the ABI-changing tail-call case
2829 // we've carefully laid out the parameters so that when sp is reset they'll be
2830 // in the correct location.
2831 if (IsTailCall && !IsSibCall) {
2832 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
2833 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2834 InFlag = Chain.getValue(1);
2837 std::vector<SDValue> Ops;
2838 Ops.push_back(Chain);
2839 Ops.push_back(Callee);
2842 // Each tail call may have to adjust the stack by a different amount, so
2843 // this information must travel along with the operation for eventual
2844 // consumption by emitEpilogue.
2845 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
2848 // Add argument registers to the end of the list so that they are known live
2850 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2851 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2852 RegsToPass[i].second.getValueType()));
2854 // Add a register mask operand representing the call-preserved registers.
2855 const uint32_t *Mask;
2856 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
2858 // For 'this' returns, use the X0-preserving mask if applicable
2859 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
2861 IsThisReturn = false;
2862 Mask = TRI->getCallPreservedMask(MF, CallConv);
2865 Mask = TRI->getCallPreservedMask(MF, CallConv);
2867 assert(Mask && "Missing call preserved mask for calling convention");
2868 Ops.push_back(DAG.getRegisterMask(Mask));
2870 if (InFlag.getNode())
2871 Ops.push_back(InFlag);
2873 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2875 // If we're doing a tall call, use a TC_RETURN here rather than an
2876 // actual call instruction.
2878 MF.getFrameInfo()->setHasTailCall();
2879 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2882 // Returns a chain and a flag for retval copy to use.
2883 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2884 InFlag = Chain.getValue(1);
2886 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2887 ? RoundUpToAlignment(NumBytes, 16)
2890 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
2891 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
2894 InFlag = Chain.getValue(1);
2896 // Handle result values, copying them out of physregs into vregs that we
2898 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2899 InVals, IsThisReturn,
2900 IsThisReturn ? OutVals[0] : SDValue());
2903 bool AArch64TargetLowering::CanLowerReturn(
2904 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2905 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2906 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2907 ? RetCC_AArch64_WebKit_JS
2908 : RetCC_AArch64_AAPCS;
2909 SmallVector<CCValAssign, 16> RVLocs;
2910 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2911 return CCInfo.CheckReturn(Outs, RetCC);
2915 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2917 const SmallVectorImpl<ISD::OutputArg> &Outs,
2918 const SmallVectorImpl<SDValue> &OutVals,
2919 SDLoc DL, SelectionDAG &DAG) const {
2920 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2921 ? RetCC_AArch64_WebKit_JS
2922 : RetCC_AArch64_AAPCS;
2923 SmallVector<CCValAssign, 16> RVLocs;
2924 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2926 CCInfo.AnalyzeReturn(Outs, RetCC);
2928 // Copy the result values into the output registers.
2930 SmallVector<SDValue, 4> RetOps(1, Chain);
2931 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2932 ++i, ++realRVLocIdx) {
2933 CCValAssign &VA = RVLocs[i];
2934 assert(VA.isRegLoc() && "Can only return in registers!");
2935 SDValue Arg = OutVals[realRVLocIdx];
2937 switch (VA.getLocInfo()) {
2939 llvm_unreachable("Unknown loc info!");
2940 case CCValAssign::Full:
2941 if (Outs[i].ArgVT == MVT::i1) {
2942 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2943 // value. This is strictly redundant on Darwin (which uses "zeroext
2944 // i1"), but will be optimised out before ISel.
2945 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2946 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2949 case CCValAssign::BCvt:
2950 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2954 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2955 Flag = Chain.getValue(1);
2956 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2959 RetOps[0] = Chain; // Update chain.
2961 // Add the flag if we have it.
2963 RetOps.push_back(Flag);
2965 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2968 //===----------------------------------------------------------------------===//
2969 // Other Lowering Code
2970 //===----------------------------------------------------------------------===//
2972 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2973 SelectionDAG &DAG) const {
2974 EVT PtrVT = getPointerTy();
2976 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2977 const GlobalValue *GV = GN->getGlobal();
2978 unsigned char OpFlags =
2979 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2981 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2982 "unexpected offset in global node");
2984 // This also catched the large code model case for Darwin.
2985 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2986 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2987 // FIXME: Once remat is capable of dealing with instructions with register
2988 // operands, expand this into two nodes instead of using a wrapper node.
2989 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2992 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2993 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2994 "use of MO_CONSTPOOL only supported on small model");
2995 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2996 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2997 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2998 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2999 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3000 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
3001 MachinePointerInfo::getConstantPool(),
3002 /*isVolatile=*/ false,
3003 /*isNonTemporal=*/ true,
3004 /*isInvariant=*/ true, 8);
3005 if (GN->getOffset() != 0)
3006 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
3007 DAG.getConstant(GN->getOffset(), DL, PtrVT));
3011 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3012 const unsigned char MO_NC = AArch64II::MO_NC;
3014 AArch64ISD::WrapperLarge, DL, PtrVT,
3015 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
3016 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3017 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3018 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3020 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3021 // the only correct model on Darwin.
3022 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
3023 OpFlags | AArch64II::MO_PAGE);
3024 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
3025 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
3027 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3028 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3032 /// \brief Convert a TLS address reference into the correct sequence of loads
3033 /// and calls to compute the variable's address (for Darwin, currently) and
3034 /// return an SDValue containing the final node.
3036 /// Darwin only has one TLS scheme which must be capable of dealing with the
3037 /// fully general situation, in the worst case. This means:
3038 /// + "extern __thread" declaration.
3039 /// + Defined in a possibly unknown dynamic library.
3041 /// The general system is that each __thread variable has a [3 x i64] descriptor
3042 /// which contains information used by the runtime to calculate the address. The
3043 /// only part of this the compiler needs to know about is the first xword, which
3044 /// contains a function pointer that must be called with the address of the
3045 /// entire descriptor in "x0".
3047 /// Since this descriptor may be in a different unit, in general even the
3048 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
3050 /// adrp x0, _var@TLVPPAGE
3051 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3052 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3053 /// ; the function pointer
3054 /// blr x1 ; Uses descriptor address in x0
3055 /// ; Address of _var is now in x0.
3057 /// If the address of _var's descriptor *is* known to the linker, then it can
3058 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3059 /// a slight efficiency gain.
3061 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3062 SelectionDAG &DAG) const {
3063 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
3066 MVT PtrVT = getPointerTy();
3067 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3070 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3071 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3073 // The first entry in the descriptor is a function pointer that we must call
3074 // to obtain the address of the variable.
3075 SDValue Chain = DAG.getEntryNode();
3076 SDValue FuncTLVGet =
3077 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3078 false, true, true, 8);
3079 Chain = FuncTLVGet.getValue(1);
3081 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3082 MFI->setAdjustsStack(true);
3084 // TLS calls preserve all registers except those that absolutely must be
3085 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3087 const uint32_t *Mask =
3088 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3090 // Finally, we can make the call. This is just a degenerate version of a
3091 // normal AArch64 call node: x0 takes the address of the descriptor, and
3092 // returns the address of the variable in this thread.
3093 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3095 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3096 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3097 DAG.getRegisterMask(Mask), Chain.getValue(1));
3098 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3101 /// When accessing thread-local variables under either the general-dynamic or
3102 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3103 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3104 /// is a function pointer to carry out the resolution.
3106 /// The sequence is:
3107 /// adrp x0, :tlsdesc:var
3108 /// ldr x1, [x0, #:tlsdesc_lo12:var]
3109 /// add x0, x0, #:tlsdesc_lo12:var
3110 /// .tlsdesccall var
3112 /// (TPIDR_EL0 offset now in x0)
3114 /// The above sequence must be produced unscheduled, to enable the linker to
3115 /// optimize/relax this sequence.
3116 /// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3117 /// above sequence, and expanded really late in the compilation flow, to ensure
3118 /// the sequence is produced as per above.
3119 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
3120 SelectionDAG &DAG) const {
3121 EVT PtrVT = getPointerTy();
3123 SDValue Chain = DAG.getEntryNode();
3124 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3126 SmallVector<SDValue, 2> Ops;
3127 Ops.push_back(Chain);
3128 Ops.push_back(SymAddr);
3130 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
3131 SDValue Glue = Chain.getValue(1);
3133 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3137 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3138 SelectionDAG &DAG) const {
3139 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3140 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3141 "ELF TLS only supported in small memory model");
3142 // Different choices can be made for the maximum size of the TLS area for a
3143 // module. For the small address model, the default TLS size is 16MiB and the
3144 // maximum TLS size is 4GiB.
3145 // FIXME: add -mtls-size command line option and make it control the 16MiB
3146 // vs. 4GiB code sequence generation.
3147 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3149 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3150 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3151 if (Model == TLSModel::LocalDynamic)
3152 Model = TLSModel::GeneralDynamic;
3156 EVT PtrVT = getPointerTy();
3158 const GlobalValue *GV = GA->getGlobal();
3160 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3162 if (Model == TLSModel::LocalExec) {
3163 SDValue HiVar = DAG.getTargetGlobalAddress(
3164 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3165 SDValue LoVar = DAG.getTargetGlobalAddress(
3167 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3169 SDValue TPWithOff_lo =
3170 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3172 DAG.getTargetConstant(0, DL, MVT::i32)),
3175 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3177 DAG.getTargetConstant(0, DL, MVT::i32)),
3180 } else if (Model == TLSModel::InitialExec) {
3181 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3182 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3183 } else if (Model == TLSModel::LocalDynamic) {
3184 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3185 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3186 // the beginning of the module's TLS region, followed by a DTPREL offset
3189 // These accesses will need deduplicating if there's more than one.
3190 AArch64FunctionInfo *MFI =
3191 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3192 MFI->incNumLocalDynamicTLSAccesses();
3194 // The call needs a relocation too for linker relaxation. It doesn't make
3195 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3197 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3200 // Now we can calculate the offset from TPIDR_EL0 to this module's
3201 // thread-local area.
3202 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3204 // Now use :dtprel_whatever: operations to calculate this variable's offset
3205 // in its thread-storage area.
3206 SDValue HiVar = DAG.getTargetGlobalAddress(
3207 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3208 SDValue LoVar = DAG.getTargetGlobalAddress(
3209 GV, DL, MVT::i64, 0,
3210 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3212 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3213 DAG.getTargetConstant(0, DL, MVT::i32)),
3215 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3216 DAG.getTargetConstant(0, DL, MVT::i32)),
3218 } else if (Model == TLSModel::GeneralDynamic) {
3219 // The call needs a relocation too for linker relaxation. It doesn't make
3220 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3223 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3225 // Finally we can make a call to calculate the offset from tpidr_el0.
3226 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3228 llvm_unreachable("Unsupported ELF TLS access model");
3230 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3233 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3234 SelectionDAG &DAG) const {
3235 if (Subtarget->isTargetDarwin())
3236 return LowerDarwinGlobalTLSAddress(Op, DAG);
3237 else if (Subtarget->isTargetELF())
3238 return LowerELFGlobalTLSAddress(Op, DAG);
3240 llvm_unreachable("Unexpected platform trying to use TLS");
3242 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3243 SDValue Chain = Op.getOperand(0);
3244 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3245 SDValue LHS = Op.getOperand(2);
3246 SDValue RHS = Op.getOperand(3);
3247 SDValue Dest = Op.getOperand(4);
3250 // Handle f128 first, since lowering it will result in comparing the return
3251 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3252 // is expecting to deal with.
3253 if (LHS.getValueType() == MVT::f128) {
3254 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3256 // If softenSetCCOperands returned a scalar, we need to compare the result
3257 // against zero to select between true and false values.
3258 if (!RHS.getNode()) {
3259 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3264 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3266 unsigned Opc = LHS.getOpcode();
3267 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3268 cast<ConstantSDNode>(RHS)->isOne() &&
3269 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3270 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3271 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3272 "Unexpected condition code.");
3273 // Only lower legal XALUO ops.
3274 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3277 // The actual operation with overflow check.
3278 AArch64CC::CondCode OFCC;
3279 SDValue Value, Overflow;
3280 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3282 if (CC == ISD::SETNE)
3283 OFCC = getInvertedCondCode(OFCC);
3284 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
3286 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3290 if (LHS.getValueType().isInteger()) {
3291 assert((LHS.getValueType() == RHS.getValueType()) &&
3292 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3294 // If the RHS of the comparison is zero, we can potentially fold this
3295 // to a specialized branch.
3296 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3297 if (RHSC && RHSC->getZExtValue() == 0) {
3298 if (CC == ISD::SETEQ) {
3299 // See if we can use a TBZ to fold in an AND as well.
3300 // TBZ has a smaller branch displacement than CBZ. If the offset is
3301 // out of bounds, a late MI-layer pass rewrites branches.
3302 // 403.gcc is an example that hits this case.
3303 if (LHS.getOpcode() == ISD::AND &&
3304 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3305 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3306 SDValue Test = LHS.getOperand(0);
3307 uint64_t Mask = LHS.getConstantOperandVal(1);
3308 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3309 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3313 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3314 } else if (CC == ISD::SETNE) {
3315 // See if we can use a TBZ to fold in an AND as well.
3316 // TBZ has a smaller branch displacement than CBZ. If the offset is
3317 // out of bounds, a late MI-layer pass rewrites branches.
3318 // 403.gcc is an example that hits this case.
3319 if (LHS.getOpcode() == ISD::AND &&
3320 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3321 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3322 SDValue Test = LHS.getOperand(0);
3323 uint64_t Mask = LHS.getConstantOperandVal(1);
3324 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3325 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
3329 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3330 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3331 // Don't combine AND since emitComparison converts the AND to an ANDS
3332 // (a.k.a. TST) and the test in the test bit and branch instruction
3333 // becomes redundant. This would also increase register pressure.
3334 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3335 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3336 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3339 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3340 LHS.getOpcode() != ISD::AND) {
3341 // Don't combine AND since emitComparison converts the AND to an ANDS
3342 // (a.k.a. TST) and the test in the test bit and branch instruction
3343 // becomes redundant. This would also increase register pressure.
3344 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3345 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3346 DAG.getConstant(Mask, dl, MVT::i64), Dest);
3350 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3351 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3355 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3357 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3358 // clean. Some of them require two branches to implement.
3359 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3360 AArch64CC::CondCode CC1, CC2;
3361 changeFPCCToAArch64CC(CC, CC1, CC2);
3362 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3364 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3365 if (CC2 != AArch64CC::AL) {
3366 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3367 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3374 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3375 SelectionDAG &DAG) const {
3376 EVT VT = Op.getValueType();
3379 SDValue In1 = Op.getOperand(0);
3380 SDValue In2 = Op.getOperand(1);
3381 EVT SrcVT = In2.getValueType();
3383 if (SrcVT == MVT::f32 && VT == MVT::f64)
3384 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3385 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3386 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2,
3387 DAG.getIntPtrConstant(0, DL));
3389 // FIXME: Src type is different, bail out for now. Can VT really be a
3397 SDValue VecVal1, VecVal2;
3398 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3401 EltMask = 0x80000000ULL;
3403 if (!VT.isVector()) {
3404 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3405 DAG.getUNDEF(VecVT), In1);
3406 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3407 DAG.getUNDEF(VecVT), In2);
3409 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3410 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3412 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3416 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3417 // immediate moves cannot materialize that in a single instruction for
3418 // 64-bit elements. Instead, materialize zero and then negate it.
3421 if (!VT.isVector()) {
3422 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3423 DAG.getUNDEF(VecVT), In1);
3424 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3425 DAG.getUNDEF(VecVT), In2);
3427 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3428 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3431 llvm_unreachable("Invalid type for copysign!");
3434 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
3436 // If we couldn't materialize the mask above, then the mask vector will be
3437 // the zero vector, and we need to negate it here.
3438 if (VT == MVT::f64 || VT == MVT::v2f64) {
3439 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3440 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3441 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3445 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3448 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3449 else if (VT == MVT::f64)
3450 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3452 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3455 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3456 if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
3457 Attribute::NoImplicitFloat))
3460 if (!Subtarget->hasNEON())
3463 // While there is no integer popcount instruction, it can
3464 // be more efficiently lowered to the following sequence that uses
3465 // AdvSIMD registers/instructions as long as the copies to/from
3466 // the AdvSIMD registers are cheap.
3467 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3468 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3469 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3470 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3471 SDValue Val = Op.getOperand(0);
3473 EVT VT = Op.getValueType();
3476 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3477 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3479 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
3480 SDValue UaddLV = DAG.getNode(
3481 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3482 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
3485 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3489 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3491 if (Op.getValueType().isVector())
3492 return LowerVSETCC(Op, DAG);
3494 SDValue LHS = Op.getOperand(0);
3495 SDValue RHS = Op.getOperand(1);
3496 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3499 // We chose ZeroOrOneBooleanContents, so use zero and one.
3500 EVT VT = Op.getValueType();
3501 SDValue TVal = DAG.getConstant(1, dl, VT);
3502 SDValue FVal = DAG.getConstant(0, dl, VT);
3504 // Handle f128 first, since one possible outcome is a normal integer
3505 // comparison which gets picked up by the next if statement.
3506 if (LHS.getValueType() == MVT::f128) {
3507 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3509 // If softenSetCCOperands returned a scalar, use it.
3510 if (!RHS.getNode()) {
3511 assert(LHS.getValueType() == Op.getValueType() &&
3512 "Unexpected setcc expansion!");
3517 if (LHS.getValueType().isInteger()) {
3520 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3522 // Note that we inverted the condition above, so we reverse the order of
3523 // the true and false operands here. This will allow the setcc to be
3524 // matched to a single CSINC instruction.
3525 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3528 // Now we know we're dealing with FP values.
3529 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3531 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3532 // and do the comparison.
3533 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3535 AArch64CC::CondCode CC1, CC2;
3536 changeFPCCToAArch64CC(CC, CC1, CC2);
3537 if (CC2 == AArch64CC::AL) {
3538 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3539 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3541 // Note that we inverted the condition above, so we reverse the order of
3542 // the true and false operands here. This will allow the setcc to be
3543 // matched to a single CSINC instruction.
3544 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3546 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3547 // totally clean. Some of them require two CSELs to implement. As is in
3548 // this case, we emit the first CSEL and then emit a second using the output
3549 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3551 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3552 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3554 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3556 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3557 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3561 /// A SELECT_CC operation is really some kind of max or min if both values being
3562 /// compared are, in some sense, equal to the results in either case. However,
3563 /// it is permissible to compare f32 values and produce directly extended f64
3566 /// Extending the comparison operands would also be allowed, but is less likely
3567 /// to happen in practice since their use is right here. Note that truncate
3568 /// operations would *not* be semantically equivalent.
3569 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3573 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3574 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3575 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3576 Result.getValueType() == MVT::f64) {
3578 APFloat CmpVal = CCmp->getValueAPF();
3579 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3580 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3583 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3586 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3587 SDValue RHS, SDValue TVal,
3588 SDValue FVal, SDLoc dl,
3589 SelectionDAG &DAG) const {
3590 // Handle f128 first, because it will result in a comparison of some RTLIB
3591 // call result against zero.
3592 if (LHS.getValueType() == MVT::f128) {
3593 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3595 // If softenSetCCOperands returned a scalar, we need to compare the result
3596 // against zero to select between true and false values.
3597 if (!RHS.getNode()) {
3598 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3603 // Handle integers first.
3604 if (LHS.getValueType().isInteger()) {
3605 assert((LHS.getValueType() == RHS.getValueType()) &&
3606 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3608 unsigned Opcode = AArch64ISD::CSEL;
3610 // If both the TVal and the FVal are constants, see if we can swap them in
3611 // order to for a CSINV or CSINC out of them.
3612 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3613 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3615 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3616 std::swap(TVal, FVal);
3617 std::swap(CTVal, CFVal);
3618 CC = ISD::getSetCCInverse(CC, true);
3619 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3620 std::swap(TVal, FVal);
3621 std::swap(CTVal, CFVal);
3622 CC = ISD::getSetCCInverse(CC, true);
3623 } else if (TVal.getOpcode() == ISD::XOR) {
3624 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3625 // with a CSINV rather than a CSEL.
3626 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3628 if (CVal && CVal->isAllOnesValue()) {
3629 std::swap(TVal, FVal);
3630 std::swap(CTVal, CFVal);
3631 CC = ISD::getSetCCInverse(CC, true);
3633 } else if (TVal.getOpcode() == ISD::SUB) {
3634 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3635 // that we can match with a CSNEG rather than a CSEL.
3636 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3638 if (CVal && CVal->isNullValue()) {
3639 std::swap(TVal, FVal);
3640 std::swap(CTVal, CFVal);
3641 CC = ISD::getSetCCInverse(CC, true);
3643 } else if (CTVal && CFVal) {
3644 const int64_t TrueVal = CTVal->getSExtValue();
3645 const int64_t FalseVal = CFVal->getSExtValue();
3648 // If both TVal and FVal are constants, see if FVal is the
3649 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3650 // instead of a CSEL in that case.
3651 if (TrueVal == ~FalseVal) {
3652 Opcode = AArch64ISD::CSINV;
3653 } else if (TrueVal == -FalseVal) {
3654 Opcode = AArch64ISD::CSNEG;
3655 } else if (TVal.getValueType() == MVT::i32) {
3656 // If our operands are only 32-bit wide, make sure we use 32-bit
3657 // arithmetic for the check whether we can use CSINC. This ensures that
3658 // the addition in the check will wrap around properly in case there is
3659 // an overflow (which would not be the case if we do the check with
3660 // 64-bit arithmetic).
3661 const uint32_t TrueVal32 = CTVal->getZExtValue();
3662 const uint32_t FalseVal32 = CFVal->getZExtValue();
3664 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3665 Opcode = AArch64ISD::CSINC;
3667 if (TrueVal32 > FalseVal32) {
3671 // 64-bit check whether we can use CSINC.
3672 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3673 Opcode = AArch64ISD::CSINC;
3675 if (TrueVal > FalseVal) {
3680 // Swap TVal and FVal if necessary.
3682 std::swap(TVal, FVal);
3683 std::swap(CTVal, CFVal);
3684 CC = ISD::getSetCCInverse(CC, true);
3687 if (Opcode != AArch64ISD::CSEL) {
3688 // Drop FVal since we can get its value by simply inverting/negating
3695 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3697 EVT VT = TVal.getValueType();
3698 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3701 // Now we know we're dealing with FP values.
3702 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3703 assert(LHS.getValueType() == RHS.getValueType());
3704 EVT VT = TVal.getValueType();
3705 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3707 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3708 // clean. Some of them require two CSELs to implement.
3709 AArch64CC::CondCode CC1, CC2;
3710 changeFPCCToAArch64CC(CC, CC1, CC2);
3711 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
3712 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3714 // If we need a second CSEL, emit it, using the output of the first as the
3715 // RHS. We're effectively OR'ing the two CC's together.
3716 if (CC2 != AArch64CC::AL) {
3717 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
3718 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3721 // Otherwise, return the output of the first CSEL.
3725 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3726 SelectionDAG &DAG) const {
3727 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3728 SDValue LHS = Op.getOperand(0);
3729 SDValue RHS = Op.getOperand(1);
3730 SDValue TVal = Op.getOperand(2);
3731 SDValue FVal = Op.getOperand(3);
3733 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3736 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3737 SelectionDAG &DAG) const {
3738 SDValue CCVal = Op->getOperand(0);
3739 SDValue TVal = Op->getOperand(1);
3740 SDValue FVal = Op->getOperand(2);
3743 unsigned Opc = CCVal.getOpcode();
3744 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3746 if (CCVal.getResNo() == 1 &&
3747 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3748 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3749 // Only lower legal XALUO ops.
3750 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
3753 AArch64CC::CondCode OFCC;
3754 SDValue Value, Overflow;
3755 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
3756 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
3758 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3762 // Lower it the same way as we would lower a SELECT_CC node.
3765 if (CCVal.getOpcode() == ISD::SETCC) {
3766 LHS = CCVal.getOperand(0);
3767 RHS = CCVal.getOperand(1);
3768 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
3771 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
3774 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
3777 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3778 SelectionDAG &DAG) const {
3779 // Jump table entries as PC relative offsets. No additional tweaking
3780 // is necessary here. Just get the address of the jump table.
3781 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3782 EVT PtrVT = getPointerTy();
3785 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3786 !Subtarget->isTargetMachO()) {
3787 const unsigned char MO_NC = AArch64II::MO_NC;
3789 AArch64ISD::WrapperLarge, DL, PtrVT,
3790 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3791 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3792 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3793 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3794 AArch64II::MO_G0 | MO_NC));
3798 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3799 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3800 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3801 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3802 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3805 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3806 SelectionDAG &DAG) const {
3807 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3808 EVT PtrVT = getPointerTy();
3811 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3812 // Use the GOT for the large code model on iOS.
3813 if (Subtarget->isTargetMachO()) {
3814 SDValue GotAddr = DAG.getTargetConstantPool(
3815 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3817 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3820 const unsigned char MO_NC = AArch64II::MO_NC;
3822 AArch64ISD::WrapperLarge, DL, PtrVT,
3823 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3824 CP->getOffset(), AArch64II::MO_G3),
3825 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3826 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3827 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3828 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3829 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3830 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3832 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3833 // ELF, the only valid one on Darwin.
3835 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3836 CP->getOffset(), AArch64II::MO_PAGE);
3837 SDValue Lo = DAG.getTargetConstantPool(
3838 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3839 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3841 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3842 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3846 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3847 SelectionDAG &DAG) const {
3848 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3849 EVT PtrVT = getPointerTy();
3851 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3852 !Subtarget->isTargetMachO()) {
3853 const unsigned char MO_NC = AArch64II::MO_NC;
3855 AArch64ISD::WrapperLarge, DL, PtrVT,
3856 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3857 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3858 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3859 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3861 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3862 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3864 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3865 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3869 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3870 SelectionDAG &DAG) const {
3871 AArch64FunctionInfo *FuncInfo =
3872 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3876 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3877 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3878 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3879 MachinePointerInfo(SV), false, false, 0);
3882 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3883 SelectionDAG &DAG) const {
3884 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3885 // Standard, section B.3.
3886 MachineFunction &MF = DAG.getMachineFunction();
3887 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3890 SDValue Chain = Op.getOperand(0);
3891 SDValue VAList = Op.getOperand(1);
3892 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3893 SmallVector<SDValue, 4> MemOps;
3895 // void *__stack at offset 0
3897 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3898 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3899 MachinePointerInfo(SV), false, false, 8));
3901 // void *__gr_top at offset 8
3902 int GPRSize = FuncInfo->getVarArgsGPRSize();
3904 SDValue GRTop, GRTopAddr;
3906 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3907 DAG.getConstant(8, DL, getPointerTy()));
3909 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3910 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3911 DAG.getConstant(GPRSize, DL, getPointerTy()));
3913 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3914 MachinePointerInfo(SV, 8), false, false, 8));
3917 // void *__vr_top at offset 16
3918 int FPRSize = FuncInfo->getVarArgsFPRSize();
3920 SDValue VRTop, VRTopAddr;
3921 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3922 DAG.getConstant(16, DL, getPointerTy()));
3924 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3925 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3926 DAG.getConstant(FPRSize, DL, getPointerTy()));
3928 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3929 MachinePointerInfo(SV, 16), false, false, 8));
3932 // int __gr_offs at offset 24
3933 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3934 DAG.getConstant(24, DL, getPointerTy()));
3935 MemOps.push_back(DAG.getStore(Chain, DL,
3936 DAG.getConstant(-GPRSize, DL, MVT::i32),
3937 GROffsAddr, MachinePointerInfo(SV, 24), false,
3940 // int __vr_offs at offset 28
3941 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3942 DAG.getConstant(28, DL, getPointerTy()));
3943 MemOps.push_back(DAG.getStore(Chain, DL,
3944 DAG.getConstant(-FPRSize, DL, MVT::i32),
3945 VROffsAddr, MachinePointerInfo(SV, 28), false,
3948 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3951 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3952 SelectionDAG &DAG) const {
3953 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3954 : LowerAAPCS_VASTART(Op, DAG);
3957 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3958 SelectionDAG &DAG) const {
3959 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3962 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3963 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3964 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3966 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
3968 DAG.getConstant(VaListSize, DL, MVT::i32),
3969 8, false, false, false, MachinePointerInfo(DestSV),
3970 MachinePointerInfo(SrcSV));
3973 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3974 assert(Subtarget->isTargetDarwin() &&
3975 "automatic va_arg instruction only works on Darwin");
3977 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3978 EVT VT = Op.getValueType();
3980 SDValue Chain = Op.getOperand(0);
3981 SDValue Addr = Op.getOperand(1);
3982 unsigned Align = Op.getConstantOperandVal(3);
3984 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3985 MachinePointerInfo(V), false, false, false, 0);
3986 Chain = VAList.getValue(1);
3989 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3990 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3991 DAG.getConstant(Align - 1, DL, getPointerTy()));
3992 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3993 DAG.getConstant(-(int64_t)Align, DL, getPointerTy()));
3996 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3997 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3999 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4000 // up to 64 bits. At the very least, we have to increase the striding of the
4001 // vaargs list to match this, and for FP values we need to introduce
4002 // FP_ROUND nodes as well.
4003 if (VT.isInteger() && !VT.isVector())
4005 bool NeedFPTrunc = false;
4006 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4011 // Increment the pointer, VAList, to the next vaarg
4012 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4013 DAG.getConstant(ArgSize, DL, getPointerTy()));
4014 // Store the incremented VAList to the legalized pointer
4015 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4018 // Load the actual argument out of the pointer VAList
4020 // Load the value as an f64.
4021 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4022 MachinePointerInfo(), false, false, false, 0);
4023 // Round the value down to an f32.
4024 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4025 DAG.getIntPtrConstant(1, DL));
4026 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4027 // Merge the rounded value with the chain output of the load.
4028 return DAG.getMergeValues(Ops, DL);
4031 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4035 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4036 SelectionDAG &DAG) const {
4037 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4038 MFI->setFrameAddressIsTaken(true);
4040 EVT VT = Op.getValueType();
4042 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4044 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4046 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4047 MachinePointerInfo(), false, false, false, 0);
4051 // FIXME? Maybe this could be a TableGen attribute on some registers and
4052 // this table could be generated automatically from RegInfo.
4053 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4055 unsigned Reg = StringSwitch<unsigned>(RegName)
4056 .Case("sp", AArch64::SP)
4060 report_fatal_error("Invalid register name global variable");
4063 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4064 SelectionDAG &DAG) const {
4065 MachineFunction &MF = DAG.getMachineFunction();
4066 MachineFrameInfo *MFI = MF.getFrameInfo();
4067 MFI->setReturnAddressIsTaken(true);
4069 EVT VT = Op.getValueType();
4071 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4073 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4074 SDValue Offset = DAG.getConstant(8, DL, getPointerTy());
4075 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4076 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4077 MachinePointerInfo(), false, false, false, 0);
4080 // Return LR, which contains the return address. Mark it an implicit live-in.
4081 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4082 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4085 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4086 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4087 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4088 SelectionDAG &DAG) const {
4089 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4090 EVT VT = Op.getValueType();
4091 unsigned VTBits = VT.getSizeInBits();
4093 SDValue ShOpLo = Op.getOperand(0);
4094 SDValue ShOpHi = Op.getOperand(1);
4095 SDValue ShAmt = Op.getOperand(2);
4097 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4099 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4101 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4102 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4103 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4104 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4105 DAG.getConstant(VTBits, dl, MVT::i64));
4106 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4108 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4109 ISD::SETGE, dl, DAG);
4110 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4112 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4113 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4115 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4117 // AArch64 shifts larger than the register width are wrapped rather than
4118 // clamped, so we can't just emit "hi >> x".
4119 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4120 SDValue TrueValHi = Opc == ISD::SRA
4121 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4122 DAG.getConstant(VTBits - 1, dl,
4124 : DAG.getConstant(0, dl, VT);
4126 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4128 SDValue Ops[2] = { Lo, Hi };
4129 return DAG.getMergeValues(Ops, dl);
4132 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4133 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4134 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4135 SelectionDAG &DAG) const {
4136 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4137 EVT VT = Op.getValueType();
4138 unsigned VTBits = VT.getSizeInBits();
4140 SDValue ShOpLo = Op.getOperand(0);
4141 SDValue ShOpHi = Op.getOperand(1);
4142 SDValue ShAmt = Op.getOperand(2);
4145 assert(Op.getOpcode() == ISD::SHL_PARTS);
4146 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4147 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4148 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4149 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4150 DAG.getConstant(VTBits, dl, MVT::i64));
4151 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4152 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4154 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4156 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64),
4157 ISD::SETGE, dl, DAG);
4158 SDValue CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4160 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4162 // AArch64 shifts of larger than register sizes are wrapped rather than
4163 // clamped, so we can't just emit "lo << a" if a is too big.
4164 SDValue TrueValLo = DAG.getConstant(0, dl, VT);
4165 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4167 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4169 SDValue Ops[2] = { Lo, Hi };
4170 return DAG.getMergeValues(Ops, dl);
4173 bool AArch64TargetLowering::isOffsetFoldingLegal(
4174 const GlobalAddressSDNode *GA) const {
4175 // The AArch64 target doesn't support folding offsets into global addresses.
4179 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4180 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4181 // FIXME: We should be able to handle f128 as well with a clever lowering.
4182 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4186 return AArch64_AM::getFP64Imm(Imm) != -1;
4187 else if (VT == MVT::f32)
4188 return AArch64_AM::getFP32Imm(Imm) != -1;
4192 //===----------------------------------------------------------------------===//
4193 // AArch64 Optimization Hooks
4194 //===----------------------------------------------------------------------===//
4196 //===----------------------------------------------------------------------===//
4197 // AArch64 Inline Assembly Support
4198 //===----------------------------------------------------------------------===//
4200 // Table of Constraints
4201 // TODO: This is the current set of constraints supported by ARM for the
4202 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4204 // r - A general register
4205 // w - An FP/SIMD register of some size in the range v0-v31
4206 // x - An FP/SIMD register of some size in the range v0-v15
4207 // I - Constant that can be used with an ADD instruction
4208 // J - Constant that can be used with a SUB instruction
4209 // K - Constant that can be used with a 32-bit logical instruction
4210 // L - Constant that can be used with a 64-bit logical instruction
4211 // M - Constant that can be used as a 32-bit MOV immediate
4212 // N - Constant that can be used as a 64-bit MOV immediate
4213 // Q - A memory reference with base register and no offset
4214 // S - A symbolic address
4215 // Y - Floating point constant zero
4216 // Z - Integer constant zero
4218 // Note that general register operands will be output using their 64-bit x
4219 // register name, whatever the size of the variable, unless the asm operand
4220 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4221 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4224 /// getConstraintType - Given a constraint letter, return the type of
4225 /// constraint it is for this target.
4226 AArch64TargetLowering::ConstraintType
4227 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4228 if (Constraint.size() == 1) {
4229 switch (Constraint[0]) {
4236 return C_RegisterClass;
4237 // An address with a single base register. Due to the way we
4238 // currently handle addresses it is the same as 'r'.
4243 return TargetLowering::getConstraintType(Constraint);
4246 /// Examine constraint type and operand type and determine a weight value.
4247 /// This object must already have been set up with the operand type
4248 /// and the current alternative constraint selected.
4249 TargetLowering::ConstraintWeight
4250 AArch64TargetLowering::getSingleConstraintMatchWeight(
4251 AsmOperandInfo &info, const char *constraint) const {
4252 ConstraintWeight weight = CW_Invalid;
4253 Value *CallOperandVal = info.CallOperandVal;
4254 // If we don't have a value, we can't do a match,
4255 // but allow it at the lowest weight.
4256 if (!CallOperandVal)
4258 Type *type = CallOperandVal->getType();
4259 // Look at the constraint type.
4260 switch (*constraint) {
4262 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4266 if (type->isFloatingPointTy() || type->isVectorTy())
4267 weight = CW_Register;
4270 weight = CW_Constant;
4276 std::pair<unsigned, const TargetRegisterClass *>
4277 AArch64TargetLowering::getRegForInlineAsmConstraint(
4278 const TargetRegisterInfo *TRI, const std::string &Constraint,
4280 if (Constraint.size() == 1) {
4281 switch (Constraint[0]) {
4283 if (VT.getSizeInBits() == 64)
4284 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4285 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4288 return std::make_pair(0U, &AArch64::FPR32RegClass);
4289 if (VT.getSizeInBits() == 64)
4290 return std::make_pair(0U, &AArch64::FPR64RegClass);
4291 if (VT.getSizeInBits() == 128)
4292 return std::make_pair(0U, &AArch64::FPR128RegClass);
4294 // The instructions that this constraint is designed for can
4295 // only take 128-bit registers so just use that regclass.
4297 if (VT.getSizeInBits() == 128)
4298 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4302 if (StringRef("{cc}").equals_lower(Constraint))
4303 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4305 // Use the default implementation in TargetLowering to convert the register
4306 // constraint into a member of a register class.
4307 std::pair<unsigned, const TargetRegisterClass *> Res;
4308 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4310 // Not found as a standard register?
4312 unsigned Size = Constraint.size();
4313 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4314 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4315 const std::string Reg =
4316 std::string(&Constraint[2], &Constraint[Size - 1]);
4317 int RegNo = atoi(Reg.c_str());
4318 if (RegNo >= 0 && RegNo <= 31) {
4319 // v0 - v31 are aliases of q0 - q31.
4320 // By default we'll emit v0-v31 for this unless there's a modifier where
4321 // we'll emit the correct register as well.
4322 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4323 Res.second = &AArch64::FPR128RegClass;
4331 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4332 /// vector. If it is invalid, don't add anything to Ops.
4333 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4334 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4335 SelectionDAG &DAG) const {
4338 // Currently only support length 1 constraints.
4339 if (Constraint.length() != 1)
4342 char ConstraintLetter = Constraint[0];
4343 switch (ConstraintLetter) {
4347 // This set of constraints deal with valid constants for various instructions.
4348 // Validate and return a target constant for them if we can.
4350 // 'z' maps to xzr or wzr so it needs an input of 0.
4351 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4352 if (!C || C->getZExtValue() != 0)
4355 if (Op.getValueType() == MVT::i64)
4356 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4358 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4368 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4372 // Grab the value and do some validation.
4373 uint64_t CVal = C->getZExtValue();
4374 switch (ConstraintLetter) {
4375 // The I constraint applies only to simple ADD or SUB immediate operands:
4376 // i.e. 0 to 4095 with optional shift by 12
4377 // The J constraint applies only to ADD or SUB immediates that would be
4378 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4379 // instruction [or vice versa], in other words -1 to -4095 with optional
4380 // left shift by 12.
4382 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4386 uint64_t NVal = -C->getSExtValue();
4387 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4388 CVal = C->getSExtValue();
4393 // The K and L constraints apply *only* to logical immediates, including
4394 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4395 // been removed and MOV should be used). So these constraints have to
4396 // distinguish between bit patterns that are valid 32-bit or 64-bit
4397 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4398 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4401 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4405 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4408 // The M and N constraints are a superset of K and L respectively, for use
4409 // with the MOV (immediate) alias. As well as the logical immediates they
4410 // also match 32 or 64-bit immediates that can be loaded either using a
4411 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4412 // (M) or 64-bit 0x1234000000000000 (N) etc.
4413 // As a note some of this code is liberally stolen from the asm parser.
4415 if (!isUInt<32>(CVal))
4417 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4419 if ((CVal & 0xFFFF) == CVal)
4421 if ((CVal & 0xFFFF0000ULL) == CVal)
4423 uint64_t NCVal = ~(uint32_t)CVal;
4424 if ((NCVal & 0xFFFFULL) == NCVal)
4426 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4431 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4433 if ((CVal & 0xFFFFULL) == CVal)
4435 if ((CVal & 0xFFFF0000ULL) == CVal)
4437 if ((CVal & 0xFFFF00000000ULL) == CVal)
4439 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4441 uint64_t NCVal = ~CVal;
4442 if ((NCVal & 0xFFFFULL) == NCVal)
4444 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4446 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4448 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4456 // All assembler immediates are 64-bit integers.
4457 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
4461 if (Result.getNode()) {
4462 Ops.push_back(Result);
4466 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4469 //===----------------------------------------------------------------------===//
4470 // AArch64 Advanced SIMD Support
4471 //===----------------------------------------------------------------------===//
4473 /// WidenVector - Given a value in the V64 register class, produce the
4474 /// equivalent value in the V128 register class.
4475 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4476 EVT VT = V64Reg.getValueType();
4477 unsigned NarrowSize = VT.getVectorNumElements();
4478 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4479 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4482 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4483 V64Reg, DAG.getConstant(0, DL, MVT::i32));
4486 /// getExtFactor - Determine the adjustment factor for the position when
4487 /// generating an "extract from vector registers" instruction.
4488 static unsigned getExtFactor(SDValue &V) {
4489 EVT EltType = V.getValueType().getVectorElementType();
4490 return EltType.getSizeInBits() / 8;
4493 /// NarrowVector - Given a value in the V128 register class, produce the
4494 /// equivalent value in the V64 register class.
4495 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4496 EVT VT = V128Reg.getValueType();
4497 unsigned WideSize = VT.getVectorNumElements();
4498 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4499 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4502 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4505 // Gather data to see if the operation can be modelled as a
4506 // shuffle in combination with VEXTs.
4507 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4508 SelectionDAG &DAG) const {
4509 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4511 EVT VT = Op.getValueType();
4512 unsigned NumElts = VT.getVectorNumElements();
4514 struct ShuffleSourceInfo {
4519 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4520 // be compatible with the shuffle we intend to construct. As a result
4521 // ShuffleVec will be some sliding window into the original Vec.
4524 // Code should guarantee that element i in Vec starts at element "WindowBase
4525 // + i * WindowScale in ShuffleVec".
4529 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4530 ShuffleSourceInfo(SDValue Vec)
4531 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4535 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4537 SmallVector<ShuffleSourceInfo, 2> Sources;
4538 for (unsigned i = 0; i < NumElts; ++i) {
4539 SDValue V = Op.getOperand(i);
4540 if (V.getOpcode() == ISD::UNDEF)
4542 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4543 // A shuffle can only come from building a vector from various
4544 // elements of other vectors.
4548 // Add this element source to the list if it's not already there.
4549 SDValue SourceVec = V.getOperand(0);
4550 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4551 if (Source == Sources.end())
4552 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4554 // Update the minimum and maximum lane number seen.
4555 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4556 Source->MinElt = std::min(Source->MinElt, EltNo);
4557 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4560 // Currently only do something sane when at most two source vectors
4562 if (Sources.size() > 2)
4565 // Find out the smallest element size among result and two sources, and use
4566 // it as element size to build the shuffle_vector.
4567 EVT SmallestEltTy = VT.getVectorElementType();
4568 for (auto &Source : Sources) {
4569 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4570 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4571 SmallestEltTy = SrcEltTy;
4574 unsigned ResMultiplier =
4575 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4576 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4577 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4579 // If the source vector is too wide or too narrow, we may nevertheless be able
4580 // to construct a compatible shuffle either by concatenating it with UNDEF or
4581 // extracting a suitable range of elements.
4582 for (auto &Src : Sources) {
4583 EVT SrcVT = Src.ShuffleVec.getValueType();
4585 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4588 // This stage of the search produces a source with the same element type as
4589 // the original, but with a total width matching the BUILD_VECTOR output.
4590 EVT EltVT = SrcVT.getVectorElementType();
4591 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4592 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4594 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4595 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4596 // We can pad out the smaller vector for free, so if it's part of a
4599 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4600 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4604 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4606 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4607 // Span too large for a VEXT to cope
4611 if (Src.MinElt >= NumSrcElts) {
4612 // The extraction can just take the second half
4614 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4615 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4616 Src.WindowBase = -NumSrcElts;
4617 } else if (Src.MaxElt < NumSrcElts) {
4618 // The extraction can just take the first half
4620 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4621 DAG.getConstant(0, dl, MVT::i64));
4623 // An actual VEXT is needed
4625 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4626 DAG.getConstant(0, dl, MVT::i64));
4628 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4629 DAG.getConstant(NumSrcElts, dl, MVT::i64));
4630 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4632 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4634 DAG.getConstant(Imm, dl, MVT::i32));
4635 Src.WindowBase = -Src.MinElt;
4639 // Another possible incompatibility occurs from the vector element types. We
4640 // can fix this by bitcasting the source vectors to the same type we intend
4642 for (auto &Src : Sources) {
4643 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4644 if (SrcEltTy == SmallestEltTy)
4646 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4647 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4648 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4649 Src.WindowBase *= Src.WindowScale;
4652 // Final sanity check before we try to actually produce a shuffle.
4654 for (auto Src : Sources)
4655 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4658 // The stars all align, our next step is to produce the mask for the shuffle.
4659 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4660 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4661 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4662 SDValue Entry = Op.getOperand(i);
4663 if (Entry.getOpcode() == ISD::UNDEF)
4666 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4667 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4669 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4670 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4672 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4673 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4674 VT.getVectorElementType().getSizeInBits());
4675 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4677 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4678 // starting at the appropriate offset.
4679 int *LaneMask = &Mask[i * ResMultiplier];
4681 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4682 ExtractBase += NumElts * (Src - Sources.begin());
4683 for (int j = 0; j < LanesDefined; ++j)
4684 LaneMask[j] = ExtractBase + j;
4687 // Final check before we try to produce nonsense...
4688 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4691 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4692 for (unsigned i = 0; i < Sources.size(); ++i)
4693 ShuffleOps[i] = Sources[i].ShuffleVec;
4695 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4696 ShuffleOps[1], &Mask[0]);
4697 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4700 // check if an EXT instruction can handle the shuffle mask when the
4701 // vector sources of the shuffle are the same.
4702 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4703 unsigned NumElts = VT.getVectorNumElements();
4705 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4711 // If this is a VEXT shuffle, the immediate value is the index of the first
4712 // element. The other shuffle indices must be the successive elements after
4714 unsigned ExpectedElt = Imm;
4715 for (unsigned i = 1; i < NumElts; ++i) {
4716 // Increment the expected index. If it wraps around, just follow it
4717 // back to index zero and keep going.
4719 if (ExpectedElt == NumElts)
4723 continue; // ignore UNDEF indices
4724 if (ExpectedElt != static_cast<unsigned>(M[i]))
4731 // check if an EXT instruction can handle the shuffle mask when the
4732 // vector sources of the shuffle are different.
4733 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4735 // Look for the first non-undef element.
4736 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4737 [](int Elt) {return Elt >= 0;});
4739 // Benefit form APInt to handle overflow when calculating expected element.
4740 unsigned NumElts = VT.getVectorNumElements();
4741 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4742 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4743 // The following shuffle indices must be the successive elements after the
4744 // first real element.
4745 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4746 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4747 if (FirstWrongElt != M.end())
4750 // The index of an EXT is the first element if it is not UNDEF.
4751 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4752 // value of the first element. E.g.
4753 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4754 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4755 // ExpectedElt is the last mask index plus 1.
4756 Imm = ExpectedElt.getZExtValue();
4758 // There are two difference cases requiring to reverse input vectors.
4759 // For example, for vector <4 x i32> we have the following cases,
4760 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4761 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4762 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4763 // to reverse two input vectors.
4772 /// isREVMask - Check if a vector shuffle corresponds to a REV
4773 /// instruction with the specified blocksize. (The order of the elements
4774 /// within each block of the vector is reversed.)
4775 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4776 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4777 "Only possible block sizes for REV are: 16, 32, 64");
4779 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4783 unsigned NumElts = VT.getVectorNumElements();
4784 unsigned BlockElts = M[0] + 1;
4785 // If the first shuffle index is UNDEF, be optimistic.
4787 BlockElts = BlockSize / EltSz;
4789 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4792 for (unsigned i = 0; i < NumElts; ++i) {
4794 continue; // ignore UNDEF indices
4795 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4802 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4803 unsigned NumElts = VT.getVectorNumElements();
4804 WhichResult = (M[0] == 0 ? 0 : 1);
4805 unsigned Idx = WhichResult * NumElts / 2;
4806 for (unsigned i = 0; i != NumElts; i += 2) {
4807 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4808 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4816 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4817 unsigned NumElts = VT.getVectorNumElements();
4818 WhichResult = (M[0] == 0 ? 0 : 1);
4819 for (unsigned i = 0; i != NumElts; ++i) {
4821 continue; // ignore UNDEF indices
4822 if ((unsigned)M[i] != 2 * i + WhichResult)
4829 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4830 unsigned NumElts = VT.getVectorNumElements();
4831 WhichResult = (M[0] == 0 ? 0 : 1);
4832 for (unsigned i = 0; i < NumElts; i += 2) {
4833 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4834 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4840 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4841 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4842 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4843 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4844 unsigned NumElts = VT.getVectorNumElements();
4845 WhichResult = (M[0] == 0 ? 0 : 1);
4846 unsigned Idx = WhichResult * NumElts / 2;
4847 for (unsigned i = 0; i != NumElts; i += 2) {
4848 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4849 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4857 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4858 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4859 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4860 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4861 unsigned Half = VT.getVectorNumElements() / 2;
4862 WhichResult = (M[0] == 0 ? 0 : 1);
4863 for (unsigned j = 0; j != 2; ++j) {
4864 unsigned Idx = WhichResult;
4865 for (unsigned i = 0; i != Half; ++i) {
4866 int MIdx = M[i + j * Half];
4867 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4876 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4877 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4878 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4879 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4880 unsigned NumElts = VT.getVectorNumElements();
4881 WhichResult = (M[0] == 0 ? 0 : 1);
4882 for (unsigned i = 0; i < NumElts; i += 2) {
4883 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4884 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4890 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4891 bool &DstIsLeft, int &Anomaly) {
4892 if (M.size() != static_cast<size_t>(NumInputElements))
4895 int NumLHSMatch = 0, NumRHSMatch = 0;
4896 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4898 for (int i = 0; i < NumInputElements; ++i) {
4908 LastLHSMismatch = i;
4910 if (M[i] == i + NumInputElements)
4913 LastRHSMismatch = i;
4916 if (NumLHSMatch == NumInputElements - 1) {
4918 Anomaly = LastLHSMismatch;
4920 } else if (NumRHSMatch == NumInputElements - 1) {
4922 Anomaly = LastRHSMismatch;
4929 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4930 if (VT.getSizeInBits() != 128)
4933 unsigned NumElts = VT.getVectorNumElements();
4935 for (int I = 0, E = NumElts / 2; I != E; I++) {
4940 int Offset = NumElts / 2;
4941 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4942 if (Mask[I] != I + SplitLHS * Offset)
4949 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4951 EVT VT = Op.getValueType();
4952 SDValue V0 = Op.getOperand(0);
4953 SDValue V1 = Op.getOperand(1);
4954 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4956 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4957 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4960 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4962 if (!isConcatMask(Mask, VT, SplitV0))
4965 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4966 VT.getVectorNumElements() / 2);
4968 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4969 DAG.getConstant(0, DL, MVT::i64));
4971 if (V1.getValueType().getSizeInBits() == 128) {
4972 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4973 DAG.getConstant(0, DL, MVT::i64));
4975 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4978 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4979 /// the specified operations to build the shuffle.
4980 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4981 SDValue RHS, SelectionDAG &DAG,
4983 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4984 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4985 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4988 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4997 OP_VUZPL, // VUZP, left result
4998 OP_VUZPR, // VUZP, right result
4999 OP_VZIPL, // VZIP, left result
5000 OP_VZIPR, // VZIP, right result
5001 OP_VTRNL, // VTRN, left result
5002 OP_VTRNR // VTRN, right result
5005 if (OpNum == OP_COPY) {
5006 if (LHSID == (1 * 9 + 2) * 9 + 3)
5008 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5012 SDValue OpLHS, OpRHS;
5013 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5014 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5015 EVT VT = OpLHS.getValueType();
5019 llvm_unreachable("Unknown shuffle opcode!");
5021 // VREV divides the vector in half and swaps within the half.
5022 if (VT.getVectorElementType() == MVT::i32 ||
5023 VT.getVectorElementType() == MVT::f32)
5024 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5025 // vrev <4 x i16> -> REV32
5026 if (VT.getVectorElementType() == MVT::i16 ||
5027 VT.getVectorElementType() == MVT::f16)
5028 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5029 // vrev <4 x i8> -> REV16
5030 assert(VT.getVectorElementType() == MVT::i8);
5031 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5036 EVT EltTy = VT.getVectorElementType();
5038 if (EltTy == MVT::i8)
5039 Opcode = AArch64ISD::DUPLANE8;
5040 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
5041 Opcode = AArch64ISD::DUPLANE16;
5042 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5043 Opcode = AArch64ISD::DUPLANE32;
5044 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5045 Opcode = AArch64ISD::DUPLANE64;
5047 llvm_unreachable("Invalid vector element type?");
5049 if (VT.getSizeInBits() == 64)
5050 OpLHS = WidenVector(OpLHS, DAG);
5051 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
5052 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5057 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5058 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5059 DAG.getConstant(Imm, dl, MVT::i32));
5062 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5065 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5068 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5071 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5074 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5077 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5082 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5083 SelectionDAG &DAG) {
5084 // Check to see if we can use the TBL instruction.
5085 SDValue V1 = Op.getOperand(0);
5086 SDValue V2 = Op.getOperand(1);
5089 EVT EltVT = Op.getValueType().getVectorElementType();
5090 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5092 SmallVector<SDValue, 8> TBLMask;
5093 for (int Val : ShuffleMask) {
5094 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5095 unsigned Offset = Byte + Val * BytesPerElt;
5096 TBLMask.push_back(DAG.getConstant(Offset, DL, MVT::i32));
5100 MVT IndexVT = MVT::v8i8;
5101 unsigned IndexLen = 8;
5102 if (Op.getValueType().getSizeInBits() == 128) {
5103 IndexVT = MVT::v16i8;
5107 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5108 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5111 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5113 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5114 Shuffle = DAG.getNode(
5115 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5116 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5117 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5118 makeArrayRef(TBLMask.data(), IndexLen)));
5120 if (IndexLen == 8) {
5121 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5122 Shuffle = DAG.getNode(
5123 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5124 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst,
5125 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5126 makeArrayRef(TBLMask.data(), IndexLen)));
5128 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5129 // cannot currently represent the register constraints on the input
5131 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5132 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5133 // &TBLMask[0], IndexLen));
5134 Shuffle = DAG.getNode(
5135 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5136 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32),
5138 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5139 makeArrayRef(TBLMask.data(), IndexLen)));
5142 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5145 static unsigned getDUPLANEOp(EVT EltType) {
5146 if (EltType == MVT::i8)
5147 return AArch64ISD::DUPLANE8;
5148 if (EltType == MVT::i16 || EltType == MVT::f16)
5149 return AArch64ISD::DUPLANE16;
5150 if (EltType == MVT::i32 || EltType == MVT::f32)
5151 return AArch64ISD::DUPLANE32;
5152 if (EltType == MVT::i64 || EltType == MVT::f64)
5153 return AArch64ISD::DUPLANE64;
5155 llvm_unreachable("Invalid vector element type?");
5158 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5159 SelectionDAG &DAG) const {
5161 EVT VT = Op.getValueType();
5163 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5165 // Convert shuffles that are directly supported on NEON to target-specific
5166 // DAG nodes, instead of keeping them as shuffles and matching them again
5167 // during code selection. This is more efficient and avoids the possibility
5168 // of inconsistencies between legalization and selection.
5169 ArrayRef<int> ShuffleMask = SVN->getMask();
5171 SDValue V1 = Op.getOperand(0);
5172 SDValue V2 = Op.getOperand(1);
5174 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5175 V1.getValueType().getSimpleVT())) {
5176 int Lane = SVN->getSplatIndex();
5177 // If this is undef splat, generate it via "just" vdup, if possible.
5181 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5182 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5184 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5185 // constant. If so, we can just reference the lane's definition directly.
5186 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5187 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5188 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5190 // Otherwise, duplicate from the lane of the input vector.
5191 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5193 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5194 // to make a vector of the same size as this SHUFFLE. We can ignore the
5195 // extract entirely, and canonicalise the concat using WidenVector.
5196 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5197 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5198 V1 = V1.getOperand(0);
5199 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5200 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5201 Lane -= Idx * VT.getVectorNumElements() / 2;
5202 V1 = WidenVector(V1.getOperand(Idx), DAG);
5203 } else if (VT.getSizeInBits() == 64)
5204 V1 = WidenVector(V1, DAG);
5206 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64));
5209 if (isREVMask(ShuffleMask, VT, 64))
5210 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5211 if (isREVMask(ShuffleMask, VT, 32))
5212 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5213 if (isREVMask(ShuffleMask, VT, 16))
5214 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5216 bool ReverseEXT = false;
5218 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5221 Imm *= getExtFactor(V1);
5222 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5223 DAG.getConstant(Imm, dl, MVT::i32));
5224 } else if (V2->getOpcode() == ISD::UNDEF &&
5225 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5226 Imm *= getExtFactor(V1);
5227 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5228 DAG.getConstant(Imm, dl, MVT::i32));
5231 unsigned WhichResult;
5232 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5233 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5234 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5236 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5237 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5238 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5240 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5241 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5242 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5245 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5246 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5247 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5249 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5250 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5251 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5253 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5254 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5255 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5258 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5259 if (Concat.getNode())
5264 int NumInputElements = V1.getValueType().getVectorNumElements();
5265 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5266 SDValue DstVec = DstIsLeft ? V1 : V2;
5267 SDValue DstLaneV = DAG.getConstant(Anomaly, dl, MVT::i64);
5269 SDValue SrcVec = V1;
5270 int SrcLane = ShuffleMask[Anomaly];
5271 if (SrcLane >= NumInputElements) {
5273 SrcLane -= VT.getVectorNumElements();
5275 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64);
5277 EVT ScalarVT = VT.getVectorElementType();
5279 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5280 ScalarVT = MVT::i32;
5283 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5284 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5288 // If the shuffle is not directly supported and it has 4 elements, use
5289 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5290 unsigned NumElts = VT.getVectorNumElements();
5292 unsigned PFIndexes[4];
5293 for (unsigned i = 0; i != 4; ++i) {
5294 if (ShuffleMask[i] < 0)
5297 PFIndexes[i] = ShuffleMask[i];
5300 // Compute the index in the perfect shuffle table.
5301 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5302 PFIndexes[2] * 9 + PFIndexes[3];
5303 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5304 unsigned Cost = (PFEntry >> 30);
5307 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5310 return GenerateTBL(Op, ShuffleMask, DAG);
5313 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5315 EVT VT = BVN->getValueType(0);
5316 APInt SplatBits, SplatUndef;
5317 unsigned SplatBitSize;
5319 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5320 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5322 for (unsigned i = 0; i < NumSplats; ++i) {
5323 CnstBits <<= SplatBitSize;
5324 UndefBits <<= SplatBitSize;
5325 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5326 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5335 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5336 SelectionDAG &DAG) const {
5337 BuildVectorSDNode *BVN =
5338 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5339 SDValue LHS = Op.getOperand(0);
5341 EVT VT = Op.getValueType();
5346 APInt CnstBits(VT.getSizeInBits(), 0);
5347 APInt UndefBits(VT.getSizeInBits(), 0);
5348 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5349 // We only have BIC vector immediate instruction, which is and-not.
5350 CnstBits = ~CnstBits;
5352 // We make use of a little bit of goto ickiness in order to avoid having to
5353 // duplicate the immediate matching logic for the undef toggled case.
5354 bool SecondTry = false;
5357 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5358 CnstBits = CnstBits.zextOrTrunc(64);
5359 uint64_t CnstVal = CnstBits.getZExtValue();
5361 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5362 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5363 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5364 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5365 DAG.getConstant(CnstVal, dl, MVT::i32),
5366 DAG.getConstant(0, dl, MVT::i32));
5367 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5370 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5371 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5372 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5373 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5374 DAG.getConstant(CnstVal, dl, MVT::i32),
5375 DAG.getConstant(8, dl, MVT::i32));
5376 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5379 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5380 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5381 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5382 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5383 DAG.getConstant(CnstVal, dl, MVT::i32),
5384 DAG.getConstant(16, dl, MVT::i32));
5385 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5388 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5389 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5390 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5391 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5392 DAG.getConstant(CnstVal, dl, MVT::i32),
5393 DAG.getConstant(24, dl, MVT::i32));
5394 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5397 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5398 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5399 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5400 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5401 DAG.getConstant(CnstVal, dl, MVT::i32),
5402 DAG.getConstant(0, dl, MVT::i32));
5403 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5406 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5407 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5408 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5409 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5410 DAG.getConstant(CnstVal, dl, MVT::i32),
5411 DAG.getConstant(8, dl, MVT::i32));
5412 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5419 CnstBits = ~UndefBits;
5423 // We can always fall back to a non-immediate AND.
5428 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5429 // consists of only the same constant int value, returned in reference arg
5431 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5432 uint64_t &ConstVal) {
5433 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5436 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5439 EVT VT = Bvec->getValueType(0);
5440 unsigned NumElts = VT.getVectorNumElements();
5441 for (unsigned i = 1; i < NumElts; ++i)
5442 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5444 ConstVal = FirstElt->getZExtValue();
5448 static unsigned getIntrinsicID(const SDNode *N) {
5449 unsigned Opcode = N->getOpcode();
5452 return Intrinsic::not_intrinsic;
5453 case ISD::INTRINSIC_WO_CHAIN: {
5454 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5455 if (IID < Intrinsic::num_intrinsics)
5457 return Intrinsic::not_intrinsic;
5462 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5463 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5464 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5465 // Also, logical shift right -> sri, with the same structure.
5466 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5467 EVT VT = N->getValueType(0);
5474 // Is the first op an AND?
5475 const SDValue And = N->getOperand(0);
5476 if (And.getOpcode() != ISD::AND)
5479 // Is the second op an shl or lshr?
5480 SDValue Shift = N->getOperand(1);
5481 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5482 // or AArch64ISD::VLSHR vector, #shift
5483 unsigned ShiftOpc = Shift.getOpcode();
5484 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5486 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5488 // Is the shift amount constant?
5489 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5493 // Is the and mask vector all constant?
5495 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5498 // Is C1 == ~C2, taking into account how much one can shift elements of a
5500 uint64_t C2 = C2node->getZExtValue();
5501 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5502 if (C2 > ElemSizeInBits)
5504 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5505 if ((C1 & ElemMask) != (~C2 & ElemMask))
5508 SDValue X = And.getOperand(0);
5509 SDValue Y = Shift.getOperand(0);
5512 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5514 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5515 DAG.getConstant(Intrin, DL, MVT::i32), X, Y,
5516 Shift.getOperand(1));
5518 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5519 DEBUG(N->dump(&DAG));
5520 DEBUG(dbgs() << "into: \n");
5521 DEBUG(ResultSLI->dump(&DAG));
5527 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5528 SelectionDAG &DAG) const {
5529 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5530 if (EnableAArch64SlrGeneration) {
5531 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5536 BuildVectorSDNode *BVN =
5537 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5538 SDValue LHS = Op.getOperand(1);
5540 EVT VT = Op.getValueType();
5542 // OR commutes, so try swapping the operands.
5544 LHS = Op.getOperand(0);
5545 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5550 APInt CnstBits(VT.getSizeInBits(), 0);
5551 APInt UndefBits(VT.getSizeInBits(), 0);
5552 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5553 // We make use of a little bit of goto ickiness in order to avoid having to
5554 // duplicate the immediate matching logic for the undef toggled case.
5555 bool SecondTry = false;
5558 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5559 CnstBits = CnstBits.zextOrTrunc(64);
5560 uint64_t CnstVal = CnstBits.getZExtValue();
5562 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5563 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5564 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5565 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5566 DAG.getConstant(CnstVal, dl, MVT::i32),
5567 DAG.getConstant(0, dl, MVT::i32));
5568 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5571 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5572 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5573 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5574 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5575 DAG.getConstant(CnstVal, dl, MVT::i32),
5576 DAG.getConstant(8, dl, MVT::i32));
5577 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5580 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5581 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5582 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5583 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5584 DAG.getConstant(CnstVal, dl, MVT::i32),
5585 DAG.getConstant(16, dl, MVT::i32));
5586 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5589 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5590 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5591 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5592 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5593 DAG.getConstant(CnstVal, dl, MVT::i32),
5594 DAG.getConstant(24, dl, MVT::i32));
5595 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5598 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5599 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5600 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5601 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5602 DAG.getConstant(CnstVal, dl, MVT::i32),
5603 DAG.getConstant(0, dl, MVT::i32));
5604 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5607 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5608 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5609 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5610 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5611 DAG.getConstant(CnstVal, dl, MVT::i32),
5612 DAG.getConstant(8, dl, MVT::i32));
5613 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5620 CnstBits = UndefBits;
5624 // We can always fall back to a non-immediate OR.
5629 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5630 // be truncated to fit element width.
5631 static SDValue NormalizeBuildVector(SDValue Op,
5632 SelectionDAG &DAG) {
5633 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5635 EVT VT = Op.getValueType();
5636 EVT EltTy= VT.getVectorElementType();
5638 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5641 SmallVector<SDValue, 16> Ops;
5642 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5643 SDValue Lane = Op.getOperand(I);
5644 if (Lane.getOpcode() == ISD::Constant) {
5645 APInt LowBits(EltTy.getSizeInBits(),
5646 cast<ConstantSDNode>(Lane)->getZExtValue());
5647 Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
5649 Ops.push_back(Lane);
5651 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5654 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5655 SelectionDAG &DAG) const {
5657 EVT VT = Op.getValueType();
5658 Op = NormalizeBuildVector(Op, DAG);
5659 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5661 APInt CnstBits(VT.getSizeInBits(), 0);
5662 APInt UndefBits(VT.getSizeInBits(), 0);
5663 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5664 // We make use of a little bit of goto ickiness in order to avoid having to
5665 // duplicate the immediate matching logic for the undef toggled case.
5666 bool SecondTry = false;
5669 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5670 CnstBits = CnstBits.zextOrTrunc(64);
5671 uint64_t CnstVal = CnstBits.getZExtValue();
5673 // Certain magic vector constants (used to express things like NOT
5674 // and NEG) are passed through unmodified. This allows codegen patterns
5675 // for these operations to match. Special-purpose patterns will lower
5676 // these immediates to MOVIs if it proves necessary.
5677 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5680 // The many faces of MOVI...
5681 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5682 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5683 if (VT.getSizeInBits() == 128) {
5684 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5685 DAG.getConstant(CnstVal, dl, MVT::i32));
5686 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5689 // Support the V64 version via subregister insertion.
5690 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5691 DAG.getConstant(CnstVal, dl, MVT::i32));
5692 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5695 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5696 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5697 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5698 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5699 DAG.getConstant(CnstVal, dl, MVT::i32),
5700 DAG.getConstant(0, dl, MVT::i32));
5701 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5704 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5705 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5706 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5707 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5708 DAG.getConstant(CnstVal, dl, MVT::i32),
5709 DAG.getConstant(8, dl, MVT::i32));
5710 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5713 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5714 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5715 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5716 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5717 DAG.getConstant(CnstVal, dl, MVT::i32),
5718 DAG.getConstant(16, dl, MVT::i32));
5719 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5722 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5723 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5724 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5725 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5726 DAG.getConstant(CnstVal, dl, MVT::i32),
5727 DAG.getConstant(24, dl, MVT::i32));
5728 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5731 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5732 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5733 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5734 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5735 DAG.getConstant(CnstVal, dl, MVT::i32),
5736 DAG.getConstant(0, dl, MVT::i32));
5737 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5740 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5741 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5742 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5743 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5744 DAG.getConstant(CnstVal, dl, MVT::i32),
5745 DAG.getConstant(8, dl, MVT::i32));
5746 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5749 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5750 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5751 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5752 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5753 DAG.getConstant(CnstVal, dl, MVT::i32),
5754 DAG.getConstant(264, dl, MVT::i32));
5755 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5758 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5759 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5760 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5761 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5762 DAG.getConstant(CnstVal, dl, MVT::i32),
5763 DAG.getConstant(272, dl, MVT::i32));
5764 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5767 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5768 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5769 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5770 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5771 DAG.getConstant(CnstVal, dl, MVT::i32));
5772 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5775 // The few faces of FMOV...
5776 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5777 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5778 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5779 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5780 DAG.getConstant(CnstVal, dl, MVT::i32));
5781 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5784 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5785 VT.getSizeInBits() == 128) {
5786 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5787 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5788 DAG.getConstant(CnstVal, dl, MVT::i32));
5789 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5792 // The many faces of MVNI...
5794 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5795 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5796 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5797 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5798 DAG.getConstant(CnstVal, dl, MVT::i32),
5799 DAG.getConstant(0, dl, MVT::i32));
5800 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5803 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5804 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5805 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5806 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5807 DAG.getConstant(CnstVal, dl, MVT::i32),
5808 DAG.getConstant(8, dl, MVT::i32));
5809 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5812 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5813 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5814 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5815 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5816 DAG.getConstant(CnstVal, dl, MVT::i32),
5817 DAG.getConstant(16, dl, MVT::i32));
5818 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5821 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5822 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5823 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5824 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5825 DAG.getConstant(CnstVal, dl, MVT::i32),
5826 DAG.getConstant(24, dl, MVT::i32));
5827 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5830 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5831 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5832 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5833 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5834 DAG.getConstant(CnstVal, dl, MVT::i32),
5835 DAG.getConstant(0, dl, MVT::i32));
5836 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5839 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5840 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5841 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5842 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5843 DAG.getConstant(CnstVal, dl, MVT::i32),
5844 DAG.getConstant(8, dl, MVT::i32));
5845 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5848 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5849 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5850 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5851 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5852 DAG.getConstant(CnstVal, dl, MVT::i32),
5853 DAG.getConstant(264, dl, MVT::i32));
5854 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5857 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5858 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5859 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5860 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5861 DAG.getConstant(CnstVal, dl, MVT::i32),
5862 DAG.getConstant(272, dl, MVT::i32));
5863 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5870 CnstBits = UndefBits;
5875 // Scan through the operands to find some interesting properties we can
5877 // 1) If only one value is used, we can use a DUP, or
5878 // 2) if only the low element is not undef, we can just insert that, or
5879 // 3) if only one constant value is used (w/ some non-constant lanes),
5880 // we can splat the constant value into the whole vector then fill
5881 // in the non-constant lanes.
5882 // 4) FIXME: If different constant values are used, but we can intelligently
5883 // select the values we'll be overwriting for the non-constant
5884 // lanes such that we can directly materialize the vector
5885 // some other way (MOVI, e.g.), we can be sneaky.
5886 unsigned NumElts = VT.getVectorNumElements();
5887 bool isOnlyLowElement = true;
5888 bool usesOnlyOneValue = true;
5889 bool usesOnlyOneConstantValue = true;
5890 bool isConstant = true;
5891 unsigned NumConstantLanes = 0;
5893 SDValue ConstantValue;
5894 for (unsigned i = 0; i < NumElts; ++i) {
5895 SDValue V = Op.getOperand(i);
5896 if (V.getOpcode() == ISD::UNDEF)
5899 isOnlyLowElement = false;
5900 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5903 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5905 if (!ConstantValue.getNode())
5907 else if (ConstantValue != V)
5908 usesOnlyOneConstantValue = false;
5911 if (!Value.getNode())
5913 else if (V != Value)
5914 usesOnlyOneValue = false;
5917 if (!Value.getNode())
5918 return DAG.getUNDEF(VT);
5920 if (isOnlyLowElement)
5921 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5923 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5924 // i32 and try again.
5925 if (usesOnlyOneValue) {
5927 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5928 Value.getValueType() != VT)
5929 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5931 // This is actually a DUPLANExx operation, which keeps everything vectory.
5933 // DUPLANE works on 128-bit vectors, widen it if necessary.
5934 SDValue Lane = Value.getOperand(1);
5935 Value = Value.getOperand(0);
5936 if (Value.getValueType().getSizeInBits() == 64)
5937 Value = WidenVector(Value, DAG);
5939 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5940 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5943 if (VT.getVectorElementType().isFloatingPoint()) {
5944 SmallVector<SDValue, 8> Ops;
5945 EVT EltTy = VT.getVectorElementType();
5946 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
5947 "Unsupported floating-point vector type");
5948 MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
5949 for (unsigned i = 0; i < NumElts; ++i)
5950 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5951 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5952 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5953 Val = LowerBUILD_VECTOR(Val, DAG);
5955 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5959 // If there was only one constant value used and for more than one lane,
5960 // start by splatting that value, then replace the non-constant lanes. This
5961 // is better than the default, which will perform a separate initialization
5963 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5964 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5965 // Now insert the non-constant lanes.
5966 for (unsigned i = 0; i < NumElts; ++i) {
5967 SDValue V = Op.getOperand(i);
5968 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
5969 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5970 // Note that type legalization likely mucked about with the VT of the
5971 // source operand, so we may have to convert it here before inserting.
5972 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5978 // If all elements are constants and the case above didn't get hit, fall back
5979 // to the default expansion, which will generate a load from the constant
5984 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5986 SDValue shuffle = ReconstructShuffle(Op, DAG);
5987 if (shuffle != SDValue())
5991 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5992 // know the default expansion would otherwise fall back on something even
5993 // worse. For a vector with one or two non-undef values, that's
5994 // scalar_to_vector for the elements followed by a shuffle (provided the
5995 // shuffle is valid for the target) and materialization element by element
5996 // on the stack followed by a load for everything else.
5997 if (!isConstant && !usesOnlyOneValue) {
5998 SDValue Vec = DAG.getUNDEF(VT);
5999 SDValue Op0 = Op.getOperand(0);
6000 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
6002 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
6003 // a) Avoid a RMW dependency on the full vector register, and
6004 // b) Allow the register coalescer to fold away the copy if the
6005 // value is already in an S or D register.
6006 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6007 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6009 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6010 DAG.getTargetConstant(SubIdx, dl, MVT::i32));
6011 Vec = SDValue(N, 0);
6014 for (; i < NumElts; ++i) {
6015 SDValue V = Op.getOperand(i);
6016 if (V.getOpcode() == ISD::UNDEF)
6018 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
6019 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6024 // Just use the default expansion. We failed to find a better alternative.
6028 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6029 SelectionDAG &DAG) const {
6030 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6032 // Check for non-constant or out of range lane.
6033 EVT VT = Op.getOperand(0).getValueType();
6034 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6035 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6039 // Insertion/extraction are legal for V128 types.
6040 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6041 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6045 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6046 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6049 // For V64 types, we perform insertion by expanding the value
6050 // to a V128 type and perform the insertion on that.
6052 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6053 EVT WideTy = WideVec.getValueType();
6055 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6056 Op.getOperand(1), Op.getOperand(2));
6057 // Re-narrow the resultant vector.
6058 return NarrowVector(Node, DAG);
6062 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6063 SelectionDAG &DAG) const {
6064 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6066 // Check for non-constant or out of range lane.
6067 EVT VT = Op.getOperand(0).getValueType();
6068 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6069 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6073 // Insertion/extraction are legal for V128 types.
6074 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6075 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6079 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6080 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6083 // For V64 types, we perform extraction by expanding the value
6084 // to a V128 type and perform the extraction on that.
6086 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6087 EVT WideTy = WideVec.getValueType();
6089 EVT ExtrTy = WideTy.getVectorElementType();
6090 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6093 // For extractions, we just return the result directly.
6094 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6098 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6099 SelectionDAG &DAG) const {
6100 EVT VT = Op.getOperand(0).getValueType();
6106 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6109 unsigned Val = Cst->getZExtValue();
6111 unsigned Size = Op.getValueType().getSizeInBits();
6115 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6118 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6121 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6124 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6127 llvm_unreachable("Unexpected vector type in extract_subvector!");
6130 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6132 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6138 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6140 if (VT.getVectorNumElements() == 4 &&
6141 (VT.is128BitVector() || VT.is64BitVector())) {
6142 unsigned PFIndexes[4];
6143 for (unsigned i = 0; i != 4; ++i) {
6147 PFIndexes[i] = M[i];
6150 // Compute the index in the perfect shuffle table.
6151 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6152 PFIndexes[2] * 9 + PFIndexes[3];
6153 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6154 unsigned Cost = (PFEntry >> 30);
6162 unsigned DummyUnsigned;
6164 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6165 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6166 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6167 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6168 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6169 isZIPMask(M, VT, DummyUnsigned) ||
6170 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6171 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6172 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6173 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6174 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6177 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6178 /// operand of a vector shift operation, where all the elements of the
6179 /// build_vector must have the same constant integer value.
6180 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6181 // Ignore bit_converts.
6182 while (Op.getOpcode() == ISD::BITCAST)
6183 Op = Op.getOperand(0);
6184 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6185 APInt SplatBits, SplatUndef;
6186 unsigned SplatBitSize;
6188 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6189 HasAnyUndefs, ElementBits) ||
6190 SplatBitSize > ElementBits)
6192 Cnt = SplatBits.getSExtValue();
6196 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6197 /// operand of a vector shift left operation. That value must be in the range:
6198 /// 0 <= Value < ElementBits for a left shift; or
6199 /// 0 <= Value <= ElementBits for a long left shift.
6200 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6201 assert(VT.isVector() && "vector shift count is not a vector type");
6202 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6203 if (!getVShiftImm(Op, ElementBits, Cnt))
6205 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6208 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6209 /// operand of a vector shift right operation. For a shift opcode, the value
6210 /// is positive, but for an intrinsic the value count must be negative. The
6211 /// absolute value must be in the range:
6212 /// 1 <= |Value| <= ElementBits for a right shift; or
6213 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6214 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6216 assert(VT.isVector() && "vector shift count is not a vector type");
6217 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6218 if (!getVShiftImm(Op, ElementBits, Cnt))
6222 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6225 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6226 SelectionDAG &DAG) const {
6227 EVT VT = Op.getValueType();
6231 if (!Op.getOperand(1).getValueType().isVector())
6233 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6235 switch (Op.getOpcode()) {
6237 llvm_unreachable("unexpected shift opcode");
6240 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6241 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
6242 DAG.getConstant(Cnt, DL, MVT::i32));
6243 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6244 DAG.getConstant(Intrinsic::aarch64_neon_ushl, DL,
6246 Op.getOperand(0), Op.getOperand(1));
6249 // Right shift immediate
6250 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6253 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6254 return DAG.getNode(Opc, DL, VT, Op.getOperand(0),
6255 DAG.getConstant(Cnt, DL, MVT::i32));
6258 // Right shift register. Note, there is not a shift right register
6259 // instruction, but the shift left register instruction takes a signed
6260 // value, where negative numbers specify a right shift.
6261 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6262 : Intrinsic::aarch64_neon_ushl;
6263 // negate the shift amount
6264 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6265 SDValue NegShiftLeft =
6266 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6267 DAG.getConstant(Opc, DL, MVT::i32), Op.getOperand(0),
6269 return NegShiftLeft;
6275 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6276 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6277 SDLoc dl, SelectionDAG &DAG) {
6278 EVT SrcVT = LHS.getValueType();
6279 assert(VT.getSizeInBits() == SrcVT.getSizeInBits() &&
6280 "function only supposed to emit natural comparisons");
6282 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6283 APInt CnstBits(VT.getSizeInBits(), 0);
6284 APInt UndefBits(VT.getSizeInBits(), 0);
6285 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6286 bool IsZero = IsCnst && (CnstBits == 0);
6288 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6292 case AArch64CC::NE: {
6295 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6297 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6298 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6302 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6303 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6306 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6307 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6310 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6311 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6314 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6315 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6319 // If we ignore NaNs then we can use to the MI implementation.
6323 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6324 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6331 case AArch64CC::NE: {
6334 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6336 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6337 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6341 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6342 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6345 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6346 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6349 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6350 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6353 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6354 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6356 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6358 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6361 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6362 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6364 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6366 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6370 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6371 SelectionDAG &DAG) const {
6372 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6373 SDValue LHS = Op.getOperand(0);
6374 SDValue RHS = Op.getOperand(1);
6375 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
6378 if (LHS.getValueType().getVectorElementType().isInteger()) {
6379 assert(LHS.getValueType() == RHS.getValueType());
6380 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6382 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
6383 return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6386 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6387 LHS.getValueType().getVectorElementType() == MVT::f64);
6389 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6390 // clean. Some of them require two branches to implement.
6391 AArch64CC::CondCode CC1, CC2;
6393 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6395 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6397 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG);
6401 if (CC2 != AArch64CC::AL) {
6403 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG);
6404 if (!Cmp2.getNode())
6407 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
6410 Cmp = DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
6413 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6418 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6419 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6420 /// specified in the intrinsic calls.
6421 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6423 unsigned Intrinsic) const {
6424 switch (Intrinsic) {
6425 case Intrinsic::aarch64_neon_ld2:
6426 case Intrinsic::aarch64_neon_ld3:
6427 case Intrinsic::aarch64_neon_ld4:
6428 case Intrinsic::aarch64_neon_ld1x2:
6429 case Intrinsic::aarch64_neon_ld1x3:
6430 case Intrinsic::aarch64_neon_ld1x4:
6431 case Intrinsic::aarch64_neon_ld2lane:
6432 case Intrinsic::aarch64_neon_ld3lane:
6433 case Intrinsic::aarch64_neon_ld4lane:
6434 case Intrinsic::aarch64_neon_ld2r:
6435 case Intrinsic::aarch64_neon_ld3r:
6436 case Intrinsic::aarch64_neon_ld4r: {
6437 Info.opc = ISD::INTRINSIC_W_CHAIN;
6438 // Conservatively set memVT to the entire set of vectors loaded.
6439 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6440 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6441 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6444 Info.vol = false; // volatile loads with NEON intrinsics not supported
6445 Info.readMem = true;
6446 Info.writeMem = false;
6449 case Intrinsic::aarch64_neon_st2:
6450 case Intrinsic::aarch64_neon_st3:
6451 case Intrinsic::aarch64_neon_st4:
6452 case Intrinsic::aarch64_neon_st1x2:
6453 case Intrinsic::aarch64_neon_st1x3:
6454 case Intrinsic::aarch64_neon_st1x4:
6455 case Intrinsic::aarch64_neon_st2lane:
6456 case Intrinsic::aarch64_neon_st3lane:
6457 case Intrinsic::aarch64_neon_st4lane: {
6458 Info.opc = ISD::INTRINSIC_VOID;
6459 // Conservatively set memVT to the entire set of vectors stored.
6460 unsigned NumElts = 0;
6461 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6462 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6463 if (!ArgTy->isVectorTy())
6465 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6467 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6468 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6471 Info.vol = false; // volatile stores with NEON intrinsics not supported
6472 Info.readMem = false;
6473 Info.writeMem = true;
6476 case Intrinsic::aarch64_ldaxr:
6477 case Intrinsic::aarch64_ldxr: {
6478 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6479 Info.opc = ISD::INTRINSIC_W_CHAIN;
6480 Info.memVT = MVT::getVT(PtrTy->getElementType());
6481 Info.ptrVal = I.getArgOperand(0);
6483 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6485 Info.readMem = true;
6486 Info.writeMem = false;
6489 case Intrinsic::aarch64_stlxr:
6490 case Intrinsic::aarch64_stxr: {
6491 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6492 Info.opc = ISD::INTRINSIC_W_CHAIN;
6493 Info.memVT = MVT::getVT(PtrTy->getElementType());
6494 Info.ptrVal = I.getArgOperand(1);
6496 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6498 Info.readMem = false;
6499 Info.writeMem = true;
6502 case Intrinsic::aarch64_ldaxp:
6503 case Intrinsic::aarch64_ldxp: {
6504 Info.opc = ISD::INTRINSIC_W_CHAIN;
6505 Info.memVT = MVT::i128;
6506 Info.ptrVal = I.getArgOperand(0);
6510 Info.readMem = true;
6511 Info.writeMem = false;
6514 case Intrinsic::aarch64_stlxp:
6515 case Intrinsic::aarch64_stxp: {
6516 Info.opc = ISD::INTRINSIC_W_CHAIN;
6517 Info.memVT = MVT::i128;
6518 Info.ptrVal = I.getArgOperand(2);
6522 Info.readMem = false;
6523 Info.writeMem = true;
6533 // Truncations from 64-bit GPR to 32-bit GPR is free.
6534 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6535 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6537 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6538 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6539 return NumBits1 > NumBits2;
6541 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6542 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6544 unsigned NumBits1 = VT1.getSizeInBits();
6545 unsigned NumBits2 = VT2.getSizeInBits();
6546 return NumBits1 > NumBits2;
6549 /// Check if it is profitable to hoist instruction in then/else to if.
6550 /// Not profitable if I and it's user can form a FMA instruction
6551 /// because we prefer FMSUB/FMADD.
6552 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6553 if (I->getOpcode() != Instruction::FMul)
6556 if (I->getNumUses() != 1)
6559 Instruction *User = I->user_back();
6562 !(User->getOpcode() == Instruction::FSub ||
6563 User->getOpcode() == Instruction::FAdd))
6566 const TargetOptions &Options = getTargetMachine().Options;
6567 EVT VT = getValueType(User->getOperand(0)->getType());
6569 if (isFMAFasterThanFMulAndFAdd(VT) &&
6570 isOperationLegalOrCustom(ISD::FMA, VT) &&
6571 (Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath))
6577 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6579 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6580 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6582 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6583 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6584 return NumBits1 == 32 && NumBits2 == 64;
6586 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6587 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6589 unsigned NumBits1 = VT1.getSizeInBits();
6590 unsigned NumBits2 = VT2.getSizeInBits();
6591 return NumBits1 == 32 && NumBits2 == 64;
6594 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6595 EVT VT1 = Val.getValueType();
6596 if (isZExtFree(VT1, VT2)) {
6600 if (Val.getOpcode() != ISD::LOAD)
6603 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6604 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6605 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6606 VT1.getSizeInBits() <= 32);
6609 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
6610 if (isa<FPExtInst>(Ext))
6613 // Vector types are next free.
6614 if (Ext->getType()->isVectorTy())
6617 for (const Use &U : Ext->uses()) {
6618 // The extension is free if we can fold it with a left shift in an
6619 // addressing mode or an arithmetic operation: add, sub, and cmp.
6621 // Is there a shift?
6622 const Instruction *Instr = cast<Instruction>(U.getUser());
6624 // Is this a constant shift?
6625 switch (Instr->getOpcode()) {
6626 case Instruction::Shl:
6627 if (!isa<ConstantInt>(Instr->getOperand(1)))
6630 case Instruction::GetElementPtr: {
6631 gep_type_iterator GTI = gep_type_begin(Instr);
6632 std::advance(GTI, U.getOperandNo());
6634 // This extension will end up with a shift because of the scaling factor.
6635 // 8-bit sized types have a scaling factor of 1, thus a shift amount of 0.
6636 // Get the shift amount based on the scaling factor:
6637 // log2(sizeof(IdxTy)) - log2(8).
6639 countTrailingZeros(getDataLayout()->getTypeStoreSizeInBits(IdxTy)) - 3;
6640 // Is the constant foldable in the shift of the addressing mode?
6641 // I.e., shift amount is between 1 and 4 inclusive.
6642 if (ShiftAmt == 0 || ShiftAmt > 4)
6646 case Instruction::Trunc:
6647 // Check if this is a noop.
6648 // trunc(sext ty1 to ty2) to ty1.
6649 if (Instr->getType() == Ext->getOperand(0)->getType())
6656 // At this point we can use the bfm family, so this extension is free
6662 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6663 unsigned &RequiredAligment) const {
6664 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6666 // Cyclone supports unaligned accesses.
6667 RequiredAligment = 0;
6668 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6669 return NumBits == 32 || NumBits == 64;
6672 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6673 unsigned &RequiredAligment) const {
6674 if (!LoadedType.isSimple() ||
6675 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6677 // Cyclone supports unaligned accesses.
6678 RequiredAligment = 0;
6679 unsigned NumBits = LoadedType.getSizeInBits();
6680 return NumBits == 32 || NumBits == 64;
6683 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6684 unsigned AlignCheck) {
6685 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6686 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6689 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6690 unsigned SrcAlign, bool IsMemset,
6693 MachineFunction &MF) const {
6694 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6695 // instruction to materialize the v2i64 zero and one store (with restrictive
6696 // addressing mode). Just do two i64 store of zero-registers.
6698 const Function *F = MF.getFunction();
6699 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6700 !F->hasFnAttribute(Attribute::NoImplicitFloat) &&
6701 (memOpAlign(SrcAlign, DstAlign, 16) ||
6702 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6706 (memOpAlign(SrcAlign, DstAlign, 8) ||
6707 (allowsMisalignedMemoryAccesses(MVT::i64, 0, 1, &Fast) && Fast)))
6711 (memOpAlign(SrcAlign, DstAlign, 4) ||
6712 (allowsMisalignedMemoryAccesses(MVT::i32, 0, 1, &Fast) && Fast)))
6718 // 12-bit optionally shifted immediates are legal for adds.
6719 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6720 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6725 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6726 // immediates is the same as for an add or a sub.
6727 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6730 return isLegalAddImmediate(Immed);
6733 /// isLegalAddressingMode - Return true if the addressing mode represented
6734 /// by AM is legal for this target, for a load/store of the specified type.
6735 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6737 // AArch64 has five basic addressing modes:
6739 // reg + 9-bit signed offset
6740 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6742 // reg + SIZE_IN_BYTES * reg
6744 // No global is ever allowed as a base.
6748 // No reg+reg+imm addressing.
6749 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6752 // check reg + imm case:
6753 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6754 uint64_t NumBytes = 0;
6755 if (Ty->isSized()) {
6756 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6757 NumBytes = NumBits / 8;
6758 if (!isPowerOf2_64(NumBits))
6763 int64_t Offset = AM.BaseOffs;
6765 // 9-bit signed offset
6766 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6769 // 12-bit unsigned offset
6770 unsigned shift = Log2_64(NumBytes);
6771 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6772 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6773 (Offset >> shift) << shift == Offset)
6778 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6780 if (!AM.Scale || AM.Scale == 1 ||
6781 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6786 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6788 // Scaling factors are not free at all.
6789 // Operands | Rt Latency
6790 // -------------------------------------------
6792 // -------------------------------------------
6793 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6794 // Rt, [Xn, Wm, <extend> #imm] |
6795 if (isLegalAddressingMode(AM, Ty))
6796 // Scale represents reg2 * scale, thus account for 1 if
6797 // it is not equal to 0 or 1.
6798 return AM.Scale != 0 && AM.Scale != 1;
6802 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6803 VT = VT.getScalarType();
6808 switch (VT.getSimpleVT().SimpleTy) {
6820 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6821 // LR is a callee-save register, but we must treat it as clobbered by any call
6822 // site. Hence we include LR in the scratch registers, which are in turn added
6823 // as implicit-defs for stackmaps and patchpoints.
6824 static const MCPhysReg ScratchRegs[] = {
6825 AArch64::X16, AArch64::X17, AArch64::LR, 0
6831 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6832 EVT VT = N->getValueType(0);
6833 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6834 // it with shift to let it be lowered to UBFX.
6835 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6836 isa<ConstantSDNode>(N->getOperand(1))) {
6837 uint64_t TruncMask = N->getConstantOperandVal(1);
6838 if (isMask_64(TruncMask) &&
6839 N->getOperand(0).getOpcode() == ISD::SRL &&
6840 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6846 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6848 assert(Ty->isIntegerTy());
6850 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6854 int64_t Val = Imm.getSExtValue();
6855 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6858 if ((int64_t)Val < 0)
6861 Val &= (1LL << 32) - 1;
6863 unsigned LZ = countLeadingZeros((uint64_t)Val);
6864 unsigned Shift = (63 - LZ) / 16;
6865 // MOVZ is free so return true for one or fewer MOVK.
6869 // Generate SUBS and CSEL for integer abs.
6870 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6871 EVT VT = N->getValueType(0);
6873 SDValue N0 = N->getOperand(0);
6874 SDValue N1 = N->getOperand(1);
6877 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6878 // and change it to SUB and CSEL.
6879 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6880 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6881 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6882 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6883 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6884 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
6886 // Generate SUBS & CSEL.
6888 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6889 N0.getOperand(0), DAG.getConstant(0, DL, VT));
6890 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6891 DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
6892 SDValue(Cmp.getNode(), 1));
6897 // performXorCombine - Attempts to handle integer ABS.
6898 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6899 TargetLowering::DAGCombinerInfo &DCI,
6900 const AArch64Subtarget *Subtarget) {
6901 if (DCI.isBeforeLegalizeOps())
6904 return performIntegerAbsCombine(N, DAG);
6908 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6910 std::vector<SDNode *> *Created) const {
6911 // fold (sdiv X, pow2)
6912 EVT VT = N->getValueType(0);
6913 if ((VT != MVT::i32 && VT != MVT::i64) ||
6914 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6918 SDValue N0 = N->getOperand(0);
6919 unsigned Lg2 = Divisor.countTrailingZeros();
6920 SDValue Zero = DAG.getConstant(0, DL, VT);
6921 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
6923 // Add (N0 < 0) ? Pow2 - 1 : 0;
6925 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6926 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6927 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6930 Created->push_back(Cmp.getNode());
6931 Created->push_back(Add.getNode());
6932 Created->push_back(CSel.getNode());
6937 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
6939 // If we're dividing by a positive value, we're done. Otherwise, we must
6940 // negate the result.
6941 if (Divisor.isNonNegative())
6945 Created->push_back(SRA.getNode());
6946 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
6949 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6950 TargetLowering::DAGCombinerInfo &DCI,
6951 const AArch64Subtarget *Subtarget) {
6952 if (DCI.isBeforeLegalizeOps())
6955 // Multiplication of a power of two plus/minus one can be done more
6956 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6957 // future CPUs have a cheaper MADD instruction, this may need to be
6958 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6959 // 64-bit is 5 cycles, so this is always a win.
6960 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6961 APInt Value = C->getAPIntValue();
6962 EVT VT = N->getValueType(0);
6964 if (Value.isNonNegative()) {
6965 // (mul x, 2^N + 1) => (add (shl x, N), x)
6966 APInt VM1 = Value - 1;
6967 if (VM1.isPowerOf2()) {
6968 SDValue ShiftedVal =
6969 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
6970 DAG.getConstant(VM1.logBase2(), DL, MVT::i64));
6971 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
6974 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6975 APInt VP1 = Value + 1;
6976 if (VP1.isPowerOf2()) {
6977 SDValue ShiftedVal =
6978 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
6979 DAG.getConstant(VP1.logBase2(), DL, MVT::i64));
6980 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
6984 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6985 APInt VNP1 = -Value + 1;
6986 if (VNP1.isPowerOf2()) {
6987 SDValue ShiftedVal =
6988 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
6989 DAG.getConstant(VNP1.logBase2(), DL, MVT::i64));
6990 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
6993 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6994 APInt VNM1 = -Value - 1;
6995 if (VNM1.isPowerOf2()) {
6996 SDValue ShiftedVal =
6997 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
6998 DAG.getConstant(VNM1.logBase2(), DL, MVT::i64));
7000 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7001 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
7008 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
7009 SelectionDAG &DAG) {
7010 // Take advantage of vector comparisons producing 0 or -1 in each lane to
7011 // optimize away operation when it's from a constant.
7013 // The general transformation is:
7014 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
7015 // AND(VECTOR_CMP(x,y), constant2)
7016 // constant2 = UNARYOP(constant)
7018 // Early exit if this isn't a vector operation, the operand of the
7019 // unary operation isn't a bitwise AND, or if the sizes of the operations
7021 EVT VT = N->getValueType(0);
7022 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
7023 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
7024 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
7027 // Now check that the other operand of the AND is a constant. We could
7028 // make the transformation for non-constant splats as well, but it's unclear
7029 // that would be a benefit as it would not eliminate any operations, just
7030 // perform one more step in scalar code before moving to the vector unit.
7031 if (BuildVectorSDNode *BV =
7032 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
7033 // Bail out if the vector isn't a constant.
7034 if (!BV->isConstant())
7037 // Everything checks out. Build up the new and improved node.
7039 EVT IntVT = BV->getValueType(0);
7040 // Create a new constant of the appropriate type for the transformed
7042 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
7043 // The AND node needs bitcasts to/from an integer vector type around it.
7044 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
7045 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
7046 N->getOperand(0)->getOperand(0), MaskConst);
7047 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
7054 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
7055 const AArch64Subtarget *Subtarget) {
7056 // First try to optimize away the conversion when it's conditionally from
7057 // a constant. Vectors only.
7058 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
7059 if (Res != SDValue())
7062 EVT VT = N->getValueType(0);
7063 if (VT != MVT::f32 && VT != MVT::f64)
7066 // Only optimize when the source and destination types have the same width.
7067 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
7070 // If the result of an integer load is only used by an integer-to-float
7071 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
7072 // This eliminates an "integer-to-vector-move UOP and improve throughput.
7073 SDValue N0 = N->getOperand(0);
7074 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7075 // Do not change the width of a volatile load.
7076 !cast<LoadSDNode>(N0)->isVolatile()) {
7077 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7078 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
7079 LN0->getPointerInfo(), LN0->isVolatile(),
7080 LN0->isNonTemporal(), LN0->isInvariant(),
7081 LN0->getAlignment());
7083 // Make sure successors of the original load stay after it by updating them
7084 // to use the new Chain.
7085 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
7088 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
7089 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
7095 /// An EXTR instruction is made up of two shifts, ORed together. This helper
7096 /// searches for and classifies those shifts.
7097 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
7099 if (N.getOpcode() == ISD::SHL)
7101 else if (N.getOpcode() == ISD::SRL)
7106 if (!isa<ConstantSDNode>(N.getOperand(1)))
7109 ShiftAmount = N->getConstantOperandVal(1);
7110 Src = N->getOperand(0);
7114 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7115 /// registers viewed as a high/low pair. This function looks for the pattern:
7116 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7117 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7119 static SDValue tryCombineToEXTR(SDNode *N,
7120 TargetLowering::DAGCombinerInfo &DCI) {
7121 SelectionDAG &DAG = DCI.DAG;
7123 EVT VT = N->getValueType(0);
7125 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7127 if (VT != MVT::i32 && VT != MVT::i64)
7131 uint32_t ShiftLHS = 0;
7133 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7137 uint32_t ShiftRHS = 0;
7139 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7142 // If they're both trying to come from the high part of the register, they're
7143 // not really an EXTR.
7144 if (LHSFromHi == RHSFromHi)
7147 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7151 std::swap(LHS, RHS);
7152 std::swap(ShiftLHS, ShiftRHS);
7155 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7156 DAG.getConstant(ShiftRHS, DL, MVT::i64));
7159 static SDValue tryCombineToBSL(SDNode *N,
7160 TargetLowering::DAGCombinerInfo &DCI) {
7161 EVT VT = N->getValueType(0);
7162 SelectionDAG &DAG = DCI.DAG;
7168 SDValue N0 = N->getOperand(0);
7169 if (N0.getOpcode() != ISD::AND)
7172 SDValue N1 = N->getOperand(1);
7173 if (N1.getOpcode() != ISD::AND)
7176 // We only have to look for constant vectors here since the general, variable
7177 // case can be handled in TableGen.
7178 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7179 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7180 for (int i = 1; i >= 0; --i)
7181 for (int j = 1; j >= 0; --j) {
7182 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7183 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7187 bool FoundMatch = true;
7188 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7189 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7190 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7192 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7199 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7200 N0->getOperand(1 - i), N1->getOperand(1 - j));
7206 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7207 const AArch64Subtarget *Subtarget) {
7208 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7209 if (!EnableAArch64ExtrGeneration)
7211 SelectionDAG &DAG = DCI.DAG;
7212 EVT VT = N->getValueType(0);
7214 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7217 SDValue Res = tryCombineToEXTR(N, DCI);
7221 Res = tryCombineToBSL(N, DCI);
7228 static SDValue performBitcastCombine(SDNode *N,
7229 TargetLowering::DAGCombinerInfo &DCI,
7230 SelectionDAG &DAG) {
7231 // Wait 'til after everything is legalized to try this. That way we have
7232 // legal vector types and such.
7233 if (DCI.isBeforeLegalizeOps())
7236 // Remove extraneous bitcasts around an extract_subvector.
7238 // (v4i16 (bitconvert
7239 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7241 // (extract_subvector ((v8i16 ...), (i64 4)))
7243 // Only interested in 64-bit vectors as the ultimate result.
7244 EVT VT = N->getValueType(0);
7247 if (VT.getSimpleVT().getSizeInBits() != 64)
7249 // Is the operand an extract_subvector starting at the beginning or halfway
7250 // point of the vector? A low half may also come through as an
7251 // EXTRACT_SUBREG, so look for that, too.
7252 SDValue Op0 = N->getOperand(0);
7253 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7254 !(Op0->isMachineOpcode() &&
7255 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7257 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7258 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7259 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7261 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7262 if (idx != AArch64::dsub)
7264 // The dsub reference is equivalent to a lane zero subvector reference.
7267 // Look through the bitcast of the input to the extract.
7268 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7270 SDValue Source = Op0->getOperand(0)->getOperand(0);
7271 // If the source type has twice the number of elements as our destination
7272 // type, we know this is an extract of the high or low half of the vector.
7273 EVT SVT = Source->getValueType(0);
7274 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7277 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7279 // Create the simplified form to just extract the low or high half of the
7280 // vector directly rather than bothering with the bitcasts.
7282 unsigned NumElements = VT.getVectorNumElements();
7284 SDValue HalfIdx = DAG.getConstant(NumElements, dl, MVT::i64);
7285 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7287 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, dl, MVT::i32);
7288 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7294 static SDValue performConcatVectorsCombine(SDNode *N,
7295 TargetLowering::DAGCombinerInfo &DCI,
7296 SelectionDAG &DAG) {
7298 EVT VT = N->getValueType(0);
7299 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
7301 // Optimize concat_vectors of truncated vectors, where the intermediate
7302 // type is illegal, to avoid said illegality, e.g.,
7303 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7304 // (v2i16 (truncate (v2i64)))))
7306 // (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
7307 // (v4i32 (bitcast (v2i64))),
7309 // This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
7310 // on both input and result type, so we might generate worse code.
7311 // On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
7312 if (N->getNumOperands() == 2 &&
7313 N0->getOpcode() == ISD::TRUNCATE &&
7314 N1->getOpcode() == ISD::TRUNCATE) {
7315 SDValue N00 = N0->getOperand(0);
7316 SDValue N10 = N1->getOperand(0);
7317 EVT N00VT = N00.getValueType();
7319 if (N00VT == N10.getValueType() &&
7320 (N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
7321 N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
7322 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
7323 SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
7324 for (size_t i = 0; i < Mask.size(); ++i)
7326 return DAG.getNode(ISD::TRUNCATE, dl, VT,
7327 DAG.getVectorShuffle(
7329 DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
7330 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
7334 // Wait 'til after everything is legalized to try this. That way we have
7335 // legal vector types and such.
7336 if (DCI.isBeforeLegalizeOps())
7339 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7340 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7341 // canonicalise to that.
7342 if (N0 == N1 && VT.getVectorNumElements() == 2) {
7343 assert(VT.getVectorElementType().getSizeInBits() == 64);
7344 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG),
7345 DAG.getConstant(0, dl, MVT::i64));
7348 // Canonicalise concat_vectors so that the right-hand vector has as few
7349 // bit-casts as possible before its real operation. The primary matching
7350 // destination for these operations will be the narrowing "2" instructions,
7351 // which depend on the operation being performed on this right-hand vector.
7353 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7355 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7357 if (N1->getOpcode() != ISD::BITCAST)
7359 SDValue RHS = N1->getOperand(0);
7360 MVT RHSTy = RHS.getValueType().getSimpleVT();
7361 // If the RHS is not a vector, this is not the pattern we're looking for.
7362 if (!RHSTy.isVector())
7365 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7367 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7368 RHSTy.getVectorNumElements() * 2);
7369 return DAG.getNode(ISD::BITCAST, dl, VT,
7370 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7371 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),
7375 static SDValue tryCombineFixedPointConvert(SDNode *N,
7376 TargetLowering::DAGCombinerInfo &DCI,
7377 SelectionDAG &DAG) {
7378 // Wait 'til after everything is legalized to try this. That way we have
7379 // legal vector types and such.
7380 if (DCI.isBeforeLegalizeOps())
7382 // Transform a scalar conversion of a value from a lane extract into a
7383 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7384 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7385 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7387 // The second form interacts better with instruction selection and the
7388 // register allocator to avoid cross-class register copies that aren't
7389 // coalescable due to a lane reference.
7391 // Check the operand and see if it originates from a lane extract.
7392 SDValue Op1 = N->getOperand(1);
7393 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7394 // Yep, no additional predication needed. Perform the transform.
7395 SDValue IID = N->getOperand(0);
7396 SDValue Shift = N->getOperand(2);
7397 SDValue Vec = Op1.getOperand(0);
7398 SDValue Lane = Op1.getOperand(1);
7399 EVT ResTy = N->getValueType(0);
7403 // The vector width should be 128 bits by the time we get here, even
7404 // if it started as 64 bits (the extract_vector handling will have
7406 assert(Vec.getValueType().getSizeInBits() == 128 &&
7407 "unexpected vector size on extract_vector_elt!");
7408 if (Vec.getValueType() == MVT::v4i32)
7409 VecResTy = MVT::v4f32;
7410 else if (Vec.getValueType() == MVT::v2i64)
7411 VecResTy = MVT::v2f64;
7413 llvm_unreachable("unexpected vector type!");
7416 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7417 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7422 // AArch64 high-vector "long" operations are formed by performing the non-high
7423 // version on an extract_subvector of each operand which gets the high half:
7425 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7427 // However, there are cases which don't have an extract_high explicitly, but
7428 // have another operation that can be made compatible with one for free. For
7431 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7433 // This routine does the actual conversion of such DUPs, once outer routines
7434 // have determined that everything else is in order.
7435 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7436 // We can handle most types of duplicate, but the lane ones have an extra
7437 // operand saying *which* lane, so we need to know.
7439 switch (N.getOpcode()) {
7440 case AArch64ISD::DUP:
7443 case AArch64ISD::DUPLANE8:
7444 case AArch64ISD::DUPLANE16:
7445 case AArch64ISD::DUPLANE32:
7446 case AArch64ISD::DUPLANE64:
7453 MVT NarrowTy = N.getSimpleValueType();
7454 if (!NarrowTy.is64BitVector())
7457 MVT ElementTy = NarrowTy.getVectorElementType();
7458 unsigned NumElems = NarrowTy.getVectorNumElements();
7459 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7464 NewDUP = DAG.getNode(N.getOpcode(), dl, NewDUPVT, N.getOperand(0),
7467 NewDUP = DAG.getNode(AArch64ISD::DUP, dl, NewDUPVT, N.getOperand(0));
7469 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy, NewDUP,
7470 DAG.getConstant(NumElems, dl, MVT::i64));
7473 static bool isEssentiallyExtractSubvector(SDValue N) {
7474 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7477 return N.getOpcode() == ISD::BITCAST &&
7478 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7481 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7482 struct GenericSetCCInfo {
7483 const SDValue *Opnd0;
7484 const SDValue *Opnd1;
7488 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7489 struct AArch64SetCCInfo {
7491 AArch64CC::CondCode CC;
7494 /// \brief Helper structure to keep track of SetCC information.
7496 GenericSetCCInfo Generic;
7497 AArch64SetCCInfo AArch64;
7500 /// \brief Helper structure to be able to read SetCC information. If set to
7501 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7502 /// GenericSetCCInfo.
7503 struct SetCCInfoAndKind {
7508 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7510 /// AArch64 lowered one.
7511 /// \p SetCCInfo is filled accordingly.
7512 /// \post SetCCInfo is meanginfull only when this function returns true.
7513 /// \return True when Op is a kind of SET_CC operation.
7514 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7515 // If this is a setcc, this is straight forward.
7516 if (Op.getOpcode() == ISD::SETCC) {
7517 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7518 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7519 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7520 SetCCInfo.IsAArch64 = false;
7523 // Otherwise, check if this is a matching csel instruction.
7527 if (Op.getOpcode() != AArch64ISD::CSEL)
7529 // Set the information about the operands.
7530 // TODO: we want the operands of the Cmp not the csel
7531 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7532 SetCCInfo.IsAArch64 = true;
7533 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7534 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7536 // Check that the operands matches the constraints:
7537 // (1) Both operands must be constants.
7538 // (2) One must be 1 and the other must be 0.
7539 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7540 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7543 if (!TValue || !FValue)
7547 if (!TValue->isOne()) {
7548 // Update the comparison when we are interested in !cc.
7549 std::swap(TValue, FValue);
7550 SetCCInfo.Info.AArch64.CC =
7551 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7553 return TValue->isOne() && FValue->isNullValue();
7556 // Returns true if Op is setcc or zext of setcc.
7557 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7558 if (isSetCC(Op, Info))
7560 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7561 isSetCC(Op->getOperand(0), Info));
7564 // The folding we want to perform is:
7565 // (add x, [zext] (setcc cc ...) )
7567 // (csel x, (add x, 1), !cc ...)
7569 // The latter will get matched to a CSINC instruction.
7570 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7571 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7572 SDValue LHS = Op->getOperand(0);
7573 SDValue RHS = Op->getOperand(1);
7574 SetCCInfoAndKind InfoAndKind;
7576 // If neither operand is a SET_CC, give up.
7577 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7578 std::swap(LHS, RHS);
7579 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7583 // FIXME: This could be generatized to work for FP comparisons.
7584 EVT CmpVT = InfoAndKind.IsAArch64
7585 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7586 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7587 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7593 if (InfoAndKind.IsAArch64) {
7594 CCVal = DAG.getConstant(
7595 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
7597 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7599 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7600 *InfoAndKind.Info.Generic.Opnd1,
7601 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7604 EVT VT = Op->getValueType(0);
7605 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
7606 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7609 // The basic add/sub long vector instructions have variants with "2" on the end
7610 // which act on the high-half of their inputs. They are normally matched by
7613 // (add (zeroext (extract_high LHS)),
7614 // (zeroext (extract_high RHS)))
7615 // -> uaddl2 vD, vN, vM
7617 // However, if one of the extracts is something like a duplicate, this
7618 // instruction can still be used profitably. This function puts the DAG into a
7619 // more appropriate form for those patterns to trigger.
7620 static SDValue performAddSubLongCombine(SDNode *N,
7621 TargetLowering::DAGCombinerInfo &DCI,
7622 SelectionDAG &DAG) {
7623 if (DCI.isBeforeLegalizeOps())
7626 MVT VT = N->getSimpleValueType(0);
7627 if (!VT.is128BitVector()) {
7628 if (N->getOpcode() == ISD::ADD)
7629 return performSetccAddFolding(N, DAG);
7633 // Make sure both branches are extended in the same way.
7634 SDValue LHS = N->getOperand(0);
7635 SDValue RHS = N->getOperand(1);
7636 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7637 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7638 LHS.getOpcode() != RHS.getOpcode())
7641 unsigned ExtType = LHS.getOpcode();
7643 // It's not worth doing if at least one of the inputs isn't already an
7644 // extract, but we don't know which it'll be so we have to try both.
7645 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7646 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7650 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7651 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7652 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7656 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7659 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7662 // Massage DAGs which we can use the high-half "long" operations on into
7663 // something isel will recognize better. E.g.
7665 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7666 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7667 // (extract_high (v2i64 (dup128 scalar)))))
7669 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7670 TargetLowering::DAGCombinerInfo &DCI,
7671 SelectionDAG &DAG) {
7672 if (DCI.isBeforeLegalizeOps())
7675 SDValue LHS = N->getOperand(1);
7676 SDValue RHS = N->getOperand(2);
7677 assert(LHS.getValueType().is64BitVector() &&
7678 RHS.getValueType().is64BitVector() &&
7679 "unexpected shape for long operation");
7681 // Either node could be a DUP, but it's not worth doing both of them (you'd
7682 // just as well use the non-high version) so look for a corresponding extract
7683 // operation on the other "wing".
7684 if (isEssentiallyExtractSubvector(LHS)) {
7685 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7688 } else if (isEssentiallyExtractSubvector(RHS)) {
7689 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7694 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7695 N->getOperand(0), LHS, RHS);
7698 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7699 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7700 unsigned ElemBits = ElemTy.getSizeInBits();
7702 int64_t ShiftAmount;
7703 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7704 APInt SplatValue, SplatUndef;
7705 unsigned SplatBitSize;
7707 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7708 HasAnyUndefs, ElemBits) ||
7709 SplatBitSize != ElemBits)
7712 ShiftAmount = SplatValue.getSExtValue();
7713 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7714 ShiftAmount = CVN->getSExtValue();
7722 llvm_unreachable("Unknown shift intrinsic");
7723 case Intrinsic::aarch64_neon_sqshl:
7724 Opcode = AArch64ISD::SQSHL_I;
7725 IsRightShift = false;
7727 case Intrinsic::aarch64_neon_uqshl:
7728 Opcode = AArch64ISD::UQSHL_I;
7729 IsRightShift = false;
7731 case Intrinsic::aarch64_neon_srshl:
7732 Opcode = AArch64ISD::SRSHR_I;
7733 IsRightShift = true;
7735 case Intrinsic::aarch64_neon_urshl:
7736 Opcode = AArch64ISD::URSHR_I;
7737 IsRightShift = true;
7739 case Intrinsic::aarch64_neon_sqshlu:
7740 Opcode = AArch64ISD::SQSHLU_I;
7741 IsRightShift = false;
7745 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
7747 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
7748 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
7749 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) {
7751 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1),
7752 DAG.getConstant(ShiftAmount, dl, MVT::i32));
7758 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7759 // the intrinsics must be legal and take an i32, this means there's almost
7760 // certainly going to be a zext in the DAG which we can eliminate.
7761 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7762 SDValue AndN = N->getOperand(2);
7763 if (AndN.getOpcode() != ISD::AND)
7766 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7767 if (!CMask || CMask->getZExtValue() != Mask)
7770 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7771 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7774 static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
7775 SelectionDAG &DAG) {
7777 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0),
7778 DAG.getNode(Opc, dl,
7779 N->getOperand(1).getSimpleValueType(),
7781 DAG.getConstant(0, dl, MVT::i64));
7784 static SDValue performIntrinsicCombine(SDNode *N,
7785 TargetLowering::DAGCombinerInfo &DCI,
7786 const AArch64Subtarget *Subtarget) {
7787 SelectionDAG &DAG = DCI.DAG;
7788 unsigned IID = getIntrinsicID(N);
7792 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7793 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7794 return tryCombineFixedPointConvert(N, DCI, DAG);
7796 case Intrinsic::aarch64_neon_saddv:
7797 return combineAcrossLanesIntrinsic(AArch64ISD::SADDV, N, DAG);
7798 case Intrinsic::aarch64_neon_uaddv:
7799 return combineAcrossLanesIntrinsic(AArch64ISD::UADDV, N, DAG);
7800 case Intrinsic::aarch64_neon_sminv:
7801 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG);
7802 case Intrinsic::aarch64_neon_uminv:
7803 return combineAcrossLanesIntrinsic(AArch64ISD::UMINV, N, DAG);
7804 case Intrinsic::aarch64_neon_smaxv:
7805 return combineAcrossLanesIntrinsic(AArch64ISD::SMAXV, N, DAG);
7806 case Intrinsic::aarch64_neon_umaxv:
7807 return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
7808 case Intrinsic::aarch64_neon_fmax:
7809 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7810 N->getOperand(1), N->getOperand(2));
7811 case Intrinsic::aarch64_neon_fmin:
7812 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7813 N->getOperand(1), N->getOperand(2));
7814 case Intrinsic::aarch64_neon_smull:
7815 case Intrinsic::aarch64_neon_umull:
7816 case Intrinsic::aarch64_neon_pmull:
7817 case Intrinsic::aarch64_neon_sqdmull:
7818 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7819 case Intrinsic::aarch64_neon_sqshl:
7820 case Intrinsic::aarch64_neon_uqshl:
7821 case Intrinsic::aarch64_neon_sqshlu:
7822 case Intrinsic::aarch64_neon_srshl:
7823 case Intrinsic::aarch64_neon_urshl:
7824 return tryCombineShiftImm(IID, N, DAG);
7825 case Intrinsic::aarch64_crc32b:
7826 case Intrinsic::aarch64_crc32cb:
7827 return tryCombineCRC32(0xff, N, DAG);
7828 case Intrinsic::aarch64_crc32h:
7829 case Intrinsic::aarch64_crc32ch:
7830 return tryCombineCRC32(0xffff, N, DAG);
7835 static SDValue performExtendCombine(SDNode *N,
7836 TargetLowering::DAGCombinerInfo &DCI,
7837 SelectionDAG &DAG) {
7838 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7839 // we can convert that DUP into another extract_high (of a bigger DUP), which
7840 // helps the backend to decide that an sabdl2 would be useful, saving a real
7841 // extract_high operation.
7842 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7843 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7844 SDNode *ABDNode = N->getOperand(0).getNode();
7845 unsigned IID = getIntrinsicID(ABDNode);
7846 if (IID == Intrinsic::aarch64_neon_sabd ||
7847 IID == Intrinsic::aarch64_neon_uabd) {
7848 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7849 if (!NewABD.getNode())
7852 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7857 // This is effectively a custom type legalization for AArch64.
7859 // Type legalization will split an extend of a small, legal, type to a larger
7860 // illegal type by first splitting the destination type, often creating
7861 // illegal source types, which then get legalized in isel-confusing ways,
7862 // leading to really terrible codegen. E.g.,
7863 // %result = v8i32 sext v8i8 %value
7865 // %losrc = extract_subreg %value, ...
7866 // %hisrc = extract_subreg %value, ...
7867 // %lo = v4i32 sext v4i8 %losrc
7868 // %hi = v4i32 sext v4i8 %hisrc
7869 // Things go rapidly downhill from there.
7871 // For AArch64, the [sz]ext vector instructions can only go up one element
7872 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7873 // take two instructions.
7875 // This implies that the most efficient way to do the extend from v8i8
7876 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7877 // the normal splitting to happen for the v8i16->v8i32.
7879 // This is pre-legalization to catch some cases where the default
7880 // type legalization will create ill-tempered code.
7881 if (!DCI.isBeforeLegalizeOps())
7884 // We're only interested in cleaning things up for non-legal vector types
7885 // here. If both the source and destination are legal, things will just
7886 // work naturally without any fiddling.
7887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7888 EVT ResVT = N->getValueType(0);
7889 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7891 // If the vector type isn't a simple VT, it's beyond the scope of what
7892 // we're worried about here. Let legalization do its thing and hope for
7894 SDValue Src = N->getOperand(0);
7895 EVT SrcVT = Src->getValueType(0);
7896 if (!ResVT.isSimple() || !SrcVT.isSimple())
7899 // If the source VT is a 64-bit vector, we can play games and get the
7900 // better results we want.
7901 if (SrcVT.getSizeInBits() != 64)
7904 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7905 unsigned ElementCount = SrcVT.getVectorNumElements();
7906 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7908 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7910 // Now split the rest of the operation into two halves, each with a 64
7914 unsigned NumElements = ResVT.getVectorNumElements();
7915 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7916 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7917 ResVT.getVectorElementType(), NumElements / 2);
7919 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7920 LoVT.getVectorNumElements());
7921 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7922 DAG.getConstant(0, DL, MVT::i64));
7923 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7924 DAG.getConstant(InNVT.getVectorNumElements(), DL, MVT::i64));
7925 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7926 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7928 // Now combine the parts back together so we still have a single result
7929 // like the combiner expects.
7930 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7933 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7934 /// value. The load store optimizer pass will merge them to store pair stores.
7935 /// This has better performance than a splat of the scalar followed by a split
7936 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7937 /// followed by an ext.b and two stores.
7938 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7939 SDValue StVal = St->getValue();
7940 EVT VT = StVal.getValueType();
7942 // Don't replace floating point stores, they possibly won't be transformed to
7943 // stp because of the store pair suppress pass.
7944 if (VT.isFloatingPoint())
7947 // Check for insert vector elements.
7948 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7951 // We can express a splat as store pair(s) for 2 or 4 elements.
7952 unsigned NumVecElts = VT.getVectorNumElements();
7953 if (NumVecElts != 4 && NumVecElts != 2)
7955 SDValue SplatVal = StVal.getOperand(1);
7956 unsigned RemainInsertElts = NumVecElts - 1;
7958 // Check that this is a splat.
7959 while (--RemainInsertElts) {
7960 SDValue NextInsertElt = StVal.getOperand(0);
7961 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7963 if (NextInsertElt.getOperand(1) != SplatVal)
7965 StVal = NextInsertElt;
7967 unsigned OrigAlignment = St->getAlignment();
7968 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7969 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7971 // Create scalar stores. This is at least as good as the code sequence for a
7972 // split unaligned store wich is a dup.s, ext.b, and two stores.
7973 // Most of the time the three stores should be replaced by store pair
7974 // instructions (stp).
7976 SDValue BasePtr = St->getBasePtr();
7978 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7979 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7981 unsigned Offset = EltOffset;
7982 while (--NumVecElts) {
7983 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7984 DAG.getConstant(Offset, DL, MVT::i64));
7985 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7986 St->getPointerInfo(), St->isVolatile(),
7987 St->isNonTemporal(), Alignment);
7988 Offset += EltOffset;
7993 static SDValue performSTORECombine(SDNode *N,
7994 TargetLowering::DAGCombinerInfo &DCI,
7996 const AArch64Subtarget *Subtarget) {
7997 if (!DCI.isBeforeLegalize())
8000 StoreSDNode *S = cast<StoreSDNode>(N);
8001 if (S->isVolatile())
8004 // Cyclone has bad performance on unaligned 16B stores when crossing line and
8005 // page boundaries. We want to split such stores.
8006 if (!Subtarget->isCyclone())
8009 // Don't split at Oz.
8010 MachineFunction &MF = DAG.getMachineFunction();
8011 bool IsMinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
8015 SDValue StVal = S->getValue();
8016 EVT VT = StVal.getValueType();
8018 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
8019 // those up regresses performance on micro-benchmarks and olden/bh.
8020 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
8023 // Split unaligned 16B stores. They are terrible for performance.
8024 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
8025 // extensions can use this to mark that it does not want splitting to happen
8026 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
8027 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
8028 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
8029 S->getAlignment() <= 2)
8032 // If we get a splat of a scalar convert this vector store to a store of
8033 // scalars. They will be merged into store pairs thereby removing two
8035 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
8036 if (ReplacedSplat != SDValue())
8037 return ReplacedSplat;
8040 unsigned NumElts = VT.getVectorNumElements() / 2;
8041 // Split VT into two.
8043 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
8044 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8045 DAG.getConstant(0, DL, MVT::i64));
8046 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
8047 DAG.getConstant(NumElts, DL, MVT::i64));
8048 SDValue BasePtr = S->getBasePtr();
8050 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
8051 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
8052 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8053 DAG.getConstant(8, DL, MVT::i64));
8054 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
8055 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
8059 /// Target-specific DAG combine function for post-increment LD1 (lane) and
8060 /// post-increment LD1R.
8061 static SDValue performPostLD1Combine(SDNode *N,
8062 TargetLowering::DAGCombinerInfo &DCI,
8064 if (DCI.isBeforeLegalizeOps())
8067 SelectionDAG &DAG = DCI.DAG;
8068 EVT VT = N->getValueType(0);
8070 unsigned LoadIdx = IsLaneOp ? 1 : 0;
8071 SDNode *LD = N->getOperand(LoadIdx).getNode();
8072 // If it is not LOAD, can not do such combine.
8073 if (LD->getOpcode() != ISD::LOAD)
8076 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
8077 EVT MemVT = LoadSDN->getMemoryVT();
8078 // Check if memory operand is the same type as the vector element.
8079 if (MemVT != VT.getVectorElementType())
8082 // Check if there are other uses. If so, do not combine as it will introduce
8084 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
8086 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
8092 SDValue Addr = LD->getOperand(1);
8093 SDValue Vector = N->getOperand(0);
8094 // Search for a use of the address operand that is an increment.
8095 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
8096 Addr.getNode()->use_end(); UI != UE; ++UI) {
8098 if (User->getOpcode() != ISD::ADD
8099 || UI.getUse().getResNo() != Addr.getResNo())
8102 // Check that the add is independent of the load. Otherwise, folding it
8103 // would create a cycle.
8104 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
8106 // Also check that add is not used in the vector operand. This would also
8108 if (User->isPredecessorOf(Vector.getNode()))
8111 // If the increment is a constant, it must match the memory ref size.
8112 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8113 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8114 uint32_t IncVal = CInc->getZExtValue();
8115 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
8116 if (IncVal != NumBytes)
8118 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8121 // Finally, check that the vector doesn't depend on the load.
8122 // Again, this would create a cycle.
8123 // The load depending on the vector is fine, as that's the case for the
8124 // LD1*post we'll eventually generate anyway.
8125 if (LoadSDN->isPredecessorOf(Vector.getNode()))
8128 SmallVector<SDValue, 8> Ops;
8129 Ops.push_back(LD->getOperand(0)); // Chain
8131 Ops.push_back(Vector); // The vector to be inserted
8132 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
8134 Ops.push_back(Addr);
8137 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
8138 SDVTList SDTys = DAG.getVTList(Tys);
8139 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
8140 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
8142 LoadSDN->getMemOperand());
8145 SmallVector<SDValue, 2> NewResults;
8146 NewResults.push_back(SDValue(LD, 0)); // The result of load
8147 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
8148 DCI.CombineTo(LD, NewResults);
8149 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
8150 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
8157 /// Target-specific DAG combine function for NEON load/store intrinsics
8158 /// to merge base address updates.
8159 static SDValue performNEONPostLDSTCombine(SDNode *N,
8160 TargetLowering::DAGCombinerInfo &DCI,
8161 SelectionDAG &DAG) {
8162 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8165 unsigned AddrOpIdx = N->getNumOperands() - 1;
8166 SDValue Addr = N->getOperand(AddrOpIdx);
8168 // Search for a use of the address operand that is an increment.
8169 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8170 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8172 if (User->getOpcode() != ISD::ADD ||
8173 UI.getUse().getResNo() != Addr.getResNo())
8176 // Check that the add is independent of the load/store. Otherwise, folding
8177 // it would create a cycle.
8178 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8181 // Find the new opcode for the updating load/store.
8182 bool IsStore = false;
8183 bool IsLaneOp = false;
8184 bool IsDupOp = false;
8185 unsigned NewOpc = 0;
8186 unsigned NumVecs = 0;
8187 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8189 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8190 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8192 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8194 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8196 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8197 NumVecs = 2; IsStore = true; break;
8198 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8199 NumVecs = 3; IsStore = true; break;
8200 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8201 NumVecs = 4; IsStore = true; break;
8202 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8204 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8206 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8208 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8209 NumVecs = 2; IsStore = true; break;
8210 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8211 NumVecs = 3; IsStore = true; break;
8212 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8213 NumVecs = 4; IsStore = true; break;
8214 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8215 NumVecs = 2; IsDupOp = true; break;
8216 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8217 NumVecs = 3; IsDupOp = true; break;
8218 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8219 NumVecs = 4; IsDupOp = true; break;
8220 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8221 NumVecs = 2; IsLaneOp = true; break;
8222 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8223 NumVecs = 3; IsLaneOp = true; break;
8224 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8225 NumVecs = 4; IsLaneOp = true; break;
8226 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8227 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8228 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8229 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8230 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8231 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8236 VecTy = N->getOperand(2).getValueType();
8238 VecTy = N->getValueType(0);
8240 // If the increment is a constant, it must match the memory ref size.
8241 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8242 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8243 uint32_t IncVal = CInc->getZExtValue();
8244 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8245 if (IsLaneOp || IsDupOp)
8246 NumBytes /= VecTy.getVectorNumElements();
8247 if (IncVal != NumBytes)
8249 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8251 SmallVector<SDValue, 8> Ops;
8252 Ops.push_back(N->getOperand(0)); // Incoming chain
8253 // Load lane and store have vector list as input.
8254 if (IsLaneOp || IsStore)
8255 for (unsigned i = 2; i < AddrOpIdx; ++i)
8256 Ops.push_back(N->getOperand(i));
8257 Ops.push_back(Addr); // Base register
8262 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8264 for (n = 0; n < NumResultVecs; ++n)
8266 Tys[n++] = MVT::i64; // Type of write back register
8267 Tys[n] = MVT::Other; // Type of the chain
8268 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8270 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8271 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8272 MemInt->getMemoryVT(),
8273 MemInt->getMemOperand());
8276 std::vector<SDValue> NewResults;
8277 for (unsigned i = 0; i < NumResultVecs; ++i) {
8278 NewResults.push_back(SDValue(UpdN.getNode(), i));
8280 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8281 DCI.CombineTo(N, NewResults);
8282 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8289 // Checks to see if the value is the prescribed width and returns information
8290 // about its extension mode.
8292 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8293 ExtType = ISD::NON_EXTLOAD;
8294 switch(V.getNode()->getOpcode()) {
8298 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8299 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8300 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8301 ExtType = LoadNode->getExtensionType();
8306 case ISD::AssertSext: {
8307 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8308 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8309 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8310 ExtType = ISD::SEXTLOAD;
8315 case ISD::AssertZext: {
8316 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8317 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8318 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8319 ExtType = ISD::ZEXTLOAD;
8325 case ISD::TargetConstant: {
8326 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8336 // This function does a whole lot of voodoo to determine if the tests are
8337 // equivalent without and with a mask. Essentially what happens is that given a
8340 // +-------------+ +-------------+ +-------------+ +-------------+
8341 // | Input | | AddConstant | | CompConstant| | CC |
8342 // +-------------+ +-------------+ +-------------+ +-------------+
8344 // V V | +----------+
8345 // +-------------+ +----+ | |
8346 // | ADD | |0xff| | |
8347 // +-------------+ +----+ | |
8350 // +-------------+ | |
8352 // +-------------+ | |
8361 // The AND node may be safely removed for some combinations of inputs. In
8362 // particular we need to take into account the extension type of the Input,
8363 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8364 // width of the input (this can work for any width inputs, the above graph is
8365 // specific to 8 bits.
8367 // The specific equations were worked out by generating output tables for each
8368 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8369 // problem was simplified by working with 4 bit inputs, which means we only
8370 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8371 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8372 // patterns present in both extensions (0,7). For every distinct set of
8373 // AddConstant and CompConstants bit patterns we can consider the masked and
8374 // unmasked versions to be equivalent if the result of this function is true for
8375 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8378 // and w10, w8, #0x0f
8380 // cset w9, AArch64CC
8382 // cset w11, AArch64CC
8387 // Since the above function shows when the outputs are equivalent it defines
8388 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8389 // would be expensive to run during compiles. The equations below were written
8390 // in a test harness that confirmed they gave equivalent outputs to the above
8391 // for all inputs function, so they can be used determine if the removal is
8394 // isEquivalentMaskless() is the code for testing if the AND can be removed
8395 // factored out of the DAG recognition as the DAG can take several forms.
8398 bool isEquivalentMaskless(unsigned CC, unsigned width,
8399 ISD::LoadExtType ExtType, signed AddConstant,
8400 signed CompConstant) {
8401 // By being careful about our equations and only writing the in term
8402 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8403 // make them generally applicable to all bit widths.
8404 signed MaxUInt = (1 << width);
8406 // For the purposes of these comparisons sign extending the type is
8407 // equivalent to zero extending the add and displacing it by half the integer
8408 // width. Provided we are careful and make sure our equations are valid over
8409 // the whole range we can just adjust the input and avoid writing equations
8410 // for sign extended inputs.
8411 if (ExtType == ISD::SEXTLOAD)
8412 AddConstant -= (1 << (width-1));
8416 case AArch64CC::GT: {
8417 if ((AddConstant == 0) ||
8418 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8419 (AddConstant >= 0 && CompConstant < 0) ||
8420 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8424 case AArch64CC::GE: {
8425 if ((AddConstant == 0) ||
8426 (AddConstant >= 0 && CompConstant <= 0) ||
8427 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8431 case AArch64CC::LS: {
8432 if ((AddConstant >= 0 && CompConstant < 0) ||
8433 (AddConstant <= 0 && CompConstant >= -1 &&
8434 CompConstant < AddConstant + MaxUInt))
8438 case AArch64CC::MI: {
8439 if ((AddConstant == 0) ||
8440 (AddConstant > 0 && CompConstant <= 0) ||
8441 (AddConstant < 0 && CompConstant <= AddConstant))
8445 case AArch64CC::HS: {
8446 if ((AddConstant >= 0 && CompConstant <= 0) ||
8447 (AddConstant <= 0 && CompConstant >= 0 &&
8448 CompConstant <= AddConstant + MaxUInt))
8452 case AArch64CC::NE: {
8453 if ((AddConstant > 0 && CompConstant < 0) ||
8454 (AddConstant < 0 && CompConstant >= 0 &&
8455 CompConstant < AddConstant + MaxUInt) ||
8456 (AddConstant >= 0 && CompConstant >= 0 &&
8457 CompConstant >= AddConstant) ||
8458 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8467 case AArch64CC::Invalid:
8475 SDValue performCONDCombine(SDNode *N,
8476 TargetLowering::DAGCombinerInfo &DCI,
8477 SelectionDAG &DAG, unsigned CCIndex,
8478 unsigned CmpIndex) {
8479 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8480 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8481 unsigned CondOpcode = SubsNode->getOpcode();
8483 if (CondOpcode != AArch64ISD::SUBS)
8486 // There is a SUBS feeding this condition. Is it fed by a mask we can
8489 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8490 unsigned MaskBits = 0;
8492 if (AndNode->getOpcode() != ISD::AND)
8495 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8496 uint32_t CNV = CN->getZExtValue();
8499 else if (CNV == 65535)
8506 SDValue AddValue = AndNode->getOperand(0);
8508 if (AddValue.getOpcode() != ISD::ADD)
8511 // The basic dag structure is correct, grab the inputs and validate them.
8513 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8514 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8515 SDValue SubsInputValue = SubsNode->getOperand(1);
8517 // The mask is present and the provenance of all the values is a smaller type,
8518 // lets see if the mask is superfluous.
8520 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8521 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8524 ISD::LoadExtType ExtType;
8526 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8527 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8528 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8531 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8532 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8533 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8536 // The AND is not necessary, remove it.
8538 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8539 SubsNode->getValueType(1));
8540 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8542 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8543 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8545 return SDValue(N, 0);
8548 // Optimize compare with zero and branch.
8549 static SDValue performBRCONDCombine(SDNode *N,
8550 TargetLowering::DAGCombinerInfo &DCI,
8551 SelectionDAG &DAG) {
8552 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8555 SDValue Chain = N->getOperand(0);
8556 SDValue Dest = N->getOperand(1);
8557 SDValue CCVal = N->getOperand(2);
8558 SDValue Cmp = N->getOperand(3);
8560 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8561 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8562 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8565 unsigned CmpOpc = Cmp.getOpcode();
8566 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8569 // Only attempt folding if there is only one use of the flag and no use of the
8571 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8574 SDValue LHS = Cmp.getOperand(0);
8575 SDValue RHS = Cmp.getOperand(1);
8577 assert(LHS.getValueType() == RHS.getValueType() &&
8578 "Expected the value type to be the same for both operands!");
8579 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8582 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8583 std::swap(LHS, RHS);
8585 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8588 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8589 LHS.getOpcode() == ISD::SRL)
8592 // Fold the compare into the branch instruction.
8594 if (CC == AArch64CC::EQ)
8595 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8597 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8599 // Do not add new nodes to DAG combiner worklist.
8600 DCI.CombineTo(N, BR, false);
8605 // vselect (v1i1 setcc) ->
8606 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8607 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8608 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8610 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8611 SDValue N0 = N->getOperand(0);
8612 EVT CCVT = N0.getValueType();
8614 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8615 CCVT.getVectorElementType() != MVT::i1)
8618 EVT ResVT = N->getValueType(0);
8619 EVT CmpVT = N0.getOperand(0).getValueType();
8620 // Only combine when the result type is of the same size as the compared
8622 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8625 SDValue IfTrue = N->getOperand(1);
8626 SDValue IfFalse = N->getOperand(2);
8628 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8629 N0.getOperand(0), N0.getOperand(1),
8630 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8631 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8635 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8636 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8637 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8638 /// with a vector one followed by a DUP shuffle on the result.
8639 static SDValue performSelectCombine(SDNode *N,
8640 TargetLowering::DAGCombinerInfo &DCI) {
8641 SelectionDAG &DAG = DCI.DAG;
8642 SDValue N0 = N->getOperand(0);
8643 EVT ResVT = N->getValueType(0);
8645 if (N0.getOpcode() != ISD::SETCC)
8648 // Make sure the SETCC result is either i1 (initial DAG), or i32, the lowered
8649 // scalar SetCCResultType. We also don't expect vectors, because we assume
8650 // that selects fed by vector SETCCs are canonicalized to VSELECT.
8651 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) &&
8652 "Scalar-SETCC feeding SELECT has unexpected result type!");
8654 // If NumMaskElts == 0, the comparison is larger than select result. The
8655 // largest real NEON comparison is 64-bits per lane, which means the result is
8656 // at most 32-bits and an illegal vector. Just bail out for now.
8657 EVT SrcVT = N0.getOperand(0).getValueType();
8659 // Don't try to do this optimization when the setcc itself has i1 operands.
8660 // There are no legal vectors of i1, so this would be pointless.
8661 if (SrcVT == MVT::i1)
8664 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8665 if (!ResVT.isVector() || NumMaskElts == 0)
8668 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8669 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8671 // Also bail out if the vector CCVT isn't the same size as ResVT.
8672 // This can happen if the SETCC operand size doesn't divide the ResVT size
8673 // (e.g., f64 vs v3f32).
8674 if (CCVT.getSizeInBits() != ResVT.getSizeInBits())
8677 // Make sure we didn't create illegal types, if we're not supposed to.
8678 assert(DCI.isBeforeLegalize() ||
8679 DAG.getTargetLoweringInfo().isTypeLegal(SrcVT));
8681 // First perform a vector comparison, where lane 0 is the one we're interested
8685 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8687 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8688 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8690 // Now duplicate the comparison mask we want across all other lanes.
8691 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8692 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8693 Mask = DAG.getNode(ISD::BITCAST, DL,
8694 ResVT.changeVectorElementTypeToInteger(), Mask);
8696 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8699 /// performSelectCCCombine - Target-specific DAG combining for ISD::SELECT_CC
8700 /// to match FMIN/FMAX patterns.
8701 static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
8702 // Try to use FMIN/FMAX instructions for FP selects like "x < y ? x : y".
8703 // Unless the NoNaNsFPMath option is set, be careful about NaNs:
8704 // vmax/vmin return NaN if either operand is a NaN;
8705 // only do the transformation when it matches that behavior.
8707 SDValue CondLHS = N->getOperand(0);
8708 SDValue CondRHS = N->getOperand(1);
8709 SDValue LHS = N->getOperand(2);
8710 SDValue RHS = N->getOperand(3);
8711 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
8715 if (selectCCOpsAreFMaxCompatible(CondLHS, LHS) &&
8716 selectCCOpsAreFMaxCompatible(CondRHS, RHS)) {
8717 IsReversed = false; // x CC y ? x : y
8718 } else if (selectCCOpsAreFMaxCompatible(CondRHS, LHS) &&
8719 selectCCOpsAreFMaxCompatible(CondLHS, RHS)) {
8720 IsReversed = true ; // x CC y ? y : x
8725 bool IsUnordered = false, IsOrEqual;
8736 IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);
8737 Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;
8747 IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);
8748 Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;
8752 // If LHS is NaN, an ordered comparison will be false and the result will be
8753 // the RHS, but FMIN(NaN, RHS) = FMAX(NaN, RHS) = NaN. Avoid this by checking
8754 // that LHS != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
8755 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
8758 // For xxx-or-equal comparisons, "+0 <= -0" and "-0 >= +0" will both be true,
8759 // but FMIN will return -0, and FMAX will return +0. So FMIN/FMAX can only be
8760 // used for unsafe math or if one of the operands is known to be nonzero.
8761 if (IsOrEqual && !DAG.getTarget().Options.UnsafeFPMath &&
8762 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8765 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
8768 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8769 DAGCombinerInfo &DCI) const {
8770 SelectionDAG &DAG = DCI.DAG;
8771 switch (N->getOpcode()) {
8776 return performAddSubLongCombine(N, DCI, DAG);
8778 return performXorCombine(N, DAG, DCI, Subtarget);
8780 return performMulCombine(N, DAG, DCI, Subtarget);
8781 case ISD::SINT_TO_FP:
8782 case ISD::UINT_TO_FP:
8783 return performIntToFpCombine(N, DAG, Subtarget);
8785 return performORCombine(N, DCI, Subtarget);
8786 case ISD::INTRINSIC_WO_CHAIN:
8787 return performIntrinsicCombine(N, DCI, Subtarget);
8788 case ISD::ANY_EXTEND:
8789 case ISD::ZERO_EXTEND:
8790 case ISD::SIGN_EXTEND:
8791 return performExtendCombine(N, DCI, DAG);
8793 return performBitcastCombine(N, DCI, DAG);
8794 case ISD::CONCAT_VECTORS:
8795 return performConcatVectorsCombine(N, DCI, DAG);
8797 return performSelectCombine(N, DCI);
8799 return performVSelectCombine(N, DCI.DAG);
8800 case ISD::SELECT_CC:
8801 return performSelectCCCombine(N, DCI.DAG);
8803 return performSTORECombine(N, DCI, DAG, Subtarget);
8804 case AArch64ISD::BRCOND:
8805 return performBRCONDCombine(N, DCI, DAG);
8806 case AArch64ISD::CSEL:
8807 return performCONDCombine(N, DCI, DAG, 2, 3);
8808 case AArch64ISD::DUP:
8809 return performPostLD1Combine(N, DCI, false);
8810 case ISD::INSERT_VECTOR_ELT:
8811 return performPostLD1Combine(N, DCI, true);
8812 case ISD::INTRINSIC_VOID:
8813 case ISD::INTRINSIC_W_CHAIN:
8814 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8815 case Intrinsic::aarch64_neon_ld2:
8816 case Intrinsic::aarch64_neon_ld3:
8817 case Intrinsic::aarch64_neon_ld4:
8818 case Intrinsic::aarch64_neon_ld1x2:
8819 case Intrinsic::aarch64_neon_ld1x3:
8820 case Intrinsic::aarch64_neon_ld1x4:
8821 case Intrinsic::aarch64_neon_ld2lane:
8822 case Intrinsic::aarch64_neon_ld3lane:
8823 case Intrinsic::aarch64_neon_ld4lane:
8824 case Intrinsic::aarch64_neon_ld2r:
8825 case Intrinsic::aarch64_neon_ld3r:
8826 case Intrinsic::aarch64_neon_ld4r:
8827 case Intrinsic::aarch64_neon_st2:
8828 case Intrinsic::aarch64_neon_st3:
8829 case Intrinsic::aarch64_neon_st4:
8830 case Intrinsic::aarch64_neon_st1x2:
8831 case Intrinsic::aarch64_neon_st1x3:
8832 case Intrinsic::aarch64_neon_st1x4:
8833 case Intrinsic::aarch64_neon_st2lane:
8834 case Intrinsic::aarch64_neon_st3lane:
8835 case Intrinsic::aarch64_neon_st4lane:
8836 return performNEONPostLDSTCombine(N, DCI, DAG);
8844 // Check if the return value is used as only a return value, as otherwise
8845 // we can't perform a tail-call. In particular, we need to check for
8846 // target ISD nodes that are returns and any other "odd" constructs
8847 // that the generic analysis code won't necessarily catch.
8848 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8849 SDValue &Chain) const {
8850 if (N->getNumValues() != 1)
8852 if (!N->hasNUsesOfValue(1, 0))
8855 SDValue TCChain = Chain;
8856 SDNode *Copy = *N->use_begin();
8857 if (Copy->getOpcode() == ISD::CopyToReg) {
8858 // If the copy has a glue operand, we conservatively assume it isn't safe to
8859 // perform a tail call.
8860 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8863 TCChain = Copy->getOperand(0);
8864 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8867 bool HasRet = false;
8868 for (SDNode *Node : Copy->uses()) {
8869 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8881 // Return whether the an instruction can potentially be optimized to a tail
8882 // call. This will cause the optimizers to attempt to move, or duplicate,
8883 // return instructions to help enable tail call optimizations for this
8885 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8886 if (!CI->isTailCall())
8892 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8894 ISD::MemIndexedMode &AM,
8896 SelectionDAG &DAG) const {
8897 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8900 Base = Op->getOperand(0);
8901 // All of the indexed addressing mode instructions take a signed
8902 // 9 bit immediate offset.
8903 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8904 int64_t RHSC = (int64_t)RHS->getZExtValue();
8905 if (RHSC >= 256 || RHSC <= -256)
8907 IsInc = (Op->getOpcode() == ISD::ADD);
8908 Offset = Op->getOperand(1);
8914 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8916 ISD::MemIndexedMode &AM,
8917 SelectionDAG &DAG) const {
8920 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8921 VT = LD->getMemoryVT();
8922 Ptr = LD->getBasePtr();
8923 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8924 VT = ST->getMemoryVT();
8925 Ptr = ST->getBasePtr();
8930 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8932 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8936 bool AArch64TargetLowering::getPostIndexedAddressParts(
8937 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8938 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8941 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8942 VT = LD->getMemoryVT();
8943 Ptr = LD->getBasePtr();
8944 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8945 VT = ST->getMemoryVT();
8946 Ptr = ST->getBasePtr();
8951 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8953 // Post-indexing updates the base, so it's not a valid transform
8954 // if that's not the same as the load's pointer.
8957 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8961 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8962 SelectionDAG &DAG) {
8964 SDValue Op = N->getOperand(0);
8966 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)
8970 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8971 DAG.getUNDEF(MVT::i32), Op,
8972 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
8974 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8975 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8978 void AArch64TargetLowering::ReplaceNodeResults(
8979 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8980 switch (N->getOpcode()) {
8982 llvm_unreachable("Don't know how to custom expand this");
8984 ReplaceBITCASTResults(N, Results, DAG);
8986 case ISD::FP_TO_UINT:
8987 case ISD::FP_TO_SINT:
8988 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8989 // Let normal code take care of it by not adding anything to Results.
8994 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8998 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8999 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9000 // reciprocal if there are three or more FDIVs.
9001 return NumUsers > 2;
9004 TargetLoweringBase::LegalizeTypeAction
9005 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
9006 MVT SVT = VT.getSimpleVT();
9007 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
9008 // v4i16, v2i32 instead of to promote.
9009 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
9010 || SVT == MVT::v1f32)
9011 return TypeWidenVector;
9013 return TargetLoweringBase::getPreferredVectorAction(VT);
9016 // Loads and stores less than 128-bits are already atomic; ones above that
9017 // are doomed anyway, so defer to the default libcall and blame the OS when
9019 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
9020 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
9024 // Loads and stores less than 128-bits are already atomic; ones above that
9025 // are doomed anyway, so defer to the default libcall and blame the OS when
9027 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
9028 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
9032 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
9033 TargetLoweringBase::AtomicRMWExpansionKind
9034 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
9035 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
9036 return Size <= 128 ? AtomicRMWExpansionKind::LLSC
9037 : AtomicRMWExpansionKind::None;
9040 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
9044 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
9045 AtomicOrdering Ord) const {
9046 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9047 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
9048 bool IsAcquire = isAtLeastAcquire(Ord);
9050 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9051 // intrinsic must return {i64, i64} and we have to recombine them into a
9052 // single i128 here.
9053 if (ValTy->getPrimitiveSizeInBits() == 128) {
9055 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
9056 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
9058 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9059 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
9061 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
9062 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
9063 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
9064 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
9065 return Builder.CreateOr(
9066 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
9069 Type *Tys[] = { Addr->getType() };
9071 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
9072 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
9074 return Builder.CreateTruncOrBitCast(
9075 Builder.CreateCall(Ldxr, Addr),
9076 cast<PointerType>(Addr->getType())->getElementType());
9079 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
9080 Value *Val, Value *Addr,
9081 AtomicOrdering Ord) const {
9082 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
9083 bool IsRelease = isAtLeastRelease(Ord);
9085 // Since the intrinsics must have legal type, the i128 intrinsics take two
9086 // parameters: "i64, i64". We must marshal Val into the appropriate form
9088 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
9090 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
9091 Function *Stxr = Intrinsic::getDeclaration(M, Int);
9092 Type *Int64Ty = Type::getInt64Ty(M->getContext());
9094 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
9095 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
9096 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
9097 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
9101 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
9102 Type *Tys[] = { Addr->getType() };
9103 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
9105 return Builder.CreateCall2(
9106 Stxr, Builder.CreateZExtOrBitCast(
9107 Val, Stxr->getFunctionType()->getParamType(0)),
9111 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
9112 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
9113 return Ty->isArrayTy();