1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the AArch64 target.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "MCTargetDesc/AArch64AddressingModes.h"
16 #include "llvm/ADT/APSInt.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/IR/Function.h" // To access function attributes.
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/IR/Intrinsics.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "aarch64-isel"
30 //===--------------------------------------------------------------------===//
31 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
32 /// instructions for SelectionDAG operations.
36 class AArch64DAGToDAGISel : public SelectionDAGISel {
37 AArch64TargetMachine &TM;
39 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const AArch64Subtarget *Subtarget;
46 explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
47 CodeGenOpt::Level OptLevel)
48 : SelectionDAGISel(tm, OptLevel), TM(tm), Subtarget(nullptr),
51 const char *getPassName() const override {
52 return "AArch64 Instruction Selection";
55 bool runOnMachineFunction(MachineFunction &MF) override {
56 AttributeSet FnAttrs = MF.getFunction()->getAttributes();
58 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
59 Attribute::OptimizeForSize) ||
60 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
61 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
62 return SelectionDAGISel::runOnMachineFunction(MF);
65 SDNode *Select(SDNode *Node) override;
67 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
68 /// inline asm expressions.
69 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
71 std::vector<SDValue> &OutOps) override;
73 SDNode *SelectMLAV64LaneV128(SDNode *N);
74 SDNode *SelectMULLV64LaneV128(unsigned IntNo, SDNode *N);
75 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
76 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
77 bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
78 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
79 return SelectShiftedRegister(N, false, Reg, Shift);
81 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
82 return SelectShiftedRegister(N, true, Reg, Shift);
84 bool SelectAddrModeIndexed8(SDValue N, SDValue &Base, SDValue &OffImm) {
85 return SelectAddrModeIndexed(N, 1, Base, OffImm);
87 bool SelectAddrModeIndexed16(SDValue N, SDValue &Base, SDValue &OffImm) {
88 return SelectAddrModeIndexed(N, 2, Base, OffImm);
90 bool SelectAddrModeIndexed32(SDValue N, SDValue &Base, SDValue &OffImm) {
91 return SelectAddrModeIndexed(N, 4, Base, OffImm);
93 bool SelectAddrModeIndexed64(SDValue N, SDValue &Base, SDValue &OffImm) {
94 return SelectAddrModeIndexed(N, 8, Base, OffImm);
96 bool SelectAddrModeIndexed128(SDValue N, SDValue &Base, SDValue &OffImm) {
97 return SelectAddrModeIndexed(N, 16, Base, OffImm);
99 bool SelectAddrModeUnscaled8(SDValue N, SDValue &Base, SDValue &OffImm) {
100 return SelectAddrModeUnscaled(N, 1, Base, OffImm);
102 bool SelectAddrModeUnscaled16(SDValue N, SDValue &Base, SDValue &OffImm) {
103 return SelectAddrModeUnscaled(N, 2, Base, OffImm);
105 bool SelectAddrModeUnscaled32(SDValue N, SDValue &Base, SDValue &OffImm) {
106 return SelectAddrModeUnscaled(N, 4, Base, OffImm);
108 bool SelectAddrModeUnscaled64(SDValue N, SDValue &Base, SDValue &OffImm) {
109 return SelectAddrModeUnscaled(N, 8, Base, OffImm);
111 bool SelectAddrModeUnscaled128(SDValue N, SDValue &Base, SDValue &OffImm) {
112 return SelectAddrModeUnscaled(N, 16, Base, OffImm);
116 bool SelectAddrModeWRO(SDValue N, SDValue &Base, SDValue &Offset,
117 SDValue &SignExtend, SDValue &DoShift) {
118 return SelectAddrModeWRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
122 bool SelectAddrModeXRO(SDValue N, SDValue &Base, SDValue &Offset,
123 SDValue &SignExtend, SDValue &DoShift) {
124 return SelectAddrModeXRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
128 /// Form sequences of consecutive 64/128-bit registers for use in NEON
129 /// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
130 /// between 1 and 4 elements. If it contains a single element that is returned
131 /// unchanged; otherwise a REG_SEQUENCE value is returned.
132 SDValue createDTuple(ArrayRef<SDValue> Vecs);
133 SDValue createQTuple(ArrayRef<SDValue> Vecs);
135 /// Generic helper for the createDTuple/createQTuple
136 /// functions. Those should almost always be called instead.
137 SDValue createTuple(ArrayRef<SDValue> Vecs, unsigned RegClassIDs[],
140 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
142 SDNode *SelectIndexedLoad(SDNode *N, bool &Done);
144 SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
146 SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
148 SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
149 SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
151 SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
152 SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
153 SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
154 SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
156 SDNode *SelectBitfieldExtractOp(SDNode *N);
157 SDNode *SelectBitfieldInsertOp(SDNode *N);
159 SDNode *SelectLIBM(SDNode *N);
161 // Include the pieces autogenerated from the target description.
162 #include "AArch64GenDAGISel.inc"
165 bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
167 bool SelectAddrModeIndexed(SDValue N, unsigned Size, SDValue &Base,
169 bool SelectAddrModeUnscaled(SDValue N, unsigned Size, SDValue &Base,
171 bool SelectAddrModeWRO(SDValue N, unsigned Size, SDValue &Base,
172 SDValue &Offset, SDValue &SignExtend,
174 bool SelectAddrModeXRO(SDValue N, unsigned Size, SDValue &Base,
175 SDValue &Offset, SDValue &SignExtend,
177 bool isWorthFolding(SDValue V) const;
178 bool SelectExtendedSHL(SDValue N, unsigned Size, bool WantExtend,
179 SDValue &Offset, SDValue &SignExtend);
181 template<unsigned RegWidth>
182 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
183 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
186 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
188 } // end anonymous namespace
190 /// isIntImmediate - This method tests to see if the node is a constant
191 /// operand. If so Imm will receive the 32-bit value.
192 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
193 if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
194 Imm = C->getZExtValue();
200 // isIntImmediate - This method tests to see if a constant operand.
201 // If so Imm will receive the value.
202 static bool isIntImmediate(SDValue N, uint64_t &Imm) {
203 return isIntImmediate(N.getNode(), Imm);
206 // isOpcWithIntImmediate - This method tests to see if the node is a specific
207 // opcode and that it has a immediate integer right operand.
208 // If so Imm will receive the 32 bit value.
209 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
211 return N->getOpcode() == Opc &&
212 isIntImmediate(N->getOperand(1).getNode(), Imm);
215 bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
216 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
217 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
218 // Require the address to be in a register. That is safe for all AArch64
219 // variants and it is hard to do anything much smarter without knowing
220 // how the operand is used.
221 OutOps.push_back(Op);
225 /// SelectArithImmed - Select an immediate value that can be represented as
226 /// a 12-bit value shifted left by either 0 or 12. If so, return true with
227 /// Val set to the 12-bit value and Shift set to the shifter operand.
228 bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
230 // This function is called from the addsub_shifted_imm ComplexPattern,
231 // which lists [imm] as the list of opcode it's interested in, however
232 // we still need to check whether the operand is actually an immediate
233 // here because the ComplexPattern opcode list is only used in
234 // root-level opcode matching.
235 if (!isa<ConstantSDNode>(N.getNode()))
238 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
241 if (Immed >> 12 == 0) {
243 } else if ((Immed & 0xfff) == 0 && Immed >> 24 == 0) {
249 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
250 Val = CurDAG->getTargetConstant(Immed, MVT::i32);
251 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
255 /// SelectNegArithImmed - As above, but negates the value before trying to
257 bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
259 // This function is called from the addsub_shifted_imm ComplexPattern,
260 // which lists [imm] as the list of opcode it's interested in, however
261 // we still need to check whether the operand is actually an immediate
262 // here because the ComplexPattern opcode list is only used in
263 // root-level opcode matching.
264 if (!isa<ConstantSDNode>(N.getNode()))
267 // The immediate operand must be a 24-bit zero-extended immediate.
268 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
270 // This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
271 // have the opposite effect on the C flag, so this pattern mustn't match under
272 // those circumstances.
276 if (N.getValueType() == MVT::i32)
277 Immed = ~((uint32_t)Immed) + 1;
279 Immed = ~Immed + 1ULL;
280 if (Immed & 0xFFFFFFFFFF000000ULL)
283 Immed &= 0xFFFFFFULL;
284 return SelectArithImmed(CurDAG->getConstant(Immed, MVT::i32), Val, Shift);
287 /// getShiftTypeForNode - Translate a shift node to the corresponding
289 static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
290 switch (N.getOpcode()) {
292 return AArch64_AM::InvalidShiftExtend;
294 return AArch64_AM::LSL;
296 return AArch64_AM::LSR;
298 return AArch64_AM::ASR;
300 return AArch64_AM::ROR;
304 /// \brief Determine wether it is worth to fold V into an extended register.
305 bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
306 // it hurts if the value is used at least twice, unless we are optimizing
308 if (ForCodeSize || V.hasOneUse())
313 /// SelectShiftedRegister - Select a "shifted register" operand. If the value
314 /// is not shifted, set the Shift operand to default of "LSL 0". The logical
315 /// instructions allow the shifted register to be rotated, but the arithmetic
316 /// instructions do not. The AllowROR parameter specifies whether ROR is
318 bool AArch64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
319 SDValue &Reg, SDValue &Shift) {
320 AArch64_AM::ShiftExtendType ShType = getShiftTypeForNode(N);
321 if (ShType == AArch64_AM::InvalidShiftExtend)
323 if (!AllowROR && ShType == AArch64_AM::ROR)
326 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
327 unsigned BitSize = N.getValueType().getSizeInBits();
328 unsigned Val = RHS->getZExtValue() & (BitSize - 1);
329 unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val);
331 Reg = N.getOperand(0);
332 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
333 return isWorthFolding(N);
339 /// getExtendTypeForNode - Translate an extend node to the corresponding
340 /// ExtendType value.
341 static AArch64_AM::ShiftExtendType
342 getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
343 if (N.getOpcode() == ISD::SIGN_EXTEND ||
344 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
346 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
347 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
349 SrcVT = N.getOperand(0).getValueType();
351 if (!IsLoadStore && SrcVT == MVT::i8)
352 return AArch64_AM::SXTB;
353 else if (!IsLoadStore && SrcVT == MVT::i16)
354 return AArch64_AM::SXTH;
355 else if (SrcVT == MVT::i32)
356 return AArch64_AM::SXTW;
357 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
359 return AArch64_AM::InvalidShiftExtend;
360 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
361 N.getOpcode() == ISD::ANY_EXTEND) {
362 EVT SrcVT = N.getOperand(0).getValueType();
363 if (!IsLoadStore && SrcVT == MVT::i8)
364 return AArch64_AM::UXTB;
365 else if (!IsLoadStore && SrcVT == MVT::i16)
366 return AArch64_AM::UXTH;
367 else if (SrcVT == MVT::i32)
368 return AArch64_AM::UXTW;
369 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
371 return AArch64_AM::InvalidShiftExtend;
372 } else if (N.getOpcode() == ISD::AND) {
373 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
375 return AArch64_AM::InvalidShiftExtend;
376 uint64_t AndMask = CSD->getZExtValue();
380 return AArch64_AM::InvalidShiftExtend;
382 return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend;
384 return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend;
386 return AArch64_AM::UXTW;
390 return AArch64_AM::InvalidShiftExtend;
393 // Helper for SelectMLAV64LaneV128 - Recognize high lane extracts.
394 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) {
395 if (DL->getOpcode() != AArch64ISD::DUPLANE16 &&
396 DL->getOpcode() != AArch64ISD::DUPLANE32)
399 SDValue SV = DL->getOperand(0);
400 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
403 SDValue EV = SV.getOperand(1);
404 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
407 ConstantSDNode *DLidx = cast<ConstantSDNode>(DL->getOperand(1).getNode());
408 ConstantSDNode *EVidx = cast<ConstantSDNode>(EV.getOperand(1).getNode());
409 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
410 LaneOp = EV.getOperand(0);
415 // Helper for SelectOpcV64LaneV128 - Recogzine operatinos where one operand is a
416 // high lane extract.
417 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
418 SDValue &LaneOp, int &LaneIdx) {
420 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
422 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
429 /// SelectMLAV64LaneV128 - AArch64 supports vector MLAs where one multiplicand
430 /// is a lane in the upper half of a 128-bit vector. Recognize and select this
431 /// so that we don't emit unnecessary lane extracts.
432 SDNode *AArch64DAGToDAGISel::SelectMLAV64LaneV128(SDNode *N) {
433 SDValue Op0 = N->getOperand(0);
434 SDValue Op1 = N->getOperand(1);
435 SDValue MLAOp1; // Will hold ordinary multiplicand for MLA.
436 SDValue MLAOp2; // Will hold lane-accessed multiplicand for MLA.
437 int LaneIdx = -1; // Will hold the lane index.
439 if (Op1.getOpcode() != ISD::MUL ||
440 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
443 if (Op1.getOpcode() != ISD::MUL ||
444 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
449 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
451 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
453 unsigned MLAOpc = ~0U;
455 switch (N->getSimpleValueType(0).SimpleTy) {
457 llvm_unreachable("Unrecognized MLA.");
459 MLAOpc = AArch64::MLAv4i16_indexed;
462 MLAOpc = AArch64::MLAv8i16_indexed;
465 MLAOpc = AArch64::MLAv2i32_indexed;
468 MLAOpc = AArch64::MLAv4i32_indexed;
472 return CurDAG->getMachineNode(MLAOpc, SDLoc(N), N->getValueType(0), Ops);
475 SDNode *AArch64DAGToDAGISel::SelectMULLV64LaneV128(unsigned IntNo, SDNode *N) {
480 if (!checkV64LaneV128(N->getOperand(1), N->getOperand(2), SMULLOp0, SMULLOp1,
484 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
486 SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
488 unsigned SMULLOpc = ~0U;
490 if (IntNo == Intrinsic::aarch64_neon_smull) {
491 switch (N->getSimpleValueType(0).SimpleTy) {
493 llvm_unreachable("Unrecognized SMULL.");
495 SMULLOpc = AArch64::SMULLv4i16_indexed;
498 SMULLOpc = AArch64::SMULLv2i32_indexed;
501 } else if (IntNo == Intrinsic::aarch64_neon_umull) {
502 switch (N->getSimpleValueType(0).SimpleTy) {
504 llvm_unreachable("Unrecognized SMULL.");
506 SMULLOpc = AArch64::UMULLv4i16_indexed;
509 SMULLOpc = AArch64::UMULLv2i32_indexed;
513 llvm_unreachable("Unrecognized intrinsic.");
515 return CurDAG->getMachineNode(SMULLOpc, SDLoc(N), N->getValueType(0), Ops);
518 /// Instructions that accept extend modifiers like UXTW expect the register
519 /// being extended to be a GPR32, but the incoming DAG might be acting on a
520 /// GPR64 (either via SEXT_INREG or AND). Extract the appropriate low bits if
521 /// this is the case.
522 static SDValue narrowIfNeeded(SelectionDAG *CurDAG, SDValue N) {
523 if (N.getValueType() == MVT::i32)
526 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
527 MachineSDNode *Node = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
528 SDLoc(N), MVT::i32, N, SubReg);
529 return SDValue(Node, 0);
533 /// SelectArithExtendedRegister - Select a "extended register" operand. This
534 /// operand folds in an extend followed by an optional left shift.
535 bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
537 unsigned ShiftVal = 0;
538 AArch64_AM::ShiftExtendType Ext;
540 if (N.getOpcode() == ISD::SHL) {
541 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
544 ShiftVal = CSD->getZExtValue();
548 Ext = getExtendTypeForNode(N.getOperand(0));
549 if (Ext == AArch64_AM::InvalidShiftExtend)
552 Reg = N.getOperand(0).getOperand(0);
554 Ext = getExtendTypeForNode(N);
555 if (Ext == AArch64_AM::InvalidShiftExtend)
558 Reg = N.getOperand(0);
561 // AArch64 mandates that the RHS of the operation must use the smallest
562 // register classs that could contain the size being extended from. Thus,
563 // if we're folding a (sext i8), we need the RHS to be a GPR32, even though
564 // there might not be an actual 32-bit value in the program. We can
565 // (harmlessly) synthesize one by injected an EXTRACT_SUBREG here.
566 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
567 Reg = narrowIfNeeded(CurDAG, Reg);
568 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), MVT::i32);
569 return isWorthFolding(N);
572 /// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit
573 /// immediate" address. The "Size" argument is the size in bytes of the memory
574 /// reference, which determines the scale.
575 bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
576 SDValue &Base, SDValue &OffImm) {
577 const TargetLowering *TLI = getTargetLowering();
578 if (N.getOpcode() == ISD::FrameIndex) {
579 int FI = cast<FrameIndexSDNode>(N)->getIndex();
580 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
581 OffImm = CurDAG->getTargetConstant(0, MVT::i64);
585 if (N.getOpcode() == AArch64ISD::ADDlow) {
586 GlobalAddressSDNode *GAN =
587 dyn_cast<GlobalAddressSDNode>(N.getOperand(1).getNode());
588 Base = N.getOperand(0);
589 OffImm = N.getOperand(1);
593 const GlobalValue *GV = GAN->getGlobal();
594 unsigned Alignment = GV->getAlignment();
595 const DataLayout *DL = TLI->getDataLayout();
596 Type *Ty = GV->getType()->getElementType();
597 if (Alignment == 0 && Ty->isSized() && !Subtarget->isTargetDarwin())
598 Alignment = DL->getABITypeAlignment(Ty);
600 if (Alignment >= Size)
604 if (CurDAG->isBaseWithConstantOffset(N)) {
605 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
606 int64_t RHSC = (int64_t)RHS->getZExtValue();
607 unsigned Scale = Log2_32(Size);
608 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
609 Base = N.getOperand(0);
610 if (Base.getOpcode() == ISD::FrameIndex) {
611 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
612 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
614 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, MVT::i64);
620 // Before falling back to our general case, check if the unscaled
621 // instructions can handle this. If so, that's preferable.
622 if (SelectAddrModeUnscaled(N, Size, Base, OffImm))
625 // Base only. The address will be materialized into a register before
626 // the memory is accessed.
627 // add x0, Xbase, #offset
630 OffImm = CurDAG->getTargetConstant(0, MVT::i64);
634 /// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bit
635 /// immediate" address. This should only match when there is an offset that
636 /// is not valid for a scaled immediate addressing mode. The "Size" argument
637 /// is the size in bytes of the memory reference, which is needed here to know
638 /// what is valid for a scaled immediate.
639 bool AArch64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
642 if (!CurDAG->isBaseWithConstantOffset(N))
644 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
645 int64_t RHSC = RHS->getSExtValue();
646 // If the offset is valid as a scaled immediate, don't match here.
647 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 &&
648 RHSC < (0x1000 << Log2_32(Size)))
650 if (RHSC >= -256 && RHSC < 256) {
651 Base = N.getOperand(0);
652 if (Base.getOpcode() == ISD::FrameIndex) {
653 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
654 const TargetLowering *TLI = getTargetLowering();
655 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
657 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i64);
664 static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
665 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
666 SDValue ImpDef = SDValue(
667 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, SDLoc(N), MVT::i64),
669 MachineSDNode *Node = CurDAG->getMachineNode(
670 TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg);
671 return SDValue(Node, 0);
674 /// \brief Check if the given SHL node (\p N), can be used to form an
675 /// extended register for an addressing mode.
676 bool AArch64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
677 bool WantExtend, SDValue &Offset,
678 SDValue &SignExtend) {
679 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
680 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
681 if (!CSD || (CSD->getZExtValue() & 0x7) != CSD->getZExtValue())
685 AArch64_AM::ShiftExtendType Ext =
686 getExtendTypeForNode(N.getOperand(0), true);
687 if (Ext == AArch64_AM::InvalidShiftExtend)
690 Offset = narrowIfNeeded(CurDAG, N.getOperand(0).getOperand(0));
691 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32);
693 Offset = N.getOperand(0);
694 SignExtend = CurDAG->getTargetConstant(0, MVT::i32);
697 unsigned LegalShiftVal = Log2_32(Size);
698 unsigned ShiftVal = CSD->getZExtValue();
700 if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
703 if (isWorthFolding(N))
709 bool AArch64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
710 SDValue &Base, SDValue &Offset,
713 if (N.getOpcode() != ISD::ADD)
715 SDValue LHS = N.getOperand(0);
716 SDValue RHS = N.getOperand(1);
718 // We don't want to match immediate adds here, because they are better lowered
719 // to the register-immediate addressing modes.
720 if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
723 // Check if this particular node is reused in any non-memory related
724 // operation. If yes, do not try to fold this node into the address
725 // computation, since the computation will be kept.
726 const SDNode *Node = N.getNode();
727 for (SDNode *UI : Node->uses()) {
728 if (!isa<MemSDNode>(*UI))
732 // Remember if it is worth folding N when it produces extended register.
733 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
735 // Try to match a shifted extend on the RHS.
736 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
737 SelectExtendedSHL(RHS, Size, true, Offset, SignExtend)) {
739 DoShift = CurDAG->getTargetConstant(true, MVT::i32);
743 // Try to match a shifted extend on the LHS.
744 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
745 SelectExtendedSHL(LHS, Size, true, Offset, SignExtend)) {
747 DoShift = CurDAG->getTargetConstant(true, MVT::i32);
751 // There was no shift, whatever else we find.
752 DoShift = CurDAG->getTargetConstant(false, MVT::i32);
754 AArch64_AM::ShiftExtendType Ext = AArch64_AM::InvalidShiftExtend;
755 // Try to match an unshifted extend on the LHS.
756 if (IsExtendedRegisterWorthFolding &&
757 (Ext = getExtendTypeForNode(LHS, true)) !=
758 AArch64_AM::InvalidShiftExtend) {
760 Offset = narrowIfNeeded(CurDAG, LHS.getOperand(0));
761 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32);
762 if (isWorthFolding(LHS))
766 // Try to match an unshifted extend on the RHS.
767 if (IsExtendedRegisterWorthFolding &&
768 (Ext = getExtendTypeForNode(RHS, true)) !=
769 AArch64_AM::InvalidShiftExtend) {
771 Offset = narrowIfNeeded(CurDAG, RHS.getOperand(0));
772 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32);
773 if (isWorthFolding(RHS))
780 bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
781 SDValue &Base, SDValue &Offset,
784 if (N.getOpcode() != ISD::ADD)
786 SDValue LHS = N.getOperand(0);
787 SDValue RHS = N.getOperand(1);
789 // We don't want to match immediate adds here, because they are better lowered
790 // to the register-immediate addressing modes.
791 if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
794 // Check if this particular node is reused in any non-memory related
795 // operation. If yes, do not try to fold this node into the address
796 // computation, since the computation will be kept.
797 const SDNode *Node = N.getNode();
798 for (SDNode *UI : Node->uses()) {
799 if (!isa<MemSDNode>(*UI))
803 // Remember if it is worth folding N when it produces extended register.
804 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
806 // Try to match a shifted extend on the RHS.
807 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
808 SelectExtendedSHL(RHS, Size, false, Offset, SignExtend)) {
810 DoShift = CurDAG->getTargetConstant(true, MVT::i32);
814 // Try to match a shifted extend on the LHS.
815 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
816 SelectExtendedSHL(LHS, Size, false, Offset, SignExtend)) {
818 DoShift = CurDAG->getTargetConstant(true, MVT::i32);
822 // Match any non-shifted, non-extend, non-immediate add expression.
825 SignExtend = CurDAG->getTargetConstant(false, MVT::i32);
826 DoShift = CurDAG->getTargetConstant(false, MVT::i32);
827 // Reg1 + Reg2 is free: no check needed.
831 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
832 static unsigned RegClassIDs[] = {
833 AArch64::DDRegClassID, AArch64::DDDRegClassID, AArch64::DDDDRegClassID};
834 static unsigned SubRegs[] = { AArch64::dsub0, AArch64::dsub1,
835 AArch64::dsub2, AArch64::dsub3 };
837 return createTuple(Regs, RegClassIDs, SubRegs);
840 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
841 static unsigned RegClassIDs[] = {
842 AArch64::QQRegClassID, AArch64::QQQRegClassID, AArch64::QQQQRegClassID};
843 static unsigned SubRegs[] = { AArch64::qsub0, AArch64::qsub1,
844 AArch64::qsub2, AArch64::qsub3 };
846 return createTuple(Regs, RegClassIDs, SubRegs);
849 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
850 unsigned RegClassIDs[],
851 unsigned SubRegs[]) {
852 // There's no special register-class for a vector-list of 1 element: it's just
854 if (Regs.size() == 1)
857 assert(Regs.size() >= 2 && Regs.size() <= 4);
859 SDLoc DL(Regs[0].getNode());
861 SmallVector<SDValue, 4> Ops;
863 // First operand of REG_SEQUENCE is the desired RegClass.
865 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], MVT::i32));
867 // Then we get pairs of source & subregister-position for the components.
868 for (unsigned i = 0; i < Regs.size(); ++i) {
869 Ops.push_back(Regs[i]);
870 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], MVT::i32));
874 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
875 return SDValue(N, 0);
878 SDNode *AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs,
879 unsigned Opc, bool isExt) {
881 EVT VT = N->getValueType(0);
883 unsigned ExtOff = isExt;
885 // Form a REG_SEQUENCE to force register allocation.
886 unsigned Vec0Off = ExtOff + 1;
887 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
888 N->op_begin() + Vec0Off + NumVecs);
889 SDValue RegSeq = createQTuple(Regs);
891 SmallVector<SDValue, 6> Ops;
893 Ops.push_back(N->getOperand(1));
894 Ops.push_back(RegSeq);
895 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
896 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
899 SDNode *AArch64DAGToDAGISel::SelectIndexedLoad(SDNode *N, bool &Done) {
900 LoadSDNode *LD = cast<LoadSDNode>(N);
901 if (LD->isUnindexed())
903 EVT VT = LD->getMemoryVT();
904 EVT DstVT = N->getValueType(0);
905 ISD::MemIndexedMode AM = LD->getAddressingMode();
906 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
908 // We're not doing validity checking here. That was done when checking
909 // if we should mark the load as indexed or not. We're just selecting
910 // the right instruction.
913 ISD::LoadExtType ExtType = LD->getExtensionType();
914 bool InsertTo64 = false;
916 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost;
917 else if (VT == MVT::i32) {
918 if (ExtType == ISD::NON_EXTLOAD)
919 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
920 else if (ExtType == ISD::SEXTLOAD)
921 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost;
923 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
925 // The result of the load is only i32. It's the subreg_to_reg that makes
929 } else if (VT == MVT::i16) {
930 if (ExtType == ISD::SEXTLOAD) {
931 if (DstVT == MVT::i64)
932 Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost;
934 Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost;
936 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost;
937 InsertTo64 = DstVT == MVT::i64;
938 // The result of the load is only i32. It's the subreg_to_reg that makes
942 } else if (VT == MVT::i8) {
943 if (ExtType == ISD::SEXTLOAD) {
944 if (DstVT == MVT::i64)
945 Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost;
947 Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost;
949 Opcode = IsPre ? AArch64::LDRBBpre : AArch64::LDRBBpost;
950 InsertTo64 = DstVT == MVT::i64;
951 // The result of the load is only i32. It's the subreg_to_reg that makes
955 } else if (VT == MVT::f32) {
956 Opcode = IsPre ? AArch64::LDRSpre : AArch64::LDRSpost;
957 } else if (VT == MVT::f64 || VT.is64BitVector()) {
958 Opcode = IsPre ? AArch64::LDRDpre : AArch64::LDRDpost;
959 } else if (VT.is128BitVector()) {
960 Opcode = IsPre ? AArch64::LDRQpre : AArch64::LDRQpost;
963 SDValue Chain = LD->getChain();
964 SDValue Base = LD->getBasePtr();
965 ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
966 int OffsetVal = (int)OffsetOp->getZExtValue();
967 SDValue Offset = CurDAG->getTargetConstant(OffsetVal, MVT::i64);
968 SDValue Ops[] = { Base, Offset, Chain };
969 SDNode *Res = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, DstVT,
971 // Either way, we're replacing the node, so tell the caller that.
973 SDValue LoadedVal = SDValue(Res, 1);
975 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
977 SDValue(CurDAG->getMachineNode(
978 AArch64::SUBREG_TO_REG, SDLoc(N), MVT::i64,
979 CurDAG->getTargetConstant(0, MVT::i64), LoadedVal, SubReg),
983 ReplaceUses(SDValue(N, 0), LoadedVal);
984 ReplaceUses(SDValue(N, 1), SDValue(Res, 0));
985 ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
990 SDNode *AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs,
991 unsigned Opc, unsigned SubRegIdx) {
993 EVT VT = N->getValueType(0);
994 SDValue Chain = N->getOperand(0);
996 SmallVector<SDValue, 6> Ops;
997 Ops.push_back(N->getOperand(2)); // Mem operand;
998 Ops.push_back(Chain);
1000 std::vector<EVT> ResTys;
1001 ResTys.push_back(MVT::Untyped);
1002 ResTys.push_back(MVT::Other);
1004 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1005 SDValue SuperReg = SDValue(Ld, 0);
1006 for (unsigned i = 0; i < NumVecs; ++i)
1007 ReplaceUses(SDValue(N, i),
1008 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1010 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1014 SDNode *AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
1015 unsigned Opc, unsigned SubRegIdx) {
1017 EVT VT = N->getValueType(0);
1018 SDValue Chain = N->getOperand(0);
1020 SmallVector<SDValue, 6> Ops;
1021 Ops.push_back(N->getOperand(1)); // Mem operand
1022 Ops.push_back(N->getOperand(2)); // Incremental
1023 Ops.push_back(Chain);
1025 std::vector<EVT> ResTys;
1026 ResTys.push_back(MVT::i64); // Type of the write back register
1027 ResTys.push_back(MVT::Untyped);
1028 ResTys.push_back(MVT::Other);
1030 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1032 // Update uses of write back register
1033 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1035 // Update uses of vector list
1036 SDValue SuperReg = SDValue(Ld, 1);
1038 ReplaceUses(SDValue(N, 0), SuperReg);
1040 for (unsigned i = 0; i < NumVecs; ++i)
1041 ReplaceUses(SDValue(N, i),
1042 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1045 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1049 SDNode *AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
1052 EVT VT = N->getOperand(2)->getValueType(0);
1054 // Form a REG_SEQUENCE to force register allocation.
1055 bool Is128Bit = VT.getSizeInBits() == 128;
1056 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1057 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1059 SmallVector<SDValue, 6> Ops;
1060 Ops.push_back(RegSeq);
1061 Ops.push_back(N->getOperand(NumVecs + 2));
1062 Ops.push_back(N->getOperand(0));
1063 SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
1068 SDNode *AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
1071 EVT VT = N->getOperand(2)->getValueType(0);
1072 SmallVector<EVT, 2> ResTys;
1073 ResTys.push_back(MVT::i64); // Type of the write back register
1074 ResTys.push_back(MVT::Other); // Type for the Chain
1076 // Form a REG_SEQUENCE to force register allocation.
1077 bool Is128Bit = VT.getSizeInBits() == 128;
1078 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1079 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1081 SmallVector<SDValue, 6> Ops;
1082 Ops.push_back(RegSeq);
1083 Ops.push_back(N->getOperand(NumVecs + 1)); // base register
1084 Ops.push_back(N->getOperand(NumVecs + 2)); // Incremental
1085 Ops.push_back(N->getOperand(0)); // Chain
1086 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1091 /// WidenVector - Given a value in the V64 register class, produce the
1092 /// equivalent value in the V128 register class.
1097 WidenVector(SelectionDAG &DAG) : DAG(DAG) {}
1099 SDValue operator()(SDValue V64Reg) {
1100 EVT VT = V64Reg.getValueType();
1101 unsigned NarrowSize = VT.getVectorNumElements();
1102 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1103 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
1107 SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
1108 return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg);
1112 /// NarrowVector - Given a value in the V128 register class, produce the
1113 /// equivalent value in the V64 register class.
1114 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
1115 EVT VT = V128Reg.getValueType();
1116 unsigned WideSize = VT.getVectorNumElements();
1117 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1118 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
1120 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy,
1124 SDNode *AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
1127 EVT VT = N->getValueType(0);
1128 bool Narrow = VT.getSizeInBits() == 64;
1130 // Form a REG_SEQUENCE to force register allocation.
1131 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1134 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1135 WidenVector(*CurDAG));
1137 SDValue RegSeq = createQTuple(Regs);
1139 std::vector<EVT> ResTys;
1140 ResTys.push_back(MVT::Untyped);
1141 ResTys.push_back(MVT::Other);
1144 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1146 SmallVector<SDValue, 6> Ops;
1147 Ops.push_back(RegSeq);
1148 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1149 Ops.push_back(N->getOperand(NumVecs + 3));
1150 Ops.push_back(N->getOperand(0));
1151 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1152 SDValue SuperReg = SDValue(Ld, 0);
1154 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1155 static unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1, AArch64::qsub2,
1157 for (unsigned i = 0; i < NumVecs; ++i) {
1158 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1160 NV = NarrowVector(NV, *CurDAG);
1161 ReplaceUses(SDValue(N, i), NV);
1164 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1169 SDNode *AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
1172 EVT VT = N->getValueType(0);
1173 bool Narrow = VT.getSizeInBits() == 64;
1175 // Form a REG_SEQUENCE to force register allocation.
1176 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1179 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1180 WidenVector(*CurDAG));
1182 SDValue RegSeq = createQTuple(Regs);
1184 std::vector<EVT> ResTys;
1185 ResTys.push_back(MVT::i64); // Type of the write back register
1186 ResTys.push_back(MVT::Untyped);
1187 ResTys.push_back(MVT::Other);
1190 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1192 SmallVector<SDValue, 6> Ops;
1193 Ops.push_back(RegSeq);
1194 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64)); // Lane Number
1195 Ops.push_back(N->getOperand(NumVecs + 2)); // Base register
1196 Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
1197 Ops.push_back(N->getOperand(0));
1198 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1200 // Update uses of the write back register
1201 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1203 // Update uses of the vector list
1204 SDValue SuperReg = SDValue(Ld, 1);
1206 ReplaceUses(SDValue(N, 0),
1207 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg);
1209 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1210 static unsigned QSubs[] = { AArch64::qsub0, AArch64::qsub1, AArch64::qsub2,
1212 for (unsigned i = 0; i < NumVecs; ++i) {
1213 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT,
1216 NV = NarrowVector(NV, *CurDAG);
1217 ReplaceUses(SDValue(N, i), NV);
1222 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1227 SDNode *AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
1230 EVT VT = N->getOperand(2)->getValueType(0);
1231 bool Narrow = VT.getSizeInBits() == 64;
1233 // Form a REG_SEQUENCE to force register allocation.
1234 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1237 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1238 WidenVector(*CurDAG));
1240 SDValue RegSeq = createQTuple(Regs);
1243 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1245 SmallVector<SDValue, 6> Ops;
1246 Ops.push_back(RegSeq);
1247 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1248 Ops.push_back(N->getOperand(NumVecs + 3));
1249 Ops.push_back(N->getOperand(0));
1250 SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
1252 // Transfer memoperands.
1253 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1254 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1255 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1260 SDNode *AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
1263 EVT VT = N->getOperand(2)->getValueType(0);
1264 bool Narrow = VT.getSizeInBits() == 64;
1266 // Form a REG_SEQUENCE to force register allocation.
1267 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1270 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1271 WidenVector(*CurDAG));
1273 SDValue RegSeq = createQTuple(Regs);
1275 SmallVector<EVT, 2> ResTys;
1276 ResTys.push_back(MVT::i64); // Type of the write back register
1277 ResTys.push_back(MVT::Other);
1280 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1282 SmallVector<SDValue, 6> Ops;
1283 Ops.push_back(RegSeq);
1284 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1285 Ops.push_back(N->getOperand(NumVecs + 2)); // Base Register
1286 Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
1287 Ops.push_back(N->getOperand(0));
1288 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1290 // Transfer memoperands.
1291 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1292 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1293 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1298 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
1299 unsigned &Opc, SDValue &Opd0,
1300 unsigned &LSB, unsigned &MSB,
1301 unsigned NumberOfIgnoredLowBits,
1302 bool BiggerPattern) {
1303 assert(N->getOpcode() == ISD::AND &&
1304 "N must be a AND operation to call this function");
1306 EVT VT = N->getValueType(0);
1308 // Here we can test the type of VT and return false when the type does not
1309 // match, but since it is done prior to that call in the current context
1310 // we turned that into an assert to avoid redundant code.
1311 assert((VT == MVT::i32 || VT == MVT::i64) &&
1312 "Type checking must have been done before calling this function");
1314 // FIXME: simplify-demanded-bits in DAGCombine will probably have
1315 // changed the AND node to a 32-bit mask operation. We'll have to
1316 // undo that as part of the transform here if we want to catch all
1317 // the opportunities.
1318 // Currently the NumberOfIgnoredLowBits argument helps to recover
1319 // form these situations when matching bigger pattern (bitfield insert).
1321 // For unsigned extracts, check for a shift right and mask
1322 uint64_t And_imm = 0;
1323 if (!isOpcWithIntImmediate(N, ISD::AND, And_imm))
1326 const SDNode *Op0 = N->getOperand(0).getNode();
1328 // Because of simplify-demanded-bits in DAGCombine, the mask may have been
1329 // simplified. Try to undo that
1330 And_imm |= (1 << NumberOfIgnoredLowBits) - 1;
1332 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1333 if (And_imm & (And_imm + 1))
1336 bool ClampMSB = false;
1337 uint64_t Srl_imm = 0;
1338 // Handle the SRL + ANY_EXTEND case.
1339 if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
1340 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, Srl_imm)) {
1341 // Extend the incoming operand of the SRL to 64-bit.
1342 Opd0 = Widen(CurDAG, Op0->getOperand(0).getOperand(0));
1343 // Make sure to clamp the MSB so that we preserve the semantics of the
1344 // original operations.
1346 } else if (VT == MVT::i32 && Op0->getOpcode() == ISD::TRUNCATE &&
1347 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL,
1349 // If the shift result was truncated, we can still combine them.
1350 Opd0 = Op0->getOperand(0).getOperand(0);
1352 // Use the type of SRL node.
1353 VT = Opd0->getValueType(0);
1354 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, Srl_imm)) {
1355 Opd0 = Op0->getOperand(0);
1356 } else if (BiggerPattern) {
1357 // Let's pretend a 0 shift right has been performed.
1358 // The resulting code will be at least as good as the original one
1359 // plus it may expose more opportunities for bitfield insert pattern.
1360 // FIXME: Currently we limit this to the bigger pattern, because
1361 // some optimizations expect AND and not UBFM
1362 Opd0 = N->getOperand(0);
1366 assert((BiggerPattern || (Srl_imm > 0 && Srl_imm < VT.getSizeInBits())) &&
1367 "bad amount in shift node!");
1370 MSB = Srl_imm + (VT == MVT::i32 ? CountTrailingOnes_32(And_imm)
1371 : CountTrailingOnes_64(And_imm)) -
1374 // Since we're moving the extend before the right shift operation, we need
1375 // to clamp the MSB to make sure we don't shift in undefined bits instead of
1376 // the zeros which would get shifted in with the original right shift
1378 MSB = MSB > 31 ? 31 : MSB;
1380 Opc = VT == MVT::i32 ? AArch64::UBFMWri : AArch64::UBFMXri;
1384 static bool isSeveralBitsExtractOpFromShr(SDNode *N, unsigned &Opc,
1385 SDValue &Opd0, unsigned &LSB,
1387 // We are looking for the following pattern which basically extracts several
1388 // continuous bits from the source value and places it from the LSB of the
1389 // destination value, all other bits of the destination value or set to zero:
1391 // Value2 = AND Value, MaskImm
1392 // SRL Value2, ShiftImm
1394 // with MaskImm >> ShiftImm to search for the bit width.
1396 // This gets selected into a single UBFM:
1398 // UBFM Value, ShiftImm, BitWide + Srl_imm -1
1401 if (N->getOpcode() != ISD::SRL)
1404 uint64_t And_mask = 0;
1405 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_mask))
1408 Opd0 = N->getOperand(0).getOperand(0);
1410 uint64_t Srl_imm = 0;
1411 if (!isIntImmediate(N->getOperand(1), Srl_imm))
1414 // Check whether we really have several bits extract here.
1415 unsigned BitWide = 64 - CountLeadingOnes_64(~(And_mask >> Srl_imm));
1416 if (BitWide && isMask_64(And_mask >> Srl_imm)) {
1417 if (N->getValueType(0) == MVT::i32)
1418 Opc = AArch64::UBFMWri;
1420 Opc = AArch64::UBFMXri;
1423 MSB = BitWide + Srl_imm - 1;
1430 static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1431 unsigned &LSB, unsigned &MSB,
1432 bool BiggerPattern) {
1433 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1434 "N must be a SHR/SRA operation to call this function");
1436 EVT VT = N->getValueType(0);
1438 // Here we can test the type of VT and return false when the type does not
1439 // match, but since it is done prior to that call in the current context
1440 // we turned that into an assert to avoid redundant code.
1441 assert((VT == MVT::i32 || VT == MVT::i64) &&
1442 "Type checking must have been done before calling this function");
1444 // Check for AND + SRL doing several bits extract.
1445 if (isSeveralBitsExtractOpFromShr(N, Opc, Opd0, LSB, MSB))
1448 // we're looking for a shift of a shift
1449 uint64_t Shl_imm = 0;
1450 uint64_t Trunc_bits = 0;
1451 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1452 Opd0 = N->getOperand(0).getOperand(0);
1453 } else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL &&
1454 N->getOperand(0).getNode()->getOpcode() == ISD::TRUNCATE) {
1455 // We are looking for a shift of truncate. Truncate from i64 to i32 could
1456 // be considered as setting high 32 bits as zero. Our strategy here is to
1457 // always generate 64bit UBFM. This consistency will help the CSE pass
1458 // later find more redundancy.
1459 Opd0 = N->getOperand(0).getOperand(0);
1460 Trunc_bits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits();
1461 VT = Opd0->getValueType(0);
1462 assert(VT == MVT::i64 && "the promoted type should be i64");
1463 } else if (BiggerPattern) {
1464 // Let's pretend a 0 shift left has been performed.
1465 // FIXME: Currently we limit this to the bigger pattern case,
1466 // because some optimizations expect AND and not UBFM
1467 Opd0 = N->getOperand(0);
1471 assert(Shl_imm < VT.getSizeInBits() && "bad amount in shift node!");
1472 uint64_t Srl_imm = 0;
1473 if (!isIntImmediate(N->getOperand(1), Srl_imm))
1476 assert(Srl_imm > 0 && Srl_imm < VT.getSizeInBits() &&
1477 "bad amount in shift node!");
1478 // Note: The width operand is encoded as width-1.
1479 unsigned Width = VT.getSizeInBits() - Trunc_bits - Srl_imm - 1;
1480 int sLSB = Srl_imm - Shl_imm;
1485 // SRA requires a signed extraction
1487 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
1489 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
1493 static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
1494 SDValue &Opd0, unsigned &LSB, unsigned &MSB,
1495 unsigned NumberOfIgnoredLowBits = 0,
1496 bool BiggerPattern = false) {
1497 if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
1500 switch (N->getOpcode()) {
1502 if (!N->isMachineOpcode())
1506 return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, LSB, MSB,
1507 NumberOfIgnoredLowBits, BiggerPattern);
1510 return isBitfieldExtractOpFromShr(N, Opc, Opd0, LSB, MSB, BiggerPattern);
1513 unsigned NOpc = N->getMachineOpcode();
1517 case AArch64::SBFMWri:
1518 case AArch64::UBFMWri:
1519 case AArch64::SBFMXri:
1520 case AArch64::UBFMXri:
1522 Opd0 = N->getOperand(0);
1523 LSB = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
1524 MSB = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
1531 SDNode *AArch64DAGToDAGISel::SelectBitfieldExtractOp(SDNode *N) {
1532 unsigned Opc, LSB, MSB;
1534 if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, LSB, MSB))
1537 EVT VT = N->getValueType(0);
1539 // If the bit extract operation is 64bit but the original type is 32bit, we
1540 // need to add one EXTRACT_SUBREG.
1541 if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32) {
1542 SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(LSB, MVT::i64),
1543 CurDAG->getTargetConstant(MSB, MVT::i64)};
1545 SDNode *BFM = CurDAG->getMachineNode(Opc, SDLoc(N), MVT::i64, Ops64);
1546 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32);
1547 MachineSDNode *Node =
1548 CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDLoc(N), MVT::i32,
1549 SDValue(BFM, 0), SubReg);
1553 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(LSB, VT),
1554 CurDAG->getTargetConstant(MSB, VT)};
1555 return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
1558 /// Does DstMask form a complementary pair with the mask provided by
1559 /// BitsToBeInserted, suitable for use in a BFI instruction. Roughly speaking,
1560 /// this asks whether DstMask zeroes precisely those bits that will be set by
1562 static bool isBitfieldDstMask(uint64_t DstMask, APInt BitsToBeInserted,
1563 unsigned NumberOfIgnoredHighBits, EVT VT) {
1564 assert((VT == MVT::i32 || VT == MVT::i64) &&
1565 "i32 or i64 mask type expected!");
1566 unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;
1568 APInt SignificantDstMask = APInt(BitWidth, DstMask);
1569 APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);
1571 return (SignificantDstMask & SignificantBitsToBeInserted) == 0 &&
1572 (SignificantDstMask | SignificantBitsToBeInserted).isAllOnesValue();
1575 // Look for bits that will be useful for later uses.
1576 // A bit is consider useless as soon as it is dropped and never used
1577 // before it as been dropped.
1578 // E.g., looking for useful bit of x
1581 // After #1, x useful bits are 0x7, then the useful bits of x, live through
1583 // After #2, the useful bits of x are 0x4.
1584 // However, if x is used on an unpredicatable instruction, then all its bits
1590 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);
1592 static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
1595 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1596 Imm = AArch64_AM::decodeLogicalImmediate(Imm, UsefulBits.getBitWidth());
1597 UsefulBits &= APInt(UsefulBits.getBitWidth(), Imm);
1598 getUsefulBits(Op, UsefulBits, Depth + 1);
1601 static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
1602 uint64_t Imm, uint64_t MSB,
1604 // inherit the bitwidth value
1605 APInt OpUsefulBits(UsefulBits);
1609 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
1611 // The interesting part will be in the lower part of the result
1612 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1613 // The interesting part was starting at Imm in the argument
1614 OpUsefulBits = OpUsefulBits.shl(Imm);
1616 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
1618 // The interesting part will be shifted in the result
1619 OpUsefulBits = OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm);
1620 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1621 // The interesting part was at zero in the argument
1622 OpUsefulBits = OpUsefulBits.lshr(OpUsefulBits.getBitWidth() - Imm);
1625 UsefulBits &= OpUsefulBits;
1628 static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
1631 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1633 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1635 getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1638 static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
1640 uint64_t ShiftTypeAndValue =
1641 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1642 APInt Mask(UsefulBits);
1643 Mask.clearAllBits();
1646 if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
1648 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
1649 Mask = Mask.shl(ShiftAmt);
1650 getUsefulBits(Op, Mask, Depth + 1);
1651 Mask = Mask.lshr(ShiftAmt);
1652 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
1654 // We do not handle AArch64_AM::ASR, because the sign will change the
1655 // number of useful bits
1656 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
1657 Mask = Mask.lshr(ShiftAmt);
1658 getUsefulBits(Op, Mask, Depth + 1);
1659 Mask = Mask.shl(ShiftAmt);
1666 static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
1669 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1671 cast<const ConstantSDNode>(Op.getOperand(3).getNode())->getZExtValue();
1673 if (Op.getOperand(1) == Orig)
1674 return getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1676 APInt OpUsefulBits(UsefulBits);
1680 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
1682 UsefulBits &= ~OpUsefulBits;
1683 getUsefulBits(Op, UsefulBits, Depth + 1);
1685 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
1687 UsefulBits = ~(OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm));
1688 getUsefulBits(Op, UsefulBits, Depth + 1);
1692 static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
1693 SDValue Orig, unsigned Depth) {
1695 // Users of this node should have already been instruction selected
1696 // FIXME: Can we turn that into an assert?
1697 if (!UserNode->isMachineOpcode())
1700 switch (UserNode->getMachineOpcode()) {
1703 case AArch64::ANDSWri:
1704 case AArch64::ANDSXri:
1705 case AArch64::ANDWri:
1706 case AArch64::ANDXri:
1707 // We increment Depth only when we call the getUsefulBits
1708 return getUsefulBitsFromAndWithImmediate(SDValue(UserNode, 0), UsefulBits,
1710 case AArch64::UBFMWri:
1711 case AArch64::UBFMXri:
1712 return getUsefulBitsFromUBFM(SDValue(UserNode, 0), UsefulBits, Depth);
1714 case AArch64::ORRWrs:
1715 case AArch64::ORRXrs:
1716 if (UserNode->getOperand(1) != Orig)
1718 return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
1720 case AArch64::BFMWri:
1721 case AArch64::BFMXri:
1722 return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
1726 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
1729 // Initialize UsefulBits
1731 unsigned Bitwidth = Op.getValueType().getScalarType().getSizeInBits();
1732 // At the beginning, assume every produced bits is useful
1733 UsefulBits = APInt(Bitwidth, 0);
1734 UsefulBits.flipAllBits();
1736 APInt UsersUsefulBits(UsefulBits.getBitWidth(), 0);
1738 for (SDNode *Node : Op.getNode()->uses()) {
1739 // A use cannot produce useful bits
1740 APInt UsefulBitsForUse = APInt(UsefulBits);
1741 getUsefulBitsForUse(Node, UsefulBitsForUse, Op, Depth);
1742 UsersUsefulBits |= UsefulBitsForUse;
1744 // UsefulBits contains the produced bits that are meaningful for the
1745 // current definition, thus a user cannot make a bit meaningful at
1747 UsefulBits &= UsersUsefulBits;
1750 /// Create a machine node performing a notional SHL of Op by ShlAmount. If
1751 /// ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is
1752 /// 0, return Op unchanged.
1753 static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
1757 EVT VT = Op.getValueType();
1758 unsigned BitWidth = VT.getSizeInBits();
1759 unsigned UBFMOpc = BitWidth == 32 ? AArch64::UBFMWri : AArch64::UBFMXri;
1762 if (ShlAmount > 0) {
1763 // LSL wD, wN, #Amt == UBFM wD, wN, #32-Amt, #31-Amt
1764 ShiftNode = CurDAG->getMachineNode(
1765 UBFMOpc, SDLoc(Op), VT, Op,
1766 CurDAG->getTargetConstant(BitWidth - ShlAmount, VT),
1767 CurDAG->getTargetConstant(BitWidth - 1 - ShlAmount, VT));
1769 // LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1
1770 assert(ShlAmount < 0 && "expected right shift");
1771 int ShrAmount = -ShlAmount;
1772 ShiftNode = CurDAG->getMachineNode(
1773 UBFMOpc, SDLoc(Op), VT, Op, CurDAG->getTargetConstant(ShrAmount, VT),
1774 CurDAG->getTargetConstant(BitWidth - 1, VT));
1777 return SDValue(ShiftNode, 0);
1780 /// Does this tree qualify as an attempt to move a bitfield into position,
1781 /// essentially "(and (shl VAL, N), Mask)".
1782 static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
1783 SDValue &Src, int &ShiftAmount,
1785 EVT VT = Op.getValueType();
1786 unsigned BitWidth = VT.getSizeInBits();
1788 assert(BitWidth == 32 || BitWidth == 64);
1790 APInt KnownZero, KnownOne;
1791 CurDAG->computeKnownBits(Op, KnownZero, KnownOne);
1793 // Non-zero in the sense that they're not provably zero, which is the key
1794 // point if we want to use this value
1795 uint64_t NonZeroBits = (~KnownZero).getZExtValue();
1797 // Discard a constant AND mask if present. It's safe because the node will
1798 // already have been factored into the computeKnownBits calculation above.
1800 if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
1801 assert((~APInt(BitWidth, AndImm) & ~KnownZero) == 0);
1802 Op = Op.getOperand(0);
1806 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SHL, ShlImm))
1808 Op = Op.getOperand(0);
1810 if (!isShiftedMask_64(NonZeroBits))
1813 ShiftAmount = countTrailingZeros(NonZeroBits);
1814 MaskWidth = CountTrailingOnes_64(NonZeroBits >> ShiftAmount);
1816 // BFI encompasses sufficiently many nodes that it's worth inserting an extra
1817 // LSL/LSR if the mask in NonZeroBits doesn't quite match up with the ISD::SHL
1819 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
1824 // Given a OR operation, check if we have the following pattern
1825 // ubfm c, b, imm, imm2 (or something that does the same jobs, see
1826 // isBitfieldExtractOp)
1827 // d = e & mask2 ; where mask is a binary sequence of 1..10..0 and
1828 // countTrailingZeros(mask2) == imm2 - imm + 1
1830 // if yes, given reference arguments will be update so that one can replace
1831 // the OR instruction with:
1832 // f = Opc Opd0, Opd1, LSB, MSB ; where Opc is a BFM, LSB = imm, and MSB = imm2
1833 static bool isBitfieldInsertOpFromOr(SDNode *N, unsigned &Opc, SDValue &Dst,
1834 SDValue &Src, unsigned &ImmR,
1835 unsigned &ImmS, SelectionDAG *CurDAG) {
1836 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
1839 EVT VT = N->getValueType(0);
1841 Opc = AArch64::BFMWri;
1842 else if (VT == MVT::i64)
1843 Opc = AArch64::BFMXri;
1847 // Because of simplify-demanded-bits in DAGCombine, involved masks may not
1848 // have the expected shape. Try to undo that.
1850 getUsefulBits(SDValue(N, 0), UsefulBits);
1852 unsigned NumberOfIgnoredLowBits = UsefulBits.countTrailingZeros();
1853 unsigned NumberOfIgnoredHighBits = UsefulBits.countLeadingZeros();
1855 // OR is commutative, check both possibilities (does llvm provide a
1856 // way to do that directely, e.g., via code matcher?)
1857 SDValue OrOpd1Val = N->getOperand(1);
1858 SDNode *OrOpd0 = N->getOperand(0).getNode();
1859 SDNode *OrOpd1 = N->getOperand(1).getNode();
1860 for (int i = 0; i < 2;
1861 ++i, std::swap(OrOpd0, OrOpd1), OrOpd1Val = N->getOperand(0)) {
1864 if (isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Src, ImmR, ImmS,
1865 NumberOfIgnoredLowBits, true)) {
1866 // Check that the returned opcode is compatible with the pattern,
1867 // i.e., same type and zero extended (U and not S)
1868 if ((BFXOpc != AArch64::UBFMXri && VT == MVT::i64) ||
1869 (BFXOpc != AArch64::UBFMWri && VT == MVT::i32))
1872 // Compute the width of the bitfield insertion
1874 Width = ImmS - ImmR + 1;
1875 // FIXME: This constraint is to catch bitfield insertion we may
1876 // want to widen the pattern if we want to grab general bitfied
1881 // If the mask on the insertee is correct, we have a BFXIL operation. We
1882 // can share the ImmR and ImmS values from the already-computed UBFM.
1883 } else if (isBitfieldPositioningOp(CurDAG, SDValue(OrOpd0, 0), Src,
1885 ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits();
1890 // Check the second part of the pattern
1891 EVT VT = OrOpd1->getValueType(0);
1892 assert((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand");
1894 // Compute the Known Zero for the candidate of the first operand.
1895 // This allows to catch more general case than just looking for
1896 // AND with imm. Indeed, simplify-demanded-bits may have removed
1897 // the AND instruction because it proves it was useless.
1898 APInt KnownZero, KnownOne;
1899 CurDAG->computeKnownBits(OrOpd1Val, KnownZero, KnownOne);
1901 // Check if there is enough room for the second operand to appear
1903 APInt BitsToBeInserted =
1904 APInt::getBitsSet(KnownZero.getBitWidth(), DstLSB, DstLSB + Width);
1906 if ((BitsToBeInserted & ~KnownZero) != 0)
1909 // Set the first operand
1911 if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
1912 isBitfieldDstMask(Imm, BitsToBeInserted, NumberOfIgnoredHighBits, VT))
1913 // In that case, we can eliminate the AND
1914 Dst = OrOpd1->getOperand(0);
1916 // Maybe the AND has been removed by simplify-demanded-bits
1917 // or is useful because it discards more bits
1927 SDNode *AArch64DAGToDAGISel::SelectBitfieldInsertOp(SDNode *N) {
1928 if (N->getOpcode() != ISD::OR)
1935 if (!isBitfieldInsertOpFromOr(N, Opc, Opd0, Opd1, LSB, MSB, CurDAG))
1938 EVT VT = N->getValueType(0);
1939 SDValue Ops[] = { Opd0,
1941 CurDAG->getTargetConstant(LSB, VT),
1942 CurDAG->getTargetConstant(MSB, VT) };
1943 return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
1946 SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) {
1947 EVT VT = N->getValueType(0);
1950 unsigned FRINTXOpcs[] = { AArch64::FRINTXSr, AArch64::FRINTXDr };
1952 if (VT == MVT::f32) {
1954 } else if (VT == MVT::f64) {
1957 return nullptr; // Unrecognized argument type. Fall back on default codegen.
1959 // Pick the FRINTX variant needed to set the flags.
1960 unsigned FRINTXOpc = FRINTXOpcs[Variant];
1962 switch (N->getOpcode()) {
1964 return nullptr; // Unrecognized libm ISD node. Fall back on default codegen.
1966 unsigned FRINTPOpcs[] = { AArch64::FRINTPSr, AArch64::FRINTPDr };
1967 Opc = FRINTPOpcs[Variant];
1971 unsigned FRINTMOpcs[] = { AArch64::FRINTMSr, AArch64::FRINTMDr };
1972 Opc = FRINTMOpcs[Variant];
1976 unsigned FRINTZOpcs[] = { AArch64::FRINTZSr, AArch64::FRINTZDr };
1977 Opc = FRINTZOpcs[Variant];
1981 unsigned FRINTAOpcs[] = { AArch64::FRINTASr, AArch64::FRINTADr };
1982 Opc = FRINTAOpcs[Variant];
1988 SDValue In = N->getOperand(0);
1989 SmallVector<SDValue, 2> Ops;
1992 if (!TM.Options.UnsafeFPMath) {
1993 SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In);
1994 Ops.push_back(SDValue(FRINTX, 1));
1997 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2001 AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
2002 unsigned RegWidth) {
2004 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
2005 FVal = CN->getValueAPF();
2006 else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
2007 // Some otherwise illegal constants are allowed in this case.
2008 if (LN->getOperand(1).getOpcode() != AArch64ISD::ADDlow ||
2009 !isa<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1)))
2012 ConstantPoolSDNode *CN =
2013 dyn_cast<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1));
2014 FVal = cast<ConstantFP>(CN->getConstVal())->getValueAPF();
2018 // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
2019 // is between 1 and 32 for a destination w-register, or 1 and 64 for an
2022 // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
2023 // want THIS_NODE to be 2^fbits. This is much easier to deal with using
2027 // fbits is between 1 and 64 in the worst-case, which means the fmul
2028 // could have 2^64 as an actual operand. Need 65 bits of precision.
2029 APSInt IntVal(65, true);
2030 FVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact);
2032 // N.b. isPowerOf2 also checks for > 0.
2033 if (!IsExact || !IntVal.isPowerOf2()) return false;
2034 unsigned FBits = IntVal.logBase2();
2036 // Checks above should have guaranteed that we haven't lost information in
2037 // finding FBits, but it must still be in range.
2038 if (FBits == 0 || FBits > RegWidth) return false;
2040 FixedPos = CurDAG->getTargetConstant(FBits, MVT::i32);
2044 SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
2045 // Dump information about the Node being selected
2046 DEBUG(errs() << "Selecting: ");
2047 DEBUG(Node->dump(CurDAG));
2048 DEBUG(errs() << "\n");
2050 // If we have a custom node, we already have selected!
2051 if (Node->isMachineOpcode()) {
2052 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
2053 Node->setNodeId(-1);
2057 // Few custom selection stuff.
2058 SDNode *ResNode = nullptr;
2059 EVT VT = Node->getValueType(0);
2061 switch (Node->getOpcode()) {
2066 if (SDNode *I = SelectMLAV64LaneV128(Node))
2071 // Try to select as an indexed load. Fall through to normal processing
2074 SDNode *I = SelectIndexedLoad(Node, Done);
2083 if (SDNode *I = SelectBitfieldExtractOp(Node))
2088 if (SDNode *I = SelectBitfieldInsertOp(Node))
2092 case ISD::EXTRACT_VECTOR_ELT: {
2093 // Extracting lane zero is a special case where we can just use a plain
2094 // EXTRACT_SUBREG instruction, which will become FMOV. This is easier for
2095 // the rest of the compiler, especially the register allocator and copyi
2096 // propagation, to reason about, so is preferred when it's possible to
2098 ConstantSDNode *LaneNode = cast<ConstantSDNode>(Node->getOperand(1));
2099 // Bail and use the default Select() for non-zero lanes.
2100 if (LaneNode->getZExtValue() != 0)
2102 // If the element type is not the same as the result type, likewise
2103 // bail and use the default Select(), as there's more to do than just
2104 // a cross-class COPY. This catches extracts of i8 and i16 elements
2105 // since they will need an explicit zext.
2106 if (VT != Node->getOperand(0).getValueType().getVectorElementType())
2109 switch (Node->getOperand(0)
2111 .getVectorElementType()
2114 llvm_unreachable("Unexpected vector element type!");
2116 SubReg = AArch64::dsub;
2119 SubReg = AArch64::ssub;
2122 SubReg = AArch64::hsub;
2125 llvm_unreachable("unexpected zext-requiring extract element!");
2127 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT,
2128 Node->getOperand(0));
2129 DEBUG(dbgs() << "ISEL: Custom selection!\n=> ");
2130 DEBUG(Extract->dumpr(CurDAG));
2131 DEBUG(dbgs() << "\n");
2132 return Extract.getNode();
2134 case ISD::Constant: {
2135 // Materialize zero constants as copies from WZR/XZR. This allows
2136 // the coalescer to propagate these into other instructions.
2137 ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
2138 if (ConstNode->isNullValue()) {
2140 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
2141 AArch64::WZR, MVT::i32).getNode();
2142 else if (VT == MVT::i64)
2143 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
2144 AArch64::XZR, MVT::i64).getNode();
2149 case ISD::FrameIndex: {
2150 // Selects to ADDXri FI, 0 which in turn will become ADDXri SP, imm.
2151 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
2152 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
2153 const TargetLowering *TLI = getTargetLowering();
2154 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
2155 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2156 CurDAG->getTargetConstant(Shifter, MVT::i32) };
2157 return CurDAG->SelectNodeTo(Node, AArch64::ADDXri, MVT::i64, Ops);
2159 case ISD::INTRINSIC_W_CHAIN: {
2160 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2164 case Intrinsic::aarch64_ldaxp:
2165 case Intrinsic::aarch64_ldxp: {
2167 IntNo == Intrinsic::aarch64_ldaxp ? AArch64::LDAXPX : AArch64::LDXPX;
2168 SDValue MemAddr = Node->getOperand(2);
2170 SDValue Chain = Node->getOperand(0);
2172 SDNode *Ld = CurDAG->getMachineNode(Op, DL, MVT::i64, MVT::i64,
2173 MVT::Other, MemAddr, Chain);
2175 // Transfer memoperands.
2176 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2177 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2178 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2181 case Intrinsic::aarch64_stlxp:
2182 case Intrinsic::aarch64_stxp: {
2184 IntNo == Intrinsic::aarch64_stlxp ? AArch64::STLXPX : AArch64::STXPX;
2186 SDValue Chain = Node->getOperand(0);
2187 SDValue ValLo = Node->getOperand(2);
2188 SDValue ValHi = Node->getOperand(3);
2189 SDValue MemAddr = Node->getOperand(4);
2191 // Place arguments in the right order.
2192 SmallVector<SDValue, 7> Ops;
2193 Ops.push_back(ValLo);
2194 Ops.push_back(ValHi);
2195 Ops.push_back(MemAddr);
2196 Ops.push_back(Chain);
2198 SDNode *St = CurDAG->getMachineNode(Op, DL, MVT::i32, MVT::Other, Ops);
2199 // Transfer memoperands.
2200 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2201 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2202 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
2206 case Intrinsic::aarch64_neon_ld1x2:
2207 if (VT == MVT::v8i8)
2208 return SelectLoad(Node, 2, AArch64::LD1Twov8b, AArch64::dsub0);
2209 else if (VT == MVT::v16i8)
2210 return SelectLoad(Node, 2, AArch64::LD1Twov16b, AArch64::qsub0);
2211 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2212 return SelectLoad(Node, 2, AArch64::LD1Twov4h, AArch64::dsub0);
2213 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2214 return SelectLoad(Node, 2, AArch64::LD1Twov8h, AArch64::qsub0);
2215 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2216 return SelectLoad(Node, 2, AArch64::LD1Twov2s, AArch64::dsub0);
2217 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2218 return SelectLoad(Node, 2, AArch64::LD1Twov4s, AArch64::qsub0);
2219 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2220 return SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
2221 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2222 return SelectLoad(Node, 2, AArch64::LD1Twov2d, AArch64::qsub0);
2224 case Intrinsic::aarch64_neon_ld1x3:
2225 if (VT == MVT::v8i8)
2226 return SelectLoad(Node, 3, AArch64::LD1Threev8b, AArch64::dsub0);
2227 else if (VT == MVT::v16i8)
2228 return SelectLoad(Node, 3, AArch64::LD1Threev16b, AArch64::qsub0);
2229 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2230 return SelectLoad(Node, 3, AArch64::LD1Threev4h, AArch64::dsub0);
2231 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2232 return SelectLoad(Node, 3, AArch64::LD1Threev8h, AArch64::qsub0);
2233 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2234 return SelectLoad(Node, 3, AArch64::LD1Threev2s, AArch64::dsub0);
2235 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2236 return SelectLoad(Node, 3, AArch64::LD1Threev4s, AArch64::qsub0);
2237 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2238 return SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
2239 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2240 return SelectLoad(Node, 3, AArch64::LD1Threev2d, AArch64::qsub0);
2242 case Intrinsic::aarch64_neon_ld1x4:
2243 if (VT == MVT::v8i8)
2244 return SelectLoad(Node, 4, AArch64::LD1Fourv8b, AArch64::dsub0);
2245 else if (VT == MVT::v16i8)
2246 return SelectLoad(Node, 4, AArch64::LD1Fourv16b, AArch64::qsub0);
2247 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2248 return SelectLoad(Node, 4, AArch64::LD1Fourv4h, AArch64::dsub0);
2249 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2250 return SelectLoad(Node, 4, AArch64::LD1Fourv8h, AArch64::qsub0);
2251 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2252 return SelectLoad(Node, 4, AArch64::LD1Fourv2s, AArch64::dsub0);
2253 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2254 return SelectLoad(Node, 4, AArch64::LD1Fourv4s, AArch64::qsub0);
2255 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2256 return SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
2257 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2258 return SelectLoad(Node, 4, AArch64::LD1Fourv2d, AArch64::qsub0);
2260 case Intrinsic::aarch64_neon_ld2:
2261 if (VT == MVT::v8i8)
2262 return SelectLoad(Node, 2, AArch64::LD2Twov8b, AArch64::dsub0);
2263 else if (VT == MVT::v16i8)
2264 return SelectLoad(Node, 2, AArch64::LD2Twov16b, AArch64::qsub0);
2265 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2266 return SelectLoad(Node, 2, AArch64::LD2Twov4h, AArch64::dsub0);
2267 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2268 return SelectLoad(Node, 2, AArch64::LD2Twov8h, AArch64::qsub0);
2269 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2270 return SelectLoad(Node, 2, AArch64::LD2Twov2s, AArch64::dsub0);
2271 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2272 return SelectLoad(Node, 2, AArch64::LD2Twov4s, AArch64::qsub0);
2273 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2274 return SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
2275 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2276 return SelectLoad(Node, 2, AArch64::LD2Twov2d, AArch64::qsub0);
2278 case Intrinsic::aarch64_neon_ld3:
2279 if (VT == MVT::v8i8)
2280 return SelectLoad(Node, 3, AArch64::LD3Threev8b, AArch64::dsub0);
2281 else if (VT == MVT::v16i8)
2282 return SelectLoad(Node, 3, AArch64::LD3Threev16b, AArch64::qsub0);
2283 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2284 return SelectLoad(Node, 3, AArch64::LD3Threev4h, AArch64::dsub0);
2285 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2286 return SelectLoad(Node, 3, AArch64::LD3Threev8h, AArch64::qsub0);
2287 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2288 return SelectLoad(Node, 3, AArch64::LD3Threev2s, AArch64::dsub0);
2289 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2290 return SelectLoad(Node, 3, AArch64::LD3Threev4s, AArch64::qsub0);
2291 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2292 return SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
2293 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2294 return SelectLoad(Node, 3, AArch64::LD3Threev2d, AArch64::qsub0);
2296 case Intrinsic::aarch64_neon_ld4:
2297 if (VT == MVT::v8i8)
2298 return SelectLoad(Node, 4, AArch64::LD4Fourv8b, AArch64::dsub0);
2299 else if (VT == MVT::v16i8)
2300 return SelectLoad(Node, 4, AArch64::LD4Fourv16b, AArch64::qsub0);
2301 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2302 return SelectLoad(Node, 4, AArch64::LD4Fourv4h, AArch64::dsub0);
2303 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2304 return SelectLoad(Node, 4, AArch64::LD4Fourv8h, AArch64::qsub0);
2305 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2306 return SelectLoad(Node, 4, AArch64::LD4Fourv2s, AArch64::dsub0);
2307 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2308 return SelectLoad(Node, 4, AArch64::LD4Fourv4s, AArch64::qsub0);
2309 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2310 return SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
2311 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2312 return SelectLoad(Node, 4, AArch64::LD4Fourv2d, AArch64::qsub0);
2314 case Intrinsic::aarch64_neon_ld2r:
2315 if (VT == MVT::v8i8)
2316 return SelectLoad(Node, 2, AArch64::LD2Rv8b, AArch64::dsub0);
2317 else if (VT == MVT::v16i8)
2318 return SelectLoad(Node, 2, AArch64::LD2Rv16b, AArch64::qsub0);
2319 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2320 return SelectLoad(Node, 2, AArch64::LD2Rv4h, AArch64::dsub0);
2321 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2322 return SelectLoad(Node, 2, AArch64::LD2Rv8h, AArch64::qsub0);
2323 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2324 return SelectLoad(Node, 2, AArch64::LD2Rv2s, AArch64::dsub0);
2325 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2326 return SelectLoad(Node, 2, AArch64::LD2Rv4s, AArch64::qsub0);
2327 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2328 return SelectLoad(Node, 2, AArch64::LD2Rv1d, AArch64::dsub0);
2329 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2330 return SelectLoad(Node, 2, AArch64::LD2Rv2d, AArch64::qsub0);
2332 case Intrinsic::aarch64_neon_ld3r:
2333 if (VT == MVT::v8i8)
2334 return SelectLoad(Node, 3, AArch64::LD3Rv8b, AArch64::dsub0);
2335 else if (VT == MVT::v16i8)
2336 return SelectLoad(Node, 3, AArch64::LD3Rv16b, AArch64::qsub0);
2337 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2338 return SelectLoad(Node, 3, AArch64::LD3Rv4h, AArch64::dsub0);
2339 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2340 return SelectLoad(Node, 3, AArch64::LD3Rv8h, AArch64::qsub0);
2341 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2342 return SelectLoad(Node, 3, AArch64::LD3Rv2s, AArch64::dsub0);
2343 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2344 return SelectLoad(Node, 3, AArch64::LD3Rv4s, AArch64::qsub0);
2345 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2346 return SelectLoad(Node, 3, AArch64::LD3Rv1d, AArch64::dsub0);
2347 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2348 return SelectLoad(Node, 3, AArch64::LD3Rv2d, AArch64::qsub0);
2350 case Intrinsic::aarch64_neon_ld4r:
2351 if (VT == MVT::v8i8)
2352 return SelectLoad(Node, 4, AArch64::LD4Rv8b, AArch64::dsub0);
2353 else if (VT == MVT::v16i8)
2354 return SelectLoad(Node, 4, AArch64::LD4Rv16b, AArch64::qsub0);
2355 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2356 return SelectLoad(Node, 4, AArch64::LD4Rv4h, AArch64::dsub0);
2357 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2358 return SelectLoad(Node, 4, AArch64::LD4Rv8h, AArch64::qsub0);
2359 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2360 return SelectLoad(Node, 4, AArch64::LD4Rv2s, AArch64::dsub0);
2361 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2362 return SelectLoad(Node, 4, AArch64::LD4Rv4s, AArch64::qsub0);
2363 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2364 return SelectLoad(Node, 4, AArch64::LD4Rv1d, AArch64::dsub0);
2365 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2366 return SelectLoad(Node, 4, AArch64::LD4Rv2d, AArch64::qsub0);
2368 case Intrinsic::aarch64_neon_ld2lane:
2369 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2370 return SelectLoadLane(Node, 2, AArch64::LD2i8);
2371 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2373 return SelectLoadLane(Node, 2, AArch64::LD2i16);
2374 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2376 return SelectLoadLane(Node, 2, AArch64::LD2i32);
2377 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2379 return SelectLoadLane(Node, 2, AArch64::LD2i64);
2381 case Intrinsic::aarch64_neon_ld3lane:
2382 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2383 return SelectLoadLane(Node, 3, AArch64::LD3i8);
2384 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2386 return SelectLoadLane(Node, 3, AArch64::LD3i16);
2387 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2389 return SelectLoadLane(Node, 3, AArch64::LD3i32);
2390 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2392 return SelectLoadLane(Node, 3, AArch64::LD3i64);
2394 case Intrinsic::aarch64_neon_ld4lane:
2395 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2396 return SelectLoadLane(Node, 4, AArch64::LD4i8);
2397 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2399 return SelectLoadLane(Node, 4, AArch64::LD4i16);
2400 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2402 return SelectLoadLane(Node, 4, AArch64::LD4i32);
2403 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2405 return SelectLoadLane(Node, 4, AArch64::LD4i64);
2409 case ISD::INTRINSIC_WO_CHAIN: {
2410 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
2414 case Intrinsic::aarch64_neon_tbl2:
2415 return SelectTable(Node, 2, VT == MVT::v8i8 ? AArch64::TBLv8i8Two
2416 : AArch64::TBLv16i8Two,
2418 case Intrinsic::aarch64_neon_tbl3:
2419 return SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBLv8i8Three
2420 : AArch64::TBLv16i8Three,
2422 case Intrinsic::aarch64_neon_tbl4:
2423 return SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBLv8i8Four
2424 : AArch64::TBLv16i8Four,
2426 case Intrinsic::aarch64_neon_tbx2:
2427 return SelectTable(Node, 2, VT == MVT::v8i8 ? AArch64::TBXv8i8Two
2428 : AArch64::TBXv16i8Two,
2430 case Intrinsic::aarch64_neon_tbx3:
2431 return SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBXv8i8Three
2432 : AArch64::TBXv16i8Three,
2434 case Intrinsic::aarch64_neon_tbx4:
2435 return SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBXv8i8Four
2436 : AArch64::TBXv16i8Four,
2438 case Intrinsic::aarch64_neon_smull:
2439 case Intrinsic::aarch64_neon_umull:
2440 if (SDNode *N = SelectMULLV64LaneV128(IntNo, Node))
2446 case ISD::INTRINSIC_VOID: {
2447 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2448 if (Node->getNumOperands() >= 3)
2449 VT = Node->getOperand(2)->getValueType(0);
2453 case Intrinsic::aarch64_neon_st1x2: {
2454 if (VT == MVT::v8i8)
2455 return SelectStore(Node, 2, AArch64::ST1Twov8b);
2456 else if (VT == MVT::v16i8)
2457 return SelectStore(Node, 2, AArch64::ST1Twov16b);
2458 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2459 return SelectStore(Node, 2, AArch64::ST1Twov4h);
2460 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2461 return SelectStore(Node, 2, AArch64::ST1Twov8h);
2462 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2463 return SelectStore(Node, 2, AArch64::ST1Twov2s);
2464 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2465 return SelectStore(Node, 2, AArch64::ST1Twov4s);
2466 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2467 return SelectStore(Node, 2, AArch64::ST1Twov2d);
2468 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2469 return SelectStore(Node, 2, AArch64::ST1Twov1d);
2472 case Intrinsic::aarch64_neon_st1x3: {
2473 if (VT == MVT::v8i8)
2474 return SelectStore(Node, 3, AArch64::ST1Threev8b);
2475 else if (VT == MVT::v16i8)
2476 return SelectStore(Node, 3, AArch64::ST1Threev16b);
2477 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2478 return SelectStore(Node, 3, AArch64::ST1Threev4h);
2479 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2480 return SelectStore(Node, 3, AArch64::ST1Threev8h);
2481 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2482 return SelectStore(Node, 3, AArch64::ST1Threev2s);
2483 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2484 return SelectStore(Node, 3, AArch64::ST1Threev4s);
2485 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2486 return SelectStore(Node, 3, AArch64::ST1Threev2d);
2487 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2488 return SelectStore(Node, 3, AArch64::ST1Threev1d);
2491 case Intrinsic::aarch64_neon_st1x4: {
2492 if (VT == MVT::v8i8)
2493 return SelectStore(Node, 4, AArch64::ST1Fourv8b);
2494 else if (VT == MVT::v16i8)
2495 return SelectStore(Node, 4, AArch64::ST1Fourv16b);
2496 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2497 return SelectStore(Node, 4, AArch64::ST1Fourv4h);
2498 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2499 return SelectStore(Node, 4, AArch64::ST1Fourv8h);
2500 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2501 return SelectStore(Node, 4, AArch64::ST1Fourv2s);
2502 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2503 return SelectStore(Node, 4, AArch64::ST1Fourv4s);
2504 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2505 return SelectStore(Node, 4, AArch64::ST1Fourv2d);
2506 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2507 return SelectStore(Node, 4, AArch64::ST1Fourv1d);
2510 case Intrinsic::aarch64_neon_st2: {
2511 if (VT == MVT::v8i8)
2512 return SelectStore(Node, 2, AArch64::ST2Twov8b);
2513 else if (VT == MVT::v16i8)
2514 return SelectStore(Node, 2, AArch64::ST2Twov16b);
2515 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2516 return SelectStore(Node, 2, AArch64::ST2Twov4h);
2517 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2518 return SelectStore(Node, 2, AArch64::ST2Twov8h);
2519 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2520 return SelectStore(Node, 2, AArch64::ST2Twov2s);
2521 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2522 return SelectStore(Node, 2, AArch64::ST2Twov4s);
2523 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2524 return SelectStore(Node, 2, AArch64::ST2Twov2d);
2525 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2526 return SelectStore(Node, 2, AArch64::ST1Twov1d);
2529 case Intrinsic::aarch64_neon_st3: {
2530 if (VT == MVT::v8i8)
2531 return SelectStore(Node, 3, AArch64::ST3Threev8b);
2532 else if (VT == MVT::v16i8)
2533 return SelectStore(Node, 3, AArch64::ST3Threev16b);
2534 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2535 return SelectStore(Node, 3, AArch64::ST3Threev4h);
2536 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2537 return SelectStore(Node, 3, AArch64::ST3Threev8h);
2538 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2539 return SelectStore(Node, 3, AArch64::ST3Threev2s);
2540 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2541 return SelectStore(Node, 3, AArch64::ST3Threev4s);
2542 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2543 return SelectStore(Node, 3, AArch64::ST3Threev2d);
2544 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2545 return SelectStore(Node, 3, AArch64::ST1Threev1d);
2548 case Intrinsic::aarch64_neon_st4: {
2549 if (VT == MVT::v8i8)
2550 return SelectStore(Node, 4, AArch64::ST4Fourv8b);
2551 else if (VT == MVT::v16i8)
2552 return SelectStore(Node, 4, AArch64::ST4Fourv16b);
2553 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2554 return SelectStore(Node, 4, AArch64::ST4Fourv4h);
2555 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2556 return SelectStore(Node, 4, AArch64::ST4Fourv8h);
2557 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2558 return SelectStore(Node, 4, AArch64::ST4Fourv2s);
2559 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2560 return SelectStore(Node, 4, AArch64::ST4Fourv4s);
2561 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2562 return SelectStore(Node, 4, AArch64::ST4Fourv2d);
2563 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2564 return SelectStore(Node, 4, AArch64::ST1Fourv1d);
2567 case Intrinsic::aarch64_neon_st2lane: {
2568 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2569 return SelectStoreLane(Node, 2, AArch64::ST2i8);
2570 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2572 return SelectStoreLane(Node, 2, AArch64::ST2i16);
2573 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2575 return SelectStoreLane(Node, 2, AArch64::ST2i32);
2576 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2578 return SelectStoreLane(Node, 2, AArch64::ST2i64);
2581 case Intrinsic::aarch64_neon_st3lane: {
2582 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2583 return SelectStoreLane(Node, 3, AArch64::ST3i8);
2584 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2586 return SelectStoreLane(Node, 3, AArch64::ST3i16);
2587 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2589 return SelectStoreLane(Node, 3, AArch64::ST3i32);
2590 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2592 return SelectStoreLane(Node, 3, AArch64::ST3i64);
2595 case Intrinsic::aarch64_neon_st4lane: {
2596 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2597 return SelectStoreLane(Node, 4, AArch64::ST4i8);
2598 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2600 return SelectStoreLane(Node, 4, AArch64::ST4i16);
2601 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2603 return SelectStoreLane(Node, 4, AArch64::ST4i32);
2604 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2606 return SelectStoreLane(Node, 4, AArch64::ST4i64);
2611 case AArch64ISD::LD2post: {
2612 if (VT == MVT::v8i8)
2613 return SelectPostLoad(Node, 2, AArch64::LD2Twov8b_POST, AArch64::dsub0);
2614 else if (VT == MVT::v16i8)
2615 return SelectPostLoad(Node, 2, AArch64::LD2Twov16b_POST, AArch64::qsub0);
2616 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2617 return SelectPostLoad(Node, 2, AArch64::LD2Twov4h_POST, AArch64::dsub0);
2618 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2619 return SelectPostLoad(Node, 2, AArch64::LD2Twov8h_POST, AArch64::qsub0);
2620 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2621 return SelectPostLoad(Node, 2, AArch64::LD2Twov2s_POST, AArch64::dsub0);
2622 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2623 return SelectPostLoad(Node, 2, AArch64::LD2Twov4s_POST, AArch64::qsub0);
2624 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2625 return SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
2626 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2627 return SelectPostLoad(Node, 2, AArch64::LD2Twov2d_POST, AArch64::qsub0);
2630 case AArch64ISD::LD3post: {
2631 if (VT == MVT::v8i8)
2632 return SelectPostLoad(Node, 3, AArch64::LD3Threev8b_POST, AArch64::dsub0);
2633 else if (VT == MVT::v16i8)
2634 return SelectPostLoad(Node, 3, AArch64::LD3Threev16b_POST, AArch64::qsub0);
2635 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2636 return SelectPostLoad(Node, 3, AArch64::LD3Threev4h_POST, AArch64::dsub0);
2637 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2638 return SelectPostLoad(Node, 3, AArch64::LD3Threev8h_POST, AArch64::qsub0);
2639 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2640 return SelectPostLoad(Node, 3, AArch64::LD3Threev2s_POST, AArch64::dsub0);
2641 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2642 return SelectPostLoad(Node, 3, AArch64::LD3Threev4s_POST, AArch64::qsub0);
2643 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2644 return SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
2645 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2646 return SelectPostLoad(Node, 3, AArch64::LD3Threev2d_POST, AArch64::qsub0);
2649 case AArch64ISD::LD4post: {
2650 if (VT == MVT::v8i8)
2651 return SelectPostLoad(Node, 4, AArch64::LD4Fourv8b_POST, AArch64::dsub0);
2652 else if (VT == MVT::v16i8)
2653 return SelectPostLoad(Node, 4, AArch64::LD4Fourv16b_POST, AArch64::qsub0);
2654 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2655 return SelectPostLoad(Node, 4, AArch64::LD4Fourv4h_POST, AArch64::dsub0);
2656 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2657 return SelectPostLoad(Node, 4, AArch64::LD4Fourv8h_POST, AArch64::qsub0);
2658 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2659 return SelectPostLoad(Node, 4, AArch64::LD4Fourv2s_POST, AArch64::dsub0);
2660 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2661 return SelectPostLoad(Node, 4, AArch64::LD4Fourv4s_POST, AArch64::qsub0);
2662 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2663 return SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
2664 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2665 return SelectPostLoad(Node, 4, AArch64::LD4Fourv2d_POST, AArch64::qsub0);
2668 case AArch64ISD::LD1x2post: {
2669 if (VT == MVT::v8i8)
2670 return SelectPostLoad(Node, 2, AArch64::LD1Twov8b_POST, AArch64::dsub0);
2671 else if (VT == MVT::v16i8)
2672 return SelectPostLoad(Node, 2, AArch64::LD1Twov16b_POST, AArch64::qsub0);
2673 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2674 return SelectPostLoad(Node, 2, AArch64::LD1Twov4h_POST, AArch64::dsub0);
2675 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2676 return SelectPostLoad(Node, 2, AArch64::LD1Twov8h_POST, AArch64::qsub0);
2677 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2678 return SelectPostLoad(Node, 2, AArch64::LD1Twov2s_POST, AArch64::dsub0);
2679 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2680 return SelectPostLoad(Node, 2, AArch64::LD1Twov4s_POST, AArch64::qsub0);
2681 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2682 return SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
2683 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2684 return SelectPostLoad(Node, 2, AArch64::LD1Twov2d_POST, AArch64::qsub0);
2687 case AArch64ISD::LD1x3post: {
2688 if (VT == MVT::v8i8)
2689 return SelectPostLoad(Node, 3, AArch64::LD1Threev8b_POST, AArch64::dsub0);
2690 else if (VT == MVT::v16i8)
2691 return SelectPostLoad(Node, 3, AArch64::LD1Threev16b_POST, AArch64::qsub0);
2692 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2693 return SelectPostLoad(Node, 3, AArch64::LD1Threev4h_POST, AArch64::dsub0);
2694 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2695 return SelectPostLoad(Node, 3, AArch64::LD1Threev8h_POST, AArch64::qsub0);
2696 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2697 return SelectPostLoad(Node, 3, AArch64::LD1Threev2s_POST, AArch64::dsub0);
2698 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2699 return SelectPostLoad(Node, 3, AArch64::LD1Threev4s_POST, AArch64::qsub0);
2700 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2701 return SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
2702 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2703 return SelectPostLoad(Node, 3, AArch64::LD1Threev2d_POST, AArch64::qsub0);
2706 case AArch64ISD::LD1x4post: {
2707 if (VT == MVT::v8i8)
2708 return SelectPostLoad(Node, 4, AArch64::LD1Fourv8b_POST, AArch64::dsub0);
2709 else if (VT == MVT::v16i8)
2710 return SelectPostLoad(Node, 4, AArch64::LD1Fourv16b_POST, AArch64::qsub0);
2711 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2712 return SelectPostLoad(Node, 4, AArch64::LD1Fourv4h_POST, AArch64::dsub0);
2713 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2714 return SelectPostLoad(Node, 4, AArch64::LD1Fourv8h_POST, AArch64::qsub0);
2715 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2716 return SelectPostLoad(Node, 4, AArch64::LD1Fourv2s_POST, AArch64::dsub0);
2717 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2718 return SelectPostLoad(Node, 4, AArch64::LD1Fourv4s_POST, AArch64::qsub0);
2719 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2720 return SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
2721 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2722 return SelectPostLoad(Node, 4, AArch64::LD1Fourv2d_POST, AArch64::qsub0);
2725 case AArch64ISD::LD1DUPpost: {
2726 if (VT == MVT::v8i8)
2727 return SelectPostLoad(Node, 1, AArch64::LD1Rv8b_POST, AArch64::dsub0);
2728 else if (VT == MVT::v16i8)
2729 return SelectPostLoad(Node, 1, AArch64::LD1Rv16b_POST, AArch64::qsub0);
2730 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2731 return SelectPostLoad(Node, 1, AArch64::LD1Rv4h_POST, AArch64::dsub0);
2732 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2733 return SelectPostLoad(Node, 1, AArch64::LD1Rv8h_POST, AArch64::qsub0);
2734 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2735 return SelectPostLoad(Node, 1, AArch64::LD1Rv2s_POST, AArch64::dsub0);
2736 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2737 return SelectPostLoad(Node, 1, AArch64::LD1Rv4s_POST, AArch64::qsub0);
2738 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2739 return SelectPostLoad(Node, 1, AArch64::LD1Rv1d_POST, AArch64::dsub0);
2740 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2741 return SelectPostLoad(Node, 1, AArch64::LD1Rv2d_POST, AArch64::qsub0);
2744 case AArch64ISD::LD2DUPpost: {
2745 if (VT == MVT::v8i8)
2746 return SelectPostLoad(Node, 2, AArch64::LD2Rv8b_POST, AArch64::dsub0);
2747 else if (VT == MVT::v16i8)
2748 return SelectPostLoad(Node, 2, AArch64::LD2Rv16b_POST, AArch64::qsub0);
2749 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2750 return SelectPostLoad(Node, 2, AArch64::LD2Rv4h_POST, AArch64::dsub0);
2751 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2752 return SelectPostLoad(Node, 2, AArch64::LD2Rv8h_POST, AArch64::qsub0);
2753 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2754 return SelectPostLoad(Node, 2, AArch64::LD2Rv2s_POST, AArch64::dsub0);
2755 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2756 return SelectPostLoad(Node, 2, AArch64::LD2Rv4s_POST, AArch64::qsub0);
2757 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2758 return SelectPostLoad(Node, 2, AArch64::LD2Rv1d_POST, AArch64::dsub0);
2759 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2760 return SelectPostLoad(Node, 2, AArch64::LD2Rv2d_POST, AArch64::qsub0);
2763 case AArch64ISD::LD3DUPpost: {
2764 if (VT == MVT::v8i8)
2765 return SelectPostLoad(Node, 3, AArch64::LD3Rv8b_POST, AArch64::dsub0);
2766 else if (VT == MVT::v16i8)
2767 return SelectPostLoad(Node, 3, AArch64::LD3Rv16b_POST, AArch64::qsub0);
2768 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2769 return SelectPostLoad(Node, 3, AArch64::LD3Rv4h_POST, AArch64::dsub0);
2770 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2771 return SelectPostLoad(Node, 3, AArch64::LD3Rv8h_POST, AArch64::qsub0);
2772 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2773 return SelectPostLoad(Node, 3, AArch64::LD3Rv2s_POST, AArch64::dsub0);
2774 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2775 return SelectPostLoad(Node, 3, AArch64::LD3Rv4s_POST, AArch64::qsub0);
2776 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2777 return SelectPostLoad(Node, 3, AArch64::LD3Rv1d_POST, AArch64::dsub0);
2778 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2779 return SelectPostLoad(Node, 3, AArch64::LD3Rv2d_POST, AArch64::qsub0);
2782 case AArch64ISD::LD4DUPpost: {
2783 if (VT == MVT::v8i8)
2784 return SelectPostLoad(Node, 4, AArch64::LD4Rv8b_POST, AArch64::dsub0);
2785 else if (VT == MVT::v16i8)
2786 return SelectPostLoad(Node, 4, AArch64::LD4Rv16b_POST, AArch64::qsub0);
2787 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2788 return SelectPostLoad(Node, 4, AArch64::LD4Rv4h_POST, AArch64::dsub0);
2789 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2790 return SelectPostLoad(Node, 4, AArch64::LD4Rv8h_POST, AArch64::qsub0);
2791 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2792 return SelectPostLoad(Node, 4, AArch64::LD4Rv2s_POST, AArch64::dsub0);
2793 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2794 return SelectPostLoad(Node, 4, AArch64::LD4Rv4s_POST, AArch64::qsub0);
2795 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2796 return SelectPostLoad(Node, 4, AArch64::LD4Rv1d_POST, AArch64::dsub0);
2797 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2798 return SelectPostLoad(Node, 4, AArch64::LD4Rv2d_POST, AArch64::qsub0);
2801 case AArch64ISD::LD1LANEpost: {
2802 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2803 return SelectPostLoadLane(Node, 1, AArch64::LD1i8_POST);
2804 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2806 return SelectPostLoadLane(Node, 1, AArch64::LD1i16_POST);
2807 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2809 return SelectPostLoadLane(Node, 1, AArch64::LD1i32_POST);
2810 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2812 return SelectPostLoadLane(Node, 1, AArch64::LD1i64_POST);
2815 case AArch64ISD::LD2LANEpost: {
2816 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2817 return SelectPostLoadLane(Node, 2, AArch64::LD2i8_POST);
2818 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2820 return SelectPostLoadLane(Node, 2, AArch64::LD2i16_POST);
2821 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2823 return SelectPostLoadLane(Node, 2, AArch64::LD2i32_POST);
2824 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2826 return SelectPostLoadLane(Node, 2, AArch64::LD2i64_POST);
2829 case AArch64ISD::LD3LANEpost: {
2830 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2831 return SelectPostLoadLane(Node, 3, AArch64::LD3i8_POST);
2832 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2834 return SelectPostLoadLane(Node, 3, AArch64::LD3i16_POST);
2835 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2837 return SelectPostLoadLane(Node, 3, AArch64::LD3i32_POST);
2838 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2840 return SelectPostLoadLane(Node, 3, AArch64::LD3i64_POST);
2843 case AArch64ISD::LD4LANEpost: {
2844 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2845 return SelectPostLoadLane(Node, 4, AArch64::LD4i8_POST);
2846 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2848 return SelectPostLoadLane(Node, 4, AArch64::LD4i16_POST);
2849 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2851 return SelectPostLoadLane(Node, 4, AArch64::LD4i32_POST);
2852 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2854 return SelectPostLoadLane(Node, 4, AArch64::LD4i64_POST);
2857 case AArch64ISD::ST2post: {
2858 VT = Node->getOperand(1).getValueType();
2859 if (VT == MVT::v8i8)
2860 return SelectPostStore(Node, 2, AArch64::ST2Twov8b_POST);
2861 else if (VT == MVT::v16i8)
2862 return SelectPostStore(Node, 2, AArch64::ST2Twov16b_POST);
2863 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2864 return SelectPostStore(Node, 2, AArch64::ST2Twov4h_POST);
2865 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2866 return SelectPostStore(Node, 2, AArch64::ST2Twov8h_POST);
2867 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2868 return SelectPostStore(Node, 2, AArch64::ST2Twov2s_POST);
2869 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2870 return SelectPostStore(Node, 2, AArch64::ST2Twov4s_POST);
2871 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2872 return SelectPostStore(Node, 2, AArch64::ST2Twov2d_POST);
2873 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2874 return SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
2877 case AArch64ISD::ST3post: {
2878 VT = Node->getOperand(1).getValueType();
2879 if (VT == MVT::v8i8)
2880 return SelectPostStore(Node, 3, AArch64::ST3Threev8b_POST);
2881 else if (VT == MVT::v16i8)
2882 return SelectPostStore(Node, 3, AArch64::ST3Threev16b_POST);
2883 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2884 return SelectPostStore(Node, 3, AArch64::ST3Threev4h_POST);
2885 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2886 return SelectPostStore(Node, 3, AArch64::ST3Threev8h_POST);
2887 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2888 return SelectPostStore(Node, 3, AArch64::ST3Threev2s_POST);
2889 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2890 return SelectPostStore(Node, 3, AArch64::ST3Threev4s_POST);
2891 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2892 return SelectPostStore(Node, 3, AArch64::ST3Threev2d_POST);
2893 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2894 return SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
2897 case AArch64ISD::ST4post: {
2898 VT = Node->getOperand(1).getValueType();
2899 if (VT == MVT::v8i8)
2900 return SelectPostStore(Node, 4, AArch64::ST4Fourv8b_POST);
2901 else if (VT == MVT::v16i8)
2902 return SelectPostStore(Node, 4, AArch64::ST4Fourv16b_POST);
2903 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2904 return SelectPostStore(Node, 4, AArch64::ST4Fourv4h_POST);
2905 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2906 return SelectPostStore(Node, 4, AArch64::ST4Fourv8h_POST);
2907 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2908 return SelectPostStore(Node, 4, AArch64::ST4Fourv2s_POST);
2909 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2910 return SelectPostStore(Node, 4, AArch64::ST4Fourv4s_POST);
2911 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2912 return SelectPostStore(Node, 4, AArch64::ST4Fourv2d_POST);
2913 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2914 return SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
2917 case AArch64ISD::ST1x2post: {
2918 VT = Node->getOperand(1).getValueType();
2919 if (VT == MVT::v8i8)
2920 return SelectPostStore(Node, 2, AArch64::ST1Twov8b_POST);
2921 else if (VT == MVT::v16i8)
2922 return SelectPostStore(Node, 2, AArch64::ST1Twov16b_POST);
2923 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2924 return SelectPostStore(Node, 2, AArch64::ST1Twov4h_POST);
2925 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2926 return SelectPostStore(Node, 2, AArch64::ST1Twov8h_POST);
2927 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2928 return SelectPostStore(Node, 2, AArch64::ST1Twov2s_POST);
2929 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2930 return SelectPostStore(Node, 2, AArch64::ST1Twov4s_POST);
2931 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2932 return SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
2933 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2934 return SelectPostStore(Node, 2, AArch64::ST1Twov2d_POST);
2937 case AArch64ISD::ST1x3post: {
2938 VT = Node->getOperand(1).getValueType();
2939 if (VT == MVT::v8i8)
2940 return SelectPostStore(Node, 3, AArch64::ST1Threev8b_POST);
2941 else if (VT == MVT::v16i8)
2942 return SelectPostStore(Node, 3, AArch64::ST1Threev16b_POST);
2943 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2944 return SelectPostStore(Node, 3, AArch64::ST1Threev4h_POST);
2945 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2946 return SelectPostStore(Node, 3, AArch64::ST1Threev8h_POST);
2947 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2948 return SelectPostStore(Node, 3, AArch64::ST1Threev2s_POST);
2949 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2950 return SelectPostStore(Node, 3, AArch64::ST1Threev4s_POST);
2951 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2952 return SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
2953 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2954 return SelectPostStore(Node, 3, AArch64::ST1Threev2d_POST);
2957 case AArch64ISD::ST1x4post: {
2958 VT = Node->getOperand(1).getValueType();
2959 if (VT == MVT::v8i8)
2960 return SelectPostStore(Node, 4, AArch64::ST1Fourv8b_POST);
2961 else if (VT == MVT::v16i8)
2962 return SelectPostStore(Node, 4, AArch64::ST1Fourv16b_POST);
2963 else if (VT == MVT::v4i16 || VT == MVT::v4f16)
2964 return SelectPostStore(Node, 4, AArch64::ST1Fourv4h_POST);
2965 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
2966 return SelectPostStore(Node, 4, AArch64::ST1Fourv8h_POST);
2967 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2968 return SelectPostStore(Node, 4, AArch64::ST1Fourv2s_POST);
2969 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2970 return SelectPostStore(Node, 4, AArch64::ST1Fourv4s_POST);
2971 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2972 return SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
2973 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2974 return SelectPostStore(Node, 4, AArch64::ST1Fourv2d_POST);
2977 case AArch64ISD::ST2LANEpost: {
2978 VT = Node->getOperand(1).getValueType();
2979 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2980 return SelectPostStoreLane(Node, 2, AArch64::ST2i8_POST);
2981 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2983 return SelectPostStoreLane(Node, 2, AArch64::ST2i16_POST);
2984 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2986 return SelectPostStoreLane(Node, 2, AArch64::ST2i32_POST);
2987 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2989 return SelectPostStoreLane(Node, 2, AArch64::ST2i64_POST);
2992 case AArch64ISD::ST3LANEpost: {
2993 VT = Node->getOperand(1).getValueType();
2994 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2995 return SelectPostStoreLane(Node, 3, AArch64::ST3i8_POST);
2996 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
2998 return SelectPostStoreLane(Node, 3, AArch64::ST3i16_POST);
2999 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3001 return SelectPostStoreLane(Node, 3, AArch64::ST3i32_POST);
3002 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3004 return SelectPostStoreLane(Node, 3, AArch64::ST3i64_POST);
3007 case AArch64ISD::ST4LANEpost: {
3008 VT = Node->getOperand(1).getValueType();
3009 if (VT == MVT::v16i8 || VT == MVT::v8i8)
3010 return SelectPostStoreLane(Node, 4, AArch64::ST4i8_POST);
3011 else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
3013 return SelectPostStoreLane(Node, 4, AArch64::ST4i16_POST);
3014 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
3016 return SelectPostStoreLane(Node, 4, AArch64::ST4i32_POST);
3017 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
3019 return SelectPostStoreLane(Node, 4, AArch64::ST4i64_POST);
3027 if (SDNode *I = SelectLIBM(Node))
3032 // Select the default instruction
3033 ResNode = SelectCode(Node);
3035 DEBUG(errs() << "=> ");
3036 if (ResNode == nullptr || ResNode == Node)
3037 DEBUG(Node->dump(CurDAG));
3039 DEBUG(ResNode->dump(CurDAG));
3040 DEBUG(errs() << "\n");
3045 /// createAArch64ISelDag - This pass converts a legalized DAG into a
3046 /// AArch64-specific DAG, ready for instruction scheduling.
3047 FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM,
3048 CodeGenOpt::Level OptLevel) {
3049 return new AArch64DAGToDAGISel(TM, OptLevel);