1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Operator.h"
38 #include "llvm/Support/CommandLine.h"
43 class AArch64FastISel final : public FastISel {
53 AArch64_AM::ShiftExtendType ExtType;
61 const GlobalValue *GV;
64 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
65 OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; }
66 void setKind(BaseKind K) { Kind = K; }
67 BaseKind getKind() const { return Kind; }
68 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
69 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
70 bool isRegBase() const { return Kind == RegBase; }
71 bool isFIBase() const { return Kind == FrameIndexBase; }
72 void setReg(unsigned Reg) {
73 assert(isRegBase() && "Invalid base register access!");
76 unsigned getReg() const {
77 assert(isRegBase() && "Invalid base register access!");
80 void setOffsetReg(unsigned Reg) {
81 assert(isRegBase() && "Invalid offset register access!");
84 unsigned getOffsetReg() const {
85 assert(isRegBase() && "Invalid offset register access!");
88 void setFI(unsigned FI) {
89 assert(isFIBase() && "Invalid base frame index access!");
92 unsigned getFI() const {
93 assert(isFIBase() && "Invalid base frame index access!");
96 void setOffset(int64_t O) { Offset = O; }
97 int64_t getOffset() { return Offset; }
98 void setShift(unsigned S) { Shift = S; }
99 unsigned getShift() { return Shift; }
101 void setGlobalValue(const GlobalValue *G) { GV = G; }
102 const GlobalValue *getGlobalValue() { return GV; }
105 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
106 /// make the right decision when generating code for different targets.
107 const AArch64Subtarget *Subtarget;
108 LLVMContext *Context;
110 bool fastLowerArguments() override;
111 bool fastLowerCall(CallLoweringInfo &CLI) override;
112 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
115 // Selection routines.
116 bool selectAddSub(const Instruction *I);
117 bool selectLogicalOp(const Instruction *I);
118 bool selectLoad(const Instruction *I);
119 bool selectStore(const Instruction *I);
120 bool selectBranch(const Instruction *I);
121 bool selectIndirectBr(const Instruction *I);
122 bool selectCmp(const Instruction *I);
123 bool selectSelect(const Instruction *I);
124 bool selectFPExt(const Instruction *I);
125 bool selectFPTrunc(const Instruction *I);
126 bool selectFPToInt(const Instruction *I, bool Signed);
127 bool selectIntToFP(const Instruction *I, bool Signed);
128 bool selectRem(const Instruction *I, unsigned ISDOpcode);
129 bool selectRet(const Instruction *I);
130 bool selectTrunc(const Instruction *I);
131 bool selectIntExt(const Instruction *I);
132 bool selectMul(const Instruction *I);
133 bool selectShift(const Instruction *I);
134 bool selectBitCast(const Instruction *I);
135 bool selectFRem(const Instruction *I);
136 bool selectSDiv(const Instruction *I);
138 // Utility helper routines.
139 bool isTypeLegal(Type *Ty, MVT &VT);
140 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
141 bool isValueAvailable(const Value *V) const;
142 bool computeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
143 bool computeCallAddress(const Value *V, Address &Addr);
144 bool simplifyAddress(Address &Addr, MVT VT);
145 void addLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
146 unsigned Flags, unsigned ScaleFactor,
147 MachineMemOperand *MMO);
148 bool isMemCpySmall(uint64_t Len, unsigned Alignment);
149 bool tryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
151 bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
154 // Emit helper routines.
155 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
156 const Value *RHS, bool SetFlags = false,
157 bool WantResult = true, bool IsZExt = false);
158 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
159 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
160 bool SetFlags = false, bool WantResult = true);
161 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
162 bool LHSIsKill, uint64_t Imm, bool SetFlags = false,
163 bool WantResult = true);
164 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
165 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
166 AArch64_AM::ShiftExtendType ShiftType,
167 uint64_t ShiftImm, bool SetFlags = false,
168 bool WantResult = true);
169 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
170 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
171 AArch64_AM::ShiftExtendType ExtType,
172 uint64_t ShiftImm, bool SetFlags = false,
173 bool WantResult = true);
176 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
177 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
178 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
179 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
180 bool emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
181 MachineMemOperand *MMO = nullptr);
182 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
183 MachineMemOperand *MMO = nullptr);
184 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
185 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
186 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
187 bool SetFlags = false, bool WantResult = true,
188 bool IsZExt = false);
189 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
190 bool SetFlags = false, bool WantResult = true,
191 bool IsZExt = false);
192 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
193 unsigned RHSReg, bool RHSIsKill, bool WantResult = true);
194 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
195 unsigned RHSReg, bool RHSIsKill,
196 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
197 bool WantResult = true);
198 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
200 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
201 bool LHSIsKill, uint64_t Imm);
202 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
203 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
205 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
206 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
207 unsigned Op1, bool Op1IsKill);
208 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
209 unsigned Op1, bool Op1IsKill);
210 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
211 unsigned Op1, bool Op1IsKill);
212 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
213 unsigned Op1Reg, bool Op1IsKill);
214 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
215 uint64_t Imm, bool IsZExt = true);
216 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
217 unsigned Op1Reg, bool Op1IsKill);
218 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
219 uint64_t Imm, bool IsZExt = true);
220 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
221 unsigned Op1Reg, bool Op1IsKill);
222 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
223 uint64_t Imm, bool IsZExt = false);
225 unsigned materializeInt(const ConstantInt *CI, MVT VT);
226 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
227 unsigned materializeGV(const GlobalValue *GV);
229 // Call handling routines.
231 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
232 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
234 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
237 // Backend specific FastISel code.
238 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
239 unsigned fastMaterializeConstant(const Constant *C) override;
240 unsigned fastMaterializeFloatZero(const ConstantFP* CF) override;
242 explicit AArch64FastISel(FunctionLoweringInfo &FuncInfo,
243 const TargetLibraryInfo *LibInfo)
244 : FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
245 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
246 Context = &FuncInfo.Fn->getContext();
249 bool fastSelectInstruction(const Instruction *I) override;
251 #include "AArch64GenFastISel.inc"
254 } // end anonymous namespace
256 #include "AArch64GenCallingConv.inc"
258 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
259 if (CC == CallingConv::WebKit_JS)
260 return CC_AArch64_WebKit_JS;
261 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
264 unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
265 assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
266 "Alloca should always return a pointer.");
268 // Don't handle dynamic allocas.
269 if (!FuncInfo.StaticAllocaMap.count(AI))
272 DenseMap<const AllocaInst *, int>::iterator SI =
273 FuncInfo.StaticAllocaMap.find(AI);
275 if (SI != FuncInfo.StaticAllocaMap.end()) {
276 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
279 .addFrameIndex(SI->second)
288 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {
293 return fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
295 // Create a copy from the zero register to materialize a "0" value.
296 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
297 : &AArch64::GPR32RegClass;
298 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
299 unsigned ResultReg = createResultReg(RC);
300 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
301 ResultReg).addReg(ZeroReg, getKillRegState(true));
305 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
306 // Positive zero (+0.0) has to be materialized with a fmov from the zero
307 // register, because the immediate version of fmov cannot encode zero.
308 if (CFP->isNullValue())
309 return fastMaterializeFloatZero(CFP);
311 if (VT != MVT::f32 && VT != MVT::f64)
314 const APFloat Val = CFP->getValueAPF();
315 bool Is64Bit = (VT == MVT::f64);
316 // This checks to see if we can use FMOV instructions to materialize
317 // a constant, otherwise we have to materialize via the constant pool.
318 if (TLI.isFPImmLegal(Val, VT)) {
320 Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val);
321 assert((Imm != -1) && "Cannot encode floating-point constant.");
322 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi;
323 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
326 // Materialize via constant pool. MachineConstantPool wants an explicit
328 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
330 Align = DL.getTypeAllocSize(CFP->getType());
332 unsigned CPI = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
333 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
334 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
335 ADRPReg).addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGE);
337 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui;
338 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
339 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
341 .addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
345 unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
346 // We can't handle thread-local variables quickly yet.
347 if (GV->isThreadLocal())
350 // MachO still uses GOT for large code-model accesses, but ELF requires
351 // movz/movk sequences, which FastISel doesn't handle yet.
352 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
355 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
357 EVT DestEVT = TLI.getValueType(GV->getType(), true);
358 if (!DestEVT.isSimple())
361 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
364 if (OpFlags & AArch64II::MO_GOT) {
366 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
368 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
370 ResultReg = createResultReg(&AArch64::GPR64RegClass);
371 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
374 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
376 } else if (OpFlags & AArch64II::MO_CONSTPOOL) {
377 // We can't handle addresses loaded from a constant pool quickly yet.
381 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
383 .addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
385 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
386 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
389 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
395 unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {
396 EVT CEVT = TLI.getValueType(C->getType(), true);
398 // Only handle simple types.
399 if (!CEVT.isSimple())
401 MVT VT = CEVT.getSimpleVT();
403 if (const auto *CI = dyn_cast<ConstantInt>(C))
404 return materializeInt(CI, VT);
405 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
406 return materializeFP(CFP, VT);
407 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
408 return materializeGV(GV);
413 unsigned AArch64FastISel::fastMaterializeFloatZero(const ConstantFP* CFP) {
414 assert(CFP->isNullValue() &&
415 "Floating-point constant is not a positive zero.");
417 if (!isTypeLegal(CFP->getType(), VT))
420 if (VT != MVT::f32 && VT != MVT::f64)
423 bool Is64Bit = (VT == MVT::f64);
424 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
425 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr;
426 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true);
429 /// \brief Check if the multiply is by a power-of-2 constant.
430 static bool isMulPowOf2(const Value *I) {
431 if (const auto *MI = dyn_cast<MulOperator>(I)) {
432 if (const auto *C = dyn_cast<ConstantInt>(MI->getOperand(0)))
433 if (C->getValue().isPowerOf2())
435 if (const auto *C = dyn_cast<ConstantInt>(MI->getOperand(1)))
436 if (C->getValue().isPowerOf2())
442 // Computes the address to get to an object.
443 bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
445 const User *U = nullptr;
446 unsigned Opcode = Instruction::UserOp1;
447 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
448 // Don't walk into other basic blocks unless the object is an alloca from
449 // another block, otherwise it may not have a virtual register assigned.
450 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
451 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
452 Opcode = I->getOpcode();
455 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
456 Opcode = C->getOpcode();
460 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
461 if (Ty->getAddressSpace() > 255)
462 // Fast instruction selection doesn't support the special
469 case Instruction::BitCast: {
470 // Look through bitcasts.
471 return computeAddress(U->getOperand(0), Addr, Ty);
473 case Instruction::IntToPtr: {
474 // Look past no-op inttoptrs.
475 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
476 return computeAddress(U->getOperand(0), Addr, Ty);
479 case Instruction::PtrToInt: {
480 // Look past no-op ptrtoints.
481 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
482 return computeAddress(U->getOperand(0), Addr, Ty);
485 case Instruction::GetElementPtr: {
486 Address SavedAddr = Addr;
487 uint64_t TmpOffset = Addr.getOffset();
489 // Iterate through the GEP folding the constants into offsets where
491 gep_type_iterator GTI = gep_type_begin(U);
492 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
494 const Value *Op = *i;
495 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
496 const StructLayout *SL = DL.getStructLayout(STy);
497 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
498 TmpOffset += SL->getElementOffset(Idx);
500 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
502 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
503 // Constant-offset addressing.
504 TmpOffset += CI->getSExtValue() * S;
507 if (canFoldAddIntoGEP(U, Op)) {
508 // A compatible add with a constant operand. Fold the constant.
510 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
511 TmpOffset += CI->getSExtValue() * S;
512 // Iterate on the other operand.
513 Op = cast<AddOperator>(Op)->getOperand(0);
517 goto unsupported_gep;
522 // Try to grab the base operand now.
523 Addr.setOffset(TmpOffset);
524 if (computeAddress(U->getOperand(0), Addr, Ty))
527 // We failed, restore everything and try the other options.
533 case Instruction::Alloca: {
534 const AllocaInst *AI = cast<AllocaInst>(Obj);
535 DenseMap<const AllocaInst *, int>::iterator SI =
536 FuncInfo.StaticAllocaMap.find(AI);
537 if (SI != FuncInfo.StaticAllocaMap.end()) {
538 Addr.setKind(Address::FrameIndexBase);
539 Addr.setFI(SI->second);
544 case Instruction::Add: {
545 // Adds of constants are common and easy enough.
546 const Value *LHS = U->getOperand(0);
547 const Value *RHS = U->getOperand(1);
549 if (isa<ConstantInt>(LHS))
552 if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
553 Addr.setOffset(Addr.getOffset() + (uint64_t)CI->getSExtValue());
554 return computeAddress(LHS, Addr, Ty);
557 Address Backup = Addr;
558 if (computeAddress(LHS, Addr, Ty) && computeAddress(RHS, Addr, Ty))
564 case Instruction::Shl:
565 if (Addr.getOffsetReg())
568 if (const auto *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
569 unsigned Val = CI->getZExtValue();
570 if (Val < 1 || Val > 3)
573 uint64_t NumBytes = 0;
574 if (Ty && Ty->isSized()) {
575 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
576 NumBytes = NumBits / 8;
577 if (!isPowerOf2_64(NumBits))
581 if (NumBytes != (1ULL << Val))
585 Addr.setExtendType(AArch64_AM::LSL);
587 if (const auto *I = dyn_cast<Instruction>(U->getOperand(0)))
588 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
591 if (const auto *ZE = dyn_cast<ZExtInst>(U))
592 if (ZE->getOperand(0)->getType()->isIntegerTy(32))
593 Addr.setExtendType(AArch64_AM::UXTW);
595 if (const auto *SE = dyn_cast<SExtInst>(U))
596 if (SE->getOperand(0)->getType()->isIntegerTy(32))
597 Addr.setExtendType(AArch64_AM::SXTW);
599 if (const auto *AI = dyn_cast<BinaryOperator>(U))
600 if (AI->getOpcode() == Instruction::And) {
601 const Value *LHS = AI->getOperand(0);
602 const Value *RHS = AI->getOperand(1);
604 if (const auto *C = dyn_cast<ConstantInt>(LHS))
605 if (C->getValue() == 0xffffffff)
608 if (const auto *C = cast<ConstantInt>(RHS))
609 if (C->getValue() == 0xffffffff) {
610 Addr.setExtendType(AArch64_AM::UXTW);
611 unsigned Reg = getRegForValue(LHS);
614 bool RegIsKill = hasTrivialKill(LHS);
615 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill,
617 Addr.setOffsetReg(Reg);
622 unsigned Reg = getRegForValue(U->getOperand(0));
625 Addr.setOffsetReg(Reg);
629 case Instruction::Mul: {
630 if (Addr.getOffsetReg())
636 const Value *LHS = U->getOperand(0);
637 const Value *RHS = U->getOperand(1);
639 // Canonicalize power-of-2 value to the RHS.
640 if (const auto *C = dyn_cast<ConstantInt>(LHS))
641 if (C->getValue().isPowerOf2())
644 assert(isa<ConstantInt>(RHS) && "Expected an ConstantInt.");
645 const auto *C = cast<ConstantInt>(RHS);
646 unsigned Val = C->getValue().logBase2();
647 if (Val < 1 || Val > 3)
650 uint64_t NumBytes = 0;
651 if (Ty && Ty->isSized()) {
652 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
653 NumBytes = NumBits / 8;
654 if (!isPowerOf2_64(NumBits))
658 if (NumBytes != (1ULL << Val))
662 Addr.setExtendType(AArch64_AM::LSL);
664 if (const auto *I = dyn_cast<Instruction>(LHS))
665 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
668 if (const auto *ZE = dyn_cast<ZExtInst>(U))
669 if (ZE->getOperand(0)->getType()->isIntegerTy(32)) {
670 Addr.setExtendType(AArch64_AM::UXTW);
671 LHS = U->getOperand(0);
674 if (const auto *SE = dyn_cast<SExtInst>(U))
675 if (SE->getOperand(0)->getType()->isIntegerTy(32)) {
676 Addr.setExtendType(AArch64_AM::SXTW);
677 LHS = U->getOperand(0);
680 unsigned Reg = getRegForValue(LHS);
683 Addr.setOffsetReg(Reg);
686 case Instruction::And: {
687 if (Addr.getOffsetReg())
690 if (DL.getTypeSizeInBits(Ty) != 8)
693 const Value *LHS = U->getOperand(0);
694 const Value *RHS = U->getOperand(1);
696 if (const auto *C = dyn_cast<ConstantInt>(LHS))
697 if (C->getValue() == 0xffffffff)
700 if (const auto *C = cast<ConstantInt>(RHS))
701 if (C->getValue() == 0xffffffff) {
703 Addr.setExtendType(AArch64_AM::LSL);
704 Addr.setExtendType(AArch64_AM::UXTW);
706 unsigned Reg = getRegForValue(LHS);
709 bool RegIsKill = hasTrivialKill(LHS);
710 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill,
712 Addr.setOffsetReg(Reg);
720 if (!Addr.getOffsetReg()) {
721 unsigned Reg = getRegForValue(Obj);
724 Addr.setOffsetReg(Reg);
730 unsigned Reg = getRegForValue(Obj);
737 bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {
738 const User *U = nullptr;
739 unsigned Opcode = Instruction::UserOp1;
742 if (const auto *I = dyn_cast<Instruction>(V)) {
743 Opcode = I->getOpcode();
745 InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
746 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
747 Opcode = C->getOpcode();
753 case Instruction::BitCast:
754 // Look past bitcasts if its operand is in the same BB.
756 return computeCallAddress(U->getOperand(0), Addr);
758 case Instruction::IntToPtr:
759 // Look past no-op inttoptrs if its operand is in the same BB.
761 TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
762 return computeCallAddress(U->getOperand(0), Addr);
764 case Instruction::PtrToInt:
765 // Look past no-op ptrtoints if its operand is in the same BB.
767 TLI.getValueType(U->getType()) == TLI.getPointerTy())
768 return computeCallAddress(U->getOperand(0), Addr);
772 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
773 Addr.setGlobalValue(GV);
777 // If all else fails, try to materialize the value in a register.
778 if (!Addr.getGlobalValue()) {
779 Addr.setReg(getRegForValue(V));
780 return Addr.getReg() != 0;
787 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
788 EVT evt = TLI.getValueType(Ty, true);
790 // Only handle simple types.
791 if (evt == MVT::Other || !evt.isSimple())
793 VT = evt.getSimpleVT();
795 // This is a legal type, but it's not something we handle in fast-isel.
799 // Handle all other legal types, i.e. a register that will directly hold this
801 return TLI.isTypeLegal(VT);
804 /// \brief Determine if the value type is supported by FastISel.
806 /// FastISel for AArch64 can handle more value types than are legal. This adds
807 /// simple value type such as i1, i8, and i16.
808 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) {
809 if (Ty->isVectorTy() && !IsVectorAllowed)
812 if (isTypeLegal(Ty, VT))
815 // If this is a type than can be sign or zero-extended to a basic operation
816 // go ahead and accept it now.
817 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
823 bool AArch64FastISel::isValueAvailable(const Value *V) const {
824 if (!isa<Instruction>(V))
827 const auto *I = cast<Instruction>(V);
828 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
834 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
835 unsigned ScaleFactor;
836 switch (VT.SimpleTy) {
837 default: return false;
838 case MVT::i1: // fall-through
839 case MVT::i8: ScaleFactor = 1; break;
840 case MVT::i16: ScaleFactor = 2; break;
841 case MVT::i32: // fall-through
842 case MVT::f32: ScaleFactor = 4; break;
843 case MVT::i64: // fall-through
844 case MVT::f64: ScaleFactor = 8; break;
847 bool ImmediateOffsetNeedsLowering = false;
848 bool RegisterOffsetNeedsLowering = false;
849 int64_t Offset = Addr.getOffset();
850 if (((Offset < 0) || (Offset & (ScaleFactor - 1))) && !isInt<9>(Offset))
851 ImmediateOffsetNeedsLowering = true;
852 else if (Offset > 0 && !(Offset & (ScaleFactor - 1)) &&
853 !isUInt<12>(Offset / ScaleFactor))
854 ImmediateOffsetNeedsLowering = true;
856 // Cannot encode an offset register and an immediate offset in the same
857 // instruction. Fold the immediate offset into the load/store instruction and
858 // emit an additonal add to take care of the offset register.
859 if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.isRegBase() &&
861 RegisterOffsetNeedsLowering = true;
863 // Cannot encode zero register as base.
864 if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg())
865 RegisterOffsetNeedsLowering = true;
867 // If this is a stack pointer and the offset needs to be simplified then put
868 // the alloca address into a register, set the base type back to register and
869 // continue. This should almost never happen.
870 if (ImmediateOffsetNeedsLowering && Addr.isFIBase()) {
871 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
872 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
874 .addFrameIndex(Addr.getFI())
877 Addr.setKind(Address::RegBase);
878 Addr.setReg(ResultReg);
881 if (RegisterOffsetNeedsLowering) {
882 unsigned ResultReg = 0;
884 if (Addr.getExtendType() == AArch64_AM::SXTW ||
885 Addr.getExtendType() == AArch64_AM::UXTW )
886 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
887 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
888 /*TODO:IsKill=*/false, Addr.getExtendType(),
891 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
892 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
893 /*TODO:IsKill=*/false, AArch64_AM::LSL,
896 if (Addr.getExtendType() == AArch64_AM::UXTW)
897 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
898 /*Op0IsKill=*/false, Addr.getShift(),
900 else if (Addr.getExtendType() == AArch64_AM::SXTW)
901 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
902 /*Op0IsKill=*/false, Addr.getShift(),
905 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
906 /*Op0IsKill=*/false, Addr.getShift());
911 Addr.setReg(ResultReg);
912 Addr.setOffsetReg(0);
914 Addr.setExtendType(AArch64_AM::InvalidShiftExtend);
917 // Since the offset is too large for the load/store instruction get the
918 // reg+offset into a register.
919 if (ImmediateOffsetNeedsLowering) {
922 // Try to fold the immediate into the add instruction.
924 ResultReg = emitAddSub_ri(/*UseAdd=*/false, MVT::i64, Addr.getReg(),
925 /*IsKill=*/false, -Offset);
927 ResultReg = emitAddSub_ri(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
928 /*IsKill=*/false, Offset);
930 unsigned ImmReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
931 ResultReg = emitAddSub_rr(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
932 /*IsKill=*/false, ImmReg, /*IsKill=*/true);
935 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
939 Addr.setReg(ResultReg);
945 void AArch64FastISel::addLoadStoreOperands(Address &Addr,
946 const MachineInstrBuilder &MIB,
948 unsigned ScaleFactor,
949 MachineMemOperand *MMO) {
950 int64_t Offset = Addr.getOffset() / ScaleFactor;
951 // Frame base works a bit differently. Handle it separately.
952 if (Addr.isFIBase()) {
953 int FI = Addr.getFI();
954 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
955 // and alignment should be based on the VT.
956 MMO = FuncInfo.MF->getMachineMemOperand(
957 MachinePointerInfo::getFixedStack(FI, Offset), Flags,
958 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
959 // Now add the rest of the operands.
960 MIB.addFrameIndex(FI).addImm(Offset);
962 assert(Addr.isRegBase() && "Unexpected address kind.");
963 const MCInstrDesc &II = MIB->getDesc();
964 unsigned Idx = (Flags & MachineMemOperand::MOStore) ? 1 : 0;
966 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));
968 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));
969 if (Addr.getOffsetReg()) {
970 assert(Addr.getOffset() == 0 && "Unexpected offset");
971 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW ||
972 Addr.getExtendType() == AArch64_AM::SXTX;
973 MIB.addReg(Addr.getReg());
974 MIB.addReg(Addr.getOffsetReg());
975 MIB.addImm(IsSigned);
976 MIB.addImm(Addr.getShift() != 0);
978 MIB.addReg(Addr.getReg());
984 MIB.addMemOperand(MMO);
987 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
988 const Value *RHS, bool SetFlags,
989 bool WantResult, bool IsZExt) {
990 AArch64_AM::ShiftExtendType ExtendType = AArch64_AM::InvalidShiftExtend;
991 bool NeedExtend = false;
992 switch (RetVT.SimpleTy) {
1000 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
1004 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
1006 case MVT::i32: // fall-through
1011 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
1013 // Canonicalize immediates to the RHS first.
1014 if (UseAdd && isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
1015 std::swap(LHS, RHS);
1017 // Canonicalize mul by power of 2 to the RHS.
1018 if (UseAdd && LHS->hasOneUse() && isValueAvailable(LHS))
1019 if (isMulPowOf2(LHS))
1020 std::swap(LHS, RHS);
1022 // Canonicalize shift immediate to the RHS.
1023 if (UseAdd && LHS->hasOneUse() && isValueAvailable(LHS))
1024 if (const auto *SI = dyn_cast<BinaryOperator>(LHS))
1025 if (isa<ConstantInt>(SI->getOperand(1)))
1026 if (SI->getOpcode() == Instruction::Shl ||
1027 SI->getOpcode() == Instruction::LShr ||
1028 SI->getOpcode() == Instruction::AShr )
1029 std::swap(LHS, RHS);
1031 unsigned LHSReg = getRegForValue(LHS);
1034 bool LHSIsKill = hasTrivialKill(LHS);
1037 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1039 unsigned ResultReg = 0;
1040 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
1041 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
1042 if (C->isNegative())
1043 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,
1044 SetFlags, WantResult);
1046 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,
1052 // Only extend the RHS within the instruction if there is a valid extend type.
1053 if (ExtendType != AArch64_AM::InvalidShiftExtend && RHS->hasOneUse() &&
1054 isValueAvailable(RHS)) {
1055 if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
1056 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
1057 if ((SI->getOpcode() == Instruction::Shl) && (C->getZExtValue() < 4)) {
1058 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1061 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1062 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1063 RHSIsKill, ExtendType, C->getZExtValue(),
1064 SetFlags, WantResult);
1066 unsigned RHSReg = getRegForValue(RHS);
1069 bool RHSIsKill = hasTrivialKill(RHS);
1070 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1071 ExtendType, 0, SetFlags, WantResult);
1074 // Check if the mul can be folded into the instruction.
1075 if (RHS->hasOneUse() && isValueAvailable(RHS))
1076 if (isMulPowOf2(RHS)) {
1077 const Value *MulLHS = cast<MulOperator>(RHS)->getOperand(0);
1078 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1);
1080 if (const auto *C = dyn_cast<ConstantInt>(MulLHS))
1081 if (C->getValue().isPowerOf2())
1082 std::swap(MulLHS, MulRHS);
1084 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt.");
1085 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
1086 unsigned RHSReg = getRegForValue(MulLHS);
1089 bool RHSIsKill = hasTrivialKill(MulLHS);
1090 return emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1091 AArch64_AM::LSL, ShiftVal, SetFlags, WantResult);
1094 // Check if the shift can be folded into the instruction.
1095 if (RHS->hasOneUse() && isValueAvailable(RHS))
1096 if (const auto *SI = dyn_cast<BinaryOperator>(RHS)) {
1097 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1))) {
1098 AArch64_AM::ShiftExtendType ShiftType = AArch64_AM::InvalidShiftExtend;
1099 switch (SI->getOpcode()) {
1101 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break;
1102 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break;
1103 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break;
1105 uint64_t ShiftVal = C->getZExtValue();
1106 if (ShiftType != AArch64_AM::InvalidShiftExtend) {
1107 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1110 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1111 return emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1112 RHSIsKill, ShiftType, ShiftVal, SetFlags,
1118 unsigned RHSReg = getRegForValue(RHS);
1121 bool RHSIsKill = hasTrivialKill(RHS);
1124 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1126 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1127 SetFlags, WantResult);
1130 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1131 bool LHSIsKill, unsigned RHSReg,
1132 bool RHSIsKill, bool SetFlags,
1134 assert(LHSReg && RHSReg && "Invalid register number.");
1136 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1139 static const unsigned OpcTable[2][2][2] = {
1140 { { AArch64::SUBWrr, AArch64::SUBXrr },
1141 { AArch64::ADDWrr, AArch64::ADDXrr } },
1142 { { AArch64::SUBSWrr, AArch64::SUBSXrr },
1143 { AArch64::ADDSWrr, AArch64::ADDSXrr } }
1145 bool Is64Bit = RetVT == MVT::i64;
1146 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1147 const TargetRegisterClass *RC =
1148 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1151 ResultReg = createResultReg(RC);
1153 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1155 const MCInstrDesc &II = TII.get(Opc);
1156 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1157 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1159 .addReg(LHSReg, getKillRegState(LHSIsKill))
1160 .addReg(RHSReg, getKillRegState(RHSIsKill));
1164 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1165 bool LHSIsKill, uint64_t Imm,
1166 bool SetFlags, bool WantResult) {
1167 assert(LHSReg && "Invalid register number.");
1169 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1173 if (isUInt<12>(Imm))
1175 else if ((Imm & 0xfff000) == Imm) {
1181 static const unsigned OpcTable[2][2][2] = {
1182 { { AArch64::SUBWri, AArch64::SUBXri },
1183 { AArch64::ADDWri, AArch64::ADDXri } },
1184 { { AArch64::SUBSWri, AArch64::SUBSXri },
1185 { AArch64::ADDSWri, AArch64::ADDSXri } }
1187 bool Is64Bit = RetVT == MVT::i64;
1188 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1189 const TargetRegisterClass *RC;
1191 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1193 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
1196 ResultReg = createResultReg(RC);
1198 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1200 const MCInstrDesc &II = TII.get(Opc);
1201 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1202 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1203 .addReg(LHSReg, getKillRegState(LHSIsKill))
1205 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1209 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1210 bool LHSIsKill, unsigned RHSReg,
1212 AArch64_AM::ShiftExtendType ShiftType,
1213 uint64_t ShiftImm, bool SetFlags,
1215 assert(LHSReg && RHSReg && "Invalid register number.");
1217 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1220 static const unsigned OpcTable[2][2][2] = {
1221 { { AArch64::SUBWrs, AArch64::SUBXrs },
1222 { AArch64::ADDWrs, AArch64::ADDXrs } },
1223 { { AArch64::SUBSWrs, AArch64::SUBSXrs },
1224 { AArch64::ADDSWrs, AArch64::ADDSXrs } }
1226 bool Is64Bit = RetVT == MVT::i64;
1227 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1228 const TargetRegisterClass *RC =
1229 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1232 ResultReg = createResultReg(RC);
1234 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1236 const MCInstrDesc &II = TII.get(Opc);
1237 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1238 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1239 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1240 .addReg(LHSReg, getKillRegState(LHSIsKill))
1241 .addReg(RHSReg, getKillRegState(RHSIsKill))
1242 .addImm(getShifterImm(ShiftType, ShiftImm));
1246 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1247 bool LHSIsKill, unsigned RHSReg,
1249 AArch64_AM::ShiftExtendType ExtType,
1250 uint64_t ShiftImm, bool SetFlags,
1252 assert(LHSReg && RHSReg && "Invalid register number.");
1254 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1257 static const unsigned OpcTable[2][2][2] = {
1258 { { AArch64::SUBWrx, AArch64::SUBXrx },
1259 { AArch64::ADDWrx, AArch64::ADDXrx } },
1260 { { AArch64::SUBSWrx, AArch64::SUBSXrx },
1261 { AArch64::ADDSWrx, AArch64::ADDSXrx } }
1263 bool Is64Bit = RetVT == MVT::i64;
1264 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1265 const TargetRegisterClass *RC = nullptr;
1267 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1269 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
1272 ResultReg = createResultReg(RC);
1274 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1276 const MCInstrDesc &II = TII.get(Opc);
1277 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1278 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1279 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1280 .addReg(LHSReg, getKillRegState(LHSIsKill))
1281 .addReg(RHSReg, getKillRegState(RHSIsKill))
1282 .addImm(getArithExtendImm(ExtType, ShiftImm));
1286 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
1287 Type *Ty = LHS->getType();
1288 EVT EVT = TLI.getValueType(Ty, true);
1289 if (!EVT.isSimple())
1291 MVT VT = EVT.getSimpleVT();
1293 switch (VT.SimpleTy) {
1301 return emitICmp(VT, LHS, RHS, IsZExt);
1304 return emitFCmp(VT, LHS, RHS);
1308 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
1310 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1314 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1316 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,
1317 /*SetFlags=*/true, /*WantResult=*/false) != 0;
1320 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
1321 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1324 // Check to see if the 2nd operand is a constant that we can encode directly
1326 bool UseImm = false;
1327 if (const auto *CFP = dyn_cast<ConstantFP>(RHS))
1328 if (CFP->isZero() && !CFP->isNegative())
1331 unsigned LHSReg = getRegForValue(LHS);
1334 bool LHSIsKill = hasTrivialKill(LHS);
1337 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1338 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1339 .addReg(LHSReg, getKillRegState(LHSIsKill));
1343 unsigned RHSReg = getRegForValue(RHS);
1346 bool RHSIsKill = hasTrivialKill(RHS);
1348 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1349 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1350 .addReg(LHSReg, getKillRegState(LHSIsKill))
1351 .addReg(RHSReg, getKillRegState(RHSIsKill));
1355 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
1356 bool SetFlags, bool WantResult, bool IsZExt) {
1357 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1361 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
1362 bool SetFlags, bool WantResult, bool IsZExt) {
1363 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1367 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1368 bool LHSIsKill, unsigned RHSReg,
1369 bool RHSIsKill, bool WantResult) {
1370 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1371 RHSIsKill, /*SetFlags=*/true, WantResult);
1374 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1375 bool LHSIsKill, unsigned RHSReg,
1377 AArch64_AM::ShiftExtendType ShiftType,
1378 uint64_t ShiftImm, bool WantResult) {
1379 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1380 RHSIsKill, ShiftType, ShiftImm, /*SetFlags=*/true,
1384 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
1385 const Value *LHS, const Value *RHS) {
1386 // Canonicalize immediates to the RHS first.
1387 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
1388 std::swap(LHS, RHS);
1390 // Canonicalize mul by power-of-2 to the RHS.
1391 if (LHS->hasOneUse() && isValueAvailable(LHS))
1392 if (isMulPowOf2(LHS))
1393 std::swap(LHS, RHS);
1395 // Canonicalize shift immediate to the RHS.
1396 if (LHS->hasOneUse() && isValueAvailable(LHS))
1397 if (const auto *SI = dyn_cast<ShlOperator>(LHS))
1398 if (isa<ConstantInt>(SI->getOperand(1)))
1399 std::swap(LHS, RHS);
1401 unsigned LHSReg = getRegForValue(LHS);
1404 bool LHSIsKill = hasTrivialKill(LHS);
1406 unsigned ResultReg = 0;
1407 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
1408 uint64_t Imm = C->getZExtValue();
1409 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
1414 // Check if the mul can be folded into the instruction.
1415 if (RHS->hasOneUse() && isValueAvailable(RHS))
1416 if (isMulPowOf2(RHS)) {
1417 const Value *MulLHS = cast<MulOperator>(RHS)->getOperand(0);
1418 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1);
1420 if (const auto *C = dyn_cast<ConstantInt>(MulLHS))
1421 if (C->getValue().isPowerOf2())
1422 std::swap(MulLHS, MulRHS);
1424 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt.");
1425 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
1427 unsigned RHSReg = getRegForValue(MulLHS);
1430 bool RHSIsKill = hasTrivialKill(MulLHS);
1431 return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1432 RHSIsKill, ShiftVal);
1435 // Check if the shift can be folded into the instruction.
1436 if (RHS->hasOneUse() && isValueAvailable(RHS))
1437 if (const auto *SI = dyn_cast<ShlOperator>(RHS))
1438 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1))) {
1439 uint64_t ShiftVal = C->getZExtValue();
1440 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1443 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1444 return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1445 RHSIsKill, ShiftVal);
1448 unsigned RHSReg = getRegForValue(RHS);
1451 bool RHSIsKill = hasTrivialKill(RHS);
1453 MVT VT = std::max(MVT::i32, RetVT.SimpleTy);
1454 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1455 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1456 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1457 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1462 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
1463 unsigned LHSReg, bool LHSIsKill,
1465 assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
1466 "ISD nodes are not consecutive!");
1467 static const unsigned OpcTable[3][2] = {
1468 { AArch64::ANDWri, AArch64::ANDXri },
1469 { AArch64::ORRWri, AArch64::ORRXri },
1470 { AArch64::EORWri, AArch64::EORXri }
1472 const TargetRegisterClass *RC;
1475 switch (RetVT.SimpleTy) {
1482 unsigned Idx = ISDOpc - ISD::AND;
1483 Opc = OpcTable[Idx][0];
1484 RC = &AArch64::GPR32spRegClass;
1489 Opc = OpcTable[ISDOpc - ISD::AND][1];
1490 RC = &AArch64::GPR64spRegClass;
1495 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
1498 unsigned ResultReg =
1499 fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,
1500 AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
1501 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1502 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1503 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1508 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
1509 unsigned LHSReg, bool LHSIsKill,
1510 unsigned RHSReg, bool RHSIsKill,
1511 uint64_t ShiftImm) {
1512 assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
1513 "ISD nodes are not consecutive!");
1514 static const unsigned OpcTable[3][2] = {
1515 { AArch64::ANDWrs, AArch64::ANDXrs },
1516 { AArch64::ORRWrs, AArch64::ORRXrs },
1517 { AArch64::EORWrs, AArch64::EORXrs }
1519 const TargetRegisterClass *RC;
1521 switch (RetVT.SimpleTy) {
1528 Opc = OpcTable[ISDOpc - ISD::AND][0];
1529 RC = &AArch64::GPR32RegClass;
1532 Opc = OpcTable[ISDOpc - ISD::AND][1];
1533 RC = &AArch64::GPR64RegClass;
1536 unsigned ResultReg =
1537 fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1538 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));
1539 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1540 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1541 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1546 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1548 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
1551 bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
1552 MachineMemOperand *MMO) {
1553 // Simplify this down to something we can handle.
1554 if (!simplifyAddress(Addr, VT))
1557 unsigned ScaleFactor;
1558 switch (VT.SimpleTy) {
1559 default: llvm_unreachable("Unexpected value type.");
1560 case MVT::i1: // fall-through
1561 case MVT::i8: ScaleFactor = 1; break;
1562 case MVT::i16: ScaleFactor = 2; break;
1563 case MVT::i32: // fall-through
1564 case MVT::f32: ScaleFactor = 4; break;
1565 case MVT::i64: // fall-through
1566 case MVT::f64: ScaleFactor = 8; break;
1569 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
1570 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
1571 bool UseScaled = true;
1572 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
1577 static const unsigned OpcTable[4][6] = {
1578 { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi, AArch64::LDURXi,
1579 AArch64::LDURSi, AArch64::LDURDi },
1580 { AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui, AArch64::LDRXui,
1581 AArch64::LDRSui, AArch64::LDRDui },
1582 { AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX, AArch64::LDRXroX,
1583 AArch64::LDRSroX, AArch64::LDRDroX },
1584 { AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW, AArch64::LDRXroW,
1585 AArch64::LDRSroW, AArch64::LDRDroW }
1589 const TargetRegisterClass *RC;
1590 bool VTIsi1 = false;
1591 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
1592 Addr.getOffsetReg();
1593 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
1594 if (Addr.getExtendType() == AArch64_AM::UXTW ||
1595 Addr.getExtendType() == AArch64_AM::SXTW)
1598 switch (VT.SimpleTy) {
1599 default: llvm_unreachable("Unexpected value type.");
1600 case MVT::i1: VTIsi1 = true; // Intentional fall-through.
1601 case MVT::i8: Opc = OpcTable[Idx][0]; RC = &AArch64::GPR32RegClass; break;
1602 case MVT::i16: Opc = OpcTable[Idx][1]; RC = &AArch64::GPR32RegClass; break;
1603 case MVT::i32: Opc = OpcTable[Idx][2]; RC = &AArch64::GPR32RegClass; break;
1604 case MVT::i64: Opc = OpcTable[Idx][3]; RC = &AArch64::GPR64RegClass; break;
1605 case MVT::f32: Opc = OpcTable[Idx][4]; RC = &AArch64::FPR32RegClass; break;
1606 case MVT::f64: Opc = OpcTable[Idx][5]; RC = &AArch64::FPR64RegClass; break;
1609 // Create the base instruction, then add the operands.
1610 ResultReg = createResultReg(RC);
1611 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1612 TII.get(Opc), ResultReg);
1613 addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
1615 // Loading an i1 requires special handling.
1617 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
1618 assert(ANDReg && "Unexpected AND instruction emission failure.");
1624 bool AArch64FastISel::selectAddSub(const Instruction *I) {
1626 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
1630 return selectOperator(I, I->getOpcode());
1633 switch (I->getOpcode()) {
1635 llvm_unreachable("Unexpected instruction.");
1636 case Instruction::Add:
1637 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
1639 case Instruction::Sub:
1640 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
1646 updateValueMap(I, ResultReg);
1650 bool AArch64FastISel::selectLogicalOp(const Instruction *I) {
1652 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
1656 return selectOperator(I, I->getOpcode());
1659 switch (I->getOpcode()) {
1661 llvm_unreachable("Unexpected instruction.");
1662 case Instruction::And:
1663 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
1665 case Instruction::Or:
1666 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
1668 case Instruction::Xor:
1669 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
1675 updateValueMap(I, ResultReg);
1679 bool AArch64FastISel::selectLoad(const Instruction *I) {
1681 // Verify we have a legal type before going any further. Currently, we handle
1682 // simple types that will directly fit in a register (i32/f32/i64/f64) or
1683 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
1684 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true) ||
1685 cast<LoadInst>(I)->isAtomic())
1688 // See if we can handle this address.
1690 if (!computeAddress(I->getOperand(0), Addr, I->getType()))
1694 if (!emitLoad(VT, ResultReg, Addr, createMachineMemOperandFor(I)))
1697 updateValueMap(I, ResultReg);
1701 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
1702 MachineMemOperand *MMO) {
1703 // Simplify this down to something we can handle.
1704 if (!simplifyAddress(Addr, VT))
1707 unsigned ScaleFactor;
1708 switch (VT.SimpleTy) {
1709 default: llvm_unreachable("Unexpected value type.");
1710 case MVT::i1: // fall-through
1711 case MVT::i8: ScaleFactor = 1; break;
1712 case MVT::i16: ScaleFactor = 2; break;
1713 case MVT::i32: // fall-through
1714 case MVT::f32: ScaleFactor = 4; break;
1715 case MVT::i64: // fall-through
1716 case MVT::f64: ScaleFactor = 8; break;
1719 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
1720 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
1721 bool UseScaled = true;
1722 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
1728 static const unsigned OpcTable[4][6] = {
1729 { AArch64::STURBBi, AArch64::STURHHi, AArch64::STURWi, AArch64::STURXi,
1730 AArch64::STURSi, AArch64::STURDi },
1731 { AArch64::STRBBui, AArch64::STRHHui, AArch64::STRWui, AArch64::STRXui,
1732 AArch64::STRSui, AArch64::STRDui },
1733 { AArch64::STRBBroX, AArch64::STRHHroX, AArch64::STRWroX, AArch64::STRXroX,
1734 AArch64::STRSroX, AArch64::STRDroX },
1735 { AArch64::STRBBroW, AArch64::STRHHroW, AArch64::STRWroW, AArch64::STRXroW,
1736 AArch64::STRSroW, AArch64::STRDroW }
1741 bool VTIsi1 = false;
1742 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
1743 Addr.getOffsetReg();
1744 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
1745 if (Addr.getExtendType() == AArch64_AM::UXTW ||
1746 Addr.getExtendType() == AArch64_AM::SXTW)
1749 switch (VT.SimpleTy) {
1750 default: llvm_unreachable("Unexpected value type.");
1751 case MVT::i1: VTIsi1 = true;
1752 case MVT::i8: Opc = OpcTable[Idx][0]; break;
1753 case MVT::i16: Opc = OpcTable[Idx][1]; break;
1754 case MVT::i32: Opc = OpcTable[Idx][2]; break;
1755 case MVT::i64: Opc = OpcTable[Idx][3]; break;
1756 case MVT::f32: Opc = OpcTable[Idx][4]; break;
1757 case MVT::f64: Opc = OpcTable[Idx][5]; break;
1760 // Storing an i1 requires special handling.
1761 if (VTIsi1 && SrcReg != AArch64::WZR) {
1762 unsigned ANDReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
1763 assert(ANDReg && "Unexpected AND instruction emission failure.");
1766 // Create the base instruction, then add the operands.
1767 const MCInstrDesc &II = TII.get(Opc);
1768 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
1769 MachineInstrBuilder MIB =
1770 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
1771 addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
1776 bool AArch64FastISel::selectStore(const Instruction *I) {
1778 const Value *Op0 = I->getOperand(0);
1779 // Verify we have a legal type before going any further. Currently, we handle
1780 // simple types that will directly fit in a register (i32/f32/i64/f64) or
1781 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
1782 if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true) ||
1783 cast<StoreInst>(I)->isAtomic())
1786 // Get the value to be stored into a register. Use the zero register directly
1787 // when possible to avoid an unnecessary copy and a wasted register.
1788 unsigned SrcReg = 0;
1789 if (const auto *CI = dyn_cast<ConstantInt>(Op0)) {
1791 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1792 } else if (const auto *CF = dyn_cast<ConstantFP>(Op0)) {
1793 if (CF->isZero() && !CF->isNegative()) {
1794 VT = MVT::getIntegerVT(VT.getSizeInBits());
1795 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1800 SrcReg = getRegForValue(Op0);
1805 // See if we can handle this address.
1807 if (!computeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
1810 if (!emitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
1815 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
1817 case CmpInst::FCMP_ONE:
1818 case CmpInst::FCMP_UEQ:
1820 // AL is our "false" for now. The other two need more compares.
1821 return AArch64CC::AL;
1822 case CmpInst::ICMP_EQ:
1823 case CmpInst::FCMP_OEQ:
1824 return AArch64CC::EQ;
1825 case CmpInst::ICMP_SGT:
1826 case CmpInst::FCMP_OGT:
1827 return AArch64CC::GT;
1828 case CmpInst::ICMP_SGE:
1829 case CmpInst::FCMP_OGE:
1830 return AArch64CC::GE;
1831 case CmpInst::ICMP_UGT:
1832 case CmpInst::FCMP_UGT:
1833 return AArch64CC::HI;
1834 case CmpInst::FCMP_OLT:
1835 return AArch64CC::MI;
1836 case CmpInst::ICMP_ULE:
1837 case CmpInst::FCMP_OLE:
1838 return AArch64CC::LS;
1839 case CmpInst::FCMP_ORD:
1840 return AArch64CC::VC;
1841 case CmpInst::FCMP_UNO:
1842 return AArch64CC::VS;
1843 case CmpInst::FCMP_UGE:
1844 return AArch64CC::PL;
1845 case CmpInst::ICMP_SLT:
1846 case CmpInst::FCMP_ULT:
1847 return AArch64CC::LT;
1848 case CmpInst::ICMP_SLE:
1849 case CmpInst::FCMP_ULE:
1850 return AArch64CC::LE;
1851 case CmpInst::FCMP_UNE:
1852 case CmpInst::ICMP_NE:
1853 return AArch64CC::NE;
1854 case CmpInst::ICMP_UGE:
1855 return AArch64CC::HS;
1856 case CmpInst::ICMP_ULT:
1857 return AArch64CC::LO;
1861 /// \brief Check if the comparison against zero and the following branch can be
1862 /// folded into a single instruction (CBZ or CBNZ).
1863 static bool canFoldZeroCheckIntoBranch(const CmpInst *CI) {
1864 CmpInst::Predicate Predicate = CI->getPredicate();
1865 if ((Predicate != CmpInst::ICMP_EQ) && (Predicate != CmpInst::ICMP_NE))
1868 Type *Ty = CI->getOperand(0)->getType();
1869 if (!Ty->isIntegerTy())
1872 unsigned BW = cast<IntegerType>(Ty)->getBitWidth();
1873 if (BW != 1 && BW != 8 && BW != 16 && BW != 32 && BW != 64)
1876 if (const auto *C = dyn_cast<ConstantInt>(CI->getOperand(0)))
1877 if (C->isNullValue())
1880 if (const auto *C = dyn_cast<ConstantInt>(CI->getOperand(1)))
1881 if (C->isNullValue())
1887 bool AArch64FastISel::selectBranch(const Instruction *I) {
1888 const BranchInst *BI = cast<BranchInst>(I);
1889 if (BI->isUnconditional()) {
1890 MachineBasicBlock *MSucc = FuncInfo.MBBMap[BI->getSuccessor(0)];
1891 fastEmitBranch(MSucc, BI->getDebugLoc());
1895 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1896 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1898 AArch64CC::CondCode CC = AArch64CC::NE;
1899 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1900 if (CI->hasOneUse() && isValueAvailable(CI)) {
1901 // Try to optimize or fold the cmp.
1902 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
1903 switch (Predicate) {
1906 case CmpInst::FCMP_FALSE:
1907 fastEmitBranch(FBB, DbgLoc);
1909 case CmpInst::FCMP_TRUE:
1910 fastEmitBranch(TBB, DbgLoc);
1914 // Try to take advantage of fallthrough opportunities.
1915 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1916 std::swap(TBB, FBB);
1917 Predicate = CmpInst::getInversePredicate(Predicate);
1920 // Try to optimize comparisons against zero.
1921 if (canFoldZeroCheckIntoBranch(CI)) {
1922 const Value *LHS = CI->getOperand(0);
1923 const Value *RHS = CI->getOperand(1);
1925 // Canonicalize zero values to the RHS.
1926 if (const auto *C = dyn_cast<ConstantInt>(LHS))
1927 if (C->isNullValue())
1928 std::swap(LHS, RHS);
1931 if (const auto *AI = dyn_cast<BinaryOperator>(LHS))
1932 if (AI->getOpcode() == Instruction::And) {
1933 const Value *AndLHS = AI->getOperand(0);
1934 const Value *AndRHS = AI->getOperand(1);
1936 if (const auto *C = dyn_cast<ConstantInt>(AndLHS))
1937 if (C->getValue().isPowerOf2())
1938 std::swap(AndLHS, AndRHS);
1940 if (const auto *C = dyn_cast<ConstantInt>(AndRHS))
1941 if (C->getValue().isPowerOf2()) {
1942 TestBit = C->getValue().logBase2();
1947 static const unsigned OpcTable[2][2][2] = {
1948 { {AArch64::CBZW, AArch64::CBZX },
1949 {AArch64::CBNZW, AArch64::CBNZX} },
1950 { {AArch64::TBZW, AArch64::TBZX },
1951 {AArch64::TBNZW, AArch64::TBNZX} }
1953 bool IsBitTest = TestBit != -1;
1954 bool IsCmpNE = Predicate == CmpInst::ICMP_NE;
1955 bool Is64Bit = LHS->getType()->isIntegerTy(64);
1956 unsigned Opc = OpcTable[IsBitTest][IsCmpNE][Is64Bit];
1958 unsigned SrcReg = getRegForValue(LHS);
1961 bool SrcIsKill = hasTrivialKill(LHS);
1963 // Emit the combined compare and branch instruction.
1964 MachineInstrBuilder MIB =
1965 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1966 .addReg(SrcReg, getKillRegState(SrcIsKill));
1968 MIB.addImm(TestBit);
1971 // Obtain the branch weight and add the TrueBB to the successor list.
1972 uint32_t BranchWeight = 0;
1974 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1975 TBB->getBasicBlock());
1976 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
1978 fastEmitBranch(FBB, DbgLoc);
1983 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1986 // FCMP_UEQ and FCMP_ONE cannot be checked with a single branch
1988 CC = getCompareCC(Predicate);
1989 AArch64CC::CondCode ExtraCC = AArch64CC::AL;
1990 switch (Predicate) {
1993 case CmpInst::FCMP_UEQ:
1994 ExtraCC = AArch64CC::EQ;
1997 case CmpInst::FCMP_ONE:
1998 ExtraCC = AArch64CC::MI;
2002 assert((CC != AArch64CC::AL) && "Unexpected condition code.");
2004 // Emit the extra branch for FCMP_UEQ and FCMP_ONE.
2005 if (ExtraCC != AArch64CC::AL) {
2006 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2012 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2016 // Obtain the branch weight and add the TrueBB to the successor list.
2017 uint32_t BranchWeight = 0;
2019 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2020 TBB->getBasicBlock());
2021 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
2023 fastEmitBranch(FBB, DbgLoc);
2026 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
2028 if (TI->hasOneUse() && isValueAvailable(TI) &&
2029 isTypeSupported(TI->getOperand(0)->getType(), SrcVT)) {
2030 unsigned CondReg = getRegForValue(TI->getOperand(0));
2033 bool CondIsKill = hasTrivialKill(TI->getOperand(0));
2035 // Issue an extract_subreg to get the lower 32-bits.
2036 if (SrcVT == MVT::i64) {
2037 CondReg = fastEmitInst_extractsubreg(MVT::i32, CondReg, CondIsKill,
2042 unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondIsKill, 1);
2043 assert(ANDReg && "Unexpected AND instruction emission failure.");
2044 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
2046 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2047 std::swap(TBB, FBB);
2050 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2054 // Obtain the branch weight and add the TrueBB to the successor list.
2055 uint32_t BranchWeight = 0;
2057 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2058 TBB->getBasicBlock());
2059 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
2061 fastEmitBranch(FBB, DbgLoc);
2064 } else if (const auto *CI = dyn_cast<ConstantInt>(BI->getCondition())) {
2065 uint64_t Imm = CI->getZExtValue();
2066 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
2067 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
2070 // Obtain the branch weight and add the target to the successor list.
2071 uint32_t BranchWeight = 0;
2073 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2074 Target->getBasicBlock());
2075 FuncInfo.MBB->addSuccessor(Target, BranchWeight);
2077 } else if (foldXALUIntrinsic(CC, I, BI->getCondition())) {
2078 // Fake request the condition, otherwise the intrinsic might be completely
2080 unsigned CondReg = getRegForValue(BI->getCondition());
2085 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2089 // Obtain the branch weight and add the TrueBB to the successor list.
2090 uint32_t BranchWeight = 0;
2092 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2093 TBB->getBasicBlock());
2094 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
2096 fastEmitBranch(FBB, DbgLoc);
2100 unsigned CondReg = getRegForValue(BI->getCondition());
2103 bool CondRegIsKill = hasTrivialKill(BI->getCondition());
2105 // We've been divorced from our compare! Our block was split, and
2106 // now our compare lives in a predecessor block. We musn't
2107 // re-compare here, as the children of the compare aren't guaranteed
2108 // live across the block boundary (we *could* check for this).
2109 // Regardless, the compare has been done in the predecessor block,
2110 // and it left a value for us in a virtual register. Ergo, we test
2111 // the one-bit value left in the virtual register.
2112 emitICmp_ri(MVT::i32, CondReg, CondRegIsKill, 0);
2114 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2115 std::swap(TBB, FBB);
2119 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2123 // Obtain the branch weight and add the TrueBB to the successor list.
2124 uint32_t BranchWeight = 0;
2126 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
2127 TBB->getBasicBlock());
2128 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
2130 fastEmitBranch(FBB, DbgLoc);
2134 bool AArch64FastISel::selectIndirectBr(const Instruction *I) {
2135 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
2136 unsigned AddrReg = getRegForValue(BI->getOperand(0));
2140 // Emit the indirect branch.
2141 const MCInstrDesc &II = TII.get(AArch64::BR);
2142 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs());
2143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
2145 // Make sure the CFG is up-to-date.
2146 for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
2147 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
2152 bool AArch64FastISel::selectCmp(const Instruction *I) {
2153 const CmpInst *CI = cast<CmpInst>(I);
2155 // Try to optimize or fold the cmp.
2156 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2157 unsigned ResultReg = 0;
2158 switch (Predicate) {
2161 case CmpInst::FCMP_FALSE:
2162 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2163 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2164 TII.get(TargetOpcode::COPY), ResultReg)
2165 .addReg(AArch64::WZR, getKillRegState(true));
2167 case CmpInst::FCMP_TRUE:
2168 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);
2173 updateValueMap(I, ResultReg);
2178 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
2181 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2183 // FCMP_UEQ and FCMP_ONE cannot be checked with a single instruction. These
2184 // condition codes are inverted, because they are used by CSINC.
2185 static unsigned CondCodeTable[2][2] = {
2186 { AArch64CC::NE, AArch64CC::VC },
2187 { AArch64CC::PL, AArch64CC::LE }
2189 unsigned *CondCodes = nullptr;
2190 switch (Predicate) {
2193 case CmpInst::FCMP_UEQ:
2194 CondCodes = &CondCodeTable[0][0];
2196 case CmpInst::FCMP_ONE:
2197 CondCodes = &CondCodeTable[1][0];
2202 unsigned TmpReg1 = createResultReg(&AArch64::GPR32RegClass);
2203 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2205 .addReg(AArch64::WZR, getKillRegState(true))
2206 .addReg(AArch64::WZR, getKillRegState(true))
2207 .addImm(CondCodes[0]);
2208 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2210 .addReg(TmpReg1, getKillRegState(true))
2211 .addReg(AArch64::WZR, getKillRegState(true))
2212 .addImm(CondCodes[1]);
2214 updateValueMap(I, ResultReg);
2218 // Now set a register based on the comparison.
2219 AArch64CC::CondCode CC = getCompareCC(Predicate);
2220 assert((CC != AArch64CC::AL) && "Unexpected condition code.");
2221 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
2222 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2224 .addReg(AArch64::WZR, getKillRegState(true))
2225 .addReg(AArch64::WZR, getKillRegState(true))
2226 .addImm(invertedCC);
2228 updateValueMap(I, ResultReg);
2232 bool AArch64FastISel::selectSelect(const Instruction *I) {
2233 const SelectInst *SI = cast<SelectInst>(I);
2235 EVT DestEVT = TLI.getValueType(SI->getType(), true);
2236 if (!DestEVT.isSimple())
2239 MVT DestVT = DestEVT.getSimpleVT();
2240 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
2245 const TargetRegisterClass *RC = nullptr;
2246 switch (DestVT.SimpleTy) {
2247 default: return false;
2249 SelectOpc = AArch64::CSELWr; RC = &AArch64::GPR32RegClass; break;
2251 SelectOpc = AArch64::CSELXr; RC = &AArch64::GPR64RegClass; break;
2253 SelectOpc = AArch64::FCSELSrrr; RC = &AArch64::FPR32RegClass; break;
2255 SelectOpc = AArch64::FCSELDrrr; RC = &AArch64::FPR64RegClass; break;
2258 const Value *Cond = SI->getCondition();
2259 bool NeedTest = true;
2260 AArch64CC::CondCode CC = AArch64CC::NE;
2261 if (foldXALUIntrinsic(CC, I, Cond))
2264 unsigned CondReg = getRegForValue(Cond);
2267 bool CondIsKill = hasTrivialKill(Cond);
2270 unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondIsKill, 1);
2271 assert(ANDReg && "Unexpected AND instruction emission failure.");
2272 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
2275 unsigned TrueReg = getRegForValue(SI->getTrueValue());
2276 bool TrueIsKill = hasTrivialKill(SI->getTrueValue());
2278 unsigned FalseReg = getRegForValue(SI->getFalseValue());
2279 bool FalseIsKill = hasTrivialKill(SI->getFalseValue());
2281 if (!TrueReg || !FalseReg)
2284 unsigned ResultReg = fastEmitInst_rri(SelectOpc, RC, TrueReg, TrueIsKill,
2285 FalseReg, FalseIsKill, CC);
2286 updateValueMap(I, ResultReg);
2290 bool AArch64FastISel::selectFPExt(const Instruction *I) {
2291 Value *V = I->getOperand(0);
2292 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
2295 unsigned Op = getRegForValue(V);
2299 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
2300 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
2301 ResultReg).addReg(Op);
2302 updateValueMap(I, ResultReg);
2306 bool AArch64FastISel::selectFPTrunc(const Instruction *I) {
2307 Value *V = I->getOperand(0);
2308 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
2311 unsigned Op = getRegForValue(V);
2315 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
2316 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
2317 ResultReg).addReg(Op);
2318 updateValueMap(I, ResultReg);
2322 // FPToUI and FPToSI
2323 bool AArch64FastISel::selectFPToInt(const Instruction *I, bool Signed) {
2325 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2328 unsigned SrcReg = getRegForValue(I->getOperand(0));
2332 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
2333 if (SrcVT == MVT::f128)
2337 if (SrcVT == MVT::f64) {
2339 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2341 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2344 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2346 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2348 unsigned ResultReg = createResultReg(
2349 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
2350 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2352 updateValueMap(I, ResultReg);
2356 bool AArch64FastISel::selectIntToFP(const Instruction *I, bool Signed) {
2358 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2360 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2361 "Unexpected value type.");
2363 unsigned SrcReg = getRegForValue(I->getOperand(0));
2366 bool SrcIsKill = hasTrivialKill(I->getOperand(0));
2368 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
2370 // Handle sign-extension.
2371 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
2373 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
2380 if (SrcVT == MVT::i64) {
2382 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2384 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2387 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2389 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
2392 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
2394 updateValueMap(I, ResultReg);
2398 bool AArch64FastISel::fastLowerArguments() {
2399 if (!FuncInfo.CanLowerReturn)
2402 const Function *F = FuncInfo.Fn;
2406 CallingConv::ID CC = F->getCallingConv();
2407 if (CC != CallingConv::C)
2410 // Only handle simple cases of up to 8 GPR and FPR each.
2411 unsigned GPRCnt = 0;
2412 unsigned FPRCnt = 0;
2414 for (auto const &Arg : F->args()) {
2415 // The first argument is at index 1.
2417 if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
2418 F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
2419 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
2420 F->getAttributes().hasAttribute(Idx, Attribute::Nest))
2423 Type *ArgTy = Arg.getType();
2424 if (ArgTy->isStructTy() || ArgTy->isArrayTy())
2427 EVT ArgVT = TLI.getValueType(ArgTy);
2428 if (!ArgVT.isSimple())
2431 MVT VT = ArgVT.getSimpleVT().SimpleTy;
2432 if (VT.isFloatingPoint() && !Subtarget->hasFPARMv8())
2435 if (VT.isVector() &&
2436 (!Subtarget->hasNEON() || !Subtarget->isLittleEndian()))
2439 if (VT >= MVT::i1 && VT <= MVT::i64)
2441 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() ||
2442 VT.is128BitVector())
2447 if (GPRCnt > 8 || FPRCnt > 8)
2451 static const MCPhysReg Registers[6][8] = {
2452 { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
2453 AArch64::W5, AArch64::W6, AArch64::W7 },
2454 { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
2455 AArch64::X5, AArch64::X6, AArch64::X7 },
2456 { AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
2457 AArch64::H5, AArch64::H6, AArch64::H7 },
2458 { AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
2459 AArch64::S5, AArch64::S6, AArch64::S7 },
2460 { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
2461 AArch64::D5, AArch64::D6, AArch64::D7 },
2462 { AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
2463 AArch64::Q5, AArch64::Q6, AArch64::Q7 }
2466 unsigned GPRIdx = 0;
2467 unsigned FPRIdx = 0;
2468 for (auto const &Arg : F->args()) {
2469 MVT VT = TLI.getSimpleValueType(Arg.getType());
2471 const TargetRegisterClass *RC;
2472 if (VT >= MVT::i1 && VT <= MVT::i32) {
2473 SrcReg = Registers[0][GPRIdx++];
2474 RC = &AArch64::GPR32RegClass;
2476 } else if (VT == MVT::i64) {
2477 SrcReg = Registers[1][GPRIdx++];
2478 RC = &AArch64::GPR64RegClass;
2479 } else if (VT == MVT::f16) {
2480 SrcReg = Registers[2][FPRIdx++];
2481 RC = &AArch64::FPR16RegClass;
2482 } else if (VT == MVT::f32) {
2483 SrcReg = Registers[3][FPRIdx++];
2484 RC = &AArch64::FPR32RegClass;
2485 } else if ((VT == MVT::f64) || VT.is64BitVector()) {
2486 SrcReg = Registers[4][FPRIdx++];
2487 RC = &AArch64::FPR64RegClass;
2488 } else if (VT.is128BitVector()) {
2489 SrcReg = Registers[5][FPRIdx++];
2490 RC = &AArch64::FPR128RegClass;
2492 llvm_unreachable("Unexpected value type.");
2494 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
2495 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
2496 // Without this, EmitLiveInCopies may eliminate the livein if its only
2497 // use is a bitcast (which isn't turned into an instruction).
2498 unsigned ResultReg = createResultReg(RC);
2499 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2500 TII.get(TargetOpcode::COPY), ResultReg)
2501 .addReg(DstReg, getKillRegState(true));
2502 updateValueMap(&Arg, ResultReg);
2507 bool AArch64FastISel::processCallArgs(CallLoweringInfo &CLI,
2508 SmallVectorImpl<MVT> &OutVTs,
2509 unsigned &NumBytes) {
2510 CallingConv::ID CC = CLI.CallConv;
2511 SmallVector<CCValAssign, 16> ArgLocs;
2512 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
2513 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
2515 // Get a count of how many bytes are to be pushed on the stack.
2516 NumBytes = CCInfo.getNextStackOffset();
2518 // Issue CALLSEQ_START
2519 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2520 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
2523 // Process the args.
2524 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2525 CCValAssign &VA = ArgLocs[i];
2526 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
2527 MVT ArgVT = OutVTs[VA.getValNo()];
2529 unsigned ArgReg = getRegForValue(ArgVal);
2533 // Handle arg promotion: SExt, ZExt, AExt.
2534 switch (VA.getLocInfo()) {
2535 case CCValAssign::Full:
2537 case CCValAssign::SExt: {
2538 MVT DestVT = VA.getLocVT();
2540 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
2545 case CCValAssign::AExt:
2546 // Intentional fall-through.
2547 case CCValAssign::ZExt: {
2548 MVT DestVT = VA.getLocVT();
2550 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
2556 llvm_unreachable("Unknown arg promotion!");
2559 // Now copy/store arg to correct locations.
2560 if (VA.isRegLoc() && !VA.needsCustom()) {
2561 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2562 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
2563 CLI.OutRegs.push_back(VA.getLocReg());
2564 } else if (VA.needsCustom()) {
2565 // FIXME: Handle custom args.
2568 assert(VA.isMemLoc() && "Assuming store on stack.");
2570 // Don't emit stores for undef values.
2571 if (isa<UndefValue>(ArgVal))
2574 // Need to store on the stack.
2575 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
2577 unsigned BEAlign = 0;
2578 if (ArgSize < 8 && !Subtarget->isLittleEndian())
2579 BEAlign = 8 - ArgSize;
2582 Addr.setKind(Address::RegBase);
2583 Addr.setReg(AArch64::SP);
2584 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
2586 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
2587 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2588 MachinePointerInfo::getStack(Addr.getOffset()),
2589 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
2591 if (!emitStore(ArgVT, ArgReg, Addr, MMO))
2598 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
2599 unsigned NumBytes) {
2600 CallingConv::ID CC = CLI.CallConv;
2602 // Issue CALLSEQ_END
2603 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2604 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
2605 .addImm(NumBytes).addImm(0);
2607 // Now the return value.
2608 if (RetVT != MVT::isVoid) {
2609 SmallVector<CCValAssign, 16> RVLocs;
2610 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2611 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
2613 // Only handle a single return value.
2614 if (RVLocs.size() != 1)
2617 // Copy all of the result registers out of their specified physreg.
2618 MVT CopyVT = RVLocs[0].getValVT();
2619 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
2620 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2621 TII.get(TargetOpcode::COPY), ResultReg)
2622 .addReg(RVLocs[0].getLocReg());
2623 CLI.InRegs.push_back(RVLocs[0].getLocReg());
2625 CLI.ResultReg = ResultReg;
2626 CLI.NumResultRegs = 1;
2632 bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
2633 CallingConv::ID CC = CLI.CallConv;
2634 bool IsTailCall = CLI.IsTailCall;
2635 bool IsVarArg = CLI.IsVarArg;
2636 const Value *Callee = CLI.Callee;
2637 const char *SymName = CLI.SymName;
2639 if (!Callee && !SymName)
2642 // Allow SelectionDAG isel to handle tail calls.
2646 CodeModel::Model CM = TM.getCodeModel();
2647 // Only support the small and large code model.
2648 if (CM != CodeModel::Small && CM != CodeModel::Large)
2651 // FIXME: Add large code model support for ELF.
2652 if (CM == CodeModel::Large && !Subtarget->isTargetMachO())
2655 // Let SDISel handle vararg functions.
2659 // FIXME: Only handle *simple* calls for now.
2661 if (CLI.RetTy->isVoidTy())
2662 RetVT = MVT::isVoid;
2663 else if (!isTypeLegal(CLI.RetTy, RetVT))
2666 for (auto Flag : CLI.OutFlags)
2667 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
2670 // Set up the argument vectors.
2671 SmallVector<MVT, 16> OutVTs;
2672 OutVTs.reserve(CLI.OutVals.size());
2674 for (auto *Val : CLI.OutVals) {
2676 if (!isTypeLegal(Val->getType(), VT) &&
2677 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
2680 // We don't handle vector parameters yet.
2681 if (VT.isVector() || VT.getSizeInBits() > 64)
2684 OutVTs.push_back(VT);
2688 if (Callee && !computeCallAddress(Callee, Addr))
2691 // Handle the arguments now that we've gotten them.
2693 if (!processCallArgs(CLI, OutVTs, NumBytes))
2697 MachineInstrBuilder MIB;
2698 if (CM == CodeModel::Small) {
2699 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
2700 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
2702 MIB.addExternalSymbol(SymName, 0);
2703 else if (Addr.getGlobalValue())
2704 MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
2705 else if (Addr.getReg()) {
2706 unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);
2711 unsigned CallReg = 0;
2713 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
2714 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
2716 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGE);
2718 CallReg = createResultReg(&AArch64::GPR64RegClass);
2719 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
2722 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
2724 } else if (Addr.getGlobalValue())
2725 CallReg = materializeGV(Addr.getGlobalValue());
2726 else if (Addr.getReg())
2727 CallReg = Addr.getReg();
2732 const MCInstrDesc &II = TII.get(AArch64::BLR);
2733 CallReg = constrainOperandRegClass(II, CallReg, 0);
2734 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
2737 // Add implicit physical register uses to the call.
2738 for (auto Reg : CLI.OutRegs)
2739 MIB.addReg(Reg, RegState::Implicit);
2741 // Add a register mask with the call-preserved registers.
2742 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2743 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2747 // Finish off the call including any return values.
2748 return finishCall(CLI, RetVT, NumBytes);
2751 bool AArch64FastISel::isMemCpySmall(uint64_t Len, unsigned Alignment) {
2753 return Len / Alignment <= 4;
2758 bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,
2759 uint64_t Len, unsigned Alignment) {
2760 // Make sure we don't bloat code by inlining very large memcpy's.
2761 if (!isMemCpySmall(Len, Alignment))
2764 int64_t UnscaledOffset = 0;
2765 Address OrigDest = Dest;
2766 Address OrigSrc = Src;
2770 if (!Alignment || Alignment >= 8) {
2781 // Bound based on alignment.
2782 if (Len >= 4 && Alignment == 4)
2784 else if (Len >= 2 && Alignment == 2)
2793 RV = emitLoad(VT, ResultReg, Src);
2797 RV = emitStore(VT, ResultReg, Dest);
2801 int64_t Size = VT.getSizeInBits() / 8;
2803 UnscaledOffset += Size;
2805 // We need to recompute the unscaled offset for each iteration.
2806 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
2807 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
2813 /// \brief Check if it is possible to fold the condition from the XALU intrinsic
2814 /// into the user. The condition code will only be updated on success.
2815 bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode &CC,
2816 const Instruction *I,
2817 const Value *Cond) {
2818 if (!isa<ExtractValueInst>(Cond))
2821 const auto *EV = cast<ExtractValueInst>(Cond);
2822 if (!isa<IntrinsicInst>(EV->getAggregateOperand()))
2825 const auto *II = cast<IntrinsicInst>(EV->getAggregateOperand());
2827 const Function *Callee = II->getCalledFunction();
2829 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0U);
2830 if (!isTypeLegal(RetTy, RetVT))
2833 if (RetVT != MVT::i32 && RetVT != MVT::i64)
2836 AArch64CC::CondCode TmpCC;
2837 switch (II->getIntrinsicID()) {
2838 default: return false;
2839 case Intrinsic::sadd_with_overflow:
2840 case Intrinsic::ssub_with_overflow: TmpCC = AArch64CC::VS; break;
2841 case Intrinsic::uadd_with_overflow: TmpCC = AArch64CC::HS; break;
2842 case Intrinsic::usub_with_overflow: TmpCC = AArch64CC::LO; break;
2843 case Intrinsic::smul_with_overflow:
2844 case Intrinsic::umul_with_overflow: TmpCC = AArch64CC::NE; break;
2847 // Check if both instructions are in the same basic block.
2848 if (!isValueAvailable(II))
2851 // Make sure nothing is in the way
2852 BasicBlock::const_iterator Start = I;
2853 BasicBlock::const_iterator End = II;
2854 for (auto Itr = std::prev(Start); Itr != End; --Itr) {
2855 // We only expect extractvalue instructions between the intrinsic and the
2856 // instruction to be selected.
2857 if (!isa<ExtractValueInst>(Itr))
2860 // Check that the extractvalue operand comes from the intrinsic.
2861 const auto *EVI = cast<ExtractValueInst>(Itr);
2862 if (EVI->getAggregateOperand() != II)
2870 bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
2871 // FIXME: Handle more intrinsics.
2872 switch (II->getIntrinsicID()) {
2873 default: return false;
2874 case Intrinsic::frameaddress: {
2875 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2876 MFI->setFrameAddressIsTaken(true);
2878 const AArch64RegisterInfo *RegInfo =
2879 static_cast<const AArch64RegisterInfo *>(
2880 TM.getSubtargetImpl()->getRegisterInfo());
2881 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2882 unsigned SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2883 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2884 TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
2885 // Recursively load frame address
2891 unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
2893 DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,
2894 SrcReg, /*IsKill=*/true, 0);
2895 assert(DestReg && "Unexpected LDR instruction emission failure.");
2899 updateValueMap(II, SrcReg);
2902 case Intrinsic::memcpy:
2903 case Intrinsic::memmove: {
2904 const auto *MTI = cast<MemTransferInst>(II);
2905 // Don't handle volatile.
2906 if (MTI->isVolatile())
2909 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2910 // we would emit dead code because we don't currently handle memmoves.
2911 bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
2912 if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
2913 // Small memcpy's are common enough that we want to do them without a call
2915 uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
2916 unsigned Alignment = MTI->getAlignment();
2917 if (isMemCpySmall(Len, Alignment)) {
2919 if (!computeAddress(MTI->getRawDest(), Dest) ||
2920 !computeAddress(MTI->getRawSource(), Src))
2922 if (tryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2927 if (!MTI->getLength()->getType()->isIntegerTy(64))
2930 if (MTI->getSourceAddressSpace() > 255 || MTI->getDestAddressSpace() > 255)
2931 // Fast instruction selection doesn't support the special
2935 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
2936 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
2938 case Intrinsic::memset: {
2939 const MemSetInst *MSI = cast<MemSetInst>(II);
2940 // Don't handle volatile.
2941 if (MSI->isVolatile())
2944 if (!MSI->getLength()->getType()->isIntegerTy(64))
2947 if (MSI->getDestAddressSpace() > 255)
2948 // Fast instruction selection doesn't support the special
2952 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
2954 case Intrinsic::sin:
2955 case Intrinsic::cos:
2956 case Intrinsic::pow: {
2958 if (!isTypeLegal(II->getType(), RetVT))
2961 if (RetVT != MVT::f32 && RetVT != MVT::f64)
2964 static const RTLIB::Libcall LibCallTable[3][2] = {
2965 { RTLIB::SIN_F32, RTLIB::SIN_F64 },
2966 { RTLIB::COS_F32, RTLIB::COS_F64 },
2967 { RTLIB::POW_F32, RTLIB::POW_F64 }
2970 bool Is64Bit = RetVT == MVT::f64;
2971 switch (II->getIntrinsicID()) {
2973 llvm_unreachable("Unexpected intrinsic.");
2974 case Intrinsic::sin:
2975 LC = LibCallTable[0][Is64Bit];
2977 case Intrinsic::cos:
2978 LC = LibCallTable[1][Is64Bit];
2980 case Intrinsic::pow:
2981 LC = LibCallTable[2][Is64Bit];
2986 Args.reserve(II->getNumArgOperands());
2988 // Populate the argument list.
2989 for (auto &Arg : II->arg_operands()) {
2992 Entry.Ty = Arg->getType();
2993 Args.push_back(Entry);
2996 CallLoweringInfo CLI;
2997 CLI.setCallee(TLI.getLibcallCallingConv(LC), II->getType(),
2998 TLI.getLibcallName(LC), std::move(Args));
2999 if (!lowerCallTo(CLI))
3001 updateValueMap(II, CLI.ResultReg);
3004 case Intrinsic::trap: {
3005 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
3009 case Intrinsic::sqrt: {
3010 Type *RetTy = II->getCalledFunction()->getReturnType();
3013 if (!isTypeLegal(RetTy, VT))
3016 unsigned Op0Reg = getRegForValue(II->getOperand(0));
3019 bool Op0IsKill = hasTrivialKill(II->getOperand(0));
3021 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
3025 updateValueMap(II, ResultReg);
3028 case Intrinsic::sadd_with_overflow:
3029 case Intrinsic::uadd_with_overflow:
3030 case Intrinsic::ssub_with_overflow:
3031 case Intrinsic::usub_with_overflow:
3032 case Intrinsic::smul_with_overflow:
3033 case Intrinsic::umul_with_overflow: {
3034 // This implements the basic lowering of the xalu with overflow intrinsics.
3035 const Function *Callee = II->getCalledFunction();
3036 auto *Ty = cast<StructType>(Callee->getReturnType());
3037 Type *RetTy = Ty->getTypeAtIndex(0U);
3040 if (!isTypeLegal(RetTy, VT))
3043 if (VT != MVT::i32 && VT != MVT::i64)
3046 const Value *LHS = II->getArgOperand(0);
3047 const Value *RHS = II->getArgOperand(1);
3048 // Canonicalize immediate to the RHS.
3049 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
3050 isCommutativeIntrinsic(II))
3051 std::swap(LHS, RHS);
3053 unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0;
3054 AArch64CC::CondCode CC = AArch64CC::Invalid;
3055 switch (II->getIntrinsicID()) {
3056 default: llvm_unreachable("Unexpected intrinsic!");
3057 case Intrinsic::sadd_with_overflow:
3058 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3061 case Intrinsic::uadd_with_overflow:
3062 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3065 case Intrinsic::ssub_with_overflow:
3066 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3069 case Intrinsic::usub_with_overflow:
3070 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3073 case Intrinsic::smul_with_overflow: {
3075 unsigned LHSReg = getRegForValue(LHS);
3078 bool LHSIsKill = hasTrivialKill(LHS);
3080 unsigned RHSReg = getRegForValue(RHS);
3083 bool RHSIsKill = hasTrivialKill(RHS);
3085 if (VT == MVT::i32) {
3086 MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3087 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg,
3088 /*IsKill=*/false, 32);
3089 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
3091 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true,
3093 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
3094 AArch64_AM::ASR, 31, /*WantResult=*/false);
3096 assert(VT == MVT::i64 && "Unexpected value type.");
3097 MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3098 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
3100 emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
3101 AArch64_AM::ASR, 63, /*WantResult=*/false);
3105 case Intrinsic::umul_with_overflow: {
3107 unsigned LHSReg = getRegForValue(LHS);
3110 bool LHSIsKill = hasTrivialKill(LHS);
3112 unsigned RHSReg = getRegForValue(RHS);
3115 bool RHSIsKill = hasTrivialKill(RHS);
3117 if (VT == MVT::i32) {
3118 MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3119 emitSubs_rs(MVT::i64, AArch64::XZR, /*IsKill=*/true, MulReg,
3120 /*IsKill=*/false, AArch64_AM::LSR, 32,
3121 /*WantResult=*/false);
3122 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
3125 assert(VT == MVT::i64 && "Unexpected value type.");
3126 MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3127 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
3129 emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,
3130 /*IsKill=*/false, /*WantResult=*/false);
3137 ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
3138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3139 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
3142 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
3143 AArch64::WZR, /*IsKill=*/true, AArch64::WZR,
3144 /*IsKill=*/true, getInvertedCondCode(CC));
3145 assert((ResultReg1 + 1) == ResultReg2 &&
3146 "Nonconsecutive result registers.");
3147 updateValueMap(II, ResultReg1, 2);
3154 bool AArch64FastISel::selectRet(const Instruction *I) {
3155 const ReturnInst *Ret = cast<ReturnInst>(I);
3156 const Function &F = *I->getParent()->getParent();
3158 if (!FuncInfo.CanLowerReturn)
3164 // Build a list of return value registers.
3165 SmallVector<unsigned, 4> RetRegs;
3167 if (Ret->getNumOperands() > 0) {
3168 CallingConv::ID CC = F.getCallingConv();
3169 SmallVector<ISD::OutputArg, 4> Outs;
3170 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
3172 // Analyze operands of the call, assigning locations to each operand.
3173 SmallVector<CCValAssign, 16> ValLocs;
3174 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
3175 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
3176 : RetCC_AArch64_AAPCS;
3177 CCInfo.AnalyzeReturn(Outs, RetCC);
3179 // Only handle a single return value for now.
3180 if (ValLocs.size() != 1)
3183 CCValAssign &VA = ValLocs[0];
3184 const Value *RV = Ret->getOperand(0);
3186 // Don't bother handling odd stuff for now.
3187 if ((VA.getLocInfo() != CCValAssign::Full) &&
3188 (VA.getLocInfo() != CCValAssign::BCvt))
3191 // Only handle register returns for now.
3195 unsigned Reg = getRegForValue(RV);
3199 unsigned SrcReg = Reg + VA.getValNo();
3200 unsigned DestReg = VA.getLocReg();
3201 // Avoid a cross-class copy. This is very unlikely.
3202 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
3205 EVT RVEVT = TLI.getValueType(RV->getType());
3206 if (!RVEVT.isSimple())
3209 // Vectors (of > 1 lane) in big endian need tricky handling.
3210 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1 &&
3211 !Subtarget->isLittleEndian())
3214 MVT RVVT = RVEVT.getSimpleVT();
3215 if (RVVT == MVT::f128)
3218 MVT DestVT = VA.getValVT();
3219 // Special handling for extended integers.
3220 if (RVVT != DestVT) {
3221 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
3224 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
3227 bool IsZExt = Outs[0].Flags.isZExt();
3228 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
3234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3235 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
3237 // Add register to return instruction.
3238 RetRegs.push_back(VA.getLocReg());
3241 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3242 TII.get(AArch64::RET_ReallyLR));
3243 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
3244 MIB.addReg(RetRegs[i], RegState::Implicit);
3248 bool AArch64FastISel::selectTrunc(const Instruction *I) {
3249 Type *DestTy = I->getType();
3250 Value *Op = I->getOperand(0);
3251 Type *SrcTy = Op->getType();
3253 EVT SrcEVT = TLI.getValueType(SrcTy, true);
3254 EVT DestEVT = TLI.getValueType(DestTy, true);
3255 if (!SrcEVT.isSimple())
3257 if (!DestEVT.isSimple())
3260 MVT SrcVT = SrcEVT.getSimpleVT();
3261 MVT DestVT = DestEVT.getSimpleVT();
3263 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
3266 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
3270 unsigned SrcReg = getRegForValue(Op);
3273 bool SrcIsKill = hasTrivialKill(Op);
3275 // If we're truncating from i64 to a smaller non-legal type then generate an
3276 // AND. Otherwise, we know the high bits are undefined and a truncate only
3277 // generate a COPY. We cannot mark the source register also as result
3278 // register, because this can incorrectly transfer the kill flag onto the
3281 if (SrcVT == MVT::i64) {
3283 switch (DestVT.SimpleTy) {
3285 // Trunc i64 to i32 is handled by the target-independent fast-isel.
3297 // Issue an extract_subreg to get the lower 32-bits.
3298 unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
3300 // Create the AND instruction which performs the actual truncation.
3301 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
3302 assert(ResultReg && "Unexpected AND instruction emission failure.");
3304 ResultReg = createResultReg(&AArch64::GPR32RegClass);
3305 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3306 TII.get(TargetOpcode::COPY), ResultReg)
3307 .addReg(SrcReg, getKillRegState(SrcIsKill));
3310 updateValueMap(I, ResultReg);
3314 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
3315 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
3316 DestVT == MVT::i64) &&
3317 "Unexpected value type.");
3318 // Handle i8 and i16 as i32.
3319 if (DestVT == MVT::i8 || DestVT == MVT::i16)
3323 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
3324 assert(ResultReg && "Unexpected AND instruction emission failure.");
3325 if (DestVT == MVT::i64) {
3326 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
3327 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
3328 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3329 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3330 TII.get(AArch64::SUBREG_TO_REG), Reg64)
3333 .addImm(AArch64::sub_32);
3338 if (DestVT == MVT::i64) {
3339 // FIXME: We're SExt i1 to i64.
3342 return fastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg,
3343 /*TODO:IsKill=*/false, 0, 0);
3347 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3348 unsigned Op1, bool Op1IsKill) {
3350 switch (RetVT.SimpleTy) {
3356 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break;
3358 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
3361 const TargetRegisterClass *RC =
3362 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3363 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
3364 /*IsKill=*/ZReg, true);
3367 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3368 unsigned Op1, bool Op1IsKill) {
3369 if (RetVT != MVT::i64)
3372 return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,
3373 Op0, Op0IsKill, Op1, Op1IsKill,
3374 AArch64::XZR, /*IsKill=*/true);
3377 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3378 unsigned Op1, bool Op1IsKill) {
3379 if (RetVT != MVT::i64)
3382 return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,
3383 Op0, Op0IsKill, Op1, Op1IsKill,
3384 AArch64::XZR, /*IsKill=*/true);
3387 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3388 unsigned Op1Reg, bool Op1IsKill) {
3390 bool NeedTrunc = false;
3392 switch (RetVT.SimpleTy) {
3394 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break;
3395 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break;
3396 case MVT::i32: Opc = AArch64::LSLVWr; break;
3397 case MVT::i64: Opc = AArch64::LSLVXr; break;
3400 const TargetRegisterClass *RC =
3401 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3403 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3406 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3409 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3413 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3414 bool Op0IsKill, uint64_t Shift,
3416 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3417 "Unexpected source/return type pair.");
3418 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
3419 SrcVT == MVT::i64) && "Unexpected source value type.");
3420 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3421 RetVT == MVT::i64) && "Unexpected return value type.");
3423 bool Is64Bit = (RetVT == MVT::i64);
3424 unsigned RegSize = Is64Bit ? 64 : 32;
3425 unsigned DstBits = RetVT.getSizeInBits();
3426 unsigned SrcBits = SrcVT.getSizeInBits();
3428 // Don't deal with undefined shifts.
3429 if (Shift >= DstBits)
3432 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3433 // {S|U}BFM Wd, Wn, #r, #s
3434 // Wd<32+s-r,32-r> = Wn<s:0> when r > s
3436 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3437 // %2 = shl i16 %1, 4
3438 // Wd<32+7-28,32-28> = Wn<7:0> <- clamp s to 7
3439 // 0b1111_1111_1111_1111__1111_1010_1010_0000 sext
3440 // 0b0000_0000_0000_0000__0000_0101_0101_0000 sext | zext
3441 // 0b0000_0000_0000_0000__0000_1010_1010_0000 zext
3443 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3444 // %2 = shl i16 %1, 8
3445 // Wd<32+7-24,32-24> = Wn<7:0>
3446 // 0b1111_1111_1111_1111__1010_1010_0000_0000 sext
3447 // 0b0000_0000_0000_0000__0101_0101_0000_0000 sext | zext
3448 // 0b0000_0000_0000_0000__1010_1010_0000_0000 zext
3450 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3451 // %2 = shl i16 %1, 12
3452 // Wd<32+3-20,32-20> = Wn<3:0>
3453 // 0b1111_1111_1111_1111__1010_0000_0000_0000 sext
3454 // 0b0000_0000_0000_0000__0101_0000_0000_0000 sext | zext
3455 // 0b0000_0000_0000_0000__1010_0000_0000_0000 zext
3457 unsigned ImmR = RegSize - Shift;
3458 // Limit the width to the length of the source type.
3459 unsigned ImmS = std::min<unsigned>(SrcBits - 1, DstBits - 1 - Shift);
3460 static const unsigned OpcTable[2][2] = {
3461 {AArch64::SBFMWri, AArch64::SBFMXri},
3462 {AArch64::UBFMWri, AArch64::UBFMXri}
3464 unsigned Opc = OpcTable[IsZext][Is64Bit];
3465 const TargetRegisterClass *RC =
3466 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3467 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3468 unsigned TmpReg = MRI.createVirtualRegister(RC);
3469 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3470 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3472 .addReg(Op0, getKillRegState(Op0IsKill))
3473 .addImm(AArch64::sub_32);
3477 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3480 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3481 unsigned Op1Reg, bool Op1IsKill) {
3483 bool NeedTrunc = false;
3485 switch (RetVT.SimpleTy) {
3487 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
3488 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break;
3489 case MVT::i32: Opc = AArch64::LSRVWr; break;
3490 case MVT::i64: Opc = AArch64::LSRVXr; break;
3493 const TargetRegisterClass *RC =
3494 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3496 Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
3497 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3498 Op0IsKill = Op1IsKill = true;
3500 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3503 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3507 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3508 bool Op0IsKill, uint64_t Shift,
3510 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3511 "Unexpected source/return type pair.");
3512 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
3513 SrcVT == MVT::i64) && "Unexpected source value type.");
3514 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3515 RetVT == MVT::i64) && "Unexpected return value type.");
3517 bool Is64Bit = (RetVT == MVT::i64);
3518 unsigned RegSize = Is64Bit ? 64 : 32;
3519 unsigned DstBits = RetVT.getSizeInBits();
3520 unsigned SrcBits = SrcVT.getSizeInBits();
3522 // Don't deal with undefined shifts.
3523 if (Shift >= DstBits)
3526 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3527 // {S|U}BFM Wd, Wn, #r, #s
3528 // Wd<s-r:0> = Wn<s:r> when r <= s
3530 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3531 // %2 = lshr i16 %1, 4
3532 // Wd<7-4:0> = Wn<7:4>
3533 // 0b0000_0000_0000_0000__0000_1111_1111_1010 sext
3534 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
3535 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
3537 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3538 // %2 = lshr i16 %1, 8
3539 // Wd<7-7,0> = Wn<7:7>
3540 // 0b0000_0000_0000_0000__0000_0000_1111_1111 sext
3541 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3542 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3544 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3545 // %2 = lshr i16 %1, 12
3546 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
3547 // 0b0000_0000_0000_0000__0000_0000_0000_1111 sext
3548 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3549 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3551 if (Shift >= SrcBits && IsZExt)
3552 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
3554 // It is not possible to fold a sign-extend into the LShr instruction. In this
3555 // case emit a sign-extend.
3557 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
3562 SrcBits = SrcVT.getSizeInBits();
3566 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
3567 unsigned ImmS = SrcBits - 1;
3568 static const unsigned OpcTable[2][2] = {
3569 {AArch64::SBFMWri, AArch64::SBFMXri},
3570 {AArch64::UBFMWri, AArch64::UBFMXri}
3572 unsigned Opc = OpcTable[IsZExt][Is64Bit];
3573 const TargetRegisterClass *RC =
3574 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3575 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3576 unsigned TmpReg = MRI.createVirtualRegister(RC);
3577 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3578 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3580 .addReg(Op0, getKillRegState(Op0IsKill))
3581 .addImm(AArch64::sub_32);
3585 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3588 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3589 unsigned Op1Reg, bool Op1IsKill) {
3591 bool NeedTrunc = false;
3593 switch (RetVT.SimpleTy) {
3595 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break;
3596 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break;
3597 case MVT::i32: Opc = AArch64::ASRVWr; break;
3598 case MVT::i64: Opc = AArch64::ASRVXr; break;
3601 const TargetRegisterClass *RC =
3602 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3604 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
3605 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3606 Op0IsKill = Op1IsKill = true;
3608 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3611 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3615 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3616 bool Op0IsKill, uint64_t Shift,
3618 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3619 "Unexpected source/return type pair.");
3620 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
3621 SrcVT == MVT::i64) && "Unexpected source value type.");
3622 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3623 RetVT == MVT::i64) && "Unexpected return value type.");
3625 bool Is64Bit = (RetVT == MVT::i64);
3626 unsigned RegSize = Is64Bit ? 64 : 32;
3627 unsigned DstBits = RetVT.getSizeInBits();
3628 unsigned SrcBits = SrcVT.getSizeInBits();
3630 // Don't deal with undefined shifts.
3631 if (Shift >= DstBits)
3634 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3635 // {S|U}BFM Wd, Wn, #r, #s
3636 // Wd<s-r:0> = Wn<s:r> when r <= s
3638 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3639 // %2 = ashr i16 %1, 4
3640 // Wd<7-4:0> = Wn<7:4>
3641 // 0b1111_1111_1111_1111__1111_1111_1111_1010 sext
3642 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
3643 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
3645 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3646 // %2 = ashr i16 %1, 8
3647 // Wd<7-7,0> = Wn<7:7>
3648 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
3649 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3650 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3652 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3653 // %2 = ashr i16 %1, 12
3654 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
3655 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
3656 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3657 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3659 if (Shift >= SrcBits && IsZExt)
3660 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
3662 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
3663 unsigned ImmS = SrcBits - 1;
3664 static const unsigned OpcTable[2][2] = {
3665 {AArch64::SBFMWri, AArch64::SBFMXri},
3666 {AArch64::UBFMWri, AArch64::UBFMXri}
3668 unsigned Opc = OpcTable[IsZExt][Is64Bit];
3669 const TargetRegisterClass *RC =
3670 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3671 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3672 unsigned TmpReg = MRI.createVirtualRegister(RC);
3673 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3674 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3676 .addReg(Op0, getKillRegState(Op0IsKill))
3677 .addImm(AArch64::sub_32);
3681 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3684 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
3686 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
3688 // FastISel does not have plumbing to deal with extensions where the SrcVT or
3689 // DestVT are odd things, so test to make sure that they are both types we can
3690 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
3691 // bail out to SelectionDAG.
3692 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
3693 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
3694 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
3695 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
3701 switch (SrcVT.SimpleTy) {
3705 return emiti1Ext(SrcReg, DestVT, IsZExt);
3707 if (DestVT == MVT::i64)
3708 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
3710 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
3714 if (DestVT == MVT::i64)
3715 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
3717 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
3721 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
3722 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
3727 // Handle i8 and i16 as i32.
3728 if (DestVT == MVT::i8 || DestVT == MVT::i16)
3730 else if (DestVT == MVT::i64) {
3731 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3732 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3733 TII.get(AArch64::SUBREG_TO_REG), Src64)
3736 .addImm(AArch64::sub_32);
3740 const TargetRegisterClass *RC =
3741 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3742 return fastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
3745 bool AArch64FastISel::selectIntExt(const Instruction *I) {
3746 // On ARM, in general, integer casts don't involve legal types; this code
3747 // handles promotable integers. The high bits for a type smaller than
3748 // the register size are assumed to be undefined.
3749 Type *DestTy = I->getType();
3750 Value *Src = I->getOperand(0);
3751 Type *SrcTy = Src->getType();
3753 unsigned SrcReg = getRegForValue(Src);
3757 EVT SrcEVT = TLI.getValueType(SrcTy, true);
3758 EVT DestEVT = TLI.getValueType(DestTy, true);
3759 if (!SrcEVT.isSimple())
3761 if (!DestEVT.isSimple())
3764 MVT SrcVT = SrcEVT.getSimpleVT();
3765 MVT DestVT = DestEVT.getSimpleVT();
3766 unsigned ResultReg = 0;
3768 bool IsZExt = isa<ZExtInst>(I);
3769 // Check if it is an argument and if it is already zero/sign-extended.
3770 if (const auto *Arg = dyn_cast<Argument>(Src)) {
3771 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
3772 if (DestVT == MVT::i64) {
3773 ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
3774 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3775 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
3778 .addImm(AArch64::sub_32);
3785 ResultReg = emitIntExt(SrcVT, SrcReg, DestVT, IsZExt);
3790 updateValueMap(I, ResultReg);
3794 bool AArch64FastISel::selectRem(const Instruction *I, unsigned ISDOpcode) {
3795 EVT DestEVT = TLI.getValueType(I->getType(), true);
3796 if (!DestEVT.isSimple())
3799 MVT DestVT = DestEVT.getSimpleVT();
3800 if (DestVT != MVT::i64 && DestVT != MVT::i32)
3804 bool Is64bit = (DestVT == MVT::i64);
3805 switch (ISDOpcode) {
3809 DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
3812 DivOpc = Is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
3815 unsigned MSubOpc = Is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
3816 unsigned Src0Reg = getRegForValue(I->getOperand(0));
3819 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
3821 unsigned Src1Reg = getRegForValue(I->getOperand(1));
3824 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
3826 const TargetRegisterClass *RC =
3827 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3828 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false,
3829 Src1Reg, /*IsKill=*/false);
3830 assert(QuotReg && "Unexpected DIV instruction emission failure.");
3831 // The remainder is computed as numerator - (quotient * denominator) using the
3832 // MSUB instruction.
3833 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,
3834 Src1Reg, Src1IsKill, Src0Reg,
3836 updateValueMap(I, ResultReg);
3840 bool AArch64FastISel::selectMul(const Instruction *I) {
3842 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
3846 return selectBinaryOp(I, ISD::MUL);
3848 const Value *Src0 = I->getOperand(0);
3849 const Value *Src1 = I->getOperand(1);
3850 if (const auto *C = dyn_cast<ConstantInt>(Src0))
3851 if (C->getValue().isPowerOf2())
3852 std::swap(Src0, Src1);
3854 // Try to simplify to a shift instruction.
3855 if (const auto *C = dyn_cast<ConstantInt>(Src1))
3856 if (C->getValue().isPowerOf2()) {
3857 uint64_t ShiftVal = C->getValue().logBase2();
3860 if (const auto *ZExt = dyn_cast<ZExtInst>(Src0)) {
3862 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), VT)) {
3865 Src0 = ZExt->getOperand(0);
3867 } else if (const auto *SExt = dyn_cast<SExtInst>(Src0)) {
3869 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) {
3872 Src0 = SExt->getOperand(0);
3876 unsigned Src0Reg = getRegForValue(Src0);
3879 bool Src0IsKill = hasTrivialKill(Src0);
3881 unsigned ResultReg =
3882 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt);
3885 updateValueMap(I, ResultReg);
3890 unsigned Src0Reg = getRegForValue(I->getOperand(0));
3893 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
3895 unsigned Src1Reg = getRegForValue(I->getOperand(1));
3898 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
3900 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
3905 updateValueMap(I, ResultReg);
3909 bool AArch64FastISel::selectShift(const Instruction *I) {
3911 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
3914 if (RetVT.isVector())
3915 return selectOperator(I, I->getOpcode());
3917 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
3918 unsigned ResultReg = 0;
3919 uint64_t ShiftVal = C->getZExtValue();
3921 bool IsZExt = (I->getOpcode() == Instruction::AShr) ? false : true;
3922 const Value *Op0 = I->getOperand(0);
3923 if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
3925 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), TmpVT)) {
3928 Op0 = ZExt->getOperand(0);
3930 } else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) {
3932 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), TmpVT)) {
3935 Op0 = SExt->getOperand(0);
3939 unsigned Op0Reg = getRegForValue(Op0);
3942 bool Op0IsKill = hasTrivialKill(Op0);
3944 switch (I->getOpcode()) {
3945 default: llvm_unreachable("Unexpected instruction.");
3946 case Instruction::Shl:
3947 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
3949 case Instruction::AShr:
3950 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
3952 case Instruction::LShr:
3953 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
3959 updateValueMap(I, ResultReg);
3963 unsigned Op0Reg = getRegForValue(I->getOperand(0));
3966 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
3968 unsigned Op1Reg = getRegForValue(I->getOperand(1));
3971 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
3973 unsigned ResultReg = 0;
3974 switch (I->getOpcode()) {
3975 default: llvm_unreachable("Unexpected instruction.");
3976 case Instruction::Shl:
3977 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
3979 case Instruction::AShr:
3980 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
3982 case Instruction::LShr:
3983 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
3990 updateValueMap(I, ResultReg);
3994 bool AArch64FastISel::selectBitCast(const Instruction *I) {
3997 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
3999 if (!isTypeLegal(I->getType(), RetVT))
4003 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4004 Opc = AArch64::FMOVWSr;
4005 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4006 Opc = AArch64::FMOVXDr;
4007 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4008 Opc = AArch64::FMOVSWr;
4009 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
4010 Opc = AArch64::FMOVDXr;
4014 const TargetRegisterClass *RC = nullptr;
4015 switch (RetVT.SimpleTy) {
4016 default: llvm_unreachable("Unexpected value type.");
4017 case MVT::i32: RC = &AArch64::GPR32RegClass; break;
4018 case MVT::i64: RC = &AArch64::GPR64RegClass; break;
4019 case MVT::f32: RC = &AArch64::FPR32RegClass; break;
4020 case MVT::f64: RC = &AArch64::FPR64RegClass; break;
4022 unsigned Op0Reg = getRegForValue(I->getOperand(0));
4025 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
4026 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);
4031 updateValueMap(I, ResultReg);
4035 bool AArch64FastISel::selectFRem(const Instruction *I) {
4037 if (!isTypeLegal(I->getType(), RetVT))
4041 switch (RetVT.SimpleTy) {
4045 LC = RTLIB::REM_F32;
4048 LC = RTLIB::REM_F64;
4053 Args.reserve(I->getNumOperands());
4055 // Populate the argument list.
4056 for (auto &Arg : I->operands()) {
4059 Entry.Ty = Arg->getType();
4060 Args.push_back(Entry);
4063 CallLoweringInfo CLI;
4064 CLI.setCallee(TLI.getLibcallCallingConv(LC), I->getType(),
4065 TLI.getLibcallName(LC), std::move(Args));
4066 if (!lowerCallTo(CLI))
4068 updateValueMap(I, CLI.ResultReg);
4072 bool AArch64FastISel::selectSDiv(const Instruction *I) {
4074 if (!isTypeLegal(I->getType(), VT))
4077 if (!isa<ConstantInt>(I->getOperand(1)))
4078 return selectBinaryOp(I, ISD::SDIV);
4080 const APInt &C = cast<ConstantInt>(I->getOperand(1))->getValue();
4081 if ((VT != MVT::i32 && VT != MVT::i64) || !C ||
4082 !(C.isPowerOf2() || (-C).isPowerOf2()))
4083 return selectBinaryOp(I, ISD::SDIV);
4085 unsigned Lg2 = C.countTrailingZeros();
4086 unsigned Src0Reg = getRegForValue(I->getOperand(0));
4089 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
4091 if (cast<BinaryOperator>(I)->isExact()) {
4092 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2);
4095 updateValueMap(I, ResultReg);
4099 unsigned Pow2MinusOne = (1 << Lg2) - 1;
4100 unsigned AddReg = emitAddSub_ri(/*UseAdd=*/true, VT, Src0Reg,
4101 /*IsKill=*/false, Pow2MinusOne);
4105 // (Src0 < 0) ? Pow2 - 1 : 0;
4106 if (!emitICmp_ri(VT, Src0Reg, /*IsKill=*/false, 0))
4110 const TargetRegisterClass *RC;
4111 if (VT == MVT::i64) {
4112 SelectOpc = AArch64::CSELXr;
4113 RC = &AArch64::GPR64RegClass;
4115 SelectOpc = AArch64::CSELWr;
4116 RC = &AArch64::GPR32RegClass;
4118 unsigned SelectReg =
4119 fastEmitInst_rri(SelectOpc, RC, AddReg, /*IsKill=*/true, Src0Reg,
4120 Src0IsKill, AArch64CC::LT);
4124 // Divide by Pow2 --> ashr. If we're dividing by a negative value we must also
4125 // negate the result.
4126 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
4129 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true,
4130 SelectReg, /*IsKill=*/true, AArch64_AM::ASR, Lg2);
4132 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2);
4137 updateValueMap(I, ResultReg);
4141 bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
4142 switch (I->getOpcode()) {
4145 case Instruction::Add:
4146 case Instruction::Sub:
4147 return selectAddSub(I);
4148 case Instruction::Mul:
4149 return selectMul(I);
4150 case Instruction::SDiv:
4151 return selectSDiv(I);
4152 case Instruction::SRem:
4153 if (!selectBinaryOp(I, ISD::SREM))
4154 return selectRem(I, ISD::SREM);
4156 case Instruction::URem:
4157 if (!selectBinaryOp(I, ISD::UREM))
4158 return selectRem(I, ISD::UREM);
4160 case Instruction::Shl:
4161 case Instruction::LShr:
4162 case Instruction::AShr:
4163 return selectShift(I);
4164 case Instruction::And:
4165 case Instruction::Or:
4166 case Instruction::Xor:
4167 return selectLogicalOp(I);
4168 case Instruction::Br:
4169 return selectBranch(I);
4170 case Instruction::IndirectBr:
4171 return selectIndirectBr(I);
4172 case Instruction::BitCast:
4173 if (!FastISel::selectBitCast(I))
4174 return selectBitCast(I);
4176 case Instruction::FPToSI:
4177 if (!selectCast(I, ISD::FP_TO_SINT))
4178 return selectFPToInt(I, /*Signed=*/true);
4180 case Instruction::FPToUI:
4181 return selectFPToInt(I, /*Signed=*/false);
4182 case Instruction::ZExt:
4183 if (!selectCast(I, ISD::ZERO_EXTEND))
4184 return selectIntExt(I);
4186 case Instruction::SExt:
4187 if (!selectCast(I, ISD::SIGN_EXTEND))
4188 return selectIntExt(I);
4190 case Instruction::Trunc:
4191 if (!selectCast(I, ISD::TRUNCATE))
4192 return selectTrunc(I);
4194 case Instruction::FPExt:
4195 return selectFPExt(I);
4196 case Instruction::FPTrunc:
4197 return selectFPTrunc(I);
4198 case Instruction::SIToFP:
4199 if (!selectCast(I, ISD::SINT_TO_FP))
4200 return selectIntToFP(I, /*Signed=*/true);
4202 case Instruction::UIToFP:
4203 return selectIntToFP(I, /*Signed=*/false);
4204 case Instruction::Load:
4205 return selectLoad(I);
4206 case Instruction::Store:
4207 return selectStore(I);
4208 case Instruction::FCmp:
4209 case Instruction::ICmp:
4210 return selectCmp(I);
4211 case Instruction::Select:
4212 return selectSelect(I);
4213 case Instruction::Ret:
4214 return selectRet(I);
4215 case Instruction::FRem:
4216 return selectFRem(I);
4219 // fall-back to target-independent instruction selection.
4220 return selectOperator(I, I->getOpcode());
4221 // Silence warnings.
4222 (void)&CC_AArch64_DarwinPCS_VarArg;
4226 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &FuncInfo,
4227 const TargetLibraryInfo *LibInfo) {
4228 return new AArch64FastISel(FuncInfo, LibInfo);