1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GetElementPtrTypeIterator.h"
32 #include "llvm/IR/GlobalAlias.h"
33 #include "llvm/IR/GlobalVariable.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Operator.h"
37 #include "llvm/Support/CommandLine.h"
42 class AArch64FastISel : public FastISel {
60 Address() : Kind(RegBase), Offset(0) { Base.Reg = 0; }
61 void setKind(BaseKind K) { Kind = K; }
62 BaseKind getKind() const { return Kind; }
63 bool isRegBase() const { return Kind == RegBase; }
64 bool isFIBase() const { return Kind == FrameIndexBase; }
65 void setReg(unsigned Reg) {
66 assert(isRegBase() && "Invalid base register access!");
69 unsigned getReg() const {
70 assert(isRegBase() && "Invalid base register access!");
73 void setFI(unsigned FI) {
74 assert(isFIBase() && "Invalid base frame index access!");
77 unsigned getFI() const {
78 assert(isFIBase() && "Invalid base frame index access!");
81 void setOffset(int64_t O) { Offset = O; }
82 int64_t getOffset() { return Offset; }
84 bool isValid() { return isFIBase() || (isRegBase() && getReg() != 0); }
87 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
88 /// make the right decision when generating code for different targets.
89 const AArch64Subtarget *Subtarget;
92 bool FastLowerCall(CallLoweringInfo &CLI) override;
93 bool FastLowerIntrinsicCall(const IntrinsicInst *II) override;
96 // Selection routines.
97 bool SelectLoad(const Instruction *I);
98 bool SelectStore(const Instruction *I);
99 bool SelectBranch(const Instruction *I);
100 bool SelectIndirectBr(const Instruction *I);
101 bool SelectCmp(const Instruction *I);
102 bool SelectSelect(const Instruction *I);
103 bool SelectFPExt(const Instruction *I);
104 bool SelectFPTrunc(const Instruction *I);
105 bool SelectFPToInt(const Instruction *I, bool Signed);
106 bool SelectIntToFP(const Instruction *I, bool Signed);
107 bool SelectRem(const Instruction *I, unsigned ISDOpcode);
108 bool SelectRet(const Instruction *I);
109 bool SelectTrunc(const Instruction *I);
110 bool SelectIntExt(const Instruction *I);
111 bool SelectMul(const Instruction *I);
112 bool SelectShift(const Instruction *I, bool IsLeftShift, bool IsArithmetic);
114 // Utility helper routines.
115 bool isTypeLegal(Type *Ty, MVT &VT);
116 bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
117 bool ComputeAddress(const Value *Obj, Address &Addr);
118 bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
120 void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
121 unsigned Flags, bool UseUnscaled);
122 bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
123 bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
126 bool EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt);
127 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
128 bool UseUnscaled = false);
129 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
130 bool UseUnscaled = false);
131 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
132 unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
133 unsigned Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
134 unsigned Op1, bool Op1IsKill);
135 unsigned Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
136 unsigned Op1, bool Op1IsKill);
137 unsigned Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
138 unsigned Op1, bool Op1IsKill);
139 unsigned Emit_LSL_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t Imm);
140 unsigned Emit_LSR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t Imm);
141 unsigned Emit_ASR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t Imm);
143 unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
144 unsigned AArch64MaterializeGV(const GlobalValue *GV);
146 // Call handling routines.
148 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
149 bool ProcessCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
151 bool FinishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
154 // Backend specific FastISel code.
155 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
156 unsigned TargetMaterializeConstant(const Constant *C) override;
158 explicit AArch64FastISel(FunctionLoweringInfo &funcInfo,
159 const TargetLibraryInfo *libInfo)
160 : FastISel(funcInfo, libInfo) {
161 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
162 Context = &funcInfo.Fn->getContext();
165 bool TargetSelectInstruction(const Instruction *I) override;
167 #include "AArch64GenFastISel.inc"
170 } // end anonymous namespace
172 #include "AArch64GenCallingConv.inc"
174 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
175 if (CC == CallingConv::WebKit_JS)
176 return CC_AArch64_WebKit_JS;
177 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
180 unsigned AArch64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
181 assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
182 "Alloca should always return a pointer.");
184 // Don't handle dynamic allocas.
185 if (!FuncInfo.StaticAllocaMap.count(AI))
188 DenseMap<const AllocaInst *, int>::iterator SI =
189 FuncInfo.StaticAllocaMap.find(AI);
191 if (SI != FuncInfo.StaticAllocaMap.end()) {
192 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
193 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
195 .addFrameIndex(SI->second)
204 unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
205 if (VT != MVT::f32 && VT != MVT::f64)
208 const APFloat Val = CFP->getValueAPF();
209 bool is64bit = (VT == MVT::f64);
211 // This checks to see if we can use FMOV instructions to materialize
212 // a constant, otherwise we have to materialize via the constant pool.
213 if (TLI.isFPImmLegal(Val, VT)) {
217 Imm = AArch64_AM::getFP64Imm(Val);
218 Opc = AArch64::FMOVDi;
220 Imm = AArch64_AM::getFP32Imm(Val);
221 Opc = AArch64::FMOVSi;
223 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
224 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
229 // Materialize via constant pool. MachineConstantPool wants an explicit
231 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
233 Align = DL.getTypeAllocSize(CFP->getType());
235 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
236 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
237 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
238 ADRPReg).addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGE);
240 unsigned Opc = is64bit ? AArch64::LDRDui : AArch64::LDRSui;
241 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
242 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
244 .addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
248 unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
249 // We can't handle thread-local variables quickly yet.
250 if (GV->isThreadLocal())
253 // MachO still uses GOT for large code-model accesses, but ELF requires
254 // movz/movk sequences, which FastISel doesn't handle yet.
255 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
258 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
260 EVT DestEVT = TLI.getValueType(GV->getType(), true);
261 if (!DestEVT.isSimple())
264 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
267 if (OpFlags & AArch64II::MO_GOT) {
269 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
271 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
273 ResultReg = createResultReg(&AArch64::GPR64RegClass);
274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
277 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
281 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
282 ADRPReg).addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
284 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
285 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
288 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
294 unsigned AArch64FastISel::TargetMaterializeConstant(const Constant *C) {
295 EVT CEVT = TLI.getValueType(C->getType(), true);
297 // Only handle simple types.
298 if (!CEVT.isSimple())
300 MVT VT = CEVT.getSimpleVT();
302 // FIXME: Handle ConstantInt.
303 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
304 return AArch64MaterializeFP(CFP, VT);
305 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
306 return AArch64MaterializeGV(GV);
311 // Computes the address to get to an object.
312 bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr) {
313 const User *U = nullptr;
314 unsigned Opcode = Instruction::UserOp1;
315 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
316 // Don't walk into other basic blocks unless the object is an alloca from
317 // another block, otherwise it may not have a virtual register assigned.
318 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
319 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
320 Opcode = I->getOpcode();
323 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
324 Opcode = C->getOpcode();
328 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
329 if (Ty->getAddressSpace() > 255)
330 // Fast instruction selection doesn't support the special
337 case Instruction::BitCast: {
338 // Look through bitcasts.
339 return ComputeAddress(U->getOperand(0), Addr);
341 case Instruction::IntToPtr: {
342 // Look past no-op inttoptrs.
343 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
344 return ComputeAddress(U->getOperand(0), Addr);
347 case Instruction::PtrToInt: {
348 // Look past no-op ptrtoints.
349 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
350 return ComputeAddress(U->getOperand(0), Addr);
353 case Instruction::GetElementPtr: {
354 Address SavedAddr = Addr;
355 uint64_t TmpOffset = Addr.getOffset();
357 // Iterate through the GEP folding the constants into offsets where
359 gep_type_iterator GTI = gep_type_begin(U);
360 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
362 const Value *Op = *i;
363 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
364 const StructLayout *SL = DL.getStructLayout(STy);
365 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
366 TmpOffset += SL->getElementOffset(Idx);
368 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
370 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
371 // Constant-offset addressing.
372 TmpOffset += CI->getSExtValue() * S;
375 if (canFoldAddIntoGEP(U, Op)) {
376 // A compatible add with a constant operand. Fold the constant.
378 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
379 TmpOffset += CI->getSExtValue() * S;
380 // Iterate on the other operand.
381 Op = cast<AddOperator>(Op)->getOperand(0);
385 goto unsupported_gep;
390 // Try to grab the base operand now.
391 Addr.setOffset(TmpOffset);
392 if (ComputeAddress(U->getOperand(0), Addr))
395 // We failed, restore everything and try the other options.
401 case Instruction::Alloca: {
402 const AllocaInst *AI = cast<AllocaInst>(Obj);
403 DenseMap<const AllocaInst *, int>::iterator SI =
404 FuncInfo.StaticAllocaMap.find(AI);
405 if (SI != FuncInfo.StaticAllocaMap.end()) {
406 Addr.setKind(Address::FrameIndexBase);
407 Addr.setFI(SI->second);
414 // Try to get this in a register if nothing else has worked.
416 Addr.setReg(getRegForValue(Obj));
417 return Addr.isValid();
420 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
421 EVT evt = TLI.getValueType(Ty, true);
423 // Only handle simple types.
424 if (evt == MVT::Other || !evt.isSimple())
426 VT = evt.getSimpleVT();
428 // This is a legal type, but it's not something we handle in fast-isel.
432 // Handle all other legal types, i.e. a register that will directly hold this
434 return TLI.isTypeLegal(VT);
437 bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
438 if (isTypeLegal(Ty, VT))
441 // If this is a type than can be sign or zero-extended to a basic operation
442 // go ahead and accept it now. For stores, this reflects truncation.
443 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
449 bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT,
450 int64_t ScaleFactor, bool UseUnscaled) {
451 bool needsLowering = false;
452 int64_t Offset = Addr.getOffset();
453 switch (VT.SimpleTy) {
464 // Using scaled, 12-bit, unsigned immediate offsets.
465 needsLowering = ((Offset & 0xfff) != Offset);
467 // Using unscaled, 9-bit, signed immediate offsets.
468 needsLowering = (Offset > 256 || Offset < -256);
472 //If this is a stack pointer and the offset needs to be simplified then put
473 // the alloca address into a register, set the base type back to register and
474 // continue. This should almost never happen.
475 if (needsLowering && Addr.getKind() == Address::FrameIndexBase) {
476 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
477 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
479 .addFrameIndex(Addr.getFI())
482 Addr.setKind(Address::RegBase);
483 Addr.setReg(ResultReg);
486 // Since the offset is too large for the load/store instruction get the
487 // reg+offset into a register.
489 uint64_t UnscaledOffset = Addr.getOffset() * ScaleFactor;
490 unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
491 UnscaledOffset, MVT::i64);
494 Addr.setReg(ResultReg);
500 void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
501 const MachineInstrBuilder &MIB,
502 unsigned Flags, bool UseUnscaled) {
503 int64_t Offset = Addr.getOffset();
504 // Frame base works a bit differently. Handle it separately.
505 if (Addr.getKind() == Address::FrameIndexBase) {
506 int FI = Addr.getFI();
507 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
508 // and alignment should be based on the VT.
509 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
510 MachinePointerInfo::getFixedStack(FI, Offset), Flags,
511 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
512 // Now add the rest of the operands.
513 MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
515 // Now add the rest of the operands.
516 MIB.addReg(Addr.getReg());
521 bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
523 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
524 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
525 if (!UseUnscaled && Addr.getOffset() < 0)
529 const TargetRegisterClass *RC;
531 int64_t ScaleFactor = 0;
532 switch (VT.SimpleTy) {
537 // Intentional fall-through.
539 Opc = UseUnscaled ? AArch64::LDURBBi : AArch64::LDRBBui;
540 RC = &AArch64::GPR32RegClass;
544 Opc = UseUnscaled ? AArch64::LDURHHi : AArch64::LDRHHui;
545 RC = &AArch64::GPR32RegClass;
549 Opc = UseUnscaled ? AArch64::LDURWi : AArch64::LDRWui;
550 RC = &AArch64::GPR32RegClass;
554 Opc = UseUnscaled ? AArch64::LDURXi : AArch64::LDRXui;
555 RC = &AArch64::GPR64RegClass;
559 Opc = UseUnscaled ? AArch64::LDURSi : AArch64::LDRSui;
560 RC = TLI.getRegClassFor(VT);
564 Opc = UseUnscaled ? AArch64::LDURDi : AArch64::LDRDui;
565 RC = TLI.getRegClassFor(VT);
571 int64_t Offset = Addr.getOffset();
572 if (Offset & (ScaleFactor - 1))
573 // Retry using an unscaled, 9-bit, signed immediate offset.
574 return EmitLoad(VT, ResultReg, Addr, /*UseUnscaled*/ true);
576 Addr.setOffset(Offset / ScaleFactor);
579 // Simplify this down to something we can handle.
580 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
583 // Create the base instruction, then add the operands.
584 ResultReg = createResultReg(RC);
585 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
586 TII.get(Opc), ResultReg);
587 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, UseUnscaled);
589 // Loading an i1 requires special handling.
591 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
592 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
593 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
596 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
602 bool AArch64FastISel::SelectLoad(const Instruction *I) {
604 // Verify we have a legal type before going any further. Currently, we handle
605 // simple types that will directly fit in a register (i32/f32/i64/f64) or
606 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
607 if (!isLoadStoreTypeLegal(I->getType(), VT) || cast<LoadInst>(I)->isAtomic())
610 // See if we can handle this address.
612 if (!ComputeAddress(I->getOperand(0), Addr))
616 if (!EmitLoad(VT, ResultReg, Addr))
619 UpdateValueMap(I, ResultReg);
623 bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
625 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
626 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
627 if (!UseUnscaled && Addr.getOffset() < 0)
632 int64_t ScaleFactor = 0;
633 // Using scaled, 12-bit, unsigned immediate offsets.
634 switch (VT.SimpleTy) {
640 StrOpc = UseUnscaled ? AArch64::STURBBi : AArch64::STRBBui;
644 StrOpc = UseUnscaled ? AArch64::STURHHi : AArch64::STRHHui;
648 StrOpc = UseUnscaled ? AArch64::STURWi : AArch64::STRWui;
652 StrOpc = UseUnscaled ? AArch64::STURXi : AArch64::STRXui;
656 StrOpc = UseUnscaled ? AArch64::STURSi : AArch64::STRSui;
660 StrOpc = UseUnscaled ? AArch64::STURDi : AArch64::STRDui;
666 int64_t Offset = Addr.getOffset();
667 if (Offset & (ScaleFactor - 1))
668 // Retry using an unscaled, 9-bit, signed immediate offset.
669 return EmitStore(VT, SrcReg, Addr, /*UseUnscaled*/ true);
671 Addr.setOffset(Offset / ScaleFactor);
674 // Simplify this down to something we can handle.
675 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
678 // Storing an i1 requires special handling.
680 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
681 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
682 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
685 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
688 // Create the base instruction, then add the operands.
689 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
690 TII.get(StrOpc)).addReg(SrcReg);
691 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, UseUnscaled);
695 bool AArch64FastISel::SelectStore(const Instruction *I) {
697 Value *Op0 = I->getOperand(0);
698 // Verify we have a legal type before going any further. Currently, we handle
699 // simple types that will directly fit in a register (i32/f32/i64/f64) or
700 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
701 if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
702 cast<StoreInst>(I)->isAtomic())
705 // Get the value to be stored into a register.
706 unsigned SrcReg = getRegForValue(Op0);
710 // See if we can handle this address.
712 if (!ComputeAddress(I->getOperand(1), Addr))
715 if (!EmitStore(VT, SrcReg, Addr))
720 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
722 case CmpInst::FCMP_ONE:
723 case CmpInst::FCMP_UEQ:
725 // AL is our "false" for now. The other two need more compares.
726 return AArch64CC::AL;
727 case CmpInst::ICMP_EQ:
728 case CmpInst::FCMP_OEQ:
729 return AArch64CC::EQ;
730 case CmpInst::ICMP_SGT:
731 case CmpInst::FCMP_OGT:
732 return AArch64CC::GT;
733 case CmpInst::ICMP_SGE:
734 case CmpInst::FCMP_OGE:
735 return AArch64CC::GE;
736 case CmpInst::ICMP_UGT:
737 case CmpInst::FCMP_UGT:
738 return AArch64CC::HI;
739 case CmpInst::FCMP_OLT:
740 return AArch64CC::MI;
741 case CmpInst::ICMP_ULE:
742 case CmpInst::FCMP_OLE:
743 return AArch64CC::LS;
744 case CmpInst::FCMP_ORD:
745 return AArch64CC::VC;
746 case CmpInst::FCMP_UNO:
747 return AArch64CC::VS;
748 case CmpInst::FCMP_UGE:
749 return AArch64CC::PL;
750 case CmpInst::ICMP_SLT:
751 case CmpInst::FCMP_ULT:
752 return AArch64CC::LT;
753 case CmpInst::ICMP_SLE:
754 case CmpInst::FCMP_ULE:
755 return AArch64CC::LE;
756 case CmpInst::FCMP_UNE:
757 case CmpInst::ICMP_NE:
758 return AArch64CC::NE;
759 case CmpInst::ICMP_UGE:
760 return AArch64CC::HS;
761 case CmpInst::ICMP_ULT:
762 return AArch64CC::LO;
766 bool AArch64FastISel::SelectBranch(const Instruction *I) {
767 const BranchInst *BI = cast<BranchInst>(I);
768 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
769 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
771 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
772 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
773 // We may not handle every CC for now.
774 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
775 if (CC == AArch64CC::AL)
779 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
783 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
786 FuncInfo.MBB->addSuccessor(TBB);
788 FastEmitBranch(FBB, DbgLoc);
791 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
793 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
794 (isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) {
795 unsigned CondReg = getRegForValue(TI->getOperand(0));
799 // Issue an extract_subreg to get the lower 32-bits.
800 if (SrcVT == MVT::i64)
801 CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true,
804 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
805 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
806 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
807 TII.get(AArch64::ANDWri), ANDReg)
809 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
810 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
811 TII.get(AArch64::SUBSWri))
817 unsigned CC = AArch64CC::NE;
818 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
825 FuncInfo.MBB->addSuccessor(TBB);
826 FastEmitBranch(FBB, DbgLoc);
829 } else if (const ConstantInt *CI =
830 dyn_cast<ConstantInt>(BI->getCondition())) {
831 uint64_t Imm = CI->getZExtValue();
832 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
833 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
835 FuncInfo.MBB->addSuccessor(Target);
839 unsigned CondReg = getRegForValue(BI->getCondition());
843 // We've been divorced from our compare! Our block was split, and
844 // now our compare lives in a predecessor block. We musn't
845 // re-compare here, as the children of the compare aren't guaranteed
846 // live across the block boundary (we *could* check for this).
847 // Regardless, the compare has been done in the predecessor block,
848 // and it left a value for us in a virtual register. Ergo, we test
849 // the one-bit value left in the virtual register.
850 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri),
856 unsigned CC = AArch64CC::NE;
857 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
862 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
865 FuncInfo.MBB->addSuccessor(TBB);
866 FastEmitBranch(FBB, DbgLoc);
870 bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
871 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
872 unsigned AddrReg = getRegForValue(BI->getOperand(0));
876 // Emit the indirect branch.
877 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BR))
880 // Make sure the CFG is up-to-date.
881 for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
882 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
887 bool AArch64FastISel::EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt) {
888 Type *Ty = Src1Value->getType();
889 EVT SrcEVT = TLI.getValueType(Ty, true);
890 if (!SrcEVT.isSimple())
892 MVT SrcVT = SrcEVT.getSimpleVT();
894 // Check to see if the 2nd operand is a constant that we can encode directly
898 bool isNegativeImm = false;
899 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
900 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
901 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
902 const APInt &CIVal = ConstInt->getValue();
904 Imm = (isZExt) ? CIVal.getZExtValue() : CIVal.getSExtValue();
905 if (CIVal.isNegative()) {
906 isNegativeImm = true;
909 // FIXME: We can handle more immediates using shifts.
910 UseImm = ((Imm & 0xfff) == Imm);
912 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
913 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
914 if (ConstFP->isZero() && !ConstFP->isNegative())
921 bool needsExt = false;
922 switch (SrcVT.SimpleTy) {
929 // Intentional fall-through.
933 CmpOpc = isNegativeImm ? AArch64::ADDSWri : AArch64::SUBSWri;
935 CmpOpc = AArch64::SUBSWrr;
940 CmpOpc = isNegativeImm ? AArch64::ADDSXri : AArch64::SUBSXri;
942 CmpOpc = AArch64::SUBSXrr;
946 CmpOpc = UseImm ? AArch64::FCMPSri : AArch64::FCMPSrr;
950 CmpOpc = UseImm ? AArch64::FCMPDri : AArch64::FCMPDrr;
954 unsigned SrcReg1 = getRegForValue(Src1Value);
960 SrcReg2 = getRegForValue(Src2Value);
965 // We have i1, i8, or i16, we need to either zero extend or sign extend.
967 SrcReg1 = EmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
971 SrcReg2 = EmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
979 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
985 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
991 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
994 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
1001 bool AArch64FastISel::SelectCmp(const Instruction *I) {
1002 const CmpInst *CI = cast<CmpInst>(I);
1004 // We may not handle every CC for now.
1005 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
1006 if (CC == AArch64CC::AL)
1010 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1013 // Now set a register based on the comparison.
1014 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
1015 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1016 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1018 .addReg(AArch64::WZR)
1019 .addReg(AArch64::WZR)
1020 .addImm(invertedCC);
1022 UpdateValueMap(I, ResultReg);
1026 bool AArch64FastISel::SelectSelect(const Instruction *I) {
1027 const SelectInst *SI = cast<SelectInst>(I);
1029 EVT DestEVT = TLI.getValueType(SI->getType(), true);
1030 if (!DestEVT.isSimple())
1033 MVT DestVT = DestEVT.getSimpleVT();
1034 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
1038 unsigned CondReg = getRegForValue(SI->getCondition());
1041 unsigned TrueReg = getRegForValue(SI->getTrueValue());
1044 unsigned FalseReg = getRegForValue(SI->getFalseValue());
1049 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
1050 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
1051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1054 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1056 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri))
1063 switch (DestVT.SimpleTy) {
1067 SelectOpc = AArch64::CSELWr;
1070 SelectOpc = AArch64::CSELXr;
1073 SelectOpc = AArch64::FCSELSrrr;
1076 SelectOpc = AArch64::FCSELDrrr;
1080 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1081 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SelectOpc),
1085 .addImm(AArch64CC::NE);
1087 UpdateValueMap(I, ResultReg);
1091 bool AArch64FastISel::SelectFPExt(const Instruction *I) {
1092 Value *V = I->getOperand(0);
1093 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
1096 unsigned Op = getRegForValue(V);
1100 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
1101 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
1102 ResultReg).addReg(Op);
1103 UpdateValueMap(I, ResultReg);
1107 bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
1108 Value *V = I->getOperand(0);
1109 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
1112 unsigned Op = getRegForValue(V);
1116 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
1117 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
1118 ResultReg).addReg(Op);
1119 UpdateValueMap(I, ResultReg);
1123 // FPToUI and FPToSI
1124 bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
1126 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1129 unsigned SrcReg = getRegForValue(I->getOperand(0));
1133 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1134 if (SrcVT == MVT::f128)
1138 if (SrcVT == MVT::f64) {
1140 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
1142 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
1145 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
1147 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
1149 unsigned ResultReg = createResultReg(
1150 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
1151 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1153 UpdateValueMap(I, ResultReg);
1157 bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
1159 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1161 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
1162 "Unexpected value type.");
1164 unsigned SrcReg = getRegForValue(I->getOperand(0));
1168 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1170 // Handle sign-extension.
1171 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
1173 EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
1178 MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass
1179 : &AArch64::GPR32RegClass);
1182 if (SrcVT == MVT::i64) {
1184 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
1186 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
1189 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
1191 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
1194 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1195 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1197 UpdateValueMap(I, ResultReg);
1201 bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
1202 SmallVectorImpl<MVT> &OutVTs,
1203 unsigned &NumBytes) {
1204 CallingConv::ID CC = CLI.CallConv;
1205 SmallVector<CCValAssign, 16> ArgLocs;
1206 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1207 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1209 // Get a count of how many bytes are to be pushed on the stack.
1210 NumBytes = CCInfo.getNextStackOffset();
1212 // Issue CALLSEQ_START
1213 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
1217 // Process the args.
1218 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1219 CCValAssign &VA = ArgLocs[i];
1220 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1221 MVT ArgVT = OutVTs[VA.getValNo()];
1223 unsigned ArgReg = getRegForValue(ArgVal);
1227 // Handle arg promotion: SExt, ZExt, AExt.
1228 switch (VA.getLocInfo()) {
1229 case CCValAssign::Full:
1231 case CCValAssign::SExt: {
1232 MVT DestVT = VA.getLocVT();
1234 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1239 case CCValAssign::AExt:
1240 // Intentional fall-through.
1241 case CCValAssign::ZExt: {
1242 MVT DestVT = VA.getLocVT();
1244 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1250 llvm_unreachable("Unknown arg promotion!");
1253 // Now copy/store arg to correct locations.
1254 if (VA.isRegLoc() && !VA.needsCustom()) {
1255 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1256 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1257 CLI.OutRegs.push_back(VA.getLocReg());
1258 } else if (VA.needsCustom()) {
1259 // FIXME: Handle custom args.
1262 assert(VA.isMemLoc() && "Assuming store on stack.");
1264 // Need to store on the stack.
1265 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
1267 unsigned BEAlign = 0;
1268 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1269 BEAlign = 8 - ArgSize;
1272 Addr.setKind(Address::RegBase);
1273 Addr.setReg(AArch64::SP);
1274 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1276 if (!EmitStore(ArgVT, ArgReg, Addr))
1283 bool AArch64FastISel::FinishCall(CallLoweringInfo &CLI, MVT RetVT,
1284 unsigned NumBytes) {
1285 CallingConv::ID CC = CLI.CallConv;
1287 // Issue CALLSEQ_END
1288 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1289 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
1290 .addImm(NumBytes).addImm(0);
1292 // Now the return value.
1293 if (RetVT != MVT::isVoid) {
1294 SmallVector<CCValAssign, 16> RVLocs;
1295 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1296 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
1298 // Only handle a single return value.
1299 if (RVLocs.size() != 1)
1302 // Copy all of the result registers out of their specified physreg.
1303 MVT CopyVT = RVLocs[0].getValVT();
1304 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1305 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1306 TII.get(TargetOpcode::COPY), ResultReg)
1307 .addReg(RVLocs[0].getLocReg());
1308 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1310 CLI.ResultReg = ResultReg;
1311 CLI.NumResultRegs = 1;
1317 bool AArch64FastISel::FastLowerCall(CallLoweringInfo &CLI) {
1318 CallingConv::ID CC = CLI.CallConv;
1319 bool IsVarArg = CLI.IsVarArg;
1320 const Value *Callee = CLI.Callee;
1321 const char *SymName = CLI.SymName;
1323 // Only handle global variable Callees.
1324 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1328 // Let SDISel handle vararg functions.
1332 // FIXME: Only handle *simple* calls for now.
1334 if (CLI.RetTy->isVoidTy())
1335 RetVT = MVT::isVoid;
1336 else if (!isTypeLegal(CLI.RetTy, RetVT))
1339 for (auto Flag : CLI.OutFlags)
1340 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1343 // Set up the argument vectors.
1344 SmallVector<MVT, 16> OutVTs;
1345 OutVTs.reserve(CLI.OutVals.size());
1347 for (auto *Val : CLI.OutVals) {
1349 if (!isTypeLegal(Val->getType(), VT) &&
1350 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1353 // We don't handle vector parameters yet.
1354 if (VT.isVector() || VT.getSizeInBits() > 64)
1357 OutVTs.push_back(VT);
1360 // Handle the arguments now that we've gotten them.
1362 if (!ProcessCallArgs(CLI, OutVTs, NumBytes))
1366 MachineInstrBuilder MIB;
1367 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BL));
1370 MIB.addGlobalAddress(GV, 0, 0);
1372 MIB.addExternalSymbol(SymName, 0);
1374 // Add implicit physical register uses to the call.
1375 for (auto Reg : CLI.OutRegs)
1376 MIB.addReg(Reg, RegState::Implicit);
1378 // Add a register mask with the call-preserved registers.
1379 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1380 MIB.addRegMask(TRI.getCallPreservedMask(CC));
1382 // Finish off the call including any return values.
1383 return FinishCall(CLI, RetVT, NumBytes);
1386 bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
1388 return Len / Alignment <= 4;
1393 bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
1394 uint64_t Len, unsigned Alignment) {
1395 // Make sure we don't bloat code by inlining very large memcpy's.
1396 if (!IsMemCpySmall(Len, Alignment))
1399 int64_t UnscaledOffset = 0;
1400 Address OrigDest = Dest;
1401 Address OrigSrc = Src;
1405 if (!Alignment || Alignment >= 8) {
1416 // Bound based on alignment.
1417 if (Len >= 4 && Alignment == 4)
1419 else if (Len >= 2 && Alignment == 2)
1428 RV = EmitLoad(VT, ResultReg, Src);
1432 RV = EmitStore(VT, ResultReg, Dest);
1436 int64_t Size = VT.getSizeInBits() / 8;
1438 UnscaledOffset += Size;
1440 // We need to recompute the unscaled offset for each iteration.
1441 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
1442 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
1448 bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
1449 // FIXME: Handle more intrinsics.
1450 switch (II->getIntrinsicID()) {
1451 default: return false;
1452 case Intrinsic::frameaddress: {
1453 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
1454 MFI->setFrameAddressIsTaken(true);
1456 const AArch64RegisterInfo *RegInfo =
1457 static_cast<const AArch64RegisterInfo *>(TM.getRegisterInfo());
1458 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
1459 unsigned SrcReg = FramePtr;
1461 // Recursively load frame address
1467 unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
1469 DestReg = createResultReg(&AArch64::GPR64RegClass);
1470 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1471 TII.get(AArch64::LDRXui), DestReg)
1472 .addReg(SrcReg).addImm(0);
1476 UpdateValueMap(II, SrcReg);
1479 case Intrinsic::memcpy:
1480 case Intrinsic::memmove: {
1481 const auto *MTI = cast<MemTransferInst>(II);
1482 // Don't handle volatile.
1483 if (MTI->isVolatile())
1486 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
1487 // we would emit dead code because we don't currently handle memmoves.
1488 bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
1489 if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
1490 // Small memcpy's are common enough that we want to do them without a call
1492 uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
1493 unsigned Alignment = MTI->getAlignment();
1494 if (IsMemCpySmall(Len, Alignment)) {
1496 if (!ComputeAddress(MTI->getRawDest(), Dest) ||
1497 !ComputeAddress(MTI->getRawSource(), Src))
1499 if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
1504 if (!MTI->getLength()->getType()->isIntegerTy(64))
1507 if (MTI->getSourceAddressSpace() > 255 || MTI->getDestAddressSpace() > 255)
1508 // Fast instruction selection doesn't support the special
1512 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1513 return LowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1515 case Intrinsic::memset: {
1516 const MemSetInst *MSI = cast<MemSetInst>(II);
1517 // Don't handle volatile.
1518 if (MSI->isVolatile())
1521 if (!MSI->getLength()->getType()->isIntegerTy(64))
1524 if (MSI->getDestAddressSpace() > 255)
1525 // Fast instruction selection doesn't support the special
1529 return LowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1531 case Intrinsic::trap: {
1532 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
1536 case Intrinsic::sadd_with_overflow:
1537 case Intrinsic::uadd_with_overflow:
1538 case Intrinsic::ssub_with_overflow:
1539 case Intrinsic::usub_with_overflow:
1540 case Intrinsic::smul_with_overflow:
1541 case Intrinsic::umul_with_overflow: {
1542 // This implements the basic lowering of the xalu with overflow intrinsics.
1543 const Function *Callee = II->getCalledFunction();
1544 auto *Ty = cast<StructType>(Callee->getReturnType());
1545 Type *RetTy = Ty->getTypeAtIndex(0U);
1546 Type *CondTy = Ty->getTypeAtIndex(1);
1549 if (!isTypeLegal(RetTy, VT))
1552 if (VT != MVT::i32 && VT != MVT::i64)
1555 const Value *LHS = II->getArgOperand(0);
1556 const Value *RHS = II->getArgOperand(1);
1557 // Canonicalize immediate to the RHS.
1558 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
1559 isCommutativeIntrinsic(II))
1560 std::swap(LHS, RHS);
1562 unsigned LHSReg = getRegForValue(LHS);
1565 bool LHSIsKill = hasTrivialKill(LHS);
1567 unsigned RHSReg = 0;
1568 bool RHSIsKill = false;
1570 if (!isa<ConstantInt>(RHS)) {
1571 RHSReg = getRegForValue(RHS);
1574 RHSIsKill = hasTrivialKill(RHS);
1579 unsigned MulReg = 0;
1580 AArch64CC::CondCode CC = AArch64CC::Invalid;
1581 bool Is64Bit = VT == MVT::i64;
1582 switch (II->getIntrinsicID()) {
1583 default: llvm_unreachable("Unexpected intrinsic!");
1584 case Intrinsic::sadd_with_overflow:
1586 Opc = Is64Bit ? AArch64::ADDSXri : AArch64::ADDSWri;
1588 Opc = Is64Bit ? AArch64::ADDSXrr : AArch64::ADDSWrr;
1591 case Intrinsic::uadd_with_overflow:
1593 Opc = Is64Bit ? AArch64::ADDSXri : AArch64::ADDSWri;
1595 Opc = Is64Bit ? AArch64::ADDSXrr : AArch64::ADDSWrr;
1598 case Intrinsic::ssub_with_overflow:
1600 Opc = Is64Bit ? AArch64::SUBSXri : AArch64::SUBSWri;
1602 Opc = Is64Bit ? AArch64::SUBSXrr : AArch64::SUBSWrr;
1605 case Intrinsic::usub_with_overflow:
1607 Opc = Is64Bit ? AArch64::SUBSXri : AArch64::SUBSWri;
1609 Opc = Is64Bit ? AArch64::SUBSXrr : AArch64::SUBSWrr;
1612 case Intrinsic::smul_with_overflow: {
1615 RHSReg = getRegForValue(RHS);
1618 RHSIsKill = hasTrivialKill(RHS);
1620 if (VT == MVT::i32) {
1621 MulReg = Emit_SMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1622 unsigned ShiftReg = Emit_LSR_ri(MVT::i64, MulReg, false, 32);
1623 MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
1625 ShiftReg = FastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true,
1627 unsigned CmpReg = createResultReg(TLI.getRegClassFor(VT));
1628 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1629 TII.get(AArch64::SUBSWrs), CmpReg)
1630 .addReg(ShiftReg, getKillRegState(true))
1631 .addReg(MulReg, getKillRegState(false))
1632 .addImm(159); // 159 <-> asr #31
1634 assert(VT == MVT::i64 && "Unexpected value type.");
1635 MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1636 unsigned SMULHReg = FastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
1638 unsigned CmpReg = createResultReg(TLI.getRegClassFor(VT));
1639 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1640 TII.get(AArch64::SUBSXrs), CmpReg)
1641 .addReg(SMULHReg, getKillRegState(true))
1642 .addReg(MulReg, getKillRegState(false))
1643 .addImm(191); // 191 <-> asr #63
1647 case Intrinsic::umul_with_overflow: {
1650 RHSReg = getRegForValue(RHS);
1653 RHSIsKill = hasTrivialKill(RHS);
1655 if (VT == MVT::i32) {
1656 MulReg = Emit_UMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1657 unsigned CmpReg = createResultReg(TLI.getRegClassFor(MVT::i64));
1658 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1659 TII.get(AArch64::SUBSXrs), CmpReg)
1660 .addReg(AArch64::XZR, getKillRegState(true))
1661 .addReg(MulReg, getKillRegState(false))
1662 .addImm(96); // 96 <-> lsr #32
1663 MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
1666 assert(VT == MVT::i64 && "Unexpected value type.");
1667 MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1668 unsigned UMULHReg = FastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
1670 unsigned CmpReg = createResultReg(TLI.getRegClassFor(VT));
1671 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1672 TII.get(AArch64::SUBSXrr), CmpReg)
1673 .addReg(AArch64::XZR, getKillRegState(true))
1674 .addReg(UMULHReg, getKillRegState(false));
1680 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1682 MachineInstrBuilder MIB;
1683 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1685 .addReg(LHSReg, getKillRegState(LHSIsKill));
1687 MIB.addImm(cast<ConstantInt>(RHS)->getZExtValue());
1689 MIB.addReg(RHSReg, getKillRegState(RHSIsKill));
1692 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1693 TII.get(TargetOpcode::COPY), ResultReg)
1696 unsigned ResultReg2 = FuncInfo.CreateRegs(CondTy);
1697 assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
1698 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1700 .addReg(AArch64::WZR, getKillRegState(true))
1701 .addReg(AArch64::WZR, getKillRegState(true))
1702 .addImm(getInvertedCondCode(CC));
1704 UpdateValueMap(II, ResultReg, 2);
1711 bool AArch64FastISel::SelectRet(const Instruction *I) {
1712 const ReturnInst *Ret = cast<ReturnInst>(I);
1713 const Function &F = *I->getParent()->getParent();
1715 if (!FuncInfo.CanLowerReturn)
1721 // Build a list of return value registers.
1722 SmallVector<unsigned, 4> RetRegs;
1724 if (Ret->getNumOperands() > 0) {
1725 CallingConv::ID CC = F.getCallingConv();
1726 SmallVector<ISD::OutputArg, 4> Outs;
1727 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1729 // Analyze operands of the call, assigning locations to each operand.
1730 SmallVector<CCValAssign, 16> ValLocs;
1731 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
1733 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
1734 : RetCC_AArch64_AAPCS;
1735 CCInfo.AnalyzeReturn(Outs, RetCC);
1737 // Only handle a single return value for now.
1738 if (ValLocs.size() != 1)
1741 CCValAssign &VA = ValLocs[0];
1742 const Value *RV = Ret->getOperand(0);
1744 // Don't bother handling odd stuff for now.
1745 if (VA.getLocInfo() != CCValAssign::Full)
1747 // Only handle register returns for now.
1750 unsigned Reg = getRegForValue(RV);
1754 unsigned SrcReg = Reg + VA.getValNo();
1755 unsigned DestReg = VA.getLocReg();
1756 // Avoid a cross-class copy. This is very unlikely.
1757 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1760 EVT RVEVT = TLI.getValueType(RV->getType());
1761 if (!RVEVT.isSimple())
1764 // Vectors (of > 1 lane) in big endian need tricky handling.
1765 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
1768 MVT RVVT = RVEVT.getSimpleVT();
1769 if (RVVT == MVT::f128)
1771 MVT DestVT = VA.getValVT();
1772 // Special handling for extended integers.
1773 if (RVVT != DestVT) {
1774 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1777 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1780 bool isZExt = Outs[0].Flags.isZExt();
1781 SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
1787 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1788 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1790 // Add register to return instruction.
1791 RetRegs.push_back(VA.getLocReg());
1794 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1795 TII.get(AArch64::RET_ReallyLR));
1796 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1797 MIB.addReg(RetRegs[i], RegState::Implicit);
1801 bool AArch64FastISel::SelectTrunc(const Instruction *I) {
1802 Type *DestTy = I->getType();
1803 Value *Op = I->getOperand(0);
1804 Type *SrcTy = Op->getType();
1806 EVT SrcEVT = TLI.getValueType(SrcTy, true);
1807 EVT DestEVT = TLI.getValueType(DestTy, true);
1808 if (!SrcEVT.isSimple())
1810 if (!DestEVT.isSimple())
1813 MVT SrcVT = SrcEVT.getSimpleVT();
1814 MVT DestVT = DestEVT.getSimpleVT();
1816 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
1819 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
1823 unsigned SrcReg = getRegForValue(Op);
1827 // If we're truncating from i64 to a smaller non-legal type then generate an
1828 // AND. Otherwise, we know the high bits are undefined and a truncate doesn't
1829 // generate any code.
1830 if (SrcVT == MVT::i64) {
1832 switch (DestVT.SimpleTy) {
1834 // Trunc i64 to i32 is handled by the target-independent fast-isel.
1846 // Issue an extract_subreg to get the lower 32-bits.
1847 unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true,
1849 MRI.constrainRegClass(Reg32, &AArch64::GPR32RegClass);
1850 // Create the AND instruction which performs the actual truncation.
1851 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
1852 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1855 .addImm(AArch64_AM::encodeLogicalImmediate(Mask, 32));
1859 UpdateValueMap(I, SrcReg);
1863 unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
1864 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
1865 DestVT == MVT::i64) &&
1866 "Unexpected value type.");
1867 // Handle i8 and i16 as i32.
1868 if (DestVT == MVT::i8 || DestVT == MVT::i16)
1872 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
1873 unsigned ResultReg = createResultReg(&AArch64::GPR32spRegClass);
1874 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1877 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1879 if (DestVT == MVT::i64) {
1880 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
1881 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
1882 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1883 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1884 TII.get(AArch64::SUBREG_TO_REG), Reg64)
1887 .addImm(AArch64::sub_32);
1892 if (DestVT == MVT::i64) {
1893 // FIXME: We're SExt i1 to i64.
1896 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1897 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SBFMWri),
1906 unsigned AArch64FastISel::Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
1907 unsigned Op1, bool Op1IsKill) {
1909 switch (RetVT.SimpleTy) {
1915 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break;
1917 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
1920 // Create the base instruction, then add the operands.
1921 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1922 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1923 .addReg(Op0, getKillRegState(Op0IsKill))
1924 .addReg(Op1, getKillRegState(Op1IsKill))
1925 .addReg(ZReg, getKillRegState(true));
1930 unsigned AArch64FastISel::Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
1931 unsigned Op1, bool Op1IsKill) {
1932 if (RetVT != MVT::i64)
1935 // Create the base instruction, then add the operands.
1936 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
1937 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SMADDLrrr),
1939 .addReg(Op0, getKillRegState(Op0IsKill))
1940 .addReg(Op1, getKillRegState(Op1IsKill))
1941 .addReg(AArch64::XZR, getKillRegState(true));
1946 unsigned AArch64FastISel::Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
1947 unsigned Op1, bool Op1IsKill) {
1948 if (RetVT != MVT::i64)
1951 // Create the base instruction, then add the operands.
1952 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
1953 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::UMADDLrrr),
1955 .addReg(Op0, getKillRegState(Op0IsKill))
1956 .addReg(Op1, getKillRegState(Op1IsKill))
1957 .addReg(AArch64::XZR, getKillRegState(true));
1962 unsigned AArch64FastISel::Emit_LSL_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
1964 unsigned Opc, ImmR, ImmS;
1965 switch (RetVT.SimpleTy) {
1971 Opc = AArch64::UBFMWri; ImmR = -Shift % 32; ImmS = 31 - Shift; break;
1973 Opc = AArch64::UBFMXri; ImmR = -Shift % 64; ImmS = 63 - Shift; break;
1976 return FastEmitInst_rii(Opc, TLI.getRegClassFor(RetVT), Op0, Op0IsKill, ImmR,
1980 unsigned AArch64FastISel::Emit_LSR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
1983 switch (RetVT.SimpleTy) {
1989 Opc = AArch64::UBFMWri; ImmS = 31; break;
1991 Opc = AArch64::UBFMXri; ImmS = 63; break;
1994 return FastEmitInst_rii(Opc, TLI.getRegClassFor(RetVT), Op0, Op0IsKill, Shift,
1998 unsigned AArch64FastISel::Emit_ASR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
2001 switch (RetVT.SimpleTy) {
2007 Opc = AArch64::SBFMWri; ImmS = 31; break;
2009 Opc = AArch64::SBFMXri; ImmS = 63; break;
2012 return FastEmitInst_rii(Opc, TLI.getRegClassFor(RetVT), Op0, Op0IsKill, Shift,
2016 unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2018 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
2020 // FastISel does not have plumbing to deal with extensions where the SrcVT or
2021 // DestVT are odd things, so test to make sure that they are both types we can
2022 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
2023 // bail out to SelectionDAG.
2024 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
2025 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
2026 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
2027 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
2033 switch (SrcVT.SimpleTy) {
2037 return Emiti1Ext(SrcReg, DestVT, isZExt);
2039 if (DestVT == MVT::i64)
2040 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
2042 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
2046 if (DestVT == MVT::i64)
2047 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
2049 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
2053 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
2054 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
2059 // Handle i8 and i16 as i32.
2060 if (DestVT == MVT::i8 || DestVT == MVT::i16)
2062 else if (DestVT == MVT::i64) {
2063 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2065 TII.get(AArch64::SUBREG_TO_REG), Src64)
2068 .addImm(AArch64::sub_32);
2072 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
2073 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2081 bool AArch64FastISel::SelectIntExt(const Instruction *I) {
2082 // On ARM, in general, integer casts don't involve legal types; this code
2083 // handles promotable integers. The high bits for a type smaller than
2084 // the register size are assumed to be undefined.
2085 Type *DestTy = I->getType();
2086 Value *Src = I->getOperand(0);
2087 Type *SrcTy = Src->getType();
2089 bool isZExt = isa<ZExtInst>(I);
2090 unsigned SrcReg = getRegForValue(Src);
2094 EVT SrcEVT = TLI.getValueType(SrcTy, true);
2095 EVT DestEVT = TLI.getValueType(DestTy, true);
2096 if (!SrcEVT.isSimple())
2098 if (!DestEVT.isSimple())
2101 MVT SrcVT = SrcEVT.getSimpleVT();
2102 MVT DestVT = DestEVT.getSimpleVT();
2103 unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2106 UpdateValueMap(I, ResultReg);
2110 bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
2111 EVT DestEVT = TLI.getValueType(I->getType(), true);
2112 if (!DestEVT.isSimple())
2115 MVT DestVT = DestEVT.getSimpleVT();
2116 if (DestVT != MVT::i64 && DestVT != MVT::i32)
2120 bool is64bit = (DestVT == MVT::i64);
2121 switch (ISDOpcode) {
2125 DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
2128 DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
2131 unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
2132 unsigned Src0Reg = getRegForValue(I->getOperand(0));
2136 unsigned Src1Reg = getRegForValue(I->getOperand(1));
2140 unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
2141 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg)
2144 // The remainder is computed as numerator - (quotient * denominator) using the
2145 // MSUB instruction.
2146 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
2147 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
2151 UpdateValueMap(I, ResultReg);
2155 bool AArch64FastISel::SelectMul(const Instruction *I) {
2156 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
2157 if (!SrcEVT.isSimple())
2159 MVT SrcVT = SrcEVT.getSimpleVT();
2161 // Must be simple value type. Don't handle vectors.
2162 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
2166 unsigned Src0Reg = getRegForValue(I->getOperand(0));
2169 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
2171 unsigned Src1Reg = getRegForValue(I->getOperand(1));
2174 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
2176 unsigned ResultReg =
2177 Emit_MUL_rr(SrcVT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
2182 UpdateValueMap(I, ResultReg);
2186 bool AArch64FastISel::SelectShift(const Instruction *I, bool IsLeftShift,
2187 bool IsArithmetic) {
2188 EVT RetEVT = TLI.getValueType(I->getType(), true);
2189 if (!RetEVT.isSimple())
2191 MVT RetVT = RetEVT.getSimpleVT();
2193 if (!isa<ConstantInt>(I->getOperand(1)))
2196 unsigned Op0Reg = getRegForValue(I->getOperand(0));
2199 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
2201 uint64_t ShiftVal = cast<ConstantInt>(I->getOperand(1))->getZExtValue();
2205 ResultReg = Emit_LSL_ri(RetVT, Op0Reg, Op0IsKill, ShiftVal);
2208 ResultReg = Emit_ASR_ri(RetVT, Op0Reg, Op0IsKill, ShiftVal);
2210 ResultReg = Emit_LSR_ri(RetVT, Op0Reg, Op0IsKill, ShiftVal);
2216 UpdateValueMap(I, ResultReg);
2220 bool AArch64FastISel::TargetSelectInstruction(const Instruction *I) {
2221 switch (I->getOpcode()) {
2224 case Instruction::Load:
2225 return SelectLoad(I);
2226 case Instruction::Store:
2227 return SelectStore(I);
2228 case Instruction::Br:
2229 return SelectBranch(I);
2230 case Instruction::IndirectBr:
2231 return SelectIndirectBr(I);
2232 case Instruction::FCmp:
2233 case Instruction::ICmp:
2234 return SelectCmp(I);
2235 case Instruction::Select:
2236 return SelectSelect(I);
2237 case Instruction::FPExt:
2238 return SelectFPExt(I);
2239 case Instruction::FPTrunc:
2240 return SelectFPTrunc(I);
2241 case Instruction::FPToSI:
2242 return SelectFPToInt(I, /*Signed=*/true);
2243 case Instruction::FPToUI:
2244 return SelectFPToInt(I, /*Signed=*/false);
2245 case Instruction::SIToFP:
2246 return SelectIntToFP(I, /*Signed=*/true);
2247 case Instruction::UIToFP:
2248 return SelectIntToFP(I, /*Signed=*/false);
2249 case Instruction::SRem:
2250 return SelectRem(I, ISD::SREM);
2251 case Instruction::URem:
2252 return SelectRem(I, ISD::UREM);
2253 case Instruction::Ret:
2254 return SelectRet(I);
2255 case Instruction::Trunc:
2256 return SelectTrunc(I);
2257 case Instruction::ZExt:
2258 case Instruction::SExt:
2259 return SelectIntExt(I);
2261 // FIXME: All of these should really be handled by the target-independent
2262 // selector -> improve FastISel tblgen.
2263 case Instruction::Mul:
2264 return SelectMul(I);
2265 case Instruction::Shl:
2266 return SelectShift(I, /*IsLeftShift=*/true, /*IsArithmetic=*/false);
2267 case Instruction::LShr:
2268 return SelectShift(I, /*IsLeftShift=*/false, /*IsArithmetic=*/false);
2269 case Instruction::AShr:
2270 return SelectShift(I, /*IsLeftShift=*/false, /*IsArithmetic=*/true);
2273 // Silence warnings.
2274 (void)&CC_AArch64_DarwinPCS_VarArg;
2278 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
2279 const TargetLibraryInfo *libInfo) {
2280 return new AArch64FastISel(funcInfo, libInfo);