1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GetElementPtrTypeIterator.h"
32 #include "llvm/IR/GlobalAlias.h"
33 #include "llvm/IR/GlobalVariable.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Operator.h"
37 #include "llvm/Support/CommandLine.h"
42 class AArch64FastISel : public FastISel {
60 Address() : Kind(RegBase), Offset(0) { Base.Reg = 0; }
61 void setKind(BaseKind K) { Kind = K; }
62 BaseKind getKind() const { return Kind; }
63 bool isRegBase() const { return Kind == RegBase; }
64 bool isFIBase() const { return Kind == FrameIndexBase; }
65 void setReg(unsigned Reg) {
66 assert(isRegBase() && "Invalid base register access!");
69 unsigned getReg() const {
70 assert(isRegBase() && "Invalid base register access!");
73 void setFI(unsigned FI) {
74 assert(isFIBase() && "Invalid base frame index access!");
77 unsigned getFI() const {
78 assert(isFIBase() && "Invalid base frame index access!");
81 void setOffset(int64_t O) { Offset = O; }
82 int64_t getOffset() { return Offset; }
84 bool isValid() { return isFIBase() || (isRegBase() && getReg() != 0); }
87 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
88 /// make the right decision when generating code for different targets.
89 const AArch64Subtarget *Subtarget;
92 bool FastLowerCall(CallLoweringInfo &CLI) override;
93 bool FastLowerIntrinsicCall(const IntrinsicInst *II) override;
96 // Selection routines.
97 bool SelectLoad(const Instruction *I);
98 bool SelectStore(const Instruction *I);
99 bool SelectBranch(const Instruction *I);
100 bool SelectIndirectBr(const Instruction *I);
101 bool SelectCmp(const Instruction *I);
102 bool SelectSelect(const Instruction *I);
103 bool SelectFPExt(const Instruction *I);
104 bool SelectFPTrunc(const Instruction *I);
105 bool SelectFPToInt(const Instruction *I, bool Signed);
106 bool SelectIntToFP(const Instruction *I, bool Signed);
107 bool SelectRem(const Instruction *I, unsigned ISDOpcode);
108 bool SelectRet(const Instruction *I);
109 bool SelectTrunc(const Instruction *I);
110 bool SelectIntExt(const Instruction *I);
111 bool SelectMul(const Instruction *I);
113 // Utility helper routines.
114 bool isTypeLegal(Type *Ty, MVT &VT);
115 bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
116 bool ComputeAddress(const Value *Obj, Address &Addr);
117 bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
119 void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
120 unsigned Flags, bool UseUnscaled);
121 bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
122 bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
125 bool EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt);
126 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
127 bool UseUnscaled = false);
128 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
129 bool UseUnscaled = false);
130 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
131 unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
133 unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
134 unsigned AArch64MaterializeGV(const GlobalValue *GV);
136 // Call handling routines.
138 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
139 bool ProcessCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
141 bool FinishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
144 // Backend specific FastISel code.
145 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
146 unsigned TargetMaterializeConstant(const Constant *C) override;
148 explicit AArch64FastISel(FunctionLoweringInfo &funcInfo,
149 const TargetLibraryInfo *libInfo)
150 : FastISel(funcInfo, libInfo) {
151 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
152 Context = &funcInfo.Fn->getContext();
155 bool TargetSelectInstruction(const Instruction *I) override;
157 #include "AArch64GenFastISel.inc"
160 } // end anonymous namespace
162 #include "AArch64GenCallingConv.inc"
164 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
165 if (CC == CallingConv::WebKit_JS)
166 return CC_AArch64_WebKit_JS;
167 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
170 unsigned AArch64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
171 assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
172 "Alloca should always return a pointer.");
174 // Don't handle dynamic allocas.
175 if (!FuncInfo.StaticAllocaMap.count(AI))
178 DenseMap<const AllocaInst *, int>::iterator SI =
179 FuncInfo.StaticAllocaMap.find(AI);
181 if (SI != FuncInfo.StaticAllocaMap.end()) {
182 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
183 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
185 .addFrameIndex(SI->second)
194 unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
195 if (VT != MVT::f32 && VT != MVT::f64)
198 const APFloat Val = CFP->getValueAPF();
199 bool is64bit = (VT == MVT::f64);
201 // This checks to see if we can use FMOV instructions to materialize
202 // a constant, otherwise we have to materialize via the constant pool.
203 if (TLI.isFPImmLegal(Val, VT)) {
207 Imm = AArch64_AM::getFP64Imm(Val);
208 Opc = AArch64::FMOVDi;
210 Imm = AArch64_AM::getFP32Imm(Val);
211 Opc = AArch64::FMOVSi;
213 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
219 // Materialize via constant pool. MachineConstantPool wants an explicit
221 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
223 Align = DL.getTypeAllocSize(CFP->getType());
225 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
226 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
227 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
228 ADRPReg).addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGE);
230 unsigned Opc = is64bit ? AArch64::LDRDui : AArch64::LDRSui;
231 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
232 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
234 .addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
238 unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
239 // We can't handle thread-local variables quickly yet.
240 if (GV->isThreadLocal())
243 // MachO still uses GOT for large code-model accesses, but ELF requires
244 // movz/movk sequences, which FastISel doesn't handle yet.
245 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
248 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
250 EVT DestEVT = TLI.getValueType(GV->getType(), true);
251 if (!DestEVT.isSimple())
254 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
257 if (OpFlags & AArch64II::MO_GOT) {
259 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
261 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
263 ResultReg = createResultReg(&AArch64::GPR64RegClass);
264 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
267 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
271 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
272 ADRPReg).addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
274 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
275 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
278 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
284 unsigned AArch64FastISel::TargetMaterializeConstant(const Constant *C) {
285 EVT CEVT = TLI.getValueType(C->getType(), true);
287 // Only handle simple types.
288 if (!CEVT.isSimple())
290 MVT VT = CEVT.getSimpleVT();
292 // FIXME: Handle ConstantInt.
293 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
294 return AArch64MaterializeFP(CFP, VT);
295 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
296 return AArch64MaterializeGV(GV);
301 // Computes the address to get to an object.
302 bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr) {
303 const User *U = nullptr;
304 unsigned Opcode = Instruction::UserOp1;
305 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
306 // Don't walk into other basic blocks unless the object is an alloca from
307 // another block, otherwise it may not have a virtual register assigned.
308 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
309 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
310 Opcode = I->getOpcode();
313 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
314 Opcode = C->getOpcode();
318 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
319 if (Ty->getAddressSpace() > 255)
320 // Fast instruction selection doesn't support the special
327 case Instruction::BitCast: {
328 // Look through bitcasts.
329 return ComputeAddress(U->getOperand(0), Addr);
331 case Instruction::IntToPtr: {
332 // Look past no-op inttoptrs.
333 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
334 return ComputeAddress(U->getOperand(0), Addr);
337 case Instruction::PtrToInt: {
338 // Look past no-op ptrtoints.
339 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
340 return ComputeAddress(U->getOperand(0), Addr);
343 case Instruction::GetElementPtr: {
344 Address SavedAddr = Addr;
345 uint64_t TmpOffset = Addr.getOffset();
347 // Iterate through the GEP folding the constants into offsets where
349 gep_type_iterator GTI = gep_type_begin(U);
350 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
352 const Value *Op = *i;
353 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
354 const StructLayout *SL = DL.getStructLayout(STy);
355 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
356 TmpOffset += SL->getElementOffset(Idx);
358 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
360 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
361 // Constant-offset addressing.
362 TmpOffset += CI->getSExtValue() * S;
365 if (canFoldAddIntoGEP(U, Op)) {
366 // A compatible add with a constant operand. Fold the constant.
368 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
369 TmpOffset += CI->getSExtValue() * S;
370 // Iterate on the other operand.
371 Op = cast<AddOperator>(Op)->getOperand(0);
375 goto unsupported_gep;
380 // Try to grab the base operand now.
381 Addr.setOffset(TmpOffset);
382 if (ComputeAddress(U->getOperand(0), Addr))
385 // We failed, restore everything and try the other options.
391 case Instruction::Alloca: {
392 const AllocaInst *AI = cast<AllocaInst>(Obj);
393 DenseMap<const AllocaInst *, int>::iterator SI =
394 FuncInfo.StaticAllocaMap.find(AI);
395 if (SI != FuncInfo.StaticAllocaMap.end()) {
396 Addr.setKind(Address::FrameIndexBase);
397 Addr.setFI(SI->second);
404 // Try to get this in a register if nothing else has worked.
406 Addr.setReg(getRegForValue(Obj));
407 return Addr.isValid();
410 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
411 EVT evt = TLI.getValueType(Ty, true);
413 // Only handle simple types.
414 if (evt == MVT::Other || !evt.isSimple())
416 VT = evt.getSimpleVT();
418 // This is a legal type, but it's not something we handle in fast-isel.
422 // Handle all other legal types, i.e. a register that will directly hold this
424 return TLI.isTypeLegal(VT);
427 bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
428 if (isTypeLegal(Ty, VT))
431 // If this is a type than can be sign or zero-extended to a basic operation
432 // go ahead and accept it now. For stores, this reflects truncation.
433 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
439 bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT,
440 int64_t ScaleFactor, bool UseUnscaled) {
441 bool needsLowering = false;
442 int64_t Offset = Addr.getOffset();
443 switch (VT.SimpleTy) {
454 // Using scaled, 12-bit, unsigned immediate offsets.
455 needsLowering = ((Offset & 0xfff) != Offset);
457 // Using unscaled, 9-bit, signed immediate offsets.
458 needsLowering = (Offset > 256 || Offset < -256);
462 //If this is a stack pointer and the offset needs to be simplified then put
463 // the alloca address into a register, set the base type back to register and
464 // continue. This should almost never happen.
465 if (needsLowering && Addr.getKind() == Address::FrameIndexBase) {
466 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
467 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
469 .addFrameIndex(Addr.getFI())
472 Addr.setKind(Address::RegBase);
473 Addr.setReg(ResultReg);
476 // Since the offset is too large for the load/store instruction get the
477 // reg+offset into a register.
479 uint64_t UnscaledOffset = Addr.getOffset() * ScaleFactor;
480 unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
481 UnscaledOffset, MVT::i64);
484 Addr.setReg(ResultReg);
490 void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
491 const MachineInstrBuilder &MIB,
492 unsigned Flags, bool UseUnscaled) {
493 int64_t Offset = Addr.getOffset();
494 // Frame base works a bit differently. Handle it separately.
495 if (Addr.getKind() == Address::FrameIndexBase) {
496 int FI = Addr.getFI();
497 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
498 // and alignment should be based on the VT.
499 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
500 MachinePointerInfo::getFixedStack(FI, Offset), Flags,
501 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
502 // Now add the rest of the operands.
503 MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
505 // Now add the rest of the operands.
506 MIB.addReg(Addr.getReg());
511 bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
513 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
514 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
515 if (!UseUnscaled && Addr.getOffset() < 0)
519 const TargetRegisterClass *RC;
521 int64_t ScaleFactor = 0;
522 switch (VT.SimpleTy) {
527 // Intentional fall-through.
529 Opc = UseUnscaled ? AArch64::LDURBBi : AArch64::LDRBBui;
530 RC = &AArch64::GPR32RegClass;
534 Opc = UseUnscaled ? AArch64::LDURHHi : AArch64::LDRHHui;
535 RC = &AArch64::GPR32RegClass;
539 Opc = UseUnscaled ? AArch64::LDURWi : AArch64::LDRWui;
540 RC = &AArch64::GPR32RegClass;
544 Opc = UseUnscaled ? AArch64::LDURXi : AArch64::LDRXui;
545 RC = &AArch64::GPR64RegClass;
549 Opc = UseUnscaled ? AArch64::LDURSi : AArch64::LDRSui;
550 RC = TLI.getRegClassFor(VT);
554 Opc = UseUnscaled ? AArch64::LDURDi : AArch64::LDRDui;
555 RC = TLI.getRegClassFor(VT);
561 int64_t Offset = Addr.getOffset();
562 if (Offset & (ScaleFactor - 1))
563 // Retry using an unscaled, 9-bit, signed immediate offset.
564 return EmitLoad(VT, ResultReg, Addr, /*UseUnscaled*/ true);
566 Addr.setOffset(Offset / ScaleFactor);
569 // Simplify this down to something we can handle.
570 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
573 // Create the base instruction, then add the operands.
574 ResultReg = createResultReg(RC);
575 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
576 TII.get(Opc), ResultReg);
577 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, UseUnscaled);
579 // Loading an i1 requires special handling.
581 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
582 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
583 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
586 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
592 bool AArch64FastISel::SelectLoad(const Instruction *I) {
594 // Verify we have a legal type before going any further. Currently, we handle
595 // simple types that will directly fit in a register (i32/f32/i64/f64) or
596 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
597 if (!isLoadStoreTypeLegal(I->getType(), VT) || cast<LoadInst>(I)->isAtomic())
600 // See if we can handle this address.
602 if (!ComputeAddress(I->getOperand(0), Addr))
606 if (!EmitLoad(VT, ResultReg, Addr))
609 UpdateValueMap(I, ResultReg);
613 bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
615 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
616 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
617 if (!UseUnscaled && Addr.getOffset() < 0)
622 int64_t ScaleFactor = 0;
623 // Using scaled, 12-bit, unsigned immediate offsets.
624 switch (VT.SimpleTy) {
630 StrOpc = UseUnscaled ? AArch64::STURBBi : AArch64::STRBBui;
634 StrOpc = UseUnscaled ? AArch64::STURHHi : AArch64::STRHHui;
638 StrOpc = UseUnscaled ? AArch64::STURWi : AArch64::STRWui;
642 StrOpc = UseUnscaled ? AArch64::STURXi : AArch64::STRXui;
646 StrOpc = UseUnscaled ? AArch64::STURSi : AArch64::STRSui;
650 StrOpc = UseUnscaled ? AArch64::STURDi : AArch64::STRDui;
656 int64_t Offset = Addr.getOffset();
657 if (Offset & (ScaleFactor - 1))
658 // Retry using an unscaled, 9-bit, signed immediate offset.
659 return EmitStore(VT, SrcReg, Addr, /*UseUnscaled*/ true);
661 Addr.setOffset(Offset / ScaleFactor);
664 // Simplify this down to something we can handle.
665 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
668 // Storing an i1 requires special handling.
670 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
671 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
672 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
675 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
678 // Create the base instruction, then add the operands.
679 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
680 TII.get(StrOpc)).addReg(SrcReg);
681 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, UseUnscaled);
685 bool AArch64FastISel::SelectStore(const Instruction *I) {
687 Value *Op0 = I->getOperand(0);
688 // Verify we have a legal type before going any further. Currently, we handle
689 // simple types that will directly fit in a register (i32/f32/i64/f64) or
690 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
691 if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
692 cast<StoreInst>(I)->isAtomic())
695 // Get the value to be stored into a register.
696 unsigned SrcReg = getRegForValue(Op0);
700 // See if we can handle this address.
702 if (!ComputeAddress(I->getOperand(1), Addr))
705 if (!EmitStore(VT, SrcReg, Addr))
710 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
712 case CmpInst::FCMP_ONE:
713 case CmpInst::FCMP_UEQ:
715 // AL is our "false" for now. The other two need more compares.
716 return AArch64CC::AL;
717 case CmpInst::ICMP_EQ:
718 case CmpInst::FCMP_OEQ:
719 return AArch64CC::EQ;
720 case CmpInst::ICMP_SGT:
721 case CmpInst::FCMP_OGT:
722 return AArch64CC::GT;
723 case CmpInst::ICMP_SGE:
724 case CmpInst::FCMP_OGE:
725 return AArch64CC::GE;
726 case CmpInst::ICMP_UGT:
727 case CmpInst::FCMP_UGT:
728 return AArch64CC::HI;
729 case CmpInst::FCMP_OLT:
730 return AArch64CC::MI;
731 case CmpInst::ICMP_ULE:
732 case CmpInst::FCMP_OLE:
733 return AArch64CC::LS;
734 case CmpInst::FCMP_ORD:
735 return AArch64CC::VC;
736 case CmpInst::FCMP_UNO:
737 return AArch64CC::VS;
738 case CmpInst::FCMP_UGE:
739 return AArch64CC::PL;
740 case CmpInst::ICMP_SLT:
741 case CmpInst::FCMP_ULT:
742 return AArch64CC::LT;
743 case CmpInst::ICMP_SLE:
744 case CmpInst::FCMP_ULE:
745 return AArch64CC::LE;
746 case CmpInst::FCMP_UNE:
747 case CmpInst::ICMP_NE:
748 return AArch64CC::NE;
749 case CmpInst::ICMP_UGE:
750 return AArch64CC::HS;
751 case CmpInst::ICMP_ULT:
752 return AArch64CC::LO;
756 bool AArch64FastISel::SelectBranch(const Instruction *I) {
757 const BranchInst *BI = cast<BranchInst>(I);
758 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
759 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
761 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
762 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
763 // We may not handle every CC for now.
764 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
765 if (CC == AArch64CC::AL)
769 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
773 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
776 FuncInfo.MBB->addSuccessor(TBB);
778 FastEmitBranch(FBB, DbgLoc);
781 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
783 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
784 (isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) {
785 unsigned CondReg = getRegForValue(TI->getOperand(0));
789 // Issue an extract_subreg to get the lower 32-bits.
790 if (SrcVT == MVT::i64)
791 CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true,
794 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
795 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
796 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
797 TII.get(AArch64::ANDWri), ANDReg)
799 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
800 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
801 TII.get(AArch64::SUBSWri))
807 unsigned CC = AArch64CC::NE;
808 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
812 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
815 FuncInfo.MBB->addSuccessor(TBB);
816 FastEmitBranch(FBB, DbgLoc);
819 } else if (const ConstantInt *CI =
820 dyn_cast<ConstantInt>(BI->getCondition())) {
821 uint64_t Imm = CI->getZExtValue();
822 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
823 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
825 FuncInfo.MBB->addSuccessor(Target);
829 unsigned CondReg = getRegForValue(BI->getCondition());
833 // We've been divorced from our compare! Our block was split, and
834 // now our compare lives in a predecessor block. We musn't
835 // re-compare here, as the children of the compare aren't guaranteed
836 // live across the block boundary (we *could* check for this).
837 // Regardless, the compare has been done in the predecessor block,
838 // and it left a value for us in a virtual register. Ergo, we test
839 // the one-bit value left in the virtual register.
840 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri),
846 unsigned CC = AArch64CC::NE;
847 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
852 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
855 FuncInfo.MBB->addSuccessor(TBB);
856 FastEmitBranch(FBB, DbgLoc);
860 bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
861 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
862 unsigned AddrReg = getRegForValue(BI->getOperand(0));
866 // Emit the indirect branch.
867 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BR))
870 // Make sure the CFG is up-to-date.
871 for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
872 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
877 bool AArch64FastISel::EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt) {
878 Type *Ty = Src1Value->getType();
879 EVT SrcEVT = TLI.getValueType(Ty, true);
880 if (!SrcEVT.isSimple())
882 MVT SrcVT = SrcEVT.getSimpleVT();
884 // Check to see if the 2nd operand is a constant that we can encode directly
888 bool isNegativeImm = false;
889 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
890 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
891 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
892 const APInt &CIVal = ConstInt->getValue();
894 Imm = (isZExt) ? CIVal.getZExtValue() : CIVal.getSExtValue();
895 if (CIVal.isNegative()) {
896 isNegativeImm = true;
899 // FIXME: We can handle more immediates using shifts.
900 UseImm = ((Imm & 0xfff) == Imm);
902 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
903 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
904 if (ConstFP->isZero() && !ConstFP->isNegative())
911 bool needsExt = false;
912 switch (SrcVT.SimpleTy) {
919 // Intentional fall-through.
923 CmpOpc = isNegativeImm ? AArch64::ADDSWri : AArch64::SUBSWri;
925 CmpOpc = AArch64::SUBSWrr;
930 CmpOpc = isNegativeImm ? AArch64::ADDSXri : AArch64::SUBSXri;
932 CmpOpc = AArch64::SUBSXrr;
936 CmpOpc = UseImm ? AArch64::FCMPSri : AArch64::FCMPSrr;
940 CmpOpc = UseImm ? AArch64::FCMPDri : AArch64::FCMPDrr;
944 unsigned SrcReg1 = getRegForValue(Src1Value);
950 SrcReg2 = getRegForValue(Src2Value);
955 // We have i1, i8, or i16, we need to either zero extend or sign extend.
957 SrcReg1 = EmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
961 SrcReg2 = EmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
969 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
975 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
981 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
984 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
991 bool AArch64FastISel::SelectCmp(const Instruction *I) {
992 const CmpInst *CI = cast<CmpInst>(I);
994 // We may not handle every CC for now.
995 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
996 if (CC == AArch64CC::AL)
1000 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1003 // Now set a register based on the comparison.
1004 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
1005 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1006 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1008 .addReg(AArch64::WZR)
1009 .addReg(AArch64::WZR)
1010 .addImm(invertedCC);
1012 UpdateValueMap(I, ResultReg);
1016 bool AArch64FastISel::SelectSelect(const Instruction *I) {
1017 const SelectInst *SI = cast<SelectInst>(I);
1019 EVT DestEVT = TLI.getValueType(SI->getType(), true);
1020 if (!DestEVT.isSimple())
1023 MVT DestVT = DestEVT.getSimpleVT();
1024 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
1028 unsigned CondReg = getRegForValue(SI->getCondition());
1031 unsigned TrueReg = getRegForValue(SI->getTrueValue());
1034 unsigned FalseReg = getRegForValue(SI->getFalseValue());
1039 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
1040 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
1041 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1044 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1046 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri))
1053 switch (DestVT.SimpleTy) {
1057 SelectOpc = AArch64::CSELWr;
1060 SelectOpc = AArch64::CSELXr;
1063 SelectOpc = AArch64::FCSELSrrr;
1066 SelectOpc = AArch64::FCSELDrrr;
1070 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1071 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SelectOpc),
1075 .addImm(AArch64CC::NE);
1077 UpdateValueMap(I, ResultReg);
1081 bool AArch64FastISel::SelectFPExt(const Instruction *I) {
1082 Value *V = I->getOperand(0);
1083 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
1086 unsigned Op = getRegForValue(V);
1090 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
1091 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
1092 ResultReg).addReg(Op);
1093 UpdateValueMap(I, ResultReg);
1097 bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
1098 Value *V = I->getOperand(0);
1099 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
1102 unsigned Op = getRegForValue(V);
1106 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
1107 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
1108 ResultReg).addReg(Op);
1109 UpdateValueMap(I, ResultReg);
1113 // FPToUI and FPToSI
1114 bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
1116 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1119 unsigned SrcReg = getRegForValue(I->getOperand(0));
1123 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1124 if (SrcVT == MVT::f128)
1128 if (SrcVT == MVT::f64) {
1130 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
1132 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
1135 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
1137 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
1139 unsigned ResultReg = createResultReg(
1140 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
1141 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1143 UpdateValueMap(I, ResultReg);
1147 bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
1149 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1151 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
1152 "Unexpected value type.");
1154 unsigned SrcReg = getRegForValue(I->getOperand(0));
1158 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1160 // Handle sign-extension.
1161 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
1163 EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
1168 MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass
1169 : &AArch64::GPR32RegClass);
1172 if (SrcVT == MVT::i64) {
1174 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
1176 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
1179 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
1181 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
1184 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1185 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1187 UpdateValueMap(I, ResultReg);
1191 bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
1192 SmallVectorImpl<MVT> &OutVTs,
1193 unsigned &NumBytes) {
1194 CallingConv::ID CC = CLI.CallConv;
1195 SmallVector<CCValAssign, 16> ArgLocs;
1196 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1197 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1199 // Get a count of how many bytes are to be pushed on the stack.
1200 NumBytes = CCInfo.getNextStackOffset();
1202 // Issue CALLSEQ_START
1203 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1204 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
1207 // Process the args.
1208 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1209 CCValAssign &VA = ArgLocs[i];
1210 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1211 MVT ArgVT = OutVTs[VA.getValNo()];
1213 unsigned ArgReg = getRegForValue(ArgVal);
1217 // Handle arg promotion: SExt, ZExt, AExt.
1218 switch (VA.getLocInfo()) {
1219 case CCValAssign::Full:
1221 case CCValAssign::SExt: {
1222 MVT DestVT = VA.getLocVT();
1224 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1229 case CCValAssign::AExt:
1230 // Intentional fall-through.
1231 case CCValAssign::ZExt: {
1232 MVT DestVT = VA.getLocVT();
1234 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1240 llvm_unreachable("Unknown arg promotion!");
1243 // Now copy/store arg to correct locations.
1244 if (VA.isRegLoc() && !VA.needsCustom()) {
1245 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1246 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1247 CLI.OutRegs.push_back(VA.getLocReg());
1248 } else if (VA.needsCustom()) {
1249 // FIXME: Handle custom args.
1252 assert(VA.isMemLoc() && "Assuming store on stack.");
1254 // Need to store on the stack.
1255 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
1257 unsigned BEAlign = 0;
1258 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1259 BEAlign = 8 - ArgSize;
1262 Addr.setKind(Address::RegBase);
1263 Addr.setReg(AArch64::SP);
1264 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1266 if (!EmitStore(ArgVT, ArgReg, Addr))
1273 bool AArch64FastISel::FinishCall(CallLoweringInfo &CLI, MVT RetVT,
1274 unsigned NumBytes) {
1275 CallingConv::ID CC = CLI.CallConv;
1277 // Issue CALLSEQ_END
1278 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1279 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
1280 .addImm(NumBytes).addImm(0);
1282 // Now the return value.
1283 if (RetVT != MVT::isVoid) {
1284 SmallVector<CCValAssign, 16> RVLocs;
1285 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1286 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
1288 // Only handle a single return value.
1289 if (RVLocs.size() != 1)
1292 // Copy all of the result registers out of their specified physreg.
1293 MVT CopyVT = RVLocs[0].getValVT();
1294 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1295 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1296 TII.get(TargetOpcode::COPY), ResultReg)
1297 .addReg(RVLocs[0].getLocReg());
1298 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1300 CLI.ResultReg = ResultReg;
1301 CLI.NumResultRegs = 1;
1307 bool AArch64FastISel::FastLowerCall(CallLoweringInfo &CLI) {
1308 CallingConv::ID CC = CLI.CallConv;
1309 bool IsVarArg = CLI.IsVarArg;
1310 const Value *Callee = CLI.Callee;
1311 const char *SymName = CLI.SymName;
1313 // Only handle global variable Callees.
1314 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1318 // Let SDISel handle vararg functions.
1322 // FIXME: Only handle *simple* calls for now.
1324 if (CLI.RetTy->isVoidTy())
1325 RetVT = MVT::isVoid;
1326 else if (!isTypeLegal(CLI.RetTy, RetVT))
1329 for (auto Flag : CLI.OutFlags)
1330 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1333 // Set up the argument vectors.
1334 SmallVector<MVT, 16> OutVTs;
1335 OutVTs.reserve(CLI.OutVals.size());
1337 for (auto *Val : CLI.OutVals) {
1339 if (!isTypeLegal(Val->getType(), VT) &&
1340 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1343 // We don't handle vector parameters yet.
1344 if (VT.isVector() || VT.getSizeInBits() > 64)
1347 OutVTs.push_back(VT);
1350 // Handle the arguments now that we've gotten them.
1352 if (!ProcessCallArgs(CLI, OutVTs, NumBytes))
1356 MachineInstrBuilder MIB;
1357 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BL));
1360 MIB.addGlobalAddress(GV, 0, 0);
1362 MIB.addExternalSymbol(SymName, 0);
1364 // Add implicit physical register uses to the call.
1365 for (auto Reg : CLI.OutRegs)
1366 MIB.addReg(Reg, RegState::Implicit);
1368 // Add a register mask with the call-preserved registers.
1369 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1370 MIB.addRegMask(TRI.getCallPreservedMask(CC));
1372 // Finish off the call including any return values.
1373 return FinishCall(CLI, RetVT, NumBytes);
1376 bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
1378 return Len / Alignment <= 4;
1383 bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
1384 uint64_t Len, unsigned Alignment) {
1385 // Make sure we don't bloat code by inlining very large memcpy's.
1386 if (!IsMemCpySmall(Len, Alignment))
1389 int64_t UnscaledOffset = 0;
1390 Address OrigDest = Dest;
1391 Address OrigSrc = Src;
1395 if (!Alignment || Alignment >= 8) {
1406 // Bound based on alignment.
1407 if (Len >= 4 && Alignment == 4)
1409 else if (Len >= 2 && Alignment == 2)
1418 RV = EmitLoad(VT, ResultReg, Src);
1422 RV = EmitStore(VT, ResultReg, Dest);
1426 int64_t Size = VT.getSizeInBits() / 8;
1428 UnscaledOffset += Size;
1430 // We need to recompute the unscaled offset for each iteration.
1431 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
1432 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
1438 bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
1439 // FIXME: Handle more intrinsics.
1440 switch (II->getIntrinsicID()) {
1441 default: return false;
1442 case Intrinsic::frameaddress: {
1443 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
1444 MFI->setFrameAddressIsTaken(true);
1446 const AArch64RegisterInfo *RegInfo =
1447 static_cast<const AArch64RegisterInfo *>(TM.getRegisterInfo());
1448 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
1449 unsigned SrcReg = FramePtr;
1451 // Recursively load frame address
1457 unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
1459 DestReg = createResultReg(&AArch64::GPR64RegClass);
1460 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1461 TII.get(AArch64::LDRXui), DestReg)
1462 .addReg(SrcReg).addImm(0);
1466 UpdateValueMap(II, SrcReg);
1469 case Intrinsic::memcpy:
1470 case Intrinsic::memmove: {
1471 const auto *MTI = cast<MemTransferInst>(II);
1472 // Don't handle volatile.
1473 if (MTI->isVolatile())
1476 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
1477 // we would emit dead code because we don't currently handle memmoves.
1478 bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
1479 if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
1480 // Small memcpy's are common enough that we want to do them without a call
1482 uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
1483 unsigned Alignment = MTI->getAlignment();
1484 if (IsMemCpySmall(Len, Alignment)) {
1486 if (!ComputeAddress(MTI->getRawDest(), Dest) ||
1487 !ComputeAddress(MTI->getRawSource(), Src))
1489 if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
1494 if (!MTI->getLength()->getType()->isIntegerTy(64))
1497 if (MTI->getSourceAddressSpace() > 255 || MTI->getDestAddressSpace() > 255)
1498 // Fast instruction selection doesn't support the special
1502 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1503 return LowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1505 case Intrinsic::memset: {
1506 const MemSetInst *MSI = cast<MemSetInst>(II);
1507 // Don't handle volatile.
1508 if (MSI->isVolatile())
1511 if (!MSI->getLength()->getType()->isIntegerTy(64))
1514 if (MSI->getDestAddressSpace() > 255)
1515 // Fast instruction selection doesn't support the special
1519 return LowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1521 case Intrinsic::trap: {
1522 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
1530 bool AArch64FastISel::SelectRet(const Instruction *I) {
1531 const ReturnInst *Ret = cast<ReturnInst>(I);
1532 const Function &F = *I->getParent()->getParent();
1534 if (!FuncInfo.CanLowerReturn)
1540 // Build a list of return value registers.
1541 SmallVector<unsigned, 4> RetRegs;
1543 if (Ret->getNumOperands() > 0) {
1544 CallingConv::ID CC = F.getCallingConv();
1545 SmallVector<ISD::OutputArg, 4> Outs;
1546 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1548 // Analyze operands of the call, assigning locations to each operand.
1549 SmallVector<CCValAssign, 16> ValLocs;
1550 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
1552 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
1553 : RetCC_AArch64_AAPCS;
1554 CCInfo.AnalyzeReturn(Outs, RetCC);
1556 // Only handle a single return value for now.
1557 if (ValLocs.size() != 1)
1560 CCValAssign &VA = ValLocs[0];
1561 const Value *RV = Ret->getOperand(0);
1563 // Don't bother handling odd stuff for now.
1564 if (VA.getLocInfo() != CCValAssign::Full)
1566 // Only handle register returns for now.
1569 unsigned Reg = getRegForValue(RV);
1573 unsigned SrcReg = Reg + VA.getValNo();
1574 unsigned DestReg = VA.getLocReg();
1575 // Avoid a cross-class copy. This is very unlikely.
1576 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1579 EVT RVEVT = TLI.getValueType(RV->getType());
1580 if (!RVEVT.isSimple())
1583 // Vectors (of > 1 lane) in big endian need tricky handling.
1584 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
1587 MVT RVVT = RVEVT.getSimpleVT();
1588 if (RVVT == MVT::f128)
1590 MVT DestVT = VA.getValVT();
1591 // Special handling for extended integers.
1592 if (RVVT != DestVT) {
1593 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1596 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1599 bool isZExt = Outs[0].Flags.isZExt();
1600 SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
1606 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1607 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1609 // Add register to return instruction.
1610 RetRegs.push_back(VA.getLocReg());
1613 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1614 TII.get(AArch64::RET_ReallyLR));
1615 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1616 MIB.addReg(RetRegs[i], RegState::Implicit);
1620 bool AArch64FastISel::SelectTrunc(const Instruction *I) {
1621 Type *DestTy = I->getType();
1622 Value *Op = I->getOperand(0);
1623 Type *SrcTy = Op->getType();
1625 EVT SrcEVT = TLI.getValueType(SrcTy, true);
1626 EVT DestEVT = TLI.getValueType(DestTy, true);
1627 if (!SrcEVT.isSimple())
1629 if (!DestEVT.isSimple())
1632 MVT SrcVT = SrcEVT.getSimpleVT();
1633 MVT DestVT = DestEVT.getSimpleVT();
1635 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
1638 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
1642 unsigned SrcReg = getRegForValue(Op);
1646 // If we're truncating from i64 to a smaller non-legal type then generate an
1647 // AND. Otherwise, we know the high bits are undefined and a truncate doesn't
1648 // generate any code.
1649 if (SrcVT == MVT::i64) {
1651 switch (DestVT.SimpleTy) {
1653 // Trunc i64 to i32 is handled by the target-independent fast-isel.
1665 // Issue an extract_subreg to get the lower 32-bits.
1666 unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true,
1668 MRI.constrainRegClass(Reg32, &AArch64::GPR32RegClass);
1669 // Create the AND instruction which performs the actual truncation.
1670 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
1671 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1674 .addImm(AArch64_AM::encodeLogicalImmediate(Mask, 32));
1678 UpdateValueMap(I, SrcReg);
1682 unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
1683 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
1684 DestVT == MVT::i64) &&
1685 "Unexpected value type.");
1686 // Handle i8 and i16 as i32.
1687 if (DestVT == MVT::i8 || DestVT == MVT::i16)
1691 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
1692 unsigned ResultReg = createResultReg(&AArch64::GPR32spRegClass);
1693 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1696 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1698 if (DestVT == MVT::i64) {
1699 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
1700 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
1701 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1702 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1703 TII.get(AArch64::SUBREG_TO_REG), Reg64)
1706 .addImm(AArch64::sub_32);
1711 if (DestVT == MVT::i64) {
1712 // FIXME: We're SExt i1 to i64.
1715 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1716 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SBFMWri),
1725 unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1727 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
1729 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1730 // DestVT are odd things, so test to make sure that they are both types we can
1731 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1732 // bail out to SelectionDAG.
1733 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
1734 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
1735 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
1736 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
1742 switch (SrcVT.SimpleTy) {
1746 return Emiti1Ext(SrcReg, DestVT, isZExt);
1748 if (DestVT == MVT::i64)
1749 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
1751 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
1755 if (DestVT == MVT::i64)
1756 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
1758 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
1762 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
1763 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
1768 // Handle i8 and i16 as i32.
1769 if (DestVT == MVT::i8 || DestVT == MVT::i16)
1771 else if (DestVT == MVT::i64) {
1772 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1773 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1774 TII.get(AArch64::SUBREG_TO_REG), Src64)
1777 .addImm(AArch64::sub_32);
1781 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1782 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1790 bool AArch64FastISel::SelectIntExt(const Instruction *I) {
1791 // On ARM, in general, integer casts don't involve legal types; this code
1792 // handles promotable integers. The high bits for a type smaller than
1793 // the register size are assumed to be undefined.
1794 Type *DestTy = I->getType();
1795 Value *Src = I->getOperand(0);
1796 Type *SrcTy = Src->getType();
1798 bool isZExt = isa<ZExtInst>(I);
1799 unsigned SrcReg = getRegForValue(Src);
1803 EVT SrcEVT = TLI.getValueType(SrcTy, true);
1804 EVT DestEVT = TLI.getValueType(DestTy, true);
1805 if (!SrcEVT.isSimple())
1807 if (!DestEVT.isSimple())
1810 MVT SrcVT = SrcEVT.getSimpleVT();
1811 MVT DestVT = DestEVT.getSimpleVT();
1812 unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
1815 UpdateValueMap(I, ResultReg);
1819 bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
1820 EVT DestEVT = TLI.getValueType(I->getType(), true);
1821 if (!DestEVT.isSimple())
1824 MVT DestVT = DestEVT.getSimpleVT();
1825 if (DestVT != MVT::i64 && DestVT != MVT::i32)
1829 bool is64bit = (DestVT == MVT::i64);
1830 switch (ISDOpcode) {
1834 DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
1837 DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
1840 unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
1841 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1845 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1849 unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
1850 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg)
1853 // The remainder is computed as numerator - (quotient * denominator) using the
1854 // MSUB instruction.
1855 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1856 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
1860 UpdateValueMap(I, ResultReg);
1864 bool AArch64FastISel::SelectMul(const Instruction *I) {
1865 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1866 if (!SrcEVT.isSimple())
1868 MVT SrcVT = SrcEVT.getSimpleVT();
1870 // Must be simple value type. Don't handle vectors.
1871 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
1877 switch (SrcVT.SimpleTy) {
1883 ZReg = AArch64::WZR;
1884 Opc = AArch64::MADDWrrr;
1888 ZReg = AArch64::XZR;
1889 Opc = AArch64::MADDXrrr;
1893 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1897 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1901 // Create the base instruction, then add the operands.
1902 unsigned ResultReg = createResultReg(TLI.getRegClassFor(SrcVT));
1903 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1907 UpdateValueMap(I, ResultReg);
1911 bool AArch64FastISel::TargetSelectInstruction(const Instruction *I) {
1912 switch (I->getOpcode()) {
1915 case Instruction::Load:
1916 return SelectLoad(I);
1917 case Instruction::Store:
1918 return SelectStore(I);
1919 case Instruction::Br:
1920 return SelectBranch(I);
1921 case Instruction::IndirectBr:
1922 return SelectIndirectBr(I);
1923 case Instruction::FCmp:
1924 case Instruction::ICmp:
1925 return SelectCmp(I);
1926 case Instruction::Select:
1927 return SelectSelect(I);
1928 case Instruction::FPExt:
1929 return SelectFPExt(I);
1930 case Instruction::FPTrunc:
1931 return SelectFPTrunc(I);
1932 case Instruction::FPToSI:
1933 return SelectFPToInt(I, /*Signed=*/true);
1934 case Instruction::FPToUI:
1935 return SelectFPToInt(I, /*Signed=*/false);
1936 case Instruction::SIToFP:
1937 return SelectIntToFP(I, /*Signed=*/true);
1938 case Instruction::UIToFP:
1939 return SelectIntToFP(I, /*Signed=*/false);
1940 case Instruction::SRem:
1941 return SelectRem(I, ISD::SREM);
1942 case Instruction::URem:
1943 return SelectRem(I, ISD::UREM);
1944 case Instruction::Ret:
1945 return SelectRet(I);
1946 case Instruction::Trunc:
1947 return SelectTrunc(I);
1948 case Instruction::ZExt:
1949 case Instruction::SExt:
1950 return SelectIntExt(I);
1951 case Instruction::Mul:
1952 // FIXME: This really should be handled by the target-independent selector.
1953 return SelectMul(I);
1956 // Silence warnings.
1957 (void)&CC_AArch64_DarwinPCS_VarArg;
1961 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
1962 const TargetLibraryInfo *libInfo) {
1963 return new AArch64FastISel(funcInfo, libInfo);