1 //=- AArch64ConditionOptimizer.cpp - Remove useless comparisons for AArch64 -=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass tries to make consecutive compares of values use same operands to
11 // allow CSE pass to remove duplicated instructions. For this it analyzes
12 // branches and adjusts comparisons with immediate values by converting:
17 // and adjusting immediate values appropriately. It basically corrects two
18 // immediate values towards each other to make them equal.
20 // Consider the following example in C:
22 // if ((a < 5 && ...) || (a > 5 && ...)) {
27 // Here both "x" and "y" expressions compare "a" with "5". When "x" evaluates
28 // to "false", "y" can just check flags set by the first comparison. As a
29 // result of the canonicalization employed by
30 // SelectionDAGBuilder::visitSwitchCase, DAGCombine, and other target-specific
31 // code, assembly ends up in the form that is not CSE friendly:
42 // Same assembly after the pass:
49 // cmp w8, #5 // <-- CSE pass removes this instruction
53 // Currently only SUBS and ADDS followed by b.?? are supported.
55 // TODO: maybe handle TBNZ/TBZ the same way as CMP when used instead for "a < 0"
56 // TODO: handle other conditional instructions (e.g. CSET)
57 // TODO: allow second branching to be anything if it doesn't require adjusting
59 //===----------------------------------------------------------------------===//
62 #include "llvm/ADT/DepthFirstIterator.h"
63 #include "llvm/ADT/SmallVector.h"
64 #include "llvm/ADT/Statistic.h"
65 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
66 #include "llvm/CodeGen/MachineDominators.h"
67 #include "llvm/CodeGen/MachineFunction.h"
68 #include "llvm/CodeGen/MachineFunctionPass.h"
69 #include "llvm/CodeGen/MachineInstrBuilder.h"
70 #include "llvm/CodeGen/MachineRegisterInfo.h"
71 #include "llvm/CodeGen/Passes.h"
72 #include "llvm/Support/CommandLine.h"
73 #include "llvm/Support/Debug.h"
74 #include "llvm/Support/raw_ostream.h"
75 #include "llvm/Target/TargetInstrInfo.h"
76 #include "llvm/Target/TargetSubtargetInfo.h"
82 #define DEBUG_TYPE "aarch64-condopt"
84 STATISTIC(NumConditionsAdjusted, "Number of conditions adjusted");
87 class AArch64ConditionOptimizer : public MachineFunctionPass {
88 const TargetInstrInfo *TII;
89 MachineDominatorTree *DomTree;
90 const MachineRegisterInfo *MRI;
93 // Stores immediate, compare instruction opcode and branch condition (in this
94 // order) of adjusted comparison.
95 typedef std::tuple<int, unsigned, AArch64CC::CondCode> CmpInfo;
98 AArch64ConditionOptimizer() : MachineFunctionPass(ID) {}
99 void getAnalysisUsage(AnalysisUsage &AU) const override;
100 MachineInstr *findSuitableCompare(MachineBasicBlock *MBB);
101 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
102 void modifyCmp(MachineInstr *CmpMI, const CmpInfo &Info);
103 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
105 bool runOnMachineFunction(MachineFunction &MF) override;
106 const char *getPassName() const override {
107 return "AArch64 Condition Optimizer";
110 } // end anonymous namespace
112 char AArch64ConditionOptimizer::ID = 0;
115 void initializeAArch64ConditionOptimizerPass(PassRegistry &);
118 INITIALIZE_PASS_BEGIN(AArch64ConditionOptimizer, "aarch64-condopt",
119 "AArch64 CondOpt Pass", false, false)
120 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
121 INITIALIZE_PASS_END(AArch64ConditionOptimizer, "aarch64-condopt",
122 "AArch64 CondOpt Pass", false, false)
124 FunctionPass *llvm::createAArch64ConditionOptimizerPass() {
125 return new AArch64ConditionOptimizer();
128 void AArch64ConditionOptimizer::getAnalysisUsage(AnalysisUsage &AU) const {
129 AU.addRequired<MachineDominatorTree>();
130 AU.addPreserved<MachineDominatorTree>();
131 MachineFunctionPass::getAnalysisUsage(AU);
134 // Finds compare instruction that corresponds to supported types of branching.
135 // Returns the instruction or nullptr on failures or detecting unsupported
137 MachineInstr *AArch64ConditionOptimizer::findSuitableCompare(
138 MachineBasicBlock *MBB) {
139 MachineBasicBlock::iterator I = MBB->getFirstTerminator();
143 if (I->getOpcode() != AArch64::Bcc)
146 // Now find the instruction controlling the terminator.
147 for (MachineBasicBlock::iterator B = MBB->begin(); I != B;) {
149 assert(!I->isTerminator() && "Spurious terminator");
150 switch (I->getOpcode()) {
151 // cmp is an alias for subs with a dead destination register.
152 case AArch64::SUBSWri:
153 case AArch64::SUBSXri:
154 // cmn is an alias for adds with a dead destination register.
155 case AArch64::ADDSWri:
156 case AArch64::ADDSXri:
157 if (MRI->use_empty(I->getOperand(0).getReg()))
160 DEBUG(dbgs() << "Destination of cmp is not dead, " << *I << '\n');
163 // Prevent false positive case like:
169 case AArch64::FCMPDri:
170 case AArch64::FCMPSri:
171 case AArch64::FCMPESri:
172 case AArch64::FCMPEDri:
174 case AArch64::SUBSWrr:
175 case AArch64::SUBSXrr:
176 case AArch64::ADDSWrr:
177 case AArch64::ADDSXrr:
178 case AArch64::FCMPSrr:
179 case AArch64::FCMPDrr:
180 case AArch64::FCMPESrr:
181 case AArch64::FCMPEDrr:
182 // Skip comparison instructions without immediate operands.
186 DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n');
190 // Changes opcode adds <-> subs considering register operand width.
191 static int getComplementOpc(int Opc) {
193 case AArch64::ADDSWri: return AArch64::SUBSWri;
194 case AArch64::ADDSXri: return AArch64::SUBSXri;
195 case AArch64::SUBSWri: return AArch64::ADDSWri;
196 case AArch64::SUBSXri: return AArch64::ADDSXri;
198 llvm_unreachable("Unexpected opcode");
202 // Changes form of comparison inclusive <-> exclusive.
203 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) {
205 case AArch64CC::GT: return AArch64CC::GE;
206 case AArch64CC::GE: return AArch64CC::GT;
207 case AArch64CC::LT: return AArch64CC::LE;
208 case AArch64CC::LE: return AArch64CC::LT;
210 llvm_unreachable("Unexpected condition code");
214 // Transforms GT -> GE, GE -> GT, LT -> LE, LE -> LT by updating comparison
215 // operator and condition code.
216 AArch64ConditionOptimizer::CmpInfo AArch64ConditionOptimizer::adjustCmp(
217 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) {
218 unsigned Opc = CmpMI->getOpcode();
220 // CMN (compare with negative immediate) is an alias to ADDS (as
221 // "operand - negative" == "operand + positive")
222 bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri);
224 int Correction = (Cmp == AArch64CC::GT) ? 1 : -1;
225 // Negate Correction value for comparison with negative immediate (CMN).
227 Correction = -Correction;
230 const int OldImm = (int)CmpMI->getOperand(2).getImm();
231 const int NewImm = std::abs(OldImm + Correction);
233 // Handle +0 -> -1 and -0 -> +1 (CMN with 0 immediate) transitions by
234 // adjusting compare instruction opcode.
235 if (OldImm == 0 && ((Negative && Correction == 1) ||
236 (!Negative && Correction == -1))) {
237 Opc = getComplementOpc(Opc);
240 return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));
243 // Applies changes to comparison instruction suggested by adjustCmp().
244 void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI,
245 const CmpInfo &Info) {
248 AArch64CC::CondCode Cmp;
249 std::tie(Imm, Opc, Cmp) = Info;
251 MachineBasicBlock *const MBB = CmpMI->getParent();
253 // Change immediate in comparison instruction (ADDS or SUBS).
254 BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc))
255 .addOperand(CmpMI->getOperand(0))
256 .addOperand(CmpMI->getOperand(1))
258 .addOperand(CmpMI->getOperand(3));
259 CmpMI->eraseFromParent();
261 // The fact that this comparison was picked ensures that it's related to the
262 // first terminator instruction.
263 MachineInstr *BrMI = MBB->getFirstTerminator();
265 // Change condition in branch instruction.
266 BuildMI(*MBB, BrMI, BrMI->getDebugLoc(), TII->get(AArch64::Bcc))
268 .addOperand(BrMI->getOperand(1));
269 BrMI->eraseFromParent();
271 MBB->updateTerminator();
273 ++NumConditionsAdjusted;
276 // Parse a condition code returned by AnalyzeBranch, and compute the CondCode
277 // corresponding to TBB.
278 // Returns true if parsing was successful, otherwise false is returned.
279 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
280 // A normal br.cond simply has the condition code.
281 if (Cond[0].getImm() != -1) {
282 assert(Cond.size() == 1 && "Unknown Cond array format");
283 CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
289 // Adjusts one cmp instruction to another one if result of adjustment will allow
290 // CSE. Returns true if compare instruction was changed, otherwise false is
292 bool AArch64ConditionOptimizer::adjustTo(MachineInstr *CmpMI,
293 AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm)
295 CmpInfo Info = adjustCmp(CmpMI, Cmp);
296 if (std::get<0>(Info) == ToImm && std::get<1>(Info) == To->getOpcode()) {
297 modifyCmp(CmpMI, Info);
303 bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) {
304 DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
305 << "********** Function: " << MF.getName() << '\n');
306 TII = MF.getSubtarget().getInstrInfo();
307 DomTree = &getAnalysis<MachineDominatorTree>();
308 MRI = &MF.getRegInfo();
310 bool Changed = false;
312 // Visit blocks in dominator tree pre-order. The pre-order enables multiple
313 // cmp-conversions from the same head block.
314 // Note that updateDomTree() modifies the children of the DomTree node
315 // currently being visited. The df_iterator supports that; it doesn't look at
316 // child_begin() / child_end() until after a node has been visited.
317 for (MachineDomTreeNode *I : depth_first(DomTree)) {
318 MachineBasicBlock *HBB = I->getBlock();
320 SmallVector<MachineOperand, 4> HeadCond;
321 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
322 if (TII->AnalyzeBranch(*HBB, TBB, FBB, HeadCond)) {
326 // Equivalence check is to skip loops.
327 if (!TBB || TBB == HBB) {
331 SmallVector<MachineOperand, 4> TrueCond;
332 MachineBasicBlock *TBB_TBB = nullptr, *TBB_FBB = nullptr;
333 if (TII->AnalyzeBranch(*TBB, TBB_TBB, TBB_FBB, TrueCond)) {
337 MachineInstr *HeadCmpMI = findSuitableCompare(HBB);
342 MachineInstr *TrueCmpMI = findSuitableCompare(TBB);
347 AArch64CC::CondCode HeadCmp;
348 if (HeadCond.empty() || !parseCond(HeadCond, HeadCmp)) {
352 AArch64CC::CondCode TrueCmp;
353 if (TrueCond.empty() || !parseCond(TrueCond, TrueCmp)) {
357 const int HeadImm = (int)HeadCmpMI->getOperand(2).getImm();
358 const int TrueImm = (int)TrueCmpMI->getOperand(2).getImm();
360 DEBUG(dbgs() << "Head branch:\n");
361 DEBUG(dbgs() << "\tcondition: "
362 << AArch64CC::getCondCodeName(HeadCmp) << '\n');
363 DEBUG(dbgs() << "\timmediate: " << HeadImm << '\n');
365 DEBUG(dbgs() << "True branch:\n");
366 DEBUG(dbgs() << "\tcondition: "
367 << AArch64CC::getCondCodeName(TrueCmp) << '\n');
368 DEBUG(dbgs() << "\timmediate: " << TrueImm << '\n');
370 if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::LT) ||
371 (HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::GT)) &&
372 std::abs(TrueImm - HeadImm) == 2) {
373 // This branch transforms machine instructions that correspond to
375 // 1) (a > {TrueImm} && ...) || (a < {HeadImm} && ...)
376 // 2) (a < {TrueImm} && ...) || (a > {HeadImm} && ...)
380 // 1) (a >= {NewImm} && ...) || (a <= {NewImm} && ...)
381 // 2) (a <= {NewImm} && ...) || (a >= {NewImm} && ...)
383 CmpInfo HeadCmpInfo = adjustCmp(HeadCmpMI, HeadCmp);
384 CmpInfo TrueCmpInfo = adjustCmp(TrueCmpMI, TrueCmp);
385 if (std::get<0>(HeadCmpInfo) == std::get<0>(TrueCmpInfo) &&
386 std::get<1>(HeadCmpInfo) == std::get<1>(TrueCmpInfo)) {
387 modifyCmp(HeadCmpMI, HeadCmpInfo);
388 modifyCmp(TrueCmpMI, TrueCmpInfo);
391 } else if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::GT) ||
392 (HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::LT)) &&
393 std::abs(TrueImm - HeadImm) == 1) {
394 // This branch transforms machine instructions that correspond to
396 // 1) (a > {TrueImm} && ...) || (a > {HeadImm} && ...)
397 // 2) (a < {TrueImm} && ...) || (a < {HeadImm} && ...)
401 // 1) (a <= {NewImm} && ...) || (a > {NewImm} && ...)
402 // 2) (a < {NewImm} && ...) || (a >= {NewImm} && ...)
404 // GT -> GE transformation increases immediate value, so picking the
405 // smaller one; LT -> LE decreases immediate value so invert the choice.
406 bool adjustHeadCond = (HeadImm < TrueImm);
407 if (HeadCmp == AArch64CC::LT) {
408 adjustHeadCond = !adjustHeadCond;
411 if (adjustHeadCond) {
412 Changed |= adjustTo(HeadCmpMI, HeadCmp, TrueCmpMI, TrueImm);
414 Changed |= adjustTo(TrueCmpMI, TrueCmp, HeadCmpMI, HeadImm);
417 // Other transformation cases almost never occur due to generation of < or >
418 // comparisons instead of <= and >=.