1 //===-- AArch64AsmPrinter.cpp - Print machine code to an AArch64 .s file --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format AArch64 assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "AArch64AsmPrinter.h"
17 #include "InstPrinter/AArch64InstPrinter.h"
18 #include "llvm/DebugInfo.h"
19 #include "llvm/ADT/SmallString.h"
20 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/Mangler.h"
31 AArch64AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
32 // See emitFrameIndexDebugValue in InstrInfo for where this instruction is
33 // expected to be created.
34 assert(MI->getNumOperands() == 4 && MI->getOperand(0).isReg()
35 && MI->getOperand(1).isImm() && "unexpected custom DBG_VALUE");
36 return MachineLocation(MI->getOperand(0).getReg(),
37 MI->getOperand(1).getImm());
40 /// Try to print a floating-point register as if it belonged to a specified
41 /// register-class. For example the inline asm operand modifier "b" requires its
42 /// argument to be printed as "bN".
43 static bool printModifiedFPRAsmOperand(const MachineOperand &MO,
44 const TargetRegisterInfo *TRI,
45 const TargetRegisterClass &RegClass,
50 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
51 if (RegClass.contains(*AR)) {
52 O << AArch64InstPrinter::getRegisterName(*AR);
59 /// Implements the 'w' and 'x' inline asm operand modifiers, which print a GPR
60 /// with the obvious type and an immediate 0 as either wzr or xzr.
61 static bool printModifiedGPRAsmOperand(const MachineOperand &MO,
62 const TargetRegisterInfo *TRI,
63 const TargetRegisterClass &RegClass,
65 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
67 if (MO.isImm() && MO.getImm() == 0) {
70 } else if (MO.isReg()) {
71 if (MO.getReg() == AArch64::XSP || MO.getReg() == AArch64::WSP) {
72 O << (Prefix == 'x' ? "sp" : "wsp");
76 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
77 if (RegClass.contains(*AR)) {
78 O << AArch64InstPrinter::getRegisterName(*AR);
87 bool AArch64AsmPrinter::printSymbolicAddress(const MachineOperand &MO,
88 bool PrintImmediatePrefix,
89 StringRef Suffix, raw_ostream &O) {
92 switch (MO.getType()) {
94 llvm_unreachable("Unexpected operand for symbolic address constraint");
95 case MachineOperand::MO_GlobalAddress:
96 Name = Mang->getSymbol(MO.getGlobal())->getName();
98 // Global variables may be accessed either via a GOT or in various fun and
99 // interesting TLS-model specific ways. Set the prefix modifier as
101 if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal())) {
102 Reloc::Model RelocM = TM.getRelocationModel();
103 if (GV->isThreadLocal()) {
104 switch (TM.getTLSModel(GV)) {
105 case TLSModel::GeneralDynamic:
106 Modifier = "tlsdesc";
108 case TLSModel::LocalDynamic:
111 case TLSModel::InitialExec:
112 Modifier = "gottprel";
114 case TLSModel::LocalExec:
118 } else if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
123 case MachineOperand::MO_BlockAddress:
124 Name = GetBlockAddressSymbol(MO.getBlockAddress())->getName();
126 case MachineOperand::MO_ExternalSymbol:
127 Name = MO.getSymbolName();
129 case MachineOperand::MO_ConstantPoolIndex:
130 Name = GetCPISymbol(MO.getIndex())->getName();
134 // Some instructions (notably ADRP) don't take the # prefix for
135 // immediates. Only print it if asked to.
136 if (PrintImmediatePrefix)
139 // Only need the joining "_" if both the prefix and the suffix are
140 // non-null. This little block simply takes care of the four possibly
141 // combinations involved there.
142 if (Modifier == "" && Suffix == "")
144 else if (Modifier == "" && Suffix != "")
145 O << ":" << Suffix << ':' << Name;
146 else if (Modifier != "" && Suffix == "")
147 O << ":" << Modifier << ':' << Name;
149 O << ":" << Modifier << '_' << Suffix << ':' << Name;
154 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
156 const char *ExtraCode, raw_ostream &O) {
157 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
158 if (!ExtraCode || !ExtraCode[0]) {
159 // There's actually no operand modifier, which leads to a slightly eclectic
160 // set of behaviour which we have to handle here.
161 const MachineOperand &MO = MI->getOperand(OpNum);
162 switch (MO.getType()) {
164 llvm_unreachable("Unexpected operand for inline assembly");
165 case MachineOperand::MO_Register:
166 // GCC prints the unmodified operand of a 'w' constraint as the vector
167 // register. Technically, we could allocate the argument as a VPR128, but
168 // that leads to extremely dodgy copies being generated to get the data
170 if (printModifiedFPRAsmOperand(MO, TRI, AArch64::VPR128RegClass, O))
171 O << AArch64InstPrinter::getRegisterName(MO.getReg());
173 case MachineOperand::MO_Immediate:
174 O << '#' << MO.getImm();
176 case MachineOperand::MO_FPImmediate:
177 assert(MO.getFPImm()->isExactlyValue(0.0) && "Only FP 0.0 expected");
180 case MachineOperand::MO_BlockAddress:
181 case MachineOperand::MO_ConstantPoolIndex:
182 case MachineOperand::MO_GlobalAddress:
183 case MachineOperand::MO_ExternalSymbol:
184 return printSymbolicAddress(MO, false, "", O);
189 // We have a real modifier to handle.
190 switch(ExtraCode[0]) {
192 // See if this is a generic operand
193 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
194 case 'c': // Don't print "#" before an immediate operand.
195 if (!MI->getOperand(OpNum).isImm())
197 O << MI->getOperand(OpNum).getImm();
200 // Output 32-bit general register operand, constant zero as wzr, or stack
201 // pointer as wsp. Ignored when used with other operand types.
202 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
203 AArch64::GPR32RegClass, O);
205 // Output 64-bit general register operand, constant zero as xzr, or stack
206 // pointer as sp. Ignored when used with other operand types.
207 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
208 AArch64::GPR64RegClass, O);
210 // Output higher numbered of a 64-bit general register pair
212 // Output least significant register of a 64-bit general register pair
214 // Output most significant register of a 64-bit general register pair
216 // FIXME note: these three operand modifiers will require, to some extent,
217 // adding a paired GPR64 register class. Initial investigation suggests that
218 // assertions are hit unless it has a type and is made legal for that type
219 // in ISelLowering. After that step is made, the number of modifications
220 // needed explodes (operation legality, calling conventions, stores, reg
222 llvm_unreachable("FIXME: Unimplemented register pairs");
224 // Output 8-bit FP/SIMD scalar register operand, prefixed with b.
225 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
226 AArch64::FPR8RegClass, O);
228 // Output 16-bit FP/SIMD scalar register operand, prefixed with h.
229 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
230 AArch64::FPR16RegClass, O);
232 // Output 32-bit FP/SIMD scalar register operand, prefixed with s.
233 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
234 AArch64::FPR32RegClass, O);
236 // Output 64-bit FP/SIMD scalar register operand, prefixed with d.
237 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
238 AArch64::FPR64RegClass, O);
240 // Output 128-bit FP/SIMD scalar register operand, prefixed with q.
241 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
242 AArch64::FPR128RegClass, O);
244 // Output symbolic address with appropriate relocation modifier (also
245 // suitable for ADRP).
246 return printSymbolicAddress(MI->getOperand(OpNum), false, "", O);
248 // Output bits 11:0 of symbolic address with appropriate :lo12: relocation
250 return printSymbolicAddress(MI->getOperand(OpNum), true, "lo12", O);
252 // Output bits 23:12 of symbolic address with appropriate :hi12: relocation
253 // modifier (currently only for TLS local exec).
254 return printSymbolicAddress(MI->getOperand(OpNum), true, "hi12", O);
260 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
263 const char *ExtraCode,
265 // Currently both the memory constraints (m and Q) behave the same and amount
266 // to the address as a single register. In future, we may allow "m" to provide
267 // both a base and an offset.
268 const MachineOperand &MO = MI->getOperand(OpNum);
269 assert(MO.isReg() && "unexpected inline assembly memory operand");
270 O << '[' << AArch64InstPrinter::getRegisterName(MO.getReg()) << ']';
274 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
276 unsigned NOps = MI->getNumOperands();
278 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
279 // cast away const; DIetc do not take const operands for some reason.
280 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
283 // Frame address. Currently handles register +- offset only.
284 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
285 OS << '[' << AArch64InstPrinter::getRegisterName(MI->getOperand(0).getReg());
286 OS << '+' << MI->getOperand(1).getImm();
288 OS << "+" << MI->getOperand(NOps - 2).getImm();
292 #include "AArch64GenMCPseudoLowering.inc"
294 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
295 // Do any auto-generated pseudo lowerings.
296 if (emitPseudoExpansionLowering(OutStreamer, MI))
299 switch (MI->getOpcode()) {
300 case AArch64::DBG_VALUE: {
301 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
302 SmallString<128> TmpStr;
303 raw_svector_ostream OS(TmpStr);
304 PrintDebugValueComment(MI, OS);
305 OutStreamer.EmitRawText(StringRef(OS.str()));
312 LowerAArch64MachineInstrToMCInst(MI, TmpInst, *this);
313 OutStreamer.EmitInstruction(TmpInst);
316 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
317 if (Subtarget->isTargetELF()) {
318 const TargetLoweringObjectFileELF &TLOFELF =
319 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
321 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
323 // Output stubs for external and common global variables.
324 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
325 if (!Stubs.empty()) {
326 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
327 const DataLayout *TD = TM.getDataLayout();
329 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
330 OutStreamer.EmitLabel(Stubs[i].first);
331 OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(),
332 TD->getPointerSize(0), 0);
339 bool AArch64AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
340 return AsmPrinter::runOnMachineFunction(MF);
343 // Force static initialization.
344 extern "C" void LLVMInitializeAArch64AsmPrinter() {
345 RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64Target);