1 //===-- AArch64A53Fix835769.cpp -------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This pass changes code to work around Cortex-A53 erratum 835769.
10 // It works around it by inserting a nop instruction in code sequences that
11 // in some circumstances may trigger the erratum.
12 // It inserts a nop instruction between a sequence of the following 2 classes
14 // instr 1: mem-instr (including loads, stores and prefetches).
15 // instr 2: non-SIMD integer multiply-accumulate writing 64-bit X registers.
16 //===----------------------------------------------------------------------===//
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Target/TargetInstrInfo.h"
31 #define DEBUG_TYPE "aarch64-fix-cortex-a53-835769"
33 STATISTIC(NumNopsAdded, "Number of Nops added to work around erratum 835769");
35 //===----------------------------------------------------------------------===//
38 // Is the instruction a match for the instruction that comes first in the
39 // sequence of instructions that can trigger the erratum?
40 static bool isFirstInstructionInSequence(MachineInstr *MI) {
41 // Must return true if this instruction is a load, a store or a prefetch.
42 switch (MI->getOpcode()) {
44 case AArch64::PRFMroW:
45 case AArch64::PRFMroX:
50 return (MI->mayLoad() || MI->mayStore());
54 // Is the instruction a match for the instruction that comes second in the
55 // sequence that can trigger the erratum?
56 static bool isSecondInstructionInSequence(MachineInstr *MI) {
57 // Must return true for non-SIMD integer multiply-accumulates, writing
58 // to a 64-bit register.
59 switch (MI->getOpcode()) {
60 // Erratum cannot be triggered when the destination register is 32 bits,
61 // therefore only include the following.
62 case AArch64::MSUBXrrr:
63 case AArch64::MADDXrrr:
64 case AArch64::SMADDLrrr:
65 case AArch64::SMSUBLrrr:
66 case AArch64::UMADDLrrr:
67 case AArch64::UMSUBLrrr:
68 // Erratum can only be triggered by multiply-adds, not by regular
69 // non-accumulating multiplies, i.e. when Ra=XZR='11111'
70 return MI->getOperand(3).getReg() != AArch64::XZR;
77 //===----------------------------------------------------------------------===//
80 class AArch64A53Fix835769 : public MachineFunctionPass {
81 const TargetInstrInfo *TII;
85 explicit AArch64A53Fix835769() : MachineFunctionPass(ID) {}
87 bool runOnMachineFunction(MachineFunction &F) override;
89 const char *getPassName() const override {
90 return "Workaround A53 erratum 835769 pass";
93 void getAnalysisUsage(AnalysisUsage &AU) const override {
95 MachineFunctionPass::getAnalysisUsage(AU);
99 bool runOnBasicBlock(MachineBasicBlock &MBB);
101 char AArch64A53Fix835769::ID = 0;
103 } // end anonymous namespace
105 //===----------------------------------------------------------------------===//
108 AArch64A53Fix835769::runOnMachineFunction(MachineFunction &F) {
109 DEBUG(dbgs() << "***** AArch64A53Fix835769 *****\n");
110 bool Changed = false;
111 TII = F.getSubtarget().getInstrInfo();
113 for (auto &MBB : F) {
114 Changed |= runOnBasicBlock(MBB);
119 // Return the block that was fallen through to get to MBB, if any,
120 // otherwise nullptr.
121 static MachineBasicBlock *getBBFallenThrough(MachineBasicBlock *MBB,
122 const TargetInstrInfo *TII) {
123 // Get the previous machine basic block in the function.
124 MachineFunction::iterator MBBI = *MBB;
126 // Can't go off top of function.
127 if (MBBI == MBB->getParent()->begin())
130 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
131 SmallVector<MachineOperand, 2> Cond;
133 MachineBasicBlock *PrevBB = std::prev(MBBI);
134 for (MachineBasicBlock *S : MBB->predecessors())
135 if (S == PrevBB && !TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond) &&
142 // Iterate through fallen through blocks trying to find a previous non-pseudo if
143 // there is one, otherwise return nullptr. Only look for instructions in
144 // previous blocks, not the current block, since we only use this to look at
146 static MachineInstr *getLastNonPseudo(MachineBasicBlock &MBB,
147 const TargetInstrInfo *TII) {
148 MachineBasicBlock *FMBB = &MBB;
150 // If there is no non-pseudo in the current block, loop back around and try
151 // the previous block (if there is one).
152 while ((FMBB = getBBFallenThrough(FMBB, TII))) {
153 for (auto I = FMBB->rbegin(), E = FMBB->rend(); I != E; ++I) {
159 // There was no previous non-pseudo in the fallen through blocks
163 static void insertNopBeforeInstruction(MachineBasicBlock &MBB, MachineInstr* MI,
164 const TargetInstrInfo *TII) {
165 // If we are the first instruction of the block, put the NOP at the end of
166 // the previous fallthrough block
167 if (MI == &MBB.front()) {
168 MachineInstr *I = getLastNonPseudo(MBB, TII);
169 assert(I && "Expected instruction");
170 DebugLoc DL = I->getDebugLoc();
171 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
174 DebugLoc DL = MI->getDebugLoc();
175 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0);
182 AArch64A53Fix835769::runOnBasicBlock(MachineBasicBlock &MBB) {
183 bool Changed = false;
184 DEBUG(dbgs() << "Running on MBB: " << MBB << " - scanning instructions...\n");
186 // First, scan the basic block, looking for a sequence of 2 instructions
187 // that match the conditions under which the erratum may trigger.
189 // List of terminating instructions in matching sequences
190 std::vector<MachineInstr*> Sequences;
192 MachineInstr *PrevInstr = nullptr;
194 // Try and find the last non-pseudo instruction in any fallen through blocks,
195 // if there isn't one, then we use nullptr to represent that.
196 PrevInstr = getLastNonPseudo(MBB, TII);
198 for (auto &MI : MBB) {
199 MachineInstr *CurrInstr = &MI;
200 DEBUG(dbgs() << " Examining: " << MI);
202 DEBUG(dbgs() << " PrevInstr: " << *PrevInstr
203 << " CurrInstr: " << *CurrInstr
204 << " isFirstInstructionInSequence(PrevInstr): "
205 << isFirstInstructionInSequence(PrevInstr) << "\n"
206 << " isSecondInstructionInSequence(CurrInstr): "
207 << isSecondInstructionInSequence(CurrInstr) << "\n");
208 if (isFirstInstructionInSequence(PrevInstr) &&
209 isSecondInstructionInSequence(CurrInstr)) {
210 DEBUG(dbgs() << " ** pattern found at Idx " << Idx << "!\n");
211 Sequences.push_back(CurrInstr);
214 if (!CurrInstr->isPseudo())
215 PrevInstr = CurrInstr;
219 DEBUG(dbgs() << "Scan complete, "<< Sequences.size()
220 << " occurences of pattern found.\n");
222 // Then update the basic block, inserting nops between the detected sequences.
223 for (auto &MI : Sequences) {
225 insertNopBeforeInstruction(MBB, MI, TII);
231 // Factory function used by AArch64TargetMachine to add the pass to
233 FunctionPass *llvm::createAArch64A53Fix835769() {
234 return new AArch64A53Fix835769();