lib/Target/AArch64/AArch64.td

   1 //===- AArch64.td - Describe the AArch64 Target Machine -------*- tblgen -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the AArch64 target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // Target-independent interfaces
  16 //===----------------------------------------------------------------------===//
  17
  18 include "llvm/Target/Target.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // AArch64 Subtarget features.
  22 //
  23
  24 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  25   "Enable ARMv8 FP">;
  26
  27 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  28   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  29
  30 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  31   "Enable cryptographic instructions">;
  32
  33 //===----------------------------------------------------------------------===//
  34 // AArch64 Processors
  35 //
  36
  37 include "AArch64Schedule.td"
  38
  39 class ProcNoItin<string Name, list<SubtargetFeature> Features>
  40  : Processor<Name, NoItineraries, Features>;
  41
  42 def : Processor<"generic", GenericItineraries, [FeatureFPARMv8, FeatureNEON]>;
  43
  44 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
  45                                    "Cortex-A53 ARM processors",
  46                                    [FeatureFPARMv8,
  47                                    FeatureNEON,
  48                                    FeatureCrypto]>;
  49
  50 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
  51                                    "Cortex-A57 ARM processors",
  52                                    [FeatureFPARMv8,
  53                                    FeatureNEON,
  54                                    FeatureCrypto]>;
  55
  56 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
  57 def : Processor<"cortex-a57", NoItineraries, [ProcA57]>;
  58
  59 //===----------------------------------------------------------------------===//
  60 // Register File Description
  61 //===----------------------------------------------------------------------===//
  62
  63 include "AArch64RegisterInfo.td"
  64
  65 include "AArch64CallingConv.td"
  66
  67 //===----------------------------------------------------------------------===//
  68 // Instruction Descriptions
  69 //===----------------------------------------------------------------------===//
  70
  71 include "AArch64InstrInfo.td"
  72
  73 def AArch64InstrInfo : InstrInfo;
  74
  75 //===----------------------------------------------------------------------===//
  76 // Declare the target which we are implementing
  77 //===----------------------------------------------------------------------===//
  78
  79 def AArch64 : Target {
  80   let InstructionSet = AArch64InstrInfo;
  81 }