1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30 "Enable cryptographic instructions">;
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 /// Cyclone has register move instructions which are "free".
36 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
37 "Has zero-cycle register moves">;
39 /// Cyclone has instructions which zero registers for "free".
40 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
41 "Has zero-cycle zeroing instructions">;
43 //===----------------------------------------------------------------------===//
47 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
48 "Support ARM v8.1a instructions", [FeatureCRC]>;
50 //===----------------------------------------------------------------------===//
51 // Register File Description
52 //===----------------------------------------------------------------------===//
54 include "AArch64RegisterInfo.td"
55 include "AArch64CallingConvention.td"
57 //===----------------------------------------------------------------------===//
58 // Instruction Descriptions
59 //===----------------------------------------------------------------------===//
61 include "AArch64Schedule.td"
62 include "AArch64InstrInfo.td"
64 def AArch64InstrInfo : InstrInfo;
66 //===----------------------------------------------------------------------===//
67 // AArch64 Processors supported.
69 include "AArch64SchedA53.td"
70 include "AArch64SchedA57.td"
71 include "AArch64SchedCyclone.td"
73 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
74 "Cortex-A53 ARM processors",
80 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
81 "Cortex-A57 ARM processors",
87 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
93 FeatureZCRegMove, FeatureZCZeroing]>;
95 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
99 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
100 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
101 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
102 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
103 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
105 //===----------------------------------------------------------------------===//
107 //===----------------------------------------------------------------------===//
109 def GenericAsmParserVariant : AsmParserVariant {
111 string Name = "generic";
114 def AppleAsmParserVariant : AsmParserVariant {
116 string Name = "apple-neon";
119 //===----------------------------------------------------------------------===//
121 //===----------------------------------------------------------------------===//
122 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
123 // AsmWriter bits get associated with the correct class.
124 def GenericAsmWriter : AsmWriter {
125 string AsmWriterClassName = "InstPrinter";
126 int PassSubtarget = 1;
128 bit isMCAsmWriter = 1;
131 def AppleAsmWriter : AsmWriter {
132 let AsmWriterClassName = "AppleInstPrinter";
133 int PassSubtarget = 1;
135 int isMCAsmWriter = 1;
138 //===----------------------------------------------------------------------===//
139 // Target Declaration
140 //===----------------------------------------------------------------------===//
142 def AArch64 : Target {
143 let InstructionSet = AArch64InstrInfo;
144 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
145 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];