1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/DataStream.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 #define DEBUG_TYPE "host-detection"
44 //===----------------------------------------------------------------------===//
46 // Implementations of the CPU detection routines
48 //===----------------------------------------------------------------------===//
52 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
53 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
55 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
56 /// specified arguments. If we can't run cpuid on the host, return true.
57 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
58 unsigned *rECX, unsigned *rEDX) {
59 #if defined(__GNUC__) || defined(__clang__)
60 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
61 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
62 asm ("movq\t%%rbx, %%rsi\n\t"
64 "xchgq\t%%rbx, %%rsi\n\t"
71 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
72 asm ("movl\t%%ebx, %%esi\n\t"
74 "xchgl\t%%ebx, %%esi\n\t"
81 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
82 // postprocessed code that looks like "return true; return false;")
86 #elif defined(_MSC_VER)
87 // The MSVC intrinsic is portable across x86 and x64.
89 __cpuid(registers, value);
100 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
101 /// 4 values in the specified arguments. If we can't run cpuid on the host,
103 static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
104 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
106 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
107 #if defined(__GNUC__)
108 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
109 asm ("movq\t%%rbx, %%rsi\n\t"
111 "xchgq\t%%rbx, %%rsi\n\t"
119 #elif defined(_MSC_VER)
120 // __cpuidex was added in MSVC++ 9.0 SP1
121 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
123 __cpuidex(registers, value, subleaf);
124 *rEAX = registers[0];
125 *rEBX = registers[1];
126 *rECX = registers[2];
127 *rEDX = registers[3];
135 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
136 #if defined(__GNUC__)
137 asm ("movl\t%%ebx, %%esi\n\t"
139 "xchgl\t%%ebx, %%esi\n\t"
147 #elif defined(_MSC_VER)
153 mov dword ptr [esi],eax
155 mov dword ptr [esi],ebx
157 mov dword ptr [esi],ecx
159 mov dword ptr [esi],edx
170 static bool OSHasAVXSupport() {
171 #if defined(__GNUC__)
172 // Check xgetbv; this uses a .byte sequence instead of the instruction
173 // directly because older assemblers do not include support for xgetbv and
174 // there is no easy way to conditionally compile based on the assembler used.
176 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
177 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
178 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
180 int rEAX = 0; // Ensures we return false
182 return (rEAX & 6) == 6;
185 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
187 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
188 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
189 if (Family == 6 || Family == 0xf) {
191 // Examine extended family ID if family ID is F.
192 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
193 // Examine extended model ID if family ID is 6 or F.
194 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
198 StringRef sys::getHostCPUName() {
199 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
200 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
204 DetectX86FamilyModel(EAX, Family, Model);
211 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
213 unsigned MaxLeaf = EAX;
214 bool HasSSE3 = (ECX & 0x1);
215 bool HasSSE41 = (ECX & 0x80000);
216 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
217 // indicates that the AVX registers will be saved and restored on context
218 // switch, then we have full AVX support.
219 const unsigned AVXBits = (1 << 27) | (1 << 28);
220 bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
221 bool HasAVX2 = HasAVX && MaxLeaf >= 0x7 &&
222 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX) &&
224 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
225 bool Em64T = (EDX >> 29) & 0x1;
226 bool HasTBM = (ECX >> 21) & 0x1;
228 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
234 case 0: // Intel486 DX processors
235 case 1: // Intel486 DX processors
236 case 2: // Intel486 SX processors
237 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
238 // IntelDX2 processors
239 case 4: // Intel486 SL processor
240 case 5: // IntelSX2 processors
241 case 7: // Write-Back Enhanced IntelDX2 processors
242 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
243 default: return "i486";
247 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
248 // Pentium processors (60, 66)
249 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
250 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
252 case 3: // Pentium OverDrive processors for Intel486 processor-based
256 case 4: // Pentium OverDrive processor with MMX technology for Pentium
257 // processor (75, 90, 100, 120, 133), Pentium processor with
258 // MMX technology (166, 200)
259 return "pentium-mmx";
261 default: return "pentium";
265 case 1: // Pentium Pro processor
268 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
270 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
271 // model 05, and Intel Celeron processor, model 05
272 case 6: // Celeron processor, model 06
275 case 7: // Pentium III processor, model 07, and Pentium III Xeon
276 // processor, model 07
277 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
278 // model 08, and Celeron processor, model 08
279 case 10: // Pentium III Xeon processor, model 0Ah
280 case 11: // Pentium III processor, model 0Bh
283 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
284 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
285 // 0Dh. All processors are manufactured using the 90 nm process.
288 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
289 // 0Eh. All processors are manufactured using the 65 nm process.
292 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
293 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
294 // mobile processor, Intel Core 2 Extreme processor, Intel
295 // Pentium Dual-Core processor, Intel Xeon processor, model
296 // 0Fh. All processors are manufactured using the 65 nm process.
297 case 22: // Intel Celeron processor model 16h. All processors are
298 // manufactured using the 65 nm process
301 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
302 // Integrated Processor with Intel QuickAssist Technology
303 return "i686"; // FIXME: ???
305 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
306 // 17h. All processors are manufactured using the 45 nm process.
308 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
309 // Not all Penryn processors support SSE 4.1 (such as the Pentium brand)
310 return HasSSE41 ? "penryn" : "core2";
312 case 26: // Intel Core i7 processor and Intel Xeon processor. All
313 // processors are manufactured using the 45 nm process.
314 case 29: // Intel Xeon processor MP. All processors are manufactured using
315 // the 45 nm process.
316 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
317 // As found in a Summer 2010 model iMac.
318 case 37: // Intel Core i7, laptop version.
319 case 44: // Intel Core i7 processor and Intel Xeon processor. All
320 // processors are manufactured using the 32 nm process.
321 case 46: // Nehalem EX
322 case 47: // Westmere EX
326 case 42: // Intel Core i7 processor. All processors are manufactured
327 // using the 32 nm process.
329 // Not all Sandy Bridge processors support AVX (such as the Pentium
330 // versions instead of the i7 versions).
331 return HasAVX ? "corei7-avx" : "corei7";
335 case 62: // Ivy Bridge EP
336 // Not all Ivy Bridge processors support AVX (such as the Pentium
337 // versions instead of the i7 versions).
338 return HasAVX ? "core-avx-i" : "corei7";
345 // Not all Haswell processors support AVX too (such as the Pentium
346 // versions instead of the i7 versions).
347 return HasAVX2 ? "core-avx2" : "corei7";
349 case 28: // Most 45 nm Intel Atom processors
350 case 38: // 45 nm Atom Lincroft
351 case 39: // 32 nm Atom Medfield
352 case 53: // 32 nm Atom Midview
353 case 54: // 32 nm Atom Midview
356 // Atom Silvermont codes from the Intel software optimization guide.
362 default: return (Em64T) ? "x86-64" : "i686";
366 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
367 // model 00h and manufactured using the 0.18 micron process.
368 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
369 // processor MP, and Intel Celeron processor. All processors are
370 // model 01h and manufactured using the 0.18 micron process.
371 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
372 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
373 // processor, and Mobile Intel Celeron processor. All processors
374 // are model 02h and manufactured using the 0.13 micron process.
375 return (Em64T) ? "x86-64" : "pentium4";
377 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
378 // processor. All processors are model 03h and manufactured using
379 // the 90 nm process.
380 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
381 // Pentium D processor, Intel Xeon processor, Intel Xeon
382 // processor MP, Intel Celeron D processor. All processors are
383 // model 04h and manufactured using the 90 nm process.
384 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
385 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
386 // MP, Intel Celeron D processor. All processors are model 06h
387 // and manufactured using the 65 nm process.
388 return (Em64T) ? "nocona" : "prescott";
391 return (Em64T) ? "x86-64" : "pentium4";
398 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
399 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
400 // appears to be no way to generate the wide variety of AMD-specific targets
401 // from the information returned from CPUID.
409 case 8: return "k6-2";
411 case 13: return "k6-3";
412 case 10: return "geode";
413 default: return "pentium";
417 case 4: return "athlon-tbird";
420 case 8: return "athlon-mp";
421 case 10: return "athlon-xp";
422 default: return "athlon";
428 case 1: return "opteron";
429 case 5: return "athlon-fx"; // also opteron
430 default: return "athlon64";
437 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
440 return "bdver4"; // 50h-6Fh: Excavator
442 return "bdver3"; // 30h-3Fh: Steamroller
443 if (Model >= 0x10 || HasTBM)
444 return "bdver2"; // 10h-1Fh: Piledriver
445 return "bdver1"; // 00h-0Fh: Bulldozer
447 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
456 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
457 StringRef sys::getHostCPUName() {
458 host_basic_info_data_t hostInfo;
459 mach_msg_type_number_t infoCount;
461 infoCount = HOST_BASIC_INFO_COUNT;
462 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
465 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
467 switch(hostInfo.cpu_subtype) {
468 case CPU_SUBTYPE_POWERPC_601: return "601";
469 case CPU_SUBTYPE_POWERPC_602: return "602";
470 case CPU_SUBTYPE_POWERPC_603: return "603";
471 case CPU_SUBTYPE_POWERPC_603e: return "603e";
472 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
473 case CPU_SUBTYPE_POWERPC_604: return "604";
474 case CPU_SUBTYPE_POWERPC_604e: return "604e";
475 case CPU_SUBTYPE_POWERPC_620: return "620";
476 case CPU_SUBTYPE_POWERPC_750: return "750";
477 case CPU_SUBTYPE_POWERPC_7400: return "7400";
478 case CPU_SUBTYPE_POWERPC_7450: return "7450";
479 case CPU_SUBTYPE_POWERPC_970: return "970";
485 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
486 StringRef sys::getHostCPUName() {
487 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
488 // and so we must use an operating-system interface to determine the current
489 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
490 const char *generic = "generic";
492 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
493 // memory buffer because the 'file' has 0 size (it can be read from only
497 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
499 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
503 // The cpu line is second (after the 'processor: 0' line), so if this
504 // buffer is too small then something has changed (or is wrong).
506 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
509 const char *CPUInfoStart = buffer;
510 const char *CPUInfoEnd = buffer + CPUInfoSize;
512 const char *CIP = CPUInfoStart;
514 const char *CPUStart = 0;
517 // We need to find the first line which starts with cpu, spaces, and a colon.
518 // After the colon, there may be some additional spaces and then the cpu type.
519 while (CIP < CPUInfoEnd && CPUStart == 0) {
520 if (CIP < CPUInfoEnd && *CIP == '\n')
523 if (CIP < CPUInfoEnd && *CIP == 'c') {
525 if (CIP < CPUInfoEnd && *CIP == 'p') {
527 if (CIP < CPUInfoEnd && *CIP == 'u') {
529 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
532 if (CIP < CPUInfoEnd && *CIP == ':') {
534 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
537 if (CIP < CPUInfoEnd) {
539 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
540 *CIP != ',' && *CIP != '\n'))
542 CPULen = CIP - CPUStart;
550 while (CIP < CPUInfoEnd && *CIP != '\n')
557 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
558 .Case("604e", "604e")
560 .Case("7400", "7400")
561 .Case("7410", "7400")
562 .Case("7447", "7400")
563 .Case("7455", "7450")
565 .Case("POWER4", "970")
566 .Case("PPC970FX", "970")
567 .Case("PPC970MP", "970")
569 .Case("POWER5", "g5")
571 .Case("POWER6", "pwr6")
572 .Case("POWER7", "pwr7")
575 #elif defined(__linux__) && defined(__arm__)
576 StringRef sys::getHostCPUName() {
577 // The cpuid register on arm is not accessible from user space. On Linux,
578 // it is exposed through the /proc/cpuinfo file.
579 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
580 // memory buffer because the 'file' has 0 size (it can be read from only
584 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
586 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
590 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
593 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
596 StringRef Str(buffer, CPUInfoSize);
598 SmallVector<StringRef, 32> Lines;
599 Str.split(Lines, "\n");
601 // Look for the CPU implementer line.
602 StringRef Implementer;
603 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
604 if (Lines[I].startswith("CPU implementer"))
605 Implementer = Lines[I].substr(15).ltrim("\t :");
607 if (Implementer == "0x41") // ARM Ltd.
608 // Look for the CPU part line.
609 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
610 if (Lines[I].startswith("CPU part"))
611 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
612 // values correspond to the "Part number" in the CP15/c0 register. The
613 // contents are specified in the various processor manuals.
614 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
615 .Case("0x926", "arm926ej-s")
616 .Case("0xb02", "mpcore")
617 .Case("0xb36", "arm1136j-s")
618 .Case("0xb56", "arm1156t2-s")
619 .Case("0xb76", "arm1176jz-s")
620 .Case("0xc08", "cortex-a8")
621 .Case("0xc09", "cortex-a9")
622 .Case("0xc0f", "cortex-a15")
623 .Case("0xc20", "cortex-m0")
624 .Case("0xc23", "cortex-m3")
625 .Case("0xc24", "cortex-m4")
628 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
629 // Look for the CPU part line.
630 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
631 if (Lines[I].startswith("CPU part"))
632 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
633 // values correspond to the "Part number" in the CP15/c0 register. The
634 // contents are specified in the various processor manuals.
635 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
636 .Case("0x06f", "krait") // APQ8064
641 #elif defined(__linux__) && defined(__s390x__)
642 StringRef sys::getHostCPUName() {
643 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
644 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
645 // memory buffer because the 'file' has 0 size (it can be read from only
649 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
651 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
655 // The "processor 0:" line comes after a fair amount of other information,
656 // including a cache breakdown, but this should be plenty.
658 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
661 StringRef Str(buffer, CPUInfoSize);
662 SmallVector<StringRef, 32> Lines;
663 Str.split(Lines, "\n");
664 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
665 if (Lines[I].startswith("processor ")) {
666 size_t Pos = Lines[I].find("machine = ");
667 if (Pos != StringRef::npos) {
668 Pos += sizeof("machine = ") - 1;
670 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
684 StringRef sys::getHostCPUName() {
689 #if defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
690 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
692 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
694 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
698 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
701 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
704 StringRef Str(buffer, CPUInfoSize);
706 SmallVector<StringRef, 32> Lines;
707 Str.split(Lines, "\n");
709 SmallVector<StringRef, 32> CPUFeatures;
711 // Look for the CPU features.
712 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
713 if (Lines[I].startswith("Features")) {
714 Lines[I].split(CPUFeatures, " ");
718 #if defined(__aarch64__)
719 // Keep track of which crypto features we have seen
729 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
730 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
731 #if defined(__aarch64__)
732 .Case("asimd", "neon")
733 .Case("fp", "fp-armv8")
734 .Case("crc32", "crc")
736 .Case("half", "fp16")
737 .Case("neon", "neon")
738 .Case("vfpv3", "vfp3")
739 .Case("vfpv3d16", "d16")
740 .Case("vfpv4", "vfp4")
741 .Case("idiva", "hwdiv-arm")
742 .Case("idivt", "hwdiv")
746 #if defined(__aarch64__)
747 // We need to check crypto separately since we need all of the crypto
748 // extensions to enable the subtarget feature
749 if (CPUFeatures[I] == "aes")
751 else if (CPUFeatures[I] == "pmull")
753 else if (CPUFeatures[I] == "sha1")
755 else if (CPUFeatures[I] == "sha2")
759 if (LLVMFeatureStr != "")
760 Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
763 #if defined(__aarch64__)
764 // If we have all crypto bits we can add the feature
765 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
766 Features.GetOrCreateValue("crypto").setValue(true);
772 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
777 std::string sys::getProcessTriple() {
778 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
780 if (sizeof(void *) == 8 && PT.isArch32Bit())
781 PT = PT.get64BitArchVariant();
782 if (sizeof(void *) == 4 && PT.isArch64Bit())
783 PT = PT.get32BitArchVariant();