1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This header file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/DataStream.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 //===----------------------------------------------------------------------===//
44 // Implementations of the CPU detection routines
46 //===----------------------------------------------------------------------===//
50 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
51 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
53 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
54 /// specified arguments. If we can't run cpuid on the host, return true.
55 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
56 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
57 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
59 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
60 asm ("movq\t%%rbx, %%rsi\n\t"
62 "xchgq\t%%rbx, %%rsi\n\t"
69 #elif defined(_MSC_VER)
71 __cpuid(registers, value);
80 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
82 asm ("movl\t%%ebx, %%esi\n\t"
84 "xchgl\t%%ebx, %%esi\n\t"
91 #elif defined(_MSC_VER)
96 mov dword ptr [esi],eax
98 mov dword ptr [esi],ebx
100 mov dword ptr [esi],ecx
102 mov dword ptr [esi],edx
105 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
106 // postprocessed code that looks like "return true; return false;")
115 static bool OSHasAVXSupport() {
\r
116 #if defined(__GNUC__)
\r
118 __asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
\r
119 #elif defined(_MSC_VER)
\r
120 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
\r
122 int rEAX = 0; // Ensures we return false
\r
124 return (rEAX & 6) == 6;
\r
127 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
129 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
130 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
131 if (Family == 6 || Family == 0xf) {
133 // Examine extended family ID if family ID is F.
134 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
135 // Examine extended model ID if family ID is 6 or F.
136 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
140 std::string sys::getHostCPUName() {
141 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
142 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
146 DetectX86FamilyModel(EAX, Family, Model);
148 bool HasSSE3 = (ECX & 0x1);
149 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
150 // indicates that the AVX registers will be saved and restored on context
151 // switch, when we have full AVX support.
152 bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport();
153 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
154 bool Em64T = (EDX >> 29) & 0x1;
161 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
162 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
168 case 0: // Intel486 DX processors
169 case 1: // Intel486 DX processors
170 case 2: // Intel486 SX processors
171 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
172 // IntelDX2 processors
173 case 4: // Intel486 SL processor
174 case 5: // IntelSX2 processors
175 case 7: // Write-Back Enhanced IntelDX2 processors
176 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
177 default: return "i486";
181 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
182 // Pentium processors (60, 66)
183 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
184 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
186 case 3: // Pentium OverDrive processors for Intel486 processor-based
190 case 4: // Pentium OverDrive processor with MMX technology for Pentium
191 // processor (75, 90, 100, 120, 133), Pentium processor with
192 // MMX technology (166, 200)
193 return "pentium-mmx";
195 default: return "pentium";
199 case 1: // Pentium Pro processor
202 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
204 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
205 // model 05, and Intel Celeron processor, model 05
206 case 6: // Celeron processor, model 06
209 case 7: // Pentium III processor, model 07, and Pentium III Xeon
210 // processor, model 07
211 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
212 // model 08, and Celeron processor, model 08
213 case 10: // Pentium III Xeon processor, model 0Ah
214 case 11: // Pentium III processor, model 0Bh
217 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
218 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
219 // 0Dh. All processors are manufactured using the 90 nm process.
222 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
223 // 0Eh. All processors are manufactured using the 65 nm process.
226 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
227 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
228 // mobile processor, Intel Core 2 Extreme processor, Intel
229 // Pentium Dual-Core processor, Intel Xeon processor, model
230 // 0Fh. All processors are manufactured using the 65 nm process.
231 case 22: // Intel Celeron processor model 16h. All processors are
232 // manufactured using the 65 nm process
235 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
236 // Integrated Processor with Intel QuickAssist Technology
237 return "i686"; // FIXME: ???
239 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
240 // 17h. All processors are manufactured using the 45 nm process.
242 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
245 case 26: // Intel Core i7 processor and Intel Xeon processor. All
246 // processors are manufactured using the 45 nm process.
247 case 29: // Intel Xeon processor MP. All processors are manufactured using
248 // the 45 nm process.
249 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
250 // As found in a Summer 2010 model iMac.
251 case 37: // Intel Core i7, laptop version.
252 case 44: // Intel Core i7 processor and Intel Xeon processor. All
253 // processors are manufactured using the 32 nm process.
254 case 46: // Nehalem EX
255 case 47: // Westmere EX
259 case 42: // Intel Core i7 processor. All processors are manufactured
260 // using the 32 nm process.
262 // Not all Sandy Bridge processors support AVX (such as the Pentium
263 // versions instead of the i7 versions).
264 return HasAVX ? "corei7-avx" : "corei7";
268 // Not all Ivy Bridge processors support AVX (such as the Pentium
269 // versions instead of the i7 versions).
270 return HasAVX ? "core-avx-i" : "corei7";
272 case 28: // Most 45 nm Intel Atom processors
273 case 38: // 45 nm Atom Lincroft
274 case 39: // 32 nm Atom Medfield
275 case 53: // 32 nm Atom Midview
276 case 54: // 32 nm Atom Midview
279 default: return (Em64T) ? "x86-64" : "i686";
283 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
284 // model 00h and manufactured using the 0.18 micron process.
285 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
286 // processor MP, and Intel Celeron processor. All processors are
287 // model 01h and manufactured using the 0.18 micron process.
288 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
289 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
290 // processor, and Mobile Intel Celeron processor. All processors
291 // are model 02h and manufactured using the 0.13 micron process.
292 return (Em64T) ? "x86-64" : "pentium4";
294 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
295 // processor. All processors are model 03h and manufactured using
296 // the 90 nm process.
297 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
298 // Pentium D processor, Intel Xeon processor, Intel Xeon
299 // processor MP, Intel Celeron D processor. All processors are
300 // model 04h and manufactured using the 90 nm process.
301 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
302 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
303 // MP, Intel Celeron D processor. All processors are model 06h
304 // and manufactured using the 65 nm process.
305 return (Em64T) ? "nocona" : "prescott";
308 return (Em64T) ? "x86-64" : "pentium4";
315 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
316 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
317 // appears to be no way to generate the wide variety of AMD-specific targets
318 // from the information returned from CPUID.
326 case 8: return "k6-2";
328 case 13: return "k6-3";
329 case 10: return "geode";
330 default: return "pentium";
334 case 4: return "athlon-tbird";
337 case 8: return "athlon-mp";
338 case 10: return "athlon-xp";
339 default: return "athlon";
345 case 1: return "opteron";
346 case 5: return "athlon-fx"; // also opteron
347 default: return "athlon64";
356 else if (Model <= 31)
364 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
365 std::string sys::getHostCPUName() {
366 host_basic_info_data_t hostInfo;
367 mach_msg_type_number_t infoCount;
369 infoCount = HOST_BASIC_INFO_COUNT;
370 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
373 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
375 switch(hostInfo.cpu_subtype) {
376 case CPU_SUBTYPE_POWERPC_601: return "601";
377 case CPU_SUBTYPE_POWERPC_602: return "602";
378 case CPU_SUBTYPE_POWERPC_603: return "603";
379 case CPU_SUBTYPE_POWERPC_603e: return "603e";
380 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
381 case CPU_SUBTYPE_POWERPC_604: return "604";
382 case CPU_SUBTYPE_POWERPC_604e: return "604e";
383 case CPU_SUBTYPE_POWERPC_620: return "620";
384 case CPU_SUBTYPE_POWERPC_750: return "750";
385 case CPU_SUBTYPE_POWERPC_7400: return "7400";
386 case CPU_SUBTYPE_POWERPC_7450: return "7450";
387 case CPU_SUBTYPE_POWERPC_970: return "970";
393 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
394 std::string sys::getHostCPUName() {
395 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
396 // and so we must use an operating-system interface to determine the current
397 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
398 const char *generic = "generic";
400 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
401 // memory buffer because the 'file' has 0 size (it can be read from only
405 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
407 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
411 // The cpu line is second (after the 'processor: 0' line), so if this
412 // buffer is too small then something has changed (or is wrong).
414 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
417 const char *CPUInfoStart = buffer;
418 const char *CPUInfoEnd = buffer + CPUInfoSize;
420 const char *CIP = CPUInfoStart;
422 const char *CPUStart = 0;
425 // We need to find the first line which starts with cpu, spaces, and a colon.
426 // After the colon, there may be some additional spaces and then the cpu type.
427 while (CIP < CPUInfoEnd && CPUStart == 0) {
428 if (CIP < CPUInfoEnd && *CIP == '\n')
431 if (CIP < CPUInfoEnd && *CIP == 'c') {
433 if (CIP < CPUInfoEnd && *CIP == 'p') {
435 if (CIP < CPUInfoEnd && *CIP == 'u') {
437 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
440 if (CIP < CPUInfoEnd && *CIP == ':') {
442 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
445 if (CIP < CPUInfoEnd) {
447 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
448 *CIP != ',' && *CIP != '\n'))
450 CPULen = CIP - CPUStart;
458 while (CIP < CPUInfoEnd && *CIP != '\n')
465 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
466 .Case("604e", "604e")
468 .Case("7400", "7400")
469 .Case("7410", "7400")
470 .Case("7447", "7400")
471 .Case("7455", "7450")
473 .Case("POWER4", "970")
474 .Case("PPC970FX", "970")
475 .Case("PPC970MP", "970")
477 .Case("POWER5", "g5")
479 .Case("POWER6", "pwr6")
480 .Case("POWER7", "pwr7")
483 #elif defined(__linux__) && defined(__arm__)
484 std::string sys::getHostCPUName() {
485 // The cpuid register on arm is not accessible from user space. On Linux,
486 // it is exposed through the /proc/cpuinfo file.
487 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
488 // memory buffer because the 'file' has 0 size (it can be read from only
492 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
494 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
498 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
501 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
504 StringRef Str(buffer, CPUInfoSize);
506 SmallVector<StringRef, 32> Lines;
507 Str.split(Lines, "\n");
509 // Look for the CPU implementer line.
510 StringRef Implementer;
511 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
512 if (Lines[I].startswith("CPU implementer"))
513 Implementer = Lines[I].substr(15).ltrim("\t :");
515 if (Implementer == "0x41") // ARM Ltd.
516 // Look for the CPU part line.
517 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
518 if (Lines[I].startswith("CPU part"))
519 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
520 // values correspond to the "Part number" in the CP15/c0 register. The
521 // contents are specified in the various processor manuals.
522 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
523 .Case("0x926", "arm926ej-s")
524 .Case("0xb02", "mpcore")
525 .Case("0xb36", "arm1136j-s")
526 .Case("0xb56", "arm1156t2-s")
527 .Case("0xb76", "arm1176jz-s")
528 .Case("0xc08", "cortex-a8")
529 .Case("0xc09", "cortex-a9")
530 .Case("0xc0f", "cortex-a15")
531 .Case("0xc20", "cortex-m0")
532 .Case("0xc23", "cortex-m3")
533 .Case("0xc24", "cortex-m4")
539 std::string sys::getHostCPUName() {
544 #if defined(__linux__) && defined(__arm__)
545 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
547 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
549 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
553 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
556 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
559 StringRef Str(buffer, CPUInfoSize);
561 SmallVector<StringRef, 32> Lines;
562 Str.split(Lines, "\n");
564 // Look for the CPU implementer line.
565 StringRef Implementer;
566 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
567 if (Lines[I].startswith("CPU implementer"))
568 Implementer = Lines[I].substr(15).ltrim("\t :");
570 if (Implementer == "0x41") { // ARM Ltd.
571 SmallVector<StringRef, 32> CPUFeatures;
573 // Look for the CPU features.
574 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
575 if (Lines[I].startswith("Features")) {
576 Lines[I].split(CPUFeatures, " ");
580 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
581 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
582 .Case("half", "fp16")
583 .Case("neon", "neon")
584 .Case("vfpv3", "vfp3")
585 .Case("vfpv3d16", "d16")
586 .Case("vfpv4", "vfp4")
587 .Case("idiva", "hwdiv-arm")
588 .Case("idivt", "hwdiv")
591 if (LLVMFeatureStr != "")
592 Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
601 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
606 std::string sys::getProcessTriple() {
607 Triple PT(LLVM_HOSTTRIPLE);
609 if (sizeof(void *) == 8 && PT.isArch32Bit())
610 PT = PT.get64BitArchVariant();
611 if (sizeof(void *) == 4 && PT.isArch64Bit())
612 PT = PT.get32BitArchVariant();