1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/FileSystem.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 #define DEBUG_TYPE "host-detection"
44 //===----------------------------------------------------------------------===//
46 // Implementations of the CPU detection routines
48 //===----------------------------------------------------------------------===//
52 #if defined(__linux__)
53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
54 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
55 // memory buffer because the 'file' has 0 size (it can be read from only
59 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD);
61 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n");
64 int Ret = read(FD, Buf, Size);
65 int CloseStatus = close(FD);
72 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
73 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
75 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
76 /// specified arguments. If we can't run cpuid on the host, return true.
77 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
78 unsigned *rECX, unsigned *rEDX) {
79 #if defined(__GNUC__) || defined(__clang__)
80 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
81 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
82 asm ("movq\t%%rbx, %%rsi\n\t"
84 "xchgq\t%%rbx, %%rsi\n\t"
91 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
92 asm ("movl\t%%ebx, %%esi\n\t"
94 "xchgl\t%%ebx, %%esi\n\t"
101 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
102 // postprocessed code that looks like "return true; return false;")
106 #elif defined(_MSC_VER)
107 // The MSVC intrinsic is portable across x86 and x64.
109 __cpuid(registers, value);
110 *rEAX = registers[0];
111 *rEBX = registers[1];
112 *rECX = registers[2];
113 *rEDX = registers[3];
120 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
121 /// 4 values in the specified arguments. If we can't run cpuid on the host,
123 static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
124 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
126 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
127 #if defined(__GNUC__)
128 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
129 asm ("movq\t%%rbx, %%rsi\n\t"
131 "xchgq\t%%rbx, %%rsi\n\t"
139 #elif defined(_MSC_VER)
141 __cpuidex(registers, value, subleaf);
142 *rEAX = registers[0];
143 *rEBX = registers[1];
144 *rECX = registers[2];
145 *rEDX = registers[3];
150 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
151 #if defined(__GNUC__)
152 asm ("movl\t%%ebx, %%esi\n\t"
154 "xchgl\t%%ebx, %%esi\n\t"
162 #elif defined(_MSC_VER)
168 mov dword ptr [esi],eax
170 mov dword ptr [esi],ebx
172 mov dword ptr [esi],ecx
174 mov dword ptr [esi],edx
185 static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) {
186 #if defined(__GNUC__)
187 // Check xgetbv; this uses a .byte sequence instead of the instruction
188 // directly because older assemblers do not include support for xgetbv and
189 // there is no easy way to conditionally compile based on the assembler used.
190 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (*rEAX), "=d" (*rEDX) : "c" (0));
192 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
193 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
195 *rEDX = Result >> 32;
202 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
204 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
205 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
206 if (Family == 6 || Family == 0xf) {
208 // Examine extended family ID if family ID is F.
209 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
210 // Examine extended model ID if family ID is 6 or F.
211 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
215 StringRef sys::getHostCPUName() {
216 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
217 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
221 DetectX86FamilyModel(EAX, Family, Model);
229 GetX86CpuIDAndInfo(0, &MaxLeaf, text.u+0, text.u+2, text.u+1);
231 bool HasMMX = (EDX >> 23) & 1;
232 bool HasSSE = (EDX >> 25) & 1;
233 bool HasSSE2 = (EDX >> 26) & 1;
234 bool HasSSE3 = (ECX >> 0) & 1;
235 bool HasSSSE3 = (ECX >> 9) & 1;
236 bool HasSSE41 = (ECX >> 19) & 1;
237 bool HasSSE42 = (ECX >> 20) & 1;
238 bool HasMOVBE = (ECX >> 22) & 1;
239 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
240 // indicates that the AVX registers will be saved and restored on context
241 // switch, then we have full AVX support.
242 const unsigned AVXBits = (1 << 27) | (1 << 28);
243 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) &&
244 ((EAX & 0x6) == 0x6);
245 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
246 bool HasLeaf7 = MaxLeaf >= 0x7 &&
247 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
248 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
249 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
250 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
252 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
253 bool Em64T = (EDX >> 29) & 0x1;
254 bool HasTBM = (ECX >> 21) & 0x1;
256 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
262 case 0: // Intel486 DX processors
263 case 1: // Intel486 DX processors
264 case 2: // Intel486 SX processors
265 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
266 // IntelDX2 processors
267 case 4: // Intel486 SL processor
268 case 5: // IntelSX2 processors
269 case 7: // Write-Back Enhanced IntelDX2 processors
270 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
271 default: return "i486";
275 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
276 // Pentium processors (60, 66)
277 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
278 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
280 case 3: // Pentium OverDrive processors for Intel486 processor-based
284 case 4: // Pentium OverDrive processor with MMX technology for Pentium
285 // processor (75, 90, 100, 120, 133), Pentium processor with
286 // MMX technology (166, 200)
287 return "pentium-mmx";
289 default: return "pentium";
293 case 1: // Pentium Pro processor
296 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
298 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
299 // model 05, and Intel Celeron processor, model 05
300 case 6: // Celeron processor, model 06
303 case 7: // Pentium III processor, model 07, and Pentium III Xeon
304 // processor, model 07
305 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
306 // model 08, and Celeron processor, model 08
307 case 10: // Pentium III Xeon processor, model 0Ah
308 case 11: // Pentium III processor, model 0Bh
311 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
312 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
313 // 0Dh. All processors are manufactured using the 90 nm process.
314 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
315 // Integrated Processor with Intel QuickAssist Technology
318 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
319 // 0Eh. All processors are manufactured using the 65 nm process.
322 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
323 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
324 // mobile processor, Intel Core 2 Extreme processor, Intel
325 // Pentium Dual-Core processor, Intel Xeon processor, model
326 // 0Fh. All processors are manufactured using the 65 nm process.
327 case 22: // Intel Celeron processor model 16h. All processors are
328 // manufactured using the 65 nm process
331 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
332 // 17h. All processors are manufactured using the 45 nm process.
334 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
335 case 29: // Intel Xeon processor MP. All processors are manufactured using
336 // the 45 nm process.
339 case 26: // Intel Core i7 processor and Intel Xeon processor. All
340 // processors are manufactured using the 45 nm process.
341 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
342 // As found in a Summer 2010 model iMac.
343 case 46: // Nehalem EX
345 case 37: // Intel Core i7, laptop version.
346 case 44: // Intel Core i7 processor and Intel Xeon processor. All
347 // processors are manufactured using the 32 nm process.
348 case 47: // Westmere EX
352 case 42: // Intel Core i7 processor. All processors are manufactured
353 // using the 32 nm process.
355 return "sandybridge";
359 case 62: // Ivy Bridge EP
373 case 28: // Most 45 nm Intel Atom processors
374 case 38: // 45 nm Atom Lincroft
375 case 39: // 32 nm Atom Medfield
376 case 53: // 32 nm Atom Midview
377 case 54: // 32 nm Atom Midview
380 // Atom Silvermont codes from the Intel software optimization guide.
387 default: // Unknown family 6 CPU, try to guess.
395 return "sandybridge";
397 return HasMOVBE ? "silvermont" : "nehalem";
401 return HasMOVBE ? "bonnell" : "core2";
414 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
415 // model 00h and manufactured using the 0.18 micron process.
416 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
417 // processor MP, and Intel Celeron processor. All processors are
418 // model 01h and manufactured using the 0.18 micron process.
419 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
420 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
421 // processor, and Mobile Intel Celeron processor. All processors
422 // are model 02h and manufactured using the 0.13 micron process.
423 return (Em64T) ? "x86-64" : "pentium4";
425 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
426 // processor. All processors are model 03h and manufactured using
427 // the 90 nm process.
428 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
429 // Pentium D processor, Intel Xeon processor, Intel Xeon
430 // processor MP, Intel Celeron D processor. All processors are
431 // model 04h and manufactured using the 90 nm process.
432 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
433 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
434 // MP, Intel Celeron D processor. All processors are model 06h
435 // and manufactured using the 65 nm process.
436 return (Em64T) ? "nocona" : "prescott";
439 return (Em64T) ? "x86-64" : "pentium4";
446 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
447 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
448 // appears to be no way to generate the wide variety of AMD-specific targets
449 // from the information returned from CPUID.
457 case 8: return "k6-2";
459 case 13: return "k6-3";
460 case 10: return "geode";
461 default: return "pentium";
465 case 4: return "athlon-tbird";
468 case 8: return "athlon-mp";
469 case 10: return "athlon-xp";
470 default: return "athlon";
476 case 1: return "opteron";
477 case 5: return "athlon-fx"; // also opteron
478 default: return "athlon64";
485 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
488 return "bdver4"; // 50h-6Fh: Excavator
490 return "bdver3"; // 30h-3Fh: Steamroller
491 if (Model >= 0x10 || HasTBM)
492 return "bdver2"; // 10h-1Fh: Piledriver
493 return "bdver1"; // 00h-0Fh: Bulldozer
495 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
504 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
505 StringRef sys::getHostCPUName() {
506 host_basic_info_data_t hostInfo;
507 mach_msg_type_number_t infoCount;
509 infoCount = HOST_BASIC_INFO_COUNT;
510 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
513 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
515 switch(hostInfo.cpu_subtype) {
516 case CPU_SUBTYPE_POWERPC_601: return "601";
517 case CPU_SUBTYPE_POWERPC_602: return "602";
518 case CPU_SUBTYPE_POWERPC_603: return "603";
519 case CPU_SUBTYPE_POWERPC_603e: return "603e";
520 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
521 case CPU_SUBTYPE_POWERPC_604: return "604";
522 case CPU_SUBTYPE_POWERPC_604e: return "604e";
523 case CPU_SUBTYPE_POWERPC_620: return "620";
524 case CPU_SUBTYPE_POWERPC_750: return "750";
525 case CPU_SUBTYPE_POWERPC_7400: return "7400";
526 case CPU_SUBTYPE_POWERPC_7450: return "7450";
527 case CPU_SUBTYPE_POWERPC_970: return "970";
533 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
534 StringRef sys::getHostCPUName() {
535 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
536 // and so we must use an operating-system interface to determine the current
537 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
538 const char *generic = "generic";
540 // The cpu line is second (after the 'processor: 0' line), so if this
541 // buffer is too small then something has changed (or is wrong).
543 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
544 if (CPUInfoSize == -1)
547 const char *CPUInfoStart = buffer;
548 const char *CPUInfoEnd = buffer + CPUInfoSize;
550 const char *CIP = CPUInfoStart;
552 const char *CPUStart = 0;
555 // We need to find the first line which starts with cpu, spaces, and a colon.
556 // After the colon, there may be some additional spaces and then the cpu type.
557 while (CIP < CPUInfoEnd && CPUStart == 0) {
558 if (CIP < CPUInfoEnd && *CIP == '\n')
561 if (CIP < CPUInfoEnd && *CIP == 'c') {
563 if (CIP < CPUInfoEnd && *CIP == 'p') {
565 if (CIP < CPUInfoEnd && *CIP == 'u') {
567 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
570 if (CIP < CPUInfoEnd && *CIP == ':') {
572 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
575 if (CIP < CPUInfoEnd) {
577 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
578 *CIP != ',' && *CIP != '\n'))
580 CPULen = CIP - CPUStart;
588 while (CIP < CPUInfoEnd && *CIP != '\n')
595 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
596 .Case("604e", "604e")
598 .Case("7400", "7400")
599 .Case("7410", "7400")
600 .Case("7447", "7400")
601 .Case("7455", "7450")
603 .Case("POWER4", "970")
604 .Case("PPC970FX", "970")
605 .Case("PPC970MP", "970")
607 .Case("POWER5", "g5")
609 .Case("POWER6", "pwr6")
610 .Case("POWER7", "pwr7")
611 .Case("POWER8", "pwr8")
612 .Case("POWER8E", "pwr8")
615 #elif defined(__linux__) && defined(__arm__)
616 StringRef sys::getHostCPUName() {
617 // The cpuid register on arm is not accessible from user space. On Linux,
618 // it is exposed through the /proc/cpuinfo file.
620 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
623 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
624 if (CPUInfoSize == -1)
627 StringRef Str(buffer, CPUInfoSize);
629 SmallVector<StringRef, 32> Lines;
630 Str.split(Lines, "\n");
632 // Look for the CPU implementer line.
633 StringRef Implementer;
634 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
635 if (Lines[I].startswith("CPU implementer"))
636 Implementer = Lines[I].substr(15).ltrim("\t :");
638 if (Implementer == "0x41") // ARM Ltd.
639 // Look for the CPU part line.
640 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
641 if (Lines[I].startswith("CPU part"))
642 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
643 // values correspond to the "Part number" in the CP15/c0 register. The
644 // contents are specified in the various processor manuals.
645 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
646 .Case("0x926", "arm926ej-s")
647 .Case("0xb02", "mpcore")
648 .Case("0xb36", "arm1136j-s")
649 .Case("0xb56", "arm1156t2-s")
650 .Case("0xb76", "arm1176jz-s")
651 .Case("0xc08", "cortex-a8")
652 .Case("0xc09", "cortex-a9")
653 .Case("0xc0f", "cortex-a15")
654 .Case("0xc20", "cortex-m0")
655 .Case("0xc23", "cortex-m3")
656 .Case("0xc24", "cortex-m4")
659 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
660 // Look for the CPU part line.
661 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
662 if (Lines[I].startswith("CPU part"))
663 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
664 // values correspond to the "Part number" in the CP15/c0 register. The
665 // contents are specified in the various processor manuals.
666 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
667 .Case("0x06f", "krait") // APQ8064
672 #elif defined(__linux__) && defined(__s390x__)
673 StringRef sys::getHostCPUName() {
674 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
676 // The "processor 0:" line comes after a fair amount of other information,
677 // including a cache breakdown, but this should be plenty.
679 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
680 if (CPUInfoSize == -1)
683 StringRef Str(buffer, CPUInfoSize);
684 SmallVector<StringRef, 32> Lines;
685 Str.split(Lines, "\n");
687 // Look for the CPU features.
688 SmallVector<StringRef, 32> CPUFeatures;
689 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
690 if (Lines[I].startswith("features")) {
691 size_t Pos = Lines[I].find(":");
692 if (Pos != StringRef::npos) {
693 Lines[I].drop_front(Pos + 1).split(CPUFeatures, " ");
698 // We need to check for the presence of vector support independently of
699 // the machine type, since we may only use the vector register set when
700 // supported by the kernel (and hypervisor).
701 bool HaveVectorSupport = false;
702 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
703 if (CPUFeatures[I] == "vx")
704 HaveVectorSupport = true;
707 // Now check the processor machine type.
708 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
709 if (Lines[I].startswith("processor ")) {
710 size_t Pos = Lines[I].find("machine = ");
711 if (Pos != StringRef::npos) {
712 Pos += sizeof("machine = ") - 1;
714 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
715 if (Id >= 2964 && HaveVectorSupport)
730 StringRef sys::getHostCPUName() {
735 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
736 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
737 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
738 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
745 if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
749 GetX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
751 Features["cmov"] = (EDX >> 15) & 1;
752 Features["mmx"] = (EDX >> 23) & 1;
753 Features["sse"] = (EDX >> 25) & 1;
754 Features["sse2"] = (EDX >> 26) & 1;
755 Features["sse3"] = (ECX >> 0) & 1;
756 Features["ssse3"] = (ECX >> 9) & 1;
757 Features["sse4.1"] = (ECX >> 19) & 1;
758 Features["sse4.2"] = (ECX >> 20) & 1;
760 Features["pclmul"] = (ECX >> 1) & 1;
761 Features["cx16"] = (ECX >> 13) & 1;
762 Features["movbe"] = (ECX >> 22) & 1;
763 Features["popcnt"] = (ECX >> 23) & 1;
764 Features["aes"] = (ECX >> 25) & 1;
765 Features["rdrnd"] = (ECX >> 30) & 1;
767 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
768 // indicates that the AVX registers will be saved and restored on context
769 // switch, then we have full AVX support.
770 bool HasAVX = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
771 !GetX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
772 Features["avx"] = HasAVX;
773 Features["fma"] = HasAVX && (ECX >> 12) & 1;
774 Features["f16c"] = HasAVX && (ECX >> 29) & 1;
776 // AVX512 requires additional context to be saved by the OS.
777 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
779 unsigned MaxExtLevel;
780 GetX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
782 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
783 !GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
784 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
785 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
786 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
787 Features["xop"] = HasAVX && HasExtLeaf1 && ((ECX >> 11) & 1);
788 Features["fma4"] = HasAVX && HasExtLeaf1 && ((ECX >> 16) & 1);
789 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
791 bool HasLeaf7 = MaxLevel >= 7 &&
792 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
794 // AVX2 is only supported if we have the OS save support from AVX.
795 Features["avx2"] = HasAVX && HasLeaf7 && (EBX >> 5) & 1;
797 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
798 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
799 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
800 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
801 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
802 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
803 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
804 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
806 // AVX512 is only supported if the OS supports the context save for it.
807 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
808 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
809 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
810 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
811 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
812 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
813 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
817 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
818 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
819 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
822 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
823 if (CPUInfoSize == -1)
826 StringRef Str(buffer, CPUInfoSize);
828 SmallVector<StringRef, 32> Lines;
829 Str.split(Lines, "\n");
831 SmallVector<StringRef, 32> CPUFeatures;
833 // Look for the CPU features.
834 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
835 if (Lines[I].startswith("Features")) {
836 Lines[I].split(CPUFeatures, " ");
840 #if defined(__aarch64__)
841 // Keep track of which crypto features we have seen
851 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
852 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
853 #if defined(__aarch64__)
854 .Case("asimd", "neon")
855 .Case("fp", "fp-armv8")
856 .Case("crc32", "crc")
858 .Case("half", "fp16")
859 .Case("neon", "neon")
860 .Case("vfpv3", "vfp3")
861 .Case("vfpv3d16", "d16")
862 .Case("vfpv4", "vfp4")
863 .Case("idiva", "hwdiv-arm")
864 .Case("idivt", "hwdiv")
868 #if defined(__aarch64__)
869 // We need to check crypto separately since we need all of the crypto
870 // extensions to enable the subtarget feature
871 if (CPUFeatures[I] == "aes")
873 else if (CPUFeatures[I] == "pmull")
875 else if (CPUFeatures[I] == "sha1")
877 else if (CPUFeatures[I] == "sha2")
881 if (LLVMFeatureStr != "")
882 Features[LLVMFeatureStr] = true;
885 #if defined(__aarch64__)
886 // If we have all crypto bits we can add the feature
887 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
888 Features["crypto"] = true;
894 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
899 std::string sys::getProcessTriple() {
900 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
902 if (sizeof(void *) == 8 && PT.isArch32Bit())
903 PT = PT.get64BitArchVariant();
904 if (sizeof(void *) == 4 && PT.isArch64Bit())
905 PT = PT.get32BitArchVariant();