1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/FileSystem.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 #define DEBUG_TYPE "host-detection"
44 //===----------------------------------------------------------------------===//
46 // Implementations of the CPU detection routines
48 //===----------------------------------------------------------------------===//
52 #if defined(__linux__)
53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
54 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
55 // memory buffer because the 'file' has 0 size (it can be read from only
59 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD);
61 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n");
64 int Ret = read(FD, Buf, Size);
65 int CloseStatus = close(FD);
72 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
73 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
75 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
76 /// specified arguments. If we can't run cpuid on the host, return true.
77 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
78 unsigned *rECX, unsigned *rEDX) {
79 #if defined(__GNUC__) || defined(__clang__)
80 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
81 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
82 asm ("movq\t%%rbx, %%rsi\n\t"
84 "xchgq\t%%rbx, %%rsi\n\t"
91 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
92 asm ("movl\t%%ebx, %%esi\n\t"
94 "xchgl\t%%ebx, %%esi\n\t"
101 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
102 // postprocessed code that looks like "return true; return false;")
106 #elif defined(_MSC_VER)
107 // The MSVC intrinsic is portable across x86 and x64.
109 __cpuid(registers, value);
110 *rEAX = registers[0];
111 *rEBX = registers[1];
112 *rECX = registers[2];
113 *rEDX = registers[3];
120 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
121 /// 4 values in the specified arguments. If we can't run cpuid on the host,
123 static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
124 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
126 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
127 #if defined(__GNUC__)
128 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
129 asm ("movq\t%%rbx, %%rsi\n\t"
131 "xchgq\t%%rbx, %%rsi\n\t"
139 #elif defined(_MSC_VER)
141 __cpuidex(registers, value, subleaf);
142 *rEAX = registers[0];
143 *rEBX = registers[1];
144 *rECX = registers[2];
145 *rEDX = registers[3];
150 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
151 #if defined(__GNUC__)
152 asm ("movl\t%%ebx, %%esi\n\t"
154 "xchgl\t%%ebx, %%esi\n\t"
162 #elif defined(_MSC_VER)
168 mov dword ptr [esi],eax
170 mov dword ptr [esi],ebx
172 mov dword ptr [esi],ecx
174 mov dword ptr [esi],edx
185 static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) {
186 #if defined(__GNUC__)
187 // Check xgetbv; this uses a .byte sequence instead of the instruction
188 // directly because older assemblers do not include support for xgetbv and
189 // there is no easy way to conditionally compile based on the assembler used.
190 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (*rEAX), "=d" (*rEDX) : "c" (0));
192 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
193 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
195 *rEDX = Result >> 32;
202 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
204 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
205 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
206 if (Family == 6 || Family == 0xf) {
208 // Examine extended family ID if family ID is F.
209 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
210 // Examine extended model ID if family ID is 6 or F.
211 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
215 StringRef sys::getHostCPUName() {
216 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
217 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
221 DetectX86FamilyModel(EAX, Family, Model);
229 GetX86CpuIDAndInfo(0, &MaxLeaf, text.u+0, text.u+2, text.u+1);
231 bool HasMMX = (EDX >> 23) & 1;
232 bool HasSSE = (EDX >> 25) & 1;
233 bool HasSSE2 = (EDX >> 26) & 1;
234 bool HasSSE3 = (ECX >> 0) & 1;
235 bool HasSSSE3 = (ECX >> 9) & 1;
236 bool HasSSE41 = (ECX >> 19) & 1;
237 bool HasSSE42 = (ECX >> 20) & 1;
238 bool HasMOVBE = (ECX >> 22) & 1;
239 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
240 // indicates that the AVX registers will be saved and restored on context
241 // switch, then we have full AVX support.
242 const unsigned AVXBits = (1 << 27) | (1 << 28);
243 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) &&
244 ((EAX & 0x6) == 0x6);
245 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
246 bool HasLeaf7 = MaxLeaf >= 0x7 &&
247 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
248 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
249 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
250 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
252 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
253 bool Em64T = (EDX >> 29) & 0x1;
254 bool HasTBM = (ECX >> 21) & 0x1;
256 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
262 case 0: // Intel486 DX processors
263 case 1: // Intel486 DX processors
264 case 2: // Intel486 SX processors
265 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
266 // IntelDX2 processors
267 case 4: // Intel486 SL processor
268 case 5: // IntelSX2 processors
269 case 7: // Write-Back Enhanced IntelDX2 processors
270 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
271 default: return "i486";
275 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
276 // Pentium processors (60, 66)
277 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
278 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
280 case 3: // Pentium OverDrive processors for Intel486 processor-based
284 case 4: // Pentium OverDrive processor with MMX technology for Pentium
285 // processor (75, 90, 100, 120, 133), Pentium processor with
286 // MMX technology (166, 200)
287 return "pentium-mmx";
289 default: return "pentium";
293 case 1: // Pentium Pro processor
296 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
298 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
299 // model 05, and Intel Celeron processor, model 05
300 case 6: // Celeron processor, model 06
303 case 7: // Pentium III processor, model 07, and Pentium III Xeon
304 // processor, model 07
305 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
306 // model 08, and Celeron processor, model 08
307 case 10: // Pentium III Xeon processor, model 0Ah
308 case 11: // Pentium III processor, model 0Bh
311 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
312 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
313 // 0Dh. All processors are manufactured using the 90 nm process.
314 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
315 // Integrated Processor with Intel QuickAssist Technology
318 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
319 // 0Eh. All processors are manufactured using the 65 nm process.
322 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
323 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
324 // mobile processor, Intel Core 2 Extreme processor, Intel
325 // Pentium Dual-Core processor, Intel Xeon processor, model
326 // 0Fh. All processors are manufactured using the 65 nm process.
327 case 22: // Intel Celeron processor model 16h. All processors are
328 // manufactured using the 65 nm process
331 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
332 // 17h. All processors are manufactured using the 45 nm process.
334 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
335 case 29: // Intel Xeon processor MP. All processors are manufactured using
336 // the 45 nm process.
337 // Not all Penryn processors support SSE 4.1 (such as the Pentium brand)
338 return HasSSE41 ? "penryn" : "core2";
340 case 26: // Intel Core i7 processor and Intel Xeon processor. All
341 // processors are manufactured using the 45 nm process.
342 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
343 // As found in a Summer 2010 model iMac.
344 case 46: // Nehalem EX
346 case 37: // Intel Core i7, laptop version.
347 case 44: // Intel Core i7 processor and Intel Xeon processor. All
348 // processors are manufactured using the 32 nm process.
349 case 47: // Westmere EX
353 case 42: // Intel Core i7 processor. All processors are manufactured
354 // using the 32 nm process.
356 // Not all Sandy Bridge processors support AVX (such as the Pentium
357 // versions instead of the i7 versions).
358 return HasAVX ? "sandybridge" : "nehalem";
362 case 62: // Ivy Bridge EP
363 // Not all Ivy Bridge processors support AVX (such as the Pentium
364 // versions instead of the i7 versions).
365 return HasAVX ? "ivybridge" : "nehalem";
372 // Not all Haswell processors support AVX2 (such as the Pentium
373 // versions instead of the i7 versions).
374 return HasAVX2 ? "haswell" : "nehalem";
378 // Not all Broadwell processors support AVX2 (such as the Pentium
379 // versions instead of the i7 versions).
380 return HasAVX2 ? "broadwell" : "nehalem";
382 case 28: // Most 45 nm Intel Atom processors
383 case 38: // 45 nm Atom Lincroft
384 case 39: // 32 nm Atom Medfield
385 case 53: // 32 nm Atom Midview
386 case 54: // 32 nm Atom Midview
389 // Atom Silvermont codes from the Intel software optimization guide.
395 default: // Unknown family 6 CPU, try to guess.
403 return "sandybridge";
405 return HasMOVBE ? "silvermont" : "nehalem";
409 return HasMOVBE ? "bonnell" : "core2";
422 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
423 // model 00h and manufactured using the 0.18 micron process.
424 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
425 // processor MP, and Intel Celeron processor. All processors are
426 // model 01h and manufactured using the 0.18 micron process.
427 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
428 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
429 // processor, and Mobile Intel Celeron processor. All processors
430 // are model 02h and manufactured using the 0.13 micron process.
431 return (Em64T) ? "x86-64" : "pentium4";
433 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
434 // processor. All processors are model 03h and manufactured using
435 // the 90 nm process.
436 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
437 // Pentium D processor, Intel Xeon processor, Intel Xeon
438 // processor MP, Intel Celeron D processor. All processors are
439 // model 04h and manufactured using the 90 nm process.
440 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
441 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
442 // MP, Intel Celeron D processor. All processors are model 06h
443 // and manufactured using the 65 nm process.
444 return (Em64T) ? "nocona" : "prescott";
447 return (Em64T) ? "x86-64" : "pentium4";
454 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
455 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
456 // appears to be no way to generate the wide variety of AMD-specific targets
457 // from the information returned from CPUID.
465 case 8: return "k6-2";
467 case 13: return "k6-3";
468 case 10: return "geode";
469 default: return "pentium";
473 case 4: return "athlon-tbird";
476 case 8: return "athlon-mp";
477 case 10: return "athlon-xp";
478 default: return "athlon";
484 case 1: return "opteron";
485 case 5: return "athlon-fx"; // also opteron
486 default: return "athlon64";
493 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
496 return "bdver4"; // 50h-6Fh: Excavator
498 return "bdver3"; // 30h-3Fh: Steamroller
499 if (Model >= 0x10 || HasTBM)
500 return "bdver2"; // 10h-1Fh: Piledriver
501 return "bdver1"; // 00h-0Fh: Bulldozer
503 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
512 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
513 StringRef sys::getHostCPUName() {
514 host_basic_info_data_t hostInfo;
515 mach_msg_type_number_t infoCount;
517 infoCount = HOST_BASIC_INFO_COUNT;
518 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
521 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
523 switch(hostInfo.cpu_subtype) {
524 case CPU_SUBTYPE_POWERPC_601: return "601";
525 case CPU_SUBTYPE_POWERPC_602: return "602";
526 case CPU_SUBTYPE_POWERPC_603: return "603";
527 case CPU_SUBTYPE_POWERPC_603e: return "603e";
528 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
529 case CPU_SUBTYPE_POWERPC_604: return "604";
530 case CPU_SUBTYPE_POWERPC_604e: return "604e";
531 case CPU_SUBTYPE_POWERPC_620: return "620";
532 case CPU_SUBTYPE_POWERPC_750: return "750";
533 case CPU_SUBTYPE_POWERPC_7400: return "7400";
534 case CPU_SUBTYPE_POWERPC_7450: return "7450";
535 case CPU_SUBTYPE_POWERPC_970: return "970";
541 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
542 StringRef sys::getHostCPUName() {
543 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
544 // and so we must use an operating-system interface to determine the current
545 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
546 const char *generic = "generic";
548 // The cpu line is second (after the 'processor: 0' line), so if this
549 // buffer is too small then something has changed (or is wrong).
551 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
552 if (CPUInfoSize == -1)
555 const char *CPUInfoStart = buffer;
556 const char *CPUInfoEnd = buffer + CPUInfoSize;
558 const char *CIP = CPUInfoStart;
560 const char *CPUStart = 0;
563 // We need to find the first line which starts with cpu, spaces, and a colon.
564 // After the colon, there may be some additional spaces and then the cpu type.
565 while (CIP < CPUInfoEnd && CPUStart == 0) {
566 if (CIP < CPUInfoEnd && *CIP == '\n')
569 if (CIP < CPUInfoEnd && *CIP == 'c') {
571 if (CIP < CPUInfoEnd && *CIP == 'p') {
573 if (CIP < CPUInfoEnd && *CIP == 'u') {
575 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
578 if (CIP < CPUInfoEnd && *CIP == ':') {
580 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
583 if (CIP < CPUInfoEnd) {
585 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
586 *CIP != ',' && *CIP != '\n'))
588 CPULen = CIP - CPUStart;
596 while (CIP < CPUInfoEnd && *CIP != '\n')
603 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
604 .Case("604e", "604e")
606 .Case("7400", "7400")
607 .Case("7410", "7400")
608 .Case("7447", "7400")
609 .Case("7455", "7450")
611 .Case("POWER4", "970")
612 .Case("PPC970FX", "970")
613 .Case("PPC970MP", "970")
615 .Case("POWER5", "g5")
617 .Case("POWER6", "pwr6")
618 .Case("POWER7", "pwr7")
619 .Case("POWER8", "pwr8")
620 .Case("POWER8E", "pwr8")
623 #elif defined(__linux__) && defined(__arm__)
624 StringRef sys::getHostCPUName() {
625 // The cpuid register on arm is not accessible from user space. On Linux,
626 // it is exposed through the /proc/cpuinfo file.
628 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
631 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
632 if (CPUInfoSize == -1)
635 StringRef Str(buffer, CPUInfoSize);
637 SmallVector<StringRef, 32> Lines;
638 Str.split(Lines, "\n");
640 // Look for the CPU implementer line.
641 StringRef Implementer;
642 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
643 if (Lines[I].startswith("CPU implementer"))
644 Implementer = Lines[I].substr(15).ltrim("\t :");
646 if (Implementer == "0x41") // ARM Ltd.
647 // Look for the CPU part line.
648 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
649 if (Lines[I].startswith("CPU part"))
650 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
651 // values correspond to the "Part number" in the CP15/c0 register. The
652 // contents are specified in the various processor manuals.
653 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
654 .Case("0x926", "arm926ej-s")
655 .Case("0xb02", "mpcore")
656 .Case("0xb36", "arm1136j-s")
657 .Case("0xb56", "arm1156t2-s")
658 .Case("0xb76", "arm1176jz-s")
659 .Case("0xc08", "cortex-a8")
660 .Case("0xc09", "cortex-a9")
661 .Case("0xc0f", "cortex-a15")
662 .Case("0xc20", "cortex-m0")
663 .Case("0xc23", "cortex-m3")
664 .Case("0xc24", "cortex-m4")
667 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
668 // Look for the CPU part line.
669 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
670 if (Lines[I].startswith("CPU part"))
671 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
672 // values correspond to the "Part number" in the CP15/c0 register. The
673 // contents are specified in the various processor manuals.
674 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
675 .Case("0x06f", "krait") // APQ8064
680 #elif defined(__linux__) && defined(__s390x__)
681 StringRef sys::getHostCPUName() {
682 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
684 // The "processor 0:" line comes after a fair amount of other information,
685 // including a cache breakdown, but this should be plenty.
687 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
688 if (CPUInfoSize == -1)
691 StringRef Str(buffer, CPUInfoSize);
692 SmallVector<StringRef, 32> Lines;
693 Str.split(Lines, "\n");
694 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
695 if (Lines[I].startswith("processor ")) {
696 size_t Pos = Lines[I].find("machine = ");
697 if (Pos != StringRef::npos) {
698 Pos += sizeof("machine = ") - 1;
700 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
714 StringRef sys::getHostCPUName() {
719 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
720 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
721 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
722 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
729 if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
733 GetX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
735 Features["cmov"] = (EDX >> 15) & 1;
736 Features["mmx"] = (EDX >> 23) & 1;
737 Features["sse"] = (EDX >> 25) & 1;
738 Features["sse2"] = (EDX >> 26) & 1;
739 Features["sse3"] = (ECX >> 0) & 1;
740 Features["ssse3"] = (ECX >> 9) & 1;
741 Features["sse4.1"] = (ECX >> 19) & 1;
742 Features["sse4.2"] = (ECX >> 20) & 1;
744 Features["pclmul"] = (ECX >> 1) & 1;
745 Features["cx16"] = (ECX >> 13) & 1;
746 Features["movbe"] = (ECX >> 22) & 1;
747 Features["popcnt"] = (ECX >> 23) & 1;
748 Features["aes"] = (ECX >> 25) & 1;
749 Features["rdrnd"] = (ECX >> 30) & 1;
751 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
752 // indicates that the AVX registers will be saved and restored on context
753 // switch, then we have full AVX support.
754 bool HasAVX = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
755 !GetX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
756 Features["avx"] = HasAVX;
757 Features["fma"] = HasAVX && (ECX >> 12) & 1;
758 Features["f16c"] = HasAVX && (ECX >> 29) & 1;
760 // AVX512 requires additional context to be saved by the OS.
761 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
763 unsigned MaxExtLevel;
764 GetX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
766 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
767 !GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
768 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
769 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
770 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
771 Features["xop"] = HasAVX && HasExtLeaf1 && ((ECX >> 11) & 1);
772 Features["fma4"] = HasAVX && HasExtLeaf1 && ((ECX >> 16) & 1);
773 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
775 bool HasLeaf7 = MaxLevel >= 7 &&
776 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
778 // AVX2 is only supported if we have the OS save support from AVX.
779 Features["avx2"] = HasAVX && HasLeaf7 && (EBX >> 5) & 1;
781 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
782 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
783 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
784 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
785 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
786 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
787 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
788 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
790 // AVX512 is only supported if the OS supports the context save for it.
791 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
792 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
793 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
794 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
795 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
796 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
797 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
801 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
802 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
803 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
806 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
807 if (CPUInfoSize == -1)
810 StringRef Str(buffer, CPUInfoSize);
812 SmallVector<StringRef, 32> Lines;
813 Str.split(Lines, "\n");
815 SmallVector<StringRef, 32> CPUFeatures;
817 // Look for the CPU features.
818 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
819 if (Lines[I].startswith("Features")) {
820 Lines[I].split(CPUFeatures, " ");
824 #if defined(__aarch64__)
825 // Keep track of which crypto features we have seen
835 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
836 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
837 #if defined(__aarch64__)
838 .Case("asimd", "neon")
839 .Case("fp", "fp-armv8")
840 .Case("crc32", "crc")
842 .Case("half", "fp16")
843 .Case("neon", "neon")
844 .Case("vfpv3", "vfp3")
845 .Case("vfpv3d16", "d16")
846 .Case("vfpv4", "vfp4")
847 .Case("idiva", "hwdiv-arm")
848 .Case("idivt", "hwdiv")
852 #if defined(__aarch64__)
853 // We need to check crypto separately since we need all of the crypto
854 // extensions to enable the subtarget feature
855 if (CPUFeatures[I] == "aes")
857 else if (CPUFeatures[I] == "pmull")
859 else if (CPUFeatures[I] == "sha1")
861 else if (CPUFeatures[I] == "sha2")
865 if (LLVMFeatureStr != "")
866 Features[LLVMFeatureStr] = true;
869 #if defined(__aarch64__)
870 // If we have all crypto bits we can add the feature
871 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
872 Features["crypto"] = true;
878 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
883 std::string sys::getProcessTriple() {
884 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
886 if (sizeof(void *) == 8 && PT.isArch32Bit())
887 PT = PT.get64BitArchVariant();
888 if (sizeof(void *) == 4 && PT.isArch64Bit())
889 PT = PT.get32BitArchVariant();