1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCSubtargetInfo.h"
11 #include "llvm/ADT/StringRef.h"
12 #include "llvm/ADT/Triple.h"
13 #include "llvm/MC/MCInstrItineraries.h"
14 #include "llvm/MC/SubtargetFeature.h"
15 #include "llvm/Support/raw_ostream.h"
20 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
21 /// with feature string). Recompute feature bits and scheduling model.
23 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
24 SubtargetFeatures Features(FS);
25 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
27 CPUSchedModel = &getSchedModelForCPU(CPU);
29 CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
32 void MCSubtargetInfo::InitMCSubtargetInfo(
33 const Triple &TT, StringRef C, StringRef FS,
34 ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
35 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
36 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
37 const InstrStage *IS, const unsigned *OC, const unsigned *FP) {
42 ProcSchedModels = ProcSched;
43 WriteProcResTable = WPR;
44 WriteLatencyTable = WL;
45 ReadAdvanceTable = RA;
51 InitMCProcessorInfo(CPU, FS);
54 /// ToggleFeature - Toggle a feature and returns the re-computed feature
55 /// bits. This version does not change the implied bits.
56 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
61 FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
66 /// ToggleFeature - Toggle a feature and returns the re-computed feature
67 /// bits. This version will also change all implied bits.
68 FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
69 SubtargetFeatures Features;
70 FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
74 FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
75 SubtargetFeatures Features;
76 FeatureBits = Features.ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
80 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
81 assert(ProcSchedModels && "Processor machine model not available!");
83 unsigned NumProcs = ProcDesc.size();
85 for (size_t i = 1; i < NumProcs; i++) {
86 assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
87 "Processor machine model table is not sorted");
92 const SubtargetInfoKV *Found =
93 std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU);
94 if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
95 if (CPU != "help") // Don't error if the user asked for help.
97 << "' is not a recognized processor for this target"
98 << " (ignoring processor)\n";
99 return MCSchedModel::GetDefaultSchedModel();
101 assert(Found->Value && "Missing processor SchedModel value");
102 return *(const MCSchedModel *)Found->Value;
106 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
107 const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
108 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
111 /// Initialize an InstrItineraryData instance.
112 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
113 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,