1 //===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "Disassembler.h"
11 #include "llvm-c/Disassembler.h"
12 #include "llvm/MC/MCAsmInfo.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCDisassembler.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCInstPrinter.h"
17 #include "llvm/MC/MCInstrInfo.h"
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/MC/MCRelocationInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/MCSymbolizer.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/MemoryObject.h"
25 #include "llvm/Support/TargetRegistry.h"
32 // LLVMCreateDisasm() creates a disassembler for the TripleName. Symbolic
33 // disassembly is supported by passing a block of information in the DisInfo
34 // parameter and specifying the TagType and callback functions as described in
35 // the header llvm-c/Disassembler.h . The pointer to the block and the
36 // functions can all be passed as NULL. If successful, this returns a
37 // disassembler context. If not, it returns NULL.
39 LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU,
40 void *DisInfo, int TagType,
41 LLVMOpInfoCallback GetOpInfo,
42 LLVMSymbolLookupCallback SymbolLookUp){
45 const Target *TheTarget = TargetRegistry::lookupTarget(Triple, Error);
49 const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple);
53 // Get the assembler info needed to setup the MCContext.
54 const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple);
58 const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
62 // Package up features to be passed to target/subtarget
63 std::string FeaturesStr;
65 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU,
70 // Set up the MCContext for creating symbols and MCExpr's.
71 MCContext *Ctx = new MCContext(MAI, MRI, 0);
75 // Set up disassembler.
76 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
80 std::unique_ptr<MCRelocationInfo> RelInfo(
81 TheTarget->createMCRelocationInfo(Triple, *Ctx));
85 std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
86 Triple, GetOpInfo, SymbolLookUp, DisInfo, Ctx, RelInfo.release()));
87 DisAsm->setSymbolizer(std::move(Symbolizer));
88 DisAsm->setupForSymbolicDisassembly(GetOpInfo, SymbolLookUp, DisInfo,
90 // Set up the instruction printer.
91 int AsmPrinterVariant = MAI->getAssemblerDialect();
92 MCInstPrinter *IP = TheTarget->createMCInstPrinter(AsmPrinterVariant,
93 *MAI, *MII, *MRI, *STI);
97 LLVMDisasmContext *DC = new LLVMDisasmContext(Triple, DisInfo, TagType,
98 GetOpInfo, SymbolLookUp,
100 STI, MII, Ctx, DisAsm, IP);
108 LLVMDisasmContextRef LLVMCreateDisasm(const char *Triple, void *DisInfo,
109 int TagType, LLVMOpInfoCallback GetOpInfo,
110 LLVMSymbolLookupCallback SymbolLookUp) {
111 return LLVMCreateDisasmCPU(Triple, "", DisInfo, TagType, GetOpInfo,
116 // LLVMDisasmDispose() disposes of the disassembler specified by the context.
118 void LLVMDisasmDispose(LLVMDisasmContextRef DCR){
119 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
125 // The memory object created by LLVMDisasmInstruction().
127 class DisasmMemoryObject : public MemoryObject {
132 DisasmMemoryObject(uint8_t *bytes, uint64_t size, uint64_t basePC) :
133 Bytes(bytes), Size(size), BasePC(basePC) {}
135 uint64_t getBase() const { return BasePC; }
136 uint64_t getExtent() const { return Size; }
138 int readByte(uint64_t Addr, uint8_t *Byte) const {
139 if (Addr - BasePC >= Size)
141 *Byte = Bytes[Addr - BasePC];
145 } // end anonymous namespace
147 /// \brief Emits the comments that are stored in \p DC comment stream.
148 /// Each comment in the comment stream must end with a newline.
149 static void emitComments(LLVMDisasmContext *DC,
150 formatted_raw_ostream &FormattedOS) {
151 // Flush the stream before taking its content.
152 DC->CommentStream.flush();
153 StringRef Comments = DC->CommentsToEmit.str();
154 // Get the default information for printing a comment.
155 const MCAsmInfo *MAI = DC->getAsmInfo();
156 const char *CommentBegin = MAI->getCommentString();
157 unsigned CommentColumn = MAI->getCommentColumn();
159 while (!Comments.empty()) {
162 // Emit a line of comments.
163 FormattedOS.PadToColumn(CommentColumn);
164 size_t Position = Comments.find('\n');
165 FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position);
166 // Move after the newline character.
167 Comments = Comments.substr(Position+1);
172 // Tell the comment stream that the vector changed underneath it.
173 DC->CommentsToEmit.clear();
174 DC->CommentStream.resync();
177 /// \brief Gets latency information for \p Inst form the itinerary
178 /// scheduling model, based on \p DC information.
179 /// \return The maximum expected latency over all the operands or -1
180 /// if no information are available.
181 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
182 const int NoInformationAvailable = -1;
184 // Check if we have a CPU to get the itinerary information.
185 if (DC->getCPU().empty())
186 return NoInformationAvailable;
188 // Get itinerary information.
189 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
190 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
191 // Get the scheduling class of the requested instruction.
192 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
193 unsigned SCClass = Desc.getSchedClass();
196 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
198 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
203 /// \brief Gets latency information for \p Inst, based on \p DC information.
204 /// \return The maximum expected latency over all the definitions or -1
205 /// if no information are available.
206 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
207 // Try to compute scheduling information.
208 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
209 const MCSchedModel *SCModel = STI->getSchedModel();
210 const int NoInformationAvailable = -1;
212 // Check if we have a scheduling model for instructions.
213 if (!SCModel || !SCModel->hasInstrSchedModel())
214 // Try to fall back to the itinerary model if we do not have a
216 return getItineraryLatency(DC, Inst);
218 // Get the scheduling class of the requested instruction.
219 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
220 unsigned SCClass = Desc.getSchedClass();
221 const MCSchedClassDesc *SCDesc = SCModel->getSchedClassDesc(SCClass);
222 // Resolving the variant SchedClass requires an MI to pass to
223 // SubTargetInfo::resolveSchedClass.
224 if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
225 return NoInformationAvailable;
227 // Compute output latency.
229 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
230 DefIdx != DefEnd; ++DefIdx) {
231 // Lookup the definition's write latency in SubtargetInfo.
232 const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
234 Latency = std::max(Latency, WLEntry->Cycles);
241 /// \brief Emits latency information in DC->CommentStream for \p Inst, based
242 /// on the information available in \p DC.
243 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
244 int Latency = getLatency(DC, Inst);
246 // Report only interesting latency.
250 DC->CommentStream << "Latency: " << Latency << '\n';
254 // LLVMDisasmInstruction() disassembles a single instruction using the
255 // disassembler context specified in the parameter DC. The bytes of the
256 // instruction are specified in the parameter Bytes, and contains at least
257 // BytesSize number of bytes. The instruction is at the address specified by
258 // the PC parameter. If a valid instruction can be disassembled its string is
259 // returned indirectly in OutString which whos size is specified in the
260 // parameter OutStringSize. This function returns the number of bytes in the
261 // instruction or zero if there was no valid instruction. If this function
262 // returns zero the caller will have to pick how many bytes they want to step
263 // over by printing a .byte, .long etc. to continue.
265 size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
266 uint64_t BytesSize, uint64_t PC, char *OutString,
267 size_t OutStringSize){
268 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
269 // Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject.
270 DisasmMemoryObject MemoryObject(Bytes, BytesSize, PC);
274 const MCDisassembler *DisAsm = DC->getDisAsm();
275 MCInstPrinter *IP = DC->getIP();
276 MCDisassembler::DecodeStatus S;
277 SmallVector<char, 64> InsnStr;
278 raw_svector_ostream Annotations(InsnStr);
279 S = DisAsm->getInstruction(Inst, Size, MemoryObject, PC,
280 /*REMOVE*/ nulls(), Annotations);
282 case MCDisassembler::Fail:
283 case MCDisassembler::SoftFail:
284 // FIXME: Do something different for soft failure modes?
287 case MCDisassembler::Success: {
289 StringRef AnnotationsStr = Annotations.str();
291 SmallVector<char, 64> InsnStr;
292 raw_svector_ostream OS(InsnStr);
293 formatted_raw_ostream FormattedOS(OS);
294 IP->printInst(&Inst, FormattedOS, AnnotationsStr);
296 if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency)
297 emitLatency(DC, Inst);
299 emitComments(DC, FormattedOS);
302 assert(OutStringSize != 0 && "Output buffer cannot be zero size");
303 size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
304 std::memcpy(OutString, InsnStr.data(), OutputSize);
305 OutString[OutputSize] = '\0'; // Terminate string.
310 llvm_unreachable("Invalid DecodeStatus!");
314 // LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
315 // can set all the Options and 0 otherwise.
317 int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
318 if (Options & LLVMDisassembler_Option_UseMarkup){
319 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
320 MCInstPrinter *IP = DC->getIP();
322 DC->addOptions(LLVMDisassembler_Option_UseMarkup);
323 Options &= ~LLVMDisassembler_Option_UseMarkup;
325 if (Options & LLVMDisassembler_Option_PrintImmHex){
326 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
327 MCInstPrinter *IP = DC->getIP();
328 IP->setPrintImmHex(1);
329 DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
330 Options &= ~LLVMDisassembler_Option_PrintImmHex;
332 if (Options & LLVMDisassembler_Option_AsmPrinterVariant){
333 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
334 // Try to set up the new instruction printer.
335 const MCAsmInfo *MAI = DC->getAsmInfo();
336 const MCInstrInfo *MII = DC->getInstrInfo();
337 const MCRegisterInfo *MRI = DC->getRegisterInfo();
338 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
339 int AsmPrinterVariant = MAI->getAssemblerDialect();
340 AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
341 MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
342 AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
345 DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
346 Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
349 if (Options & LLVMDisassembler_Option_SetInstrComments) {
350 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
351 MCInstPrinter *IP = DC->getIP();
352 IP->setCommentStream(DC->CommentStream);
353 DC->addOptions(LLVMDisassembler_Option_SetInstrComments);
354 Options &= ~LLVMDisassembler_Option_SetInstrComments;
356 if (Options & LLVMDisassembler_Option_PrintLatency) {
357 LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
358 DC->addOptions(LLVMDisassembler_Option_PrintLatency);
359 Options &= ~LLVMDisassembler_Option_PrintLatency;
361 return (Options == 0);