lib/CodeGen/TwoAddressInstructionPass.cpp

   1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LiveInterval analysis pass which is used
  11 // by the Linear Scan Register allocator. This pass linearizes the
  12 // basic blocks of the function in DFS order and uses the
  13 // LiveVariables pass to conservatively compute live intervals for
  14 // each virtual and physical register.
  15 //
  16 //===----------------------------------------------------------------------===//
  17
  18 #define DEBUG_TYPE "twoaddrinstr"
  19 #include "llvm/Function.h"
  20 #include "llvm/CodeGen/LiveVariables.h"
  21 #include "llvm/CodeGen/MachineFrameInfo.h"
  22 #include "llvm/CodeGen/MachineFunctionPass.h"
  23 #include "llvm/CodeGen/MachineInstr.h"
  24 #include "llvm/CodeGen/Passes.h"
  25 #include "llvm/CodeGen/SSARegMap.h"
  26 #include "llvm/Target/MRegisterInfo.h"
  27 #include "llvm/Target/TargetInstrInfo.h"
  28 #include "llvm/Target/TargetMachine.h"
  29 #include "llvm/Target/TargetRegInfo.h"
  30 #include "Support/Debug.h"
  31 #include "Support/Statistic.h"
  32 #include "Support/STLExtras.h"
  33 #include <iostream>
  34
  35 using namespace llvm;
  36
  37 namespace {
  38     class TwoAddressInstructionPass : public MachineFunctionPass
  39     {
  40     private:
  41         MachineFunction* mf_;
  42         const TargetMachine* tm_;
  43         const MRegisterInfo* mri_;
  44         LiveVariables* lv_;
  45
  46     public:
  47         virtual void getAnalysisUsage(AnalysisUsage &AU) const;
  48
  49     private:
  50         /// runOnMachineFunction - pass entry point
  51         bool runOnMachineFunction(MachineFunction&);
  52     };
  53
  54     RegisterPass<TwoAddressInstructionPass> X(
  55         "twoaddressinstruction", "Two-Address instruction pass");
  56
  57     Statistic<> numTwoAddressInstrs("twoaddressinstruction",
  58                                     "Number of two-address instructions");
  59     Statistic<> numInstrsAdded("twoaddressinstruction",
  60                                "Number of instructions added");
  61 };
  62
  63 const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
  64
  65 void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const
  66 {
  67     AU.addPreserved<LiveVariables>();
  68     AU.addRequired<LiveVariables>();
  69     AU.addPreservedID(PHIEliminationID);
  70     AU.addRequiredID(PHIEliminationID);
  71     MachineFunctionPass::getAnalysisUsage(AU);
  72 }
  73
  74 /// runOnMachineFunction - Reduce two-address instructions to two
  75 /// operands
  76 ///
  77 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &fn) {
  78     DEBUG(std::cerr << "Machine Function\n");
  79     mf_ = &fn;
  80     tm_ = &fn.getTarget();
  81     mri_ = tm_->getRegisterInfo();
  82     lv_ = &getAnalysis<LiveVariables>();
  83
  84     const TargetInstrInfo& tii = tm_->getInstrInfo();
  85
  86     for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
  87          mbbi != mbbe; ++mbbi) {
  88         for (MachineBasicBlock::iterator mii = mbbi->begin();
  89              mii != mbbi->end(); ++mii) {
  90             MachineInstr* mi = *mii;
  91
  92             unsigned opcode = mi->getOpcode();
  93             // ignore if it is not a two-address instruction
  94             if (!tii.isTwoAddrInstr(opcode))
  95                 continue;
  96
  97             ++numTwoAddressInstrs;
  98
  99             DEBUG(std::cerr << "\tinstruction: "; mi->print(std::cerr, *tm_));
 100
 101             // we have nothing to do if the two operands are the same
 102             if (mi->getOperand(0).getAllocatedRegNum() ==
 103                 mi->getOperand(1).getAllocatedRegNum())
 104                 continue;
 105
 106             assert(mi->getOperand(1).isRegister() &&
 107                    mi->getOperand(1).getAllocatedRegNum() &&
 108                    mi->getOperand(1).isUse() &&
 109                    "two address instruction invalid");
 110
 111             // rewrite:
 112             //     a = b op c
 113             // to:
 114             //     a = b
 115             //     a = a op c
 116             unsigned regA = mi->getOperand(0).getAllocatedRegNum();
 117             unsigned regB = mi->getOperand(1).getAllocatedRegNum();
 118             bool regAisPhysical = regA < MRegisterInfo::FirstVirtualRegister;
 119             bool regBisPhysical = regB < MRegisterInfo::FirstVirtualRegister;
 120
 121             const TargetRegisterClass* rc = regAisPhysical ?
 122                 mri_->getRegClass(regA) :
 123                 mf_->getSSARegMap()->getRegClass(regA);
 124
 125             numInstrsAdded += mri_->copyRegToReg(*mbbi, mii, regA, regB, rc);
 126
 127             MachineInstr* prevMi = *(mii - 1);
 128             DEBUG(std::cerr << "\t\tadded instruction: ";
 129                   prevMi->print(std::cerr, *tm_));
 130
 131             // update live variables for regA
 132             if (regAisPhysical) {
 133                 lv_->HandlePhysRegDef(regA, prevMi);
 134             }
 135             else {
 136                 LiveVariables::VarInfo& varInfo = lv_->getVarInfo(regA);
 137                 varInfo.DefInst = prevMi;
 138             }
 139
 140             // update live variables for regB
 141             if (regBisPhysical) {
 142                 lv_->HandlePhysRegUse(regB, prevMi);
 143             }
 144             else {
 145                 if (lv_->removeVirtualRegisterKilled(regB, &*mbbi, mi))
 146                     lv_->addVirtualRegisterKilled(regB, &*mbbi, prevMi);
 147
 148                 if (lv_->removeVirtualRegisterDead(regB, &*mbbi, mi))
 149                     lv_->addVirtualRegisterDead(regB, &*mbbi, prevMi);
 150             }
 151
 152             // replace all occurences of regB with regA
 153             for (unsigned i = 1; i < mi->getNumOperands(); ++i) {
 154                 if (mi->getOperand(i).isRegister() &&
 155                     mi->getOperand(i).getReg() == regB)
 156                     mi->SetMachineOperandReg(i, regA);
 157             }
 158             DEBUG(std::cerr << "\t\tmodified original to: ";
 159                   mi->print(std::cerr, *tm_));
 160             assert(mi->getOperand(0).getAllocatedRegNum() ==
 161                    mi->getOperand(1).getAllocatedRegNum());
 162         }
 163     }
 164
 165     return numInstrsAdded != 0;
 166 }