1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/DenseMap.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/Analysis/AliasAnalysis.h"
38 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
39 #include "llvm/CodeGen/LiveVariables.h"
40 #include "llvm/CodeGen/MachineFunctionPass.h"
41 #include "llvm/CodeGen/MachineInstr.h"
42 #include "llvm/CodeGen/MachineInstrBuilder.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCInstrItineraries.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetMachine.h"
50 #include "llvm/Target/TargetRegisterInfo.h"
53 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
54 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
55 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
56 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
57 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
58 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
59 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
62 class TwoAddressInstructionPass : public MachineFunctionPass {
64 const TargetInstrInfo *TII;
65 const TargetRegisterInfo *TRI;
66 const InstrItineraryData *InstrItins;
67 MachineRegisterInfo *MRI;
71 CodeGenOpt::Level OptLevel;
73 // The current basic block being processed.
74 MachineBasicBlock *MBB;
76 // DistanceMap - Keep track the distance of a MI from the start of the
77 // current basic block.
78 DenseMap<MachineInstr*, unsigned> DistanceMap;
80 // Set of already processed instructions in the current block.
81 SmallPtrSet<MachineInstr*, 8> Processed;
83 // SrcRegMap - A map from virtual registers to physical registers which are
84 // likely targets to be coalesced to due to copies from physical registers to
85 // virtual registers. e.g. v1024 = move r0.
86 DenseMap<unsigned, unsigned> SrcRegMap;
88 // DstRegMap - A map from virtual registers to physical registers which are
89 // likely targets to be coalesced to due to copies to physical registers from
90 // virtual registers. e.g. r1 = move v1024.
91 DenseMap<unsigned, unsigned> DstRegMap;
93 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
94 MachineBasicBlock::iterator OldPos);
96 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
98 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
99 MachineInstr *MI, unsigned Dist);
101 bool commuteInstruction(MachineBasicBlock::iterator &mi,
102 unsigned RegB, unsigned RegC, unsigned Dist);
104 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
106 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
107 MachineBasicBlock::iterator &nmi,
108 unsigned RegA, unsigned RegB, unsigned Dist);
110 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
112 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
113 MachineBasicBlock::iterator &nmi,
115 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
116 MachineBasicBlock::iterator &nmi,
119 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
120 MachineBasicBlock::iterator &nmi,
121 unsigned SrcIdx, unsigned DstIdx,
122 unsigned Dist, bool shouldOnlyCommute);
124 void scanUses(unsigned DstReg);
126 void processCopy(MachineInstr *MI);
128 typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
129 typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
130 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
131 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
132 void eliminateRegSequence(MachineBasicBlock::iterator&);
135 static char ID; // Pass identification, replacement for typeid
136 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
137 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
140 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
141 AU.setPreservesCFG();
142 AU.addRequired<AliasAnalysis>();
143 AU.addPreserved<LiveVariables>();
144 AU.addPreserved<SlotIndexes>();
145 AU.addPreserved<LiveIntervals>();
146 AU.addPreservedID(MachineLoopInfoID);
147 AU.addPreservedID(MachineDominatorsID);
148 MachineFunctionPass::getAnalysisUsage(AU);
151 /// runOnMachineFunction - Pass entry point.
152 bool runOnMachineFunction(MachineFunction&);
154 } // end anonymous namespace
156 char TwoAddressInstructionPass::ID = 0;
157 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
158 "Two-Address instruction pass", false, false)
159 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
160 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
161 "Two-Address instruction pass", false, false)
163 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
165 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
167 /// sink3AddrInstruction - A two-address instruction has been converted to a
168 /// three-address instruction to avoid clobbering a register. Try to sink it
169 /// past the instruction that would kill the above mentioned register to reduce
170 /// register pressure.
171 bool TwoAddressInstructionPass::
172 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
173 MachineBasicBlock::iterator OldPos) {
174 // FIXME: Shouldn't we be trying to do this before we three-addressify the
175 // instruction? After this transformation is done, we no longer need
176 // the instruction to be in three-address form.
178 // Check if it's safe to move this instruction.
179 bool SeenStore = true; // Be conservative.
180 if (!MI->isSafeToMove(TII, AA, SeenStore))
184 SmallSet<unsigned, 4> UseRegs;
186 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
187 const MachineOperand &MO = MI->getOperand(i);
190 unsigned MOReg = MO.getReg();
193 if (MO.isUse() && MOReg != SavedReg)
194 UseRegs.insert(MO.getReg());
198 // Don't try to move it if it implicitly defines a register.
201 // For now, don't move any instructions that define multiple registers.
203 DefReg = MO.getReg();
206 // Find the instruction that kills SavedReg.
207 MachineInstr *KillMI = NULL;
209 LiveInterval &LI = LIS->getInterval(SavedReg);
210 assert(LI.end() != LI.begin() &&
211 "Reg should not have empty live interval.");
213 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
214 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
215 if (I != LI.end() && I->start < MBBEndIdx)
219 KillMI = LIS->getInstructionFromIndex(I->end);
222 for (MachineRegisterInfo::use_nodbg_iterator
223 UI = MRI->use_nodbg_begin(SavedReg),
224 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
225 MachineOperand &UseMO = UI.getOperand();
228 KillMI = UseMO.getParent();
233 // If we find the instruction that kills SavedReg, and it is in an
234 // appropriate location, we can try to sink the current instruction
236 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
237 KillMI == OldPos || KillMI->isTerminator())
240 // If any of the definitions are used by another instruction between the
241 // position and the kill use, then it's not safe to sink it.
243 // FIXME: This can be sped up if there is an easy way to query whether an
244 // instruction is before or after another instruction. Then we can use
245 // MachineRegisterInfo def / use instead.
246 MachineOperand *KillMO = NULL;
247 MachineBasicBlock::iterator KillPos = KillMI;
250 unsigned NumVisited = 0;
251 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
252 MachineInstr *OtherMI = I;
253 // DBG_VALUE cannot be counted against the limit.
254 if (OtherMI->isDebugValue())
256 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
259 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
260 MachineOperand &MO = OtherMI->getOperand(i);
263 unsigned MOReg = MO.getReg();
269 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) {
270 if (OtherMI == KillMI && MOReg == SavedReg)
271 // Save the operand that kills the register. We want to unset the kill
272 // marker if we can sink MI past it.
274 else if (UseRegs.count(MOReg))
275 // One of the uses is killed before the destination.
280 assert(KillMO && "Didn't find kill");
283 // Update kill and LV information.
284 KillMO->setIsKill(false);
285 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
286 KillMO->setIsKill(true);
289 LV->replaceKillInstruction(SavedReg, KillMI, MI);
292 // Move instruction to its destination.
294 MBB->insert(KillPos, MI);
303 /// noUseAfterLastDef - Return true if there are no intervening uses between the
304 /// last instruction in the MBB that defines the specified register and the
305 /// two-address instruction which is being processed. It also returns the last
306 /// def location by reference
307 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
310 unsigned LastUse = Dist;
311 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
312 E = MRI->reg_end(); I != E; ++I) {
313 MachineOperand &MO = I.getOperand();
314 MachineInstr *MI = MO.getParent();
315 if (MI->getParent() != MBB || MI->isDebugValue())
317 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
318 if (DI == DistanceMap.end())
320 if (MO.isUse() && DI->second < LastUse)
321 LastUse = DI->second;
322 if (MO.isDef() && DI->second > LastDef)
323 LastDef = DI->second;
326 return !(LastUse > LastDef && LastUse < Dist);
329 /// isCopyToReg - Return true if the specified MI is a copy instruction or
330 /// a extract_subreg instruction. It also returns the source and destination
331 /// registers and whether they are physical registers by reference.
332 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
333 unsigned &SrcReg, unsigned &DstReg,
334 bool &IsSrcPhys, bool &IsDstPhys) {
338 DstReg = MI.getOperand(0).getReg();
339 SrcReg = MI.getOperand(1).getReg();
340 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
341 DstReg = MI.getOperand(0).getReg();
342 SrcReg = MI.getOperand(2).getReg();
346 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
347 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
351 /// isPLainlyKilled - Test if the given register value, which is used by the
352 // given instruction, is killed by the given instruction.
353 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
354 LiveIntervals *LIS) {
355 if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
356 !LIS->isNotInMIMap(MI)) {
357 // FIXME: Sometimes tryInstructionTransform() will add instructions and
358 // test whether they can be folded before keeping them. In this case it
359 // sets a kill before recursively calling tryInstructionTransform() again.
360 // If there is no interval available, we assume that this instruction is
361 // one of those. A kill flag is manually inserted on the operand so the
362 // check below will handle it.
363 LiveInterval &LI = LIS->getInterval(Reg);
364 // This is to match the kill flag version where undefs don't have kill
366 if (!LI.hasAtLeastOneValue())
369 SlotIndex useIdx = LIS->getInstructionIndex(MI);
370 LiveInterval::const_iterator I = LI.find(useIdx);
371 assert(I != LI.end() && "Reg must be live-in to use.");
372 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
375 return MI->killsRegister(Reg);
378 /// isKilled - Test if the given register value, which is used by the given
379 /// instruction, is killed by the given instruction. This looks through
380 /// coalescable copies to see if the original value is potentially not killed.
382 /// For example, in this code:
384 /// %reg1034 = copy %reg1024
385 /// %reg1035 = copy %reg1025<kill>
386 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
388 /// %reg1034 is not considered to be killed, since it is copied from a
389 /// register which is not killed. Treating it as not killed lets the
390 /// normal heuristics commute the (two-address) add, which lets
391 /// coalescing eliminate the extra copy.
393 /// If allowFalsePositives is true then likely kills are treated as kills even
394 /// if it can't be proven that they are kills.
395 static bool isKilled(MachineInstr &MI, unsigned Reg,
396 const MachineRegisterInfo *MRI,
397 const TargetInstrInfo *TII,
399 bool allowFalsePositives) {
400 MachineInstr *DefMI = &MI;
402 // All uses of physical registers are likely to be kills.
403 if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
404 (allowFalsePositives || MRI->hasOneUse(Reg)))
406 if (!isPlainlyKilled(DefMI, Reg, LIS))
408 if (TargetRegisterInfo::isPhysicalRegister(Reg))
410 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
411 // If there are multiple defs, we can't do a simple analysis, so just
412 // go with what the kill flag says.
413 if (llvm::next(Begin) != MRI->def_end())
416 bool IsSrcPhys, IsDstPhys;
417 unsigned SrcReg, DstReg;
418 // If the def is something other than a copy, then it isn't going to
419 // be coalesced, so follow the kill flag.
420 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
426 /// isTwoAddrUse - Return true if the specified MI uses the specified register
427 /// as a two-address use. If so, return the destination register by reference.
428 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
429 const MCInstrDesc &MCID = MI.getDesc();
430 unsigned NumOps = MI.isInlineAsm()
431 ? MI.getNumOperands() : MCID.getNumOperands();
432 for (unsigned i = 0; i != NumOps; ++i) {
433 const MachineOperand &MO = MI.getOperand(i);
434 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
437 if (MI.isRegTiedToDefOperand(i, &ti)) {
438 DstReg = MI.getOperand(ti).getReg();
445 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
446 /// use, return the use instruction if it's a copy or a two-address use.
448 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
449 MachineRegisterInfo *MRI,
450 const TargetInstrInfo *TII,
452 unsigned &DstReg, bool &IsDstPhys) {
453 if (!MRI->hasOneNonDBGUse(Reg))
454 // None or more than one use.
456 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
457 if (UseMI.getParent() != MBB)
461 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
466 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
467 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
473 /// getMappedReg - Return the physical register the specified virtual register
474 /// might be mapped to.
476 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
477 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
478 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
479 if (SI == RegMap.end())
483 if (TargetRegisterInfo::isPhysicalRegister(Reg))
488 /// regsAreCompatible - Return true if the two registers are equal or aliased.
491 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
496 return TRI->regsOverlap(RegA, RegB);
500 /// isProfitableToCommute - Return true if it's potentially profitable to commute
501 /// the two-address instruction that's being processed.
503 TwoAddressInstructionPass::
504 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
505 MachineInstr *MI, unsigned Dist) {
506 if (OptLevel == CodeGenOpt::None)
509 // Determine if it's profitable to commute this two address instruction. In
510 // general, we want no uses between this instruction and the definition of
511 // the two-address register.
513 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
514 // %reg1029<def> = MOV8rr %reg1028
515 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
516 // insert => %reg1030<def> = MOV8rr %reg1028
517 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
518 // In this case, it might not be possible to coalesce the second MOV8rr
519 // instruction if the first one is coalesced. So it would be profitable to
521 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
522 // %reg1029<def> = MOV8rr %reg1028
523 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
524 // insert => %reg1030<def> = MOV8rr %reg1029
525 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
527 if (!isPlainlyKilled(MI, regC, LIS))
530 // Ok, we have something like:
531 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
532 // let's see if it's worth commuting it.
534 // Look for situations like this:
535 // %reg1024<def> = MOV r1
536 // %reg1025<def> = MOV r0
537 // %reg1026<def> = ADD %reg1024, %reg1025
539 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
540 unsigned ToRegA = getMappedReg(regA, DstRegMap);
542 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
543 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
544 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI);
545 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI);
547 return !BComp && CComp;
550 // If there is a use of regC between its last def (could be livein) and this
551 // instruction, then bail.
552 unsigned LastDefC = 0;
553 if (!noUseAfterLastDef(regC, Dist, LastDefC))
556 // If there is a use of regB between its last def (could be livein) and this
557 // instruction, then go ahead and make this transformation.
558 unsigned LastDefB = 0;
559 if (!noUseAfterLastDef(regB, Dist, LastDefB))
562 // Since there are no intervening uses for both registers, then commute
563 // if the def of regC is closer. Its live interval is shorter.
564 return LastDefB && LastDefC && LastDefC > LastDefB;
567 /// commuteInstruction - Commute a two-address instruction and update the basic
568 /// block, distance map, and live variables if needed. Return true if it is
570 bool TwoAddressInstructionPass::
571 commuteInstruction(MachineBasicBlock::iterator &mi,
572 unsigned RegB, unsigned RegC, unsigned Dist) {
573 MachineInstr *MI = mi;
574 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
575 MachineInstr *NewMI = TII->commuteInstruction(MI);
578 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
582 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
583 assert(NewMI == MI &&
584 "TargetInstrInfo::commuteInstruction() should not return a new "
585 "instruction unless it was requested.");
587 // Update source register map.
588 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
590 unsigned RegA = MI->getOperand(0).getReg();
591 SrcRegMap[RegA] = FromRegC;
597 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
598 /// given 2-address instruction to a 3-address one.
600 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
601 // Look for situations like this:
602 // %reg1024<def> = MOV r1
603 // %reg1025<def> = MOV r0
604 // %reg1026<def> = ADD %reg1024, %reg1025
606 // Turn ADD into a 3-address instruction to avoid a copy.
607 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
610 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
611 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
614 /// convertInstTo3Addr - Convert the specified two-address instruction into a
615 /// three address one. Return true if this transformation was successful.
617 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
618 MachineBasicBlock::iterator &nmi,
619 unsigned RegA, unsigned RegB,
621 // FIXME: Why does convertToThreeAddress() need an iterator reference?
622 MachineFunction::iterator MFI = MBB;
623 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
624 assert(MBB == MFI && "convertToThreeAddress changed iterator reference");
628 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
629 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
633 LIS->ReplaceMachineInstrInMaps(mi, NewMI);
635 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
636 // FIXME: Temporary workaround. If the new instruction doesn't
637 // uses RegB, convertToThreeAddress must have created more
638 // then one instruction.
639 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
641 MBB->erase(mi); // Nuke the old inst.
644 DistanceMap.insert(std::make_pair(NewMI, Dist));
646 nmi = llvm::next(mi);
649 // Update source and destination register maps.
650 SrcRegMap.erase(RegA);
651 DstRegMap.erase(RegB);
655 /// scanUses - Scan forward recursively for only uses, update maps if the use
656 /// is a copy or a two-address instruction.
658 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
659 SmallVector<unsigned, 4> VirtRegPairs;
663 unsigned Reg = DstReg;
664 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
665 NewReg, IsDstPhys)) {
666 if (IsCopy && !Processed.insert(UseMI))
669 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
670 if (DI != DistanceMap.end())
671 // Earlier in the same MBB.Reached via a back edge.
675 VirtRegPairs.push_back(NewReg);
678 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
680 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
681 VirtRegPairs.push_back(NewReg);
685 if (!VirtRegPairs.empty()) {
686 unsigned ToReg = VirtRegPairs.back();
687 VirtRegPairs.pop_back();
688 while (!VirtRegPairs.empty()) {
689 unsigned FromReg = VirtRegPairs.back();
690 VirtRegPairs.pop_back();
691 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
693 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
696 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
698 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
702 /// processCopy - If the specified instruction is not yet processed, process it
703 /// if it's a copy. For a copy instruction, we find the physical registers the
704 /// source and destination registers might be mapped to. These are kept in
705 /// point-to maps used to determine future optimizations. e.g.
708 /// v1026 = add v1024, v1025
710 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
711 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
712 /// potentially joined with r1 on the output side. It's worthwhile to commute
713 /// 'add' to eliminate a copy.
714 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
715 if (Processed.count(MI))
718 bool IsSrcPhys, IsDstPhys;
719 unsigned SrcReg, DstReg;
720 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
723 if (IsDstPhys && !IsSrcPhys)
724 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
725 else if (!IsDstPhys && IsSrcPhys) {
726 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
728 assert(SrcRegMap[DstReg] == SrcReg &&
729 "Can't map to two src physical registers!");
734 Processed.insert(MI);
738 /// rescheduleMIBelowKill - If there is one more local instruction that reads
739 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
740 /// instruction in order to eliminate the need for the copy.
741 bool TwoAddressInstructionPass::
742 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
743 MachineBasicBlock::iterator &nmi,
745 // Bail immediately if we don't have LV or LIS available. We use them to find
746 // kills efficiently.
750 MachineInstr *MI = &*mi;
751 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
752 if (DI == DistanceMap.end())
753 // Must be created from unfolded load. Don't waste time trying this.
756 MachineInstr *KillMI = 0;
758 LiveInterval &LI = LIS->getInterval(Reg);
759 assert(LI.end() != LI.begin() &&
760 "Reg should not have empty live interval.");
762 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
763 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
764 if (I != LI.end() && I->start < MBBEndIdx)
768 KillMI = LIS->getInstructionFromIndex(I->end);
770 KillMI = LV->getVarInfo(Reg).findKill(MBB);
772 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
773 // Don't mess with copies, they may be coalesced later.
776 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
777 KillMI->isBranch() || KillMI->isTerminator())
778 // Don't move pass calls, etc.
782 if (isTwoAddrUse(*KillMI, Reg, DstReg))
785 bool SeenStore = true;
786 if (!MI->isSafeToMove(TII, AA, SeenStore))
789 if (TII->getInstrLatency(InstrItins, MI) > 1)
790 // FIXME: Needs more sophisticated heuristics.
793 SmallSet<unsigned, 2> Uses;
794 SmallSet<unsigned, 2> Kills;
795 SmallSet<unsigned, 2> Defs;
796 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
797 const MachineOperand &MO = MI->getOperand(i);
800 unsigned MOReg = MO.getReg();
807 if (MOReg != Reg && (MO.isKill() ||
808 (LIS && isPlainlyKilled(MI, MOReg, LIS))))
813 // Move the copies connected to MI down as well.
814 MachineBasicBlock::iterator Begin = MI;
815 MachineBasicBlock::iterator AfterMI = llvm::next(Begin);
817 MachineBasicBlock::iterator End = AfterMI;
818 while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
819 Defs.insert(End->getOperand(0).getReg());
823 // Check if the reschedule will not break depedencies.
824 unsigned NumVisited = 0;
825 MachineBasicBlock::iterator KillPos = KillMI;
827 for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) {
828 MachineInstr *OtherMI = I;
829 // DBG_VALUE cannot be counted against the limit.
830 if (OtherMI->isDebugValue())
832 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
835 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
836 OtherMI->isBranch() || OtherMI->isTerminator())
837 // Don't move pass calls, etc.
839 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
840 const MachineOperand &MO = OtherMI->getOperand(i);
843 unsigned MOReg = MO.getReg();
847 if (Uses.count(MOReg))
848 // Physical register use would be clobbered.
850 if (!MO.isDead() && Defs.count(MOReg))
851 // May clobber a physical register def.
852 // FIXME: This may be too conservative. It's ok if the instruction
853 // is sunken completely below the use.
856 if (Defs.count(MOReg))
858 bool isKill = MO.isKill() ||
859 (LIS && isPlainlyKilled(OtherMI, MOReg, LIS));
861 ((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
862 // Don't want to extend other live ranges and update kills.
864 if (MOReg == Reg && !isKill)
865 // We can't schedule across a use of the register in question.
867 // Ensure that if this is register in question, its the kill we expect.
868 assert((MOReg != Reg || OtherMI == KillMI) &&
869 "Found multiple kills of a register in a basic block");
874 // Move debug info as well.
875 while (Begin != MBB->begin() && llvm::prior(Begin)->isDebugValue())
879 MachineBasicBlock::iterator InsertPos = KillPos;
881 // We have to move the copies first so that the MBB is still well-formed
882 // when calling handleMove().
883 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
884 MachineInstr *CopyMI = MBBI;
886 MBB->splice(InsertPos, MBB, CopyMI);
887 LIS->handleMove(CopyMI);
890 End = llvm::next(MachineBasicBlock::iterator(MI));
893 // Copies following MI may have been moved as well.
894 MBB->splice(InsertPos, MBB, Begin, End);
895 DistanceMap.erase(DI);
897 // Update live variables
901 LV->removeVirtualRegisterKilled(Reg, KillMI);
902 LV->addVirtualRegisterKilled(Reg, MI);
905 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
909 /// isDefTooClose - Return true if the re-scheduling will put the given
910 /// instruction too close to the defs of its register dependencies.
911 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
913 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
914 DE = MRI->def_end(); DI != DE; ++DI) {
915 MachineInstr *DefMI = &*DI;
916 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
919 return true; // MI is defining something KillMI uses
920 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
921 if (DDI == DistanceMap.end())
922 return true; // Below MI
923 unsigned DefDist = DDI->second;
924 assert(Dist > DefDist && "Visited def already?");
925 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
931 /// rescheduleKillAboveMI - If there is one more local instruction that reads
932 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
933 /// current two-address instruction in order to eliminate the need for the
935 bool TwoAddressInstructionPass::
936 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
937 MachineBasicBlock::iterator &nmi,
939 // Bail immediately if we don't have LV or LIS available. We use them to find
940 // kills efficiently.
944 MachineInstr *MI = &*mi;
945 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
946 if (DI == DistanceMap.end())
947 // Must be created from unfolded load. Don't waste time trying this.
950 MachineInstr *KillMI = 0;
952 LiveInterval &LI = LIS->getInterval(Reg);
953 assert(LI.end() != LI.begin() &&
954 "Reg should not have empty live interval.");
956 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
957 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
958 if (I != LI.end() && I->start < MBBEndIdx)
962 KillMI = LIS->getInstructionFromIndex(I->end);
964 KillMI = LV->getVarInfo(Reg).findKill(MBB);
966 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
967 // Don't mess with copies, they may be coalesced later.
971 if (isTwoAddrUse(*KillMI, Reg, DstReg))
974 bool SeenStore = true;
975 if (!KillMI->isSafeToMove(TII, AA, SeenStore))
978 SmallSet<unsigned, 2> Uses;
979 SmallSet<unsigned, 2> Kills;
980 SmallSet<unsigned, 2> Defs;
981 SmallSet<unsigned, 2> LiveDefs;
982 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
983 const MachineOperand &MO = KillMI->getOperand(i);
986 unsigned MOReg = MO.getReg();
990 if (isDefTooClose(MOReg, DI->second, MI))
992 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
993 if (MOReg == Reg && !isKill)
996 if (isKill && MOReg != Reg)
998 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1001 LiveDefs.insert(MOReg);
1005 // Check if the reschedule will not break depedencies.
1006 unsigned NumVisited = 0;
1007 MachineBasicBlock::iterator KillPos = KillMI;
1008 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
1009 MachineInstr *OtherMI = I;
1010 // DBG_VALUE cannot be counted against the limit.
1011 if (OtherMI->isDebugValue())
1013 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1016 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
1017 OtherMI->isBranch() || OtherMI->isTerminator())
1018 // Don't move pass calls, etc.
1020 SmallVector<unsigned, 2> OtherDefs;
1021 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
1022 const MachineOperand &MO = OtherMI->getOperand(i);
1025 unsigned MOReg = MO.getReg();
1029 if (Defs.count(MOReg))
1030 // Moving KillMI can clobber the physical register if the def has
1033 if (Kills.count(MOReg))
1034 // Don't want to extend other live ranges and update kills.
1036 if (OtherMI != MI && MOReg == Reg &&
1037 !(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))))
1038 // We can't schedule across a use of the register in question.
1041 OtherDefs.push_back(MOReg);
1045 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1046 unsigned MOReg = OtherDefs[i];
1047 if (Uses.count(MOReg))
1049 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1050 LiveDefs.count(MOReg))
1052 // Physical register def is seen.
1057 // Move the old kill above MI, don't forget to move debug info as well.
1058 MachineBasicBlock::iterator InsertPos = mi;
1059 while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
1061 MachineBasicBlock::iterator From = KillMI;
1062 MachineBasicBlock::iterator To = llvm::next(From);
1063 while (llvm::prior(From)->isDebugValue())
1065 MBB->splice(InsertPos, MBB, From, To);
1067 nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr.
1068 DistanceMap.erase(DI);
1070 // Update live variables
1072 LIS->handleMove(KillMI);
1074 LV->removeVirtualRegisterKilled(Reg, KillMI);
1075 LV->addVirtualRegisterKilled(Reg, MI);
1078 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1082 /// tryInstructionTransform - For the case where an instruction has a single
1083 /// pair of tied register operands, attempt some transformations that may
1084 /// either eliminate the tied operands or improve the opportunities for
1085 /// coalescing away the register copy. Returns true if no copy needs to be
1086 /// inserted to untie mi's operands (either because they were untied, or
1087 /// because mi was rescheduled, and will be visited again later). If the
1088 /// shouldOnlyCommute flag is true, only instruction commutation is attempted.
1089 bool TwoAddressInstructionPass::
1090 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1091 MachineBasicBlock::iterator &nmi,
1092 unsigned SrcIdx, unsigned DstIdx,
1093 unsigned Dist, bool shouldOnlyCommute) {
1094 if (OptLevel == CodeGenOpt::None)
1097 MachineInstr &MI = *mi;
1098 unsigned regA = MI.getOperand(DstIdx).getReg();
1099 unsigned regB = MI.getOperand(SrcIdx).getReg();
1101 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1102 "cannot make instruction into two-address form");
1103 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1105 if (TargetRegisterInfo::isVirtualRegister(regA))
1108 // Check if it is profitable to commute the operands.
1109 unsigned SrcOp1, SrcOp2;
1111 unsigned regCIdx = ~0U;
1112 bool TryCommute = false;
1113 bool AggressiveCommute = false;
1114 if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
1115 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1116 if (SrcIdx == SrcOp1)
1118 else if (SrcIdx == SrcOp2)
1121 if (regCIdx != ~0U) {
1122 regC = MI.getOperand(regCIdx).getReg();
1123 if (!regBKilled && isKilled(MI, regC, MRI, TII, LIS, false))
1124 // If C dies but B does not, swap the B and C operands.
1125 // This makes the live ranges of A and C joinable.
1127 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1129 AggressiveCommute = true;
1134 // If it's profitable to commute, try to do so.
1135 if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
1137 if (AggressiveCommute)
1142 if (shouldOnlyCommute)
1145 // If there is one more use of regB later in the same MBB, consider
1146 // re-schedule this MI below it.
1147 if (rescheduleMIBelowKill(mi, nmi, regB)) {
1152 if (MI.isConvertibleTo3Addr()) {
1153 // This instruction is potentially convertible to a true
1154 // three-address instruction. Check if it is profitable.
1155 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1156 // Try to convert it.
1157 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1158 ++NumConvertedTo3Addr;
1159 return true; // Done with this instruction.
1164 // If there is one more use of regB later in the same MBB, consider
1165 // re-schedule it before this MI if it's legal.
1166 if (rescheduleKillAboveMI(mi, nmi, regB)) {
1171 // If this is an instruction with a load folded into it, try unfolding
1172 // the load, e.g. avoid this:
1174 // addq (%rax), %rcx
1175 // in favor of this:
1176 // movq (%rax), %rcx
1178 // because it's preferable to schedule a load than a register copy.
1179 if (MI.mayLoad() && !regBKilled) {
1180 // Determine if a load can be unfolded.
1181 unsigned LoadRegIndex;
1183 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1184 /*UnfoldLoad=*/true,
1185 /*UnfoldStore=*/false,
1188 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1189 if (UnfoldMCID.getNumDefs() == 1) {
1191 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1192 const TargetRegisterClass *RC =
1193 TRI->getAllocatableClass(
1194 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1195 unsigned Reg = MRI->createVirtualRegister(RC);
1196 SmallVector<MachineInstr *, 2> NewMIs;
1197 if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
1198 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1200 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1203 assert(NewMIs.size() == 2 &&
1204 "Unfolded a load into multiple instructions!");
1205 // The load was previously folded, so this is the only use.
1206 NewMIs[1]->addRegisterKilled(Reg, TRI);
1208 // Tentatively insert the instructions into the block so that they
1209 // look "normal" to the transformation logic.
1210 MBB->insert(mi, NewMIs[0]);
1211 MBB->insert(mi, NewMIs[1]);
1213 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1214 << "2addr: NEW INST: " << *NewMIs[1]);
1216 // Transform the instruction, now that it no longer has a load.
1217 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1218 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1219 MachineBasicBlock::iterator NewMI = NewMIs[1];
1220 bool TransformResult =
1221 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1222 (void)TransformResult;
1223 assert(!TransformResult &&
1224 "tryInstructionTransform() should return false.");
1225 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1226 // Success, or at least we made an improvement. Keep the unfolded
1227 // instructions and discard the original.
1229 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1230 MachineOperand &MO = MI.getOperand(i);
1232 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1235 if (NewMIs[0]->killsRegister(MO.getReg()))
1236 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1238 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1239 "Kill missing after load unfold!");
1240 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1243 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1244 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1245 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1247 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1248 "Dead flag missing after load unfold!");
1249 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1254 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1257 SmallVector<unsigned, 4> OrigRegs;
1259 for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
1260 MOE = MI.operands_end(); MOI != MOE; ++MOI) {
1262 OrigRegs.push_back(MOI->getReg());
1266 MI.eraseFromParent();
1268 // Update LiveIntervals.
1270 MachineBasicBlock::iterator Begin(NewMIs[0]);
1271 MachineBasicBlock::iterator End(NewMIs[1]);
1272 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1277 // Transforming didn't eliminate the tie and didn't lead to an
1278 // improvement. Clean up the unfolded instructions and keep the
1280 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1281 NewMIs[0]->eraseFromParent();
1282 NewMIs[1]->eraseFromParent();
1291 // Collect tied operands of MI that need to be handled.
1292 // Rewrite trivial cases immediately.
1293 // Return true if any tied operands where found, including the trivial ones.
1294 bool TwoAddressInstructionPass::
1295 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1296 const MCInstrDesc &MCID = MI->getDesc();
1297 bool AnyOps = false;
1298 unsigned NumOps = MI->getNumOperands();
1300 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1301 unsigned DstIdx = 0;
1302 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1305 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1306 MachineOperand &DstMO = MI->getOperand(DstIdx);
1307 unsigned SrcReg = SrcMO.getReg();
1308 unsigned DstReg = DstMO.getReg();
1309 // Tied constraint already satisfied?
1310 if (SrcReg == DstReg)
1313 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1315 // Deal with <undef> uses immediately - simply rewrite the src operand.
1316 if (SrcMO.isUndef()) {
1317 // Constrain the DstReg register class if required.
1318 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1319 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1321 MRI->constrainRegClass(DstReg, RC);
1322 SrcMO.setReg(DstReg);
1323 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1326 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1331 // Process a list of tied MI operands that all use the same source register.
1332 // The tied pairs are of the form (SrcIdx, DstIdx).
1334 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1335 TiedPairList &TiedPairs,
1337 bool IsEarlyClobber = false;
1338 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1339 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1340 IsEarlyClobber |= DstMO.isEarlyClobber();
1343 bool RemovedKillFlag = false;
1344 bool AllUsesCopied = true;
1345 unsigned LastCopiedReg = 0;
1346 SlotIndex LastCopyIdx;
1348 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1349 unsigned SrcIdx = TiedPairs[tpi].first;
1350 unsigned DstIdx = TiedPairs[tpi].second;
1352 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1353 unsigned RegA = DstMO.getReg();
1355 // Grab RegB from the instruction because it may have changed if the
1356 // instruction was commuted.
1357 RegB = MI->getOperand(SrcIdx).getReg();
1360 // The register is tied to multiple destinations (or else we would
1361 // not have continued this far), but this use of the register
1362 // already matches the tied destination. Leave it.
1363 AllUsesCopied = false;
1366 LastCopiedReg = RegA;
1368 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1369 "cannot make instruction into two-address form");
1372 // First, verify that we don't have a use of "a" in the instruction
1373 // (a = b + a for example) because our transformation will not
1374 // work. This should never occur because we are in SSA form.
1375 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1376 assert(i == DstIdx ||
1377 !MI->getOperand(i).isReg() ||
1378 MI->getOperand(i).getReg() != RegA);
1382 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1383 TII->get(TargetOpcode::COPY), RegA).addReg(RegB);
1385 // Update DistanceMap.
1386 MachineBasicBlock::iterator PrevMI = MI;
1388 DistanceMap.insert(std::make_pair(PrevMI, Dist));
1389 DistanceMap[MI] = ++Dist;
1392 LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot();
1394 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1395 LiveInterval &LI = LIS->getInterval(RegA);
1396 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1398 LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber);
1399 LI.addRange(LiveRange(LastCopyIdx, endIdx, VNI));
1403 DEBUG(dbgs() << "\t\tprepend:\t" << *PrevMI);
1405 MachineOperand &MO = MI->getOperand(SrcIdx);
1406 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1407 "inconsistent operand info for 2-reg pass");
1409 MO.setIsKill(false);
1410 RemovedKillFlag = true;
1413 // Make sure regA is a legal regclass for the SrcIdx operand.
1414 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1415 TargetRegisterInfo::isVirtualRegister(RegB))
1416 MRI->constrainRegClass(RegA, MRI->getRegClass(RegB));
1420 // Propagate SrcRegMap.
1421 SrcRegMap[RegA] = RegB;
1425 if (AllUsesCopied) {
1426 if (!IsEarlyClobber) {
1427 // Replace other (un-tied) uses of regB with LastCopiedReg.
1428 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1429 MachineOperand &MO = MI->getOperand(i);
1430 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1432 MO.setIsKill(false);
1433 RemovedKillFlag = true;
1435 MO.setReg(LastCopiedReg);
1440 // Update live variables for regB.
1441 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1442 MachineBasicBlock::iterator PrevMI = MI;
1444 LV->addVirtualRegisterKilled(RegB, PrevMI);
1447 // Update LiveIntervals.
1449 LiveInterval &LI = LIS->getInterval(RegB);
1450 SlotIndex MIIdx = LIS->getInstructionIndex(MI);
1451 LiveInterval::const_iterator I = LI.find(MIIdx);
1452 assert(I != LI.end() && "RegB must be live-in to use.");
1454 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1455 if (I->end == UseIdx)
1456 LI.removeRange(LastCopyIdx, UseIdx);
1459 } else if (RemovedKillFlag) {
1460 // Some tied uses of regB matched their destination registers, so
1461 // regB is still used in this instruction, but a kill flag was
1462 // removed from a different tied use of regB, so now we need to add
1463 // a kill flag to one of the remaining uses of regB.
1464 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1465 MachineOperand &MO = MI->getOperand(i);
1466 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1474 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1476 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1478 const TargetMachine &TM = MF->getTarget();
1479 MRI = &MF->getRegInfo();
1480 TII = TM.getInstrInfo();
1481 TRI = TM.getRegisterInfo();
1482 InstrItins = TM.getInstrItineraryData();
1483 LV = getAnalysisIfAvailable<LiveVariables>();
1484 LIS = getAnalysisIfAvailable<LiveIntervals>();
1485 AA = &getAnalysis<AliasAnalysis>();
1486 OptLevel = TM.getOptLevel();
1488 bool MadeChange = false;
1490 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1491 DEBUG(dbgs() << "********** Function: "
1492 << MF->getName() << '\n');
1494 // This pass takes the function out of SSA form.
1497 TiedOperandMap TiedOperands;
1498 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1499 MBBI != MBBE; ++MBBI) {
1502 DistanceMap.clear();
1506 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1508 MachineBasicBlock::iterator nmi = llvm::next(mi);
1509 if (mi->isDebugValue()) {
1514 // Expand REG_SEQUENCE instructions. This will position mi at the first
1515 // expanded instruction.
1516 if (mi->isRegSequence())
1517 eliminateRegSequence(mi);
1519 DistanceMap.insert(std::make_pair(mi, ++Dist));
1523 // First scan through all the tied register uses in this instruction
1524 // and record a list of pairs of tied operands for each register.
1525 if (!collectTiedOperands(mi, TiedOperands)) {
1530 ++NumTwoAddressInstrs;
1532 DEBUG(dbgs() << '\t' << *mi);
1534 // If the instruction has a single pair of tied operands, try some
1535 // transformations that may either eliminate the tied operands or
1536 // improve the opportunities for coalescing away the register copy.
1537 if (TiedOperands.size() == 1) {
1538 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs
1539 = TiedOperands.begin()->second;
1540 if (TiedPairs.size() == 1) {
1541 unsigned SrcIdx = TiedPairs[0].first;
1542 unsigned DstIdx = TiedPairs[0].second;
1543 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1544 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1545 if (SrcReg != DstReg &&
1546 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1547 // The tied operands have been eliminated or shifted further down the
1548 // block to ease elimination. Continue processing with 'nmi'.
1549 TiedOperands.clear();
1556 // Now iterate over the information collected above.
1557 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1558 OE = TiedOperands.end(); OI != OE; ++OI) {
1559 processTiedPairs(mi, OI->second, Dist);
1560 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1563 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1564 if (mi->isInsertSubreg()) {
1565 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1566 // To %reg:subidx = COPY %subreg
1567 unsigned SubIdx = mi->getOperand(3).getImm();
1568 mi->RemoveOperand(3);
1569 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1570 mi->getOperand(0).setSubReg(SubIdx);
1571 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1572 mi->RemoveOperand(1);
1573 mi->setDesc(TII->get(TargetOpcode::COPY));
1574 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1577 // Clear TiedOperands here instead of at the top of the loop
1578 // since most instructions do not have tied operands.
1579 TiedOperands.clear();
1585 MF->verify(this, "After two-address instruction pass");
1590 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1592 /// The instruction is turned into a sequence of sub-register copies:
1594 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1598 /// %dst:ssub0<def,undef> = COPY %v1
1599 /// %dst:ssub1<def> = COPY %v2
1601 void TwoAddressInstructionPass::
1602 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1603 MachineInstr *MI = MBBI;
1604 unsigned DstReg = MI->getOperand(0).getReg();
1605 if (MI->getOperand(0).getSubReg() ||
1606 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1607 !(MI->getNumOperands() & 1)) {
1608 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1609 llvm_unreachable(0);
1612 SmallVector<unsigned, 4> OrigRegs;
1614 OrigRegs.push_back(MI->getOperand(0).getReg());
1615 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2)
1616 OrigRegs.push_back(MI->getOperand(i).getReg());
1619 bool DefEmitted = false;
1620 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1621 MachineOperand &UseMO = MI->getOperand(i);
1622 unsigned SrcReg = UseMO.getReg();
1623 unsigned SubIdx = MI->getOperand(i+1).getImm();
1624 // Nothing needs to be inserted for <undef> operands.
1625 if (UseMO.isUndef())
1628 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1629 // might insert a COPY that uses SrcReg after is was killed.
1630 bool isKill = UseMO.isKill();
1632 for (unsigned j = i + 2; j < e; j += 2)
1633 if (MI->getOperand(j).getReg() == SrcReg) {
1634 MI->getOperand(j).setIsKill();
1635 UseMO.setIsKill(false);
1640 // Insert the sub-register copy.
1641 MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1642 TII->get(TargetOpcode::COPY))
1643 .addReg(DstReg, RegState::Define, SubIdx)
1646 // The first def needs an <undef> flag because there is no live register
1649 CopyMI->getOperand(0).setIsUndef(true);
1650 // Return an iterator pointing to the first inserted instr.
1655 // Update LiveVariables' kill info.
1656 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1657 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1659 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1662 MachineBasicBlock::iterator EndMBBI =
1663 llvm::next(MachineBasicBlock::iterator(MI));
1666 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1667 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1668 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1669 MI->RemoveOperand(j);
1671 DEBUG(dbgs() << "Eliminated: " << *MI);
1672 MI->eraseFromParent();
1675 // Udpate LiveIntervals.
1677 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);