1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/DenseMap.h"
45 #include "llvm/ADT/SmallPtrSet.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/STLExtras.h"
50 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
51 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
52 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
53 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
54 STATISTIC(NumReMats, "Number of instructions re-materialized");
57 class VISIBILITY_HIDDEN TwoAddressInstructionPass
58 : public MachineFunctionPass {
59 const TargetInstrInfo *TII;
60 const TargetRegisterInfo *TRI;
61 MachineRegisterInfo *MRI;
64 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
66 MachineBasicBlock::iterator OldPos);
68 bool isSafeToReMat(unsigned DstReg, MachineInstr *MI);
69 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
70 MachineInstr *MI, MachineInstr *DefMI,
71 MachineBasicBlock *MBB, unsigned Loc,
72 DenseMap<MachineInstr*, unsigned> &DistanceMap);
74 static char ID; // Pass identification, replacement for typeid
75 TwoAddressInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
77 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
78 AU.addRequired<LiveVariables>();
79 AU.addPreserved<LiveVariables>();
80 AU.addPreservedID(MachineLoopInfoID);
81 AU.addPreservedID(MachineDominatorsID);
82 AU.addPreservedID(PHIEliminationID);
83 MachineFunctionPass::getAnalysisUsage(AU);
86 /// runOnMachineFunction - Pass entry point.
87 bool runOnMachineFunction(MachineFunction&);
91 char TwoAddressInstructionPass::ID = 0;
92 static RegisterPass<TwoAddressInstructionPass>
93 X("twoaddressinstruction", "Two-Address instruction pass");
95 const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
97 /// Sink3AddrInstruction - A two-address instruction has been converted to a
98 /// three-address instruction to avoid clobbering a register. Try to sink it
99 /// past the instruction that would kill the above mentioned register to reduce
100 /// register pressure.
101 bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
102 MachineInstr *MI, unsigned SavedReg,
103 MachineBasicBlock::iterator OldPos) {
104 // Check if it's safe to move this instruction.
105 bool SeenStore = true; // Be conservative.
106 if (!MI->isSafeToMove(TII, SeenStore))
110 SmallSet<unsigned, 4> UseRegs;
112 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
113 const MachineOperand &MO = MI->getOperand(i);
114 if (!MO.isRegister())
116 unsigned MOReg = MO.getReg();
119 if (MO.isUse() && MOReg != SavedReg)
120 UseRegs.insert(MO.getReg());
124 // Don't try to move it if it implicitly defines a register.
127 // For now, don't move any instructions that define multiple registers.
129 DefReg = MO.getReg();
132 // Find the instruction that kills SavedReg.
133 MachineInstr *KillMI = NULL;
134 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
135 UE = MRI->use_end(); UI != UE; ++UI) {
136 MachineOperand &UseMO = UI.getOperand();
139 KillMI = UseMO.getParent();
143 if (!KillMI || KillMI->getParent() != MBB)
146 // If any of the definitions are used by another instruction between the
147 // position and the kill use, then it's not safe to sink it.
149 // FIXME: This can be sped up if there is an easy way to query whether an
150 // instruction is before or after another instruction. Then we can use
151 // MachineRegisterInfo def / use instead.
152 MachineOperand *KillMO = NULL;
153 MachineBasicBlock::iterator KillPos = KillMI;
156 unsigned NumVisited = 0;
157 for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) {
158 MachineInstr *OtherMI = I;
159 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
162 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
163 MachineOperand &MO = OtherMI->getOperand(i);
164 if (!MO.isRegister())
166 unsigned MOReg = MO.getReg();
173 if (OtherMI == KillMI && MOReg == SavedReg)
174 // Save the operand that kills the register. We want to unset the kill
175 // marker if we can sink MI past it.
177 else if (UseRegs.count(MOReg))
178 // One of the uses is killed before the destination.
184 // Update kill and LV information.
185 KillMO->setIsKill(false);
186 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
187 KillMO->setIsKill(true);
188 LiveVariables::VarInfo& VarInfo = LV->getVarInfo(SavedReg);
189 VarInfo.removeKill(KillMI);
190 VarInfo.Kills.push_back(MI);
192 // Move instruction to its destination.
194 MBB->insert(KillPos, MI);
200 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
201 /// instruction which defined the specified register instead of copying it.
203 TwoAddressInstructionPass::isSafeToReMat(unsigned DstReg, MachineInstr *MI) {
204 const TargetInstrDesc &TID = MI->getDesc();
205 if (!TID.isAsCheapAsAMove())
207 bool SawStore = false;
208 if (!MI->isSafeToMove(TII, SawStore))
210 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
211 MachineOperand &MO = MI->getOperand(i);
212 if (!MO.isRegister())
214 // FIXME: For now, do not remat any instruction with register operands.
215 // Later on, we can loosen the restriction is the register operands have
216 // not been modified between the def and use. Note, this is different from
217 // MachineSink because the code in no longer in two-address form (at least
221 else if (!MO.isDead() && MO.getReg() != DstReg)
227 /// isTwoAddrUse - Return true if the specified MI is using the specified
228 /// register as a two-address operand.
229 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
230 const TargetInstrDesc &TID = UseMI->getDesc();
231 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
232 MachineOperand &MO = UseMI->getOperand(i);
233 if (MO.isRegister() && MO.getReg() == Reg &&
234 (MO.isDef() || TID.getOperandConstraint(i, TOI::TIED_TO) != -1))
235 // Earlier use is a two-address one.
241 /// isProfitableToReMat - Return true if the heuristics determines it is likely
242 /// to be profitable to re-materialize the definition of Reg rather than copy
245 TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
246 const TargetRegisterClass *RC,
247 MachineInstr *MI, MachineInstr *DefMI,
248 MachineBasicBlock *MBB, unsigned Loc,
249 DenseMap<MachineInstr*, unsigned> &DistanceMap){
250 bool OtherUse = false;
251 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
252 UE = MRI->use_end(); UI != UE; ++UI) {
253 MachineOperand &UseMO = UI.getOperand();
256 MachineInstr *UseMI = UseMO.getParent();
257 MachineBasicBlock *UseMBB = UseMI->getParent();
259 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
260 if (DI != DistanceMap.end() && DI->second == Loc)
261 continue; // Current use.
263 // There is at least one other use in the MBB that will clobber the
265 if (isTwoAddrUse(UseMI, Reg))
270 // If other uses in MBB are not two-address uses, then don't remat.
274 // No other uses in the same block, remat if it's defined in the same
275 // block so it does not unnecessarily extend the live range.
276 return MBB == DefMI->getParent();
279 /// runOnMachineFunction - Reduce two-address instructions to two operands.
281 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
282 DOUT << "Machine Function\n";
283 const TargetMachine &TM = MF.getTarget();
284 MRI = &MF.getRegInfo();
285 TII = TM.getInstrInfo();
286 TRI = TM.getRegisterInfo();
287 LV = &getAnalysis<LiveVariables>();
289 bool MadeChange = false;
291 DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n";
292 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
294 // ReMatRegs - Keep track of the registers whose def's are remat'ed.
296 ReMatRegs.resize(MRI->getLastVirtReg()+1);
298 // DistanceMap - Keep track the distance of a MI from the start of the
299 // current basic block.
300 DenseMap<MachineInstr*, unsigned> DistanceMap;
302 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
303 mbbi != mbbe; ++mbbi) {
306 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
308 MachineBasicBlock::iterator nmi = next(mi);
309 const TargetInstrDesc &TID = mi->getDesc();
310 bool FirstTied = true;
312 DistanceMap.insert(std::make_pair(mi, ++Dist));
313 for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
314 int ti = TID.getOperandConstraint(si, TOI::TIED_TO);
319 ++NumTwoAddressInstrs;
320 DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM));
325 assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() &&
326 mi->getOperand(si).isUse() && "two address instruction invalid");
328 // If the two operands are the same we just remove the use
329 // and mark the def as def&use, otherwise we have to insert a copy.
330 if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
336 unsigned regA = mi->getOperand(ti).getReg();
337 unsigned regB = mi->getOperand(si).getReg();
339 assert(TargetRegisterInfo::isVirtualRegister(regA) &&
340 TargetRegisterInfo::isVirtualRegister(regB) &&
341 "cannot update physical register live information");
344 // First, verify that we don't have a use of a in the instruction (a =
345 // b + a for example) because our transformation will not work. This
346 // should never occur because we are in SSA form.
347 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
348 assert((int)i == ti ||
349 !mi->getOperand(i).isRegister() ||
350 mi->getOperand(i).getReg() != regA);
353 // If this instruction is not the killing user of B, see if we can
354 // rearrange the code to make it so. Making it the killing user will
355 // allow us to coalesce A and B together, eliminating the copy we are
357 if (!mi->killsRegister(regB)) {
358 // If this instruction is commutative, check to see if C dies. If
359 // so, swap the B and C operands. This makes the live ranges of A
361 // FIXME: This code also works for A := B op C instructions.
362 if (TID.isCommutable() && mi->getNumOperands() >= 3) {
363 assert(mi->getOperand(3-si).isRegister() &&
364 "Not a proper commutative instruction!");
365 unsigned regC = mi->getOperand(3-si).getReg();
367 if (mi->killsRegister(regC)) {
368 DOUT << "2addr: COMMUTING : " << *mi;
369 MachineInstr *NewMI = TII->commuteInstruction(mi);
372 DOUT << "2addr: COMMUTING FAILED!\n";
374 DOUT << "2addr: COMMUTED TO: " << *NewMI;
375 // If the instruction changed to commute it, update livevar.
377 LV->instructionChanged(mi, NewMI); // Update live variables
378 mbbi->insert(mi, NewMI); // Insert the new inst
379 mbbi->erase(mi); // Nuke the old inst.
381 DistanceMap.insert(std::make_pair(NewMI, Dist));
386 goto InstructionRearranged;
391 // If this instruction is potentially convertible to a true
392 // three-address instruction,
393 if (TID.isConvertibleTo3Addr()) {
394 // FIXME: This assumes there are no more operands which are tied
395 // to another register.
397 for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i)
398 assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
401 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, *LV);
403 DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
404 DOUT << "2addr: TO 3-ADDR: " << *NewMI;
407 if (NewMI->findRegisterUseOperand(regB, false, TRI))
408 // FIXME: Temporary workaround. If the new instruction doesn't
409 // uses regB, convertToThreeAddress must have created more
410 // then one instruction.
411 Sunk = Sink3AddrInstruction(mbbi, NewMI, regB, mi);
413 mbbi->erase(mi); // Nuke the old inst.
416 DistanceMap.insert(std::make_pair(NewMI, Dist));
421 ++NumConvertedTo3Addr;
422 break; // Done with this instruction.
427 InstructionRearranged:
428 const TargetRegisterClass* rc = MRI->getRegClass(regA);
429 MachineInstr *DefMI = MRI->getVRegDef(regB);
430 // If it's safe and profitable, remat the definition instead of
433 isSafeToReMat(regB, DefMI) &&
434 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist,DistanceMap)){
435 DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n");
436 TII->reMaterialize(*mbbi, mi, regA, DefMI);
440 TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
443 MachineBasicBlock::iterator prevMi = prior(mi);
444 DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
446 // Update live variables for regB.
447 LiveVariables::VarInfo& varInfoB = LV->getVarInfo(regB);
449 // regB is used in this BB.
450 varInfoB.UsedBlocks[mbbi->getNumber()] = true;
452 if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
453 LV->addVirtualRegisterKilled(regB, prevMi);
455 if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
456 LV->addVirtualRegisterDead(regB, prevMi);
458 // Replace all occurences of regB with regA.
459 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
460 if (mi->getOperand(i).isRegister() &&
461 mi->getOperand(i).getReg() == regB)
462 mi->getOperand(i).setReg(regA);
466 assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
467 mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
470 DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM));
477 // Some remat'ed instructions are dead.
478 int VReg = ReMatRegs.find_first();
480 if (MRI->use_empty(VReg)) {
481 MachineInstr *DefMI = MRI->getVRegDef(VReg);
482 DefMI->eraseFromParent();
484 VReg = ReMatRegs.find_next(VReg);