1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfoImpl class, it just provides default
11 // implementations of various methods.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Target/TargetLowering.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PostRAHazardRecognizer.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
32 TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
33 MachineBasicBlock *NewDest) const {
34 MachineBasicBlock *MBB = Tail->getParent();
36 // Remove all the old successors of MBB from the CFG.
37 while (!MBB->succ_empty())
38 MBB->removeSuccessor(MBB->succ_begin());
40 // Remove all the dead instructions from the end of MBB.
41 MBB->erase(Tail, MBB->end());
43 // If MBB isn't immediately before MBB, insert a branch to it.
44 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
45 InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
47 MBB->addSuccessor(NewDest);
50 // commuteInstruction - The default implementation of this method just exchanges
51 // the two operands returned by findCommutedOpIndices.
52 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
54 const TargetInstrDesc &TID = MI->getDesc();
55 bool HasDef = TID.getNumDefs();
56 if (HasDef && !MI->getOperand(0).isReg())
57 // No idea how to commute this instruction. Target should implement its own.
60 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
62 raw_string_ostream Msg(msg);
63 Msg << "Don't know how to commute: " << *MI;
64 report_fatal_error(Msg.str());
67 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
68 "This only knows how to commute register operands so far");
69 unsigned Reg1 = MI->getOperand(Idx1).getReg();
70 unsigned Reg2 = MI->getOperand(Idx2).getReg();
71 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
72 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
73 bool ChangeReg0 = false;
74 if (HasDef && MI->getOperand(0).getReg() == Reg1) {
75 // Must be two address instruction!
76 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
77 "Expecting a two-address instruction!");
83 // Create a new instruction.
84 unsigned Reg0 = HasDef
85 ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
86 bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
87 MachineFunction &MF = *MI->getParent()->getParent();
89 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
90 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
91 .addReg(Reg2, getKillRegState(Reg2IsKill))
92 .addReg(Reg1, getKillRegState(Reg2IsKill));
94 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
95 .addReg(Reg2, getKillRegState(Reg2IsKill))
96 .addReg(Reg1, getKillRegState(Reg2IsKill));
100 MI->getOperand(0).setReg(Reg2);
101 MI->getOperand(Idx2).setReg(Reg1);
102 MI->getOperand(Idx1).setReg(Reg2);
103 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
104 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
108 /// findCommutedOpIndices - If specified MI is commutable, return the two
109 /// operand indices that would swap value. Return true if the instruction
110 /// is not in a form which this routine understands.
111 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
113 unsigned &SrcOpIdx2) const {
114 const TargetInstrDesc &TID = MI->getDesc();
115 if (!TID.isCommutable())
117 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
118 // is not true, then the target must implement this.
119 SrcOpIdx1 = TID.getNumDefs();
120 SrcOpIdx2 = SrcOpIdx1 + 1;
121 if (!MI->getOperand(SrcOpIdx1).isReg() ||
122 !MI->getOperand(SrcOpIdx2).isReg())
129 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
130 const SmallVectorImpl<MachineOperand> &Pred) const {
131 bool MadeChange = false;
132 const TargetInstrDesc &TID = MI->getDesc();
133 if (!TID.isPredicable())
136 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
137 if (TID.OpInfo[i].isPredicate()) {
138 MachineOperand &MO = MI->getOperand(i);
140 MO.setReg(Pred[j].getReg());
142 } else if (MO.isImm()) {
143 MO.setImm(Pred[j].getImm());
145 } else if (MO.isMBB()) {
146 MO.setMBB(Pred[j].getMBB());
155 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
156 MachineBasicBlock::iterator I,
159 const MachineInstr *Orig,
160 const TargetRegisterInfo &TRI) const {
161 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
162 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
166 bool TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0,
167 const MachineInstr *MI1) const {
168 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
171 MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
172 MachineFunction &MF) const {
173 assert(!Orig->getDesc().isNotDuplicable() &&
174 "Instruction cannot be duplicated");
175 return MF.CloneMachineInstr(Orig);
179 TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
181 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
183 const MachineBasicBlock &MBB = *MBBI;
184 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
186 FnSize += GetInstSizeInBytes(I);
191 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
192 /// slot into the specified machine instruction for the specified operand(s).
193 /// If this is possible, a new instruction is returned with the specified
194 /// operand folded, otherwise NULL is returned. The client is responsible for
195 /// removing the old instruction and adding the new one in the instruction
198 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
200 const SmallVectorImpl<unsigned> &Ops,
201 int FrameIndex) const {
203 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
204 if (MI->getOperand(Ops[i]).isDef())
205 Flags |= MachineMemOperand::MOStore;
207 Flags |= MachineMemOperand::MOLoad;
209 // Ask the target to do the actual folding.
210 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
211 if (!NewMI) return 0;
213 assert((!(Flags & MachineMemOperand::MOStore) ||
214 NewMI->getDesc().mayStore()) &&
215 "Folded a def to a non-store!");
216 assert((!(Flags & MachineMemOperand::MOLoad) ||
217 NewMI->getDesc().mayLoad()) &&
218 "Folded a use to a non-load!");
219 const MachineFrameInfo &MFI = *MF.getFrameInfo();
220 assert(MFI.getObjectOffset(FrameIndex) != -1);
221 MachineMemOperand *MMO =
222 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIndex),
224 MFI.getObjectSize(FrameIndex),
225 MFI.getObjectAlignment(FrameIndex));
226 NewMI->addMemOperand(MF, MMO);
231 /// foldMemoryOperand - Same as the previous version except it allows folding
232 /// of any load and store from / to any address, not just from a specific
235 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
237 const SmallVectorImpl<unsigned> &Ops,
238 MachineInstr* LoadMI) const {
239 assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
241 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
242 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
245 // Ask the target to do the actual folding.
246 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
247 if (!NewMI) return 0;
249 // Copy the memoperands from the load to the folded instruction.
250 NewMI->setMemRefs(LoadMI->memoperands_begin(),
251 LoadMI->memoperands_end());
256 bool TargetInstrInfo::
257 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
258 AliasAnalysis *AA) const {
259 const MachineFunction &MF = *MI->getParent()->getParent();
260 const MachineRegisterInfo &MRI = MF.getRegInfo();
261 const TargetMachine &TM = MF.getTarget();
262 const TargetInstrInfo &TII = *TM.getInstrInfo();
263 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
265 // A load from a fixed stack slot can be rematerialized. This may be
266 // redundant with subsequent checks, but it's target-independent,
267 // simple, and a common case.
269 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
270 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
273 const TargetInstrDesc &TID = MI->getDesc();
275 // Avoid instructions obviously unsafe for remat.
276 if (TID.hasUnmodeledSideEffects() || TID.isNotDuplicable() ||
280 // Avoid instructions which load from potentially varying memory.
281 if (TID.mayLoad() && !MI->isInvariantLoad(AA))
284 // If any of the registers accessed are non-constant, conservatively assume
285 // the instruction is not rematerializable.
286 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
287 const MachineOperand &MO = MI->getOperand(i);
288 if (!MO.isReg()) continue;
289 unsigned Reg = MO.getReg();
293 // Check for a well-behaved physical register.
294 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
296 // If the physreg has no defs anywhere, it's just an ambient register
297 // and we can freely move its uses. Alternatively, if it's allocatable,
298 // it could get allocated to something with a def during allocation.
299 if (!MRI.def_empty(Reg))
301 BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
302 if (AllocatableRegs.test(Reg))
304 // Check for a def among the register's aliases too.
305 for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
306 unsigned AliasReg = *Alias;
307 if (!MRI.def_empty(AliasReg))
309 if (AllocatableRegs.test(AliasReg))
313 // A physreg def. We can't remat it.
319 // Only allow one virtual-register def, and that in the first operand.
320 if (MO.isDef() != (i == 0))
323 // For the def, it should be the only def of that register.
324 if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() ||
328 // Don't allow any virtual-register uses. Rematting an instruction with
329 // virtual register uses would length the live ranges of the uses, which
330 // is not necessarily a good idea, certainly not "trivial".
335 // Everything checked out.
339 /// isSchedulingBoundary - Test if the given instruction should be
340 /// considered a scheduling boundary. This primarily includes labels
342 bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI,
343 const MachineBasicBlock *MBB,
344 const MachineFunction &MF) const{
345 // Terminators and labels can't be scheduled around.
346 if (MI->getDesc().isTerminator() || MI->isLabel())
349 // Don't attempt to schedule around any instruction that defines
350 // a stack-oriented pointer, as it's unlikely to be profitable. This
351 // saves compile time, because it doesn't require every single
352 // stack slot reference to depend on the instruction that does the
354 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
355 if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore()))
361 // Default implementation of CreateTargetPostRAHazardRecognizer.
362 ScheduleHazardRecognizer *TargetInstrInfoImpl::
363 CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const {
364 return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II);