1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/CalcSpillWeights.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
34 AllowSplit("spiller-splits-edges",
35 cl::desc("Allow critical edge splitting during spilling"));
37 STATISTIC(NumFinished, "Number of splits finished");
38 STATISTIC(NumSimple, "Number of splits that were simple");
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
44 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
45 const LiveIntervals &lis,
46 const MachineLoopInfo &mli)
47 : MF(vrm.getMachineFunction()),
51 TII(*MF.getTarget().getInstrInfo()),
54 void SplitAnalysis::clear() {
62 bool SplitAnalysis::canAnalyzeBranch(const MachineBasicBlock *MBB) {
63 MachineBasicBlock *T, *F;
64 SmallVector<MachineOperand, 4> Cond;
65 return !TII.AnalyzeBranch(const_cast<MachineBasicBlock&>(*MBB), T, F, Cond);
68 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
69 void SplitAnalysis::analyzeUses() {
70 const MachineRegisterInfo &MRI = MF.getRegInfo();
71 for (MachineRegisterInfo::reg_iterator I = MRI.reg_begin(CurLI->reg),
72 E = MRI.reg_end(); I != E; ++I) {
73 MachineOperand &MO = I.getOperand();
74 if (MO.isUse() && MO.isUndef())
76 MachineInstr *MI = MO.getParent();
77 if (MI->isDebugValue() || !UsingInstrs.insert(MI))
79 UseSlots.push_back(LIS.getInstructionIndex(MI).getDefIndex());
80 MachineBasicBlock *MBB = MI->getParent();
83 array_pod_sort(UseSlots.begin(), UseSlots.end());
85 DEBUG(dbgs() << " counted "
86 << UsingInstrs.size() << " instrs, "
87 << UsingBlocks.size() << " blocks.\n");
90 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
91 /// where CurLI is live.
92 void SplitAnalysis::calcLiveBlockInfo() {
96 LiveInterval::const_iterator LVI = CurLI->begin();
97 LiveInterval::const_iterator LVE = CurLI->end();
99 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
100 UseI = UseSlots.begin();
101 UseE = UseSlots.end();
103 // Loop over basic blocks where CurLI is live.
104 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
108 tie(BI.Start, BI.Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
110 // The last split point is the latest possible insertion point that dominates
111 // all successor blocks. If interference reaches LastSplitPoint, it is not
112 // possible to insert a split or reload that makes CurLI live in the
114 MachineBasicBlock::iterator LSP = LIS.getLastSplitPoint(*CurLI, BI.MBB);
115 if (LSP == BI.MBB->end())
116 BI.LastSplitPoint = BI.Stop;
118 BI.LastSplitPoint = LIS.getInstructionIndex(LSP);
120 // LVI is the first live segment overlapping MBB.
121 BI.LiveIn = LVI->start <= BI.Start;
125 // Find the first and last uses in the block.
126 BI.Uses = hasUses(MFI);
127 if (BI.Uses && UseI != UseE) {
129 assert(BI.FirstUse >= BI.Start);
131 while (UseI != UseE && *UseI < BI.Stop);
132 BI.LastUse = UseI[-1];
133 assert(BI.LastUse < BI.Stop);
136 // Look for gaps in the live range.
139 while (LVI->end < BI.Stop) {
140 SlotIndex LastStop = LVI->end;
141 if (++LVI == LVE || LVI->start >= BI.Stop) {
146 if (LastStop < LVI->start) {
153 // Don't set LiveThrough when the block has a gap.
154 BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
155 LiveBlocks.push_back(BI);
157 // LVI is now at LVE or LVI->end >= Stop.
161 // Live segment ends exactly at Stop. Move to the next segment.
162 if (LVI->end == BI.Stop && ++LVI == LVE)
165 // Pick the next basic block.
166 if (LVI->start < BI.Stop)
169 MFI = LIS.getMBBFromIndex(LVI->start);
173 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
174 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
175 const LiveInterval &Orig = LIS.getInterval(OrigReg);
176 assert(!Orig.empty() && "Splitting empty interval?");
177 LiveInterval::const_iterator I = Orig.find(Idx);
179 // Range containing Idx should begin at Idx.
180 if (I != Orig.end() && I->start <= Idx)
181 return I->start == Idx;
183 // Range does not contain Idx, previous must end at Idx.
184 return I != Orig.begin() && (--I)->end == Idx;
187 void SplitAnalysis::print(const BlockPtrSet &B, raw_ostream &OS) const {
188 for (BlockPtrSet::const_iterator I = B.begin(), E = B.end(); I != E; ++I) {
189 unsigned count = UsingBlocks.lookup(*I);
190 OS << " BB#" << (*I)->getNumber();
192 OS << '(' << count << ')';
196 void SplitAnalysis::analyze(const LiveInterval *li) {
203 //===----------------------------------------------------------------------===//
205 //===----------------------------------------------------------------------===//
207 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
208 SplitEditor::SplitEditor(SplitAnalysis &sa,
211 MachineDominatorTree &mdt)
212 : SA(sa), LIS(lis), VRM(vrm),
213 MRI(vrm.getMachineFunction().getRegInfo()),
215 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
216 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
222 void SplitEditor::reset(LiveRangeEdit &lre) {
228 // We don't need to clear LiveOutCache, only LiveOutSeen entries are read.
231 // We don't need an AliasAnalysis since we will only be performing
232 // cheap-as-a-copy remats anyway.
233 Edit->anyRematerializable(LIS, TII, 0);
236 void SplitEditor::dump() const {
237 if (RegAssign.empty()) {
238 dbgs() << " empty\n";
242 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
243 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
247 VNInfo *SplitEditor::defValue(unsigned RegIdx,
248 const VNInfo *ParentVNI,
250 assert(ParentVNI && "Mapping NULL value");
251 assert(Idx.isValid() && "Invalid SlotIndex");
252 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
253 LiveInterval *LI = Edit->get(RegIdx);
255 // Create a new value.
256 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
258 // Preserve the PHIDef bit.
259 if (ParentVNI->isPHIDef() && Idx == ParentVNI->def)
260 VNI->setIsPHIDef(true);
262 // Use insert for lookup, so we can add missing values with a second lookup.
263 std::pair<ValueMap::iterator, bool> InsP =
264 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
266 // This was the first time (RegIdx, ParentVNI) was mapped.
267 // Keep it as a simple def without any liveness.
271 // If the previous value was a simple mapping, add liveness for it now.
272 if (VNInfo *OldVNI = InsP.first->second) {
273 SlotIndex Def = OldVNI->def;
274 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
275 // No longer a simple mapping.
276 InsP.first->second = 0;
279 // This is a complex mapping, add liveness for VNI
280 SlotIndex Def = VNI->def;
281 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
286 void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
287 assert(ParentVNI && "Mapping NULL value");
288 VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
290 // ParentVNI was either unmapped or already complex mapped. Either way.
294 // This was previously a single mapping. Make sure the old def is represented
295 // by a trivial live range.
296 SlotIndex Def = VNI->def;
297 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
301 // extendRange - Extend the live range to reach Idx.
302 // Potentially create phi-def values.
303 void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
304 assert(Idx.isValid() && "Invalid SlotIndex");
305 MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
306 assert(IdxMBB && "No MBB at Idx");
307 LiveInterval *LI = Edit->get(RegIdx);
309 // Is there a def in the same MBB we can extend?
310 if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
313 // Now for the fun part. We know that ParentVNI potentially has multiple defs,
314 // and we may need to create even more phi-defs to preserve VNInfo SSA form.
315 // Perform a search for all predecessor blocks where we know the dominating
316 // VNInfo. Insert phi-def VNInfos along the path back to IdxMBB.
318 // Initialize the live-out cache the first time it is needed.
319 if (LiveOutSeen.empty()) {
320 unsigned N = VRM.getMachineFunction().getNumBlockIDs();
321 LiveOutSeen.resize(N);
322 LiveOutCache.resize(N);
325 // Blocks where LI should be live-in.
326 SmallVector<MachineDomTreeNode*, 16> LiveIn;
327 LiveIn.push_back(MDT[IdxMBB]);
329 // Remember if we have seen more than one value.
330 bool UniqueVNI = true;
333 // Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
334 for (unsigned i = 0; i != LiveIn.size(); ++i) {
335 MachineBasicBlock *MBB = LiveIn[i]->getBlock();
336 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
337 PE = MBB->pred_end(); PI != PE; ++PI) {
338 MachineBasicBlock *Pred = *PI;
339 LiveOutPair &LOP = LiveOutCache[Pred];
341 // Is this a known live-out block?
342 if (LiveOutSeen.test(Pred->getNumber())) {
343 if (VNInfo *VNI = LOP.first) {
344 if (IdxVNI && IdxVNI != VNI)
351 // First time. LOP is garbage and must be cleared below.
352 LiveOutSeen.set(Pred->getNumber());
354 // Does Pred provide a live-out value?
355 SlotIndex Start, Last;
356 tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
357 Last = Last.getPrevSlot();
358 VNInfo *VNI = LI->extendInBlock(Start, Last);
361 LOP.second = MDT[LIS.getMBBFromIndex(VNI->def)];
362 if (IdxVNI && IdxVNI != VNI)
369 // No, we need a live-in value for Pred as well
371 LiveIn.push_back(MDT[Pred]);
373 UniqueVNI = false; // Loopback to IdxMBB, ask updateSSA() for help.
377 // We may need to add phi-def values to preserve the SSA form.
379 LiveOutPair LOP(IdxVNI, MDT[LIS.getMBBFromIndex(IdxVNI->def)]);
380 // Update LiveOutCache, but skip IdxMBB at LiveIn[0].
381 for (unsigned i = 1, e = LiveIn.size(); i != e; ++i)
382 LiveOutCache[LiveIn[i]->getBlock()] = LOP;
384 IdxVNI = updateSSA(RegIdx, LiveIn, Idx, IdxMBB);
386 // Since we went through the trouble of a full BFS visiting all reaching defs,
387 // the values in LiveIn are now accurate. No more phi-defs are needed
388 // for these blocks, so we can color the live ranges.
389 for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
390 MachineBasicBlock *MBB = LiveIn[i]->getBlock();
391 SlotIndex Start = LIS.getMBBStartIdx(MBB);
392 VNInfo *VNI = LiveOutCache[MBB].first;
394 // Anything in LiveIn other than IdxMBB is live-through.
395 // In IdxMBB, we should stop at Idx unless the same value is live-out.
396 if (MBB == IdxMBB && IdxVNI != VNI)
397 LI->addRange(LiveRange(Start, Idx.getNextSlot(), IdxVNI));
399 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
403 VNInfo *SplitEditor::updateSSA(unsigned RegIdx,
404 SmallVectorImpl<MachineDomTreeNode*> &LiveIn,
406 const MachineBasicBlock *IdxMBB) {
407 // This is essentially the same iterative algorithm that SSAUpdater uses,
408 // except we already have a dominator tree, so we don't have to recompute it.
409 LiveInterval *LI = Edit->get(RegIdx);
414 // Propagate live-out values down the dominator tree, inserting phi-defs
415 // when necessary. Since LiveIn was created by a BFS, going backwards makes
416 // it more likely for us to visit immediate dominators before their
418 for (unsigned i = LiveIn.size(); i; --i) {
419 MachineDomTreeNode *Node = LiveIn[i-1];
420 MachineBasicBlock *MBB = Node->getBlock();
421 MachineDomTreeNode *IDom = Node->getIDom();
422 LiveOutPair IDomValue;
424 // We need a live-in value to a block with no immediate dominator?
425 // This is probably an unreachable block that has survived somehow.
426 bool needPHI = !IDom || !LiveOutSeen.test(IDom->getBlock()->getNumber());
428 // IDom dominates all of our predecessors, but it may not be the immediate
429 // dominator. Check if any of them have live-out values that are properly
430 // dominated by IDom. If so, we need a phi-def here.
432 IDomValue = LiveOutCache[IDom->getBlock()];
433 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
434 PE = MBB->pred_end(); PI != PE; ++PI) {
435 LiveOutPair Value = LiveOutCache[*PI];
436 if (!Value.first || Value.first == IDomValue.first)
438 // This predecessor is carrying something other than IDomValue.
439 // It could be because IDomValue hasn't propagated yet, or it could be
440 // because MBB is in the dominance frontier of that value.
441 if (MDT.dominates(IDom, Value.second)) {
448 // Create a phi-def if required.
451 SlotIndex Start = LIS.getMBBStartIdx(MBB);
452 VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
453 VNI->setIsPHIDef(true);
454 // We no longer need LI to be live-in.
455 LiveIn.erase(LiveIn.begin()+(i-1));
456 // Blocks in LiveIn are either IdxMBB, or have a value live-through.
459 // Check if we need to update live-out info.
460 LiveOutPair &LOP = LiveOutCache[MBB];
461 if (LOP.second == Node || !LiveOutSeen.test(MBB->getNumber())) {
462 // We already have a live-out defined in MBB, so this must be IdxMBB.
463 assert(MBB == IdxMBB && "Adding phi-def to known live-out");
464 LI->addRange(LiveRange(Start, Idx.getNextSlot(), VNI));
466 // This phi-def is also live-out, so color the whole block.
467 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
468 LOP = LiveOutPair(VNI, Node);
470 } else if (IDomValue.first) {
471 // No phi-def here. Remember incoming value for IdxMBB.
473 IdxVNI = IDomValue.first;
474 // IdxMBB need not be live-out.
475 if (!LiveOutSeen.test(MBB->getNumber()))
478 assert(LiveOutSeen.test(MBB->getNumber()) && "Expected live-out block");
479 // Propagate IDomValue if needed:
480 // MBB is live-out and doesn't define its own value.
481 LiveOutPair &LOP = LiveOutCache[MBB];
482 if (LOP.second != Node && LOP.first != IDomValue.first) {
490 assert(IdxVNI && "Didn't find value for Idx");
494 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
497 MachineBasicBlock &MBB,
498 MachineBasicBlock::iterator I) {
499 MachineInstr *CopyMI = 0;
501 LiveInterval *LI = Edit->get(RegIdx);
503 // Attempt cheap-as-a-copy rematerialization.
504 LiveRangeEdit::Remat RM(ParentVNI);
505 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
506 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
508 // Can't remat, just insert a copy from parent.
509 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
510 .addReg(Edit->getReg());
511 Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
514 // Define the value in Reg.
515 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
516 VNI->setCopy(CopyMI);
520 /// Create a new virtual register and live interval.
521 void SplitEditor::openIntv() {
522 assert(!OpenIdx && "Previous LI not closed before openIntv");
524 // Create the complement as index 0.
526 Edit->create(MRI, LIS, VRM);
528 // Create the open interval.
529 OpenIdx = Edit->size();
530 Edit->create(MRI, LIS, VRM);
533 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
534 assert(OpenIdx && "openIntv not called before enterIntvBefore");
535 DEBUG(dbgs() << " enterIntvBefore " << Idx);
536 Idx = Idx.getBaseIndex();
537 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
539 DEBUG(dbgs() << ": not live\n");
542 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
543 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
544 assert(MI && "enterIntvBefore called with invalid index");
546 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
550 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
551 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
552 SlotIndex End = LIS.getMBBEndIdx(&MBB);
553 SlotIndex Last = End.getPrevSlot();
554 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
555 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
557 DEBUG(dbgs() << ": not live\n");
560 DEBUG(dbgs() << ": valno " << ParentVNI->id);
561 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
562 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
563 RegAssign.insert(VNI->def, End, OpenIdx);
568 /// useIntv - indicate that all instructions in MBB should use OpenLI.
569 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
570 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
573 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
574 assert(OpenIdx && "openIntv not called before useIntv");
575 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
576 RegAssign.insert(Start, End, OpenIdx);
580 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
581 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
582 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
584 // The interval must be live beyond the instruction at Idx.
585 Idx = Idx.getBoundaryIndex();
586 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
588 DEBUG(dbgs() << ": not live\n");
589 return Idx.getNextSlot();
591 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
593 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
594 assert(MI && "No instruction at index");
595 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
596 llvm::next(MachineBasicBlock::iterator(MI)));
600 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
601 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
602 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
604 // The interval must be live into the instruction at Idx.
605 Idx = Idx.getBoundaryIndex();
606 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
608 DEBUG(dbgs() << ": not live\n");
609 return Idx.getNextSlot();
611 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
613 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
614 assert(MI && "No instruction at index");
615 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
619 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
620 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
621 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
622 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
624 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
626 DEBUG(dbgs() << ": not live\n");
630 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
631 MBB.SkipPHIsAndLabels(MBB.begin()));
632 RegAssign.insert(Start, VNI->def, OpenIdx);
637 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
638 assert(OpenIdx && "openIntv not called before overlapIntv");
639 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
640 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
641 "Parent changes value in extended range");
642 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
643 "Range cannot span basic blocks");
645 // The complement interval will be extended as needed by extendRange().
646 markComplexMapped(0, ParentVNI);
647 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
648 RegAssign.insert(Start, End, OpenIdx);
652 /// closeIntv - Indicate that we are done editing the currently open
653 /// LiveInterval, and ranges can be trimmed.
654 void SplitEditor::closeIntv() {
655 assert(OpenIdx && "openIntv not called before closeIntv");
659 /// transferSimpleValues - Transfer all simply defined values to the new live
661 /// Values that were rematerialized or that have multiple defs are left alone.
662 bool SplitEditor::transferSimpleValues() {
663 bool Skipped = false;
664 RegAssignMap::const_iterator AssignI = RegAssign.begin();
665 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
666 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
667 DEBUG(dbgs() << " blit " << *ParentI << ':');
668 VNInfo *ParentVNI = ParentI->valno;
669 // RegAssign has holes where RegIdx 0 should be used.
670 SlotIndex Start = ParentI->start;
671 AssignI.advanceTo(Start);
674 SlotIndex End = ParentI->end;
675 if (!AssignI.valid()) {
677 } else if (AssignI.start() <= Start) {
678 RegIdx = AssignI.value();
679 if (AssignI.stop() < End) {
680 End = AssignI.stop();
685 End = std::min(End, AssignI.start());
687 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
688 if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
689 DEBUG(dbgs() << ':' << VNI->id);
690 Edit->get(RegIdx)->addRange(LiveRange(Start, End, VNI));
694 } while (Start != ParentI->end);
695 DEBUG(dbgs() << '\n');
700 void SplitEditor::extendPHIKillRanges() {
701 // Extend live ranges to be live-out for successor PHI values.
702 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
703 E = Edit->getParent().vni_end(); I != E; ++I) {
704 const VNInfo *PHIVNI = *I;
705 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
707 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
708 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
709 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
710 PE = MBB->pred_end(); PI != PE; ++PI) {
711 SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
712 // The predecessor may not have a live-out value. That is OK, like an
713 // undef PHI operand.
714 if (Edit->getParent().liveAt(End)) {
715 assert(RegAssign.lookup(End) == RegIdx &&
716 "Different register assignment in phi predecessor");
717 extendRange(RegIdx, End);
723 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
724 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
725 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
726 RE = MRI.reg_end(); RI != RE;) {
727 MachineOperand &MO = RI.getOperand();
728 MachineInstr *MI = MO.getParent();
730 // LiveDebugVariables should have handled all DBG_VALUE instructions.
731 if (MI->isDebugValue()) {
732 DEBUG(dbgs() << "Zapping " << *MI);
737 // <undef> operands don't really read the register, so just assign them to
739 if (MO.isUse() && MO.isUndef()) {
740 MO.setReg(Edit->get(0)->reg);
744 SlotIndex Idx = LIS.getInstructionIndex(MI);
745 Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
747 // Rewrite to the mapped register at Idx.
748 unsigned RegIdx = RegAssign.lookup(Idx);
749 MO.setReg(Edit->get(RegIdx)->reg);
750 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
751 << Idx << ':' << RegIdx << '\t' << *MI);
753 // Extend liveness to Idx.
755 extendRange(RegIdx, Idx);
759 /// rewriteSplit - Rewrite uses of Intvs[0] according to the ConEQ mapping.
760 void SplitEditor::rewriteComponents(const SmallVectorImpl<LiveInterval*> &Intvs,
761 const ConnectedVNInfoEqClasses &ConEq) {
762 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Intvs[0]->reg),
763 RE = MRI.reg_end(); RI != RE;) {
764 MachineOperand &MO = RI.getOperand();
765 MachineInstr *MI = MO.getParent();
767 if (MO.isUse() && MO.isUndef())
769 // DBG_VALUE instructions should have been eliminated earlier.
770 SlotIndex Idx = LIS.getInstructionIndex(MI);
771 Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
772 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
774 const VNInfo *VNI = Intvs[0]->getVNInfoAt(Idx);
775 assert(VNI && "Interval not live at use.");
776 MO.setReg(Intvs[ConEq.getEqClass(VNI)]->reg);
777 DEBUG(dbgs() << VNI->id << '\t' << *MI);
781 void SplitEditor::finish() {
782 assert(OpenIdx == 0 && "Previous LI not closed before rewrite");
785 // At this point, the live intervals in Edit contain VNInfos corresponding to
786 // the inserted copies.
788 // Add the original defs from the parent interval.
789 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
790 E = Edit->getParent().vni_end(); I != E; ++I) {
791 const VNInfo *ParentVNI = *I;
792 if (ParentVNI->isUnused())
794 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
795 defValue(RegIdx, ParentVNI, ParentVNI->def);
796 // Mark rematted values as complex everywhere to force liveness computation.
797 // The new live ranges may be truncated.
798 if (Edit->didRematerialize(ParentVNI))
799 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
800 markComplexMapped(i, ParentVNI);
804 // Every new interval must have a def by now, otherwise the split is bogus.
805 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
806 assert((*I)->hasAtLeastOneValue() && "Split interval has no value");
809 // Transfer the simply mapped values, check if any are complex.
810 bool Complex = transferSimpleValues();
812 extendPHIKillRanges();
816 // Rewrite virtual registers, possibly extending ranges.
817 rewriteAssigned(Complex);
819 // FIXME: Delete defs that were rematted everywhere.
821 // Get rid of unused values and set phi-kill flags.
822 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
823 (*I)->RenumberValues(LIS);
825 // Now check if any registers were separated into multiple components.
826 ConnectedVNInfoEqClasses ConEQ(LIS);
827 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
828 // Don't use iterators, they are invalidated by create() below.
829 LiveInterval *li = Edit->get(i);
830 unsigned NumComp = ConEQ.Classify(li);
833 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
834 SmallVector<LiveInterval*, 8> dups;
836 for (unsigned i = 1; i != NumComp; ++i)
837 dups.push_back(&Edit->create(MRI, LIS, VRM));
838 rewriteComponents(dups, ConEQ);
839 ConEQ.Distribute(&dups[0]);
842 // Calculate spill weight and allocation hints for new intervals.
843 VirtRegAuxInfo vrai(VRM.getMachineFunction(), LIS, SA.Loops);
844 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
845 LiveInterval &li = **I;
846 vrai.CalculateRegClass(li.reg);
847 vrai.CalculateWeightAndHint(li);
848 DEBUG(dbgs() << " new interval " << MRI.getRegClass(li.reg)->getName()
849 << ":" << li << '\n');
854 //===----------------------------------------------------------------------===//
855 // Single Block Splitting
856 //===----------------------------------------------------------------------===//
858 /// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
859 /// may be an advantage to split CurLI for the duration of the block.
860 bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
861 // If CurLI is local to one block, there is no point to splitting it.
862 if (LiveBlocks.size() <= 1)
864 // Add blocks with multiple uses.
865 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
866 const BlockInfo &BI = LiveBlocks[i];
869 unsigned Instrs = UsingBlocks.lookup(BI.MBB);
872 if (Instrs == 2 && BI.LiveIn && BI.LiveOut && !BI.LiveThrough)
874 Blocks.insert(BI.MBB);
876 return !Blocks.empty();
879 /// splitSingleBlocks - Split CurLI into a separate live interval inside each
880 /// basic block in Blocks.
881 void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
882 DEBUG(dbgs() << " splitSingleBlocks for " << Blocks.size() << " blocks.\n");
884 for (unsigned i = 0, e = SA.LiveBlocks.size(); i != e; ++i) {
885 const SplitAnalysis::BlockInfo &BI = SA.LiveBlocks[i];
886 if (!BI.Uses || !Blocks.count(BI.MBB))
890 SlotIndex SegStart = enterIntvBefore(BI.FirstUse);
891 if (!BI.LiveOut || BI.LastUse < BI.LastSplitPoint) {
892 useIntv(SegStart, leaveIntvAfter(BI.LastUse));
894 // The last use is after the last valid split point.
895 SlotIndex SegStop = leaveIntvBefore(BI.LastSplitPoint);
896 useIntv(SegStart, SegStop);
897 overlapIntv(SegStop, BI.LastUse);