1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
31 STATISTIC(NumFinished, "Number of splits finished");
32 STATISTIC(NumSimple, "Number of splits that were simple");
33 STATISTIC(NumCopies, "Number of copies inserted for splitting");
34 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
35 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
41 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
42 const LiveIntervals &lis,
43 const MachineLoopInfo &mli)
44 : MF(vrm.getMachineFunction()),
48 TII(*MF.getTarget().getInstrInfo()),
50 LastSplitPoint(MF.getNumBlockIDs()) {}
52 void SplitAnalysis::clear() {
55 ThroughBlocks.clear();
57 DidRepairRange = false;
60 SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
61 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
62 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
63 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
65 // Compute split points on the first call. The pair is independent of the
66 // current live interval.
67 if (!LSP.first.isValid()) {
68 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
69 if (FirstTerm == MBB->end())
70 LSP.first = LIS.getMBBEndIdx(MBB);
72 LSP.first = LIS.getInstructionIndex(FirstTerm);
74 // If there is a landing pad successor, also find the call instruction.
77 // There may not be a call instruction (?) in which case we ignore LPad.
78 LSP.second = LSP.first;
79 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
82 if (I->getDesc().isCall()) {
83 LSP.second = LIS.getInstructionIndex(I);
89 // If CurLI is live into a landing pad successor, move the last split point
90 // back to the call that may throw.
91 if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
97 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
98 void SplitAnalysis::analyzeUses() {
99 assert(UseSlots.empty() && "Call clear first");
101 // First get all the defs from the interval values. This provides the correct
102 // slots for early clobbers.
103 for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
104 E = CurLI->vni_end(); I != E; ++I)
105 if (!(*I)->isPHIDef() && !(*I)->isUnused())
106 UseSlots.push_back((*I)->def);
108 // Get use slots form the use-def chain.
109 const MachineRegisterInfo &MRI = MF.getRegInfo();
110 for (MachineRegisterInfo::use_nodbg_iterator
111 I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
113 if (!I.getOperand().isUndef())
114 UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
116 array_pod_sort(UseSlots.begin(), UseSlots.end());
118 // Remove duplicates, keeping the smaller slot for each instruction.
119 // That is what we want for early clobbers.
120 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
121 SlotIndex::isSameInstr),
124 // Compute per-live block info.
125 if (!calcLiveBlockInfo()) {
126 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
127 // I am looking at you, RegisterCoalescer!
128 DidRepairRange = true;
130 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
131 const_cast<LiveIntervals&>(LIS)
132 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
134 ThroughBlocks.clear();
135 bool fixed = calcLiveBlockInfo();
137 assert(fixed && "Couldn't fix broken live interval");
140 DEBUG(dbgs() << "Analyze counted "
141 << UseSlots.size() << " instrs in "
142 << UseBlocks.size() << " blocks, through "
143 << NumThroughBlocks << " blocks.\n");
146 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
147 /// where CurLI is live.
148 bool SplitAnalysis::calcLiveBlockInfo() {
149 ThroughBlocks.resize(MF.getNumBlockIDs());
150 NumThroughBlocks = NumGapBlocks = 0;
154 LiveInterval::const_iterator LVI = CurLI->begin();
155 LiveInterval::const_iterator LVE = CurLI->end();
157 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
158 UseI = UseSlots.begin();
159 UseE = UseSlots.end();
161 // Loop over basic blocks where CurLI is live.
162 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
166 SlotIndex Start, Stop;
167 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
169 // If the block contains no uses, the range must be live through. At one
170 // point, RegisterCoalescer could create dangling ranges that ended
172 if (UseI == UseE || *UseI >= Stop) {
174 ThroughBlocks.set(BI.MBB->getNumber());
175 // The range shouldn't end mid-block if there are no uses. This shouldn't
180 // This block has uses. Find the first and last uses in the block.
181 BI.FirstInstr = *UseI;
182 assert(BI.FirstInstr >= Start);
184 while (UseI != UseE && *UseI < Stop);
185 BI.LastInstr = UseI[-1];
186 assert(BI.LastInstr < Stop);
188 // LVI is the first live segment overlapping MBB.
189 BI.LiveIn = LVI->start <= Start;
191 // When not live in, the first use should be a def.
193 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
194 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
195 BI.FirstDef = BI.FirstInstr;
198 // Look for gaps in the live range.
200 while (LVI->end < Stop) {
201 SlotIndex LastStop = LVI->end;
202 if (++LVI == LVE || LVI->start >= Stop) {
204 BI.LastInstr = LastStop;
208 if (LastStop < LVI->start) {
209 // There is a gap in the live range. Create duplicate entries for the
210 // live-in snippet and the live-out snippet.
213 // Push the Live-in part.
215 UseBlocks.push_back(BI);
216 UseBlocks.back().LastInstr = LastStop;
218 // Set up BI for the live-out part.
221 BI.FirstInstr = BI.FirstDef = LVI->start;
224 // A LiveRange that starts in the middle of the block must be a def.
225 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
227 BI.FirstDef = LVI->start;
230 UseBlocks.push_back(BI);
232 // LVI is now at LVE or LVI->end >= Stop.
237 // Live segment ends exactly at Stop. Move to the next segment.
238 if (LVI->end == Stop && ++LVI == LVE)
241 // Pick the next basic block.
242 if (LVI->start < Stop)
245 MFI = LIS.getMBBFromIndex(LVI->start);
248 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
252 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
255 LiveInterval *li = const_cast<LiveInterval*>(cli);
256 LiveInterval::iterator LVI = li->begin();
257 LiveInterval::iterator LVE = li->end();
260 // Loop over basic blocks where li is live.
261 MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
262 SlotIndex Stop = LIS.getMBBEndIdx(MFI);
265 LVI = li->advanceTo(LVI, Stop);
270 Stop = LIS.getMBBEndIdx(MFI);
271 } while (Stop <= LVI->start);
275 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
276 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
277 const LiveInterval &Orig = LIS.getInterval(OrigReg);
278 assert(!Orig.empty() && "Splitting empty interval?");
279 LiveInterval::const_iterator I = Orig.find(Idx);
281 // Range containing Idx should begin at Idx.
282 if (I != Orig.end() && I->start <= Idx)
283 return I->start == Idx;
285 // Range does not contain Idx, previous must end at Idx.
286 return I != Orig.begin() && (--I)->end == Idx;
289 void SplitAnalysis::analyze(const LiveInterval *li) {
296 //===----------------------------------------------------------------------===//
298 //===----------------------------------------------------------------------===//
300 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
301 SplitEditor::SplitEditor(SplitAnalysis &sa,
304 MachineDominatorTree &mdt)
305 : SA(sa), LIS(lis), VRM(vrm),
306 MRI(vrm.getMachineFunction().getRegInfo()),
308 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
309 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
312 SpillMode(SM_Partition),
316 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
323 // Reset the LiveRangeCalc instances needed for this spill mode.
324 LRCalc[0].reset(&VRM.getMachineFunction());
326 LRCalc[1].reset(&VRM.getMachineFunction());
328 // We don't need an AliasAnalysis since we will only be performing
329 // cheap-as-a-copy remats anyway.
330 Edit->anyRematerializable(LIS, TII, 0);
333 void SplitEditor::dump() const {
334 if (RegAssign.empty()) {
335 dbgs() << " empty\n";
339 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
340 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
344 VNInfo *SplitEditor::defValue(unsigned RegIdx,
345 const VNInfo *ParentVNI,
347 assert(ParentVNI && "Mapping NULL value");
348 assert(Idx.isValid() && "Invalid SlotIndex");
349 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
350 LiveInterval *LI = Edit->get(RegIdx);
352 // Create a new value.
353 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
355 // Use insert for lookup, so we can add missing values with a second lookup.
356 std::pair<ValueMap::iterator, bool> InsP =
357 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
359 // This was the first time (RegIdx, ParentVNI) was mapped.
360 // Keep it as a simple def without any liveness.
364 // If the previous value was a simple mapping, add liveness for it now.
365 if (VNInfo *OldVNI = InsP.first->second) {
366 SlotIndex Def = OldVNI->def;
367 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
368 // No longer a simple mapping.
369 InsP.first->second = 0;
372 // This is a complex mapping, add liveness for VNI
373 SlotIndex Def = VNI->def;
374 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
379 void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
380 assert(ParentVNI && "Mapping NULL value");
381 VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
383 // ParentVNI was either unmapped or already complex mapped. Either way.
387 // This was previously a single mapping. Make sure the old def is represented
388 // by a trivial live range.
389 SlotIndex Def = VNI->def;
390 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
394 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
397 MachineBasicBlock &MBB,
398 MachineBasicBlock::iterator I) {
399 MachineInstr *CopyMI = 0;
401 LiveInterval *LI = Edit->get(RegIdx);
403 // We may be trying to avoid interference that ends at a deleted instruction,
404 // so always begin RegIdx 0 early and all others late.
405 bool Late = RegIdx != 0;
407 // Attempt cheap-as-a-copy rematerialization.
408 LiveRangeEdit::Remat RM(ParentVNI);
409 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
410 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
413 // Can't remat, just insert a copy from parent.
414 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
415 .addReg(Edit->getReg());
416 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
421 // Define the value in Reg.
422 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
423 VNI->setCopy(CopyMI);
427 /// Create a new virtual register and live interval.
428 unsigned SplitEditor::openIntv() {
429 // Create the complement as index 0.
431 Edit->create(LIS, VRM);
433 // Create the open interval.
434 OpenIdx = Edit->size();
435 Edit->create(LIS, VRM);
439 void SplitEditor::selectIntv(unsigned Idx) {
440 assert(Idx != 0 && "Cannot select the complement interval");
441 assert(Idx < Edit->size() && "Can only select previously opened interval");
442 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
446 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
447 assert(OpenIdx && "openIntv not called before enterIntvBefore");
448 DEBUG(dbgs() << " enterIntvBefore " << Idx);
449 Idx = Idx.getBaseIndex();
450 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
452 DEBUG(dbgs() << ": not live\n");
455 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
456 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
457 assert(MI && "enterIntvBefore called with invalid index");
459 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
463 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
464 assert(OpenIdx && "openIntv not called before enterIntvAfter");
465 DEBUG(dbgs() << " enterIntvAfter " << Idx);
466 Idx = Idx.getBoundaryIndex();
467 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
469 DEBUG(dbgs() << ": not live\n");
472 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
473 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
474 assert(MI && "enterIntvAfter called with invalid index");
476 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
477 llvm::next(MachineBasicBlock::iterator(MI)));
481 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
482 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
483 SlotIndex End = LIS.getMBBEndIdx(&MBB);
484 SlotIndex Last = End.getPrevSlot();
485 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
486 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
488 DEBUG(dbgs() << ": not live\n");
491 DEBUG(dbgs() << ": valno " << ParentVNI->id);
492 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
493 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
494 RegAssign.insert(VNI->def, End, OpenIdx);
499 /// useIntv - indicate that all instructions in MBB should use OpenLI.
500 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
501 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
504 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
505 assert(OpenIdx && "openIntv not called before useIntv");
506 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
507 RegAssign.insert(Start, End, OpenIdx);
511 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
512 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
513 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
515 // The interval must be live beyond the instruction at Idx.
516 Idx = Idx.getBoundaryIndex();
517 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
519 DEBUG(dbgs() << ": not live\n");
520 return Idx.getNextSlot();
522 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
524 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
525 assert(MI && "No instruction at index");
526 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
527 llvm::next(MachineBasicBlock::iterator(MI)));
531 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
532 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
533 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
535 // The interval must be live into the instruction at Idx.
536 Idx = Idx.getBaseIndex();
537 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
539 DEBUG(dbgs() << ": not live\n");
540 return Idx.getNextSlot();
542 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
544 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
545 assert(MI && "No instruction at index");
546 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
550 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
551 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
552 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
553 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
555 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
557 DEBUG(dbgs() << ": not live\n");
561 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
562 MBB.SkipPHIsAndLabels(MBB.begin()));
563 RegAssign.insert(Start, VNI->def, OpenIdx);
568 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
569 assert(OpenIdx && "openIntv not called before overlapIntv");
570 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
571 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
572 "Parent changes value in extended range");
573 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
574 "Range cannot span basic blocks");
576 // The complement interval will be extended as needed by LRCalc.extend().
578 markComplexMapped(0, ParentVNI);
579 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
580 RegAssign.insert(Start, End, OpenIdx);
584 /// transferValues - Transfer all possible values to the new live ranges.
585 /// Values that were rematerialized are left alone, they need LRCalc.extend().
586 bool SplitEditor::transferValues() {
587 bool Skipped = false;
588 RegAssignMap::const_iterator AssignI = RegAssign.begin();
589 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
590 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
591 DEBUG(dbgs() << " blit " << *ParentI << ':');
592 VNInfo *ParentVNI = ParentI->valno;
593 // RegAssign has holes where RegIdx 0 should be used.
594 SlotIndex Start = ParentI->start;
595 AssignI.advanceTo(Start);
598 SlotIndex End = ParentI->end;
599 if (!AssignI.valid()) {
601 } else if (AssignI.start() <= Start) {
602 RegIdx = AssignI.value();
603 if (AssignI.stop() < End) {
604 End = AssignI.stop();
609 End = std::min(End, AssignI.start());
612 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
613 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
614 LiveInterval *LI = Edit->get(RegIdx);
616 // Check for a simply defined value that can be blitted directly.
617 if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
618 DEBUG(dbgs() << ':' << VNI->id);
619 LI->addRange(LiveRange(Start, End, VNI));
624 // Skip rematerialized values, we need to use LRCalc.extend() and
625 // extendPHIKillRanges() to completely recompute the live ranges.
626 if (Edit->didRematerialize(ParentVNI)) {
627 DEBUG(dbgs() << "(remat)");
633 LiveRangeCalc &LRC = getLRCalc(RegIdx);
635 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
636 // so the live range is accurate. Add live-in blocks in [Start;End) to the
638 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
639 SlotIndex BlockStart, BlockEnd;
640 tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
642 // The first block may be live-in, or it may have its own def.
643 if (Start != BlockStart) {
644 VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
645 assert(VNI && "Missing def for complex mapped value");
646 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
647 // MBB has its own def. Is it also live-out?
649 LRC.setLiveOutValue(MBB, VNI);
651 // Skip to the next block for live-in.
653 BlockStart = BlockEnd;
656 // Handle the live-in blocks covered by [Start;End).
657 assert(Start <= BlockStart && "Expected live-in block");
658 while (BlockStart < End) {
659 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
660 BlockEnd = LIS.getMBBEndIdx(MBB);
661 if (BlockStart == ParentVNI->def) {
662 // This block has the def of a parent PHI, so it isn't live-in.
663 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
664 VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
665 assert(VNI && "Missing def for complex mapped parent PHI");
667 LRC.setLiveOutValue(MBB, VNI); // Live-out as well.
669 // This block needs a live-in value. The last block covered may not
672 LRC.addLiveInBlock(LI, MDT[MBB], End);
674 // Live-through, and we don't know the value.
675 LRC.addLiveInBlock(LI, MDT[MBB]);
676 LRC.setLiveOutValue(MBB, 0);
679 BlockStart = BlockEnd;
683 } while (Start != ParentI->end);
684 DEBUG(dbgs() << '\n');
687 LRCalc[0].calculateValues(LIS.getSlotIndexes(), &MDT,
688 &LIS.getVNInfoAllocator());
690 LRCalc[1].calculateValues(LIS.getSlotIndexes(), &MDT,
691 &LIS.getVNInfoAllocator());
696 void SplitEditor::extendPHIKillRanges() {
697 // Extend live ranges to be live-out for successor PHI values.
698 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
699 E = Edit->getParent().vni_end(); I != E; ++I) {
700 const VNInfo *PHIVNI = *I;
701 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
703 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
704 LiveInterval *LI = Edit->get(RegIdx);
705 LiveRangeCalc &LRC = getLRCalc(RegIdx);
706 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
707 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
708 PE = MBB->pred_end(); PI != PE; ++PI) {
709 SlotIndex End = LIS.getMBBEndIdx(*PI);
710 SlotIndex LastUse = End.getPrevSlot();
711 // The predecessor may not have a live-out value. That is OK, like an
712 // undef PHI operand.
713 if (Edit->getParent().liveAt(LastUse)) {
714 assert(RegAssign.lookup(LastUse) == RegIdx &&
715 "Different register assignment in phi predecessor");
717 LIS.getSlotIndexes(), &MDT, &LIS.getVNInfoAllocator());
723 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
724 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
725 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
726 RE = MRI.reg_end(); RI != RE;) {
727 MachineOperand &MO = RI.getOperand();
728 MachineInstr *MI = MO.getParent();
730 // LiveDebugVariables should have handled all DBG_VALUE instructions.
731 if (MI->isDebugValue()) {
732 DEBUG(dbgs() << "Zapping " << *MI);
737 // <undef> operands don't really read the register, so it doesn't matter
738 // which register we choose. When the use operand is tied to a def, we must
739 // use the same register as the def, so just do that always.
740 SlotIndex Idx = LIS.getInstructionIndex(MI);
741 if (MO.isDef() || MO.isUndef())
742 Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
744 // Rewrite to the mapped register at Idx.
745 unsigned RegIdx = RegAssign.lookup(Idx);
746 LiveInterval *LI = Edit->get(RegIdx);
748 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
749 << Idx << ':' << RegIdx << '\t' << *MI);
751 // Extend liveness to Idx if the instruction reads reg.
752 if (!ExtendRanges || MO.isUndef())
755 // Skip instructions that don't read Reg.
757 if (!MO.getSubReg() && !MO.isEarlyClobber())
759 // We may wan't to extend a live range for a partial redef, or for a use
760 // tied to an early clobber.
761 Idx = Idx.getPrevSlot();
762 if (!Edit->getParent().liveAt(Idx))
765 Idx = Idx.getUseIndex();
767 getLRCalc(RegIdx).extend(LI, Idx.getNextSlot(), LIS.getSlotIndexes(),
768 &MDT, &LIS.getVNInfoAllocator());
772 void SplitEditor::deleteRematVictims() {
773 SmallVector<MachineInstr*, 8> Dead;
774 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
775 LiveInterval *LI = *I;
776 for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
778 // Dead defs end at the store slot.
779 if (LII->end != LII->valno->def.getNextSlot())
781 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
782 assert(MI && "Missing instruction for dead def");
783 MI->addRegisterDead(LI->reg, &TRI);
785 if (!MI->allDefsAreDead())
788 DEBUG(dbgs() << "All defs dead: " << *MI);
796 Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
799 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
802 // At this point, the live intervals in Edit contain VNInfos corresponding to
803 // the inserted copies.
805 // Add the original defs from the parent interval.
806 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
807 E = Edit->getParent().vni_end(); I != E; ++I) {
808 const VNInfo *ParentVNI = *I;
809 if (ParentVNI->isUnused())
811 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
812 VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
813 VNI->setIsPHIDef(ParentVNI->isPHIDef());
814 VNI->setCopy(ParentVNI->getCopy());
816 // Mark rematted values as complex everywhere to force liveness computation.
817 // The new live ranges may be truncated.
818 if (Edit->didRematerialize(ParentVNI))
819 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
820 markComplexMapped(i, ParentVNI);
823 // Transfer the simply mapped values, check if any are skipped.
824 bool Skipped = transferValues();
826 extendPHIKillRanges();
830 // Rewrite virtual registers, possibly extending ranges.
831 rewriteAssigned(Skipped);
833 // Delete defs that were rematted everywhere.
835 deleteRematVictims();
837 // Get rid of unused values and set phi-kill flags.
838 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
839 (*I)->RenumberValues(LIS);
841 // Provide a reverse mapping from original indices to Edit ranges.
844 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
848 // Now check if any registers were separated into multiple components.
849 ConnectedVNInfoEqClasses ConEQ(LIS);
850 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
851 // Don't use iterators, they are invalidated by create() below.
852 LiveInterval *li = Edit->get(i);
853 unsigned NumComp = ConEQ.Classify(li);
856 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
857 SmallVector<LiveInterval*, 8> dups;
859 for (unsigned j = 1; j != NumComp; ++j)
860 dups.push_back(&Edit->create(LIS, VRM));
861 ConEQ.Distribute(&dups[0], MRI);
862 // The new intervals all map back to i.
864 LRMap->resize(Edit->size(), i);
867 // Calculate spill weight and allocation hints for new intervals.
868 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
870 assert(!LRMap || LRMap->size() == Edit->size());
874 //===----------------------------------------------------------------------===//
875 // Single Block Splitting
876 //===----------------------------------------------------------------------===//
878 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
879 bool SingleInstrs) const {
880 // Always split for multiple instructions.
881 if (!BI.isOneInstr())
883 // Don't split for single instructions unless explicitly requested.
886 // Splitting a live-through range always makes progress.
887 if (BI.LiveIn && BI.LiveOut)
889 // No point in isolating a copy. It has no register class constraints.
890 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
892 // Finally, don't isolate an end point that was created by earlier splits.
893 return isOriginalEndpoint(BI.FirstInstr);
896 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
898 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
899 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
901 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
902 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
904 // The last use is after the last valid split point.
905 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
906 useIntv(SegStart, SegStop);
907 overlapIntv(SegStop, BI.LastInstr);
912 //===----------------------------------------------------------------------===//
913 // Global Live Range Splitting Support
914 //===----------------------------------------------------------------------===//
916 // These methods support a method of global live range splitting that uses a
917 // global algorithm to decide intervals for CFG edges. They will insert split
918 // points and color intervals in basic blocks while avoiding interference.
920 // Note that splitSingleBlock is also useful for blocks where both CFG edges
923 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
924 unsigned IntvIn, SlotIndex LeaveBefore,
925 unsigned IntvOut, SlotIndex EnterAfter){
926 SlotIndex Start, Stop;
927 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
929 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
930 << ") intf " << LeaveBefore << '-' << EnterAfter
931 << ", live-through " << IntvIn << " -> " << IntvOut);
933 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
935 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
936 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
937 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
939 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
942 DEBUG(dbgs() << ", spill on entry.\n");
944 // <<<<<<<<< Possible LeaveBefore interference.
945 // |-----------| Live through.
946 // -____________ Spill on entry.
949 SlotIndex Idx = leaveIntvAtTop(*MBB);
950 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
956 DEBUG(dbgs() << ", reload on exit.\n");
958 // >>>>>>> Possible EnterAfter interference.
959 // |-----------| Live through.
960 // ___________-- Reload on exit.
963 SlotIndex Idx = enterIntvAtEnd(*MBB);
964 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
969 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
970 DEBUG(dbgs() << ", straight through.\n");
972 // |-----------| Live through.
973 // ------------- Straight through, same intv, no interference.
976 useIntv(Start, Stop);
980 // We cannot legally insert splits after LSP.
981 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
982 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
984 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
985 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
986 DEBUG(dbgs() << ", switch avoiding interference.\n");
988 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
989 // |-----------| Live through.
990 // ------======= Switch intervals between interference.
994 if (LeaveBefore && LeaveBefore < LSP) {
995 Idx = enterIntvBefore(LeaveBefore);
998 Idx = enterIntvAtEnd(*MBB);
1001 useIntv(Start, Idx);
1002 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1003 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1007 DEBUG(dbgs() << ", create local intv for interference.\n");
1009 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1010 // |-----------| Live through.
1011 // ==---------== Switch intervals before/after interference.
1013 assert(LeaveBefore <= EnterAfter && "Missed case");
1015 selectIntv(IntvOut);
1016 SlotIndex Idx = enterIntvAfter(EnterAfter);
1018 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1021 Idx = leaveIntvBefore(LeaveBefore);
1022 useIntv(Start, Idx);
1023 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1027 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1028 unsigned IntvIn, SlotIndex LeaveBefore) {
1029 SlotIndex Start, Stop;
1030 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1032 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1033 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1034 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1035 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1037 assert(IntvIn && "Must have register in");
1038 assert(BI.LiveIn && "Must be live-in");
1039 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1041 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1042 DEBUG(dbgs() << " before interference.\n");
1044 // <<< Interference after kill.
1045 // |---o---x | Killed in block.
1046 // ========= Use IntvIn everywhere.
1049 useIntv(Start, BI.LastInstr);
1053 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1055 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1057 // <<< Possible interference after last use.
1058 // |---o---o---| Live-out on stack.
1059 // =========____ Leave IntvIn after last use.
1061 // < Interference after last use.
1062 // |---o---o--o| Live-out on stack, late last use.
1063 // ============ Copy to stack after LSP, overlap IntvIn.
1064 // \_____ Stack interval is live-out.
1066 if (BI.LastInstr < LSP) {
1067 DEBUG(dbgs() << ", spill after last use before interference.\n");
1069 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1070 useIntv(Start, Idx);
1071 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1073 DEBUG(dbgs() << ", spill before last split point.\n");
1075 SlotIndex Idx = leaveIntvBefore(LSP);
1076 overlapIntv(Idx, BI.LastInstr);
1077 useIntv(Start, Idx);
1078 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1083 // The interference is overlapping somewhere we wanted to use IntvIn. That
1084 // means we need to create a local interval that can be allocated a
1085 // different register.
1086 unsigned LocalIntv = openIntv();
1088 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1090 if (!BI.LiveOut || BI.LastInstr < LSP) {
1092 // <<<<<<< Interference overlapping uses.
1093 // |---o---o---| Live-out on stack.
1094 // =====----____ Leave IntvIn before interference, then spill.
1096 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1097 SlotIndex From = enterIntvBefore(LeaveBefore);
1100 useIntv(Start, From);
1101 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1105 // <<<<<<< Interference overlapping uses.
1106 // |---o---o--o| Live-out on stack, late last use.
1107 // =====------- Copy to stack before LSP, overlap LocalIntv.
1108 // \_____ Stack interval is live-out.
1110 SlotIndex To = leaveIntvBefore(LSP);
1111 overlapIntv(To, BI.LastInstr);
1112 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1115 useIntv(Start, From);
1116 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1119 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1120 unsigned IntvOut, SlotIndex EnterAfter) {
1121 SlotIndex Start, Stop;
1122 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1124 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1125 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1126 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1127 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1129 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1131 assert(IntvOut && "Must have register out");
1132 assert(BI.LiveOut && "Must be live-out");
1133 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1135 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1136 DEBUG(dbgs() << " after interference.\n");
1138 // >>>> Interference before def.
1139 // | o---o---| Defined in block.
1140 // ========= Use IntvOut everywhere.
1142 selectIntv(IntvOut);
1143 useIntv(BI.FirstInstr, Stop);
1147 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1148 DEBUG(dbgs() << ", reload after interference.\n");
1150 // >>>> Interference before def.
1151 // |---o---o---| Live-through, stack-in.
1152 // ____========= Enter IntvOut before first use.
1154 selectIntv(IntvOut);
1155 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1157 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1161 // The interference is overlapping somewhere we wanted to use IntvOut. That
1162 // means we need to create a local interval that can be allocated a
1163 // different register.
1164 DEBUG(dbgs() << ", interference overlaps uses.\n");
1166 // >>>>>>> Interference overlapping uses.
1167 // |---o---o---| Live-through, stack-in.
1168 // ____---====== Create local interval for interference range.
1170 selectIntv(IntvOut);
1171 SlotIndex Idx = enterIntvAfter(EnterAfter);
1173 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1176 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));