1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
31 STATISTIC(NumFinished, "Number of splits finished");
32 STATISTIC(NumSimple, "Number of splits that were simple");
33 STATISTIC(NumCopies, "Number of copies inserted for splitting");
34 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
35 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
41 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
42 const LiveIntervals &lis,
43 const MachineLoopInfo &mli)
44 : MF(vrm.getMachineFunction()),
48 TII(*MF.getTarget().getInstrInfo()),
50 LastSplitPoint(MF.getNumBlockIDs()) {}
52 void SplitAnalysis::clear() {
55 ThroughBlocks.clear();
57 DidRepairRange = false;
60 SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
61 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
62 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
63 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
65 // Compute split points on the first call. The pair is independent of the
66 // current live interval.
67 if (!LSP.first.isValid()) {
68 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
69 if (FirstTerm == MBB->end())
70 LSP.first = LIS.getMBBEndIdx(MBB);
72 LSP.first = LIS.getInstructionIndex(FirstTerm);
74 // If there is a landing pad successor, also find the call instruction.
77 // There may not be a call instruction (?) in which case we ignore LPad.
78 LSP.second = LSP.first;
79 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
82 if (I->getDesc().isCall()) {
83 LSP.second = LIS.getInstructionIndex(I);
89 // If CurLI is live into a landing pad successor, move the last split point
90 // back to the call that may throw.
91 if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
97 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
98 void SplitAnalysis::analyzeUses() {
99 assert(UseSlots.empty() && "Call clear first");
101 // First get all the defs from the interval values. This provides the correct
102 // slots for early clobbers.
103 for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
104 E = CurLI->vni_end(); I != E; ++I)
105 if (!(*I)->isPHIDef() && !(*I)->isUnused())
106 UseSlots.push_back((*I)->def);
108 // Get use slots form the use-def chain.
109 const MachineRegisterInfo &MRI = MF.getRegInfo();
110 for (MachineRegisterInfo::use_nodbg_iterator
111 I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
113 if (!I.getOperand().isUndef())
114 UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
116 array_pod_sort(UseSlots.begin(), UseSlots.end());
118 // Remove duplicates, keeping the smaller slot for each instruction.
119 // That is what we want for early clobbers.
120 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
121 SlotIndex::isSameInstr),
124 // Compute per-live block info.
125 if (!calcLiveBlockInfo()) {
126 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
127 // I am looking at you, RegisterCoalescer!
128 DidRepairRange = true;
130 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
131 const_cast<LiveIntervals&>(LIS)
132 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
134 ThroughBlocks.clear();
135 bool fixed = calcLiveBlockInfo();
137 assert(fixed && "Couldn't fix broken live interval");
140 DEBUG(dbgs() << "Analyze counted "
141 << UseSlots.size() << " instrs in "
142 << UseBlocks.size() << " blocks, through "
143 << NumThroughBlocks << " blocks.\n");
146 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
147 /// where CurLI is live.
148 bool SplitAnalysis::calcLiveBlockInfo() {
149 ThroughBlocks.resize(MF.getNumBlockIDs());
150 NumThroughBlocks = NumGapBlocks = 0;
154 LiveInterval::const_iterator LVI = CurLI->begin();
155 LiveInterval::const_iterator LVE = CurLI->end();
157 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
158 UseI = UseSlots.begin();
159 UseE = UseSlots.end();
161 // Loop over basic blocks where CurLI is live.
162 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
166 SlotIndex Start, Stop;
167 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
169 // If the block contains no uses, the range must be live through. At one
170 // point, RegisterCoalescer could create dangling ranges that ended
172 if (UseI == UseE || *UseI >= Stop) {
174 ThroughBlocks.set(BI.MBB->getNumber());
175 // The range shouldn't end mid-block if there are no uses. This shouldn't
180 // This block has uses. Find the first and last uses in the block.
181 BI.FirstInstr = *UseI;
182 assert(BI.FirstInstr >= Start);
184 while (UseI != UseE && *UseI < Stop);
185 BI.LastInstr = UseI[-1];
186 assert(BI.LastInstr < Stop);
188 // LVI is the first live segment overlapping MBB.
189 BI.LiveIn = LVI->start <= Start;
191 // When not live in, the first use should be a def.
193 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
194 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
195 BI.FirstDef = BI.FirstInstr;
198 // Look for gaps in the live range.
200 while (LVI->end < Stop) {
201 SlotIndex LastStop = LVI->end;
202 if (++LVI == LVE || LVI->start >= Stop) {
204 BI.LastInstr = LastStop;
208 if (LastStop < LVI->start) {
209 // There is a gap in the live range. Create duplicate entries for the
210 // live-in snippet and the live-out snippet.
213 // Push the Live-in part.
215 UseBlocks.push_back(BI);
216 UseBlocks.back().LastInstr = LastStop;
218 // Set up BI for the live-out part.
221 BI.FirstInstr = BI.FirstDef = LVI->start;
224 // A LiveRange that starts in the middle of the block must be a def.
225 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
227 BI.FirstDef = LVI->start;
230 UseBlocks.push_back(BI);
232 // LVI is now at LVE or LVI->end >= Stop.
237 // Live segment ends exactly at Stop. Move to the next segment.
238 if (LVI->end == Stop && ++LVI == LVE)
241 // Pick the next basic block.
242 if (LVI->start < Stop)
245 MFI = LIS.getMBBFromIndex(LVI->start);
248 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
252 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
255 LiveInterval *li = const_cast<LiveInterval*>(cli);
256 LiveInterval::iterator LVI = li->begin();
257 LiveInterval::iterator LVE = li->end();
260 // Loop over basic blocks where li is live.
261 MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
262 SlotIndex Stop = LIS.getMBBEndIdx(MFI);
265 LVI = li->advanceTo(LVI, Stop);
270 Stop = LIS.getMBBEndIdx(MFI);
271 } while (Stop <= LVI->start);
275 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
276 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
277 const LiveInterval &Orig = LIS.getInterval(OrigReg);
278 assert(!Orig.empty() && "Splitting empty interval?");
279 LiveInterval::const_iterator I = Orig.find(Idx);
281 // Range containing Idx should begin at Idx.
282 if (I != Orig.end() && I->start <= Idx)
283 return I->start == Idx;
285 // Range does not contain Idx, previous must end at Idx.
286 return I != Orig.begin() && (--I)->end == Idx;
289 void SplitAnalysis::analyze(const LiveInterval *li) {
296 //===----------------------------------------------------------------------===//
298 //===----------------------------------------------------------------------===//
300 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
301 SplitEditor::SplitEditor(SplitAnalysis &sa,
304 MachineDominatorTree &mdt)
305 : SA(sa), LIS(lis), VRM(vrm),
306 MRI(vrm.getMachineFunction().getRegInfo()),
308 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
309 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
312 SpillMode(SM_Partition),
316 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
323 // Reset the LiveRangeCalc instances needed for this spill mode.
324 LRCalc[0].reset(&VRM.getMachineFunction());
326 LRCalc[1].reset(&VRM.getMachineFunction());
328 // We don't need an AliasAnalysis since we will only be performing
329 // cheap-as-a-copy remats anyway.
330 Edit->anyRematerializable(LIS, TII, 0);
333 void SplitEditor::dump() const {
334 if (RegAssign.empty()) {
335 dbgs() << " empty\n";
339 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
340 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
344 VNInfo *SplitEditor::defValue(unsigned RegIdx,
345 const VNInfo *ParentVNI,
347 assert(ParentVNI && "Mapping NULL value");
348 assert(Idx.isValid() && "Invalid SlotIndex");
349 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
350 LiveInterval *LI = Edit->get(RegIdx);
352 // Create a new value.
353 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
355 // Use insert for lookup, so we can add missing values with a second lookup.
356 std::pair<ValueMap::iterator, bool> InsP =
357 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
358 ValueForcePair(VNI, false)));
360 // This was the first time (RegIdx, ParentVNI) was mapped.
361 // Keep it as a simple def without any liveness.
365 // If the previous value was a simple mapping, add liveness for it now.
366 if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
367 SlotIndex Def = OldVNI->def;
368 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
369 // No longer a simple mapping. Switch to a complex, non-forced mapping.
370 InsP.first->second = ValueForcePair();
373 // This is a complex mapping, add liveness for VNI
374 SlotIndex Def = VNI->def;
375 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
380 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
381 assert(ParentVNI && "Mapping NULL value");
382 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
383 VNInfo *VNI = VFP.getPointer();
385 // ParentVNI was either unmapped or already complex mapped. Either way, just
386 // set the force bit.
392 // This was previously a single mapping. Make sure the old def is represented
393 // by a trivial live range.
394 SlotIndex Def = VNI->def;
395 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
396 // Mark as complex mapped, forced.
397 VFP = ValueForcePair(0, true);
400 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
403 MachineBasicBlock &MBB,
404 MachineBasicBlock::iterator I) {
405 MachineInstr *CopyMI = 0;
407 LiveInterval *LI = Edit->get(RegIdx);
409 // We may be trying to avoid interference that ends at a deleted instruction,
410 // so always begin RegIdx 0 early and all others late.
411 bool Late = RegIdx != 0;
413 // Attempt cheap-as-a-copy rematerialization.
414 LiveRangeEdit::Remat RM(ParentVNI);
415 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
416 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
419 // Can't remat, just insert a copy from parent.
420 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
421 .addReg(Edit->getReg());
422 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
427 // Define the value in Reg.
428 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
429 VNI->setCopy(CopyMI);
433 /// Create a new virtual register and live interval.
434 unsigned SplitEditor::openIntv() {
435 // Create the complement as index 0.
437 Edit->create(LIS, VRM);
439 // Create the open interval.
440 OpenIdx = Edit->size();
441 Edit->create(LIS, VRM);
445 void SplitEditor::selectIntv(unsigned Idx) {
446 assert(Idx != 0 && "Cannot select the complement interval");
447 assert(Idx < Edit->size() && "Can only select previously opened interval");
448 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
452 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
453 assert(OpenIdx && "openIntv not called before enterIntvBefore");
454 DEBUG(dbgs() << " enterIntvBefore " << Idx);
455 Idx = Idx.getBaseIndex();
456 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
458 DEBUG(dbgs() << ": not live\n");
461 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
462 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
463 assert(MI && "enterIntvBefore called with invalid index");
465 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
469 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
470 assert(OpenIdx && "openIntv not called before enterIntvAfter");
471 DEBUG(dbgs() << " enterIntvAfter " << Idx);
472 Idx = Idx.getBoundaryIndex();
473 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
475 DEBUG(dbgs() << ": not live\n");
478 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
479 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
480 assert(MI && "enterIntvAfter called with invalid index");
482 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
483 llvm::next(MachineBasicBlock::iterator(MI)));
487 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
488 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
489 SlotIndex End = LIS.getMBBEndIdx(&MBB);
490 SlotIndex Last = End.getPrevSlot();
491 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
492 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
494 DEBUG(dbgs() << ": not live\n");
497 DEBUG(dbgs() << ": valno " << ParentVNI->id);
498 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
499 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
500 RegAssign.insert(VNI->def, End, OpenIdx);
505 /// useIntv - indicate that all instructions in MBB should use OpenLI.
506 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
507 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
510 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
511 assert(OpenIdx && "openIntv not called before useIntv");
512 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
513 RegAssign.insert(Start, End, OpenIdx);
517 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
518 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
519 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
521 // The interval must be live beyond the instruction at Idx.
522 Idx = Idx.getBoundaryIndex();
523 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
525 DEBUG(dbgs() << ": not live\n");
526 return Idx.getNextSlot();
528 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
530 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
531 assert(MI && "No instruction at index");
532 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
533 llvm::next(MachineBasicBlock::iterator(MI)));
537 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
538 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
539 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
541 // The interval must be live into the instruction at Idx.
542 Idx = Idx.getBaseIndex();
543 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
545 DEBUG(dbgs() << ": not live\n");
546 return Idx.getNextSlot();
548 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
550 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
551 assert(MI && "No instruction at index");
552 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
556 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
557 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
558 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
559 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
561 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
563 DEBUG(dbgs() << ": not live\n");
567 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
568 MBB.SkipPHIsAndLabels(MBB.begin()));
569 RegAssign.insert(Start, VNI->def, OpenIdx);
574 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
575 assert(OpenIdx && "openIntv not called before overlapIntv");
576 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
577 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
578 "Parent changes value in extended range");
579 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
580 "Range cannot span basic blocks");
582 // The complement interval will be extended as needed by LRCalc.extend().
584 forceRecompute(0, ParentVNI);
585 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
586 RegAssign.insert(Start, End, OpenIdx);
590 //===----------------------------------------------------------------------===//
592 //===----------------------------------------------------------------------===//
594 void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
595 LiveInterval *LI = Edit->get(0);
596 DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
597 RegAssignMap::iterator AssignI;
598 AssignI.setMap(RegAssign);
600 for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
601 VNInfo *VNI = Copies[i];
602 SlotIndex Def = VNI->def;
603 MachineInstr *MI = LIS.getInstructionFromIndex(Def);
604 assert(MI && "No instruction for back-copy");
606 MachineBasicBlock *MBB = MI->getParent();
607 MachineBasicBlock::iterator MBBI(MI);
609 do AtBegin = MBBI == MBB->begin();
610 while (!AtBegin && (--MBBI)->isDebugValue());
612 DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
613 LI->removeValNo(VNI);
614 LIS.RemoveMachineInstrFromMaps(MI);
615 MI->eraseFromParent();
617 // Adjust RegAssign if a register assignment is killed at VNI->def. We
618 // want to avoid calculating the live range of the source register if
620 AssignI.find(VNI->def.getPrevSlot());
621 if (!AssignI.valid() || AssignI.start() >= Def)
623 // If MI doesn't kill the assigned register, just leave it.
624 if (AssignI.stop() != Def)
626 unsigned RegIdx = AssignI.value();
627 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
628 DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
629 forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
631 SlotIndex Kill = LIS.getInstructionIndex(MBBI).getDefIndex();
632 DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
633 AssignI.setStop(Kill);
638 void SplitEditor::hoistCopiesForSize() {
639 // Get the complement interval, always RegIdx 0.
640 LiveInterval *LI = Edit->get(0);
641 LiveInterval *Parent = &Edit->getParent();
643 // Track the nearest common dominator for all back-copies for each ParentVNI,
644 // indexed by ParentVNI->id.
645 typedef std::pair<MachineBasicBlock*, SlotIndex> DomPair;
646 SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
648 // Find the nearest common dominator for parent values with multiple
649 // back-copies. If a single back-copy dominates, put it in DomPair.second.
650 for (LiveInterval::vni_iterator VI = LI->vni_begin(), VE = LI->vni_end();
653 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
654 assert(ParentVNI && "Parent not live at complement def");
656 // Don't hoist remats. The complement is probably going to disappear
657 // completely anyway.
658 if (Edit->didRematerialize(ParentVNI))
661 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(VNI->def);
662 DomPair &Dom = NearestDom[ParentVNI->id];
664 // Keep directly defined parent values. This is either a PHI or an
665 // instruction in the complement range. All other copies of ParentVNI
666 // should be eliminated.
667 if (VNI->def == ParentVNI->def) {
668 DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
669 Dom = DomPair(ValMBB, VNI->def);
672 // Skip the singly mapped values. There is nothing to gain from hoisting a
674 if (Values.lookup(std::make_pair(0, ParentVNI->id)).getPointer()) {
675 DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
680 // First time we see ParentVNI. VNI dominates itself.
681 Dom = DomPair(ValMBB, VNI->def);
682 } else if (Dom.first == ValMBB) {
683 // Two defs in the same block. Pick the earlier def.
684 if (!Dom.second.isValid() || VNI->def < Dom.second)
685 Dom.second = VNI->def;
687 // Different basic blocks. Check if one dominates.
688 MachineBasicBlock *Near =
689 MDT.findNearestCommonDominator(Dom.first, ValMBB);
691 // Def ValMBB dominates.
692 Dom = DomPair(ValMBB, VNI->def);
693 else if (Near != Dom.first)
694 // None dominate. Hoist to common dominator, need new def.
695 Dom = DomPair(Near, SlotIndex());
698 DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
699 << " for parent " << ParentVNI->id << '@' << ParentVNI->def
700 << " hoist to BB#" << Dom.first->getNumber() << ' '
701 << Dom.second << '\n');
704 // Insert the hoisted copies.
705 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
706 DomPair &Dom = NearestDom[i];
707 if (!Dom.first || Dom.second.isValid())
709 // This value needs a hoisted copy inserted at the end of Dom.second.
710 SlotIndex Last = LIS.getMBBEndIdx(Dom.first).getPrevSlot();
712 defFromParent(0, Parent->getValNumInfo(i), Last, *Dom.first,
713 LIS.getLastSplitPoint(Edit->getParent(), Dom.first))->def;
716 // Remove redundant back-copies that are now known to be dominated by another
717 // def with the same value.
718 SmallVector<VNInfo*, 8> BackCopies;
719 for (LiveInterval::vni_iterator VI = LI->vni_begin(), VE = LI->vni_end();
722 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
723 const DomPair &Dom = NearestDom[ParentVNI->id];
724 if (!Dom.first || Dom.second == VNI->def)
726 BackCopies.push_back(VNI);
727 forceRecompute(0, ParentVNI);
729 removeBackCopies(BackCopies);
733 /// transferValues - Transfer all possible values to the new live ranges.
734 /// Values that were rematerialized are left alone, they need LRCalc.extend().
735 bool SplitEditor::transferValues() {
736 bool Skipped = false;
737 RegAssignMap::const_iterator AssignI = RegAssign.begin();
738 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
739 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
740 DEBUG(dbgs() << " blit " << *ParentI << ':');
741 VNInfo *ParentVNI = ParentI->valno;
742 // RegAssign has holes where RegIdx 0 should be used.
743 SlotIndex Start = ParentI->start;
744 AssignI.advanceTo(Start);
747 SlotIndex End = ParentI->end;
748 if (!AssignI.valid()) {
750 } else if (AssignI.start() <= Start) {
751 RegIdx = AssignI.value();
752 if (AssignI.stop() < End) {
753 End = AssignI.stop();
758 End = std::min(End, AssignI.start());
761 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
762 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
763 LiveInterval *LI = Edit->get(RegIdx);
765 // Check for a simply defined value that can be blitted directly.
766 ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id));
767 if (VNInfo *VNI = VFP.getPointer()) {
768 DEBUG(dbgs() << ':' << VNI->id);
769 LI->addRange(LiveRange(Start, End, VNI));
774 // Skip values with forced recomputation.
776 DEBUG(dbgs() << "(recalc)");
782 LiveRangeCalc &LRC = getLRCalc(RegIdx);
784 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
785 // so the live range is accurate. Add live-in blocks in [Start;End) to the
787 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
788 SlotIndex BlockStart, BlockEnd;
789 tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
791 // The first block may be live-in, or it may have its own def.
792 if (Start != BlockStart) {
793 VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
794 assert(VNI && "Missing def for complex mapped value");
795 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
796 // MBB has its own def. Is it also live-out?
798 LRC.setLiveOutValue(MBB, VNI);
800 // Skip to the next block for live-in.
802 BlockStart = BlockEnd;
805 // Handle the live-in blocks covered by [Start;End).
806 assert(Start <= BlockStart && "Expected live-in block");
807 while (BlockStart < End) {
808 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
809 BlockEnd = LIS.getMBBEndIdx(MBB);
810 if (BlockStart == ParentVNI->def) {
811 // This block has the def of a parent PHI, so it isn't live-in.
812 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
813 VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
814 assert(VNI && "Missing def for complex mapped parent PHI");
816 LRC.setLiveOutValue(MBB, VNI); // Live-out as well.
818 // This block needs a live-in value. The last block covered may not
821 LRC.addLiveInBlock(LI, MDT[MBB], End);
823 // Live-through, and we don't know the value.
824 LRC.addLiveInBlock(LI, MDT[MBB]);
825 LRC.setLiveOutValue(MBB, 0);
828 BlockStart = BlockEnd;
832 } while (Start != ParentI->end);
833 DEBUG(dbgs() << '\n');
836 LRCalc[0].calculateValues(LIS.getSlotIndexes(), &MDT,
837 &LIS.getVNInfoAllocator());
839 LRCalc[1].calculateValues(LIS.getSlotIndexes(), &MDT,
840 &LIS.getVNInfoAllocator());
845 void SplitEditor::extendPHIKillRanges() {
846 // Extend live ranges to be live-out for successor PHI values.
847 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
848 E = Edit->getParent().vni_end(); I != E; ++I) {
849 const VNInfo *PHIVNI = *I;
850 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
852 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
853 LiveInterval *LI = Edit->get(RegIdx);
854 LiveRangeCalc &LRC = getLRCalc(RegIdx);
855 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
856 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
857 PE = MBB->pred_end(); PI != PE; ++PI) {
858 SlotIndex End = LIS.getMBBEndIdx(*PI);
859 SlotIndex LastUse = End.getPrevSlot();
860 // The predecessor may not have a live-out value. That is OK, like an
861 // undef PHI operand.
862 if (Edit->getParent().liveAt(LastUse)) {
863 assert(RegAssign.lookup(LastUse) == RegIdx &&
864 "Different register assignment in phi predecessor");
866 LIS.getSlotIndexes(), &MDT, &LIS.getVNInfoAllocator());
872 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
873 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
874 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
875 RE = MRI.reg_end(); RI != RE;) {
876 MachineOperand &MO = RI.getOperand();
877 MachineInstr *MI = MO.getParent();
879 // LiveDebugVariables should have handled all DBG_VALUE instructions.
880 if (MI->isDebugValue()) {
881 DEBUG(dbgs() << "Zapping " << *MI);
886 // <undef> operands don't really read the register, so it doesn't matter
887 // which register we choose. When the use operand is tied to a def, we must
888 // use the same register as the def, so just do that always.
889 SlotIndex Idx = LIS.getInstructionIndex(MI);
890 if (MO.isDef() || MO.isUndef())
891 Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
893 // Rewrite to the mapped register at Idx.
894 unsigned RegIdx = RegAssign.lookup(Idx);
895 LiveInterval *LI = Edit->get(RegIdx);
897 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
898 << Idx << ':' << RegIdx << '\t' << *MI);
900 // Extend liveness to Idx if the instruction reads reg.
901 if (!ExtendRanges || MO.isUndef())
904 // Skip instructions that don't read Reg.
906 if (!MO.getSubReg() && !MO.isEarlyClobber())
908 // We may wan't to extend a live range for a partial redef, or for a use
909 // tied to an early clobber.
910 Idx = Idx.getPrevSlot();
911 if (!Edit->getParent().liveAt(Idx))
914 Idx = Idx.getUseIndex();
916 getLRCalc(RegIdx).extend(LI, Idx.getNextSlot(), LIS.getSlotIndexes(),
917 &MDT, &LIS.getVNInfoAllocator());
921 void SplitEditor::deleteRematVictims() {
922 SmallVector<MachineInstr*, 8> Dead;
923 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
924 LiveInterval *LI = *I;
925 for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
927 // Dead defs end at the store slot.
928 if (LII->end != LII->valno->def.getNextSlot())
930 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
931 assert(MI && "Missing instruction for dead def");
932 MI->addRegisterDead(LI->reg, &TRI);
934 if (!MI->allDefsAreDead())
937 DEBUG(dbgs() << "All defs dead: " << *MI);
945 Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
948 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
951 // At this point, the live intervals in Edit contain VNInfos corresponding to
952 // the inserted copies.
954 // Add the original defs from the parent interval.
955 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
956 E = Edit->getParent().vni_end(); I != E; ++I) {
957 const VNInfo *ParentVNI = *I;
958 if (ParentVNI->isUnused())
960 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
961 VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
962 VNI->setIsPHIDef(ParentVNI->isPHIDef());
963 VNI->setCopy(ParentVNI->getCopy());
965 // Force rematted values to be recomputed everywhere.
966 // The new live ranges may be truncated.
967 if (Edit->didRematerialize(ParentVNI))
968 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
969 forceRecompute(i, ParentVNI);
972 // Hoist back-copies to the complement interval when in spill mode.
975 // Leave all back-copies as is.
978 hoistCopiesForSize();
981 llvm_unreachable("Spill mode 'speed' not implemented yet");
985 // Transfer the simply mapped values, check if any are skipped.
986 bool Skipped = transferValues();
988 extendPHIKillRanges();
992 // Rewrite virtual registers, possibly extending ranges.
993 rewriteAssigned(Skipped);
995 // Delete defs that were rematted everywhere.
997 deleteRematVictims();
999 // Get rid of unused values and set phi-kill flags.
1000 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
1001 (*I)->RenumberValues(LIS);
1003 // Provide a reverse mapping from original indices to Edit ranges.
1006 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1007 LRMap->push_back(i);
1010 // Now check if any registers were separated into multiple components.
1011 ConnectedVNInfoEqClasses ConEQ(LIS);
1012 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1013 // Don't use iterators, they are invalidated by create() below.
1014 LiveInterval *li = Edit->get(i);
1015 unsigned NumComp = ConEQ.Classify(li);
1018 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
1019 SmallVector<LiveInterval*, 8> dups;
1021 for (unsigned j = 1; j != NumComp; ++j)
1022 dups.push_back(&Edit->create(LIS, VRM));
1023 ConEQ.Distribute(&dups[0], MRI);
1024 // The new intervals all map back to i.
1026 LRMap->resize(Edit->size(), i);
1029 // Calculate spill weight and allocation hints for new intervals.
1030 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
1032 assert(!LRMap || LRMap->size() == Edit->size());
1036 //===----------------------------------------------------------------------===//
1037 // Single Block Splitting
1038 //===----------------------------------------------------------------------===//
1040 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
1041 bool SingleInstrs) const {
1042 // Always split for multiple instructions.
1043 if (!BI.isOneInstr())
1045 // Don't split for single instructions unless explicitly requested.
1048 // Splitting a live-through range always makes progress.
1049 if (BI.LiveIn && BI.LiveOut)
1051 // No point in isolating a copy. It has no register class constraints.
1052 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
1054 // Finally, don't isolate an end point that was created by earlier splits.
1055 return isOriginalEndpoint(BI.FirstInstr);
1058 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1060 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1061 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
1063 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1064 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
1066 // The last use is after the last valid split point.
1067 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1068 useIntv(SegStart, SegStop);
1069 overlapIntv(SegStop, BI.LastInstr);
1074 //===----------------------------------------------------------------------===//
1075 // Global Live Range Splitting Support
1076 //===----------------------------------------------------------------------===//
1078 // These methods support a method of global live range splitting that uses a
1079 // global algorithm to decide intervals for CFG edges. They will insert split
1080 // points and color intervals in basic blocks while avoiding interference.
1082 // Note that splitSingleBlock is also useful for blocks where both CFG edges
1083 // are on the stack.
1085 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1086 unsigned IntvIn, SlotIndex LeaveBefore,
1087 unsigned IntvOut, SlotIndex EnterAfter){
1088 SlotIndex Start, Stop;
1089 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1091 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1092 << ") intf " << LeaveBefore << '-' << EnterAfter
1093 << ", live-through " << IntvIn << " -> " << IntvOut);
1095 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1097 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1098 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1099 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1101 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1104 DEBUG(dbgs() << ", spill on entry.\n");
1106 // <<<<<<<<< Possible LeaveBefore interference.
1107 // |-----------| Live through.
1108 // -____________ Spill on entry.
1111 SlotIndex Idx = leaveIntvAtTop(*MBB);
1112 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1118 DEBUG(dbgs() << ", reload on exit.\n");
1120 // >>>>>>> Possible EnterAfter interference.
1121 // |-----------| Live through.
1122 // ___________-- Reload on exit.
1124 selectIntv(IntvOut);
1125 SlotIndex Idx = enterIntvAtEnd(*MBB);
1126 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1131 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1132 DEBUG(dbgs() << ", straight through.\n");
1134 // |-----------| Live through.
1135 // ------------- Straight through, same intv, no interference.
1137 selectIntv(IntvOut);
1138 useIntv(Start, Stop);
1142 // We cannot legally insert splits after LSP.
1143 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1144 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1146 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1147 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1148 DEBUG(dbgs() << ", switch avoiding interference.\n");
1150 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1151 // |-----------| Live through.
1152 // ------======= Switch intervals between interference.
1154 selectIntv(IntvOut);
1156 if (LeaveBefore && LeaveBefore < LSP) {
1157 Idx = enterIntvBefore(LeaveBefore);
1160 Idx = enterIntvAtEnd(*MBB);
1163 useIntv(Start, Idx);
1164 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1165 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1169 DEBUG(dbgs() << ", create local intv for interference.\n");
1171 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1172 // |-----------| Live through.
1173 // ==---------== Switch intervals before/after interference.
1175 assert(LeaveBefore <= EnterAfter && "Missed case");
1177 selectIntv(IntvOut);
1178 SlotIndex Idx = enterIntvAfter(EnterAfter);
1180 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1183 Idx = leaveIntvBefore(LeaveBefore);
1184 useIntv(Start, Idx);
1185 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1189 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1190 unsigned IntvIn, SlotIndex LeaveBefore) {
1191 SlotIndex Start, Stop;
1192 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1194 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1195 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1196 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1197 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1199 assert(IntvIn && "Must have register in");
1200 assert(BI.LiveIn && "Must be live-in");
1201 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1203 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1204 DEBUG(dbgs() << " before interference.\n");
1206 // <<< Interference after kill.
1207 // |---o---x | Killed in block.
1208 // ========= Use IntvIn everywhere.
1211 useIntv(Start, BI.LastInstr);
1215 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1217 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1219 // <<< Possible interference after last use.
1220 // |---o---o---| Live-out on stack.
1221 // =========____ Leave IntvIn after last use.
1223 // < Interference after last use.
1224 // |---o---o--o| Live-out on stack, late last use.
1225 // ============ Copy to stack after LSP, overlap IntvIn.
1226 // \_____ Stack interval is live-out.
1228 if (BI.LastInstr < LSP) {
1229 DEBUG(dbgs() << ", spill after last use before interference.\n");
1231 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1232 useIntv(Start, Idx);
1233 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1235 DEBUG(dbgs() << ", spill before last split point.\n");
1237 SlotIndex Idx = leaveIntvBefore(LSP);
1238 overlapIntv(Idx, BI.LastInstr);
1239 useIntv(Start, Idx);
1240 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1245 // The interference is overlapping somewhere we wanted to use IntvIn. That
1246 // means we need to create a local interval that can be allocated a
1247 // different register.
1248 unsigned LocalIntv = openIntv();
1250 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1252 if (!BI.LiveOut || BI.LastInstr < LSP) {
1254 // <<<<<<< Interference overlapping uses.
1255 // |---o---o---| Live-out on stack.
1256 // =====----____ Leave IntvIn before interference, then spill.
1258 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1259 SlotIndex From = enterIntvBefore(LeaveBefore);
1262 useIntv(Start, From);
1263 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1267 // <<<<<<< Interference overlapping uses.
1268 // |---o---o--o| Live-out on stack, late last use.
1269 // =====------- Copy to stack before LSP, overlap LocalIntv.
1270 // \_____ Stack interval is live-out.
1272 SlotIndex To = leaveIntvBefore(LSP);
1273 overlapIntv(To, BI.LastInstr);
1274 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1277 useIntv(Start, From);
1278 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1281 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1282 unsigned IntvOut, SlotIndex EnterAfter) {
1283 SlotIndex Start, Stop;
1284 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1286 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1287 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1288 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1289 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1291 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1293 assert(IntvOut && "Must have register out");
1294 assert(BI.LiveOut && "Must be live-out");
1295 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1297 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1298 DEBUG(dbgs() << " after interference.\n");
1300 // >>>> Interference before def.
1301 // | o---o---| Defined in block.
1302 // ========= Use IntvOut everywhere.
1304 selectIntv(IntvOut);
1305 useIntv(BI.FirstInstr, Stop);
1309 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1310 DEBUG(dbgs() << ", reload after interference.\n");
1312 // >>>> Interference before def.
1313 // |---o---o---| Live-through, stack-in.
1314 // ____========= Enter IntvOut before first use.
1316 selectIntv(IntvOut);
1317 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1319 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1323 // The interference is overlapping somewhere we wanted to use IntvOut. That
1324 // means we need to create a local interval that can be allocated a
1325 // different register.
1326 DEBUG(dbgs() << ", interference overlaps uses.\n");
1328 // >>>>>>> Interference overlapping uses.
1329 // |---o---o---| Live-through, stack-in.
1330 // ____---====== Create local interval for interference range.
1332 selectIntv(IntvOut);
1333 SlotIndex Idx = enterIntvAfter(EnterAfter);
1335 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1338 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));