1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/RegisterCoalescer.h"
20 #include "llvm/ADT/BitVector.h"
24 class SimpleRegisterCoalescing;
26 class TargetRegisterInfo;
27 class TargetInstrInfo;
29 class MachineLoopInfo;
31 /// CopyRec - Representation for copy instructions in coalescer queue.
37 CopyRec(MachineInstr *mi, unsigned depth, bool be)
38 : MI(mi), LoopDepth(depth), isBackEdge(be) {};
41 template<class SF> class JoinPriorityQueue;
43 /// CopyRecSort - Sorting function for coalescer queue.
45 struct CopyRecSort : public std::binary_function<CopyRec,CopyRec,bool> {
46 JoinPriorityQueue<CopyRecSort> *JPQ;
47 explicit CopyRecSort(JoinPriorityQueue<CopyRecSort> *jpq) : JPQ(jpq) {}
48 CopyRecSort(const CopyRecSort &RHS) : JPQ(RHS.JPQ) {}
49 bool operator()(CopyRec left, CopyRec right) const;
52 /// JoinQueue - A priority queue of copy instructions the coalescer is
55 class JoinPriorityQueue {
56 SimpleRegisterCoalescing *Rc;
57 std::priority_queue<CopyRec, std::vector<CopyRec>, SF> Queue;
60 explicit JoinPriorityQueue(SimpleRegisterCoalescing *rc)
61 : Rc(rc), Queue(SF(this)) {}
63 bool empty() const { return Queue.empty(); }
64 void push(CopyRec R) { Queue.push(R); }
66 if (empty()) return CopyRec(0, 0, false);
67 CopyRec R = Queue.top();
72 // Callbacks to SimpleRegisterCoalescing.
73 unsigned getRepIntervalSize(unsigned Reg);
76 class SimpleRegisterCoalescing : public MachineFunctionPass,
77 public RegisterCoalescer {
79 MachineRegisterInfo* mri_;
80 const TargetMachine* tm_;
81 const TargetRegisterInfo* tri_;
82 const TargetInstrInfo* tii_;
84 const MachineLoopInfo* loopInfo;
86 BitVector allocatableRegs_;
87 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
89 /// JoinQueue - A priority queue of copy instructions the coalescer is
91 JoinPriorityQueue<CopyRecSort> *JoinQueue;
93 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
95 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
97 /// ReMatCopies - Keep track of copies eliminated due to remat.
99 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
101 /// ReMatDefs - Keep track of definition instructions which have
103 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
106 static char ID; // Pass identifcation, replacement for typeid
107 SimpleRegisterCoalescing() : MachineFunctionPass(&ID) {}
119 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
120 virtual void releaseMemory();
122 /// runOnMachineFunction - pass entry point
123 virtual bool runOnMachineFunction(MachineFunction&);
125 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
126 // This runs as an independent pass, so don't do anything.
130 /// getRepIntervalSize - Called from join priority queue sorting function.
131 /// It returns the size of the interval that represent the given register.
132 unsigned getRepIntervalSize(unsigned Reg) {
133 if (!li_->hasInterval(Reg))
135 return li_->getApproximateInstructionCount(li_->getInterval(Reg)) *
136 LiveIntervals::InstrSlots::NUM;
139 /// print - Implement the dump method.
140 virtual void print(std::ostream &O, const Module* = 0) const;
141 void print(std::ostream *O, const Module* M = 0) const {
146 /// joinIntervals - join compatible live intervals
147 void joinIntervals();
149 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
150 /// copies that cannot yet be coalesced into the "TryAgain" list.
151 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
152 std::vector<CopyRec> &TryAgain);
154 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
155 /// which are the src/dst of the copy instruction CopyMI. This returns true
156 /// if the copy was successfully coalesced away. If it is not currently
157 /// possible to coalesce this interval, but it may be possible if other
158 /// things get coalesced, then it returns true by reference in 'Again'.
159 bool JoinCopy(CopyRec &TheCopy, bool &Again);
161 /// JoinIntervals - Attempt to join these two intervals. On failure, this
162 /// returns false. Otherwise, if one of the intervals being joined is a
163 /// physreg, this method always canonicalizes DestInt to be it. The output
164 /// "SrcInt" will not have been modified, so we can use this information
165 /// below to update aliases.
166 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped);
168 /// SimpleJoin - Attempt to join the specified interval into this one. The
169 /// caller of this method must guarantee that the RHS only contains a single
170 /// value number and that the RHS is not defined by a copy from this
171 /// interval. This returns false if the intervals are not joinable, or it
172 /// joins them and returns true.
173 bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
175 /// Return true if the two specified registers belong to different register
176 /// classes. The registers may be either phys or virt regs. In the
177 /// case where both registers are virtual registers, it would also returns
178 /// true by reference the RegB register class in SubRC if it is a subset of
179 /// RegA's register class.
180 bool differingRegisterClasses(unsigned RegA, unsigned RegB,
181 const TargetRegisterClass *&SubRC) const;
184 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
185 /// the source value number is defined by a copy from the destination reg
186 /// see if we can merge these two destination reg valno# into a single
187 /// value number, eliminating a copy.
188 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
189 MachineInstr *CopyMI);
191 /// HasOtherReachingDefs - Return true if there are definitions of IntB
192 /// other than BValNo val# that can reach uses of AValno val# of IntA.
193 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
194 VNInfo *AValNo, VNInfo *BValNo);
196 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
197 /// If the source value number is defined by a commutable instruction and
198 /// its other operand is coalesced to the copy dest register, see if we
199 /// can transform the copy into a noop by commuting the definition.
200 bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
201 MachineInstr *CopyMI);
203 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
204 MachineInstr *CopyMI);
206 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
207 /// turn the copy into an implicit def.
208 bool TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
209 MachineBasicBlock *MBB,
210 unsigned DstReg, unsigned SrcReg);
212 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
213 /// from an implicit def to another register can be coalesced away.
214 bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
215 LiveInterval &li, LiveInterval &ImpLi) const;
217 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
218 /// def and it is being removed. Turn all copies from this value# into
219 /// identity copies so they will be removed.
220 void RemoveCopiesFromValNo(LiveInterval &li, VNInfo *VNI);
222 /// isProfitableToCoalesceToSubRC - Given that register class of DstReg is
223 /// a subset of the register class of SrcReg, return true if it's profitable
224 /// to coalesce the two registers.
225 bool isProfitableToCoalesceToSubRC(unsigned SrcReg, unsigned DstReg,
226 MachineBasicBlock *MBB);
228 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
229 /// register with a physical register, check if any of the virtual register
230 /// operand is a sub-register use or def. If so, make sure it won't result
231 /// in an illegal extract_subreg or insert_subreg instruction.
232 bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
233 unsigned VirtReg, unsigned PhysReg);
235 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
236 /// the specified live interval is defined by a copy from the specified
238 bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR,
241 /// isBackEdgeCopy - Return true if CopyMI is a back edge copy.
243 bool isBackEdgeCopy(MachineInstr *CopyMI, unsigned DstReg) const;
245 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
246 /// update the subregister number if it is not zero. If DstReg is a
247 /// physical register and the existing subregister number of the def / use
248 /// being updated is not zero, make sure to set it to the correct physical
250 void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
252 /// RemoveDeadImpDef - Remove implicit_def instructions which are
253 /// "re-defining" registers due to insert_subreg coalescing. e.g.
254 void RemoveDeadImpDef(unsigned Reg, LiveInterval &LI);
256 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
257 /// due to live range lengthening as the result of coalescing.
258 void RemoveUnnecessaryKills(unsigned Reg, LiveInterval &LI);
260 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
261 /// Return true if live interval is removed.
262 bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
264 /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
265 /// extended by a dead copy. Mark the last use (if any) of the val# as kill
266 /// as ends the live range there. If there isn't another use, then this
267 /// live range is dead. Return true if live interval is removed.
268 bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
270 /// RemoveDeadDef - If a def of a live interval is now determined dead,
271 /// remove the val# it defines. If the live interval becomes empty, remove
273 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
275 /// lastRegisterUse - Returns the last use of the specific register between
276 /// cycles Start and End or NULL if there are no uses.
277 MachineOperand *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
278 unsigned &LastUseIdx) const;
280 void printRegName(unsigned reg) const;
283 } // End llvm namespace