1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numJoins , "Number of interval joins performed");
40 STATISTIC(numCrossRCs , "Number of cross class joins performed");
41 STATISTIC(numCommutes , "Number of instruction commuting performed");
42 STATISTIC(numExtends , "Number of copies extended");
43 STATISTIC(NumReMats , "Number of instructions re-materialized");
44 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
45 STATISTIC(numAborts , "Number of times interval joining aborted");
46 STATISTIC(numDeadValNo, "Number of valno def marked dead");
48 char SimpleRegisterCoalescing::ID = 0;
50 EnableJoining("join-liveintervals",
51 cl::desc("Coalesce copies (default=true)"),
55 NewHeuristic("new-coalescer-heuristic",
56 cl::desc("Use new coalescer heuristic"),
57 cl::init(false), cl::Hidden);
60 CrossClassJoin("join-cross-class-copies",
61 cl::desc("Coalesce cross register class copies"),
62 cl::init(false), cl::Hidden);
65 PhysJoinTweak("tweak-phys-join-heuristics",
66 cl::desc("Tweak heuristics for joining phys reg with vr"),
67 cl::init(false), cl::Hidden);
69 static RegisterPass<SimpleRegisterCoalescing>
70 X("simple-register-coalescing", "Simple Register Coalescing");
72 // Declare that we implement the RegisterCoalescer interface
73 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
75 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
77 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
78 AU.addRequired<LiveIntervals>();
79 AU.addPreserved<LiveIntervals>();
80 AU.addRequired<MachineLoopInfo>();
81 AU.addPreserved<MachineLoopInfo>();
82 AU.addPreservedID(MachineDominatorsID);
84 AU.addPreservedID(StrongPHIEliminationID);
86 AU.addPreservedID(PHIEliminationID);
87 AU.addPreservedID(TwoAddressInstructionPassID);
88 MachineFunctionPass::getAnalysisUsage(AU);
91 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
92 /// being the source and IntB being the dest, thus this defines a value number
93 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
94 /// see if we can merge these two pieces of B into a single value number,
95 /// eliminating a copy. For example:
99 /// B1 = A3 <- this copy
101 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
102 /// value number to be replaced with B0 (which simplifies the B liveinterval).
104 /// This returns true if an interval was modified.
106 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
108 MachineInstr *CopyMI) {
109 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
111 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
112 // the example above.
113 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
114 assert(BLR != IntB.end() && "Live range not found!");
115 VNInfo *BValNo = BLR->valno;
117 // Get the location that B is defined at. Two options: either this value has
118 // an unknown definition point or it is defined at CopyIdx. If unknown, we
120 if (!BValNo->copy) return false;
121 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
123 // AValNo is the value number in A that defines the copy, A3 in the example.
124 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
125 assert(ALR != IntA.end() && "Live range not found!");
126 VNInfo *AValNo = ALR->valno;
127 // If it's re-defined by an early clobber somewhere in the live range, then
128 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
130 // 172 %ECX<def> = MOV32rr %reg1039<kill>
131 // 180 INLINEASM <es:subl $5,$1
132 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
133 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
134 // 188 %EAX<def> = MOV32rr %EAX<kill>
135 // 196 %ECX<def> = MOV32rr %ECX<kill>
136 // 204 %ECX<def> = MOV32rr %ECX<kill>
137 // 212 %EAX<def> = MOV32rr %EAX<kill>
138 // 220 %EAX<def> = MOV32rr %EAX
139 // 228 %reg1039<def> = MOV32rr %ECX<kill>
140 // The early clobber operand ties ECX input to the ECX def.
142 // The live interval of ECX is represented as this:
143 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
144 // The coalescer has no idea there was a def in the middle of [174,230].
145 if (AValNo->hasRedefByEC())
148 // If AValNo is defined as a copy from IntB, we can potentially process this.
149 // Get the instruction that defines this value number.
150 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
151 if (!SrcReg) return false; // Not defined by a copy.
153 // If the value number is not defined by a copy instruction, ignore it.
155 // If the source register comes from an interval other than IntB, we can't
157 if (SrcReg != IntB.reg) return false;
159 // Get the LiveRange in IntB that this value number starts with.
160 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
161 assert(ValLR != IntB.end() && "Live range not found!");
163 // Make sure that the end of the live range is inside the same block as
165 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
167 ValLREndInst->getParent() != CopyMI->getParent()) return false;
169 // Okay, we now know that ValLR ends in the same block that the CopyMI
170 // live-range starts. If there are no intervening live ranges between them in
171 // IntB, we can merge them.
172 if (ValLR+1 != BLR) return false;
174 // If a live interval is a physical register, conservatively check if any
175 // of its sub-registers is overlapping the live interval of the virtual
176 // register. If so, do not coalesce.
177 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
178 *tri_->getSubRegisters(IntB.reg)) {
179 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
180 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
181 DOUT << "Interfere with sub-register ";
182 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
187 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
189 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
190 // We are about to delete CopyMI, so need to remove it as the 'instruction
191 // that defines this value #'. Update the the valnum with the new defining
193 BValNo->def = FillerStart;
196 // Okay, we can merge them. We need to insert a new liverange:
197 // [ValLR.end, BLR.begin) of either value number, then we merge the
198 // two value numbers.
199 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
201 // If the IntB live range is assigned to a physical register, and if that
202 // physreg has sub-registers, update their live intervals as well.
203 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
204 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
205 LiveInterval &SRLI = li_->getInterval(*SR);
206 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
207 SRLI.getNextValue(FillerStart, 0, true,
208 li_->getVNInfoAllocator())));
212 // Okay, merge "B1" into the same value number as "B0".
213 if (BValNo != ValLR->valno) {
214 IntB.addKills(ValLR->valno, BValNo->kills);
215 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
217 DOUT << " result = "; IntB.print(DOUT, tri_);
220 // If the source instruction was killing the source register before the
221 // merge, unset the isKill marker given the live range has been extended.
222 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
224 ValLREndInst->getOperand(UIdx).setIsKill(false);
225 IntB.removeKill(ValLR->valno, FillerStart);
232 /// HasOtherReachingDefs - Return true if there are definitions of IntB
233 /// other than BValNo val# that can reach uses of AValno val# of IntA.
234 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
238 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
240 if (AI->valno != AValNo) continue;
241 LiveInterval::Ranges::iterator BI =
242 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
243 if (BI != IntB.ranges.begin())
245 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
246 if (BI->valno == BValNo)
248 if (BI->start <= AI->start && BI->end > AI->start)
250 if (BI->start > AI->start && BI->start < AI->end)
257 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
258 /// being the source and IntB being the dest, thus this defines a value number
259 /// in IntB. If the source value number (in IntA) is defined by a commutable
260 /// instruction and its other operand is coalesced to the copy dest register,
261 /// see if we can transform the copy into a noop by commuting the definition. For
264 /// A3 = op A2 B0<kill>
266 /// B1 = A3 <- this copy
268 /// = op A3 <- more uses
272 /// B2 = op B0 A2<kill>
274 /// B1 = B2 <- now an identify copy
276 /// = op B2 <- more uses
278 /// This returns true if an interval was modified.
280 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
282 MachineInstr *CopyMI) {
283 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
285 // FIXME: For now, only eliminate the copy by commuting its def when the
286 // source register is a virtual register. We want to guard against cases
287 // where the copy is a back edge copy and commuting the def lengthen the
288 // live interval of the source register to the entire loop.
289 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
292 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
293 // the example above.
294 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
295 assert(BLR != IntB.end() && "Live range not found!");
296 VNInfo *BValNo = BLR->valno;
298 // Get the location that B is defined at. Two options: either this value has
299 // an unknown definition point or it is defined at CopyIdx. If unknown, we
301 if (!BValNo->copy) return false;
302 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
304 // AValNo is the value number in A that defines the copy, A3 in the example.
305 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
306 assert(ALR != IntA.end() && "Live range not found!");
307 VNInfo *AValNo = ALR->valno;
308 // If other defs can reach uses of this def, then it's not safe to perform
309 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
311 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
312 AValNo->isUnused() || AValNo->hasPHIKill())
314 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
315 const TargetInstrDesc &TID = DefMI->getDesc();
316 if (!TID.isCommutable())
318 // If DefMI is a two-address instruction then commuting it will change the
319 // destination register.
320 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
321 assert(DefIdx != -1);
323 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
325 unsigned Op1, Op2, NewDstIdx;
326 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
330 else if (Op2 == UseOpIdx)
335 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
336 unsigned NewReg = NewDstMO.getReg();
337 if (NewReg != IntB.reg || !NewDstMO.isKill())
340 // Make sure there are no other definitions of IntB that would reach the
341 // uses which the new definition can reach.
342 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
345 // If some of the uses of IntA.reg is already coalesced away, return false.
346 // It's not possible to determine whether it's safe to perform the coalescing.
347 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
348 UE = mri_->use_end(); UI != UE; ++UI) {
349 MachineInstr *UseMI = &*UI;
350 unsigned UseIdx = li_->getInstructionIndex(UseMI);
351 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
352 if (ULR == IntA.end())
354 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
358 // At this point we have decided that it is legal to do this
359 // transformation. Start by commuting the instruction.
360 MachineBasicBlock *MBB = DefMI->getParent();
361 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
364 if (NewMI != DefMI) {
365 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
366 MBB->insert(DefMI, NewMI);
369 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
370 NewMI->getOperand(OpIdx).setIsKill();
372 bool BHasPHIKill = BValNo->hasPHIKill();
373 SmallVector<VNInfo*, 4> BDeadValNos;
374 VNInfo::KillSet BKills;
375 std::map<unsigned, unsigned> BExtend;
377 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
386 // then do not add kills of A to the newly created B interval.
387 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
389 BExtend[ALR->end] = BLR->end;
391 // Update uses of IntA of the specific Val# with IntB.
392 bool BHasSubRegs = false;
393 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
394 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
395 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
396 UE = mri_->use_end(); UI != UE;) {
397 MachineOperand &UseMO = UI.getOperand();
398 MachineInstr *UseMI = &*UI;
400 if (JoinedCopies.count(UseMI))
402 unsigned UseIdx = li_->getInstructionIndex(UseMI);
403 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
404 if (ULR == IntA.end() || ULR->valno != AValNo)
406 UseMO.setReg(NewReg);
409 if (UseMO.isKill()) {
411 UseMO.setIsKill(false);
413 BKills.push_back(VNInfo::KillInfo(false, li_->getUseIndex(UseIdx)+1));
415 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
416 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
418 if (DstReg == IntB.reg) {
419 // This copy will become a noop. If it's defining a new val#,
420 // remove that val# as well. However this live range is being
421 // extended to the end of the existing live range defined by the copy.
422 unsigned DefIdx = li_->getDefIndex(UseIdx);
423 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
424 BHasPHIKill |= DLR->valno->hasPHIKill();
425 assert(DLR->valno->def == DefIdx);
426 BDeadValNos.push_back(DLR->valno);
427 BExtend[DLR->start] = DLR->end;
428 JoinedCopies.insert(UseMI);
429 // If this is a kill but it's going to be removed, the last use
430 // of the same val# is the new kill.
436 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
437 // simply extend BLR if CopyMI doesn't end the range.
438 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
440 // Remove val#'s defined by copies that will be coalesced away.
441 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
442 VNInfo *DeadVNI = BDeadValNos[i];
444 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
445 LiveInterval &SRLI = li_->getInterval(*SR);
446 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
447 SRLI.removeValNo(SRLR->valno);
450 IntB.removeValNo(BDeadValNos[i]);
453 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
454 // is updated. Kills are also updated.
455 VNInfo *ValNo = BValNo;
456 ValNo->def = AValNo->def;
458 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
459 unsigned Kill = ValNo->kills[j].killIdx;
460 if (Kill != BLR->end)
461 BKills.push_back(VNInfo::KillInfo(ValNo->kills[j].isPHIKill, Kill));
463 ValNo->kills.clear();
464 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
466 if (AI->valno != AValNo) continue;
467 unsigned End = AI->end;
468 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
469 if (EI != BExtend.end())
471 IntB.addRange(LiveRange(AI->start, End, ValNo));
473 // If the IntB live range is assigned to a physical register, and if that
474 // physreg has sub-registers, update their live intervals as well.
476 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
477 LiveInterval &SRLI = li_->getInterval(*SR);
478 SRLI.MergeInClobberRange(AI->start, End, li_->getVNInfoAllocator());
482 IntB.addKills(ValNo, BKills);
483 ValNo->setHasPHIKill(BHasPHIKill);
485 DOUT << " result = "; IntB.print(DOUT, tri_);
488 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
489 IntA.removeValNo(AValNo);
490 DOUT << " result = "; IntA.print(DOUT, tri_);
497 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
498 /// fallthoughs to SuccMBB.
499 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
500 MachineBasicBlock *SuccMBB,
501 const TargetInstrInfo *tii_) {
504 MachineBasicBlock *TBB = 0, *FBB = 0;
505 SmallVector<MachineOperand, 4> Cond;
506 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
507 MBB->isSuccessor(SuccMBB);
510 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
511 /// from a physical register live interval as well as from the live intervals
512 /// of its sub-registers.
513 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
514 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
515 li.removeRange(Start, End, true);
516 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
517 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
518 if (!li_->hasInterval(*SR))
520 LiveInterval &sli = li_->getInterval(*SR);
521 unsigned RemoveEnd = Start;
522 while (RemoveEnd != End) {
523 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
526 RemoveEnd = (LR->end < End) ? LR->end : End;
527 sli.removeRange(Start, RemoveEnd, true);
534 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
535 /// as the copy instruction, trim the live interval to the last use and return
538 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
539 MachineBasicBlock *CopyMBB,
541 const LiveRange *LR) {
542 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
544 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
547 MachineInstr *LastUseMI = LastUse->getParent();
548 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
555 // r1025<dead> = r1024<kill>
556 if (MBBStart < LR->end)
557 removeRange(li, MBBStart, LR->end, li_, tri_);
561 // There are uses before the copy, just shorten the live range to the end
563 LastUse->setIsKill();
564 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
565 li.addKill(LR->valno, LastUseIdx+1, false);
566 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
567 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
569 // Last use is itself an identity code.
570 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
571 LastUseMI->getOperand(DeadIdx).setIsDead();
577 if (LR->start <= MBBStart && LR->end > MBBStart) {
578 if (LR->start == 0) {
579 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
580 // Live-in to the function but dead. Remove it from entry live-in set.
581 mf_->begin()->removeLiveIn(li.reg);
583 // FIXME: Shorten intervals in BBs that reaches this BB.
589 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
590 /// computation, replace the copy by rematerialize the definition.
591 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
593 MachineInstr *CopyMI) {
594 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
595 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
596 assert(SrcLR != SrcInt.end() && "Live range not found!");
597 VNInfo *ValNo = SrcLR->valno;
598 // If other defs can reach uses of this def, then it's not safe to perform
599 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
601 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
602 ValNo->isUnused() || ValNo->hasPHIKill())
604 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
605 const TargetInstrDesc &TID = DefMI->getDesc();
606 if (!TID.isAsCheapAsAMove())
608 if (!DefMI->getDesc().isRematerializable() ||
609 !tii_->isTriviallyReMaterializable(DefMI))
611 bool SawStore = false;
612 if (!DefMI->isSafeToMove(tii_, SawStore))
614 if (TID.getNumDefs() != 1)
616 // Make sure the copy destination register class fits the instruction
617 // definition register class. The mismatch can happen as a result of earlier
618 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
619 const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0);
620 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
621 if (mri_->getRegClass(DstReg) != RC)
623 } else if (!RC->contains(DstReg))
626 unsigned DefIdx = li_->getDefIndex(CopyIdx);
627 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
628 DLR->valno->copy = NULL;
629 // Don't forget to update sub-register intervals.
630 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
631 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
632 if (!li_->hasInterval(*SR))
634 DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
635 if (DLR && DLR->valno->copy == CopyMI)
636 DLR->valno->copy = NULL;
640 // If copy kills the source register, find the last use and propagate
642 bool checkForDeadDef = false;
643 MachineBasicBlock *MBB = CopyMI->getParent();
644 if (CopyMI->killsRegister(SrcInt.reg))
645 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
646 checkForDeadDef = true;
649 MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
650 tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
651 MachineInstr *NewMI = prior(MII);
653 if (checkForDeadDef) {
654 // PR4090 fix: Trim interval failed because there was no use of the
655 // source interval in this MBB. If the def is in this MBB too then we
656 // should mark it dead:
657 if (DefMI->getParent() == MBB) {
658 DefMI->addRegisterDead(SrcInt.reg, tri_);
659 SrcLR->end = SrcLR->start + 1;
663 // CopyMI may have implicit operands, transfer them over to the newly
664 // rematerialized instruction. And update implicit def interval valnos.
665 for (unsigned i = CopyMI->getDesc().getNumOperands(),
666 e = CopyMI->getNumOperands(); i != e; ++i) {
667 MachineOperand &MO = CopyMI->getOperand(i);
668 if (MO.isReg() && MO.isImplicit())
669 NewMI->addOperand(MO);
670 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
671 unsigned Reg = MO.getReg();
672 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
673 if (DLR && DLR->valno->copy == CopyMI)
674 DLR->valno->copy = NULL;
678 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
679 CopyMI->eraseFromParent();
680 ReMatCopies.insert(CopyMI);
681 ReMatDefs.insert(DefMI);
686 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
688 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
689 unsigned DstReg) const {
690 MachineBasicBlock *MBB = CopyMI->getParent();
691 const MachineLoop *L = loopInfo->getLoopFor(MBB);
694 if (MBB != L->getLoopLatch())
697 LiveInterval &LI = li_->getInterval(DstReg);
698 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
699 LiveInterval::const_iterator DstLR =
700 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
701 if (DstLR == LI.end())
703 if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0].isPHIKill)
708 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
709 /// update the subregister number if it is not zero. If DstReg is a
710 /// physical register and the existing subregister number of the def / use
711 /// being updated is not zero, make sure to set it to the correct physical
714 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
716 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
717 if (DstIsPhys && SubIdx) {
718 // Figure out the real physical register we are updating with.
719 DstReg = tri_->getSubReg(DstReg, SubIdx);
723 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
724 E = mri_->reg_end(); I != E; ) {
725 MachineOperand &O = I.getOperand();
726 MachineInstr *UseMI = &*I;
728 unsigned OldSubIdx = O.getSubReg();
730 unsigned UseDstReg = DstReg;
732 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
734 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
735 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
736 CopySrcSubIdx, CopyDstSubIdx) &&
737 CopySrcReg != CopyDstReg &&
738 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
739 // If the use is a copy and it won't be coalesced away, and its source
740 // is defined by a trivial computation, try to rematerialize it instead.
741 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
750 // Sub-register indexes goes from small to large. e.g.
751 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
752 // EAX: 1 -> AL, 2 -> AX
753 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
754 // sub-register 2 is also AX.
755 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
756 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
759 // Remove would-be duplicated kill marker.
760 if (O.isKill() && UseMI->killsRegister(DstReg))
764 // After updating the operand, check if the machine instruction has
765 // become a copy. If so, update its val# information.
766 if (JoinedCopies.count(UseMI))
769 const TargetInstrDesc &TID = UseMI->getDesc();
770 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
771 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
772 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
773 CopySrcSubIdx, CopyDstSubIdx) &&
774 CopySrcReg != CopyDstReg &&
775 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
776 allocatableRegs_[CopyDstReg])) {
777 LiveInterval &LI = li_->getInterval(CopyDstReg);
778 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
779 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
780 if (DLR->valno->def == DefIdx)
781 DLR->valno->copy = UseMI;
787 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
788 /// registers due to insert_subreg coalescing. e.g.
790 /// r1025 = implicit_def
791 /// r1025 = insert_subreg r1025, r1024
795 /// r1025 = implicit_def
796 /// r1025 = insert_subreg r1025, r1025
799 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
800 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
801 E = mri_->reg_end(); I != E; ) {
802 MachineOperand &O = I.getOperand();
803 MachineInstr *DefMI = &*I;
807 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
809 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
811 li_->RemoveMachineInstrFromMaps(DefMI);
812 DefMI->eraseFromParent();
816 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
817 /// due to live range lengthening as the result of coalescing.
818 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
820 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
821 UE = mri_->use_end(); UI != UE; ++UI) {
822 MachineOperand &UseMO = UI.getOperand();
823 if (UseMO.isKill()) {
824 MachineInstr *UseMI = UseMO.getParent();
825 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
826 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
827 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
828 UseMO.setIsKill(false);
833 /// removeIntervalIfEmpty - Check if the live interval of a physical register
834 /// is empty, if so remove it and also remove the empty intervals of its
835 /// sub-registers. Return true if live interval is removed.
836 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
837 const TargetRegisterInfo *tri_) {
839 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
840 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
841 if (!li_->hasInterval(*SR))
843 LiveInterval &sli = li_->getInterval(*SR);
845 li_->removeInterval(*SR);
847 li_->removeInterval(li.reg);
853 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
854 /// Return true if live interval is removed.
855 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
856 MachineInstr *CopyMI) {
857 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
858 LiveInterval::iterator MLR =
859 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
861 return false; // Already removed by ShortenDeadCopySrcLiveRange.
862 unsigned RemoveStart = MLR->start;
863 unsigned RemoveEnd = MLR->end;
864 // Remove the liverange that's defined by this.
865 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
866 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
867 return removeIntervalIfEmpty(li, li_, tri_);
872 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
873 /// the val# it defines. If the live interval becomes empty, remove it as well.
874 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
875 MachineInstr *DefMI) {
876 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
877 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
878 if (DefIdx != MLR->valno->def)
880 li.removeValNo(MLR->valno);
881 return removeIntervalIfEmpty(li, li_, tri_);
884 /// PropagateDeadness - Propagate the dead marker to the instruction which
885 /// defines the val#.
886 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
887 unsigned &LRStart, LiveIntervals *li_,
888 const TargetRegisterInfo* tri_) {
889 MachineInstr *DefMI =
890 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
891 if (DefMI && DefMI != CopyMI) {
892 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
894 DefMI->getOperand(DeadIdx).setIsDead();
895 // A dead def should have a single cycle interval.
901 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
902 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
903 /// ends the live range there. If there isn't another use, then this live range
904 /// is dead. Return true if live interval is removed.
906 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
907 MachineInstr *CopyMI) {
908 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
910 // FIXME: special case: function live in. It can be a general case if the
911 // first instruction index starts at > 0 value.
912 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
913 // Live-in to the function but dead. Remove it from entry live-in set.
914 if (mf_->begin()->isLiveIn(li.reg))
915 mf_->begin()->removeLiveIn(li.reg);
916 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
917 removeRange(li, LR->start, LR->end, li_, tri_);
918 return removeIntervalIfEmpty(li, li_, tri_);
921 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
923 // Livein but defined by a phi.
926 unsigned RemoveStart = LR->start;
927 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
928 if (LR->end > RemoveEnd)
929 // More uses past this copy? Nothing to do.
932 // If there is a last use in the same bb, we can't remove the live range.
933 // Shorten the live interval and return.
934 MachineBasicBlock *CopyMBB = CopyMI->getParent();
935 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
938 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
939 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
940 // If the live range starts in another mbb and the copy mbb is not a fall
941 // through mbb, then we can only cut the range from the beginning of the
943 RemoveStart = li_->getMBBStartIdx(CopyMBB) + 1;
945 if (LR->valno->def == RemoveStart) {
946 // If the def MI defines the val# and this copy is the only kill of the
947 // val#, then propagate the dead marker.
948 if (li.isOnlyLROfValNo(LR)) {
949 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
952 if (li.isKill(LR->valno, RemoveEnd))
953 li.removeKill(LR->valno, RemoveEnd);
956 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
957 return removeIntervalIfEmpty(li, li_, tri_);
960 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
961 /// from an implicit def to another register can be coalesced away.
962 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
964 LiveInterval &ImpLi) const{
965 if (!CopyMI->killsRegister(ImpLi.reg))
967 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
968 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
971 if (LR->valno->hasPHIKill())
973 if (LR->valno->def != CopyIdx)
975 // Make sure all of val# uses are copies.
976 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
977 UE = mri_->use_end(); UI != UE;) {
978 MachineInstr *UseMI = &*UI;
980 if (JoinedCopies.count(UseMI))
982 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
983 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
984 if (ULR == li.end() || ULR->valno != LR->valno)
986 // If the use is not a use, then it's not safe to coalesce the move.
987 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
988 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
989 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
990 UseMI->getOperand(1).getReg() == li.reg)
999 /// TurnCopiesFromValNoToImpDefs - The specified value# is defined by an
1000 /// implicit_def and it is being removed. Turn all copies from this value#
1001 /// into implicit_defs.
1002 void SimpleRegisterCoalescing::TurnCopiesFromValNoToImpDefs(LiveInterval &li,
1004 SmallVector<MachineInstr*, 4> ImpDefs;
1005 MachineOperand *LastUse = NULL;
1006 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
1007 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
1008 RE = mri_->reg_end(); RI != RE;) {
1009 MachineOperand *MO = &RI.getOperand();
1010 MachineInstr *MI = &*RI;
1013 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
1014 ImpDefs.push_back(MI);
1017 if (JoinedCopies.count(MI))
1019 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
1020 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
1021 if (ULR == li.end() || ULR->valno != VNI)
1023 // If the use is a copy, turn it into an identity copy.
1024 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1025 if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1027 // Change it to an implicit_def.
1028 MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
1029 for (int i = MI->getNumOperands() - 1, e = 0; i > e; --i)
1030 MI->RemoveOperand(i);
1031 // It's no longer a copy, update the valno it defines.
1032 unsigned DefIdx = li_->getDefIndex(UseIdx);
1033 LiveInterval &DstInt = li_->getInterval(DstReg);
1034 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(DefIdx);
1035 assert(DLR != DstInt.end() && "Live range not found!");
1036 assert(DLR->valno->copy == MI);
1037 DLR->valno->copy = NULL;
1038 ReMatCopies.insert(MI);
1039 } else if (UseIdx > LastUseIdx) {
1040 LastUseIdx = UseIdx;
1045 LastUse->setIsKill();
1046 li.addKill(VNI, LastUseIdx+1, false);
1048 // Remove dead implicit_def's.
1049 while (!ImpDefs.empty()) {
1050 MachineInstr *ImpDef = ImpDefs.back();
1052 li_->RemoveMachineInstrFromMaps(ImpDef);
1053 ImpDef->eraseFromParent();
1058 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
1059 /// a virtual destination register with physical source register.
1061 SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
1062 MachineBasicBlock *CopyMBB,
1063 LiveInterval &DstInt,
1064 LiveInterval &SrcInt) {
1065 // If the virtual register live interval is long but it has low use desity,
1066 // do not join them, instead mark the physical register as its allocation
1068 const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg);
1069 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1070 unsigned Length = li_->getApproximateInstructionCount(DstInt);
1071 if (Length > Threshold &&
1072 (((float)std::distance(mri_->use_begin(DstInt.reg),
1073 mri_->use_end()) / Length) < (1.0 / Threshold)))
1076 // If the virtual register live interval extends into a loop, turn down
1078 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1079 const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
1081 // Let's see if the virtual register live interval extends into the loop.
1082 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
1083 assert(DLR != DstInt.end() && "Live range not found!");
1084 DLR = DstInt.FindLiveRangeContaining(DLR->end+1);
1085 if (DLR != DstInt.end()) {
1086 CopyMBB = li_->getMBBFromIndex(DLR->start);
1087 L = loopInfo->getLoopFor(CopyMBB);
1091 if (!L || Length <= Threshold)
1094 unsigned UseIdx = li_->getUseIndex(CopyIdx);
1095 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1096 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1097 if (loopInfo->getLoopFor(SMBB) != L) {
1098 if (!loopInfo->isLoopHeader(CopyMBB))
1100 // If vr's live interval extends pass the loop header, do not join.
1101 for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(),
1102 SE = CopyMBB->succ_end(); SI != SE; ++SI) {
1103 MachineBasicBlock *SuccMBB = *SI;
1104 if (SuccMBB == CopyMBB)
1106 if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
1107 li_->getMBBEndIdx(SuccMBB)+1))
1114 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
1115 /// copy from a virtual source register to a physical destination register.
1117 SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
1118 MachineBasicBlock *CopyMBB,
1119 LiveInterval &DstInt,
1120 LiveInterval &SrcInt) {
1121 // If the virtual register live interval is long but it has low use desity,
1122 // do not join them, instead mark the physical register as its allocation
1124 const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
1125 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1126 unsigned Length = li_->getApproximateInstructionCount(SrcInt);
1127 if (Length > Threshold &&
1128 (((float)std::distance(mri_->use_begin(SrcInt.reg),
1129 mri_->use_end()) / Length) < (1.0 / Threshold)))
1133 // Must be implicit_def.
1136 // If the virtual register live interval is defined or cross a loop, turn
1137 // down aggressiveness.
1138 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1139 unsigned UseIdx = li_->getUseIndex(CopyIdx);
1140 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1141 assert(SLR != SrcInt.end() && "Live range not found!");
1142 SLR = SrcInt.FindLiveRangeContaining(SLR->start-1);
1143 if (SLR == SrcInt.end())
1145 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1146 const MachineLoop *L = loopInfo->getLoopFor(SMBB);
1148 if (!L || Length <= Threshold)
1151 if (loopInfo->getLoopFor(CopyMBB) != L) {
1152 if (SMBB != L->getLoopLatch())
1154 // If vr's live interval is extended from before the loop latch, do not
1156 for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(),
1157 PE = SMBB->pred_end(); PI != PE; ++PI) {
1158 MachineBasicBlock *PredMBB = *PI;
1159 if (PredMBB == SMBB)
1161 if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
1162 li_->getMBBEndIdx(PredMBB)+1))
1169 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1170 /// two virtual registers from different register classes.
1172 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned LargeReg,
1174 unsigned Threshold) {
1175 // Then make sure the intervals are *short*.
1176 LiveInterval &LargeInt = li_->getInterval(LargeReg);
1177 LiveInterval &SmallInt = li_->getInterval(SmallReg);
1178 unsigned LargeSize = li_->getApproximateInstructionCount(LargeInt);
1179 unsigned SmallSize = li_->getApproximateInstructionCount(SmallInt);
1180 if (SmallSize > Threshold || LargeSize > Threshold)
1181 if ((float)std::distance(mri_->use_begin(SmallReg),
1182 mri_->use_end()) / SmallSize <
1183 (float)std::distance(mri_->use_begin(LargeReg),
1184 mri_->use_end()) / LargeSize)
1189 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1190 /// register with a physical register, check if any of the virtual register
1191 /// operand is a sub-register use or def. If so, make sure it won't result
1192 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1193 /// vr1024 = extract_subreg vr1025, 1
1195 /// vr1024 = mov8rr AH
1196 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1197 /// AH does not have a super-reg whose sub-register 1 is AH.
1199 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1202 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1203 E = mri_->reg_end(); I != E; ++I) {
1204 MachineOperand &O = I.getOperand();
1205 MachineInstr *MI = &*I;
1206 if (MI == CopyMI || JoinedCopies.count(MI))
1208 unsigned SubIdx = O.getSubReg();
1209 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1211 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1212 SubIdx = MI->getOperand(2).getImm();
1213 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1216 unsigned SrcReg = MI->getOperand(1).getReg();
1217 const TargetRegisterClass *RC =
1218 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1219 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1220 : mri_->getRegClass(SrcReg);
1221 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1225 if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
1226 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
1227 SubIdx = MI->getOperand(3).getImm();
1228 if (VirtReg == MI->getOperand(0).getReg()) {
1229 if (!tri_->getSubReg(PhysReg, SubIdx))
1232 unsigned DstReg = MI->getOperand(0).getReg();
1233 const TargetRegisterClass *RC =
1234 TargetRegisterInfo::isPhysicalRegister(DstReg)
1235 ? tri_->getPhysicalRegisterRegClass(DstReg)
1236 : mri_->getRegClass(DstReg);
1237 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1246 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1247 /// an extract_subreg where dst is a physical register, e.g.
1248 /// cl = EXTRACT_SUBREG reg1024, 1
1250 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1251 unsigned SrcReg, unsigned SubIdx,
1252 unsigned &RealDstReg) {
1253 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1254 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1255 assert(RealDstReg && "Invalid extract_subreg instruction!");
1257 // For this type of EXTRACT_SUBREG, conservatively
1258 // check if the live interval of the source register interfere with the
1259 // actual super physical register we are trying to coalesce with.
1260 LiveInterval &RHS = li_->getInterval(SrcReg);
1261 if (li_->hasInterval(RealDstReg) &&
1262 RHS.overlaps(li_->getInterval(RealDstReg))) {
1263 DOUT << "Interfere with register ";
1264 DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
1265 return false; // Not coalescable
1267 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1268 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1269 DOUT << "Interfere with sub-register ";
1270 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1271 return false; // Not coalescable
1276 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1277 /// an insert_subreg where src is a physical register, e.g.
1278 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1280 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1281 unsigned SrcReg, unsigned SubIdx,
1282 unsigned &RealSrcReg) {
1283 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1284 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1285 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1287 LiveInterval &RHS = li_->getInterval(DstReg);
1288 if (li_->hasInterval(RealSrcReg) &&
1289 RHS.overlaps(li_->getInterval(RealSrcReg))) {
1290 DOUT << "Interfere with register ";
1291 DEBUG(li_->getInterval(RealSrcReg).print(DOUT, tri_));
1292 return false; // Not coalescable
1294 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1295 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1296 DOUT << "Interfere with sub-register ";
1297 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1298 return false; // Not coalescable
1303 /// getRegAllocPreference - Return register allocation preference register.
1305 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1306 MachineRegisterInfo *MRI,
1307 const TargetRegisterInfo *TRI) {
1308 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1310 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
1311 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1314 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1315 /// which are the src/dst of the copy instruction CopyMI. This returns true
1316 /// if the copy was successfully coalesced away. If it is not currently
1317 /// possible to coalesce this interval, but it may be possible if other
1318 /// things get coalesced, then it returns true by reference in 'Again'.
1319 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1320 MachineInstr *CopyMI = TheCopy.MI;
1323 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1324 return false; // Already done.
1326 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
1328 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1329 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
1330 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
1331 bool isSubRegToReg = CopyMI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG;
1332 unsigned SubIdx = 0;
1334 DstReg = CopyMI->getOperand(0).getReg();
1335 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1336 SrcReg = CopyMI->getOperand(1).getReg();
1337 SrcSubIdx = CopyMI->getOperand(2).getImm();
1338 } else if (isInsSubReg || isSubRegToReg) {
1339 if (CopyMI->getOperand(2).getSubReg()) {
1340 DOUT << "\tSource of insert_subreg is already coalesced "
1341 << "to another register.\n";
1342 return false; // Not coalescable.
1344 DstReg = CopyMI->getOperand(0).getReg();
1345 DstSubIdx = CopyMI->getOperand(3).getImm();
1346 SrcReg = CopyMI->getOperand(2).getReg();
1347 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
1348 llvm_unreachable("Unrecognized copy instruction!");
1351 // If they are already joined we continue.
1352 if (SrcReg == DstReg) {
1353 DOUT << "\tCopy already coalesced.\n";
1354 return false; // Not coalescable.
1357 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1358 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1360 // If they are both physical registers, we cannot join them.
1361 if (SrcIsPhys && DstIsPhys) {
1362 DOUT << "\tCan not coalesce physregs.\n";
1363 return false; // Not coalescable.
1366 // We only join virtual registers with allocatable physical registers.
1367 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1368 DOUT << "\tSrc reg is unallocatable physreg.\n";
1369 return false; // Not coalescable.
1371 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1372 DOUT << "\tDst reg is unallocatable physreg.\n";
1373 return false; // Not coalescable.
1376 // Check that a physical source register is compatible with dst regclass
1378 unsigned SrcSubReg = SrcSubIdx ?
1379 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1380 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1381 const TargetRegisterClass *DstSubRC = DstRC;
1383 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1384 assert(DstSubRC && "Illegal subregister index");
1385 if (!DstSubRC->contains(SrcSubReg)) {
1386 DOUT << "\tIncompatible destination regclass: "
1387 << tri_->getName(SrcSubReg) << " not in " << DstSubRC->getName()
1389 return false; // Not coalescable.
1393 // Check that a physical dst register is compatible with source regclass
1395 unsigned DstSubReg = DstSubIdx ?
1396 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1397 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1398 const TargetRegisterClass *SrcSubRC = SrcRC;
1400 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1401 assert(SrcSubRC && "Illegal subregister index");
1402 if (!SrcSubRC->contains(DstReg)) {
1403 DOUT << "\tIncompatible source regclass: "
1404 << tri_->getName(DstSubReg) << " not in " << SrcSubRC->getName()
1406 return false; // Not coalescable.
1410 // Should be non-null only when coalescing to a sub-register class.
1411 bool CrossRC = false;
1412 const TargetRegisterClass *NewRC = NULL;
1413 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1414 unsigned RealDstReg = 0;
1415 unsigned RealSrcReg = 0;
1416 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1417 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1418 if (SrcIsPhys && isExtSubReg) {
1419 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1420 // coalesced with AX.
1421 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1423 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1424 // coalesced to a larger register so the subreg indices cancel out.
1425 if (DstSubIdx != SubIdx) {
1426 DOUT << "\t Sub-register indices mismatch.\n";
1427 return false; // Not coalescable.
1430 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1432 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1433 // EAX = INSERT_SUBREG EAX, r1024, 0
1434 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1436 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1437 // coalesced to a larger register so the subreg indices cancel out.
1438 if (SrcSubIdx != SubIdx) {
1439 DOUT << "\t Sub-register indices mismatch.\n";
1440 return false; // Not coalescable.
1443 DstReg = tri_->getSubReg(DstReg, SubIdx);
1445 } else if ((DstIsPhys && isExtSubReg) ||
1446 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1447 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1448 DOUT << "\tSrc of extract_subreg already coalesced with reg"
1449 << " of a super-class.\n";
1450 return false; // Not coalescable.
1454 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1455 return false; // Not coalescable
1457 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1458 return false; // Not coalescable
1462 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1463 : CopyMI->getOperand(2).getSubReg();
1465 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1466 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1467 // coalesced to a larger register so the subreg indices cancel out.
1468 // Also check if the other larger register is of the same register
1469 // class as the would be resulting register.
1472 DOUT << "\t Sub-register indices mismatch.\n";
1473 return false; // Not coalescable.
1477 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1478 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1479 unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
1480 if (!isWinToJoinCrossClass(LargeReg, SmallReg, Limit)) {
1481 Again = true; // May be possible to coalesce later.
1486 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1487 if (!CrossClassJoin)
1491 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1492 // with another? If it's the resulting destination register, then
1493 // the subidx must be propagated to uses (but only those defined
1494 // by the EXTRACT_SUBREG). If it's being coalesced into another
1495 // register, it should be safe because register is assumed to have
1496 // the register class of the super-register.
1498 // Process moves where one of the registers have a sub-register index.
1499 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1500 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1501 SubIdx = DstMO->getSubReg();
1503 if (SrcMO->getSubReg())
1504 // FIXME: can we handle this?
1506 // This is not an insert_subreg but it looks like one.
1507 // e.g. %reg1024:4 = MOV32rr %EAX
1510 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1511 return false; // Not coalescable
1515 SubIdx = SrcMO->getSubReg();
1517 // This is not a extract_subreg but it looks like one.
1518 // e.g. %cl = MOV16rr %reg1024:1
1521 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1522 return false; // Not coalescable
1528 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1529 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1530 unsigned LargeReg = SrcReg;
1531 unsigned SmallReg = DstReg;
1534 // Now determine the register class of the joined register.
1536 if (SubIdx && DstRC && DstRC->isASubClass()) {
1537 // This is a move to a sub-register class. However, the source is a
1538 // sub-register of a larger register class. We don't know what should
1539 // the register class be. FIXME.
1543 Limit = allocatableRCRegs_[DstRC].count();
1544 } else if (!SrcIsPhys && !DstIsPhys) {
1545 NewRC = getCommonSubClass(SrcRC, DstRC);
1547 DOUT << "\tDisjoint regclasses: "
1548 << SrcRC->getName() << ", "
1549 << DstRC->getName() << ".\n";
1550 return false; // Not coalescable.
1552 if (DstRC->getSize() > SrcRC->getSize())
1553 std::swap(LargeReg, SmallReg);
1556 // If we are joining two virtual registers and the resulting register
1557 // class is more restrictive (fewer register, smaller size). Check if it's
1558 // worth doing the merge.
1559 if (!SrcIsPhys && !DstIsPhys &&
1560 (isExtSubReg || DstRC->isASubClass()) &&
1561 !isWinToJoinCrossClass(LargeReg, SmallReg,
1562 allocatableRCRegs_[NewRC].count())) {
1563 DOUT << "\tSrc/Dest are different register classes.\n";
1564 // Allow the coalescer to try again in case either side gets coalesced to
1565 // a physical register that's compatible with the other side. e.g.
1566 // r1024 = MOV32to32_ r1025
1567 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1568 Again = true; // May be possible to coalesce later.
1573 // Will it create illegal extract_subreg / insert_subreg?
1574 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1576 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1579 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1580 LiveInterval &DstInt = li_->getInterval(DstReg);
1581 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1582 "Register mapping is horribly broken!");
1584 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1585 DOUT << " and "; DstInt.print(DOUT, tri_);
1588 // Save a copy of the virtual register live interval. We'll manually
1589 // merge this into the "real" physical register live interval this is
1591 LiveInterval *SavedLI = 0;
1593 SavedLI = li_->dupInterval(&SrcInt);
1594 else if (RealSrcReg)
1595 SavedLI = li_->dupInterval(&DstInt);
1597 // Check if it is necessary to propagate "isDead" property.
1598 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1599 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1600 bool isDead = mopd->isDead();
1602 // We need to be careful about coalescing a source physical register with a
1603 // virtual register. Once the coalescing is done, it cannot be broken and
1604 // these are not spillable! If the destination interval uses are far away,
1605 // think twice about coalescing them!
1606 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1607 // If the copy is in a loop, take care not to coalesce aggressively if the
1608 // src is coming in from outside the loop (or the dst is out of the loop).
1609 // If it's not in a loop, then determine whether to join them base purely
1610 // by the length of the interval.
1611 if (PhysJoinTweak) {
1613 if (!isWinToJoinVRWithSrcPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
1614 mri_->setRegAllocationHint(DstInt.reg, 0, SrcReg);
1616 DOUT << "\tMay tie down a physical register, abort!\n";
1617 Again = true; // May be possible to coalesce later.
1621 if (!isWinToJoinVRWithDstPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
1622 mri_->setRegAllocationHint(SrcInt.reg, 0, DstReg);
1624 DOUT << "\tMay tie down a physical register, abort!\n";
1625 Again = true; // May be possible to coalesce later.
1630 // If the virtual register live interval is long but it has low use desity,
1631 // do not join them, instead mark the physical register as its allocation
1633 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1634 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1635 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1636 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1637 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1638 if (TheCopy.isBackEdge)
1639 Threshold *= 2; // Favors back edge copies.
1641 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1642 float Ratio = 1.0 / Threshold;
1643 if (Length > Threshold &&
1644 (((float)std::distance(mri_->use_begin(JoinVReg),
1645 mri_->use_end()) / Length) < Ratio)) {
1646 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1648 DOUT << "\tMay tie down a physical register, abort!\n";
1649 Again = true; // May be possible to coalesce later.
1656 // Okay, attempt to join these two intervals. On failure, this returns false.
1657 // Otherwise, if one of the intervals being joined is a physreg, this method
1658 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1659 // been modified, so we can use this information below to update aliases.
1660 bool Swapped = false;
1661 // If SrcInt is implicitly defined, it's safe to coalesce.
1662 bool isEmpty = SrcInt.empty();
1663 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1664 // Only coalesce an empty interval (defined by implicit_def) with
1665 // another interval which has a valno defined by the CopyMI and the CopyMI
1666 // is a kill of the implicit def.
1667 DOUT << "Not profitable!\n";
1671 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1672 // Coalescing failed.
1674 // If definition of source is defined by trivial computation, try
1675 // rematerializing it.
1676 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1677 ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
1680 // If we can eliminate the copy without merging the live ranges, do so now.
1681 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1682 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1683 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1684 JoinedCopies.insert(CopyMI);
1688 // Otherwise, we are unable to join the intervals.
1689 DOUT << "Interference!\n";
1690 Again = true; // May be possible to coalesce later.
1694 LiveInterval *ResSrcInt = &SrcInt;
1695 LiveInterval *ResDstInt = &DstInt;
1697 std::swap(SrcReg, DstReg);
1698 std::swap(ResSrcInt, ResDstInt);
1700 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1701 "LiveInterval::join didn't work right!");
1703 // If we're about to merge live ranges into a physical register live interval,
1704 // we have to update any aliased register's live ranges to indicate that they
1705 // have clobbered values for this range.
1706 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1707 // If this is a extract_subreg where dst is a physical register, e.g.
1708 // cl = EXTRACT_SUBREG reg1024, 1
1709 // then create and update the actual physical register allocated to RHS.
1710 if (RealDstReg || RealSrcReg) {
1711 LiveInterval &RealInt =
1712 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1713 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1714 E = SavedLI->vni_end(); I != E; ++I) {
1715 const VNInfo *ValNo = *I;
1716 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->copy,
1717 false, // updated at *
1718 li_->getVNInfoAllocator());
1719 NewValNo->setFlags(ValNo->getFlags()); // * updated here.
1720 RealInt.addKills(NewValNo, ValNo->kills);
1721 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1723 RealInt.weight += SavedLI->weight;
1724 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1727 // Update the liveintervals of sub-registers.
1728 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1729 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1730 li_->getVNInfoAllocator());
1733 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1734 // larger super-register.
1735 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1736 !SrcIsPhys && !DstIsPhys) {
1737 if ((isExtSubReg && !Swapped) ||
1738 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1739 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1740 std::swap(SrcReg, DstReg);
1741 std::swap(ResSrcInt, ResDstInt);
1745 // Coalescing to a virtual register that is of a sub-register class of the
1746 // other. Make sure the resulting register is set to the right register class.
1750 mri_->setRegClass(DstReg, NewRC);
1754 // Add all copies that define val# in the source interval into the queue.
1755 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1756 e = ResSrcInt->vni_end(); i != e; ++i) {
1757 const VNInfo *vni = *i;
1758 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1759 if (!vni->def || vni->isUnused() || vni->isPHIDef() || !vni->isDefAccurate())
1761 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1762 unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx;
1764 JoinedCopies.count(CopyMI) == 0 &&
1765 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg,
1766 NewSrcSubIdx, NewDstSubIdx)) {
1767 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1768 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1769 isBackEdgeCopy(CopyMI, DstReg)));
1774 // Remember to delete the copy instruction.
1775 JoinedCopies.insert(CopyMI);
1777 // Some live range has been lengthened due to colaescing, eliminate the
1778 // unnecessary kills.
1779 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1780 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1781 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1786 // r1024 = implicit_def
1789 RemoveDeadImpDef(DstReg, *ResDstInt);
1790 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1792 // SrcReg is guarateed to be the register whose live interval that is
1794 li_->removeInterval(SrcReg);
1796 // Update regalloc hint.
1797 tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
1799 // Manually deleted the live interval copy.
1806 // Now the copy is being coalesced away, the val# previously defined
1807 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1808 // length interval. Remove the val#.
1809 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1810 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1811 VNInfo *ImpVal = LR->valno;
1812 assert(ImpVal->def == CopyIdx);
1813 unsigned NextDef = LR->end;
1814 TurnCopiesFromValNoToImpDefs(*ResDstInt, ImpVal);
1815 ResDstInt->removeValNo(ImpVal);
1816 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1817 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1818 // Special case: vr1024 = implicit_def
1819 // vr1024 = insert_subreg vr1024, vr1025, c
1820 // The insert_subreg becomes a "copy" that defines a val# which can itself
1821 // be coalesced away.
1822 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1823 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1824 LR->valno->copy = DefMI;
1828 // If resulting interval has a preference that no longer fits because of subreg
1829 // coalescing, just clear the preference.
1830 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1831 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1832 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1833 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1834 if (!RC->contains(Preference))
1835 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1838 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1845 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1846 /// compute what the resultant value numbers for each value in the input two
1847 /// ranges will be. This is complicated by copies between the two which can
1848 /// and will commonly cause multiple value numbers to be merged into one.
1850 /// VN is the value number that we're trying to resolve. InstDefiningValue
1851 /// keeps track of the new InstDefiningValue assignment for the result
1852 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1853 /// whether a value in this or other is a copy from the opposite set.
1854 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1855 /// already been assigned.
1857 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1858 /// contains the value number the copy is from.
1860 static unsigned ComputeUltimateVN(VNInfo *VNI,
1861 SmallVector<VNInfo*, 16> &NewVNInfo,
1862 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1863 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1864 SmallVector<int, 16> &ThisValNoAssignments,
1865 SmallVector<int, 16> &OtherValNoAssignments) {
1866 unsigned VN = VNI->id;
1868 // If the VN has already been computed, just return it.
1869 if (ThisValNoAssignments[VN] >= 0)
1870 return ThisValNoAssignments[VN];
1871 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1873 // If this val is not a copy from the other val, then it must be a new value
1874 // number in the destination.
1875 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1876 if (I == ThisFromOther.end()) {
1877 NewVNInfo.push_back(VNI);
1878 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1880 VNInfo *OtherValNo = I->second;
1882 // Otherwise, this *is* a copy from the RHS. If the other side has already
1883 // been computed, return it.
1884 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1885 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1887 // Mark this value number as currently being computed, then ask what the
1888 // ultimate value # of the other value is.
1889 ThisValNoAssignments[VN] = -2;
1890 unsigned UltimateVN =
1891 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1892 OtherValNoAssignments, ThisValNoAssignments);
1893 return ThisValNoAssignments[VN] = UltimateVN;
1896 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1897 return std::find(V.begin(), V.end(), Val) != V.end();
1900 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1901 /// the specified live interval is defined by a copy from the specified
1903 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1906 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1909 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1910 if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) &&
1911 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1912 *tri_->getSuperRegisters(li.reg)) {
1913 // It's a sub-register live interval, we may not have precise information.
1915 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1916 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1918 tii_->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1919 DstReg == li.reg && SrcReg == Reg) {
1920 // Cache computed info.
1921 LR->valno->def = LR->start;
1922 LR->valno->copy = DefMI;
1929 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1930 /// caller of this method must guarantee that the RHS only contains a single
1931 /// value number and that the RHS is not defined by a copy from this
1932 /// interval. This returns false if the intervals are not joinable, or it
1933 /// joins them and returns true.
1934 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1935 assert(RHS.containsOneValue());
1937 // Some number (potentially more than one) value numbers in the current
1938 // interval may be defined as copies from the RHS. Scan the overlapping
1939 // portions of the LHS and RHS, keeping track of this and looking for
1940 // overlapping live ranges that are NOT defined as copies. If these exist, we
1943 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1944 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1946 if (LHSIt->start < RHSIt->start) {
1947 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1948 if (LHSIt != LHS.begin()) --LHSIt;
1949 } else if (RHSIt->start < LHSIt->start) {
1950 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1951 if (RHSIt != RHS.begin()) --RHSIt;
1954 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1957 // Determine if these live intervals overlap.
1958 bool Overlaps = false;
1959 if (LHSIt->start <= RHSIt->start)
1960 Overlaps = LHSIt->end > RHSIt->start;
1962 Overlaps = RHSIt->end > LHSIt->start;
1964 // If the live intervals overlap, there are two interesting cases: if the
1965 // LHS interval is defined by a copy from the RHS, it's ok and we record
1966 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1967 // coalesce these live ranges and we bail out.
1969 // If we haven't already recorded that this value # is safe, check it.
1970 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1971 // Copy from the RHS?
1972 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1973 return false; // Nope, bail out.
1975 if (LHSIt->contains(RHSIt->valno->def))
1976 // Here is an interesting situation:
1978 // vr1025 = copy vr1024
1983 // Even though vr1025 is copied from vr1024, it's not safe to
1984 // coalesce them since the live range of vr1025 intersects the
1985 // def of vr1024. This happens because vr1025 is assigned the
1986 // value of the previous iteration of vr1024.
1988 EliminatedLHSVals.push_back(LHSIt->valno);
1991 // We know this entire LHS live range is okay, so skip it now.
1992 if (++LHSIt == LHSEnd) break;
1996 if (LHSIt->end < RHSIt->end) {
1997 if (++LHSIt == LHSEnd) break;
1999 // One interesting case to check here. It's possible that we have
2000 // something like "X3 = Y" which defines a new value number in the LHS,
2001 // and is the last use of this liverange of the RHS. In this case, we
2002 // want to notice this copy (so that it gets coalesced away) even though
2003 // the live ranges don't actually overlap.
2004 if (LHSIt->start == RHSIt->end) {
2005 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
2006 // We already know that this value number is going to be merged in
2007 // if coalescing succeeds. Just skip the liverange.
2008 if (++LHSIt == LHSEnd) break;
2010 // Otherwise, if this is a copy from the RHS, mark it as being merged
2012 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
2013 if (LHSIt->contains(RHSIt->valno->def))
2014 // Here is an interesting situation:
2016 // vr1025 = copy vr1024
2021 // Even though vr1025 is copied from vr1024, it's not safe to
2022 // coalesced them since live range of vr1025 intersects the
2023 // def of vr1024. This happens because vr1025 is assigned the
2024 // value of the previous iteration of vr1024.
2026 EliminatedLHSVals.push_back(LHSIt->valno);
2028 // We know this entire LHS live range is okay, so skip it now.
2029 if (++LHSIt == LHSEnd) break;
2034 if (++RHSIt == RHSEnd) break;
2038 // If we got here, we know that the coalescing will be successful and that
2039 // the value numbers in EliminatedLHSVals will all be merged together. Since
2040 // the most common case is that EliminatedLHSVals has a single number, we
2041 // optimize for it: if there is more than one value, we merge them all into
2042 // the lowest numbered one, then handle the interval as if we were merging
2043 // with one value number.
2044 VNInfo *LHSValNo = NULL;
2045 if (EliminatedLHSVals.size() > 1) {
2046 // Loop through all the equal value numbers merging them into the smallest
2048 VNInfo *Smallest = EliminatedLHSVals[0];
2049 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
2050 if (EliminatedLHSVals[i]->id < Smallest->id) {
2051 // Merge the current notion of the smallest into the smaller one.
2052 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
2053 Smallest = EliminatedLHSVals[i];
2055 // Merge into the smallest.
2056 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
2059 LHSValNo = Smallest;
2060 } else if (EliminatedLHSVals.empty()) {
2061 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2062 *tri_->getSuperRegisters(LHS.reg))
2063 // Imprecise sub-register information. Can't handle it.
2065 llvm_unreachable("No copies from the RHS?");
2067 LHSValNo = EliminatedLHSVals[0];
2070 // Okay, now that there is a single LHS value number that we're merging the
2071 // RHS into, update the value number info for the LHS to indicate that the
2072 // value number is defined where the RHS value number was.
2073 const VNInfo *VNI = RHS.getValNumInfo(0);
2074 LHSValNo->def = VNI->def;
2075 LHSValNo->copy = VNI->copy;
2077 // Okay, the final step is to loop over the RHS live intervals, adding them to
2079 if (VNI->hasPHIKill())
2080 LHSValNo->setHasPHIKill(true);
2081 LHS.addKills(LHSValNo, VNI->kills);
2082 LHS.MergeRangesInAsValue(RHS, LHSValNo);
2083 LHS.weight += RHS.weight;
2085 // Update regalloc hint if both are virtual registers.
2086 if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
2087 TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
2088 std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
2089 std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
2090 if (RHSPref != LHSPref)
2091 mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second);
2094 // Update the liveintervals of sub-registers.
2095 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
2096 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
2097 li_->getOrCreateInterval(*AS).MergeInClobberRanges(LHS,
2098 li_->getVNInfoAllocator());
2103 /// JoinIntervals - Attempt to join these two intervals. On failure, this
2104 /// returns false. Otherwise, if one of the intervals being joined is a
2105 /// physreg, this method always canonicalizes LHS to be it. The output
2106 /// "RHS" will not have been modified, so we can use this information
2107 /// below to update aliases.
2109 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
2111 // Compute the final value assignment, assuming that the live ranges can be
2113 SmallVector<int, 16> LHSValNoAssignments;
2114 SmallVector<int, 16> RHSValNoAssignments;
2115 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
2116 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
2117 SmallVector<VNInfo*, 16> NewVNInfo;
2119 // If a live interval is a physical register, conservatively check if any
2120 // of its sub-registers is overlapping the live interval of the virtual
2121 // register. If so, do not coalesce.
2122 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2123 *tri_->getSubRegisters(LHS.reg)) {
2124 // If it's coalescing a virtual register to a physical register, estimate
2125 // its live interval length. This is the *cost* of scanning an entire live
2126 // interval. If the cost is low, we'll do an exhaustive check instead.
2128 // If this is something like this:
2136 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
2137 // less conservative check. It's possible a sub-register is defined before
2138 // v1024 (or live in) and live out of BB1.
2139 if (RHS.containsOneValue() &&
2140 li_->intervalIsInOneMBB(RHS) &&
2141 li_->getApproximateInstructionCount(RHS) <= 10) {
2142 // Perform a more exhaustive check for some common cases.
2143 if (li_->conflictsWithPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
2146 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
2147 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
2148 DOUT << "Interfere with sub-register ";
2149 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
2153 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
2154 *tri_->getSubRegisters(RHS.reg)) {
2155 if (LHS.containsOneValue() &&
2156 li_->getApproximateInstructionCount(LHS) <= 10) {
2157 // Perform a more exhaustive check for some common cases.
2158 if (li_->conflictsWithPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
2161 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
2162 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
2163 DOUT << "Interfere with sub-register ";
2164 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
2170 // Compute ultimate value numbers for the LHS and RHS values.
2171 if (RHS.containsOneValue()) {
2172 // Copies from a liveinterval with a single value are simple to handle and
2173 // very common, handle the special case here. This is important, because
2174 // often RHS is small and LHS is large (e.g. a physreg).
2176 // Find out if the RHS is defined as a copy from some value in the LHS.
2177 int RHSVal0DefinedFromLHS = -1;
2179 VNInfo *RHSValNoInfo = NULL;
2180 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
2181 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
2182 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
2183 // If RHS is not defined as a copy from the LHS, we can use simpler and
2184 // faster checks to see if the live ranges are coalescable. This joiner
2185 // can't swap the LHS/RHS intervals though.
2186 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2187 return SimpleJoin(LHS, RHS);
2189 RHSValNoInfo = RHSValNoInfo0;
2192 // It was defined as a copy from the LHS, find out what value # it is.
2193 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
2194 RHSValID = RHSValNoInfo->id;
2195 RHSVal0DefinedFromLHS = RHSValID;
2198 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2199 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2200 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2202 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2203 // should now get updated.
2204 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2207 unsigned VN = VNI->id;
2208 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2209 if (LHSSrcReg != RHS.reg) {
2210 // If this is not a copy from the RHS, its value number will be
2211 // unmodified by the coalescing.
2212 NewVNInfo[VN] = VNI;
2213 LHSValNoAssignments[VN] = VN;
2214 } else if (RHSValID == -1) {
2215 // Otherwise, it is a copy from the RHS, and we don't already have a
2216 // value# for it. Keep the current value number, but remember it.
2217 LHSValNoAssignments[VN] = RHSValID = VN;
2218 NewVNInfo[VN] = RHSValNoInfo;
2219 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2221 // Otherwise, use the specified value #.
2222 LHSValNoAssignments[VN] = RHSValID;
2223 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2224 NewVNInfo[VN] = RHSValNoInfo;
2225 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2229 NewVNInfo[VN] = VNI;
2230 LHSValNoAssignments[VN] = VN;
2234 assert(RHSValID != -1 && "Didn't find value #?");
2235 RHSValNoAssignments[0] = RHSValID;
2236 if (RHSVal0DefinedFromLHS != -1) {
2237 // This path doesn't go through ComputeUltimateVN so just set
2239 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2242 // Loop over the value numbers of the LHS, seeing if any are defined from
2244 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2247 if (VNI->isUnused() || VNI->copy == 0) // Src not defined by a copy?
2250 // DstReg is known to be a register in the LHS interval. If the src is
2251 // from the RHS interval, we can use its value #.
2252 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2255 // Figure out the value # from the RHS.
2256 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
2259 // Loop over the value numbers of the RHS, seeing if any are defined from
2261 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2264 if (VNI->isUnused() || VNI->copy == 0) // Src not defined by a copy?
2267 // DstReg is known to be a register in the RHS interval. If the src is
2268 // from the LHS interval, we can use its value #.
2269 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2272 // Figure out the value # from the LHS.
2273 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
2276 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2277 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2278 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2280 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2283 unsigned VN = VNI->id;
2284 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2286 ComputeUltimateVN(VNI, NewVNInfo,
2287 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2288 LHSValNoAssignments, RHSValNoAssignments);
2290 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2293 unsigned VN = VNI->id;
2294 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2296 // If this value number isn't a copy from the LHS, it's a new number.
2297 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2298 NewVNInfo.push_back(VNI);
2299 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2303 ComputeUltimateVN(VNI, NewVNInfo,
2304 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2305 RHSValNoAssignments, LHSValNoAssignments);
2309 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2310 // interval lists to see if these intervals are coalescable.
2311 LiveInterval::const_iterator I = LHS.begin();
2312 LiveInterval::const_iterator IE = LHS.end();
2313 LiveInterval::const_iterator J = RHS.begin();
2314 LiveInterval::const_iterator JE = RHS.end();
2316 // Skip ahead until the first place of potential sharing.
2317 if (I->start < J->start) {
2318 I = std::upper_bound(I, IE, J->start);
2319 if (I != LHS.begin()) --I;
2320 } else if (J->start < I->start) {
2321 J = std::upper_bound(J, JE, I->start);
2322 if (J != RHS.begin()) --J;
2326 // Determine if these two live ranges overlap.
2328 if (I->start < J->start) {
2329 Overlaps = I->end > J->start;
2331 Overlaps = J->end > I->start;
2334 // If so, check value # info to determine if they are really different.
2336 // If the live range overlap will map to the same value number in the
2337 // result liverange, we can still coalesce them. If not, we can't.
2338 if (LHSValNoAssignments[I->valno->id] !=
2339 RHSValNoAssignments[J->valno->id])
2343 if (I->end < J->end) {
2352 // Update kill info. Some live ranges are extended due to copy coalescing.
2353 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2354 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2355 VNInfo *VNI = I->first;
2356 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2357 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
2358 if (VNI->hasPHIKill())
2359 NewVNInfo[LHSValID]->setHasPHIKill(true);
2360 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2363 // Update kill info. Some live ranges are extended due to copy coalescing.
2364 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2365 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2366 VNInfo *VNI = I->first;
2367 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2368 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
2369 if (VNI->hasPHIKill())
2370 NewVNInfo[RHSValID]->setHasPHIKill(true);
2371 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2374 // If we get here, we know that we can coalesce the live ranges. Ask the
2375 // intervals to coalesce themselves now.
2376 if ((RHS.ranges.size() > LHS.ranges.size() &&
2377 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2378 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2379 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2383 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2391 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2392 // depth of the basic block (the unsigned), and then on the MBB number.
2393 struct DepthMBBCompare {
2394 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2395 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2396 if (LHS.first > RHS.first) return true; // Deeper loops first
2397 return LHS.first == RHS.first &&
2398 LHS.second->getNumber() < RHS.second->getNumber();
2403 /// getRepIntervalSize - Returns the size of the interval that represents the
2404 /// specified register.
2406 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
2407 return Rc->getRepIntervalSize(Reg);
2410 /// CopyRecSort::operator - Join priority queue sorting function.
2412 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
2413 // Inner loops first.
2414 if (left.LoopDepth > right.LoopDepth)
2416 else if (left.LoopDepth == right.LoopDepth)
2417 if (left.isBackEdge && !right.isBackEdge)
2422 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2423 std::vector<CopyRec> &TryAgain) {
2424 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
2426 std::vector<CopyRec> VirtCopies;
2427 std::vector<CopyRec> PhysCopies;
2428 std::vector<CopyRec> ImpDefCopies;
2429 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
2430 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2432 MachineInstr *Inst = MII++;
2434 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2435 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2436 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
2437 DstReg = Inst->getOperand(0).getReg();
2438 SrcReg = Inst->getOperand(1).getReg();
2439 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2440 Inst->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
2441 DstReg = Inst->getOperand(0).getReg();
2442 SrcReg = Inst->getOperand(2).getReg();
2443 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2446 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2447 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2449 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
2451 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
2452 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
2453 else if (SrcIsPhys || DstIsPhys)
2454 PhysCopies.push_back(CopyRec(Inst, 0, false));
2456 VirtCopies.push_back(CopyRec(Inst, 0, false));
2463 // Try coalescing implicit copies first, followed by copies to / from
2464 // physical registers, then finally copies from virtual registers to
2465 // virtual registers.
2466 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2467 CopyRec &TheCopy = ImpDefCopies[i];
2469 if (!JoinCopy(TheCopy, Again))
2471 TryAgain.push_back(TheCopy);
2473 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2474 CopyRec &TheCopy = PhysCopies[i];
2476 if (!JoinCopy(TheCopy, Again))
2478 TryAgain.push_back(TheCopy);
2480 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2481 CopyRec &TheCopy = VirtCopies[i];
2483 if (!JoinCopy(TheCopy, Again))
2485 TryAgain.push_back(TheCopy);
2489 void SimpleRegisterCoalescing::joinIntervals() {
2490 DOUT << "********** JOINING INTERVALS ***********\n";
2493 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
2495 std::vector<CopyRec> TryAgainList;
2496 if (loopInfo->empty()) {
2497 // If there are no loops in the function, join intervals in function order.
2498 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2500 CopyCoalesceInMBB(I, TryAgainList);
2502 // Otherwise, join intervals in inner loops before other intervals.
2503 // Unfortunately we can't just iterate over loop hierarchy here because
2504 // there may be more MBB's than BB's. Collect MBB's for sorting.
2506 // Join intervals in the function prolog first. We want to join physical
2507 // registers with virtual registers before the intervals got too long.
2508 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2509 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2510 MachineBasicBlock *MBB = I;
2511 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2514 // Sort by loop depth.
2515 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2517 // Finally, join intervals in loop nest order.
2518 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2519 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2522 // Joining intervals can allow other intervals to be joined. Iteratively join
2523 // until we make no progress.
2525 SmallVector<CopyRec, 16> TryAgain;
2526 bool ProgressMade = true;
2527 while (ProgressMade) {
2528 ProgressMade = false;
2529 while (!JoinQueue->empty()) {
2530 CopyRec R = JoinQueue->pop();
2532 bool Success = JoinCopy(R, Again);
2534 ProgressMade = true;
2536 TryAgain.push_back(R);
2540 while (!TryAgain.empty()) {
2541 JoinQueue->push(TryAgain.back());
2542 TryAgain.pop_back();
2547 bool ProgressMade = true;
2548 while (ProgressMade) {
2549 ProgressMade = false;
2551 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2552 CopyRec &TheCopy = TryAgainList[i];
2555 bool Success = JoinCopy(TheCopy, Again);
2556 if (Success || !Again) {
2557 TheCopy.MI = 0; // Mark this one as done.
2558 ProgressMade = true;
2569 /// Return true if the two specified registers belong to different register
2570 /// classes. The registers may be either phys or virt regs.
2572 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2573 unsigned RegB) const {
2574 // Get the register classes for the first reg.
2575 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2576 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2577 "Shouldn't consider two physregs!");
2578 return !mri_->getRegClass(RegB)->contains(RegA);
2581 // Compare against the regclass for the second reg.
2582 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2583 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2584 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2585 return RegClassA != RegClassB;
2587 return !RegClassA->contains(RegB);
2590 /// lastRegisterUse - Returns the last use of the specific register between
2591 /// cycles Start and End or NULL if there are no uses.
2593 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2594 unsigned Reg, unsigned &UseIdx) const{
2596 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2597 MachineOperand *LastUse = NULL;
2598 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2599 E = mri_->use_end(); I != E; ++I) {
2600 MachineOperand &Use = I.getOperand();
2601 MachineInstr *UseMI = Use.getParent();
2602 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2603 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2605 // Ignore identity copies.
2607 unsigned Idx = li_->getInstructionIndex(UseMI);
2608 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2610 UseIdx = li_->getUseIndex(Idx);
2616 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2619 // Skip deleted instructions
2620 MachineInstr *MI = li_->getInstructionFromIndex(e);
2621 while ((e - InstrSlots::NUM) >= s && !MI) {
2622 e -= InstrSlots::NUM;
2623 MI = li_->getInstructionFromIndex(e);
2625 if (e < s || MI == NULL)
2628 // Ignore identity copies.
2629 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2630 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2632 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2633 MachineOperand &Use = MI->getOperand(i);
2634 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2635 tri_->regsOverlap(Use.getReg(), Reg)) {
2636 UseIdx = li_->getUseIndex(e);
2641 e -= InstrSlots::NUM;
2648 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2649 if (TargetRegisterInfo::isPhysicalRegister(reg))
2650 cerr << tri_->getName(reg);
2652 cerr << "%reg" << reg;
2655 void SimpleRegisterCoalescing::releaseMemory() {
2656 JoinedCopies.clear();
2657 ReMatCopies.clear();
2661 static bool isZeroLengthInterval(LiveInterval *li) {
2662 for (LiveInterval::Ranges::const_iterator
2663 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2664 if (i->end - i->start > LiveInterval::InstrSlots::NUM)
2669 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
2670 /// turn the copy into an implicit def.
2672 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
2673 MachineBasicBlock *MBB,
2674 unsigned DstReg, unsigned SrcReg) {
2675 MachineInstr *CopyMI = &*I;
2676 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
2677 if (!li_->hasInterval(SrcReg))
2679 LiveInterval &SrcInt = li_->getInterval(SrcReg);
2680 if (!SrcInt.empty())
2682 if (!li_->hasInterval(DstReg))
2684 LiveInterval &DstInt = li_->getInterval(DstReg);
2685 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
2686 // If the valno extends beyond this basic block, then it's not safe to delete
2687 // the val# or else livein information won't be correct.
2688 MachineBasicBlock *EndMBB = li_->getMBBFromIndex(DstLR->end);
2691 DstInt.removeValNo(DstLR->valno);
2692 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
2693 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
2694 CopyMI->RemoveOperand(i);
2695 CopyMI->getOperand(0).setIsUndef();
2696 bool NoUse = mri_->use_empty(SrcReg);
2698 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
2699 RE = mri_->reg_end(); RI != RE; ) {
2700 assert(RI.getOperand().isDef());
2701 MachineInstr *DefMI = &*RI;
2703 // The implicit_def source has no other uses, delete it.
2704 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2705 li_->RemoveMachineInstrFromMaps(DefMI);
2706 DefMI->eraseFromParent();
2710 // Mark uses of implicit_def isUndef.
2711 for (MachineRegisterInfo::use_iterator RI = mri_->use_begin(DstReg),
2712 RE = mri_->use_end(); RI != RE; ++RI) {
2713 assert((*RI).getParent() == MBB);
2714 RI.getOperand().setIsUndef();
2722 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2724 mri_ = &fn.getRegInfo();
2725 tm_ = &fn.getTarget();
2726 tri_ = tm_->getRegisterInfo();
2727 tii_ = tm_->getInstrInfo();
2728 li_ = &getAnalysis<LiveIntervals>();
2729 loopInfo = &getAnalysis<MachineLoopInfo>();
2731 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2732 << "********** Function: "
2733 << ((Value*)mf_->getFunction())->getName() << '\n';
2735 allocatableRegs_ = tri_->getAllocatableSet(fn);
2736 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2737 E = tri_->regclass_end(); I != E; ++I)
2738 allocatableRCRegs_.insert(std::make_pair(*I,
2739 tri_->getAllocatableSet(fn, *I)));
2741 // Join (coalesce) intervals if requested.
2742 if (EnableJoining) {
2745 DOUT << "********** INTERVALS POST JOINING **********\n";
2746 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2747 I->second->print(DOUT, tri_);
2753 // Perform a final pass over the instructions and compute spill weights
2754 // and remove identity moves.
2755 SmallVector<unsigned, 4> DeadDefs;
2756 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2757 mbbi != mbbe; ++mbbi) {
2758 MachineBasicBlock* mbb = mbbi;
2759 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2761 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2763 MachineInstr *MI = mii;
2764 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2765 if (JoinedCopies.count(MI)) {
2766 // Delete all coalesced copies.
2767 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2768 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2769 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2770 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
2771 "Unrecognized copy instruction");
2772 DstReg = MI->getOperand(0).getReg();
2774 if (MI->registerDefIsDead(DstReg)) {
2775 LiveInterval &li = li_->getInterval(DstReg);
2776 if (!ShortenDeadCopySrcLiveRange(li, MI))
2777 ShortenDeadCopyLiveRange(li, MI);
2779 li_->RemoveMachineInstrFromMaps(MI);
2780 mii = mbbi->erase(mii);
2785 // Now check if this is a remat'ed def instruction which is now dead.
2786 if (ReMatDefs.count(MI)) {
2788 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2789 const MachineOperand &MO = MI->getOperand(i);
2792 unsigned Reg = MO.getReg();
2795 if (TargetRegisterInfo::isVirtualRegister(Reg))
2796 DeadDefs.push_back(Reg);
2799 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2800 !mri_->use_empty(Reg)) {
2806 while (!DeadDefs.empty()) {
2807 unsigned DeadDef = DeadDefs.back();
2808 DeadDefs.pop_back();
2809 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2811 li_->RemoveMachineInstrFromMaps(mii);
2812 mii = mbbi->erase(mii);
2818 // If the move will be an identity move delete it
2819 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2820 if (isMove && SrcReg == DstReg) {
2821 if (li_->hasInterval(SrcReg)) {
2822 LiveInterval &RegInt = li_->getInterval(SrcReg);
2823 // If def of this move instruction is dead, remove its live range
2824 // from the dstination register's live interval.
2825 if (MI->registerDefIsDead(DstReg)) {
2826 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2827 ShortenDeadCopyLiveRange(RegInt, MI);
2830 li_->RemoveMachineInstrFromMaps(MI);
2831 mii = mbbi->erase(mii);
2833 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2834 SmallSet<unsigned, 4> UniqueUses;
2835 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2836 const MachineOperand &mop = MI->getOperand(i);
2837 if (mop.isReg() && mop.getReg() &&
2838 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2839 unsigned reg = mop.getReg();
2840 // Multiple uses of reg by the same instruction. It should not
2841 // contribute to spill weight again.
2842 if (UniqueUses.count(reg) != 0)
2844 LiveInterval &RegInt = li_->getInterval(reg);
2846 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2847 UniqueUses.insert(reg);
2855 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2856 LiveInterval &LI = *I->second;
2857 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2858 // If the live interval length is essentially zero, i.e. in every live
2859 // range the use follows def immediately, it doesn't make sense to spill
2860 // it and hope it will be easier to allocate for this li.
2861 if (isZeroLengthInterval(&LI))
2862 LI.weight = HUGE_VALF;
2864 bool isLoad = false;
2865 SmallVector<LiveInterval*, 4> SpillIs;
2866 if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
2867 // If all of the definitions of the interval are re-materializable,
2868 // it is a preferred candidate for spilling. If non of the defs are
2869 // loads, then it's potentially very cheap to re-materialize.
2870 // FIXME: this gets much more complicated once we support non-trivial
2871 // re-materialization.
2879 // Slightly prefer live interval that has been assigned a preferred reg.
2880 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(LI.reg);
2881 if (Hint.first || Hint.second)
2884 // Divide the weight of the interval by its size. This encourages
2885 // spilling of intervals that are large and have few uses, and
2886 // discourages spilling of small intervals with many uses.
2887 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2895 /// print - Implement the dump method.
2896 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2900 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2901 return new SimpleRegisterCoalescing();
2904 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2905 DEFINING_FILE_FOR(SimpleRegisterCoalescing)