1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/ADT/STLExtras.h"
37 STATISTIC(numJoins , "Number of interval joins performed");
38 STATISTIC(numCommutes , "Number of instruction commuting performed");
39 STATISTIC(numExtends , "Number of copies extended");
40 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
41 STATISTIC(numAborts , "Number of times interval joining aborted");
43 char SimpleRegisterCoalescing::ID = 0;
45 EnableJoining("join-liveintervals",
46 cl::desc("Coalesce copies (default=true)"),
50 NewHeuristic("new-coalescer-heuristic",
51 cl::desc("Use new coalescer heuristic"),
54 static RegisterPass<SimpleRegisterCoalescing>
55 X("simple-register-coalescing", "Simple Register Coalescing");
57 // Declare that we implement the RegisterCoalescer interface
58 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
60 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
62 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addPreserved<LiveIntervals>();
64 AU.addPreserved<MachineLoopInfo>();
65 AU.addPreservedID(MachineDominatorsID);
66 AU.addPreservedID(PHIEliminationID);
67 AU.addPreservedID(TwoAddressInstructionPassID);
68 AU.addRequired<LiveIntervals>();
69 AU.addRequired<MachineLoopInfo>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
74 /// being the source and IntB being the dest, thus this defines a value number
75 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
76 /// see if we can merge these two pieces of B into a single value number,
77 /// eliminating a copy. For example:
81 /// B1 = A3 <- this copy
83 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
84 /// value number to be replaced with B0 (which simplifies the B liveinterval).
86 /// This returns true if an interval was modified.
88 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
90 MachineInstr *CopyMI) {
91 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
93 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
95 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
96 if (BLR == IntB.end()) // Should never happen!
98 VNInfo *BValNo = BLR->valno;
100 // Get the location that B is defined at. Two options: either this value has
101 // an unknown definition point or it is defined at CopyIdx. If unknown, we
103 if (!BValNo->copy) return false;
104 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
106 // AValNo is the value number in A that defines the copy, A3 in the example.
107 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
108 if (ALR == IntA.end()) // Should never happen!
110 VNInfo *AValNo = ALR->valno;
112 // If AValNo is defined as a copy from IntB, we can potentially process this.
113 // Get the instruction that defines this value number.
114 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
115 if (!SrcReg) return false; // Not defined by a copy.
117 // If the value number is not defined by a copy instruction, ignore it.
119 // If the source register comes from an interval other than IntB, we can't
121 if (SrcReg != IntB.reg) return false;
123 // Get the LiveRange in IntB that this value number starts with.
124 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
125 if (ValLR == IntB.end()) // Should never happen!
128 // Make sure that the end of the live range is inside the same block as
130 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
132 ValLREndInst->getParent() != CopyMI->getParent()) return false;
134 // Okay, we now know that ValLR ends in the same block that the CopyMI
135 // live-range starts. If there are no intervening live ranges between them in
136 // IntB, we can merge them.
137 if (ValLR+1 != BLR) return false;
139 // If a live interval is a physical register, conservatively check if any
140 // of its sub-registers is overlapping the live interval of the virtual
141 // register. If so, do not coalesce.
142 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
143 *tri_->getSubRegisters(IntB.reg)) {
144 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
145 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
146 DOUT << "Interfere with sub-register ";
147 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
152 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
154 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
155 // We are about to delete CopyMI, so need to remove it as the 'instruction
156 // that defines this value #'. Update the the valnum with the new defining
158 BValNo->def = FillerStart;
161 // Okay, we can merge them. We need to insert a new liverange:
162 // [ValLR.end, BLR.begin) of either value number, then we merge the
163 // two value numbers.
164 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
166 // If the IntB live range is assigned to a physical register, and if that
167 // physreg has aliases,
168 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
169 // Update the liveintervals of sub-registers.
170 for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
171 LiveInterval &AliasLI = li_->getInterval(*AS);
172 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
173 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
177 // Okay, merge "B1" into the same value number as "B0".
178 if (BValNo != ValLR->valno)
179 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
180 DOUT << " result = "; IntB.print(DOUT, tri_);
183 // If the source instruction was killing the source register before the
184 // merge, unset the isKill marker given the live range has been extended.
185 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
187 ValLREndInst->getOperand(UIdx).setIsKill(false);
193 /// HasOtherReachingDefs - Return true if there are definitions of IntB
194 /// other than BValNo val# that can reach uses of AValno val# of IntA.
195 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
199 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
201 if (AI->valno != AValNo) continue;
202 LiveInterval::Ranges::iterator BI =
203 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
204 if (BI != IntB.ranges.begin())
206 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
207 if (BI->valno == BValNo)
209 if (BI->start <= AI->start && BI->end > AI->start)
211 if (BI->start > AI->start && BI->start < AI->end)
218 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
219 /// being the source and IntB being the dest, thus this defines a value number
220 /// in IntB. If the source value number (in IntA) is defined by a commutable
221 /// instruction and its other operand is coalesced to the copy dest register,
222 /// see if we can transform the copy into a noop by commuting the definition. For
225 /// A3 = op A2 B0<kill>
227 /// B1 = A3 <- this copy
229 /// = op A3 <- more uses
233 /// B2 = op B0 A2<kill>
235 /// B1 = B2 <- now an identify copy
237 /// = op B2 <- more uses
239 /// This returns true if an interval was modified.
241 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
243 MachineInstr *CopyMI) {
244 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
246 // FIXME: For now, only eliminate the copy by commuting its def when the
247 // source register is a virtual register. We want to guard against cases
248 // where the copy is a back edge copy and commuting the def lengthen the
249 // live interval of the source register to the entire loop.
250 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
253 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
254 // the example above.
255 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
256 if (BLR == IntB.end()) // Should never happen!
258 VNInfo *BValNo = BLR->valno;
260 // Get the location that B is defined at. Two options: either this value has
261 // an unknown definition point or it is defined at CopyIdx. If unknown, we
263 if (!BValNo->copy) return false;
264 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
266 // AValNo is the value number in A that defines the copy, A3 in the example.
267 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
268 if (ALR == IntA.end()) // Should never happen!
270 VNInfo *AValNo = ALR->valno;
271 // If other defs can reach uses of this def, then it's not safe to perform
273 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
275 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
276 const TargetInstrDesc &TID = DefMI->getDesc();
278 if (!TID.isCommutable() ||
279 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
282 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
283 unsigned NewReg = NewDstMO.getReg();
284 if (NewReg != IntB.reg || !NewDstMO.isKill())
287 // Make sure there are no other definitions of IntB that would reach the
288 // uses which the new definition can reach.
289 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
292 // If some of the uses of IntA.reg is already coalesced away, return false.
293 // It's not possible to determine whether it's safe to perform the coalescing.
294 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
295 UE = mri_->use_end(); UI != UE; ++UI) {
296 MachineInstr *UseMI = &*UI;
297 unsigned UseIdx = li_->getInstructionIndex(UseMI);
298 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
299 if (ULR == IntA.end())
301 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
305 // At this point we have decided that it is legal to do this
306 // transformation. Start by commuting the instruction.
307 MachineBasicBlock *MBB = DefMI->getParent();
308 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
311 if (NewMI != DefMI) {
312 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
313 MBB->insert(DefMI, NewMI);
316 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
317 NewMI->getOperand(OpIdx).setIsKill();
319 bool BHasPHIKill = BValNo->hasPHIKill;
320 SmallVector<VNInfo*, 4> BDeadValNos;
321 SmallVector<unsigned, 4> BKills;
322 std::map<unsigned, unsigned> BExtend;
324 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
333 // then do not add kills of A to the newly created B interval.
334 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
336 BExtend[ALR->end] = BLR->end;
338 // Update uses of IntA of the specific Val# with IntB.
339 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
340 UE = mri_->use_end(); UI != UE;) {
341 MachineOperand &UseMO = UI.getOperand();
342 MachineInstr *UseMI = &*UI;
344 if (JoinedCopies.count(UseMI))
346 unsigned UseIdx = li_->getInstructionIndex(UseMI);
347 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
348 if (ULR == IntA.end() || ULR->valno != AValNo)
350 UseMO.setReg(NewReg);
353 if (UseMO.isKill()) {
355 UseMO.setIsKill(false);
357 BKills.push_back(li_->getUseIndex(UseIdx)+1);
359 unsigned SrcReg, DstReg;
360 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
362 if (DstReg == IntB.reg) {
363 // This copy will become a noop. If it's defining a new val#,
364 // remove that val# as well. However this live range is being
365 // extended to the end of the existing live range defined by the copy.
366 unsigned DefIdx = li_->getDefIndex(UseIdx);
367 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
368 BHasPHIKill |= DLR->valno->hasPHIKill;
369 assert(DLR->valno->def == DefIdx);
370 BDeadValNos.push_back(DLR->valno);
371 BExtend[DLR->start] = DLR->end;
372 JoinedCopies.insert(UseMI);
373 // If this is a kill but it's going to be removed, the last use
374 // of the same val# is the new kill.
380 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
381 // simply extend BLR if CopyMI doesn't end the range.
382 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
384 // Remove val#'s defined by copies that will be coalesced away.
385 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
386 IntB.removeValNo(BDeadValNos[i]);
388 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
389 // is updated. Kills are also updated.
390 VNInfo *ValNo = BValNo;
391 ValNo->def = AValNo->def;
393 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
394 unsigned Kill = ValNo->kills[j];
395 if (Kill != BLR->end)
396 BKills.push_back(Kill);
398 ValNo->kills.clear();
399 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
401 if (AI->valno != AValNo) continue;
402 unsigned End = AI->end;
403 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
404 if (EI != BExtend.end())
406 IntB.addRange(LiveRange(AI->start, End, ValNo));
408 IntB.addKills(ValNo, BKills);
409 ValNo->hasPHIKill = BHasPHIKill;
411 DOUT << " result = "; IntB.print(DOUT, tri_);
414 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
415 IntA.removeValNo(AValNo);
416 DOUT << " result = "; IntA.print(DOUT, tri_);
423 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
425 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
426 unsigned DstReg) const {
427 MachineBasicBlock *MBB = CopyMI->getParent();
428 const MachineLoop *L = loopInfo->getLoopFor(MBB);
431 if (MBB != L->getLoopLatch())
434 LiveInterval &LI = li_->getInterval(DstReg);
435 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
436 LiveInterval::const_iterator DstLR =
437 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
438 if (DstLR == LI.end())
440 unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM;
441 if (DstLR->valno->kills.size() == 1 &&
442 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
447 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
448 /// update the subregister number if it is not zero. If DstReg is a
449 /// physical register and the existing subregister number of the def / use
450 /// being updated is not zero, make sure to set it to the correct physical
453 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
455 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
456 if (DstIsPhys && SubIdx) {
457 // Figure out the real physical register we are updating with.
458 DstReg = tri_->getSubReg(DstReg, SubIdx);
462 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
463 E = mri_->reg_end(); I != E; ) {
464 MachineOperand &O = I.getOperand();
465 MachineInstr *UseMI = &*I;
467 unsigned OldSubIdx = O.getSubReg();
469 unsigned UseDstReg = DstReg;
471 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
475 // Sub-register indexes goes from small to large. e.g.
476 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
477 // EAX: 1 -> AL, 2 -> AX
478 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
479 // sub-register 2 is also AX.
480 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
481 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
484 // Remove would-be duplicated kill marker.
485 if (O.isKill() && UseMI->killsRegister(DstReg))
492 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
493 /// registers due to insert_subreg coalescing. e.g.
495 /// r1025 = implicit_def
496 /// r1025 = insert_subreg r1025, r1024
500 /// r1025 = implicit_def
501 /// r1025 = insert_subreg r1025, r1025
504 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
505 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
506 E = mri_->reg_end(); I != E; ) {
507 MachineOperand &O = I.getOperand();
508 MachineInstr *DefMI = &*I;
512 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
514 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
516 li_->RemoveMachineInstrFromMaps(DefMI);
517 DefMI->eraseFromParent();
521 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
522 /// due to live range lengthening as the result of coalescing.
523 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
525 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
526 UE = mri_->use_end(); UI != UE; ++UI) {
527 MachineOperand &UseMO = UI.getOperand();
528 if (UseMO.isKill()) {
529 MachineInstr *UseMI = UseMO.getParent();
531 if (!tii_->isMoveInstr(*UseMI, SReg, DReg))
533 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
534 if (JoinedCopies.count(UseMI))
536 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
537 if (!LI.isKill(UI->valno, UseIdx+1))
538 UseMO.setIsKill(false);
543 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
544 /// from a physical register live interval as well as from the live intervals
545 /// of its sub-registers.
546 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
547 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
548 li.removeRange(Start, End, true);
549 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
550 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
551 if (!li_->hasInterval(*SR))
553 LiveInterval &sli = li_->getInterval(*SR);
554 unsigned RemoveEnd = Start;
555 while (RemoveEnd != End) {
556 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
559 RemoveEnd = (LR->end < End) ? LR->end : End;
560 sli.removeRange(Start, RemoveEnd, true);
567 /// removeIntervalIfEmpty - Check if the live interval of a physical register
568 /// is empty, if so remove it and also remove the empty intervals of its
569 /// sub-registers. Return true if live interval is removed.
570 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
571 const TargetRegisterInfo *tri_) {
573 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
574 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
575 if (!li_->hasInterval(*SR))
577 LiveInterval &sli = li_->getInterval(*SR);
579 li_->removeInterval(*SR);
581 li_->removeInterval(li.reg);
587 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
588 /// Return true if live interval is removed.
589 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
590 MachineInstr *CopyMI) {
591 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
592 LiveInterval::iterator MLR =
593 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
595 return false; // Already removed by ShortenDeadCopySrcLiveRange.
596 unsigned RemoveStart = MLR->start;
597 unsigned RemoveEnd = MLR->end;
598 // Remove the liverange that's defined by this.
599 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
600 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
601 return removeIntervalIfEmpty(li, li_, tri_);
606 /// PropagateDeadness - Propagate the dead marker to the instruction which
607 /// defines the val#.
608 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
609 unsigned &LRStart, LiveIntervals *li_,
610 const TargetRegisterInfo* tri_) {
611 MachineInstr *DefMI =
612 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
613 if (DefMI && DefMI != CopyMI) {
614 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
616 DefMI->getOperand(DeadIdx).setIsDead();
617 // A dead def should have a single cycle interval.
623 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
624 /// fallthoughs to SuccMBB.
625 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
626 MachineBasicBlock *SuccMBB,
627 const TargetInstrInfo *tii_) {
630 MachineBasicBlock *TBB = 0, *FBB = 0;
631 std::vector<MachineOperand> Cond;
632 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
633 MBB->isSuccessor(SuccMBB);
636 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
637 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
638 /// ends the live range there. If there isn't another use, then this live range
639 /// is dead. Return true if live interval is removed.
641 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
642 MachineInstr *CopyMI) {
643 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
645 // FIXME: special case: function live in. It can be a general case if the
646 // first instruction index starts at > 0 value.
647 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
648 // Live-in to the function but dead. Remove it from entry live-in set.
649 if (mf_->begin()->isLiveIn(li.reg))
650 mf_->begin()->removeLiveIn(li.reg);
651 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
652 removeRange(li, LR->start, LR->end, li_, tri_);
653 return removeIntervalIfEmpty(li, li_, tri_);
656 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
658 // Livein but defined by a phi.
661 unsigned RemoveStart = LR->start;
662 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
663 if (LR->end > RemoveEnd)
664 // More uses past this copy? Nothing to do.
667 MachineBasicBlock *CopyMBB = CopyMI->getParent();
668 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
670 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
673 MachineInstr *LastUseMI = LastUse->getParent();
674 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
681 // r1025<dead> = r1024<kill>
682 if (MBBStart < LR->end)
683 removeRange(li, MBBStart, LR->end, li_, tri_);
687 // There are uses before the copy, just shorten the live range to the end
689 LastUse->setIsKill();
690 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
691 unsigned SrcReg, DstReg;
692 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) &&
694 // Last use is itself an identity code.
695 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
696 LastUseMI->getOperand(DeadIdx).setIsDead();
702 if (LR->start <= MBBStart && LR->end > MBBStart) {
703 if (LR->start == 0) {
704 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
705 // Live-in to the function but dead. Remove it from entry live-in set.
706 mf_->begin()->removeLiveIn(li.reg);
708 // FIXME: Shorten intervals in BBs that reaches this BB.
711 if (LR->valno->def == RemoveStart)
712 // If the def MI defines the val#, propagate the dead marker.
713 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
715 removeRange(li, RemoveStart, LR->end, li_, tri_);
716 return removeIntervalIfEmpty(li, li_, tri_);
719 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
720 /// from an implicit def to another register can be coalesced away.
721 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
723 LiveInterval &ImpLi) const{
724 if (!CopyMI->killsRegister(ImpLi.reg))
726 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
727 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
730 if (LR->valno->hasPHIKill)
732 if (LR->valno->def != CopyIdx)
734 // Make sure all of val# uses are copies.
735 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
736 UE = mri_->use_end(); UI != UE;) {
737 MachineInstr *UseMI = &*UI;
739 if (JoinedCopies.count(UseMI))
741 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
742 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
743 if (ULR == li.end() || ULR->valno != LR->valno)
745 // If the use is not a use, then it's not safe to coalesce the move.
746 unsigned SrcReg, DstReg;
747 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) {
748 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
749 UseMI->getOperand(1).getReg() == li.reg)
758 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
759 /// def and it is being removed. Turn all copies from this value# into
760 /// identity copies so they will be removed.
761 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
763 SmallVector<MachineInstr*, 4> ImpDefs;
764 MachineOperand *LastUse = NULL;
765 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
766 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
767 RE = mri_->reg_end(); RI != RE;) {
768 MachineOperand *MO = &RI.getOperand();
769 MachineInstr *MI = &*RI;
772 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
773 ImpDefs.push_back(MI);
777 if (JoinedCopies.count(MI))
779 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
780 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
781 if (ULR == li.end() || ULR->valno != VNI)
783 // If the use is a copy, turn it into an identity copy.
784 unsigned SrcReg, DstReg;
785 if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) {
786 // Each use MI may have multiple uses of this register. Change them all.
787 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
788 MachineOperand &MO = MI->getOperand(i);
789 if (MO.isReg() && MO.getReg() == li.reg)
792 JoinedCopies.insert(MI);
793 } else if (UseIdx > LastUseIdx) {
799 LastUse->setIsKill();
801 // Remove dead implicit_def's.
802 while (!ImpDefs.empty()) {
803 MachineInstr *ImpDef = ImpDefs.back();
805 li_->RemoveMachineInstrFromMaps(ImpDef);
806 ImpDef->eraseFromParent();
811 static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
812 const TargetRegisterClass *RC,
813 const TargetRegisterInfo* TRI) {
814 for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
815 unsigned SR = *SRs; ++SRs)
816 if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
821 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
822 /// which are the src/dst of the copy instruction CopyMI. This returns true
823 /// if the copy was successfully coalesced away. If it is not currently
824 /// possible to coalesce this interval, but it may be possible if other
825 /// things get coalesced, then it returns true by reference in 'Again'.
826 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
827 MachineInstr *CopyMI = TheCopy.MI;
830 if (JoinedCopies.count(CopyMI))
831 return false; // Already done.
833 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
837 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
838 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
841 DstReg = CopyMI->getOperand(0).getReg();
842 SrcReg = CopyMI->getOperand(1).getReg();
843 } else if (isInsSubReg) {
844 if (CopyMI->getOperand(2).getSubReg()) {
845 DOUT << "\tSource of insert_subreg is already coalesced "
846 << "to another register.\n";
847 return false; // Not coalescable.
849 DstReg = CopyMI->getOperand(0).getReg();
850 SrcReg = CopyMI->getOperand(2).getReg();
851 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
852 assert(0 && "Unrecognized copy instruction!");
856 // If they are already joined we continue.
857 if (SrcReg == DstReg) {
858 DOUT << "\tCopy already coalesced.\n";
859 return false; // Not coalescable.
862 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
863 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
865 // If they are both physical registers, we cannot join them.
866 if (SrcIsPhys && DstIsPhys) {
867 DOUT << "\tCan not coalesce physregs.\n";
868 return false; // Not coalescable.
871 // We only join virtual registers with allocatable physical registers.
872 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
873 DOUT << "\tSrc reg is unallocatable physreg.\n";
874 return false; // Not coalescable.
876 if (DstIsPhys && !allocatableRegs_[DstReg]) {
877 DOUT << "\tDst reg is unallocatable physreg.\n";
878 return false; // Not coalescable.
881 unsigned RealDstReg = 0;
882 unsigned RealSrcReg = 0;
883 if (isExtSubReg || isInsSubReg) {
884 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
885 if (SrcIsPhys && isExtSubReg) {
886 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
887 // coalesced with AX.
888 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
890 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
891 // coalesced to a larger register so the subreg indices cancel out.
892 if (DstSubIdx != SubIdx) {
893 DOUT << "\t Sub-register indices mismatch.\n";
894 return false; // Not coalescable.
897 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
899 } else if (DstIsPhys && isInsSubReg) {
900 // EAX = INSERT_SUBREG EAX, r1024, 0
901 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
903 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
904 // coalesced to a larger register so the subreg indices cancel out.
905 if (SrcSubIdx != SubIdx) {
906 DOUT << "\t Sub-register indices mismatch.\n";
907 return false; // Not coalescable.
910 DstReg = tri_->getSubReg(DstReg, SubIdx);
912 } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
913 // If this is a extract_subreg where dst is a physical register, e.g.
914 // cl = EXTRACT_SUBREG reg1024, 1
915 // then create and update the actual physical register allocated to RHS.
917 // reg1024 = INSERT_SUBREG r1024, cl, 1
918 if (CopyMI->getOperand(1).getSubReg()) {
919 DOUT << "\tSrc of extract_ / insert_subreg already coalesced with reg"
920 << " of a super-class.\n";
921 return false; // Not coalescable.
923 const TargetRegisterClass *RC =
924 mri_->getRegClass(isExtSubReg ? SrcReg : DstReg);
926 RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
927 assert(RealDstReg && "Invalid extra_subreg instruction!");
929 RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
930 assert(RealSrcReg && "Invalid extra_subreg instruction!");
933 // For this type of EXTRACT_SUBREG, conservatively
934 // check if the live interval of the source register interfere with the
935 // actual super physical register we are trying to coalesce with.
936 unsigned PhysReg = isExtSubReg ? RealDstReg : RealSrcReg;
937 LiveInterval &RHS = li_->getInterval(isExtSubReg ? SrcReg : DstReg);
938 if (li_->hasInterval(PhysReg) &&
939 RHS.overlaps(li_->getInterval(PhysReg))) {
940 DOUT << "Interfere with register ";
941 DEBUG(li_->getInterval(PhysReg).print(DOUT, tri_));
942 return false; // Not coalescable
944 for (const unsigned* SR = tri_->getSubRegisters(PhysReg); *SR; ++SR)
945 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
946 DOUT << "Interfere with sub-register ";
947 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
948 return false; // Not coalescable
952 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
953 : CopyMI->getOperand(2).getSubReg();
955 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
956 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
957 // coalesced to a larger register so the subreg indices cancel out.
958 // Also check if the other larger register is of the same register
959 // class as the would be resulting register.
962 DOUT << "\t Sub-register indices mismatch.\n";
963 return false; // Not coalescable.
967 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
968 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
969 unsigned LargeRegSize =
970 li_->getInterval(LargeReg).getSize() / InstrSlots::NUM;
971 unsigned SmallRegSize =
972 li_->getInterval(SmallReg).getSize() / InstrSlots::NUM;
973 const TargetRegisterClass *RC = mri_->getRegClass(SmallReg);
974 unsigned Threshold = allocatableRCRegs_[RC].count();
975 // Be conservative. If both sides are virtual registers, do not coalesce
976 // if this will cause a high use density interval to target a smaller
978 if (SmallRegSize > Threshold || LargeRegSize > Threshold) {
979 if ((float)std::distance(mri_->use_begin(SmallReg),
980 mri_->use_end()) / SmallRegSize <
981 (float)std::distance(mri_->use_begin(LargeReg),
982 mri_->use_end()) / LargeRegSize) {
983 Again = true; // May be possible to coalesce later.
989 } else if (differingRegisterClasses(SrcReg, DstReg)) {
990 // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced
991 // with another? If it's the resulting destination register, then
992 // the subidx must be propagated to uses (but only those defined
993 // by the EXTRACT_SUBREG). If it's being coalesced into another
994 // register, it should be safe because register is assumed to have
995 // the register class of the super-register.
997 // If they are not of the same register class, we cannot join them.
998 DOUT << "\tSrc/Dest are different register classes.\n";
999 // Allow the coalescer to try again in case either side gets coalesced to
1000 // a physical register that's compatible with the other side. e.g.
1001 // r1024 = MOV32to32_ r1025
1002 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1003 Again = true; // May be possible to coalesce later.
1007 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1008 LiveInterval &DstInt = li_->getInterval(DstReg);
1009 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1010 "Register mapping is horribly broken!");
1012 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1013 DOUT << " and "; DstInt.print(DOUT, tri_);
1016 // Check if it is necessary to propagate "isDead" property.
1017 if (!isExtSubReg && !isInsSubReg) {
1018 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1019 bool isDead = mopd->isDead();
1021 // We need to be careful about coalescing a source physical register with a
1022 // virtual register. Once the coalescing is done, it cannot be broken and
1023 // these are not spillable! If the destination interval uses are far away,
1024 // think twice about coalescing them!
1025 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1026 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1027 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1028 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1029 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1030 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1031 if (TheCopy.isBackEdge)
1032 Threshold *= 2; // Favors back edge copies.
1034 // If the virtual register live interval is long but it has low use desity,
1035 // do not join them, instead mark the physical register as its allocation
1037 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
1038 if (Length > Threshold &&
1039 (((float)std::distance(mri_->use_begin(JoinVReg),
1040 mri_->use_end()) / Length) < (1.0 / Threshold))) {
1041 JoinVInt.preference = JoinPReg;
1043 DOUT << "\tMay tie down a physical register, abort!\n";
1044 Again = true; // May be possible to coalesce later.
1050 // Okay, attempt to join these two intervals. On failure, this returns false.
1051 // Otherwise, if one of the intervals being joined is a physreg, this method
1052 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1053 // been modified, so we can use this information below to update aliases.
1054 bool Swapped = false;
1055 // If SrcInt is implicitly defined, it's safe to coalesce.
1056 bool isEmpty = SrcInt.empty();
1057 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1058 // Only coalesce an empty interval (defined by implicit_def) with
1059 // another interval which has a valno defined by the CopyMI and the CopyMI
1060 // is a kill of the implicit def.
1061 DOUT << "Not profitable!\n";
1065 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1066 // Coalescing failed.
1068 // If we can eliminate the copy without merging the live ranges, do so now.
1069 if (!isExtSubReg && !isInsSubReg &&
1070 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1071 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1072 JoinedCopies.insert(CopyMI);
1076 // Otherwise, we are unable to join the intervals.
1077 DOUT << "Interference!\n";
1078 Again = true; // May be possible to coalesce later.
1082 LiveInterval *ResSrcInt = &SrcInt;
1083 LiveInterval *ResDstInt = &DstInt;
1085 std::swap(SrcReg, DstReg);
1086 std::swap(ResSrcInt, ResDstInt);
1088 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1089 "LiveInterval::join didn't work right!");
1091 // If we're about to merge live ranges into a physical register live range,
1092 // we have to update any aliased register's live ranges to indicate that they
1093 // have clobbered values for this range.
1094 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1095 // If this is a extract_subreg where dst is a physical register, e.g.
1096 // cl = EXTRACT_SUBREG reg1024, 1
1097 // then create and update the actual physical register allocated to RHS.
1098 if (RealDstReg || RealSrcReg) {
1099 LiveInterval &RealInt =
1100 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1101 SmallSet<const VNInfo*, 4> CopiedValNos;
1102 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
1103 E = ResSrcInt->ranges.end(); I != E; ++I) {
1104 const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start);
1105 assert(DstLR && "Invalid joined interval!");
1106 const VNInfo *DstValNo = DstLR->valno;
1107 if (CopiedValNos.insert(DstValNo)) {
1108 VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy,
1109 li_->getVNInfoAllocator());
1110 ValNo->hasPHIKill = DstValNo->hasPHIKill;
1111 RealInt.addKills(ValNo, DstValNo->kills);
1112 RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
1116 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1119 // Update the liveintervals of sub-registers.
1120 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1121 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1122 li_->getVNInfoAllocator());
1125 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1126 // larger super-register.
1127 if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) {
1128 if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) {
1129 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
1130 std::swap(SrcReg, DstReg);
1131 std::swap(ResSrcInt, ResDstInt);
1136 // Add all copies that define val# in the source interval into the queue.
1137 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1138 e = ResSrcInt->vni_end(); i != e; ++i) {
1139 const VNInfo *vni = *i;
1140 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1142 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1143 unsigned NewSrcReg, NewDstReg;
1145 JoinedCopies.count(CopyMI) == 0 &&
1146 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) {
1147 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent());
1148 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1149 isBackEdgeCopy(CopyMI, DstReg)));
1154 // Remember to delete the copy instruction.
1155 JoinedCopies.insert(CopyMI);
1157 // Some live range has been lengthened due to colaescing, eliminate the
1158 // unnecessary kills.
1159 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1160 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1161 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1163 // SrcReg is guarateed to be the register whose live interval that is
1165 li_->removeInterval(SrcReg);
1169 // r1024 = implicit_def
1172 RemoveDeadImpDef(DstReg, *ResDstInt);
1173 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1176 // Now the copy is being coalesced away, the val# previously defined
1177 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1178 // length interval. Remove the val#.
1179 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1180 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1181 VNInfo *ImpVal = LR->valno;
1182 assert(ImpVal->def == CopyIdx);
1183 unsigned NextDef = LR->end;
1184 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1185 ResDstInt->removeValNo(ImpVal);
1186 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1187 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1188 // Special case: vr1024 = implicit_def
1189 // vr1024 = insert_subreg vr1024, vr1025, c
1190 // The insert_subreg becomes a "copy" that defines a val# which can itself
1191 // be coalesced away.
1192 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1193 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1194 LR->valno->copy = DefMI;
1198 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1205 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1206 /// compute what the resultant value numbers for each value in the input two
1207 /// ranges will be. This is complicated by copies between the two which can
1208 /// and will commonly cause multiple value numbers to be merged into one.
1210 /// VN is the value number that we're trying to resolve. InstDefiningValue
1211 /// keeps track of the new InstDefiningValue assignment for the result
1212 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1213 /// whether a value in this or other is a copy from the opposite set.
1214 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1215 /// already been assigned.
1217 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1218 /// contains the value number the copy is from.
1220 static unsigned ComputeUltimateVN(VNInfo *VNI,
1221 SmallVector<VNInfo*, 16> &NewVNInfo,
1222 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1223 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1224 SmallVector<int, 16> &ThisValNoAssignments,
1225 SmallVector<int, 16> &OtherValNoAssignments) {
1226 unsigned VN = VNI->id;
1228 // If the VN has already been computed, just return it.
1229 if (ThisValNoAssignments[VN] >= 0)
1230 return ThisValNoAssignments[VN];
1231 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1233 // If this val is not a copy from the other val, then it must be a new value
1234 // number in the destination.
1235 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1236 if (I == ThisFromOther.end()) {
1237 NewVNInfo.push_back(VNI);
1238 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1240 VNInfo *OtherValNo = I->second;
1242 // Otherwise, this *is* a copy from the RHS. If the other side has already
1243 // been computed, return it.
1244 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1245 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1247 // Mark this value number as currently being computed, then ask what the
1248 // ultimate value # of the other value is.
1249 ThisValNoAssignments[VN] = -2;
1250 unsigned UltimateVN =
1251 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1252 OtherValNoAssignments, ThisValNoAssignments);
1253 return ThisValNoAssignments[VN] = UltimateVN;
1256 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1257 return std::find(V.begin(), V.end(), Val) != V.end();
1260 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1261 /// the specified live interval is defined by a copy from the specified
1263 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1266 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1269 if (LR->valno->def == ~0U &&
1270 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1271 *tri_->getSuperRegisters(li.reg)) {
1272 // It's a sub-register live interval, we may not have precise information.
1274 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1275 unsigned SrcReg, DstReg;
1276 if (tii_->isMoveInstr(*DefMI, SrcReg, DstReg) &&
1277 DstReg == li.reg && SrcReg == Reg) {
1278 // Cache computed info.
1279 LR->valno->def = LR->start;
1280 LR->valno->copy = DefMI;
1287 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1288 /// caller of this method must guarantee that the RHS only contains a single
1289 /// value number and that the RHS is not defined by a copy from this
1290 /// interval. This returns false if the intervals are not joinable, or it
1291 /// joins them and returns true.
1292 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1293 assert(RHS.containsOneValue());
1295 // Some number (potentially more than one) value numbers in the current
1296 // interval may be defined as copies from the RHS. Scan the overlapping
1297 // portions of the LHS and RHS, keeping track of this and looking for
1298 // overlapping live ranges that are NOT defined as copies. If these exist, we
1301 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1302 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1304 if (LHSIt->start < RHSIt->start) {
1305 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1306 if (LHSIt != LHS.begin()) --LHSIt;
1307 } else if (RHSIt->start < LHSIt->start) {
1308 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1309 if (RHSIt != RHS.begin()) --RHSIt;
1312 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1315 // Determine if these live intervals overlap.
1316 bool Overlaps = false;
1317 if (LHSIt->start <= RHSIt->start)
1318 Overlaps = LHSIt->end > RHSIt->start;
1320 Overlaps = RHSIt->end > LHSIt->start;
1322 // If the live intervals overlap, there are two interesting cases: if the
1323 // LHS interval is defined by a copy from the RHS, it's ok and we record
1324 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1325 // coalesce these live ranges and we bail out.
1327 // If we haven't already recorded that this value # is safe, check it.
1328 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1329 // Copy from the RHS?
1330 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1331 return false; // Nope, bail out.
1333 if (LHSIt->contains(RHSIt->valno->def))
1334 // Here is an interesting situation:
1336 // vr1025 = copy vr1024
1341 // Even though vr1025 is copied from vr1024, it's not safe to
1342 // coalesced them since live range of vr1025 intersects the
1343 // def of vr1024. This happens because vr1025 is assigned the
1344 // value of the previous iteration of vr1024.
1346 EliminatedLHSVals.push_back(LHSIt->valno);
1349 // We know this entire LHS live range is okay, so skip it now.
1350 if (++LHSIt == LHSEnd) break;
1354 if (LHSIt->end < RHSIt->end) {
1355 if (++LHSIt == LHSEnd) break;
1357 // One interesting case to check here. It's possible that we have
1358 // something like "X3 = Y" which defines a new value number in the LHS,
1359 // and is the last use of this liverange of the RHS. In this case, we
1360 // want to notice this copy (so that it gets coalesced away) even though
1361 // the live ranges don't actually overlap.
1362 if (LHSIt->start == RHSIt->end) {
1363 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1364 // We already know that this value number is going to be merged in
1365 // if coalescing succeeds. Just skip the liverange.
1366 if (++LHSIt == LHSEnd) break;
1368 // Otherwise, if this is a copy from the RHS, mark it as being merged
1370 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1371 if (LHSIt->contains(RHSIt->valno->def))
1372 // Here is an interesting situation:
1374 // vr1025 = copy vr1024
1379 // Even though vr1025 is copied from vr1024, it's not safe to
1380 // coalesced them since live range of vr1025 intersects the
1381 // def of vr1024. This happens because vr1025 is assigned the
1382 // value of the previous iteration of vr1024.
1384 EliminatedLHSVals.push_back(LHSIt->valno);
1386 // We know this entire LHS live range is okay, so skip it now.
1387 if (++LHSIt == LHSEnd) break;
1392 if (++RHSIt == RHSEnd) break;
1396 // If we got here, we know that the coalescing will be successful and that
1397 // the value numbers in EliminatedLHSVals will all be merged together. Since
1398 // the most common case is that EliminatedLHSVals has a single number, we
1399 // optimize for it: if there is more than one value, we merge them all into
1400 // the lowest numbered one, then handle the interval as if we were merging
1401 // with one value number.
1403 if (EliminatedLHSVals.size() > 1) {
1404 // Loop through all the equal value numbers merging them into the smallest
1406 VNInfo *Smallest = EliminatedLHSVals[0];
1407 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1408 if (EliminatedLHSVals[i]->id < Smallest->id) {
1409 // Merge the current notion of the smallest into the smaller one.
1410 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1411 Smallest = EliminatedLHSVals[i];
1413 // Merge into the smallest.
1414 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1417 LHSValNo = Smallest;
1418 } else if (EliminatedLHSVals.empty()) {
1419 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1420 *tri_->getSuperRegisters(LHS.reg))
1421 // Imprecise sub-register information. Can't handle it.
1423 assert(0 && "No copies from the RHS?");
1425 LHSValNo = EliminatedLHSVals[0];
1428 // Okay, now that there is a single LHS value number that we're merging the
1429 // RHS into, update the value number info for the LHS to indicate that the
1430 // value number is defined where the RHS value number was.
1431 const VNInfo *VNI = RHS.getValNumInfo(0);
1432 LHSValNo->def = VNI->def;
1433 LHSValNo->copy = VNI->copy;
1435 // Okay, the final step is to loop over the RHS live intervals, adding them to
1437 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
1438 LHS.addKills(LHSValNo, VNI->kills);
1439 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1440 LHS.weight += RHS.weight;
1441 if (RHS.preference && !LHS.preference)
1442 LHS.preference = RHS.preference;
1447 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1448 /// returns false. Otherwise, if one of the intervals being joined is a
1449 /// physreg, this method always canonicalizes LHS to be it. The output
1450 /// "RHS" will not have been modified, so we can use this information
1451 /// below to update aliases.
1452 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
1453 LiveInterval &RHS, bool &Swapped) {
1454 // Compute the final value assignment, assuming that the live ranges can be
1456 SmallVector<int, 16> LHSValNoAssignments;
1457 SmallVector<int, 16> RHSValNoAssignments;
1458 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1459 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1460 SmallVector<VNInfo*, 16> NewVNInfo;
1462 // If a live interval is a physical register, conservatively check if any
1463 // of its sub-registers is overlapping the live interval of the virtual
1464 // register. If so, do not coalesce.
1465 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1466 *tri_->getSubRegisters(LHS.reg)) {
1467 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1468 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1469 DOUT << "Interfere with sub-register ";
1470 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1473 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1474 *tri_->getSubRegisters(RHS.reg)) {
1475 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1476 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1477 DOUT << "Interfere with sub-register ";
1478 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1483 // Compute ultimate value numbers for the LHS and RHS values.
1484 if (RHS.containsOneValue()) {
1485 // Copies from a liveinterval with a single value are simple to handle and
1486 // very common, handle the special case here. This is important, because
1487 // often RHS is small and LHS is large (e.g. a physreg).
1489 // Find out if the RHS is defined as a copy from some value in the LHS.
1490 int RHSVal0DefinedFromLHS = -1;
1492 VNInfo *RHSValNoInfo = NULL;
1493 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1494 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1495 if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) {
1496 // If RHS is not defined as a copy from the LHS, we can use simpler and
1497 // faster checks to see if the live ranges are coalescable. This joiner
1498 // can't swap the LHS/RHS intervals though.
1499 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1500 return SimpleJoin(LHS, RHS);
1502 RHSValNoInfo = RHSValNoInfo0;
1505 // It was defined as a copy from the LHS, find out what value # it is.
1506 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
1507 RHSValID = RHSValNoInfo->id;
1508 RHSVal0DefinedFromLHS = RHSValID;
1511 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1512 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1513 NewVNInfo.resize(LHS.getNumValNums(), NULL);
1515 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1516 // should now get updated.
1517 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1520 unsigned VN = VNI->id;
1521 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
1522 if (LHSSrcReg != RHS.reg) {
1523 // If this is not a copy from the RHS, its value number will be
1524 // unmodified by the coalescing.
1525 NewVNInfo[VN] = VNI;
1526 LHSValNoAssignments[VN] = VN;
1527 } else if (RHSValID == -1) {
1528 // Otherwise, it is a copy from the RHS, and we don't already have a
1529 // value# for it. Keep the current value number, but remember it.
1530 LHSValNoAssignments[VN] = RHSValID = VN;
1531 NewVNInfo[VN] = RHSValNoInfo;
1532 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1534 // Otherwise, use the specified value #.
1535 LHSValNoAssignments[VN] = RHSValID;
1536 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
1537 NewVNInfo[VN] = RHSValNoInfo;
1538 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1542 NewVNInfo[VN] = VNI;
1543 LHSValNoAssignments[VN] = VN;
1547 assert(RHSValID != -1 && "Didn't find value #?");
1548 RHSValNoAssignments[0] = RHSValID;
1549 if (RHSVal0DefinedFromLHS != -1) {
1550 // This path doesn't go through ComputeUltimateVN so just set
1552 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
1555 // Loop over the value numbers of the LHS, seeing if any are defined from
1557 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1560 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1563 // DstReg is known to be a register in the LHS interval. If the src is
1564 // from the RHS interval, we can use its value #.
1565 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
1568 // Figure out the value # from the RHS.
1569 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
1572 // Loop over the value numbers of the RHS, seeing if any are defined from
1574 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1577 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1580 // DstReg is known to be a register in the RHS interval. If the src is
1581 // from the LHS interval, we can use its value #.
1582 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
1585 // Figure out the value # from the LHS.
1586 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
1589 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1590 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1591 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1593 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1596 unsigned VN = VNI->id;
1597 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1599 ComputeUltimateVN(VNI, NewVNInfo,
1600 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1601 LHSValNoAssignments, RHSValNoAssignments);
1603 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1606 unsigned VN = VNI->id;
1607 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1609 // If this value number isn't a copy from the LHS, it's a new number.
1610 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1611 NewVNInfo.push_back(VNI);
1612 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1616 ComputeUltimateVN(VNI, NewVNInfo,
1617 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1618 RHSValNoAssignments, LHSValNoAssignments);
1622 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1623 // interval lists to see if these intervals are coalescable.
1624 LiveInterval::const_iterator I = LHS.begin();
1625 LiveInterval::const_iterator IE = LHS.end();
1626 LiveInterval::const_iterator J = RHS.begin();
1627 LiveInterval::const_iterator JE = RHS.end();
1629 // Skip ahead until the first place of potential sharing.
1630 if (I->start < J->start) {
1631 I = std::upper_bound(I, IE, J->start);
1632 if (I != LHS.begin()) --I;
1633 } else if (J->start < I->start) {
1634 J = std::upper_bound(J, JE, I->start);
1635 if (J != RHS.begin()) --J;
1639 // Determine if these two live ranges overlap.
1641 if (I->start < J->start) {
1642 Overlaps = I->end > J->start;
1644 Overlaps = J->end > I->start;
1647 // If so, check value # info to determine if they are really different.
1649 // If the live range overlap will map to the same value number in the
1650 // result liverange, we can still coalesce them. If not, we can't.
1651 if (LHSValNoAssignments[I->valno->id] !=
1652 RHSValNoAssignments[J->valno->id])
1656 if (I->end < J->end) {
1665 // Update kill info. Some live ranges are extended due to copy coalescing.
1666 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1667 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1668 VNInfo *VNI = I->first;
1669 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1670 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
1671 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
1672 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
1675 // Update kill info. Some live ranges are extended due to copy coalescing.
1676 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1677 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1678 VNInfo *VNI = I->first;
1679 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1680 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
1681 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
1682 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
1685 // If we get here, we know that we can coalesce the live ranges. Ask the
1686 // intervals to coalesce themselves now.
1687 if ((RHS.ranges.size() > LHS.ranges.size() &&
1688 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
1689 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1690 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
1693 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
1700 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1701 // depth of the basic block (the unsigned), and then on the MBB number.
1702 struct DepthMBBCompare {
1703 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1704 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1705 if (LHS.first > RHS.first) return true; // Deeper loops first
1706 return LHS.first == RHS.first &&
1707 LHS.second->getNumber() < RHS.second->getNumber();
1712 /// getRepIntervalSize - Returns the size of the interval that represents the
1713 /// specified register.
1715 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
1716 return Rc->getRepIntervalSize(Reg);
1719 /// CopyRecSort::operator - Join priority queue sorting function.
1721 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
1722 // Inner loops first.
1723 if (left.LoopDepth > right.LoopDepth)
1725 else if (left.LoopDepth == right.LoopDepth)
1726 if (left.isBackEdge && !right.isBackEdge)
1731 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1732 std::vector<CopyRec> &TryAgain) {
1733 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1735 std::vector<CopyRec> VirtCopies;
1736 std::vector<CopyRec> PhysCopies;
1737 std::vector<CopyRec> ImpDefCopies;
1738 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
1739 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1741 MachineInstr *Inst = MII++;
1743 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1744 unsigned SrcReg, DstReg;
1745 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1746 DstReg = Inst->getOperand(0).getReg();
1747 SrcReg = Inst->getOperand(1).getReg();
1748 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
1749 DstReg = Inst->getOperand(0).getReg();
1750 SrcReg = Inst->getOperand(2).getReg();
1751 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
1754 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1755 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1757 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
1759 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
1760 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
1761 else if (SrcIsPhys || DstIsPhys)
1762 PhysCopies.push_back(CopyRec(Inst, 0, false));
1764 VirtCopies.push_back(CopyRec(Inst, 0, false));
1771 // Try coalescing implicit copies first, followed by copies to / from
1772 // physical registers, then finally copies from virtual registers to
1773 // virtual registers.
1774 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1775 CopyRec &TheCopy = ImpDefCopies[i];
1777 if (!JoinCopy(TheCopy, Again))
1779 TryAgain.push_back(TheCopy);
1781 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1782 CopyRec &TheCopy = PhysCopies[i];
1784 if (!JoinCopy(TheCopy, Again))
1786 TryAgain.push_back(TheCopy);
1788 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1789 CopyRec &TheCopy = VirtCopies[i];
1791 if (!JoinCopy(TheCopy, Again))
1793 TryAgain.push_back(TheCopy);
1797 void SimpleRegisterCoalescing::joinIntervals() {
1798 DOUT << "********** JOINING INTERVALS ***********\n";
1801 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
1803 std::vector<CopyRec> TryAgainList;
1804 if (loopInfo->begin() == loopInfo->end()) {
1805 // If there are no loops in the function, join intervals in function order.
1806 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1808 CopyCoalesceInMBB(I, TryAgainList);
1810 // Otherwise, join intervals in inner loops before other intervals.
1811 // Unfortunately we can't just iterate over loop hierarchy here because
1812 // there may be more MBB's than BB's. Collect MBB's for sorting.
1814 // Join intervals in the function prolog first. We want to join physical
1815 // registers with virtual registers before the intervals got too long.
1816 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1817 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1818 MachineBasicBlock *MBB = I;
1819 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1822 // Sort by loop depth.
1823 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1825 // Finally, join intervals in loop nest order.
1826 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1827 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1830 // Joining intervals can allow other intervals to be joined. Iteratively join
1831 // until we make no progress.
1833 SmallVector<CopyRec, 16> TryAgain;
1834 bool ProgressMade = true;
1835 while (ProgressMade) {
1836 ProgressMade = false;
1837 while (!JoinQueue->empty()) {
1838 CopyRec R = JoinQueue->pop();
1840 bool Success = JoinCopy(R, Again);
1842 ProgressMade = true;
1844 TryAgain.push_back(R);
1848 while (!TryAgain.empty()) {
1849 JoinQueue->push(TryAgain.back());
1850 TryAgain.pop_back();
1855 bool ProgressMade = true;
1856 while (ProgressMade) {
1857 ProgressMade = false;
1859 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1860 CopyRec &TheCopy = TryAgainList[i];
1863 bool Success = JoinCopy(TheCopy, Again);
1864 if (Success || !Again) {
1865 TheCopy.MI = 0; // Mark this one as done.
1866 ProgressMade = true;
1877 /// Return true if the two specified registers belong to different register
1878 /// classes. The registers may be either phys or virt regs.
1879 bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1880 unsigned RegB) const {
1882 // Get the register classes for the first reg.
1883 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
1884 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1885 "Shouldn't consider two physregs!");
1886 return !mri_->getRegClass(RegB)->contains(RegA);
1889 // Compare against the regclass for the second reg.
1890 const TargetRegisterClass *RegClass = mri_->getRegClass(RegA);
1891 if (TargetRegisterInfo::isVirtualRegister(RegB))
1892 return RegClass != mri_->getRegClass(RegB);
1894 return !RegClass->contains(RegB);
1897 /// lastRegisterUse - Returns the last use of the specific register between
1898 /// cycles Start and End or NULL if there are no uses.
1900 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
1901 unsigned Reg, unsigned &UseIdx) const{
1903 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1904 MachineOperand *LastUse = NULL;
1905 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
1906 E = mri_->use_end(); I != E; ++I) {
1907 MachineOperand &Use = I.getOperand();
1908 MachineInstr *UseMI = Use.getParent();
1909 unsigned SrcReg, DstReg;
1910 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg)
1911 // Ignore identity copies.
1913 unsigned Idx = li_->getInstructionIndex(UseMI);
1914 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
1922 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1925 // Skip deleted instructions
1926 MachineInstr *MI = li_->getInstructionFromIndex(e);
1927 while ((e - InstrSlots::NUM) >= s && !MI) {
1928 e -= InstrSlots::NUM;
1929 MI = li_->getInstructionFromIndex(e);
1931 if (e < s || MI == NULL)
1934 // Ignore identity copies.
1935 unsigned SrcReg, DstReg;
1936 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg))
1937 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1938 MachineOperand &Use = MI->getOperand(i);
1939 if (Use.isRegister() && Use.isUse() && Use.getReg() &&
1940 tri_->regsOverlap(Use.getReg(), Reg)) {
1946 e -= InstrSlots::NUM;
1953 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
1954 if (TargetRegisterInfo::isPhysicalRegister(reg))
1955 cerr << tri_->getName(reg);
1957 cerr << "%reg" << reg;
1960 void SimpleRegisterCoalescing::releaseMemory() {
1961 JoinedCopies.clear();
1964 static bool isZeroLengthInterval(LiveInterval *li) {
1965 for (LiveInterval::Ranges::const_iterator
1966 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
1967 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
1972 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
1973 /// turn the copy into an implicit def.
1975 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
1976 MachineBasicBlock *MBB,
1977 unsigned DstReg, unsigned SrcReg) {
1978 MachineInstr *CopyMI = &*I;
1979 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1980 if (!li_->hasInterval(SrcReg))
1982 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1983 if (!SrcInt.empty())
1985 if (!li_->hasInterval(DstReg))
1987 LiveInterval &DstInt = li_->getInterval(DstReg);
1988 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
1989 DstInt.removeValNo(DstLR->valno);
1990 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
1991 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
1992 CopyMI->RemoveOperand(i);
1993 bool NoUse = mri_->use_begin(SrcReg) == mri_->use_end();
1995 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
1996 E = mri_->reg_end(); I != E; ) {
1997 assert(I.getOperand().isDef());
1998 MachineInstr *DefMI = &*I;
2000 // The implicit_def source has no other uses, delete it.
2001 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2002 li_->RemoveMachineInstrFromMaps(DefMI);
2003 DefMI->eraseFromParent();
2011 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2013 mri_ = &fn.getRegInfo();
2014 tm_ = &fn.getTarget();
2015 tri_ = tm_->getRegisterInfo();
2016 tii_ = tm_->getInstrInfo();
2017 li_ = &getAnalysis<LiveIntervals>();
2018 loopInfo = &getAnalysis<MachineLoopInfo>();
2020 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2021 << "********** Function: "
2022 << ((Value*)mf_->getFunction())->getName() << '\n';
2024 allocatableRegs_ = tri_->getAllocatableSet(fn);
2025 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2026 E = tri_->regclass_end(); I != E; ++I)
2027 allocatableRCRegs_.insert(std::make_pair(*I,
2028 tri_->getAllocatableSet(fn, *I)));
2030 // Join (coalesce) intervals if requested.
2031 if (EnableJoining) {
2033 DOUT << "********** INTERVALS POST JOINING **********\n";
2034 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2035 I->second.print(DOUT, tri_);
2040 // Perform a final pass over the instructions and compute spill weights
2041 // and remove identity moves.
2042 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2043 mbbi != mbbe; ++mbbi) {
2044 MachineBasicBlock* mbb = mbbi;
2045 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2047 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2049 MachineInstr *MI = mii;
2050 unsigned SrcReg, DstReg;
2051 if (JoinedCopies.count(MI)) {
2052 // Delete all coalesced copies.
2053 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) {
2054 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2055 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) &&
2056 "Unrecognized copy instruction");
2057 DstReg = MI->getOperand(0).getReg();
2059 if (MI->registerDefIsDead(DstReg)) {
2060 LiveInterval &li = li_->getInterval(DstReg);
2061 if (!ShortenDeadCopySrcLiveRange(li, MI))
2062 ShortenDeadCopyLiveRange(li, MI);
2064 li_->RemoveMachineInstrFromMaps(MI);
2065 mii = mbbi->erase(mii);
2070 // If the move will be an identity move delete it
2071 bool isMove = tii_->isMoveInstr(*mii, SrcReg, DstReg);
2072 if (isMove && SrcReg == DstReg) {
2073 if (li_->hasInterval(SrcReg)) {
2074 LiveInterval &RegInt = li_->getInterval(SrcReg);
2075 // If def of this move instruction is dead, remove its live range
2076 // from the dstination register's live interval.
2077 if (mii->registerDefIsDead(DstReg)) {
2078 if (!ShortenDeadCopySrcLiveRange(RegInt, mii))
2079 ShortenDeadCopyLiveRange(RegInt, mii);
2082 li_->RemoveMachineInstrFromMaps(mii);
2083 mii = mbbi->erase(mii);
2085 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2086 SmallSet<unsigned, 4> UniqueUses;
2087 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
2088 const MachineOperand &mop = mii->getOperand(i);
2089 if (mop.isRegister() && mop.getReg() &&
2090 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2091 unsigned reg = mop.getReg();
2092 // Multiple uses of reg by the same instruction. It should not
2093 // contribute to spill weight again.
2094 if (UniqueUses.count(reg) != 0)
2096 LiveInterval &RegInt = li_->getInterval(reg);
2098 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2099 UniqueUses.insert(reg);
2107 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2108 LiveInterval &LI = I->second;
2109 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2110 // If the live interval length is essentially zero, i.e. in every live
2111 // range the use follows def immediately, it doesn't make sense to spill
2112 // it and hope it will be easier to allocate for this li.
2113 if (isZeroLengthInterval(&LI))
2114 LI.weight = HUGE_VALF;
2116 bool isLoad = false;
2117 if (li_->isReMaterializable(LI, isLoad)) {
2118 // If all of the definitions of the interval are re-materializable,
2119 // it is a preferred candidate for spilling. If non of the defs are
2120 // loads, then it's potentially very cheap to re-materialize.
2121 // FIXME: this gets much more complicated once we support non-trivial
2122 // re-materialization.
2130 // Slightly prefer live interval that has been assigned a preferred reg.
2134 // Divide the weight of the interval by its size. This encourages
2135 // spilling of intervals that are large and have few uses, and
2136 // discourages spilling of small intervals with many uses.
2137 LI.weight /= LI.getSize();
2145 /// print - Implement the dump method.
2146 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2150 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2151 return new SimpleRegisterCoalescing();
2154 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2155 DEFINING_FILE_FOR(SimpleRegisterCoalescing)