1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(numJoins , "Number of interval joins performed");
39 STATISTIC(numCrossRCs , "Number of cross class joins performed");
40 STATISTIC(numCommutes , "Number of instruction commuting performed");
41 STATISTIC(numExtends , "Number of copies extended");
42 STATISTIC(NumReMats , "Number of instructions re-materialized");
43 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
44 STATISTIC(numAborts , "Number of times interval joining aborted");
45 STATISTIC(numDeadValNo, "Number of valno def marked dead");
47 char SimpleRegisterCoalescing::ID = 0;
49 EnableJoining("join-liveintervals",
50 cl::desc("Coalesce copies (default=true)"),
54 NewHeuristic("new-coalescer-heuristic",
55 cl::desc("Use new coalescer heuristic"),
56 cl::init(false), cl::Hidden);
59 CrossClassJoin("join-cross-class-copies",
60 cl::desc("Coalesce cross register class copies"),
61 cl::init(false), cl::Hidden);
64 PhysJoinTweak("tweak-phys-join-heuristics",
65 cl::desc("Tweak heuristics for joining phys reg with vr"),
66 cl::init(false), cl::Hidden);
68 static RegisterPass<SimpleRegisterCoalescing>
69 X("simple-register-coalescing", "Simple Register Coalescing");
71 // Declare that we implement the RegisterCoalescer interface
72 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
74 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
76 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
77 AU.addRequired<LiveIntervals>();
78 AU.addPreserved<LiveIntervals>();
79 AU.addRequired<MachineLoopInfo>();
80 AU.addPreserved<MachineLoopInfo>();
81 AU.addPreservedID(MachineDominatorsID);
83 AU.addPreservedID(StrongPHIEliminationID);
85 AU.addPreservedID(PHIEliminationID);
86 AU.addPreservedID(TwoAddressInstructionPassID);
87 MachineFunctionPass::getAnalysisUsage(AU);
90 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
91 /// being the source and IntB being the dest, thus this defines a value number
92 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
93 /// see if we can merge these two pieces of B into a single value number,
94 /// eliminating a copy. For example:
98 /// B1 = A3 <- this copy
100 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
101 /// value number to be replaced with B0 (which simplifies the B liveinterval).
103 /// This returns true if an interval was modified.
105 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
107 MachineInstr *CopyMI) {
108 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
110 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
111 // the example above.
112 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
113 assert(BLR != IntB.end() && "Live range not found!");
114 VNInfo *BValNo = BLR->valno;
116 // Get the location that B is defined at. Two options: either this value has
117 // an unknown definition point or it is defined at CopyIdx. If unknown, we
119 if (!BValNo->copy) return false;
120 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
122 // AValNo is the value number in A that defines the copy, A3 in the example.
123 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
124 assert(ALR != IntA.end() && "Live range not found!");
125 VNInfo *AValNo = ALR->valno;
126 // If it's re-defined by an early clobber somewhere in the live range, then
127 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
129 // 172 %ECX<def> = MOV32rr %reg1039<kill>
130 // 180 INLINEASM <es:subl $5,$1
131 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
132 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
133 // 188 %EAX<def> = MOV32rr %EAX<kill>
134 // 196 %ECX<def> = MOV32rr %ECX<kill>
135 // 204 %ECX<def> = MOV32rr %ECX<kill>
136 // 212 %EAX<def> = MOV32rr %EAX<kill>
137 // 220 %EAX<def> = MOV32rr %EAX
138 // 228 %reg1039<def> = MOV32rr %ECX<kill>
139 // The early clobber operand ties ECX input to the ECX def.
141 // The live interval of ECX is represented as this:
142 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
143 // The coalescer has no idea there was a def in the middle of [174,230].
144 if (AValNo->redefByEC)
147 // If AValNo is defined as a copy from IntB, we can potentially process this.
148 // Get the instruction that defines this value number.
149 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
150 if (!SrcReg) return false; // Not defined by a copy.
152 // If the value number is not defined by a copy instruction, ignore it.
154 // If the source register comes from an interval other than IntB, we can't
156 if (SrcReg != IntB.reg) return false;
158 // Get the LiveRange in IntB that this value number starts with.
159 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
160 assert(ValLR != IntB.end() && "Live range not found!");
162 // Make sure that the end of the live range is inside the same block as
164 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
166 ValLREndInst->getParent() != CopyMI->getParent()) return false;
168 // Okay, we now know that ValLR ends in the same block that the CopyMI
169 // live-range starts. If there are no intervening live ranges between them in
170 // IntB, we can merge them.
171 if (ValLR+1 != BLR) return false;
173 // If a live interval is a physical register, conservatively check if any
174 // of its sub-registers is overlapping the live interval of the virtual
175 // register. If so, do not coalesce.
176 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
177 *tri_->getSubRegisters(IntB.reg)) {
178 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
179 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
180 DOUT << "Interfere with sub-register ";
181 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
186 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
188 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
189 // We are about to delete CopyMI, so need to remove it as the 'instruction
190 // that defines this value #'. Update the the valnum with the new defining
192 BValNo->def = FillerStart;
195 // Okay, we can merge them. We need to insert a new liverange:
196 // [ValLR.end, BLR.begin) of either value number, then we merge the
197 // two value numbers.
198 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
200 // If the IntB live range is assigned to a physical register, and if that
201 // physreg has sub-registers, update their live intervals as well.
202 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
203 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
204 LiveInterval &SRLI = li_->getInterval(*SR);
205 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
206 SRLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
210 // Okay, merge "B1" into the same value number as "B0".
211 if (BValNo != ValLR->valno) {
212 IntB.addKills(ValLR->valno, BValNo->kills);
213 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
215 DOUT << " result = "; IntB.print(DOUT, tri_);
218 // If the source instruction was killing the source register before the
219 // merge, unset the isKill marker given the live range has been extended.
220 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
222 ValLREndInst->getOperand(UIdx).setIsKill(false);
223 IntB.removeKill(ValLR->valno, FillerStart);
230 /// HasOtherReachingDefs - Return true if there are definitions of IntB
231 /// other than BValNo val# that can reach uses of AValno val# of IntA.
232 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
236 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
238 if (AI->valno != AValNo) continue;
239 LiveInterval::Ranges::iterator BI =
240 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
241 if (BI != IntB.ranges.begin())
243 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
244 if (BI->valno == BValNo)
246 if (BI->start <= AI->start && BI->end > AI->start)
248 if (BI->start > AI->start && BI->start < AI->end)
255 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
256 /// being the source and IntB being the dest, thus this defines a value number
257 /// in IntB. If the source value number (in IntA) is defined by a commutable
258 /// instruction and its other operand is coalesced to the copy dest register,
259 /// see if we can transform the copy into a noop by commuting the definition. For
262 /// A3 = op A2 B0<kill>
264 /// B1 = A3 <- this copy
266 /// = op A3 <- more uses
270 /// B2 = op B0 A2<kill>
272 /// B1 = B2 <- now an identify copy
274 /// = op B2 <- more uses
276 /// This returns true if an interval was modified.
278 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
280 MachineInstr *CopyMI) {
281 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
283 // FIXME: For now, only eliminate the copy by commuting its def when the
284 // source register is a virtual register. We want to guard against cases
285 // where the copy is a back edge copy and commuting the def lengthen the
286 // live interval of the source register to the entire loop.
287 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
290 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
291 // the example above.
292 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
293 assert(BLR != IntB.end() && "Live range not found!");
294 VNInfo *BValNo = BLR->valno;
296 // Get the location that B is defined at. Two options: either this value has
297 // an unknown definition point or it is defined at CopyIdx. If unknown, we
299 if (!BValNo->copy) return false;
300 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
302 // AValNo is the value number in A that defines the copy, A3 in the example.
303 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
304 assert(ALR != IntA.end() && "Live range not found!");
305 VNInfo *AValNo = ALR->valno;
306 // If other defs can reach uses of this def, then it's not safe to perform
308 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
310 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
311 const TargetInstrDesc &TID = DefMI->getDesc();
313 if (!TID.isCommutable() ||
314 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
317 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
318 unsigned NewReg = NewDstMO.getReg();
319 if (NewReg != IntB.reg || !NewDstMO.isKill())
322 // Make sure there are no other definitions of IntB that would reach the
323 // uses which the new definition can reach.
324 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
327 // If some of the uses of IntA.reg is already coalesced away, return false.
328 // It's not possible to determine whether it's safe to perform the coalescing.
329 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
330 UE = mri_->use_end(); UI != UE; ++UI) {
331 MachineInstr *UseMI = &*UI;
332 unsigned UseIdx = li_->getInstructionIndex(UseMI);
333 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
334 if (ULR == IntA.end())
336 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
340 // At this point we have decided that it is legal to do this
341 // transformation. Start by commuting the instruction.
342 MachineBasicBlock *MBB = DefMI->getParent();
343 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
346 if (NewMI != DefMI) {
347 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
348 MBB->insert(DefMI, NewMI);
351 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
352 NewMI->getOperand(OpIdx).setIsKill();
354 bool BHasPHIKill = BValNo->hasPHIKill;
355 SmallVector<VNInfo*, 4> BDeadValNos;
356 SmallVector<unsigned, 4> BKills;
357 std::map<unsigned, unsigned> BExtend;
359 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
368 // then do not add kills of A to the newly created B interval.
369 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
371 BExtend[ALR->end] = BLR->end;
373 // Update uses of IntA of the specific Val# with IntB.
374 bool BHasSubRegs = false;
375 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
376 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
377 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
378 UE = mri_->use_end(); UI != UE;) {
379 MachineOperand &UseMO = UI.getOperand();
380 MachineInstr *UseMI = &*UI;
382 if (JoinedCopies.count(UseMI))
384 unsigned UseIdx = li_->getInstructionIndex(UseMI);
385 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
386 if (ULR == IntA.end() || ULR->valno != AValNo)
388 UseMO.setReg(NewReg);
391 if (UseMO.isKill()) {
393 UseMO.setIsKill(false);
395 BKills.push_back(li_->getUseIndex(UseIdx)+1);
397 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
398 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
400 if (DstReg == IntB.reg) {
401 // This copy will become a noop. If it's defining a new val#,
402 // remove that val# as well. However this live range is being
403 // extended to the end of the existing live range defined by the copy.
404 unsigned DefIdx = li_->getDefIndex(UseIdx);
405 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
406 BHasPHIKill |= DLR->valno->hasPHIKill;
407 assert(DLR->valno->def == DefIdx);
408 BDeadValNos.push_back(DLR->valno);
409 BExtend[DLR->start] = DLR->end;
410 JoinedCopies.insert(UseMI);
411 // If this is a kill but it's going to be removed, the last use
412 // of the same val# is the new kill.
418 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
419 // simply extend BLR if CopyMI doesn't end the range.
420 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
422 // Remove val#'s defined by copies that will be coalesced away.
423 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
424 VNInfo *DeadVNI = BDeadValNos[i];
426 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
427 LiveInterval &SRLI = li_->getInterval(*SR);
428 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
429 SRLI.removeValNo(SRLR->valno);
432 IntB.removeValNo(BDeadValNos[i]);
435 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
436 // is updated. Kills are also updated.
437 VNInfo *ValNo = BValNo;
438 ValNo->def = AValNo->def;
440 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
441 unsigned Kill = ValNo->kills[j];
442 if (Kill != BLR->end)
443 BKills.push_back(Kill);
445 ValNo->kills.clear();
446 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
448 if (AI->valno != AValNo) continue;
449 unsigned End = AI->end;
450 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
451 if (EI != BExtend.end())
453 IntB.addRange(LiveRange(AI->start, End, ValNo));
455 // If the IntB live range is assigned to a physical register, and if that
456 // physreg has sub-registers, update their live intervals as well.
458 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
459 LiveInterval &SRLI = li_->getInterval(*SR);
460 SRLI.MergeInClobberRange(AI->start, End, li_->getVNInfoAllocator());
464 IntB.addKills(ValNo, BKills);
465 ValNo->hasPHIKill = BHasPHIKill;
467 DOUT << " result = "; IntB.print(DOUT, tri_);
470 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
471 IntA.removeValNo(AValNo);
472 DOUT << " result = "; IntA.print(DOUT, tri_);
479 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
480 /// fallthoughs to SuccMBB.
481 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
482 MachineBasicBlock *SuccMBB,
483 const TargetInstrInfo *tii_) {
486 MachineBasicBlock *TBB = 0, *FBB = 0;
487 SmallVector<MachineOperand, 4> Cond;
488 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
489 MBB->isSuccessor(SuccMBB);
492 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
493 /// from a physical register live interval as well as from the live intervals
494 /// of its sub-registers.
495 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
496 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
497 li.removeRange(Start, End, true);
498 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
499 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
500 if (!li_->hasInterval(*SR))
502 LiveInterval &sli = li_->getInterval(*SR);
503 unsigned RemoveEnd = Start;
504 while (RemoveEnd != End) {
505 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
508 RemoveEnd = (LR->end < End) ? LR->end : End;
509 sli.removeRange(Start, RemoveEnd, true);
516 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
517 /// as the copy instruction, trim the live interval to the last use and return
520 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
521 MachineBasicBlock *CopyMBB,
523 const LiveRange *LR) {
524 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
526 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
529 MachineInstr *LastUseMI = LastUse->getParent();
530 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
537 // r1025<dead> = r1024<kill>
538 if (MBBStart < LR->end)
539 removeRange(li, MBBStart, LR->end, li_, tri_);
543 // There are uses before the copy, just shorten the live range to the end
545 LastUse->setIsKill();
546 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
547 li.addKill(LR->valno, LastUseIdx+1);
548 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
549 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
551 // Last use is itself an identity code.
552 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
553 LastUseMI->getOperand(DeadIdx).setIsDead();
559 if (LR->start <= MBBStart && LR->end > MBBStart) {
560 if (LR->start == 0) {
561 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
562 // Live-in to the function but dead. Remove it from entry live-in set.
563 mf_->begin()->removeLiveIn(li.reg);
565 // FIXME: Shorten intervals in BBs that reaches this BB.
571 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
572 /// computation, replace the copy by rematerialize the definition.
573 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
575 MachineInstr *CopyMI) {
576 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
577 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
578 assert(SrcLR != SrcInt.end() && "Live range not found!");
579 VNInfo *ValNo = SrcLR->valno;
580 // If other defs can reach uses of this def, then it's not safe to perform
582 if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
584 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
585 const TargetInstrDesc &TID = DefMI->getDesc();
586 if (!TID.isAsCheapAsAMove())
588 if (!DefMI->getDesc().isRematerializable() ||
589 !tii_->isTriviallyReMaterializable(DefMI))
591 bool SawStore = false;
592 if (!DefMI->isSafeToMove(tii_, SawStore))
595 unsigned DefIdx = li_->getDefIndex(CopyIdx);
596 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
597 DLR->valno->copy = NULL;
598 // Don't forget to update sub-register intervals.
599 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
600 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
601 if (!li_->hasInterval(*SR))
603 DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
604 if (DLR && DLR->valno->copy == CopyMI)
605 DLR->valno->copy = NULL;
609 // If copy kills the source register, find the last use and propagate
611 bool checkForDeadDef = false;
612 MachineBasicBlock *MBB = CopyMI->getParent();
613 if (CopyMI->killsRegister(SrcInt.reg))
614 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
615 checkForDeadDef = true;
618 MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
619 tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
620 MachineInstr *NewMI = prior(MII);
622 if (checkForDeadDef) {
623 // PR4090 fix: Trim interval failed because there was no use of the
624 // source interval in this MBB. If the def is in this MBB too then we
625 // should mark it dead:
626 if (DefMI->getParent() == MBB) {
627 DefMI->addRegisterDead(SrcInt.reg, tri_);
628 SrcLR->end = SrcLR->start + 1;
632 // CopyMI may have implicit operands, transfer them over to the newly
633 // rematerialized instruction. And update implicit def interval valnos.
634 for (unsigned i = CopyMI->getDesc().getNumOperands(),
635 e = CopyMI->getNumOperands(); i != e; ++i) {
636 MachineOperand &MO = CopyMI->getOperand(i);
637 if (MO.isReg() && MO.isImplicit())
638 NewMI->addOperand(MO);
639 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
640 unsigned Reg = MO.getReg();
641 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
642 if (DLR && DLR->valno->copy == CopyMI)
643 DLR->valno->copy = NULL;
647 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
648 CopyMI->eraseFromParent();
649 ReMatCopies.insert(CopyMI);
650 ReMatDefs.insert(DefMI);
655 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
657 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
658 unsigned DstReg) const {
659 MachineBasicBlock *MBB = CopyMI->getParent();
660 const MachineLoop *L = loopInfo->getLoopFor(MBB);
663 if (MBB != L->getLoopLatch())
666 LiveInterval &LI = li_->getInterval(DstReg);
667 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
668 LiveInterval::const_iterator DstLR =
669 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
670 if (DstLR == LI.end())
672 unsigned KillIdx = li_->getMBBEndIdx(MBB) + 1;
673 if (DstLR->valno->kills.size() == 1 &&
674 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
679 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
680 /// update the subregister number if it is not zero. If DstReg is a
681 /// physical register and the existing subregister number of the def / use
682 /// being updated is not zero, make sure to set it to the correct physical
685 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
687 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
688 if (DstIsPhys && SubIdx) {
689 // Figure out the real physical register we are updating with.
690 DstReg = tri_->getSubReg(DstReg, SubIdx);
694 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
695 E = mri_->reg_end(); I != E; ) {
696 MachineOperand &O = I.getOperand();
697 MachineInstr *UseMI = &*I;
699 unsigned OldSubIdx = O.getSubReg();
701 unsigned UseDstReg = DstReg;
703 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
705 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
706 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
707 CopySrcSubIdx, CopyDstSubIdx) &&
708 CopySrcReg != CopyDstReg &&
709 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
710 // If the use is a copy and it won't be coalesced away, and its source
711 // is defined by a trivial computation, try to rematerialize it instead.
712 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
721 // Sub-register indexes goes from small to large. e.g.
722 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
723 // EAX: 1 -> AL, 2 -> AX
724 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
725 // sub-register 2 is also AX.
726 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
727 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
730 // Remove would-be duplicated kill marker.
731 if (O.isKill() && UseMI->killsRegister(DstReg))
735 // After updating the operand, check if the machine instruction has
736 // become a copy. If so, update its val# information.
737 const TargetInstrDesc &TID = UseMI->getDesc();
738 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
739 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
740 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
741 CopySrcSubIdx, CopyDstSubIdx) &&
742 CopySrcReg != CopyDstReg &&
743 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
744 allocatableRegs_[CopyDstReg])) {
745 LiveInterval &LI = li_->getInterval(CopyDstReg);
746 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
747 const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx);
748 if (DLR->valno->def == DefIdx)
749 DLR->valno->copy = UseMI;
754 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
755 /// registers due to insert_subreg coalescing. e.g.
757 /// r1025 = implicit_def
758 /// r1025 = insert_subreg r1025, r1024
762 /// r1025 = implicit_def
763 /// r1025 = insert_subreg r1025, r1025
766 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
767 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
768 E = mri_->reg_end(); I != E; ) {
769 MachineOperand &O = I.getOperand();
770 MachineInstr *DefMI = &*I;
774 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
776 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
778 li_->RemoveMachineInstrFromMaps(DefMI);
779 DefMI->eraseFromParent();
783 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
784 /// due to live range lengthening as the result of coalescing.
785 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
787 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
788 UE = mri_->use_end(); UI != UE; ++UI) {
789 MachineOperand &UseMO = UI.getOperand();
790 if (UseMO.isKill()) {
791 MachineInstr *UseMI = UseMO.getParent();
792 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
793 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
794 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
795 UseMO.setIsKill(false);
800 /// removeIntervalIfEmpty - Check if the live interval of a physical register
801 /// is empty, if so remove it and also remove the empty intervals of its
802 /// sub-registers. Return true if live interval is removed.
803 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
804 const TargetRegisterInfo *tri_) {
806 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
807 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
808 if (!li_->hasInterval(*SR))
810 LiveInterval &sli = li_->getInterval(*SR);
812 li_->removeInterval(*SR);
814 li_->removeInterval(li.reg);
820 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
821 /// Return true if live interval is removed.
822 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
823 MachineInstr *CopyMI) {
824 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
825 LiveInterval::iterator MLR =
826 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
828 return false; // Already removed by ShortenDeadCopySrcLiveRange.
829 unsigned RemoveStart = MLR->start;
830 unsigned RemoveEnd = MLR->end;
831 // Remove the liverange that's defined by this.
832 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
833 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
834 return removeIntervalIfEmpty(li, li_, tri_);
839 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
840 /// the val# it defines. If the live interval becomes empty, remove it as well.
841 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
842 MachineInstr *DefMI) {
843 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
844 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
845 if (DefIdx != MLR->valno->def)
847 li.removeValNo(MLR->valno);
848 return removeIntervalIfEmpty(li, li_, tri_);
851 /// PropagateDeadness - Propagate the dead marker to the instruction which
852 /// defines the val#.
853 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
854 unsigned &LRStart, LiveIntervals *li_,
855 const TargetRegisterInfo* tri_) {
856 MachineInstr *DefMI =
857 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
858 if (DefMI && DefMI != CopyMI) {
859 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
861 DefMI->getOperand(DeadIdx).setIsDead();
862 // A dead def should have a single cycle interval.
868 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
869 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
870 /// ends the live range there. If there isn't another use, then this live range
871 /// is dead. Return true if live interval is removed.
873 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
874 MachineInstr *CopyMI) {
875 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
877 // FIXME: special case: function live in. It can be a general case if the
878 // first instruction index starts at > 0 value.
879 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
880 // Live-in to the function but dead. Remove it from entry live-in set.
881 if (mf_->begin()->isLiveIn(li.reg))
882 mf_->begin()->removeLiveIn(li.reg);
883 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
884 removeRange(li, LR->start, LR->end, li_, tri_);
885 return removeIntervalIfEmpty(li, li_, tri_);
888 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
890 // Livein but defined by a phi.
893 unsigned RemoveStart = LR->start;
894 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
895 if (LR->end > RemoveEnd)
896 // More uses past this copy? Nothing to do.
899 // If there is a last use in the same bb, we can't remove the live range.
900 // Shorten the live interval and return.
901 MachineBasicBlock *CopyMBB = CopyMI->getParent();
902 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
905 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
906 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
907 // If the live range starts in another mbb and the copy mbb is not a fall
908 // through mbb, then we can only cut the range from the beginning of the
910 RemoveStart = li_->getMBBStartIdx(CopyMBB) + 1;
912 if (LR->valno->def == RemoveStart) {
913 // If the def MI defines the val# and this copy is the only kill of the
914 // val#, then propagate the dead marker.
915 if (li.isOnlyLROfValNo(LR)) {
916 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
919 if (li.isKill(LR->valno, RemoveEnd))
920 li.removeKill(LR->valno, RemoveEnd);
923 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
924 return removeIntervalIfEmpty(li, li_, tri_);
927 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
928 /// from an implicit def to another register can be coalesced away.
929 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
931 LiveInterval &ImpLi) const{
932 if (!CopyMI->killsRegister(ImpLi.reg))
934 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
935 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
938 if (LR->valno->hasPHIKill)
940 if (LR->valno->def != CopyIdx)
942 // Make sure all of val# uses are copies.
943 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
944 UE = mri_->use_end(); UI != UE;) {
945 MachineInstr *UseMI = &*UI;
947 if (JoinedCopies.count(UseMI))
949 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
950 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
951 if (ULR == li.end() || ULR->valno != LR->valno)
953 // If the use is not a use, then it's not safe to coalesce the move.
954 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
955 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
956 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
957 UseMI->getOperand(1).getReg() == li.reg)
966 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
967 /// def and it is being removed. Turn all copies from this value# into
969 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
971 SmallVector<MachineInstr*, 4> ImpDefs;
972 MachineOperand *LastUse = NULL;
973 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
974 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
975 RE = mri_->reg_end(); RI != RE;) {
976 MachineOperand *MO = &RI.getOperand();
977 MachineInstr *MI = &*RI;
980 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
981 ImpDefs.push_back(MI);
984 if (JoinedCopies.count(MI))
986 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
987 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
988 if (ULR == li.end() || ULR->valno != VNI)
990 // If the use is a copy, turn it into an identity copy.
991 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
992 if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
994 // Change it to an implicit_def.
995 MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
996 for (int i = MI->getNumOperands() - 1, e = 0; i > e; --i)
997 MI->RemoveOperand(i);
998 // It's no longer a copy, update the valno it defines.
999 unsigned DefIdx = li_->getDefIndex(UseIdx);
1000 LiveInterval &DstInt = li_->getInterval(DstReg);
1001 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(DefIdx);
1002 assert(DLR != DstInt.end() && "Live range not found!");
1003 assert(DLR->valno->copy == MI);
1004 DLR->valno->copy = NULL;
1005 ReMatCopies.insert(MI);
1006 } else if (UseIdx > LastUseIdx) {
1007 LastUseIdx = UseIdx;
1012 LastUse->setIsKill();
1013 li.addKill(VNI, LastUseIdx+1);
1015 // Remove dead implicit_def's.
1016 while (!ImpDefs.empty()) {
1017 MachineInstr *ImpDef = ImpDefs.back();
1019 li_->RemoveMachineInstrFromMaps(ImpDef);
1020 ImpDef->eraseFromParent();
1025 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
1026 /// a virtual destination register with physical source register.
1028 SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
1029 MachineBasicBlock *CopyMBB,
1030 LiveInterval &DstInt,
1031 LiveInterval &SrcInt) {
1032 // If the virtual register live interval is long but it has low use desity,
1033 // do not join them, instead mark the physical register as its allocation
1035 const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg);
1036 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1037 unsigned Length = li_->getApproximateInstructionCount(DstInt);
1038 if (Length > Threshold &&
1039 (((float)std::distance(mri_->use_begin(DstInt.reg),
1040 mri_->use_end()) / Length) < (1.0 / Threshold)))
1043 // If the virtual register live interval extends into a loop, turn down
1045 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1046 const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
1048 // Let's see if the virtual register live interval extends into the loop.
1049 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
1050 assert(DLR != DstInt.end() && "Live range not found!");
1051 DLR = DstInt.FindLiveRangeContaining(DLR->end+1);
1052 if (DLR != DstInt.end()) {
1053 CopyMBB = li_->getMBBFromIndex(DLR->start);
1054 L = loopInfo->getLoopFor(CopyMBB);
1058 if (!L || Length <= Threshold)
1061 unsigned UseIdx = li_->getUseIndex(CopyIdx);
1062 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1063 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1064 if (loopInfo->getLoopFor(SMBB) != L) {
1065 if (!loopInfo->isLoopHeader(CopyMBB))
1067 // If vr's live interval extends pass the loop header, do not join.
1068 for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(),
1069 SE = CopyMBB->succ_end(); SI != SE; ++SI) {
1070 MachineBasicBlock *SuccMBB = *SI;
1071 if (SuccMBB == CopyMBB)
1073 if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
1074 li_->getMBBEndIdx(SuccMBB)+1))
1081 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
1082 /// copy from a virtual source register to a physical destination register.
1084 SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
1085 MachineBasicBlock *CopyMBB,
1086 LiveInterval &DstInt,
1087 LiveInterval &SrcInt) {
1088 // If the virtual register live interval is long but it has low use desity,
1089 // do not join them, instead mark the physical register as its allocation
1091 const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
1092 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1093 unsigned Length = li_->getApproximateInstructionCount(SrcInt);
1094 if (Length > Threshold &&
1095 (((float)std::distance(mri_->use_begin(SrcInt.reg),
1096 mri_->use_end()) / Length) < (1.0 / Threshold)))
1100 // Must be implicit_def.
1103 // If the virtual register live interval is defined or cross a loop, turn
1104 // down aggressiveness.
1105 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1106 unsigned UseIdx = li_->getUseIndex(CopyIdx);
1107 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1108 assert(SLR != SrcInt.end() && "Live range not found!");
1109 SLR = SrcInt.FindLiveRangeContaining(SLR->start-1);
1110 if (SLR == SrcInt.end())
1112 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1113 const MachineLoop *L = loopInfo->getLoopFor(SMBB);
1115 if (!L || Length <= Threshold)
1118 if (loopInfo->getLoopFor(CopyMBB) != L) {
1119 if (SMBB != L->getLoopLatch())
1121 // If vr's live interval is extended from before the loop latch, do not
1123 for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(),
1124 PE = SMBB->pred_end(); PI != PE; ++PI) {
1125 MachineBasicBlock *PredMBB = *PI;
1126 if (PredMBB == SMBB)
1128 if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
1129 li_->getMBBEndIdx(PredMBB)+1))
1136 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1137 /// two virtual registers from different register classes.
1139 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned LargeReg,
1141 unsigned Threshold) {
1142 // Then make sure the intervals are *short*.
1143 LiveInterval &LargeInt = li_->getInterval(LargeReg);
1144 LiveInterval &SmallInt = li_->getInterval(SmallReg);
1145 unsigned LargeSize = li_->getApproximateInstructionCount(LargeInt);
1146 unsigned SmallSize = li_->getApproximateInstructionCount(SmallInt);
1147 if (SmallSize > Threshold || LargeSize > Threshold)
1148 if ((float)std::distance(mri_->use_begin(SmallReg),
1149 mri_->use_end()) / SmallSize <
1150 (float)std::distance(mri_->use_begin(LargeReg),
1151 mri_->use_end()) / LargeSize)
1156 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1157 /// register with a physical register, check if any of the virtual register
1158 /// operand is a sub-register use or def. If so, make sure it won't result
1159 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1160 /// vr1024 = extract_subreg vr1025, 1
1162 /// vr1024 = mov8rr AH
1163 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1164 /// AH does not have a super-reg whose sub-register 1 is AH.
1166 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1169 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1170 E = mri_->reg_end(); I != E; ++I) {
1171 MachineOperand &O = I.getOperand();
1172 MachineInstr *MI = &*I;
1173 if (MI == CopyMI || JoinedCopies.count(MI))
1175 unsigned SubIdx = O.getSubReg();
1176 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1178 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1179 SubIdx = MI->getOperand(2).getImm();
1180 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1183 unsigned SrcReg = MI->getOperand(1).getReg();
1184 const TargetRegisterClass *RC =
1185 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1186 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1187 : mri_->getRegClass(SrcReg);
1188 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1192 if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
1193 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
1194 SubIdx = MI->getOperand(3).getImm();
1195 if (VirtReg == MI->getOperand(0).getReg()) {
1196 if (!tri_->getSubReg(PhysReg, SubIdx))
1199 unsigned DstReg = MI->getOperand(0).getReg();
1200 const TargetRegisterClass *RC =
1201 TargetRegisterInfo::isPhysicalRegister(DstReg)
1202 ? tri_->getPhysicalRegisterRegClass(DstReg)
1203 : mri_->getRegClass(DstReg);
1204 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1213 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1214 /// an extract_subreg where dst is a physical register, e.g.
1215 /// cl = EXTRACT_SUBREG reg1024, 1
1217 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1218 unsigned SrcReg, unsigned SubIdx,
1219 unsigned &RealDstReg) {
1220 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1221 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1222 assert(RealDstReg && "Invalid extract_subreg instruction!");
1224 // For this type of EXTRACT_SUBREG, conservatively
1225 // check if the live interval of the source register interfere with the
1226 // actual super physical register we are trying to coalesce with.
1227 LiveInterval &RHS = li_->getInterval(SrcReg);
1228 if (li_->hasInterval(RealDstReg) &&
1229 RHS.overlaps(li_->getInterval(RealDstReg))) {
1230 DOUT << "Interfere with register ";
1231 DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
1232 return false; // Not coalescable
1234 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1235 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1236 DOUT << "Interfere with sub-register ";
1237 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1238 return false; // Not coalescable
1243 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1244 /// an insert_subreg where src is a physical register, e.g.
1245 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1247 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1248 unsigned SrcReg, unsigned SubIdx,
1249 unsigned &RealSrcReg) {
1250 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1251 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1252 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1254 LiveInterval &RHS = li_->getInterval(DstReg);
1255 if (li_->hasInterval(RealSrcReg) &&
1256 RHS.overlaps(li_->getInterval(RealSrcReg))) {
1257 DOUT << "Interfere with register ";
1258 DEBUG(li_->getInterval(RealSrcReg).print(DOUT, tri_));
1259 return false; // Not coalescable
1261 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1262 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1263 DOUT << "Interfere with sub-register ";
1264 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1265 return false; // Not coalescable
1270 /// getRegAllocPreference - Return register allocation preference register.
1272 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1273 MachineRegisterInfo *MRI,
1274 const TargetRegisterInfo *TRI) {
1275 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1277 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
1278 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1281 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1282 /// which are the src/dst of the copy instruction CopyMI. This returns true
1283 /// if the copy was successfully coalesced away. If it is not currently
1284 /// possible to coalesce this interval, but it may be possible if other
1285 /// things get coalesced, then it returns true by reference in 'Again'.
1286 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1287 MachineInstr *CopyMI = TheCopy.MI;
1290 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1291 return false; // Already done.
1293 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
1295 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1296 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
1297 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
1298 bool isSubRegToReg = CopyMI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG;
1299 unsigned SubIdx = 0;
1301 DstReg = CopyMI->getOperand(0).getReg();
1302 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1303 SrcReg = CopyMI->getOperand(1).getReg();
1304 SrcSubIdx = CopyMI->getOperand(2).getImm();
1305 } else if (isInsSubReg || isSubRegToReg) {
1306 if (CopyMI->getOperand(2).getSubReg()) {
1307 DOUT << "\tSource of insert_subreg is already coalesced "
1308 << "to another register.\n";
1309 return false; // Not coalescable.
1311 DstReg = CopyMI->getOperand(0).getReg();
1312 DstSubIdx = CopyMI->getOperand(3).getImm();
1313 SrcReg = CopyMI->getOperand(2).getReg();
1314 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
1315 assert(0 && "Unrecognized copy instruction!");
1319 // If they are already joined we continue.
1320 if (SrcReg == DstReg) {
1321 DOUT << "\tCopy already coalesced.\n";
1322 return false; // Not coalescable.
1325 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1326 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1328 // If they are both physical registers, we cannot join them.
1329 if (SrcIsPhys && DstIsPhys) {
1330 DOUT << "\tCan not coalesce physregs.\n";
1331 return false; // Not coalescable.
1334 // We only join virtual registers with allocatable physical registers.
1335 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1336 DOUT << "\tSrc reg is unallocatable physreg.\n";
1337 return false; // Not coalescable.
1339 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1340 DOUT << "\tDst reg is unallocatable physreg.\n";
1341 return false; // Not coalescable.
1344 // Check that a physical source register is compatible with dst regclass
1346 unsigned SrcSubReg = SrcSubIdx ?
1347 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1348 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1349 const TargetRegisterClass *DstSubRC = DstRC;
1351 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1352 assert(DstSubRC && "Illegal subregister index");
1353 if (!DstSubRC->contains(SrcSubReg)) {
1354 DOUT << "\tIncompatible destination regclass: "
1355 << tri_->getName(SrcSubReg) << " not in " << DstSubRC->getName()
1357 return false; // Not coalescable.
1361 // Check that a physical dst register is compatible with source regclass
1363 unsigned DstSubReg = DstSubIdx ?
1364 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1365 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1366 const TargetRegisterClass *SrcSubRC = SrcRC;
1368 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1369 assert(SrcSubRC && "Illegal subregister index");
1370 if (!SrcSubRC->contains(DstReg)) {
1371 DOUT << "\tIncompatible source regclass: "
1372 << tri_->getName(DstSubReg) << " not in " << SrcSubRC->getName()
1374 return false; // Not coalescable.
1378 // Should be non-null only when coalescing to a sub-register class.
1379 bool CrossRC = false;
1380 const TargetRegisterClass *NewRC = NULL;
1381 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1382 unsigned RealDstReg = 0;
1383 unsigned RealSrcReg = 0;
1384 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1385 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1386 if (SrcIsPhys && isExtSubReg) {
1387 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1388 // coalesced with AX.
1389 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1391 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1392 // coalesced to a larger register so the subreg indices cancel out.
1393 if (DstSubIdx != SubIdx) {
1394 DOUT << "\t Sub-register indices mismatch.\n";
1395 return false; // Not coalescable.
1398 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1400 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1401 // EAX = INSERT_SUBREG EAX, r1024, 0
1402 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1404 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1405 // coalesced to a larger register so the subreg indices cancel out.
1406 if (SrcSubIdx != SubIdx) {
1407 DOUT << "\t Sub-register indices mismatch.\n";
1408 return false; // Not coalescable.
1411 DstReg = tri_->getSubReg(DstReg, SubIdx);
1413 } else if ((DstIsPhys && isExtSubReg) ||
1414 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1415 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1416 DOUT << "\tSrc of extract_subreg already coalesced with reg"
1417 << " of a super-class.\n";
1418 return false; // Not coalescable.
1422 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1423 return false; // Not coalescable
1425 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1426 return false; // Not coalescable
1430 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1431 : CopyMI->getOperand(2).getSubReg();
1433 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1434 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1435 // coalesced to a larger register so the subreg indices cancel out.
1436 // Also check if the other larger register is of the same register
1437 // class as the would be resulting register.
1440 DOUT << "\t Sub-register indices mismatch.\n";
1441 return false; // Not coalescable.
1445 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1446 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1447 unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
1448 if (!isWinToJoinCrossClass(LargeReg, SmallReg, Limit)) {
1449 Again = true; // May be possible to coalesce later.
1454 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1455 if (!CrossClassJoin)
1459 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1460 // with another? If it's the resulting destination register, then
1461 // the subidx must be propagated to uses (but only those defined
1462 // by the EXTRACT_SUBREG). If it's being coalesced into another
1463 // register, it should be safe because register is assumed to have
1464 // the register class of the super-register.
1466 // Process moves where one of the registers have a sub-register index.
1467 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1468 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1469 SubIdx = DstMO->getSubReg();
1471 if (SrcMO->getSubReg())
1472 // FIXME: can we handle this?
1474 // This is not an insert_subreg but it looks like one.
1475 // e.g. %reg1024:4 = MOV32rr %EAX
1478 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1479 return false; // Not coalescable
1483 SubIdx = SrcMO->getSubReg();
1485 // This is not a extract_subreg but it looks like one.
1486 // e.g. %cl = MOV16rr %reg1024:1
1489 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1490 return false; // Not coalescable
1496 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1497 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1498 unsigned LargeReg = SrcReg;
1499 unsigned SmallReg = DstReg;
1502 // Now determine the register class of the joined register.
1504 if (SubIdx && DstRC && DstRC->isASubClass()) {
1505 // This is a move to a sub-register class. However, the source is a
1506 // sub-register of a larger register class. We don't know what should
1507 // the register class be. FIXME.
1511 Limit = allocatableRCRegs_[DstRC].count();
1512 } else if (!SrcIsPhys && !DstIsPhys) {
1513 NewRC = getCommonSubClass(SrcRC, DstRC);
1515 DOUT << "\tDisjoint regclasses: "
1516 << SrcRC->getName() << ", "
1517 << DstRC->getName() << ".\n";
1518 return false; // Not coalescable.
1520 if (DstRC->getSize() > SrcRC->getSize())
1521 std::swap(LargeReg, SmallReg);
1524 // If we are joining two virtual registers and the resulting register
1525 // class is more restrictive (fewer register, smaller size). Check if it's
1526 // worth doing the merge.
1527 if (!SrcIsPhys && !DstIsPhys &&
1528 (isExtSubReg || DstRC->isASubClass()) &&
1529 !isWinToJoinCrossClass(LargeReg, SmallReg,
1530 allocatableRCRegs_[NewRC].count())) {
1531 DOUT << "\tSrc/Dest are different register classes.\n";
1532 // Allow the coalescer to try again in case either side gets coalesced to
1533 // a physical register that's compatible with the other side. e.g.
1534 // r1024 = MOV32to32_ r1025
1535 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1536 Again = true; // May be possible to coalesce later.
1541 // Will it create illegal extract_subreg / insert_subreg?
1542 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1544 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1547 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1548 LiveInterval &DstInt = li_->getInterval(DstReg);
1549 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1550 "Register mapping is horribly broken!");
1552 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1553 DOUT << " and "; DstInt.print(DOUT, tri_);
1556 // Save a copy of the virtual register live interval. We'll manually
1557 // merge this into the "real" physical register live interval this is
1559 LiveInterval *SavedLI = 0;
1561 SavedLI = li_->dupInterval(&SrcInt);
1562 else if (RealSrcReg)
1563 SavedLI = li_->dupInterval(&DstInt);
1565 // Check if it is necessary to propagate "isDead" property.
1566 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1567 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1568 bool isDead = mopd->isDead();
1570 // We need to be careful about coalescing a source physical register with a
1571 // virtual register. Once the coalescing is done, it cannot be broken and
1572 // these are not spillable! If the destination interval uses are far away,
1573 // think twice about coalescing them!
1574 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1575 // If the copy is in a loop, take care not to coalesce aggressively if the
1576 // src is coming in from outside the loop (or the dst is out of the loop).
1577 // If it's not in a loop, then determine whether to join them base purely
1578 // by the length of the interval.
1579 if (PhysJoinTweak) {
1581 if (!isWinToJoinVRWithSrcPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
1582 mri_->setRegAllocationHint(DstInt.reg, 0, SrcReg);
1584 DOUT << "\tMay tie down a physical register, abort!\n";
1585 Again = true; // May be possible to coalesce later.
1589 if (!isWinToJoinVRWithDstPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
1590 mri_->setRegAllocationHint(SrcInt.reg, 0, DstReg);
1592 DOUT << "\tMay tie down a physical register, abort!\n";
1593 Again = true; // May be possible to coalesce later.
1598 // If the virtual register live interval is long but it has low use desity,
1599 // do not join them, instead mark the physical register as its allocation
1601 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1602 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1603 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1604 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1605 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1606 if (TheCopy.isBackEdge)
1607 Threshold *= 2; // Favors back edge copies.
1609 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1610 float Ratio = 1.0 / Threshold;
1611 if (Length > Threshold &&
1612 (((float)std::distance(mri_->use_begin(JoinVReg),
1613 mri_->use_end()) / Length) < Ratio)) {
1614 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1616 DOUT << "\tMay tie down a physical register, abort!\n";
1617 Again = true; // May be possible to coalesce later.
1624 // Okay, attempt to join these two intervals. On failure, this returns false.
1625 // Otherwise, if one of the intervals being joined is a physreg, this method
1626 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1627 // been modified, so we can use this information below to update aliases.
1628 bool Swapped = false;
1629 // If SrcInt is implicitly defined, it's safe to coalesce.
1630 bool isEmpty = SrcInt.empty();
1631 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1632 // Only coalesce an empty interval (defined by implicit_def) with
1633 // another interval which has a valno defined by the CopyMI and the CopyMI
1634 // is a kill of the implicit def.
1635 DOUT << "Not profitable!\n";
1639 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1640 // Coalescing failed.
1642 // If definition of source is defined by trivial computation, try
1643 // rematerializing it.
1644 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1645 ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
1648 // If we can eliminate the copy without merging the live ranges, do so now.
1649 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1650 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1651 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1652 JoinedCopies.insert(CopyMI);
1656 // Otherwise, we are unable to join the intervals.
1657 DOUT << "Interference!\n";
1658 Again = true; // May be possible to coalesce later.
1662 LiveInterval *ResSrcInt = &SrcInt;
1663 LiveInterval *ResDstInt = &DstInt;
1665 std::swap(SrcReg, DstReg);
1666 std::swap(ResSrcInt, ResDstInt);
1668 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1669 "LiveInterval::join didn't work right!");
1671 // If we're about to merge live ranges into a physical register live interval,
1672 // we have to update any aliased register's live ranges to indicate that they
1673 // have clobbered values for this range.
1674 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1675 // If this is a extract_subreg where dst is a physical register, e.g.
1676 // cl = EXTRACT_SUBREG reg1024, 1
1677 // then create and update the actual physical register allocated to RHS.
1678 if (RealDstReg || RealSrcReg) {
1679 LiveInterval &RealInt =
1680 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1681 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1682 E = SavedLI->vni_end(); I != E; ++I) {
1683 const VNInfo *ValNo = *I;
1684 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->copy,
1685 li_->getVNInfoAllocator());
1686 NewValNo->hasPHIKill = ValNo->hasPHIKill;
1687 NewValNo->redefByEC = ValNo->redefByEC;
1688 RealInt.addKills(NewValNo, ValNo->kills);
1689 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1691 RealInt.weight += SavedLI->weight;
1692 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1695 // Update the liveintervals of sub-registers.
1696 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1697 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1698 li_->getVNInfoAllocator());
1701 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1702 // larger super-register.
1703 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1704 !SrcIsPhys && !DstIsPhys) {
1705 if ((isExtSubReg && !Swapped) ||
1706 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1707 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1708 std::swap(SrcReg, DstReg);
1709 std::swap(ResSrcInt, ResDstInt);
1713 // Coalescing to a virtual register that is of a sub-register class of the
1714 // other. Make sure the resulting register is set to the right register class.
1718 mri_->setRegClass(DstReg, NewRC);
1722 // Add all copies that define val# in the source interval into the queue.
1723 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1724 e = ResSrcInt->vni_end(); i != e; ++i) {
1725 const VNInfo *vni = *i;
1726 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1728 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1729 unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx;
1731 JoinedCopies.count(CopyMI) == 0 &&
1732 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg,
1733 NewSrcSubIdx, NewDstSubIdx)) {
1734 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1735 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1736 isBackEdgeCopy(CopyMI, DstReg)));
1741 // Remember to delete the copy instruction.
1742 JoinedCopies.insert(CopyMI);
1744 // Some live range has been lengthened due to colaescing, eliminate the
1745 // unnecessary kills.
1746 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1747 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1748 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1753 // r1024 = implicit_def
1756 RemoveDeadImpDef(DstReg, *ResDstInt);
1757 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1759 // SrcReg is guarateed to be the register whose live interval that is
1761 li_->removeInterval(SrcReg);
1763 // Manually deleted the live interval copy.
1770 // Now the copy is being coalesced away, the val# previously defined
1771 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1772 // length interval. Remove the val#.
1773 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1774 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1775 VNInfo *ImpVal = LR->valno;
1776 assert(ImpVal->def == CopyIdx);
1777 unsigned NextDef = LR->end;
1778 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1779 ResDstInt->removeValNo(ImpVal);
1780 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1781 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1782 // Special case: vr1024 = implicit_def
1783 // vr1024 = insert_subreg vr1024, vr1025, c
1784 // The insert_subreg becomes a "copy" that defines a val# which can itself
1785 // be coalesced away.
1786 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1787 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1788 LR->valno->copy = DefMI;
1792 // If resulting interval has a preference that no longer fits because of subreg
1793 // coalescing, just clear the preference.
1794 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1795 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1796 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1797 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1798 if (!RC->contains(Preference))
1799 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1802 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1809 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1810 /// compute what the resultant value numbers for each value in the input two
1811 /// ranges will be. This is complicated by copies between the two which can
1812 /// and will commonly cause multiple value numbers to be merged into one.
1814 /// VN is the value number that we're trying to resolve. InstDefiningValue
1815 /// keeps track of the new InstDefiningValue assignment for the result
1816 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1817 /// whether a value in this or other is a copy from the opposite set.
1818 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1819 /// already been assigned.
1821 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1822 /// contains the value number the copy is from.
1824 static unsigned ComputeUltimateVN(VNInfo *VNI,
1825 SmallVector<VNInfo*, 16> &NewVNInfo,
1826 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1827 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1828 SmallVector<int, 16> &ThisValNoAssignments,
1829 SmallVector<int, 16> &OtherValNoAssignments) {
1830 unsigned VN = VNI->id;
1832 // If the VN has already been computed, just return it.
1833 if (ThisValNoAssignments[VN] >= 0)
1834 return ThisValNoAssignments[VN];
1835 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1837 // If this val is not a copy from the other val, then it must be a new value
1838 // number in the destination.
1839 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1840 if (I == ThisFromOther.end()) {
1841 NewVNInfo.push_back(VNI);
1842 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1844 VNInfo *OtherValNo = I->second;
1846 // Otherwise, this *is* a copy from the RHS. If the other side has already
1847 // been computed, return it.
1848 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1849 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1851 // Mark this value number as currently being computed, then ask what the
1852 // ultimate value # of the other value is.
1853 ThisValNoAssignments[VN] = -2;
1854 unsigned UltimateVN =
1855 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1856 OtherValNoAssignments, ThisValNoAssignments);
1857 return ThisValNoAssignments[VN] = UltimateVN;
1860 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1861 return std::find(V.begin(), V.end(), Val) != V.end();
1864 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1865 /// the specified live interval is defined by a copy from the specified
1867 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1870 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1873 if (LR->valno->def == ~0U &&
1874 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1875 *tri_->getSuperRegisters(li.reg)) {
1876 // It's a sub-register live interval, we may not have precise information.
1878 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1879 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1881 tii_->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1882 DstReg == li.reg && SrcReg == Reg) {
1883 // Cache computed info.
1884 LR->valno->def = LR->start;
1885 LR->valno->copy = DefMI;
1892 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1893 /// caller of this method must guarantee that the RHS only contains a single
1894 /// value number and that the RHS is not defined by a copy from this
1895 /// interval. This returns false if the intervals are not joinable, or it
1896 /// joins them and returns true.
1897 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1898 assert(RHS.containsOneValue());
1900 // Some number (potentially more than one) value numbers in the current
1901 // interval may be defined as copies from the RHS. Scan the overlapping
1902 // portions of the LHS and RHS, keeping track of this and looking for
1903 // overlapping live ranges that are NOT defined as copies. If these exist, we
1906 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1907 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1909 if (LHSIt->start < RHSIt->start) {
1910 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1911 if (LHSIt != LHS.begin()) --LHSIt;
1912 } else if (RHSIt->start < LHSIt->start) {
1913 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1914 if (RHSIt != RHS.begin()) --RHSIt;
1917 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1920 // Determine if these live intervals overlap.
1921 bool Overlaps = false;
1922 if (LHSIt->start <= RHSIt->start)
1923 Overlaps = LHSIt->end > RHSIt->start;
1925 Overlaps = RHSIt->end > LHSIt->start;
1927 // If the live intervals overlap, there are two interesting cases: if the
1928 // LHS interval is defined by a copy from the RHS, it's ok and we record
1929 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1930 // coalesce these live ranges and we bail out.
1932 // If we haven't already recorded that this value # is safe, check it.
1933 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1934 // Copy from the RHS?
1935 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1936 return false; // Nope, bail out.
1938 if (LHSIt->contains(RHSIt->valno->def))
1939 // Here is an interesting situation:
1941 // vr1025 = copy vr1024
1946 // Even though vr1025 is copied from vr1024, it's not safe to
1947 // coalesce them since the live range of vr1025 intersects the
1948 // def of vr1024. This happens because vr1025 is assigned the
1949 // value of the previous iteration of vr1024.
1951 EliminatedLHSVals.push_back(LHSIt->valno);
1954 // We know this entire LHS live range is okay, so skip it now.
1955 if (++LHSIt == LHSEnd) break;
1959 if (LHSIt->end < RHSIt->end) {
1960 if (++LHSIt == LHSEnd) break;
1962 // One interesting case to check here. It's possible that we have
1963 // something like "X3 = Y" which defines a new value number in the LHS,
1964 // and is the last use of this liverange of the RHS. In this case, we
1965 // want to notice this copy (so that it gets coalesced away) even though
1966 // the live ranges don't actually overlap.
1967 if (LHSIt->start == RHSIt->end) {
1968 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1969 // We already know that this value number is going to be merged in
1970 // if coalescing succeeds. Just skip the liverange.
1971 if (++LHSIt == LHSEnd) break;
1973 // Otherwise, if this is a copy from the RHS, mark it as being merged
1975 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1976 if (LHSIt->contains(RHSIt->valno->def))
1977 // Here is an interesting situation:
1979 // vr1025 = copy vr1024
1984 // Even though vr1025 is copied from vr1024, it's not safe to
1985 // coalesced them since live range of vr1025 intersects the
1986 // def of vr1024. This happens because vr1025 is assigned the
1987 // value of the previous iteration of vr1024.
1989 EliminatedLHSVals.push_back(LHSIt->valno);
1991 // We know this entire LHS live range is okay, so skip it now.
1992 if (++LHSIt == LHSEnd) break;
1997 if (++RHSIt == RHSEnd) break;
2001 // If we got here, we know that the coalescing will be successful and that
2002 // the value numbers in EliminatedLHSVals will all be merged together. Since
2003 // the most common case is that EliminatedLHSVals has a single number, we
2004 // optimize for it: if there is more than one value, we merge them all into
2005 // the lowest numbered one, then handle the interval as if we were merging
2006 // with one value number.
2007 VNInfo *LHSValNo = NULL;
2008 if (EliminatedLHSVals.size() > 1) {
2009 // Loop through all the equal value numbers merging them into the smallest
2011 VNInfo *Smallest = EliminatedLHSVals[0];
2012 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
2013 if (EliminatedLHSVals[i]->id < Smallest->id) {
2014 // Merge the current notion of the smallest into the smaller one.
2015 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
2016 Smallest = EliminatedLHSVals[i];
2018 // Merge into the smallest.
2019 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
2022 LHSValNo = Smallest;
2023 } else if (EliminatedLHSVals.empty()) {
2024 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2025 *tri_->getSuperRegisters(LHS.reg))
2026 // Imprecise sub-register information. Can't handle it.
2028 assert(0 && "No copies from the RHS?");
2030 LHSValNo = EliminatedLHSVals[0];
2033 // Okay, now that there is a single LHS value number that we're merging the
2034 // RHS into, update the value number info for the LHS to indicate that the
2035 // value number is defined where the RHS value number was.
2036 const VNInfo *VNI = RHS.getValNumInfo(0);
2037 LHSValNo->def = VNI->def;
2038 LHSValNo->copy = VNI->copy;
2040 // Okay, the final step is to loop over the RHS live intervals, adding them to
2042 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
2043 LHS.addKills(LHSValNo, VNI->kills);
2044 LHS.MergeRangesInAsValue(RHS, LHSValNo);
2045 LHS.weight += RHS.weight;
2047 // Update regalloc hint if both are virtual registers.
2048 if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
2049 TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
2050 std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
2051 std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
2052 if (RHSPref != LHSPref)
2053 mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second);
2056 // Update the liveintervals of sub-registers.
2057 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
2058 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
2059 li_->getOrCreateInterval(*AS).MergeInClobberRanges(LHS,
2060 li_->getVNInfoAllocator());
2065 /// JoinIntervals - Attempt to join these two intervals. On failure, this
2066 /// returns false. Otherwise, if one of the intervals being joined is a
2067 /// physreg, this method always canonicalizes LHS to be it. The output
2068 /// "RHS" will not have been modified, so we can use this information
2069 /// below to update aliases.
2071 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
2073 // Compute the final value assignment, assuming that the live ranges can be
2075 SmallVector<int, 16> LHSValNoAssignments;
2076 SmallVector<int, 16> RHSValNoAssignments;
2077 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
2078 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
2079 SmallVector<VNInfo*, 16> NewVNInfo;
2081 // If a live interval is a physical register, conservatively check if any
2082 // of its sub-registers is overlapping the live interval of the virtual
2083 // register. If so, do not coalesce.
2084 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2085 *tri_->getSubRegisters(LHS.reg)) {
2086 // If it's coalescing a virtual register to a physical register, estimate
2087 // its live interval length. This is the *cost* of scanning an entire live
2088 // interval. If the cost is low, we'll do an exhaustive check instead.
2090 // If this is something like this:
2098 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
2099 // less conservative check. It's possible a sub-register is defined before
2100 // v1024 (or live in) and live out of BB1.
2101 if (RHS.containsOneValue() &&
2102 li_->intervalIsInOneMBB(RHS) &&
2103 li_->getApproximateInstructionCount(RHS) <= 10) {
2104 // Perform a more exhaustive check for some common cases.
2105 if (li_->conflictsWithPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
2108 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
2109 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
2110 DOUT << "Interfere with sub-register ";
2111 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
2115 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
2116 *tri_->getSubRegisters(RHS.reg)) {
2117 if (LHS.containsOneValue() &&
2118 li_->getApproximateInstructionCount(LHS) <= 10) {
2119 // Perform a more exhaustive check for some common cases.
2120 if (li_->conflictsWithPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
2123 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
2124 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
2125 DOUT << "Interfere with sub-register ";
2126 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
2132 // Compute ultimate value numbers for the LHS and RHS values.
2133 if (RHS.containsOneValue()) {
2134 // Copies from a liveinterval with a single value are simple to handle and
2135 // very common, handle the special case here. This is important, because
2136 // often RHS is small and LHS is large (e.g. a physreg).
2138 // Find out if the RHS is defined as a copy from some value in the LHS.
2139 int RHSVal0DefinedFromLHS = -1;
2141 VNInfo *RHSValNoInfo = NULL;
2142 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
2143 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
2144 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
2145 // If RHS is not defined as a copy from the LHS, we can use simpler and
2146 // faster checks to see if the live ranges are coalescable. This joiner
2147 // can't swap the LHS/RHS intervals though.
2148 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2149 return SimpleJoin(LHS, RHS);
2151 RHSValNoInfo = RHSValNoInfo0;
2154 // It was defined as a copy from the LHS, find out what value # it is.
2155 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
2156 RHSValID = RHSValNoInfo->id;
2157 RHSVal0DefinedFromLHS = RHSValID;
2160 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2161 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2162 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2164 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2165 // should now get updated.
2166 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2169 unsigned VN = VNI->id;
2170 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2171 if (LHSSrcReg != RHS.reg) {
2172 // If this is not a copy from the RHS, its value number will be
2173 // unmodified by the coalescing.
2174 NewVNInfo[VN] = VNI;
2175 LHSValNoAssignments[VN] = VN;
2176 } else if (RHSValID == -1) {
2177 // Otherwise, it is a copy from the RHS, and we don't already have a
2178 // value# for it. Keep the current value number, but remember it.
2179 LHSValNoAssignments[VN] = RHSValID = VN;
2180 NewVNInfo[VN] = RHSValNoInfo;
2181 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2183 // Otherwise, use the specified value #.
2184 LHSValNoAssignments[VN] = RHSValID;
2185 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2186 NewVNInfo[VN] = RHSValNoInfo;
2187 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2191 NewVNInfo[VN] = VNI;
2192 LHSValNoAssignments[VN] = VN;
2196 assert(RHSValID != -1 && "Didn't find value #?");
2197 RHSValNoAssignments[0] = RHSValID;
2198 if (RHSVal0DefinedFromLHS != -1) {
2199 // This path doesn't go through ComputeUltimateVN so just set
2201 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2204 // Loop over the value numbers of the LHS, seeing if any are defined from
2206 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2209 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
2212 // DstReg is known to be a register in the LHS interval. If the src is
2213 // from the RHS interval, we can use its value #.
2214 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2217 // Figure out the value # from the RHS.
2218 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
2221 // Loop over the value numbers of the RHS, seeing if any are defined from
2223 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2226 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
2229 // DstReg is known to be a register in the RHS interval. If the src is
2230 // from the LHS interval, we can use its value #.
2231 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2234 // Figure out the value # from the LHS.
2235 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
2238 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2239 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2240 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2242 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2245 unsigned VN = VNI->id;
2246 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
2248 ComputeUltimateVN(VNI, NewVNInfo,
2249 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2250 LHSValNoAssignments, RHSValNoAssignments);
2252 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2255 unsigned VN = VNI->id;
2256 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
2258 // If this value number isn't a copy from the LHS, it's a new number.
2259 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2260 NewVNInfo.push_back(VNI);
2261 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2265 ComputeUltimateVN(VNI, NewVNInfo,
2266 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2267 RHSValNoAssignments, LHSValNoAssignments);
2271 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2272 // interval lists to see if these intervals are coalescable.
2273 LiveInterval::const_iterator I = LHS.begin();
2274 LiveInterval::const_iterator IE = LHS.end();
2275 LiveInterval::const_iterator J = RHS.begin();
2276 LiveInterval::const_iterator JE = RHS.end();
2278 // Skip ahead until the first place of potential sharing.
2279 if (I->start < J->start) {
2280 I = std::upper_bound(I, IE, J->start);
2281 if (I != LHS.begin()) --I;
2282 } else if (J->start < I->start) {
2283 J = std::upper_bound(J, JE, I->start);
2284 if (J != RHS.begin()) --J;
2288 // Determine if these two live ranges overlap.
2290 if (I->start < J->start) {
2291 Overlaps = I->end > J->start;
2293 Overlaps = J->end > I->start;
2296 // If so, check value # info to determine if they are really different.
2298 // If the live range overlap will map to the same value number in the
2299 // result liverange, we can still coalesce them. If not, we can't.
2300 if (LHSValNoAssignments[I->valno->id] !=
2301 RHSValNoAssignments[J->valno->id])
2305 if (I->end < J->end) {
2314 // Update kill info. Some live ranges are extended due to copy coalescing.
2315 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2316 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2317 VNInfo *VNI = I->first;
2318 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2319 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
2320 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
2321 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2324 // Update kill info. Some live ranges are extended due to copy coalescing.
2325 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2326 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2327 VNInfo *VNI = I->first;
2328 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2329 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
2330 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
2331 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2334 // If we get here, we know that we can coalesce the live ranges. Ask the
2335 // intervals to coalesce themselves now.
2336 if ((RHS.ranges.size() > LHS.ranges.size() &&
2337 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2338 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2339 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2343 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2351 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2352 // depth of the basic block (the unsigned), and then on the MBB number.
2353 struct DepthMBBCompare {
2354 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2355 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2356 if (LHS.first > RHS.first) return true; // Deeper loops first
2357 return LHS.first == RHS.first &&
2358 LHS.second->getNumber() < RHS.second->getNumber();
2363 /// getRepIntervalSize - Returns the size of the interval that represents the
2364 /// specified register.
2366 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
2367 return Rc->getRepIntervalSize(Reg);
2370 /// CopyRecSort::operator - Join priority queue sorting function.
2372 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
2373 // Inner loops first.
2374 if (left.LoopDepth > right.LoopDepth)
2376 else if (left.LoopDepth == right.LoopDepth)
2377 if (left.isBackEdge && !right.isBackEdge)
2382 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2383 std::vector<CopyRec> &TryAgain) {
2384 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
2386 std::vector<CopyRec> VirtCopies;
2387 std::vector<CopyRec> PhysCopies;
2388 std::vector<CopyRec> ImpDefCopies;
2389 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
2390 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2392 MachineInstr *Inst = MII++;
2394 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2395 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2396 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
2397 DstReg = Inst->getOperand(0).getReg();
2398 SrcReg = Inst->getOperand(1).getReg();
2399 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2400 Inst->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
2401 DstReg = Inst->getOperand(0).getReg();
2402 SrcReg = Inst->getOperand(2).getReg();
2403 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2406 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2407 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2409 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
2411 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
2412 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
2413 else if (SrcIsPhys || DstIsPhys)
2414 PhysCopies.push_back(CopyRec(Inst, 0, false));
2416 VirtCopies.push_back(CopyRec(Inst, 0, false));
2423 // Try coalescing implicit copies first, followed by copies to / from
2424 // physical registers, then finally copies from virtual registers to
2425 // virtual registers.
2426 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2427 CopyRec &TheCopy = ImpDefCopies[i];
2429 if (!JoinCopy(TheCopy, Again))
2431 TryAgain.push_back(TheCopy);
2433 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2434 CopyRec &TheCopy = PhysCopies[i];
2436 if (!JoinCopy(TheCopy, Again))
2438 TryAgain.push_back(TheCopy);
2440 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2441 CopyRec &TheCopy = VirtCopies[i];
2443 if (!JoinCopy(TheCopy, Again))
2445 TryAgain.push_back(TheCopy);
2449 void SimpleRegisterCoalescing::joinIntervals() {
2450 DOUT << "********** JOINING INTERVALS ***********\n";
2453 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
2455 std::vector<CopyRec> TryAgainList;
2456 if (loopInfo->empty()) {
2457 // If there are no loops in the function, join intervals in function order.
2458 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2460 CopyCoalesceInMBB(I, TryAgainList);
2462 // Otherwise, join intervals in inner loops before other intervals.
2463 // Unfortunately we can't just iterate over loop hierarchy here because
2464 // there may be more MBB's than BB's. Collect MBB's for sorting.
2466 // Join intervals in the function prolog first. We want to join physical
2467 // registers with virtual registers before the intervals got too long.
2468 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2469 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2470 MachineBasicBlock *MBB = I;
2471 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2474 // Sort by loop depth.
2475 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2477 // Finally, join intervals in loop nest order.
2478 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2479 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2482 // Joining intervals can allow other intervals to be joined. Iteratively join
2483 // until we make no progress.
2485 SmallVector<CopyRec, 16> TryAgain;
2486 bool ProgressMade = true;
2487 while (ProgressMade) {
2488 ProgressMade = false;
2489 while (!JoinQueue->empty()) {
2490 CopyRec R = JoinQueue->pop();
2492 bool Success = JoinCopy(R, Again);
2494 ProgressMade = true;
2496 TryAgain.push_back(R);
2500 while (!TryAgain.empty()) {
2501 JoinQueue->push(TryAgain.back());
2502 TryAgain.pop_back();
2507 bool ProgressMade = true;
2508 while (ProgressMade) {
2509 ProgressMade = false;
2511 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2512 CopyRec &TheCopy = TryAgainList[i];
2515 bool Success = JoinCopy(TheCopy, Again);
2516 if (Success || !Again) {
2517 TheCopy.MI = 0; // Mark this one as done.
2518 ProgressMade = true;
2529 /// Return true if the two specified registers belong to different register
2530 /// classes. The registers may be either phys or virt regs.
2532 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2533 unsigned RegB) const {
2534 // Get the register classes for the first reg.
2535 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2536 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2537 "Shouldn't consider two physregs!");
2538 return !mri_->getRegClass(RegB)->contains(RegA);
2541 // Compare against the regclass for the second reg.
2542 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2543 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2544 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2545 return RegClassA != RegClassB;
2547 return !RegClassA->contains(RegB);
2550 /// lastRegisterUse - Returns the last use of the specific register between
2551 /// cycles Start and End or NULL if there are no uses.
2553 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2554 unsigned Reg, unsigned &UseIdx) const{
2556 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2557 MachineOperand *LastUse = NULL;
2558 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2559 E = mri_->use_end(); I != E; ++I) {
2560 MachineOperand &Use = I.getOperand();
2561 MachineInstr *UseMI = Use.getParent();
2562 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2563 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2565 // Ignore identity copies.
2567 unsigned Idx = li_->getInstructionIndex(UseMI);
2568 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2570 UseIdx = li_->getUseIndex(Idx);
2576 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2579 // Skip deleted instructions
2580 MachineInstr *MI = li_->getInstructionFromIndex(e);
2581 while ((e - InstrSlots::NUM) >= s && !MI) {
2582 e -= InstrSlots::NUM;
2583 MI = li_->getInstructionFromIndex(e);
2585 if (e < s || MI == NULL)
2588 // Ignore identity copies.
2589 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2590 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2592 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2593 MachineOperand &Use = MI->getOperand(i);
2594 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2595 tri_->regsOverlap(Use.getReg(), Reg)) {
2596 UseIdx = li_->getUseIndex(e);
2601 e -= InstrSlots::NUM;
2608 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2609 if (TargetRegisterInfo::isPhysicalRegister(reg))
2610 cerr << tri_->getName(reg);
2612 cerr << "%reg" << reg;
2615 void SimpleRegisterCoalescing::releaseMemory() {
2616 JoinedCopies.clear();
2617 ReMatCopies.clear();
2621 static bool isZeroLengthInterval(LiveInterval *li) {
2622 for (LiveInterval::Ranges::const_iterator
2623 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2624 if (i->end - i->start > LiveInterval::InstrSlots::NUM)
2629 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
2630 /// turn the copy into an implicit def.
2632 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
2633 MachineBasicBlock *MBB,
2634 unsigned DstReg, unsigned SrcReg) {
2635 MachineInstr *CopyMI = &*I;
2636 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
2637 if (!li_->hasInterval(SrcReg))
2639 LiveInterval &SrcInt = li_->getInterval(SrcReg);
2640 if (!SrcInt.empty())
2642 if (!li_->hasInterval(DstReg))
2644 LiveInterval &DstInt = li_->getInterval(DstReg);
2645 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
2646 // If the valno extends beyond this basic block, then it's not safe to delete
2647 // the val# or else livein information won't be correct.
2648 MachineBasicBlock *EndMBB = li_->getMBBFromIndex(DstLR->end);
2651 DstInt.removeValNo(DstLR->valno);
2652 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
2653 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
2654 CopyMI->RemoveOperand(i);
2655 bool NoUse = mri_->use_empty(SrcReg);
2657 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
2658 E = mri_->reg_end(); I != E; ) {
2659 assert(I.getOperand().isDef());
2660 MachineInstr *DefMI = &*I;
2662 // The implicit_def source has no other uses, delete it.
2663 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2664 li_->RemoveMachineInstrFromMaps(DefMI);
2665 DefMI->eraseFromParent();
2673 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2675 mri_ = &fn.getRegInfo();
2676 tm_ = &fn.getTarget();
2677 tri_ = tm_->getRegisterInfo();
2678 tii_ = tm_->getInstrInfo();
2679 li_ = &getAnalysis<LiveIntervals>();
2680 loopInfo = &getAnalysis<MachineLoopInfo>();
2682 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2683 << "********** Function: "
2684 << ((Value*)mf_->getFunction())->getName() << '\n';
2686 allocatableRegs_ = tri_->getAllocatableSet(fn);
2687 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2688 E = tri_->regclass_end(); I != E; ++I)
2689 allocatableRCRegs_.insert(std::make_pair(*I,
2690 tri_->getAllocatableSet(fn, *I)));
2692 // Join (coalesce) intervals if requested.
2693 if (EnableJoining) {
2696 DOUT << "********** INTERVALS POST JOINING **********\n";
2697 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2698 I->second->print(DOUT, tri_);
2704 // Perform a final pass over the instructions and compute spill weights
2705 // and remove identity moves.
2706 SmallVector<unsigned, 4> DeadDefs;
2707 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2708 mbbi != mbbe; ++mbbi) {
2709 MachineBasicBlock* mbb = mbbi;
2710 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2712 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2714 MachineInstr *MI = mii;
2715 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2716 if (JoinedCopies.count(MI)) {
2717 // Delete all coalesced copies.
2718 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2719 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2720 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2721 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
2722 "Unrecognized copy instruction");
2723 DstReg = MI->getOperand(0).getReg();
2725 if (MI->registerDefIsDead(DstReg)) {
2726 LiveInterval &li = li_->getInterval(DstReg);
2727 if (!ShortenDeadCopySrcLiveRange(li, MI))
2728 ShortenDeadCopyLiveRange(li, MI);
2730 li_->RemoveMachineInstrFromMaps(MI);
2731 mii = mbbi->erase(mii);
2736 // Now check if this is a remat'ed def instruction which is now dead.
2737 if (ReMatDefs.count(MI)) {
2739 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2740 const MachineOperand &MO = MI->getOperand(i);
2743 unsigned Reg = MO.getReg();
2746 if (TargetRegisterInfo::isVirtualRegister(Reg))
2747 DeadDefs.push_back(Reg);
2750 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2751 !mri_->use_empty(Reg)) {
2757 while (!DeadDefs.empty()) {
2758 unsigned DeadDef = DeadDefs.back();
2759 DeadDefs.pop_back();
2760 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2762 li_->RemoveMachineInstrFromMaps(mii);
2763 mii = mbbi->erase(mii);
2769 // If the move will be an identity move delete it
2770 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2771 if (isMove && SrcReg == DstReg) {
2772 if (li_->hasInterval(SrcReg)) {
2773 LiveInterval &RegInt = li_->getInterval(SrcReg);
2774 // If def of this move instruction is dead, remove its live range
2775 // from the dstination register's live interval.
2776 if (MI->registerDefIsDead(DstReg)) {
2777 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2778 ShortenDeadCopyLiveRange(RegInt, MI);
2781 li_->RemoveMachineInstrFromMaps(MI);
2782 mii = mbbi->erase(mii);
2784 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2785 SmallSet<unsigned, 4> UniqueUses;
2786 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2787 const MachineOperand &mop = MI->getOperand(i);
2788 if (mop.isReg() && mop.getReg() &&
2789 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2790 unsigned reg = mop.getReg();
2791 // Multiple uses of reg by the same instruction. It should not
2792 // contribute to spill weight again.
2793 if (UniqueUses.count(reg) != 0)
2795 LiveInterval &RegInt = li_->getInterval(reg);
2797 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2798 UniqueUses.insert(reg);
2806 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2807 LiveInterval &LI = *I->second;
2808 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2809 // If the live interval length is essentially zero, i.e. in every live
2810 // range the use follows def immediately, it doesn't make sense to spill
2811 // it and hope it will be easier to allocate for this li.
2812 if (isZeroLengthInterval(&LI))
2813 LI.weight = HUGE_VALF;
2815 bool isLoad = false;
2816 SmallVector<LiveInterval*, 4> SpillIs;
2817 if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
2818 // If all of the definitions of the interval are re-materializable,
2819 // it is a preferred candidate for spilling. If non of the defs are
2820 // loads, then it's potentially very cheap to re-materialize.
2821 // FIXME: this gets much more complicated once we support non-trivial
2822 // re-materialization.
2830 // Slightly prefer live interval that has been assigned a preferred reg.
2831 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(LI.reg);
2832 if (Hint.first || Hint.second)
2835 // Divide the weight of the interval by its size. This encourages
2836 // spilling of intervals that are large and have few uses, and
2837 // discourages spilling of small intervals with many uses.
2838 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2846 /// print - Implement the dump method.
2847 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2851 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2852 return new SimpleRegisterCoalescing();
2855 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2856 DEFINING_FILE_FOR(SimpleRegisterCoalescing)