1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "llvm/CodeGen/SimpleRegisterCoalescing.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "VirtRegMap.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/LoopInfo.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numJoins , "Number of interval joins performed");
40 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
41 STATISTIC(numAborts , "Number of times interval joining aborted");
43 char SimpleRegisterCoalescing::ID = 0;
46 EnableJoining("join-liveintervals",
47 cl::desc("Coalesce copies (default=true)"),
50 RegisterPass<SimpleRegisterCoalescing>
51 X("simple-register-coalescing", "Simple Register Coalescing");
53 // Declare that we implement the RegisterCoalescer interface
54 RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
57 const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo();
59 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
60 //AU.addPreserved<LiveVariables>();
61 AU.addPreserved<LiveIntervals>();
62 AU.addPreservedID(PHIEliminationID);
63 AU.addPreservedID(TwoAddressInstructionPassID);
64 AU.addRequired<LiveVariables>();
65 AU.addRequired<LiveIntervals>();
66 AU.addRequired<LoopInfo>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
71 /// being the source and IntB being the dest, thus this defines a value number
72 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
73 /// see if we can merge these two pieces of B into a single value number,
74 /// eliminating a copy. For example:
78 /// B1 = A3 <- this copy
80 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
81 /// value number to be replaced with B0 (which simplifies the B liveinterval).
83 /// This returns true if an interval was modified.
85 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
86 MachineInstr *CopyMI) {
87 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
89 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
91 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
92 VNInfo *BValNo = BLR->valno;
94 // Get the location that B is defined at. Two options: either this value has
95 // an unknown definition point or it is defined at CopyIdx. If unknown, we
97 if (!BValNo->reg) return false;
98 assert(BValNo->def == CopyIdx &&
99 "Copy doesn't define the value?");
101 // AValNo is the value number in A that defines the copy, A0 in the example.
102 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
103 VNInfo *AValNo = AValLR->valno;
105 // If AValNo is defined as a copy from IntB, we can potentially process this.
107 // Get the instruction that defines this value number.
108 unsigned SrcReg = AValNo->reg;
109 if (!SrcReg) return false; // Not defined by a copy.
111 // If the value number is not defined by a copy instruction, ignore it.
113 // If the source register comes from an interval other than IntB, we can't
115 if (rep(SrcReg) != IntB.reg) return false;
117 // Get the LiveRange in IntB that this value number starts with.
118 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
120 // Make sure that the end of the live range is inside the same block as
122 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
124 ValLREndInst->getParent() != CopyMI->getParent()) return false;
126 // Okay, we now know that ValLR ends in the same block that the CopyMI
127 // live-range starts. If there are no intervening live ranges between them in
128 // IntB, we can merge them.
129 if (ValLR+1 != BLR) return false;
131 // If a live interval is a physical register, conservatively check if any
132 // of its sub-registers is overlapping the live interval of the virtual
133 // register. If so, do not coalesce.
134 if (MRegisterInfo::isPhysicalRegister(IntB.reg) &&
135 *mri_->getSubRegisters(IntB.reg)) {
136 for (const unsigned* SR = mri_->getSubRegisters(IntB.reg); *SR; ++SR)
137 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
138 DOUT << "Interfere with sub-register ";
139 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
144 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
146 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
147 // We are about to delete CopyMI, so need to remove it as the 'instruction
148 // that defines this value #'. Update the the valnum with the new defining
150 BValNo->def = FillerStart;
153 // Okay, we can merge them. We need to insert a new liverange:
154 // [ValLR.end, BLR.begin) of either value number, then we merge the
155 // two value numbers.
156 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
158 // If the IntB live range is assigned to a physical register, and if that
159 // physreg has aliases,
160 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
161 // Update the liveintervals of sub-registers.
162 for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
163 LiveInterval &AliasLI = li_->getInterval(*AS);
164 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
165 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
169 // Okay, merge "B1" into the same value number as "B0".
170 if (BValNo != ValLR->valno)
171 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
172 DOUT << " result = "; IntB.print(DOUT, mri_);
175 // If the source instruction was killing the source register before the
176 // merge, unset the isKill marker given the live range has been extended.
177 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
179 ValLREndInst->getOperand(UIdx).unsetIsKill();
181 // Finally, delete the copy instruction.
182 li_->RemoveMachineInstrFromMaps(CopyMI);
183 CopyMI->eraseFromParent();
188 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
189 /// which are the src/dst of the copy instruction CopyMI. This returns true
190 /// if the copy was successfully coalesced away, or if it is never possible
191 /// to coalesce this copy, due to register constraints. It returns
192 /// false if it is not currently possible to coalesce this interval, but
193 /// it may be possible if other things get coalesced.
194 bool SimpleRegisterCoalescing::JoinCopy(MachineInstr *CopyMI,
195 unsigned SrcReg, unsigned DstReg, bool PhysOnly) {
196 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
198 // Get representative registers.
199 unsigned repSrcReg = rep(SrcReg);
200 unsigned repDstReg = rep(DstReg);
202 // If they are already joined we continue.
203 if (repSrcReg == repDstReg) {
204 DOUT << "\tCopy already coalesced.\n";
205 return true; // Not coalescable.
208 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
209 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
210 if (PhysOnly && !SrcIsPhys && !DstIsPhys)
211 // Only joining physical registers with virtual registers in this round.
214 // If they are both physical registers, we cannot join them.
215 if (SrcIsPhys && DstIsPhys) {
216 DOUT << "\tCan not coalesce physregs.\n";
217 return true; // Not coalescable.
220 // We only join virtual registers with allocatable physical registers.
221 if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
222 DOUT << "\tSrc reg is unallocatable physreg.\n";
223 return true; // Not coalescable.
225 if (DstIsPhys && !allocatableRegs_[repDstReg]) {
226 DOUT << "\tDst reg is unallocatable physreg.\n";
227 return true; // Not coalescable.
230 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
231 unsigned RealDstReg = 0;
233 unsigned SubIdx = CopyMI->getOperand(2).getImm();
235 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
236 // coalesced with AX.
237 repSrcReg = mri_->getSubReg(repSrcReg, SubIdx);
238 else if (DstIsPhys) {
239 // If this is a extract_subreg where dst is a physical register, e.g.
240 // cl = EXTRACT_SUBREG reg1024, 1
241 // then create and update the actual physical register allocated to RHS.
242 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(SrcReg);
243 for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg);
244 unsigned SR = *SRs; ++SRs) {
245 if (repDstReg == mri_->getSubReg(SR, SubIdx) &&
251 assert(RealDstReg && "Invalid extra_subreg instruction!");
253 // For this type of EXTRACT_SUBREG, conservatively
254 // check if the live interval of the source register interfere with the
255 // actual super physical register we are trying to coalesce with.
256 LiveInterval &RHS = li_->getInterval(repSrcReg);
257 if (li_->hasInterval(RealDstReg) &&
258 RHS.overlaps(li_->getInterval(RealDstReg))) {
259 DOUT << "Interfere with register ";
260 DEBUG(li_->getInterval(RealDstReg).print(DOUT, mri_));
261 return true; // Not coalescable
263 for (const unsigned* SR = mri_->getSubRegisters(RealDstReg); *SR; ++SR)
264 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
265 DOUT << "Interfere with sub-register ";
266 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
267 return true; // Not coalescable
269 } else if (li_->getInterval(repDstReg).getSize() >
270 li_->getInterval(repSrcReg).getSize()) {
271 // Be conservative. If both sides are virtual registers, do not coalesce
272 // if the sub-register live interval is longer.
275 } else if (differingRegisterClasses(repSrcReg, repDstReg)) {
276 // If they are not of the same register class, we cannot join them.
277 DOUT << "\tSrc/Dest are different register classes.\n";
278 // Allow the coalescer to try again in case either side gets coalesced to
279 // a physical register that's compatible with the other side. e.g.
280 // r1024 = MOV32to32_ r1025
281 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
285 LiveInterval &SrcInt = li_->getInterval(repSrcReg);
286 LiveInterval &DstInt = li_->getInterval(repDstReg);
287 assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
288 "Register mapping is horribly broken!");
290 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
291 DOUT << " and "; DstInt.print(DOUT, mri_);
294 // Check if it is necessary to propagate "isDead" property before intervals
296 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
297 bool isDead = mopd->isDead();
298 bool isShorten = false;
299 unsigned SrcStart = 0, RemoveStart = 0;
300 unsigned SrcEnd = 0, RemoveEnd = 0;
302 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
303 LiveInterval::iterator SrcLR =
304 SrcInt.FindLiveRangeContaining(li_->getUseIndex(CopyIdx));
305 RemoveStart = SrcStart = SrcLR->start;
306 RemoveEnd = SrcEnd = SrcLR->end;
307 // The instruction which defines the src is only truly dead if there are
308 // no intermediate uses and there isn't a use beyond the copy.
309 // FIXME: find the last use, mark is kill and shorten the live range.
310 if (SrcEnd > li_->getDefIndex(CopyIdx)) {
314 MachineInstr *LastUse= lastRegisterUse(SrcStart, CopyIdx, repSrcReg, MOU);
316 // Shorten the liveinterval to the end of last use.
320 RemoveStart = li_->getDefIndex(li_->getInstructionIndex(LastUse));
323 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
325 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
327 // A dead def should have a single cycle interval.
334 // We need to be careful about coalescing a source physical register with a
335 // virtual register. Once the coalescing is done, it cannot be broken and
336 // these are not spillable! If the destination interval uses are far away,
337 // think twice about coalescing them!
338 if (!mopd->isDead() && (SrcIsPhys || DstIsPhys) && !isExtSubReg) {
339 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
340 unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
341 unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
342 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg);
343 unsigned Threshold = allocatableRCRegs_[RC].count();
345 // If the virtual register live interval is long but it has low use desity,
346 // do not join them, instead mark the physical register as its allocation
348 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
349 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
350 if (Length > Threshold &&
351 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
352 JoinVInt.preference = JoinPReg;
354 DOUT << "\tMay tie down a physical register, abort!\n";
359 // Okay, attempt to join these two intervals. On failure, this returns false.
360 // Otherwise, if one of the intervals being joined is a physreg, this method
361 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
362 // been modified, so we can use this information below to update aliases.
363 bool Swapped = false;
364 if (JoinIntervals(DstInt, SrcInt, Swapped)) {
366 // Result of the copy is dead. Propagate this property.
368 assert(MRegisterInfo::isPhysicalRegister(repSrcReg) &&
369 "Live-in must be a physical register!");
370 // Live-in to the function but dead. Remove it from entry live-in set.
371 // JoinIntervals may end up swapping the two intervals.
372 mf_->begin()->removeLiveIn(repSrcReg);
374 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
376 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
383 if (isShorten || isDead) {
384 // Shorten the destination live interval.
386 SrcInt.removeRange(RemoveStart, RemoveEnd);
389 // Coalescing failed.
391 // If we can eliminate the copy without merging the live ranges, do so now.
392 if (!isExtSubReg && AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI))
395 // Otherwise, we are unable to join the intervals.
396 DOUT << "Interference!\n";
400 LiveInterval *ResSrcInt = &SrcInt;
401 LiveInterval *ResDstInt = &DstInt;
403 std::swap(repSrcReg, repDstReg);
404 std::swap(ResSrcInt, ResDstInt);
406 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
407 "LiveInterval::join didn't work right!");
409 // If we're about to merge live ranges into a physical register live range,
410 // we have to update any aliased register's live ranges to indicate that they
411 // have clobbered values for this range.
412 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
413 // Unset unnecessary kills.
414 if (!ResDstInt->containsOneValue()) {
415 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(),
416 E = ResSrcInt->end(); I != E; ++I)
417 unsetRegisterKills(I->start, I->end, repDstReg);
420 // If this is a extract_subreg where dst is a physical register, e.g.
421 // cl = EXTRACT_SUBREG reg1024, 1
422 // then create and update the actual physical register allocated to RHS.
424 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
426 ResDstInt->getLiveRangeContaining(li_->getUseIndex(CopyIdx))->valno;
427 LiveInterval &RealDstInt = li_->getOrCreateInterval(RealDstReg);
428 VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->reg,
429 li_->getVNInfoAllocator());
430 RealDstInt.addKills(ValNo, DstValNo->kills);
431 RealDstInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
432 repDstReg = RealDstReg;
435 // Update the liveintervals of sub-registers.
436 for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
437 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
438 li_->getVNInfoAllocator());
440 // Merge use info if the destination is a virtual register.
441 LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
442 LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg);
443 dVI.NumUses += sVI.NumUses;
446 // Remember these liveintervals have been joined.
447 JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister);
448 if (MRegisterInfo::isVirtualRegister(repDstReg))
449 JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister);
451 if (isExtSubReg && !SrcIsPhys && !DstIsPhys) {
453 // Make sure we allocate the larger super-register.
454 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
455 std::swap(repSrcReg, repDstReg);
456 std::swap(ResSrcInt, ResDstInt);
458 SubRegIdxes.push_back(std::make_pair(repSrcReg,
459 CopyMI->getOperand(2).getImm()));
462 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_);
465 // repSrcReg is guarateed to be the register whose live interval that is
467 li_->removeInterval(repSrcReg);
468 r2rMap_[repSrcReg] = repDstReg;
470 // Finally, delete the copy instruction.
471 li_->RemoveMachineInstrFromMaps(CopyMI);
472 CopyMI->eraseFromParent();
478 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
479 /// compute what the resultant value numbers for each value in the input two
480 /// ranges will be. This is complicated by copies between the two which can
481 /// and will commonly cause multiple value numbers to be merged into one.
483 /// VN is the value number that we're trying to resolve. InstDefiningValue
484 /// keeps track of the new InstDefiningValue assignment for the result
485 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
486 /// whether a value in this or other is a copy from the opposite set.
487 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
488 /// already been assigned.
490 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
491 /// contains the value number the copy is from.
493 static unsigned ComputeUltimateVN(VNInfo *VNI,
494 SmallVector<VNInfo*, 16> &NewVNInfo,
495 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
496 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
497 SmallVector<int, 16> &ThisValNoAssignments,
498 SmallVector<int, 16> &OtherValNoAssignments) {
499 unsigned VN = VNI->id;
501 // If the VN has already been computed, just return it.
502 if (ThisValNoAssignments[VN] >= 0)
503 return ThisValNoAssignments[VN];
504 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
506 // If this val is not a copy from the other val, then it must be a new value
507 // number in the destination.
508 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
509 if (I == ThisFromOther.end()) {
510 NewVNInfo.push_back(VNI);
511 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
513 VNInfo *OtherValNo = I->second;
515 // Otherwise, this *is* a copy from the RHS. If the other side has already
516 // been computed, return it.
517 if (OtherValNoAssignments[OtherValNo->id] >= 0)
518 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
520 // Mark this value number as currently being computed, then ask what the
521 // ultimate value # of the other value is.
522 ThisValNoAssignments[VN] = -2;
523 unsigned UltimateVN =
524 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
525 OtherValNoAssignments, ThisValNoAssignments);
526 return ThisValNoAssignments[VN] = UltimateVN;
529 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
530 return std::find(V.begin(), V.end(), Val) != V.end();
533 /// SimpleJoin - Attempt to joint the specified interval into this one. The
534 /// caller of this method must guarantee that the RHS only contains a single
535 /// value number and that the RHS is not defined by a copy from this
536 /// interval. This returns false if the intervals are not joinable, or it
537 /// joins them and returns true.
538 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
539 assert(RHS.containsOneValue());
541 // Some number (potentially more than one) value numbers in the current
542 // interval may be defined as copies from the RHS. Scan the overlapping
543 // portions of the LHS and RHS, keeping track of this and looking for
544 // overlapping live ranges that are NOT defined as copies. If these exist, we
547 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
548 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
550 if (LHSIt->start < RHSIt->start) {
551 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
552 if (LHSIt != LHS.begin()) --LHSIt;
553 } else if (RHSIt->start < LHSIt->start) {
554 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
555 if (RHSIt != RHS.begin()) --RHSIt;
558 SmallVector<VNInfo*, 8> EliminatedLHSVals;
561 // Determine if these live intervals overlap.
562 bool Overlaps = false;
563 if (LHSIt->start <= RHSIt->start)
564 Overlaps = LHSIt->end > RHSIt->start;
566 Overlaps = RHSIt->end > LHSIt->start;
568 // If the live intervals overlap, there are two interesting cases: if the
569 // LHS interval is defined by a copy from the RHS, it's ok and we record
570 // that the LHS value # is the same as the RHS. If it's not, then we cannot
571 // coalesce these live ranges and we bail out.
573 // If we haven't already recorded that this value # is safe, check it.
574 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
575 // Copy from the RHS?
576 unsigned SrcReg = LHSIt->valno->reg;
577 if (rep(SrcReg) != RHS.reg)
578 return false; // Nope, bail out.
580 EliminatedLHSVals.push_back(LHSIt->valno);
583 // We know this entire LHS live range is okay, so skip it now.
584 if (++LHSIt == LHSEnd) break;
588 if (LHSIt->end < RHSIt->end) {
589 if (++LHSIt == LHSEnd) break;
591 // One interesting case to check here. It's possible that we have
592 // something like "X3 = Y" which defines a new value number in the LHS,
593 // and is the last use of this liverange of the RHS. In this case, we
594 // want to notice this copy (so that it gets coalesced away) even though
595 // the live ranges don't actually overlap.
596 if (LHSIt->start == RHSIt->end) {
597 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
598 // We already know that this value number is going to be merged in
599 // if coalescing succeeds. Just skip the liverange.
600 if (++LHSIt == LHSEnd) break;
602 // Otherwise, if this is a copy from the RHS, mark it as being merged
604 if (rep(LHSIt->valno->reg) == RHS.reg) {
605 EliminatedLHSVals.push_back(LHSIt->valno);
607 // We know this entire LHS live range is okay, so skip it now.
608 if (++LHSIt == LHSEnd) break;
613 if (++RHSIt == RHSEnd) break;
617 // If we got here, we know that the coalescing will be successful and that
618 // the value numbers in EliminatedLHSVals will all be merged together. Since
619 // the most common case is that EliminatedLHSVals has a single number, we
620 // optimize for it: if there is more than one value, we merge them all into
621 // the lowest numbered one, then handle the interval as if we were merging
622 // with one value number.
624 if (EliminatedLHSVals.size() > 1) {
625 // Loop through all the equal value numbers merging them into the smallest
627 VNInfo *Smallest = EliminatedLHSVals[0];
628 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
629 if (EliminatedLHSVals[i]->id < Smallest->id) {
630 // Merge the current notion of the smallest into the smaller one.
631 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
632 Smallest = EliminatedLHSVals[i];
634 // Merge into the smallest.
635 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
640 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
641 LHSValNo = EliminatedLHSVals[0];
644 // Okay, now that there is a single LHS value number that we're merging the
645 // RHS into, update the value number info for the LHS to indicate that the
646 // value number is defined where the RHS value number was.
647 const VNInfo *VNI = RHS.getValNumInfo(0);
648 LHSValNo->def = VNI->def;
649 LHSValNo->reg = VNI->reg;
651 // Okay, the final step is to loop over the RHS live intervals, adding them to
653 LHS.addKills(LHSValNo, VNI->kills);
654 LHS.MergeRangesInAsValue(RHS, LHSValNo);
655 LHS.weight += RHS.weight;
656 if (RHS.preference && !LHS.preference)
657 LHS.preference = RHS.preference;
662 /// JoinIntervals - Attempt to join these two intervals. On failure, this
663 /// returns false. Otherwise, if one of the intervals being joined is a
664 /// physreg, this method always canonicalizes LHS to be it. The output
665 /// "RHS" will not have been modified, so we can use this information
666 /// below to update aliases.
667 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
668 LiveInterval &RHS, bool &Swapped) {
669 // Compute the final value assignment, assuming that the live ranges can be
671 SmallVector<int, 16> LHSValNoAssignments;
672 SmallVector<int, 16> RHSValNoAssignments;
673 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
674 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
675 SmallVector<VNInfo*, 16> NewVNInfo;
677 // If a live interval is a physical register, conservatively check if any
678 // of its sub-registers is overlapping the live interval of the virtual
679 // register. If so, do not coalesce.
680 if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
681 *mri_->getSubRegisters(LHS.reg)) {
682 for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
683 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
684 DOUT << "Interfere with sub-register ";
685 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
688 } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
689 *mri_->getSubRegisters(RHS.reg)) {
690 for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
691 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
692 DOUT << "Interfere with sub-register ";
693 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
698 // Compute ultimate value numbers for the LHS and RHS values.
699 if (RHS.containsOneValue()) {
700 // Copies from a liveinterval with a single value are simple to handle and
701 // very common, handle the special case here. This is important, because
702 // often RHS is small and LHS is large (e.g. a physreg).
704 // Find out if the RHS is defined as a copy from some value in the LHS.
705 int RHSVal0DefinedFromLHS = -1;
707 VNInfo *RHSValNoInfo = NULL;
708 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
709 unsigned RHSSrcReg = RHSValNoInfo0->reg;
710 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
711 // If RHS is not defined as a copy from the LHS, we can use simpler and
712 // faster checks to see if the live ranges are coalescable. This joiner
713 // can't swap the LHS/RHS intervals though.
714 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
715 return SimpleJoin(LHS, RHS);
717 RHSValNoInfo = RHSValNoInfo0;
720 // It was defined as a copy from the LHS, find out what value # it is.
721 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
722 RHSValID = RHSValNoInfo->id;
723 RHSVal0DefinedFromLHS = RHSValID;
726 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
727 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
728 NewVNInfo.resize(LHS.getNumValNums(), NULL);
730 // Okay, *all* of the values in LHS that are defined as a copy from RHS
731 // should now get updated.
732 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
735 unsigned VN = VNI->id;
736 if (unsigned LHSSrcReg = VNI->reg) {
737 if (rep(LHSSrcReg) != RHS.reg) {
738 // If this is not a copy from the RHS, its value number will be
739 // unmodified by the coalescing.
741 LHSValNoAssignments[VN] = VN;
742 } else if (RHSValID == -1) {
743 // Otherwise, it is a copy from the RHS, and we don't already have a
744 // value# for it. Keep the current value number, but remember it.
745 LHSValNoAssignments[VN] = RHSValID = VN;
746 NewVNInfo[VN] = RHSValNoInfo;
747 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
749 // Otherwise, use the specified value #.
750 LHSValNoAssignments[VN] = RHSValID;
751 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
752 NewVNInfo[VN] = RHSValNoInfo;
753 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
758 LHSValNoAssignments[VN] = VN;
762 assert(RHSValID != -1 && "Didn't find value #?");
763 RHSValNoAssignments[0] = RHSValID;
764 if (RHSVal0DefinedFromLHS != -1) {
765 // This path doesn't go through ComputeUltimateVN so just set
767 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
770 // Loop over the value numbers of the LHS, seeing if any are defined from
772 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
775 unsigned ValSrcReg = VNI->reg;
776 if (ValSrcReg == 0) // Src not defined by a copy?
779 // DstReg is known to be a register in the LHS interval. If the src is
780 // from the RHS interval, we can use its value #.
781 if (rep(ValSrcReg) != RHS.reg)
784 // Figure out the value # from the RHS.
785 LHSValsDefinedFromRHS[VNI] = RHS.getLiveRangeContaining(VNI->def-1)->valno;
788 // Loop over the value numbers of the RHS, seeing if any are defined from
790 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
793 unsigned ValSrcReg = VNI->reg;
794 if (ValSrcReg == 0) // Src not defined by a copy?
797 // DstReg is known to be a register in the RHS interval. If the src is
798 // from the LHS interval, we can use its value #.
799 if (rep(ValSrcReg) != LHS.reg)
802 // Figure out the value # from the LHS.
803 RHSValsDefinedFromLHS[VNI]= LHS.getLiveRangeContaining(VNI->def-1)->valno;
806 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
807 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
808 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
810 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
813 unsigned VN = VNI->id;
814 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
816 ComputeUltimateVN(VNI, NewVNInfo,
817 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
818 LHSValNoAssignments, RHSValNoAssignments);
820 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
823 unsigned VN = VNI->id;
824 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
826 // If this value number isn't a copy from the LHS, it's a new number.
827 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
828 NewVNInfo.push_back(VNI);
829 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
833 ComputeUltimateVN(VNI, NewVNInfo,
834 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
835 RHSValNoAssignments, LHSValNoAssignments);
839 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
840 // interval lists to see if these intervals are coalescable.
841 LiveInterval::const_iterator I = LHS.begin();
842 LiveInterval::const_iterator IE = LHS.end();
843 LiveInterval::const_iterator J = RHS.begin();
844 LiveInterval::const_iterator JE = RHS.end();
846 // Skip ahead until the first place of potential sharing.
847 if (I->start < J->start) {
848 I = std::upper_bound(I, IE, J->start);
849 if (I != LHS.begin()) --I;
850 } else if (J->start < I->start) {
851 J = std::upper_bound(J, JE, I->start);
852 if (J != RHS.begin()) --J;
856 // Determine if these two live ranges overlap.
858 if (I->start < J->start) {
859 Overlaps = I->end > J->start;
861 Overlaps = J->end > I->start;
864 // If so, check value # info to determine if they are really different.
866 // If the live range overlap will map to the same value number in the
867 // result liverange, we can still coalesce them. If not, we can't.
868 if (LHSValNoAssignments[I->valno->id] !=
869 RHSValNoAssignments[J->valno->id])
873 if (I->end < J->end) {
882 // If we get here, we know that we can coalesce the live ranges. Ask the
883 // intervals to coalesce themselves now.
884 if ((RHS.ranges.size() > LHS.ranges.size() &&
885 MRegisterInfo::isVirtualRegister(LHS.reg)) ||
886 MRegisterInfo::isPhysicalRegister(RHS.reg)) {
887 // Update kill info. Some live ranges are extended due to copy coalescing.
888 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
889 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
890 VNInfo *VNI = I->first;
891 unsigned LHSValID = LHSValNoAssignments[VNI->id];
892 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
893 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
896 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
899 // Update kill info. Some live ranges are extended due to copy coalescing.
900 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
901 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
902 VNInfo *VNI = I->first;
903 unsigned RHSValID = RHSValNoAssignments[VNI->id];
904 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
905 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
908 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
915 // DepthMBBCompare - Comparison predicate that sort first based on the loop
916 // depth of the basic block (the unsigned), and then on the MBB number.
917 struct DepthMBBCompare {
918 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
919 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
920 if (LHS.first > RHS.first) return true; // Deeper loops first
921 return LHS.first == RHS.first &&
922 LHS.second->getNumber() < RHS.second->getNumber();
927 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
928 std::vector<CopyRec> *TryAgain, bool PhysOnly) {
929 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
931 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
933 MachineInstr *Inst = MII++;
935 // If this isn't a copy nor a extract_subreg, we can't join intervals.
936 unsigned SrcReg, DstReg;
937 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
938 DstReg = Inst->getOperand(0).getReg();
939 SrcReg = Inst->getOperand(1).getReg();
940 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
943 bool Done = JoinCopy(Inst, SrcReg, DstReg, PhysOnly);
944 if (TryAgain && !Done)
945 TryAgain->push_back(getCopyRec(Inst, SrcReg, DstReg));
949 void SimpleRegisterCoalescing::joinIntervals() {
950 DOUT << "********** JOINING INTERVALS ***********\n";
952 JoinedLIs.resize(li_->getNumIntervals());
955 std::vector<CopyRec> TryAgainList;
956 const LoopInfo &LI = getAnalysis<LoopInfo>();
957 if (LI.begin() == LI.end()) {
958 // If there are no loops in the function, join intervals in function order.
959 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
961 CopyCoalesceInMBB(I, &TryAgainList);
963 // Otherwise, join intervals in inner loops before other intervals.
964 // Unfortunately we can't just iterate over loop hierarchy here because
965 // there may be more MBB's than BB's. Collect MBB's for sorting.
967 // Join intervals in the function prolog first. We want to join physical
968 // registers with virtual registers before the intervals got too long.
969 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
970 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); I != E;++I)
971 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
973 // Sort by loop depth.
974 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
976 // Finally, join intervals in loop nest order.
977 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
978 CopyCoalesceInMBB(MBBs[i].second, NULL, true);
979 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
980 CopyCoalesceInMBB(MBBs[i].second, &TryAgainList, false);
983 // Joining intervals can allow other intervals to be joined. Iteratively join
984 // until we make no progress.
985 bool ProgressMade = true;
986 while (ProgressMade) {
987 ProgressMade = false;
989 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
990 CopyRec &TheCopy = TryAgainList[i];
992 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
993 TheCopy.MI = 0; // Mark this one as done.
999 // Some live range has been lengthened due to colaescing, eliminate the
1000 // unnecessary kills.
1001 int RegNum = JoinedLIs.find_first();
1002 while (RegNum != -1) {
1003 unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister;
1004 unsigned repReg = rep(Reg);
1005 LiveInterval &LI = li_->getInterval(repReg);
1006 LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg);
1007 for (unsigned i = 0, e = svi.Kills.size(); i != e; ++i) {
1008 MachineInstr *Kill = svi.Kills[i];
1009 // Suppose vr1 = op vr2, x
1010 // and vr1 and vr2 are coalesced. vr2 should still be marked kill
1011 // unless it is a two-address operand.
1012 if (li_->isRemoved(Kill) || hasRegisterDef(Kill, repReg))
1014 if (LI.liveAt(li_->getInstructionIndex(Kill) + InstrSlots::NUM))
1015 unsetRegisterKill(Kill, repReg);
1017 RegNum = JoinedLIs.find_next(RegNum);
1020 DOUT << "*** Register mapping ***\n";
1021 for (int i = 0, e = r2rMap_.size(); i != e; ++i)
1023 DOUT << " reg " << i << " -> ";
1024 DEBUG(printRegName(r2rMap_[i]));
1029 /// Return true if the two specified registers belong to different register
1030 /// classes. The registers may be either phys or virt regs.
1031 bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1032 unsigned RegB) const {
1034 // Get the register classes for the first reg.
1035 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1036 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1037 "Shouldn't consider two physregs!");
1038 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1041 // Compare against the regclass for the second reg.
1042 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1043 if (MRegisterInfo::isVirtualRegister(RegB))
1044 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1046 return !RegClass->contains(RegB);
1049 /// lastRegisterUse - Returns the last use of the specific register between
1050 /// cycles Start and End. It also returns the use operand by reference. It
1051 /// returns NULL if there are no uses.
1053 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
1054 MachineOperand *&MOU) {
1055 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1058 // Skip deleted instructions
1059 MachineInstr *MI = li_->getInstructionFromIndex(e);
1060 while ((e - InstrSlots::NUM) >= s && !MI) {
1061 e -= InstrSlots::NUM;
1062 MI = li_->getInstructionFromIndex(e);
1064 if (e < s || MI == NULL)
1067 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1068 MachineOperand &MO = MI->getOperand(i);
1069 if (MO.isRegister() && MO.isUse() && MO.getReg() &&
1070 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1076 e -= InstrSlots::NUM;
1083 /// findDefOperand - Returns the MachineOperand that is a def of the specific
1084 /// register. It returns NULL if the def is not found.
1085 MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) {
1086 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1087 MachineOperand &MO = MI->getOperand(i);
1088 if (MO.isRegister() && MO.isDef() &&
1089 mri_->regsOverlap(rep(MO.getReg()), Reg))
1095 /// unsetRegisterKill - Unset IsKill property of all uses of specific register
1096 /// of the specific instruction.
1097 void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
1098 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1099 MachineOperand &MO = MI->getOperand(i);
1100 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1101 mri_->regsOverlap(rep(MO.getReg()), Reg))
1106 /// unsetRegisterKills - Unset IsKill property of all uses of specific register
1107 /// between cycles Start and End.
1108 void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
1110 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1113 // Skip deleted instructions
1114 MachineInstr *MI = li_->getInstructionFromIndex(e);
1115 while ((e - InstrSlots::NUM) >= s && !MI) {
1116 e -= InstrSlots::NUM;
1117 MI = li_->getInstructionFromIndex(e);
1119 if (e < s || MI == NULL)
1122 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1123 MachineOperand &MO = MI->getOperand(i);
1124 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1125 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1130 e -= InstrSlots::NUM;
1134 /// hasRegisterDef - True if the instruction defines the specific register.
1136 bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
1137 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1138 MachineOperand &MO = MI->getOperand(i);
1139 if (MO.isRegister() && MO.isDef() &&
1140 mri_->regsOverlap(rep(MO.getReg()), Reg))
1146 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
1147 if (MRegisterInfo::isPhysicalRegister(reg))
1148 cerr << mri_->getName(reg);
1150 cerr << "%reg" << reg;
1153 void SimpleRegisterCoalescing::releaseMemory() {
1156 SubRegIdxes.clear();
1159 static bool isZeroLengthInterval(LiveInterval *li) {
1160 for (LiveInterval::Ranges::const_iterator
1161 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
1162 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
1167 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1169 tm_ = &fn.getTarget();
1170 mri_ = tm_->getRegisterInfo();
1171 tii_ = tm_->getInstrInfo();
1172 li_ = &getAnalysis<LiveIntervals>();
1173 lv_ = &getAnalysis<LiveVariables>();
1175 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
1176 << "********** Function: "
1177 << ((Value*)mf_->getFunction())->getName() << '\n';
1179 allocatableRegs_ = mri_->getAllocatableSet(fn);
1180 for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(),
1181 E = mri_->regclass_end(); I != E; ++I)
1182 allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I)));
1184 SSARegMap *RegMap = mf_->getSSARegMap();
1185 r2rMap_.grow(RegMap->getLastVirtReg());
1187 // Join (coalesce) intervals if requested.
1188 if (EnableJoining) {
1190 DOUT << "********** INTERVALS POST JOINING **********\n";
1191 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1192 I->second.print(DOUT, mri_);
1196 // Track coalesced sub-registers.
1197 while (!SubRegIdxes.empty()) {
1198 std::pair<unsigned, unsigned> RI = SubRegIdxes.back();
1199 SubRegIdxes.pop_back();
1200 mf_->getSSARegMap()->setIsSubRegister(RI.first, rep(RI.first), RI.second);
1204 // perform a final pass over the instructions and compute spill
1205 // weights, coalesce virtual registers and remove identity moves.
1206 const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
1208 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1209 mbbi != mbbe; ++mbbi) {
1210 MachineBasicBlock* mbb = mbbi;
1211 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
1213 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1215 // if the move will be an identity move delete it
1216 unsigned srcReg, dstReg, RegRep;
1217 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
1218 (RegRep = rep(srcReg)) == rep(dstReg)) {
1219 // remove from def list
1220 LiveInterval &RegInt = li_->getOrCreateInterval(RegRep);
1221 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
1222 // If def of this move instruction is dead, remove its live range from
1223 // the dstination register's live interval.
1225 unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii));
1226 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
1227 RegInt.removeRange(MLR->start, MoveIdx+1);
1229 li_->removeInterval(RegRep);
1231 li_->RemoveMachineInstrFromMaps(mii);
1232 mii = mbbi->erase(mii);
1235 SmallSet<unsigned, 4> UniqueUses;
1236 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
1237 const MachineOperand &mop = mii->getOperand(i);
1238 if (mop.isRegister() && mop.getReg() &&
1239 MRegisterInfo::isVirtualRegister(mop.getReg())) {
1240 // replace register with representative register
1241 unsigned OrigReg = mop.getReg();
1242 unsigned reg = rep(OrigReg);
1243 // Don't rewrite if it is a sub-register of a virtual register.
1244 if (!RegMap->isSubRegister(OrigReg))
1245 mii->getOperand(i).setReg(reg);
1246 else if (MRegisterInfo::isPhysicalRegister(reg))
1247 mii->getOperand(i).setReg(mri_->getSubReg(reg,
1248 RegMap->getSubRegisterIndex(OrigReg)));
1250 // Multiple uses of reg by the same instruction. It should not
1251 // contribute to spill weight again.
1252 if (UniqueUses.count(reg) != 0)
1254 LiveInterval &RegInt = li_->getInterval(reg);
1255 float w = (mop.isUse()+mop.isDef()) * powf(10.0F, (float)loopDepth);
1257 UniqueUses.insert(reg);
1265 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1266 LiveInterval &LI = I->second;
1267 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
1268 // If the live interval length is essentially zero, i.e. in every live
1269 // range the use follows def immediately, it doesn't make sense to spill
1270 // it and hope it will be easier to allocate for this li.
1271 if (isZeroLengthInterval(&LI))
1272 LI.weight = HUGE_VALF;
1274 // Slightly prefer live interval that has been assigned a preferred reg.
1278 // Divide the weight of the interval by its size. This encourages
1279 // spilling of intervals that are large and have few uses, and
1280 // discourages spilling of small intervals with many uses.
1281 LI.weight /= LI.getSize();
1289 /// print - Implement the dump method.
1290 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
1294 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1295 return new SimpleRegisterCoalescing();
1298 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1299 DEFINING_FILE_FOR(SimpleRegisterCoalescing)