1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/OwningPtr.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numCrossRCs , "Number of cross class joins performed");
44 STATISTIC(numCommutes , "Number of instruction commuting performed");
45 STATISTIC(numExtends , "Number of copies extended");
46 STATISTIC(NumReMats , "Number of instructions re-materialized");
47 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
48 STATISTIC(numAborts , "Number of times interval joining aborted");
49 STATISTIC(numDeadValNo, "Number of valno def marked dead");
51 char SimpleRegisterCoalescing::ID = 0;
53 EnableJoining("join-liveintervals",
54 cl::desc("Coalesce copies (default=true)"),
58 DisableCrossClassJoin("disable-cross-class-join",
59 cl::desc("Avoid coalescing cross register class copies"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addRequired<LiveIntervals>();
74 AU.addPreserved<LiveIntervals>();
75 AU.addPreserved<SlotIndexes>();
76 AU.addRequired<MachineLoopInfo>();
77 AU.addPreserved<MachineLoopInfo>();
78 AU.addPreservedID(MachineDominatorsID);
80 AU.addPreservedID(StrongPHIEliminationID);
82 AU.addPreservedID(PHIEliminationID);
83 AU.addPreservedID(TwoAddressInstructionPassID);
84 MachineFunctionPass::getAnalysisUsage(AU);
87 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
88 /// being the source and IntB being the dest, thus this defines a value number
89 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
90 /// see if we can merge these two pieces of B into a single value number,
91 /// eliminating a copy. For example:
95 /// B1 = A3 <- this copy
97 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
98 /// value number to be replaced with B0 (which simplifies the B liveinterval).
100 /// This returns true if an interval was modified.
102 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(const CoalescerPair &CP,
103 MachineInstr *CopyMI) {
104 // Bail if there is no dst interval - can happen when merging physical subreg
106 if (!li_->hasInterval(CP.getDstReg()))
110 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
112 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
113 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
115 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
116 // the example above.
117 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
118 if (BLR == IntB.end()) return false;
119 VNInfo *BValNo = BLR->valno;
121 // Get the location that B is defined at. Two options: either this value has
122 // an unknown definition point or it is defined at CopyIdx. If unknown, we
124 if (!BValNo->getCopy()) return false;
125 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
127 // AValNo is the value number in A that defines the copy, A3 in the example.
128 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
129 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
130 // The live range might not exist after fun with physreg coalescing.
131 if (ALR == IntA.end()) return false;
132 VNInfo *AValNo = ALR->valno;
133 // If it's re-defined by an early clobber somewhere in the live range, then
134 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
136 // 172 %ECX<def> = MOV32rr %reg1039<kill>
137 // 180 INLINEASM <es:subl $5,$1
138 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9,
140 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
141 // 188 %EAX<def> = MOV32rr %EAX<kill>
142 // 196 %ECX<def> = MOV32rr %ECX<kill>
143 // 204 %ECX<def> = MOV32rr %ECX<kill>
144 // 212 %EAX<def> = MOV32rr %EAX<kill>
145 // 220 %EAX<def> = MOV32rr %EAX
146 // 228 %reg1039<def> = MOV32rr %ECX<kill>
147 // The early clobber operand ties ECX input to the ECX def.
149 // The live interval of ECX is represented as this:
150 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
151 // The coalescer has no idea there was a def in the middle of [174,230].
152 if (AValNo->hasRedefByEC())
155 // If AValNo is defined as a copy from IntB, we can potentially process this.
156 // Get the instruction that defines this value number.
157 if (!CP.isCoalescable(AValNo->getCopy()))
160 // Get the LiveRange in IntB that this value number starts with.
161 LiveInterval::iterator ValLR =
162 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
163 if (ValLR == IntB.end())
166 // Make sure that the end of the live range is inside the same block as
168 MachineInstr *ValLREndInst =
169 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
170 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
173 // Okay, we now know that ValLR ends in the same block that the CopyMI
174 // live-range starts. If there are no intervening live ranges between them in
175 // IntB, we can merge them.
176 if (ValLR+1 != BLR) return false;
178 // If a live interval is a physical register, conservatively check if any
179 // of its sub-registers is overlapping the live interval of the virtual
180 // register. If so, do not coalesce.
181 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
182 *tri_->getSubRegisters(IntB.reg)) {
183 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
184 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
186 dbgs() << "\t\tInterfere with sub-register ";
187 li_->getInterval(*SR).print(dbgs(), tri_);
194 dbgs() << "Extending: ";
195 IntB.print(dbgs(), tri_);
198 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
199 // We are about to delete CopyMI, so need to remove it as the 'instruction
200 // that defines this value #'. Update the valnum with the new defining
202 BValNo->def = FillerStart;
205 // Okay, we can merge them. We need to insert a new liverange:
206 // [ValLR.end, BLR.begin) of either value number, then we merge the
207 // two value numbers.
208 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
210 // If the IntB live range is assigned to a physical register, and if that
211 // physreg has sub-registers, update their live intervals as well.
212 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
213 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
214 if (!li_->hasInterval(*SR))
216 LiveInterval &SRLI = li_->getInterval(*SR);
217 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
218 SRLI.getNextValue(FillerStart, 0, true,
219 li_->getVNInfoAllocator())));
223 // Okay, merge "B1" into the same value number as "B0".
224 if (BValNo != ValLR->valno) {
225 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
228 dbgs() << " result = ";
229 IntB.print(dbgs(), tri_);
233 // If the source instruction was killing the source register before the
234 // merge, unset the isKill marker given the live range has been extended.
235 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
237 ValLREndInst->getOperand(UIdx).setIsKill(false);
240 // If the copy instruction was killing the destination register before the
241 // merge, find the last use and trim the live range. That will also add the
243 if (ALR->end == CopyIdx)
244 TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR);
250 /// HasOtherReachingDefs - Return true if there are definitions of IntB
251 /// other than BValNo val# that can reach uses of AValno val# of IntA.
252 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
256 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
258 if (AI->valno != AValNo) continue;
259 LiveInterval::Ranges::iterator BI =
260 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
261 if (BI != IntB.ranges.begin())
263 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
264 if (BI->valno == BValNo)
266 // When BValNo is null, we're looking for a dummy clobber-value for a subreg.
267 if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
269 if (BI->start <= AI->start && BI->end > AI->start)
271 if (BI->start > AI->start && BI->start < AI->end)
279 TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
280 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
282 MachineOperand &MO = MI->getOperand(i);
283 if (MO.isReg() && MO.isImplicit())
284 NewMI->addOperand(MO);
288 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
289 /// IntA being the source and IntB being the dest, thus this defines a value
290 /// number in IntB. If the source value number (in IntA) is defined by a
291 /// commutable instruction and its other operand is coalesced to the copy dest
292 /// register, see if we can transform the copy into a noop by commuting the
293 /// definition. For example,
295 /// A3 = op A2 B0<kill>
297 /// B1 = A3 <- this copy
299 /// = op A3 <- more uses
303 /// B2 = op B0 A2<kill>
305 /// B1 = B2 <- now an identify copy
307 /// = op B2 <- more uses
309 /// This returns true if an interval was modified.
311 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(const CoalescerPair &CP,
312 MachineInstr *CopyMI) {
313 // FIXME: For now, only eliminate the copy by commuting its def when the
314 // source register is a virtual register. We want to guard against cases
315 // where the copy is a back edge copy and commuting the def lengthen the
316 // live interval of the source register to the entire loop.
317 if (CP.isPhys() && CP.isFlipped())
320 // Bail if there is no dst interval.
321 if (!li_->hasInterval(CP.getDstReg()))
325 li_->getInstructionIndex(CopyMI).getDefIndex();
328 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
330 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
332 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
333 // the example above.
334 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
335 if (BLR == IntB.end()) return false;
336 VNInfo *BValNo = BLR->valno;
338 // Get the location that B is defined at. Two options: either this value has
339 // an unknown definition point or it is defined at CopyIdx. If unknown, we
341 if (!BValNo->getCopy()) return false;
342 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
344 // AValNo is the value number in A that defines the copy, A3 in the example.
345 LiveInterval::iterator ALR =
346 IntA.FindLiveRangeContaining(CopyIdx.getUseIndex()); //
348 assert(ALR != IntA.end() && "Live range not found!");
349 VNInfo *AValNo = ALR->valno;
350 // If other defs can reach uses of this def, then it's not safe to perform
351 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
353 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
354 AValNo->isUnused() || AValNo->hasPHIKill())
356 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
359 const TargetInstrDesc &TID = DefMI->getDesc();
360 if (!TID.isCommutable())
362 // If DefMI is a two-address instruction then commuting it will change the
363 // destination register.
364 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
365 assert(DefIdx != -1);
367 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
369 unsigned Op1, Op2, NewDstIdx;
370 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
374 else if (Op2 == UseOpIdx)
379 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
380 unsigned NewReg = NewDstMO.getReg();
381 if (NewReg != IntB.reg || !NewDstMO.isKill())
384 // Make sure there are no other definitions of IntB that would reach the
385 // uses which the new definition can reach.
386 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
389 bool BHasSubRegs = false;
390 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
391 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
393 // Abort if the subregisters of IntB.reg have values that are not simply the
394 // clobbers from the superreg.
396 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
397 if (li_->hasInterval(*SR) &&
398 HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0))
401 // If some of the uses of IntA.reg is already coalesced away, return false.
402 // It's not possible to determine whether it's safe to perform the coalescing.
403 for (MachineRegisterInfo::use_nodbg_iterator UI =
404 mri_->use_nodbg_begin(IntA.reg),
405 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
406 MachineInstr *UseMI = &*UI;
407 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
408 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
409 if (ULR == IntA.end())
411 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
415 // At this point we have decided that it is legal to do this
416 // transformation. Start by commuting the instruction.
417 MachineBasicBlock *MBB = DefMI->getParent();
418 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
421 if (NewMI != DefMI) {
422 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
423 MBB->insert(DefMI, NewMI);
426 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
427 NewMI->getOperand(OpIdx).setIsKill();
429 bool BHasPHIKill = BValNo->hasPHIKill();
430 SmallVector<VNInfo*, 4> BDeadValNos;
431 std::map<SlotIndex, SlotIndex> BExtend;
433 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
441 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
443 BExtend[ALR->end] = BLR->end;
445 // Update uses of IntA of the specific Val# with IntB.
446 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
447 UE = mri_->use_end(); UI != UE;) {
448 MachineOperand &UseMO = UI.getOperand();
449 MachineInstr *UseMI = &*UI;
451 if (JoinedCopies.count(UseMI))
453 if (UseMI->isDebugValue()) {
454 // FIXME These don't have an instruction index. Not clear we have enough
455 // info to decide whether to do this replacement or not. For now do it.
456 UseMO.setReg(NewReg);
459 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
460 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
461 if (ULR == IntA.end() || ULR->valno != AValNo)
463 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
464 UseMO.substPhysReg(NewReg, *tri_);
466 UseMO.setReg(NewReg);
469 if (UseMO.isKill()) {
471 UseMO.setIsKill(false);
473 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
474 if (UseMI->isCopy()) {
475 if (UseMI->getOperand(0).getReg() != IntB.reg ||
476 UseMI->getOperand(0).getSubReg())
478 } else if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
479 if (DstReg != IntB.reg || DstSubIdx)
483 // This copy will become a noop. If it's defining a new val#,
484 // remove that val# as well. However this live range is being
485 // extended to the end of the existing live range defined by the copy.
486 SlotIndex DefIdx = UseIdx.getDefIndex();
487 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
490 BHasPHIKill |= DLR->valno->hasPHIKill();
491 assert(DLR->valno->def == DefIdx);
492 BDeadValNos.push_back(DLR->valno);
493 BExtend[DLR->start] = DLR->end;
494 JoinedCopies.insert(UseMI);
497 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
498 // simply extend BLR if CopyMI doesn't end the range.
500 dbgs() << "Extending: ";
501 IntB.print(dbgs(), tri_);
504 // Remove val#'s defined by copies that will be coalesced away.
505 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
506 VNInfo *DeadVNI = BDeadValNos[i];
508 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
509 if (!li_->hasInterval(*SR))
511 LiveInterval &SRLI = li_->getInterval(*SR);
512 if (const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def))
513 SRLI.removeValNo(SRLR->valno);
516 IntB.removeValNo(BDeadValNos[i]);
519 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
521 VNInfo *ValNo = BValNo;
522 ValNo->def = AValNo->def;
524 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
526 if (AI->valno != AValNo) continue;
527 SlotIndex End = AI->end;
528 std::map<SlotIndex, SlotIndex>::iterator
529 EI = BExtend.find(End);
530 if (EI != BExtend.end())
532 IntB.addRange(LiveRange(AI->start, End, ValNo));
534 ValNo->setHasPHIKill(BHasPHIKill);
537 dbgs() << " result = ";
538 IntB.print(dbgs(), tri_);
539 dbgs() << "\nShortening: ";
540 IntA.print(dbgs(), tri_);
543 IntA.removeValNo(AValNo);
546 dbgs() << " result = ";
547 IntA.print(dbgs(), tri_);
555 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
556 /// fallthoughs to SuccMBB.
557 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
558 MachineBasicBlock *SuccMBB,
559 const TargetInstrInfo *tii_) {
562 MachineBasicBlock *TBB = 0, *FBB = 0;
563 SmallVector<MachineOperand, 4> Cond;
564 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
565 MBB->isSuccessor(SuccMBB);
568 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
569 /// from a physical register live interval as well as from the live intervals
570 /// of its sub-registers.
571 static void removeRange(LiveInterval &li,
572 SlotIndex Start, SlotIndex End,
573 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
574 li.removeRange(Start, End, true);
575 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
576 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
577 if (!li_->hasInterval(*SR))
579 LiveInterval &sli = li_->getInterval(*SR);
580 SlotIndex RemoveStart = Start;
581 SlotIndex RemoveEnd = Start;
583 while (RemoveEnd != End) {
584 LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
587 RemoveEnd = (LR->end < End) ? LR->end : End;
588 sli.removeRange(RemoveStart, RemoveEnd, true);
589 RemoveStart = RemoveEnd;
595 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
596 /// as the copy instruction, trim the live interval to the last use and return
599 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
600 MachineBasicBlock *CopyMBB,
602 const LiveRange *LR) {
603 SlotIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
604 SlotIndex LastUseIdx;
605 MachineOperand *LastUse =
606 lastRegisterUse(LR->start, CopyIdx.getPrevSlot(), li.reg, LastUseIdx);
608 MachineInstr *LastUseMI = LastUse->getParent();
609 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
616 // r1025<dead> = r1024<kill>
617 if (MBBStart < LR->end)
618 removeRange(li, MBBStart, LR->end, li_, tri_);
622 // There are uses before the copy, just shorten the live range to the end
624 LastUse->setIsKill();
625 removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
626 if (LastUseMI->isCopy()) {
627 MachineOperand &DefMO = LastUseMI->getOperand(0);
628 if (DefMO.getReg() == li.reg && !DefMO.getSubReg())
631 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
632 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
633 DstReg == li.reg && DstSubIdx == 0) {
634 // Last use is itself an identity code.
635 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg,
637 LastUseMI->getOperand(DeadIdx).setIsDead();
643 if (LR->start <= MBBStart && LR->end > MBBStart) {
644 if (LR->start == li_->getZeroIndex()) {
645 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
646 // Live-in to the function but dead. Remove it from entry live-in set.
647 mf_->begin()->removeLiveIn(li.reg);
649 // FIXME: Shorten intervals in BBs that reaches this BB.
655 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
656 /// computation, replace the copy by rematerialize the definition.
657 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
660 MachineInstr *CopyMI) {
661 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
662 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
663 assert(SrcLR != SrcInt.end() && "Live range not found!");
664 VNInfo *ValNo = SrcLR->valno;
665 // If other defs can reach uses of this def, then it's not safe to perform
666 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
668 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
669 ValNo->isUnused() || ValNo->hasPHIKill())
671 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
672 assert(DefMI && "Defining instruction disappeared");
673 const TargetInstrDesc &TID = DefMI->getDesc();
674 if (!TID.isAsCheapAsAMove())
676 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
678 bool SawStore = false;
679 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
681 if (TID.getNumDefs() != 1)
683 if (!DefMI->isImplicitDef()) {
684 // Make sure the copy destination register class fits the instruction
685 // definition register class. The mismatch can happen as a result of earlier
686 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
687 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
688 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
689 if (mri_->getRegClass(DstReg) != RC)
691 } else if (!RC->contains(DstReg))
695 // If destination register has a sub-register index on it, make sure it mtches
696 // the instruction register class.
698 const TargetInstrDesc &TID = DefMI->getDesc();
699 if (TID.getNumDefs() != 1)
701 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
702 const TargetRegisterClass *DstSubRC =
703 DstRC->getSubRegisterRegClass(DstSubIdx);
704 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
707 else if (DefRC != DstSubRC)
711 RemoveCopyFlag(DstReg, CopyMI);
713 // If copy kills the source register, find the last use and propagate
715 bool checkForDeadDef = false;
716 MachineBasicBlock *MBB = CopyMI->getParent();
717 if (SrcLR->end == CopyIdx.getDefIndex())
718 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
719 checkForDeadDef = true;
722 MachineBasicBlock::iterator MII =
723 llvm::next(MachineBasicBlock::iterator(CopyMI));
724 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, *tri_);
725 MachineInstr *NewMI = prior(MII);
727 if (checkForDeadDef) {
728 // PR4090 fix: Trim interval failed because there was no use of the
729 // source interval in this MBB. If the def is in this MBB too then we
730 // should mark it dead:
731 if (DefMI->getParent() == MBB) {
732 DefMI->addRegisterDead(SrcInt.reg, tri_);
733 SrcLR->end = SrcLR->start.getNextSlot();
737 // CopyMI may have implicit operands, transfer them over to the newly
738 // rematerialized instruction. And update implicit def interval valnos.
739 for (unsigned i = CopyMI->getDesc().getNumOperands(),
740 e = CopyMI->getNumOperands(); i != e; ++i) {
741 MachineOperand &MO = CopyMI->getOperand(i);
742 if (MO.isReg() && MO.isImplicit())
743 NewMI->addOperand(MO);
745 RemoveCopyFlag(MO.getReg(), CopyMI);
748 TransferImplicitOps(CopyMI, NewMI);
749 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
750 CopyMI->eraseFromParent();
751 ReMatCopies.insert(CopyMI);
752 ReMatDefs.insert(DefMI);
753 DEBUG(dbgs() << "Remat: " << *NewMI);
758 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
759 /// update the subregister number if it is not zero. If DstReg is a
760 /// physical register and the existing subregister number of the def / use
761 /// being updated is not zero, make sure to set it to the correct physical
764 SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
765 bool DstIsPhys = CP.isPhys();
766 unsigned SrcReg = CP.getSrcReg();
767 unsigned DstReg = CP.getDstReg();
768 unsigned SubIdx = CP.getSubIdx();
770 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg);
771 MachineInstr *UseMI = I.skipInstruction();) {
772 // A PhysReg copy that won't be coalesced can perhaps be rematerialized
775 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
776 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
777 CopySrcSubIdx, CopyDstSubIdx) &&
778 CopySrcSubIdx == 0 && CopyDstSubIdx == 0 &&
779 CopySrcReg != CopyDstReg && CopySrcReg == SrcReg &&
780 CopyDstReg != DstReg && !JoinedCopies.count(UseMI) &&
781 ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg, 0,
785 if (UseMI->isCopy() &&
786 !UseMI->getOperand(1).getSubReg() &&
787 !UseMI->getOperand(0).getSubReg() &&
788 UseMI->getOperand(1).getReg() == SrcReg &&
789 UseMI->getOperand(0).getReg() != SrcReg &&
790 UseMI->getOperand(0).getReg() != DstReg &&
791 !JoinedCopies.count(UseMI) &&
792 ReMaterializeTrivialDef(li_->getInterval(SrcReg),
793 UseMI->getOperand(0).getReg(), 0, UseMI))
797 SmallVector<unsigned,8> Ops;
799 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
800 bool Kills = false, Deads = false;
802 // Replace SrcReg with DstReg in all UseMI operands.
803 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
804 MachineOperand &MO = UseMI->getOperand(Ops[i]);
805 Kills |= MO.isKill();
806 Deads |= MO.isDead();
809 MO.substPhysReg(DstReg, *tri_);
811 MO.substVirtReg(DstReg, SubIdx, *tri_);
814 // This instruction is a copy that will be removed.
815 if (JoinedCopies.count(UseMI))
819 // If UseMI was a simple SrcReg def, make sure we didn't turn it into a
820 // read-modify-write of DstReg.
822 UseMI->addRegisterDead(DstReg, tri_);
823 else if (!Reads && Writes)
824 UseMI->addRegisterDefined(DstReg, tri_);
826 // Kill flags apply to the whole physical register.
827 if (DstIsPhys && Kills)
828 UseMI->addRegisterKilled(DstReg, tri_);
832 dbgs() << "\t\tupdated: ";
833 if (!UseMI->isDebugValue())
834 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
839 // After updating the operand, check if the machine instruction has
840 // become a copy. If so, update its val# information.
841 const TargetInstrDesc &TID = UseMI->getDesc();
842 if (DstIsPhys || TID.getNumDefs() != 1 || TID.getNumOperands() <= 2)
845 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
846 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
847 CopySrcSubIdx, CopyDstSubIdx) &&
848 CopySrcReg != CopyDstReg &&
849 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
850 allocatableRegs_[CopyDstReg])) {
851 LiveInterval &LI = li_->getInterval(CopyDstReg);
853 li_->getInstructionIndex(UseMI).getDefIndex();
854 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
855 if (DLR->valno->def == DefIdx)
856 DLR->valno->setCopy(UseMI);
862 /// removeIntervalIfEmpty - Check if the live interval of a physical register
863 /// is empty, if so remove it and also remove the empty intervals of its
864 /// sub-registers. Return true if live interval is removed.
865 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
866 const TargetRegisterInfo *tri_) {
868 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
869 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
870 if (!li_->hasInterval(*SR))
872 LiveInterval &sli = li_->getInterval(*SR);
874 li_->removeInterval(*SR);
876 li_->removeInterval(li.reg);
882 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
883 /// Return true if live interval is removed.
884 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
885 MachineInstr *CopyMI) {
886 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
887 LiveInterval::iterator MLR =
888 li.FindLiveRangeContaining(CopyIdx.getDefIndex());
890 return false; // Already removed by ShortenDeadCopySrcLiveRange.
891 SlotIndex RemoveStart = MLR->start;
892 SlotIndex RemoveEnd = MLR->end;
893 SlotIndex DefIdx = CopyIdx.getDefIndex();
894 // Remove the liverange that's defined by this.
895 if (RemoveStart == DefIdx && RemoveEnd == DefIdx.getStoreIndex()) {
896 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
897 return removeIntervalIfEmpty(li, li_, tri_);
902 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
903 /// the val# it defines. If the live interval becomes empty, remove it as well.
904 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
905 MachineInstr *DefMI) {
906 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
907 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
908 if (DefIdx != MLR->valno->def)
910 li.removeValNo(MLR->valno);
911 return removeIntervalIfEmpty(li, li_, tri_);
914 void SimpleRegisterCoalescing::RemoveCopyFlag(unsigned DstReg,
915 const MachineInstr *CopyMI) {
916 SlotIndex DefIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
917 if (li_->hasInterval(DstReg)) {
918 LiveInterval &LI = li_->getInterval(DstReg);
919 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
920 if (LR->valno->getCopy() == CopyMI)
921 LR->valno->setCopy(0);
923 if (!TargetRegisterInfo::isPhysicalRegister(DstReg))
925 for (const unsigned* AS = tri_->getAliasSet(DstReg); *AS; ++AS) {
926 if (!li_->hasInterval(*AS))
928 LiveInterval &LI = li_->getInterval(*AS);
929 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
930 if (LR->valno->getCopy() == CopyMI)
931 LR->valno->setCopy(0);
935 /// PropagateDeadness - Propagate the dead marker to the instruction which
936 /// defines the val#.
937 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
938 SlotIndex &LRStart, LiveIntervals *li_,
939 const TargetRegisterInfo* tri_) {
940 MachineInstr *DefMI =
941 li_->getInstructionFromIndex(LRStart.getDefIndex());
942 if (DefMI && DefMI != CopyMI) {
943 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg);
945 DefMI->getOperand(DeadIdx).setIsDead();
947 DefMI->addOperand(MachineOperand::CreateReg(li.reg,
948 /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true));
949 LRStart = LRStart.getNextSlot();
953 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
954 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
955 /// ends the live range there. If there isn't another use, then this live range
956 /// is dead. Return true if live interval is removed.
958 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
959 MachineInstr *CopyMI) {
960 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
961 if (CopyIdx == SlotIndex()) {
962 // FIXME: special case: function live in. It can be a general case if the
963 // first instruction index starts at > 0 value.
964 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
965 // Live-in to the function but dead. Remove it from entry live-in set.
966 if (mf_->begin()->isLiveIn(li.reg))
967 mf_->begin()->removeLiveIn(li.reg);
968 if (const LiveRange *LR = li.getLiveRangeContaining(CopyIdx))
969 removeRange(li, LR->start, LR->end, li_, tri_);
970 return removeIntervalIfEmpty(li, li_, tri_);
973 LiveInterval::iterator LR =
974 li.FindLiveRangeContaining(CopyIdx.getPrevIndex().getStoreIndex());
976 // Livein but defined by a phi.
979 SlotIndex RemoveStart = LR->start;
980 SlotIndex RemoveEnd = CopyIdx.getStoreIndex();
981 if (LR->end > RemoveEnd)
982 // More uses past this copy? Nothing to do.
985 // If there is a last use in the same bb, we can't remove the live range.
986 // Shorten the live interval and return.
987 MachineBasicBlock *CopyMBB = CopyMI->getParent();
988 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
991 // There are other kills of the val#. Nothing to do.
992 if (!li.isOnlyLROfValNo(LR))
995 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
996 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
997 // If the live range starts in another mbb and the copy mbb is not a fall
998 // through mbb, then we can only cut the range from the beginning of the
1000 RemoveStart = li_->getMBBStartIdx(CopyMBB).getNextIndex().getBaseIndex();
1002 if (LR->valno->def == RemoveStart) {
1003 // If the def MI defines the val# and this copy is the only kill of the
1004 // val#, then propagate the dead marker.
1005 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
1009 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
1010 return removeIntervalIfEmpty(li, li_, tri_);
1014 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1015 /// two virtual registers from different register classes.
1017 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
1019 const TargetRegisterClass *SrcRC,
1020 const TargetRegisterClass *DstRC,
1021 const TargetRegisterClass *NewRC) {
1022 unsigned NewRCCount = allocatableRCRegs_[NewRC].count();
1023 // This heuristics is good enough in practice, but it's obviously not *right*.
1024 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
1025 // out all but the most restrictive register classes.
1026 if (NewRCCount > 4 ||
1027 // Early exit if the function is fairly small, coalesce aggressively if
1028 // that's the case. For really special register classes with 3 or
1029 // fewer registers, be a bit more careful.
1030 (li_->getFuncInstructionCount() / NewRCCount) < 8)
1032 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1033 LiveInterval &DstInt = li_->getInterval(DstReg);
1034 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
1035 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
1036 if (SrcSize <= NewRCCount && DstSize <= NewRCCount)
1038 // Estimate *register use density*. If it doubles or more, abort.
1039 unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
1040 mri_->use_nodbg_end());
1041 unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
1042 mri_->use_nodbg_end());
1043 unsigned NewUses = SrcUses + DstUses;
1044 unsigned NewSize = SrcSize + DstSize;
1045 if (SrcRC != NewRC && SrcSize > NewRCCount) {
1046 unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count();
1047 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1050 if (DstRC != NewRC && DstSize > NewRCCount) {
1051 unsigned DstRCCount = allocatableRCRegs_[DstRC].count();
1052 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1059 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1060 /// which are the src/dst of the copy instruction CopyMI. This returns true
1061 /// if the copy was successfully coalesced away. If it is not currently
1062 /// possible to coalesce this interval, but it may be possible if other
1063 /// things get coalesced, then it returns true by reference in 'Again'.
1064 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1065 MachineInstr *CopyMI = TheCopy.MI;
1068 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1069 return false; // Already done.
1071 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1073 CoalescerPair CP(*tii_, *tri_);
1074 if (!CP.setRegisters(CopyMI)) {
1075 DEBUG(dbgs() << "\tNot coalescable.\n");
1079 // If they are already joined we continue.
1080 if (CP.getSrcReg() == CP.getDstReg()) {
1081 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1082 return false; // Not coalescable.
1085 DEBUG(dbgs() << "\tConsidering merging %reg" << CP.getSrcReg());
1087 // Enforce policies.
1089 DEBUG(dbgs() <<" with physreg %" << tri_->getName(CP.getDstReg()) << "\n");
1090 // Only coalesce to allocatable physreg.
1091 if (!allocatableRegs_[CP.getDstReg()]) {
1092 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
1093 return false; // Not coalescable.
1097 dbgs() << " with reg%" << CP.getDstReg();
1099 dbgs() << ":" << tri_->getSubRegIndexName(CP.getSubIdx());
1100 dbgs() << " to " << CP.getNewRC()->getName() << "\n";
1103 // Avoid constraining virtual register regclass too much.
1104 if (CP.isCrossClass()) {
1105 if (DisableCrossClassJoin) {
1106 DEBUG(dbgs() << "\tCross-class joins disabled.\n");
1109 if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
1110 mri_->getRegClass(CP.getSrcReg()),
1111 mri_->getRegClass(CP.getDstReg()),
1113 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1114 << CP.getNewRC()->getName() << ".\n");
1115 Again = true; // May be possible to coalesce later.
1120 // When possible, let DstReg be the larger interval.
1121 if (!CP.getSubIdx() && li_->getInterval(CP.getSrcReg()).ranges.size() >
1122 li_->getInterval(CP.getDstReg()).ranges.size())
1126 // We need to be careful about coalescing a source physical register with a
1127 // virtual register. Once the coalescing is done, it cannot be broken and
1128 // these are not spillable! If the destination interval uses are far away,
1129 // think twice about coalescing them!
1130 // FIXME: Why are we skipping this test for partial copies?
1131 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
1132 if (!CP.isPartial() && CP.isPhys()) {
1133 LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
1135 // Don't join with physregs that have a ridiculous number of live
1136 // ranges. The data structure performance is really bad when that
1138 if (li_->hasInterval(CP.getDstReg()) &&
1139 li_->getInterval(CP.getDstReg()).ranges.size() > 1000) {
1140 mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg());
1143 << "\tPhysical register live interval too complicated, abort!\n");
1147 const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
1148 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1149 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1150 if (Length > Threshold &&
1151 std::distance(mri_->use_nodbg_begin(CP.getSrcReg()),
1152 mri_->use_nodbg_end()) * Threshold < Length) {
1153 // Before giving up coalescing, if definition of source is defined by
1154 // trivial computation, try rematerializing it.
1155 if (!CP.isFlipped() &&
1156 ReMaterializeTrivialDef(JoinVInt, CP.getDstReg(), 0, CopyMI))
1159 mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg());
1161 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1162 Again = true; // May be possible to coalesce later.
1167 // Okay, attempt to join these two intervals. On failure, this returns false.
1168 // Otherwise, if one of the intervals being joined is a physreg, this method
1169 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1170 // been modified, so we can use this information below to update aliases.
1171 if (!JoinIntervals(CP)) {
1172 // Coalescing failed.
1174 // If definition of source is defined by trivial computation, try
1175 // rematerializing it.
1176 if (!CP.isFlipped() &&
1177 ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()),
1178 CP.getDstReg(), 0, CopyMI))
1181 // If we can eliminate the copy without merging the live ranges, do so now.
1182 if (!CP.isPartial()) {
1183 if (AdjustCopiesBackFrom(CP, CopyMI) ||
1184 RemoveCopyByCommutingDef(CP, CopyMI)) {
1185 JoinedCopies.insert(CopyMI);
1186 DEBUG(dbgs() << "\tTrivial!\n");
1191 // Otherwise, we are unable to join the intervals.
1192 DEBUG(dbgs() << "\tInterference!\n");
1193 Again = true; // May be possible to coalesce later.
1197 // Coalescing to a virtual register that is of a sub-register class of the
1198 // other. Make sure the resulting register is set to the right register class.
1199 if (CP.isCrossClass()) {
1201 mri_->setRegClass(CP.getDstReg(), CP.getNewRC());
1204 // Remember to delete the copy instruction.
1205 JoinedCopies.insert(CopyMI);
1207 UpdateRegDefsUses(CP);
1209 // If we have extended the live range of a physical register, make sure we
1210 // update live-in lists as well.
1212 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1213 // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
1214 // ranges for this, and they are preserved.
1215 LiveInterval &SrcInt = li_->getInterval(CP.getSrcReg());
1216 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
1218 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
1219 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1220 MachineBasicBlock &block = *BlockSeq[idx];
1221 if (!block.isLiveIn(CP.getDstReg()))
1222 block.addLiveIn(CP.getDstReg());
1228 // SrcReg is guarateed to be the register whose live interval that is
1230 li_->removeInterval(CP.getSrcReg());
1232 // Update regalloc hint.
1233 tri_->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *mf_);
1236 LiveInterval &DstInt = li_->getInterval(CP.getDstReg());
1237 dbgs() << "\tJoined. Result = ";
1238 DstInt.print(dbgs(), tri_);
1246 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1247 /// compute what the resultant value numbers for each value in the input two
1248 /// ranges will be. This is complicated by copies between the two which can
1249 /// and will commonly cause multiple value numbers to be merged into one.
1251 /// VN is the value number that we're trying to resolve. InstDefiningValue
1252 /// keeps track of the new InstDefiningValue assignment for the result
1253 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1254 /// whether a value in this or other is a copy from the opposite set.
1255 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1256 /// already been assigned.
1258 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1259 /// contains the value number the copy is from.
1261 static unsigned ComputeUltimateVN(VNInfo *VNI,
1262 SmallVector<VNInfo*, 16> &NewVNInfo,
1263 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1264 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1265 SmallVector<int, 16> &ThisValNoAssignments,
1266 SmallVector<int, 16> &OtherValNoAssignments) {
1267 unsigned VN = VNI->id;
1269 // If the VN has already been computed, just return it.
1270 if (ThisValNoAssignments[VN] >= 0)
1271 return ThisValNoAssignments[VN];
1272 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1274 // If this val is not a copy from the other val, then it must be a new value
1275 // number in the destination.
1276 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1277 if (I == ThisFromOther.end()) {
1278 NewVNInfo.push_back(VNI);
1279 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1281 VNInfo *OtherValNo = I->second;
1283 // Otherwise, this *is* a copy from the RHS. If the other side has already
1284 // been computed, return it.
1285 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1286 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1288 // Mark this value number as currently being computed, then ask what the
1289 // ultimate value # of the other value is.
1290 ThisValNoAssignments[VN] = -2;
1291 unsigned UltimateVN =
1292 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1293 OtherValNoAssignments, ThisValNoAssignments);
1294 return ThisValNoAssignments[VN] = UltimateVN;
1297 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1299 bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
1300 LiveInterval &RHS = li_->getInterval(CP.getSrcReg());
1301 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), tri_); dbgs() << "\n"; });
1303 // If a live interval is a physical register, check for interference with any
1304 // aliases. The interference check implemented here is a bit more conservative
1305 // than the full interfeence check below. We allow overlapping live ranges
1306 // only when one is a copy of the other.
1308 for (const unsigned *AS = tri_->getAliasSet(CP.getDstReg()); *AS; ++AS){
1309 if (!li_->hasInterval(*AS))
1311 const LiveInterval &LHS = li_->getInterval(*AS);
1312 LiveInterval::const_iterator LI = LHS.begin();
1313 for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
1315 LI = std::lower_bound(LI, LHS.end(), RI->start);
1316 // Does LHS have an overlapping live range starting before RI?
1317 if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
1318 (RI->start != RI->valno->def ||
1319 !CP.isCoalescable(li_->getInstructionFromIndex(RI->start)))) {
1321 dbgs() << "\t\tInterference from alias: ";
1322 LHS.print(dbgs(), tri_);
1323 dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
1328 // Check that LHS ranges beginning in this range are copies.
1329 for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
1330 if (LI->start != LI->valno->def ||
1331 !CP.isCoalescable(li_->getInstructionFromIndex(LI->start))) {
1333 dbgs() << "\t\tInterference from alias: ";
1334 LHS.print(dbgs(), tri_);
1335 dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
1344 // Compute the final value assignment, assuming that the live ranges can be
1346 SmallVector<int, 16> LHSValNoAssignments;
1347 SmallVector<int, 16> RHSValNoAssignments;
1348 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1349 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1350 SmallVector<VNInfo*, 16> NewVNInfo;
1352 LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg());
1353 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
1355 // Loop over the value numbers of the LHS, seeing if any are defined from
1357 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1360 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
1363 // Never join with a register that has EarlyClobber redefs.
1364 if (VNI->hasRedefByEC())
1367 // DstReg is known to be a register in the LHS interval. If the src is
1368 // from the RHS interval, we can use its value #.
1369 if (!CP.isCoalescable(VNI->getCopy()))
1372 // Figure out the value # from the RHS.
1373 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1374 // The copy could be to an aliased physreg.
1376 LHSValsDefinedFromRHS[VNI] = lr->valno;
1379 // Loop over the value numbers of the RHS, seeing if any are defined from
1381 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1384 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
1387 // Never join with a register that has EarlyClobber redefs.
1388 if (VNI->hasRedefByEC())
1391 // DstReg is known to be a register in the RHS interval. If the src is
1392 // from the LHS interval, we can use its value #.
1393 if (!CP.isCoalescable(VNI->getCopy()))
1396 // Figure out the value # from the LHS.
1397 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1398 // The copy could be to an aliased physreg.
1400 RHSValsDefinedFromLHS[VNI] = lr->valno;
1403 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1404 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1405 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1407 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1410 unsigned VN = VNI->id;
1411 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1413 ComputeUltimateVN(VNI, NewVNInfo,
1414 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1415 LHSValNoAssignments, RHSValNoAssignments);
1417 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1420 unsigned VN = VNI->id;
1421 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1423 // If this value number isn't a copy from the LHS, it's a new number.
1424 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1425 NewVNInfo.push_back(VNI);
1426 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1430 ComputeUltimateVN(VNI, NewVNInfo,
1431 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1432 RHSValNoAssignments, LHSValNoAssignments);
1435 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1436 // interval lists to see if these intervals are coalescable.
1437 LiveInterval::const_iterator I = LHS.begin();
1438 LiveInterval::const_iterator IE = LHS.end();
1439 LiveInterval::const_iterator J = RHS.begin();
1440 LiveInterval::const_iterator JE = RHS.end();
1442 // Skip ahead until the first place of potential sharing.
1443 if (I != IE && J != JE) {
1444 if (I->start < J->start) {
1445 I = std::upper_bound(I, IE, J->start);
1446 if (I != LHS.begin()) --I;
1447 } else if (J->start < I->start) {
1448 J = std::upper_bound(J, JE, I->start);
1449 if (J != RHS.begin()) --J;
1453 while (I != IE && J != JE) {
1454 // Determine if these two live ranges overlap.
1456 if (I->start < J->start) {
1457 Overlaps = I->end > J->start;
1459 Overlaps = J->end > I->start;
1462 // If so, check value # info to determine if they are really different.
1464 // If the live range overlap will map to the same value number in the
1465 // result liverange, we can still coalesce them. If not, we can't.
1466 if (LHSValNoAssignments[I->valno->id] !=
1467 RHSValNoAssignments[J->valno->id])
1469 // If it's re-defined by an early clobber somewhere in the live range,
1470 // then conservatively abort coalescing.
1471 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
1475 if (I->end < J->end)
1481 // Update kill info. Some live ranges are extended due to copy coalescing.
1482 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1483 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1484 VNInfo *VNI = I->first;
1485 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1486 if (VNI->hasPHIKill())
1487 NewVNInfo[LHSValID]->setHasPHIKill(true);
1490 // Update kill info. Some live ranges are extended due to copy coalescing.
1491 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1492 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1493 VNInfo *VNI = I->first;
1494 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1495 if (VNI->hasPHIKill())
1496 NewVNInfo[RHSValID]->setHasPHIKill(true);
1499 if (LHSValNoAssignments.empty())
1500 LHSValNoAssignments.push_back(-1);
1501 if (RHSValNoAssignments.empty())
1502 RHSValNoAssignments.push_back(-1);
1504 // If we get here, we know that we can coalesce the live ranges. Ask the
1505 // intervals to coalesce themselves now.
1506 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1512 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1513 // depth of the basic block (the unsigned), and then on the MBB number.
1514 struct DepthMBBCompare {
1515 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1516 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1517 // Deeper loops first
1518 if (LHS.first != RHS.first)
1519 return LHS.first > RHS.first;
1521 // Prefer blocks that are more connected in the CFG. This takes care of
1522 // the most difficult copies first while intervals are short.
1523 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1524 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1528 // As a last resort, sort by block number.
1529 return LHS.second->getNumber() < RHS.second->getNumber();
1534 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1535 std::vector<CopyRec> &TryAgain) {
1536 DEBUG(dbgs() << MBB->getName() << ":\n");
1538 std::vector<CopyRec> VirtCopies;
1539 std::vector<CopyRec> PhysCopies;
1540 std::vector<CopyRec> ImpDefCopies;
1541 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1543 MachineInstr *Inst = MII++;
1545 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1546 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1547 bool isInsUndef = false;
1548 if (Inst->isCopy()) {
1549 DstReg = Inst->getOperand(0).getReg();
1550 SrcReg = Inst->getOperand(1).getReg();
1551 } else if (Inst->isSubregToReg()) {
1552 DstReg = Inst->getOperand(0).getReg();
1553 SrcReg = Inst->getOperand(2).getReg();
1554 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1557 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1558 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1560 (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
1561 ImpDefCopies.push_back(CopyRec(Inst, 0));
1562 else if (SrcIsPhys || DstIsPhys)
1563 PhysCopies.push_back(CopyRec(Inst, 0));
1565 VirtCopies.push_back(CopyRec(Inst, 0));
1568 // Try coalescing implicit copies and insert_subreg <undef> first,
1569 // followed by copies to / from physical registers, then finally copies
1570 // from virtual registers to virtual registers.
1571 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1572 CopyRec &TheCopy = ImpDefCopies[i];
1574 if (!JoinCopy(TheCopy, Again))
1576 TryAgain.push_back(TheCopy);
1578 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1579 CopyRec &TheCopy = PhysCopies[i];
1581 if (!JoinCopy(TheCopy, Again))
1583 TryAgain.push_back(TheCopy);
1585 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1586 CopyRec &TheCopy = VirtCopies[i];
1588 if (!JoinCopy(TheCopy, Again))
1590 TryAgain.push_back(TheCopy);
1594 void SimpleRegisterCoalescing::joinIntervals() {
1595 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1597 std::vector<CopyRec> TryAgainList;
1598 if (loopInfo->empty()) {
1599 // If there are no loops in the function, join intervals in function order.
1600 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1602 CopyCoalesceInMBB(I, TryAgainList);
1604 // Otherwise, join intervals in inner loops before other intervals.
1605 // Unfortunately we can't just iterate over loop hierarchy here because
1606 // there may be more MBB's than BB's. Collect MBB's for sorting.
1608 // Join intervals in the function prolog first. We want to join physical
1609 // registers with virtual registers before the intervals got too long.
1610 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1611 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1612 MachineBasicBlock *MBB = I;
1613 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1616 // Sort by loop depth.
1617 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1619 // Finally, join intervals in loop nest order.
1620 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1621 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1624 // Joining intervals can allow other intervals to be joined. Iteratively join
1625 // until we make no progress.
1626 bool ProgressMade = true;
1627 while (ProgressMade) {
1628 ProgressMade = false;
1630 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1631 CopyRec &TheCopy = TryAgainList[i];
1636 bool Success = JoinCopy(TheCopy, Again);
1637 if (Success || !Again) {
1638 TheCopy.MI = 0; // Mark this one as done.
1639 ProgressMade = true;
1645 /// Return true if the two specified registers belong to different register
1646 /// classes. The registers may be either phys or virt regs.
1648 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1649 unsigned RegB) const {
1650 // Get the register classes for the first reg.
1651 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
1652 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1653 "Shouldn't consider two physregs!");
1654 return !mri_->getRegClass(RegB)->contains(RegA);
1657 // Compare against the regclass for the second reg.
1658 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
1659 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
1660 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
1661 return RegClassA != RegClassB;
1663 return !RegClassA->contains(RegB);
1666 /// lastRegisterUse - Returns the last (non-debug) use of the specific register
1667 /// between cycles Start and End or NULL if there are no uses.
1669 SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
1672 SlotIndex &UseIdx) const{
1673 UseIdx = SlotIndex();
1674 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1675 MachineOperand *LastUse = NULL;
1676 for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg),
1677 E = mri_->use_nodbg_end(); I != E; ++I) {
1678 MachineOperand &Use = I.getOperand();
1679 MachineInstr *UseMI = Use.getParent();
1680 if (UseMI->isIdentityCopy())
1682 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1683 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1684 SrcReg == DstReg && SrcSubIdx == DstSubIdx)
1685 // Ignore identity copies.
1687 SlotIndex Idx = li_->getInstructionIndex(UseMI);
1688 // FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
1689 // that compares higher than any other interval.
1690 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
1692 UseIdx = Idx.getUseIndex();
1698 SlotIndex s = Start;
1699 SlotIndex e = End.getPrevSlot().getBaseIndex();
1701 // Skip deleted instructions
1702 MachineInstr *MI = li_->getInstructionFromIndex(e);
1703 while (e != SlotIndex() && e.getPrevIndex() >= s && !MI) {
1704 e = e.getPrevIndex();
1705 MI = li_->getInstructionFromIndex(e);
1707 if (e < s || MI == NULL)
1710 // Ignore identity copies.
1711 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1712 if (!MI->isIdentityCopy() &&
1713 !(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1714 SrcReg == DstReg && SrcSubIdx == DstSubIdx))
1715 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1716 MachineOperand &Use = MI->getOperand(i);
1717 if (Use.isReg() && Use.isUse() && Use.getReg() &&
1718 tri_->regsOverlap(Use.getReg(), Reg)) {
1719 UseIdx = e.getUseIndex();
1724 e = e.getPrevIndex();
1730 void SimpleRegisterCoalescing::releaseMemory() {
1731 JoinedCopies.clear();
1732 ReMatCopies.clear();
1736 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1738 mri_ = &fn.getRegInfo();
1739 tm_ = &fn.getTarget();
1740 tri_ = tm_->getRegisterInfo();
1741 tii_ = tm_->getInstrInfo();
1742 li_ = &getAnalysis<LiveIntervals>();
1743 AA = &getAnalysis<AliasAnalysis>();
1744 loopInfo = &getAnalysis<MachineLoopInfo>();
1746 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1747 << "********** Function: "
1748 << ((Value*)mf_->getFunction())->getName() << '\n');
1750 allocatableRegs_ = tri_->getAllocatableSet(fn);
1751 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
1752 E = tri_->regclass_end(); I != E; ++I)
1753 allocatableRCRegs_.insert(std::make_pair(*I,
1754 tri_->getAllocatableSet(fn, *I)));
1756 // Join (coalesce) intervals if requested.
1757 if (EnableJoining) {
1760 dbgs() << "********** INTERVALS POST JOINING **********\n";
1761 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
1763 I->second->print(dbgs(), tri_);
1769 // Perform a final pass over the instructions and compute spill weights
1770 // and remove identity moves.
1771 SmallVector<unsigned, 4> DeadDefs;
1772 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1773 mbbi != mbbe; ++mbbi) {
1774 MachineBasicBlock* mbb = mbbi;
1775 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1777 MachineInstr *MI = mii;
1778 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1779 if (JoinedCopies.count(MI)) {
1780 // Delete all coalesced copies.
1781 bool DoDelete = true;
1782 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
1783 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1784 SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1785 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
1786 // Do not delete extract_subreg, insert_subreg of physical
1787 // registers unless the definition is dead. e.g.
1788 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
1789 // or else the scavenger may complain. LowerSubregs will
1790 // delete them later.
1793 if (MI->allDefsAreDead()) {
1794 LiveInterval &li = li_->getInterval(SrcReg);
1795 if (!ShortenDeadCopySrcLiveRange(li, MI))
1796 ShortenDeadCopyLiveRange(li, MI);
1800 mii = llvm::next(mii);
1802 li_->RemoveMachineInstrFromMaps(MI);
1803 mii = mbbi->erase(mii);
1809 // Now check if this is a remat'ed def instruction which is now dead.
1810 if (ReMatDefs.count(MI)) {
1812 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1813 const MachineOperand &MO = MI->getOperand(i);
1816 unsigned Reg = MO.getReg();
1819 if (TargetRegisterInfo::isVirtualRegister(Reg))
1820 DeadDefs.push_back(Reg);
1823 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1824 !mri_->use_nodbg_empty(Reg)) {
1830 while (!DeadDefs.empty()) {
1831 unsigned DeadDef = DeadDefs.back();
1832 DeadDefs.pop_back();
1833 RemoveDeadDef(li_->getInterval(DeadDef), MI);
1835 li_->RemoveMachineInstrFromMaps(mii);
1836 mii = mbbi->erase(mii);
1842 // If the move will be an identity move delete it
1843 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
1844 if (MI->isIdentityCopy() ||
1845 (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) {
1846 if (li_->hasInterval(SrcReg)) {
1847 LiveInterval &RegInt = li_->getInterval(SrcReg);
1848 // If def of this move instruction is dead, remove its live range
1849 // from the destination register's live interval.
1850 if (MI->allDefsAreDead()) {
1851 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
1852 ShortenDeadCopyLiveRange(RegInt, MI);
1855 li_->RemoveMachineInstrFromMaps(MI);
1856 mii = mbbi->erase(mii);
1863 // Check for now unnecessary kill flags.
1864 if (li_->isNotInMIMap(MI)) continue;
1865 SlotIndex DefIdx = li_->getInstructionIndex(MI).getDefIndex();
1866 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1867 MachineOperand &MO = MI->getOperand(i);
1868 if (!MO.isReg() || !MO.isKill()) continue;
1869 unsigned reg = MO.getReg();
1870 if (!reg || !li_->hasInterval(reg)) continue;
1871 if (!li_->getInterval(reg).killedAt(DefIdx))
1872 MO.setIsKill(false);
1881 /// print - Implement the dump method.
1882 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
1886 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1887 return new SimpleRegisterCoalescing();
1890 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1891 DEFINING_FILE_FOR(SimpleRegisterCoalescing)