1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(numJoins , "Number of interval joins performed");
39 STATISTIC(numCrossRCs , "Number of cross class joins performed");
40 STATISTIC(numCommutes , "Number of instruction commuting performed");
41 STATISTIC(numExtends , "Number of copies extended");
42 STATISTIC(NumReMats , "Number of instructions re-materialized");
43 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
44 STATISTIC(numAborts , "Number of times interval joining aborted");
45 STATISTIC(numDeadValNo, "Number of valno def marked dead");
47 char SimpleRegisterCoalescing::ID = 0;
49 EnableJoining("join-liveintervals",
50 cl::desc("Coalesce copies (default=true)"),
54 NewHeuristic("new-coalescer-heuristic",
55 cl::desc("Use new coalescer heuristic"),
56 cl::init(false), cl::Hidden);
59 CrossClassJoin("join-cross-class-copies",
60 cl::desc("Coalesce cross register class copies"),
61 cl::init(false), cl::Hidden);
63 static RegisterPass<SimpleRegisterCoalescing>
64 X("simple-register-coalescing", "Simple Register Coalescing");
66 // Declare that we implement the RegisterCoalescer interface
67 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
69 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
71 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<LiveIntervals>();
73 AU.addPreserved<LiveIntervals>();
74 AU.addRequired<MachineLoopInfo>();
75 AU.addPreserved<MachineLoopInfo>();
76 AU.addPreservedID(MachineDominatorsID);
78 AU.addPreservedID(StrongPHIEliminationID);
80 AU.addPreservedID(PHIEliminationID);
81 AU.addPreservedID(TwoAddressInstructionPassID);
82 MachineFunctionPass::getAnalysisUsage(AU);
85 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
86 /// being the source and IntB being the dest, thus this defines a value number
87 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
88 /// see if we can merge these two pieces of B into a single value number,
89 /// eliminating a copy. For example:
93 /// B1 = A3 <- this copy
95 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
96 /// value number to be replaced with B0 (which simplifies the B liveinterval).
98 /// This returns true if an interval was modified.
100 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
102 MachineInstr *CopyMI) {
103 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
105 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
106 // the example above.
107 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
108 assert(BLR != IntB.end() && "Live range not found!");
109 VNInfo *BValNo = BLR->valno;
111 // Get the location that B is defined at. Two options: either this value has
112 // an unknown definition point or it is defined at CopyIdx. If unknown, we
114 if (!BValNo->copy) return false;
115 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
117 // AValNo is the value number in A that defines the copy, A3 in the example.
118 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
119 assert(ALR != IntA.end() && "Live range not found!");
120 VNInfo *AValNo = ALR->valno;
121 // If it's re-defined by an early clobber somewhere in the live range, then
122 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
124 // 172 %ECX<def> = MOV32rr %reg1039<kill>
125 // 180 INLINEASM <es:subl $5,$1
126 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
127 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
128 // 188 %EAX<def> = MOV32rr %EAX<kill>
129 // 196 %ECX<def> = MOV32rr %ECX<kill>
130 // 204 %ECX<def> = MOV32rr %ECX<kill>
131 // 212 %EAX<def> = MOV32rr %EAX<kill>
132 // 220 %EAX<def> = MOV32rr %EAX
133 // 228 %reg1039<def> = MOV32rr %ECX<kill>
134 // The early clobber operand ties ECX input to the ECX def.
136 // The live interval of ECX is represented as this:
137 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
138 // The coalescer has no idea there was a def in the middle of [174,230].
139 if (AValNo->redefByEC)
142 // If AValNo is defined as a copy from IntB, we can potentially process this.
143 // Get the instruction that defines this value number.
144 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
145 if (!SrcReg) return false; // Not defined by a copy.
147 // If the value number is not defined by a copy instruction, ignore it.
149 // If the source register comes from an interval other than IntB, we can't
151 if (SrcReg != IntB.reg) return false;
153 // Get the LiveRange in IntB that this value number starts with.
154 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
155 assert(ValLR != IntB.end() && "Live range not found!");
157 // Make sure that the end of the live range is inside the same block as
159 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
161 ValLREndInst->getParent() != CopyMI->getParent()) return false;
163 // Okay, we now know that ValLR ends in the same block that the CopyMI
164 // live-range starts. If there are no intervening live ranges between them in
165 // IntB, we can merge them.
166 if (ValLR+1 != BLR) return false;
168 // If a live interval is a physical register, conservatively check if any
169 // of its sub-registers is overlapping the live interval of the virtual
170 // register. If so, do not coalesce.
171 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
172 *tri_->getSubRegisters(IntB.reg)) {
173 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
174 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
175 DOUT << "Interfere with sub-register ";
176 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
181 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
183 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
184 // We are about to delete CopyMI, so need to remove it as the 'instruction
185 // that defines this value #'. Update the the valnum with the new defining
187 BValNo->def = FillerStart;
190 // Okay, we can merge them. We need to insert a new liverange:
191 // [ValLR.end, BLR.begin) of either value number, then we merge the
192 // two value numbers.
193 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
195 // If the IntB live range is assigned to a physical register, and if that
196 // physreg has sub-registers, update their live intervals as well.
197 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
198 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
199 LiveInterval &SRLI = li_->getInterval(*SR);
200 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
201 SRLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
205 // Okay, merge "B1" into the same value number as "B0".
206 if (BValNo != ValLR->valno) {
207 IntB.addKills(ValLR->valno, BValNo->kills);
208 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
210 DOUT << " result = "; IntB.print(DOUT, tri_);
213 // If the source instruction was killing the source register before the
214 // merge, unset the isKill marker given the live range has been extended.
215 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
217 ValLREndInst->getOperand(UIdx).setIsKill(false);
218 IntB.removeKill(ValLR->valno, FillerStart);
225 /// HasOtherReachingDefs - Return true if there are definitions of IntB
226 /// other than BValNo val# that can reach uses of AValno val# of IntA.
227 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
231 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
233 if (AI->valno != AValNo) continue;
234 LiveInterval::Ranges::iterator BI =
235 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
236 if (BI != IntB.ranges.begin())
238 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
239 if (BI->valno == BValNo)
241 if (BI->start <= AI->start && BI->end > AI->start)
243 if (BI->start > AI->start && BI->start < AI->end)
250 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
251 /// being the source and IntB being the dest, thus this defines a value number
252 /// in IntB. If the source value number (in IntA) is defined by a commutable
253 /// instruction and its other operand is coalesced to the copy dest register,
254 /// see if we can transform the copy into a noop by commuting the definition. For
257 /// A3 = op A2 B0<kill>
259 /// B1 = A3 <- this copy
261 /// = op A3 <- more uses
265 /// B2 = op B0 A2<kill>
267 /// B1 = B2 <- now an identify copy
269 /// = op B2 <- more uses
271 /// This returns true if an interval was modified.
273 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
275 MachineInstr *CopyMI) {
276 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
278 // FIXME: For now, only eliminate the copy by commuting its def when the
279 // source register is a virtual register. We want to guard against cases
280 // where the copy is a back edge copy and commuting the def lengthen the
281 // live interval of the source register to the entire loop.
282 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
285 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
286 // the example above.
287 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
288 assert(BLR != IntB.end() && "Live range not found!");
289 VNInfo *BValNo = BLR->valno;
291 // Get the location that B is defined at. Two options: either this value has
292 // an unknown definition point or it is defined at CopyIdx. If unknown, we
294 if (!BValNo->copy) return false;
295 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
297 // AValNo is the value number in A that defines the copy, A3 in the example.
298 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
299 assert(ALR != IntA.end() && "Live range not found!");
300 VNInfo *AValNo = ALR->valno;
301 // If other defs can reach uses of this def, then it's not safe to perform
303 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
305 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
306 const TargetInstrDesc &TID = DefMI->getDesc();
308 if (!TID.isCommutable() ||
309 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
312 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
313 unsigned NewReg = NewDstMO.getReg();
314 if (NewReg != IntB.reg || !NewDstMO.isKill())
317 // Make sure there are no other definitions of IntB that would reach the
318 // uses which the new definition can reach.
319 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
322 // If some of the uses of IntA.reg is already coalesced away, return false.
323 // It's not possible to determine whether it's safe to perform the coalescing.
324 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
325 UE = mri_->use_end(); UI != UE; ++UI) {
326 MachineInstr *UseMI = &*UI;
327 unsigned UseIdx = li_->getInstructionIndex(UseMI);
328 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
329 if (ULR == IntA.end())
331 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
335 // At this point we have decided that it is legal to do this
336 // transformation. Start by commuting the instruction.
337 MachineBasicBlock *MBB = DefMI->getParent();
338 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
341 if (NewMI != DefMI) {
342 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
343 MBB->insert(DefMI, NewMI);
346 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
347 NewMI->getOperand(OpIdx).setIsKill();
349 bool BHasPHIKill = BValNo->hasPHIKill;
350 SmallVector<VNInfo*, 4> BDeadValNos;
351 SmallVector<unsigned, 4> BKills;
352 std::map<unsigned, unsigned> BExtend;
354 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
363 // then do not add kills of A to the newly created B interval.
364 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
366 BExtend[ALR->end] = BLR->end;
368 // Update uses of IntA of the specific Val# with IntB.
369 bool BHasSubRegs = false;
370 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
371 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
372 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
373 UE = mri_->use_end(); UI != UE;) {
374 MachineOperand &UseMO = UI.getOperand();
375 MachineInstr *UseMI = &*UI;
377 if (JoinedCopies.count(UseMI))
379 unsigned UseIdx = li_->getInstructionIndex(UseMI);
380 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
381 if (ULR == IntA.end() || ULR->valno != AValNo)
383 UseMO.setReg(NewReg);
386 if (UseMO.isKill()) {
388 UseMO.setIsKill(false);
390 BKills.push_back(li_->getUseIndex(UseIdx)+1);
392 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
393 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
395 if (DstReg == IntB.reg) {
396 // This copy will become a noop. If it's defining a new val#,
397 // remove that val# as well. However this live range is being
398 // extended to the end of the existing live range defined by the copy.
399 unsigned DefIdx = li_->getDefIndex(UseIdx);
400 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
401 BHasPHIKill |= DLR->valno->hasPHIKill;
402 assert(DLR->valno->def == DefIdx);
403 BDeadValNos.push_back(DLR->valno);
404 BExtend[DLR->start] = DLR->end;
405 JoinedCopies.insert(UseMI);
406 // If this is a kill but it's going to be removed, the last use
407 // of the same val# is the new kill.
413 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
414 // simply extend BLR if CopyMI doesn't end the range.
415 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
417 // Remove val#'s defined by copies that will be coalesced away.
418 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
419 VNInfo *DeadVNI = BDeadValNos[i];
421 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
422 LiveInterval &SRLI = li_->getInterval(*SR);
423 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
424 SRLI.removeValNo(SRLR->valno);
427 IntB.removeValNo(BDeadValNos[i]);
430 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
431 // is updated. Kills are also updated.
432 VNInfo *ValNo = BValNo;
433 ValNo->def = AValNo->def;
435 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
436 unsigned Kill = ValNo->kills[j];
437 if (Kill != BLR->end)
438 BKills.push_back(Kill);
440 ValNo->kills.clear();
441 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
443 if (AI->valno != AValNo) continue;
444 unsigned End = AI->end;
445 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
446 if (EI != BExtend.end())
448 IntB.addRange(LiveRange(AI->start, End, ValNo));
450 // If the IntB live range is assigned to a physical register, and if that
451 // physreg has sub-registers, update their live intervals as well.
453 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
454 LiveInterval &SRLI = li_->getInterval(*SR);
455 SRLI.MergeInClobberRange(AI->start, End, li_->getVNInfoAllocator());
459 IntB.addKills(ValNo, BKills);
460 ValNo->hasPHIKill = BHasPHIKill;
462 DOUT << " result = "; IntB.print(DOUT, tri_);
465 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
466 IntA.removeValNo(AValNo);
467 DOUT << " result = "; IntA.print(DOUT, tri_);
474 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
475 /// fallthoughs to SuccMBB.
476 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
477 MachineBasicBlock *SuccMBB,
478 const TargetInstrInfo *tii_) {
481 MachineBasicBlock *TBB = 0, *FBB = 0;
482 SmallVector<MachineOperand, 4> Cond;
483 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
484 MBB->isSuccessor(SuccMBB);
487 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
488 /// from a physical register live interval as well as from the live intervals
489 /// of its sub-registers.
490 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
491 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
492 li.removeRange(Start, End, true);
493 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
494 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
495 if (!li_->hasInterval(*SR))
497 LiveInterval &sli = li_->getInterval(*SR);
498 unsigned RemoveEnd = Start;
499 while (RemoveEnd != End) {
500 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
503 RemoveEnd = (LR->end < End) ? LR->end : End;
504 sli.removeRange(Start, RemoveEnd, true);
511 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
512 /// as the copy instruction, trim the live interval to the last use and return
515 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
516 MachineBasicBlock *CopyMBB,
518 const LiveRange *LR) {
519 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
521 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
524 MachineInstr *LastUseMI = LastUse->getParent();
525 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
532 // r1025<dead> = r1024<kill>
533 if (MBBStart < LR->end)
534 removeRange(li, MBBStart, LR->end, li_, tri_);
538 // There are uses before the copy, just shorten the live range to the end
540 LastUse->setIsKill();
541 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
542 li.addKill(LR->valno, LastUseIdx+1);
543 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
544 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
546 // Last use is itself an identity code.
547 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
548 LastUseMI->getOperand(DeadIdx).setIsDead();
554 if (LR->start <= MBBStart && LR->end > MBBStart) {
555 if (LR->start == 0) {
556 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
557 // Live-in to the function but dead. Remove it from entry live-in set.
558 mf_->begin()->removeLiveIn(li.reg);
560 // FIXME: Shorten intervals in BBs that reaches this BB.
566 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
567 /// computation, replace the copy by rematerialize the definition.
568 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
570 MachineInstr *CopyMI) {
571 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
572 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
573 assert(SrcLR != SrcInt.end() && "Live range not found!");
574 VNInfo *ValNo = SrcLR->valno;
575 // If other defs can reach uses of this def, then it's not safe to perform
577 if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
579 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
580 const TargetInstrDesc &TID = DefMI->getDesc();
581 if (!TID.isAsCheapAsAMove())
583 if (!DefMI->getDesc().isRematerializable() ||
584 !tii_->isTriviallyReMaterializable(DefMI))
586 bool SawStore = false;
587 if (!DefMI->isSafeToMove(tii_, SawStore))
590 unsigned DefIdx = li_->getDefIndex(CopyIdx);
591 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
592 DLR->valno->copy = NULL;
593 // Don't forget to update sub-register intervals.
594 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
595 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
596 if (!li_->hasInterval(*SR))
598 DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
599 if (DLR && DLR->valno->copy == CopyMI)
600 DLR->valno->copy = NULL;
604 // If copy kills the source register, find the last use and propagate
606 MachineBasicBlock *MBB = CopyMI->getParent();
607 if (CopyMI->killsRegister(SrcInt.reg))
608 TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR);
610 MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
611 CopyMI->removeFromParent();
612 tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
613 MachineInstr *NewMI = prior(MII);
614 // CopyMI may have implicit operands, transfer them over to the newly
615 // rematerialized instruction. And update implicit def interval valnos.
616 for (unsigned i = CopyMI->getDesc().getNumOperands(),
617 e = CopyMI->getNumOperands(); i != e; ++i) {
618 MachineOperand &MO = CopyMI->getOperand(i);
619 if (MO.isReg() && MO.isImplicit())
620 NewMI->addOperand(MO);
621 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
622 unsigned Reg = MO.getReg();
623 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
624 if (DLR && DLR->valno->copy == CopyMI)
625 DLR->valno->copy = NULL;
629 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
630 MBB->getParent()->DeleteMachineInstr(CopyMI);
631 ReMatCopies.insert(CopyMI);
632 ReMatDefs.insert(DefMI);
637 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
639 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
640 unsigned DstReg) const {
641 MachineBasicBlock *MBB = CopyMI->getParent();
642 const MachineLoop *L = loopInfo->getLoopFor(MBB);
645 if (MBB != L->getLoopLatch())
648 LiveInterval &LI = li_->getInterval(DstReg);
649 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
650 LiveInterval::const_iterator DstLR =
651 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
652 if (DstLR == LI.end())
654 unsigned KillIdx = li_->getMBBEndIdx(MBB) + 1;
655 if (DstLR->valno->kills.size() == 1 &&
656 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
661 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
662 /// update the subregister number if it is not zero. If DstReg is a
663 /// physical register and the existing subregister number of the def / use
664 /// being updated is not zero, make sure to set it to the correct physical
667 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
669 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
670 if (DstIsPhys && SubIdx) {
671 // Figure out the real physical register we are updating with.
672 DstReg = tri_->getSubReg(DstReg, SubIdx);
676 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
677 E = mri_->reg_end(); I != E; ) {
678 MachineOperand &O = I.getOperand();
679 MachineInstr *UseMI = &*I;
681 unsigned OldSubIdx = O.getSubReg();
683 unsigned UseDstReg = DstReg;
685 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
687 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
688 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
689 CopySrcSubIdx, CopyDstSubIdx) &&
690 CopySrcReg != CopyDstReg &&
691 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
692 // If the use is a copy and it won't be coalesced away, and its source
693 // is defined by a trivial computation, try to rematerialize it instead.
694 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
703 // Sub-register indexes goes from small to large. e.g.
704 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
705 // EAX: 1 -> AL, 2 -> AX
706 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
707 // sub-register 2 is also AX.
708 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
709 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
712 // Remove would-be duplicated kill marker.
713 if (O.isKill() && UseMI->killsRegister(DstReg))
717 // After updating the operand, check if the machine instruction has
718 // become a copy. If so, update its val# information.
719 const TargetInstrDesc &TID = UseMI->getDesc();
720 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
721 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
722 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
723 CopySrcSubIdx, CopyDstSubIdx) &&
724 CopySrcReg != CopyDstReg &&
725 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
726 allocatableRegs_[CopyDstReg])) {
727 LiveInterval &LI = li_->getInterval(CopyDstReg);
728 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
729 const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx);
730 if (DLR->valno->def == DefIdx)
731 DLR->valno->copy = UseMI;
736 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
737 /// registers due to insert_subreg coalescing. e.g.
739 /// r1025 = implicit_def
740 /// r1025 = insert_subreg r1025, r1024
744 /// r1025 = implicit_def
745 /// r1025 = insert_subreg r1025, r1025
748 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
749 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
750 E = mri_->reg_end(); I != E; ) {
751 MachineOperand &O = I.getOperand();
752 MachineInstr *DefMI = &*I;
756 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
758 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
760 li_->RemoveMachineInstrFromMaps(DefMI);
761 DefMI->eraseFromParent();
765 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
766 /// due to live range lengthening as the result of coalescing.
767 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
769 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
770 UE = mri_->use_end(); UI != UE; ++UI) {
771 MachineOperand &UseMO = UI.getOperand();
772 if (UseMO.isKill()) {
773 MachineInstr *UseMI = UseMO.getParent();
774 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
775 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
776 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
777 UseMO.setIsKill(false);
782 /// removeIntervalIfEmpty - Check if the live interval of a physical register
783 /// is empty, if so remove it and also remove the empty intervals of its
784 /// sub-registers. Return true if live interval is removed.
785 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
786 const TargetRegisterInfo *tri_) {
788 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
789 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
790 if (!li_->hasInterval(*SR))
792 LiveInterval &sli = li_->getInterval(*SR);
794 li_->removeInterval(*SR);
796 li_->removeInterval(li.reg);
802 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
803 /// Return true if live interval is removed.
804 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
805 MachineInstr *CopyMI) {
806 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
807 LiveInterval::iterator MLR =
808 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
810 return false; // Already removed by ShortenDeadCopySrcLiveRange.
811 unsigned RemoveStart = MLR->start;
812 unsigned RemoveEnd = MLR->end;
813 // Remove the liverange that's defined by this.
814 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
815 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
816 return removeIntervalIfEmpty(li, li_, tri_);
821 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
822 /// the val# it defines. If the live interval becomes empty, remove it as well.
823 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
824 MachineInstr *DefMI) {
825 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
826 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
827 if (DefIdx != MLR->valno->def)
829 li.removeValNo(MLR->valno);
830 return removeIntervalIfEmpty(li, li_, tri_);
833 /// PropagateDeadness - Propagate the dead marker to the instruction which
834 /// defines the val#.
835 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
836 unsigned &LRStart, LiveIntervals *li_,
837 const TargetRegisterInfo* tri_) {
838 MachineInstr *DefMI =
839 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
840 if (DefMI && DefMI != CopyMI) {
841 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
843 DefMI->getOperand(DeadIdx).setIsDead();
844 // A dead def should have a single cycle interval.
850 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
851 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
852 /// ends the live range there. If there isn't another use, then this live range
853 /// is dead. Return true if live interval is removed.
855 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
856 MachineInstr *CopyMI) {
857 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
859 // FIXME: special case: function live in. It can be a general case if the
860 // first instruction index starts at > 0 value.
861 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
862 // Live-in to the function but dead. Remove it from entry live-in set.
863 if (mf_->begin()->isLiveIn(li.reg))
864 mf_->begin()->removeLiveIn(li.reg);
865 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
866 removeRange(li, LR->start, LR->end, li_, tri_);
867 return removeIntervalIfEmpty(li, li_, tri_);
870 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
872 // Livein but defined by a phi.
875 unsigned RemoveStart = LR->start;
876 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
877 if (LR->end > RemoveEnd)
878 // More uses past this copy? Nothing to do.
881 // If there is a last use in the same bb, we can't remove the live range.
882 // Shorten the live interval and return.
883 MachineBasicBlock *CopyMBB = CopyMI->getParent();
884 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
887 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
888 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
889 // If the live range starts in another mbb and the copy mbb is not a fall
890 // through mbb, then we can only cut the range from the beginning of the
892 RemoveStart = li_->getMBBStartIdx(CopyMBB) + 1;
894 if (LR->valno->def == RemoveStart) {
895 // If the def MI defines the val# and this copy is the only kill of the
896 // val#, then propagate the dead marker.
897 if (li.isOnlyLROfValNo(LR)) {
898 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
901 if (li.isKill(LR->valno, RemoveEnd))
902 li.removeKill(LR->valno, RemoveEnd);
905 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
906 return removeIntervalIfEmpty(li, li_, tri_);
909 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
910 /// from an implicit def to another register can be coalesced away.
911 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
913 LiveInterval &ImpLi) const{
914 if (!CopyMI->killsRegister(ImpLi.reg))
916 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
917 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
920 if (LR->valno->hasPHIKill)
922 if (LR->valno->def != CopyIdx)
924 // Make sure all of val# uses are copies.
925 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
926 UE = mri_->use_end(); UI != UE;) {
927 MachineInstr *UseMI = &*UI;
929 if (JoinedCopies.count(UseMI))
931 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
932 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
933 if (ULR == li.end() || ULR->valno != LR->valno)
935 // If the use is not a use, then it's not safe to coalesce the move.
936 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
937 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
938 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
939 UseMI->getOperand(1).getReg() == li.reg)
948 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
949 /// def and it is being removed. Turn all copies from this value# into
950 /// identity copies so they will be removed.
951 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
953 SmallVector<MachineInstr*, 4> ImpDefs;
954 MachineOperand *LastUse = NULL;
955 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
956 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
957 RE = mri_->reg_end(); RI != RE;) {
958 MachineOperand *MO = &RI.getOperand();
959 MachineInstr *MI = &*RI;
962 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
963 ImpDefs.push_back(MI);
967 if (JoinedCopies.count(MI))
969 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
970 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
971 if (ULR == li.end() || ULR->valno != VNI)
973 // If the use is a copy, turn it into an identity copy.
974 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
975 if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
977 // Each use MI may have multiple uses of this register. Change them all.
978 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
979 MachineOperand &MO = MI->getOperand(i);
980 if (MO.isReg() && MO.getReg() == li.reg)
983 JoinedCopies.insert(MI);
984 } else if (UseIdx > LastUseIdx) {
990 LastUse->setIsKill();
991 li.addKill(VNI, LastUseIdx+1);
993 // Remove dead implicit_def's.
994 while (!ImpDefs.empty()) {
995 MachineInstr *ImpDef = ImpDefs.back();
997 li_->RemoveMachineInstrFromMaps(ImpDef);
998 ImpDef->eraseFromParent();
1003 /// getMatchingSuperReg - Return a super-register of the specified register
1004 /// Reg so its sub-register of index SubIdx is Reg.
1005 static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
1006 const TargetRegisterClass *RC,
1007 const TargetRegisterInfo* TRI) {
1008 for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
1009 unsigned SR = *SRs; ++SRs)
1010 if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
1015 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1016 /// two virtual registers from different register classes.
1018 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned LargeReg,
1020 unsigned Threshold) {
1021 // Then make sure the intervals are *short*.
1022 LiveInterval &LargeInt = li_->getInterval(LargeReg);
1023 LiveInterval &SmallInt = li_->getInterval(SmallReg);
1024 unsigned LargeSize = li_->getApproximateInstructionCount(LargeInt);
1025 unsigned SmallSize = li_->getApproximateInstructionCount(SmallInt);
1026 if (SmallSize > Threshold || LargeSize > Threshold)
1027 if ((float)std::distance(mri_->use_begin(SmallReg),
1028 mri_->use_end()) / SmallSize <
1029 (float)std::distance(mri_->use_begin(LargeReg),
1030 mri_->use_end()) / LargeSize)
1035 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1036 /// register with a physical register, check if any of the virtual register
1037 /// operand is a sub-register use or def. If so, make sure it won't result
1038 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1039 /// vr1024 = extract_subreg vr1025, 1
1041 /// vr1024 = mov8rr AH
1042 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1043 /// AH does not have a super-reg whose sub-register 1 is AH.
1045 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1048 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1049 E = mri_->reg_end(); I != E; ++I) {
1050 MachineOperand &O = I.getOperand();
1051 MachineInstr *MI = &*I;
1052 if (MI == CopyMI || JoinedCopies.count(MI))
1054 unsigned SubIdx = O.getSubReg();
1055 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1057 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1058 SubIdx = MI->getOperand(2).getImm();
1059 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1062 unsigned SrcReg = MI->getOperand(1).getReg();
1063 const TargetRegisterClass *RC =
1064 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1065 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1066 : mri_->getRegClass(SrcReg);
1067 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
1071 if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
1072 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
1073 SubIdx = MI->getOperand(3).getImm();
1074 if (VirtReg == MI->getOperand(0).getReg()) {
1075 if (!tri_->getSubReg(PhysReg, SubIdx))
1078 unsigned DstReg = MI->getOperand(0).getReg();
1079 const TargetRegisterClass *RC =
1080 TargetRegisterInfo::isPhysicalRegister(DstReg)
1081 ? tri_->getPhysicalRegisterRegClass(DstReg)
1082 : mri_->getRegClass(DstReg);
1083 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
1092 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1093 /// an extract_subreg where dst is a physical register, e.g.
1094 /// cl = EXTRACT_SUBREG reg1024, 1
1096 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1097 unsigned SrcReg, unsigned SubIdx,
1098 unsigned &RealDstReg) {
1099 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1100 RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
1101 assert(RealDstReg && "Invalid extract_subreg instruction!");
1103 // For this type of EXTRACT_SUBREG, conservatively
1104 // check if the live interval of the source register interfere with the
1105 // actual super physical register we are trying to coalesce with.
1106 LiveInterval &RHS = li_->getInterval(SrcReg);
1107 if (li_->hasInterval(RealDstReg) &&
1108 RHS.overlaps(li_->getInterval(RealDstReg))) {
1109 DOUT << "Interfere with register ";
1110 DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
1111 return false; // Not coalescable
1113 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1114 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1115 DOUT << "Interfere with sub-register ";
1116 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1117 return false; // Not coalescable
1122 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1123 /// an insert_subreg where src is a physical register, e.g.
1124 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1126 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1127 unsigned SrcReg, unsigned SubIdx,
1128 unsigned &RealSrcReg) {
1129 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1130 RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
1131 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1133 LiveInterval &RHS = li_->getInterval(DstReg);
1134 if (li_->hasInterval(RealSrcReg) &&
1135 RHS.overlaps(li_->getInterval(RealSrcReg))) {
1136 DOUT << "Interfere with register ";
1137 DEBUG(li_->getInterval(RealSrcReg).print(DOUT, tri_));
1138 return false; // Not coalescable
1140 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1141 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1142 DOUT << "Interfere with sub-register ";
1143 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1144 return false; // Not coalescable
1149 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1150 /// which are the src/dst of the copy instruction CopyMI. This returns true
1151 /// if the copy was successfully coalesced away. If it is not currently
1152 /// possible to coalesce this interval, but it may be possible if other
1153 /// things get coalesced, then it returns true by reference in 'Again'.
1154 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1155 MachineInstr *CopyMI = TheCopy.MI;
1158 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1159 return false; // Already done.
1161 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
1163 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1164 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
1165 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
1166 bool isSubRegToReg = CopyMI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG;
1167 unsigned SubIdx = 0;
1169 DstReg = CopyMI->getOperand(0).getReg();
1170 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1171 SrcReg = CopyMI->getOperand(1).getReg();
1172 SrcSubIdx = CopyMI->getOperand(2).getImm();
1173 } else if (isInsSubReg || isSubRegToReg) {
1174 if (CopyMI->getOperand(2).getSubReg()) {
1175 DOUT << "\tSource of insert_subreg is already coalesced "
1176 << "to another register.\n";
1177 return false; // Not coalescable.
1179 DstReg = CopyMI->getOperand(0).getReg();
1180 DstSubIdx = CopyMI->getOperand(3).getImm();
1181 SrcReg = CopyMI->getOperand(2).getReg();
1182 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
1183 assert(0 && "Unrecognized copy instruction!");
1187 // If they are already joined we continue.
1188 if (SrcReg == DstReg) {
1189 DOUT << "\tCopy already coalesced.\n";
1190 return false; // Not coalescable.
1193 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1194 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1196 // If they are both physical registers, we cannot join them.
1197 if (SrcIsPhys && DstIsPhys) {
1198 DOUT << "\tCan not coalesce physregs.\n";
1199 return false; // Not coalescable.
1202 // We only join virtual registers with allocatable physical registers.
1203 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1204 DOUT << "\tSrc reg is unallocatable physreg.\n";
1205 return false; // Not coalescable.
1207 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1208 DOUT << "\tDst reg is unallocatable physreg.\n";
1209 return false; // Not coalescable.
1212 // Check that a physical source register is compatible with dst regclass
1214 unsigned SrcSubReg = SrcSubIdx ?
1215 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1216 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1217 const TargetRegisterClass *DstSubRC = DstRC;
1219 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1220 assert(DstSubRC && "Illegal subregister index");
1221 if (!DstSubRC->contains(SrcSubReg)) {
1222 DOUT << "\tIncompatible destination regclass: "
1223 << tri_->getName(SrcSubReg) << " not in " << DstSubRC->getName()
1225 return false; // Not coalescable.
1229 // Check that a physical dst register is compatible with source regclass
1231 unsigned DstSubReg = DstSubIdx ?
1232 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1233 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1234 const TargetRegisterClass *SrcSubRC = SrcRC;
1236 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1237 assert(SrcSubRC && "Illegal subregister index");
1238 if (!SrcSubRC->contains(DstReg)) {
1239 DOUT << "\tIncompatible source regclass: "
1240 << tri_->getName(DstSubReg) << " not in " << SrcSubRC->getName()
1242 return false; // Not coalescable.
1246 // Should be non-null only when coalescing to a sub-register class.
1247 bool CrossRC = false;
1248 const TargetRegisterClass *NewRC = NULL;
1249 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1250 unsigned RealDstReg = 0;
1251 unsigned RealSrcReg = 0;
1252 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1253 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1254 if (SrcIsPhys && isExtSubReg) {
1255 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1256 // coalesced with AX.
1257 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1259 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1260 // coalesced to a larger register so the subreg indices cancel out.
1261 if (DstSubIdx != SubIdx) {
1262 DOUT << "\t Sub-register indices mismatch.\n";
1263 return false; // Not coalescable.
1266 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1268 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1269 // EAX = INSERT_SUBREG EAX, r1024, 0
1270 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1272 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1273 // coalesced to a larger register so the subreg indices cancel out.
1274 if (SrcSubIdx != SubIdx) {
1275 DOUT << "\t Sub-register indices mismatch.\n";
1276 return false; // Not coalescable.
1279 DstReg = tri_->getSubReg(DstReg, SubIdx);
1281 } else if ((DstIsPhys && isExtSubReg) ||
1282 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1283 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1284 DOUT << "\tSrc of extract_subreg already coalesced with reg"
1285 << " of a super-class.\n";
1286 return false; // Not coalescable.
1290 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1291 return false; // Not coalescable
1293 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1294 return false; // Not coalescable
1298 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1299 : CopyMI->getOperand(2).getSubReg();
1301 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1302 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1303 // coalesced to a larger register so the subreg indices cancel out.
1304 // Also check if the other larger register is of the same register
1305 // class as the would be resulting register.
1308 DOUT << "\t Sub-register indices mismatch.\n";
1309 return false; // Not coalescable.
1313 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1314 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1315 unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
1316 if (!isWinToJoinCrossClass(LargeReg, SmallReg, Limit)) {
1317 Again = true; // May be possible to coalesce later.
1322 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1323 if (!CrossClassJoin)
1327 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1328 // with another? If it's the resulting destination register, then
1329 // the subidx must be propagated to uses (but only those defined
1330 // by the EXTRACT_SUBREG). If it's being coalesced into another
1331 // register, it should be safe because register is assumed to have
1332 // the register class of the super-register.
1334 // Process moves where one of the registers have a sub-register index.
1335 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1336 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1337 SubIdx = DstMO->getSubReg();
1339 if (SrcMO->getSubReg())
1340 // FIXME: can we handle this?
1342 // This is not an insert_subreg but it looks like one.
1343 // e.g. %reg1024:4 = MOV32rr %EAX
1346 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1347 return false; // Not coalescable
1351 SubIdx = SrcMO->getSubReg();
1353 // This is not a extract_subreg but it looks like one.
1354 // e.g. %cl = MOV16rr %reg1024:1
1357 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1358 return false; // Not coalescable
1364 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1365 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1366 unsigned LargeReg = SrcReg;
1367 unsigned SmallReg = DstReg;
1370 // Now determine the register class of the joined register.
1372 if (SubIdx && DstRC && DstRC->isASubClass()) {
1373 // This is a move to a sub-register class. However, the source is a
1374 // sub-register of a larger register class. We don't know what should
1375 // the register class be. FIXME.
1379 Limit = allocatableRCRegs_[DstRC].count();
1380 } else if (!SrcIsPhys && !DstIsPhys) {
1381 unsigned SrcSize = SrcRC->getSize();
1382 unsigned DstSize = DstRC->getSize();
1383 if (SrcSize < DstSize)
1384 // For example X86::MOVSD2PDrr copies from FR64 to VR128.
1386 else if (DstSize > SrcSize) {
1388 std::swap(LargeReg, SmallReg);
1390 unsigned SrcNumRegs = SrcRC->getNumRegs();
1391 unsigned DstNumRegs = DstRC->getNumRegs();
1392 if (DstNumRegs < SrcNumRegs)
1393 // Sub-register class?
1395 else if (SrcNumRegs < DstNumRegs) {
1397 std::swap(LargeReg, SmallReg);
1399 // No idea what's the right register class to use.
1404 // If we are joining two virtual registers and the resulting register
1405 // class is more restrictive (fewer register, smaller size). Check if it's
1406 // worth doing the merge.
1407 if (!SrcIsPhys && !DstIsPhys &&
1408 (isExtSubReg || DstRC->isASubClass()) &&
1409 !isWinToJoinCrossClass(LargeReg, SmallReg,
1410 allocatableRCRegs_[NewRC].count())) {
1411 DOUT << "\tSrc/Dest are different register classes.\n";
1412 // Allow the coalescer to try again in case either side gets coalesced to
1413 // a physical register that's compatible with the other side. e.g.
1414 // r1024 = MOV32to32_ r1025
1415 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1416 Again = true; // May be possible to coalesce later.
1421 // Will it create illegal extract_subreg / insert_subreg?
1422 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1424 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1427 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1428 LiveInterval &DstInt = li_->getInterval(DstReg);
1429 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1430 "Register mapping is horribly broken!");
1432 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1433 DOUT << " and "; DstInt.print(DOUT, tri_);
1436 // Save a copy of the virtual register live interval. We'll manually
1437 // merge this into the "real" physical register live interval this is
1439 LiveInterval *SavedLI = 0;
1441 SavedLI = li_->dupInterval(&SrcInt);
1442 else if (RealSrcReg)
1443 SavedLI = li_->dupInterval(&DstInt);
1445 // Check if it is necessary to propagate "isDead" property.
1446 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1447 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1448 bool isDead = mopd->isDead();
1450 // We need to be careful about coalescing a source physical register with a
1451 // virtual register. Once the coalescing is done, it cannot be broken and
1452 // these are not spillable! If the destination interval uses are far away,
1453 // think twice about coalescing them!
1454 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1455 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1456 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1457 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1458 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1459 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1460 if (TheCopy.isBackEdge)
1461 Threshold *= 2; // Favors back edge copies.
1463 // If the virtual register live interval is long but it has low use desity,
1464 // do not join them, instead mark the physical register as its allocation
1466 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1467 if (Length > Threshold &&
1468 (((float)std::distance(mri_->use_begin(JoinVReg), mri_->use_end())
1469 / Length) < (1.0 / Threshold))) {
1470 JoinVInt.preference = JoinPReg;
1472 DOUT << "\tMay tie down a physical register, abort!\n";
1473 Again = true; // May be possible to coalesce later.
1479 // Okay, attempt to join these two intervals. On failure, this returns false.
1480 // Otherwise, if one of the intervals being joined is a physreg, this method
1481 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1482 // been modified, so we can use this information below to update aliases.
1483 bool Swapped = false;
1484 // If SrcInt is implicitly defined, it's safe to coalesce.
1485 bool isEmpty = SrcInt.empty();
1486 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1487 // Only coalesce an empty interval (defined by implicit_def) with
1488 // another interval which has a valno defined by the CopyMI and the CopyMI
1489 // is a kill of the implicit def.
1490 DOUT << "Not profitable!\n";
1494 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1495 // Coalescing failed.
1497 // If definition of source is defined by trivial computation, try
1498 // rematerializing it.
1499 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1500 ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
1503 // If we can eliminate the copy without merging the live ranges, do so now.
1504 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1505 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1506 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1507 JoinedCopies.insert(CopyMI);
1511 // Otherwise, we are unable to join the intervals.
1512 DOUT << "Interference!\n";
1513 Again = true; // May be possible to coalesce later.
1517 LiveInterval *ResSrcInt = &SrcInt;
1518 LiveInterval *ResDstInt = &DstInt;
1520 std::swap(SrcReg, DstReg);
1521 std::swap(ResSrcInt, ResDstInt);
1523 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1524 "LiveInterval::join didn't work right!");
1526 // If we're about to merge live ranges into a physical register live interval,
1527 // we have to update any aliased register's live ranges to indicate that they
1528 // have clobbered values for this range.
1529 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1530 // If this is a extract_subreg where dst is a physical register, e.g.
1531 // cl = EXTRACT_SUBREG reg1024, 1
1532 // then create and update the actual physical register allocated to RHS.
1533 if (RealDstReg || RealSrcReg) {
1534 LiveInterval &RealInt =
1535 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1536 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1537 E = SavedLI->vni_end(); I != E; ++I) {
1538 const VNInfo *ValNo = *I;
1539 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->copy,
1540 li_->getVNInfoAllocator());
1541 NewValNo->hasPHIKill = ValNo->hasPHIKill;
1542 NewValNo->redefByEC = ValNo->redefByEC;
1543 RealInt.addKills(NewValNo, ValNo->kills);
1544 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1546 RealInt.weight += SavedLI->weight;
1547 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1550 // Update the liveintervals of sub-registers.
1551 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1552 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1553 li_->getVNInfoAllocator());
1556 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1557 // larger super-register.
1558 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1559 !SrcIsPhys && !DstIsPhys) {
1560 if ((isExtSubReg && !Swapped) ||
1561 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1562 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
1563 std::swap(SrcReg, DstReg);
1564 std::swap(ResSrcInt, ResDstInt);
1568 // Coalescing to a virtual register that is of a sub-register class of the
1569 // other. Make sure the resulting register is set to the right register class.
1573 mri_->setRegClass(DstReg, NewRC);
1577 // Add all copies that define val# in the source interval into the queue.
1578 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1579 e = ResSrcInt->vni_end(); i != e; ++i) {
1580 const VNInfo *vni = *i;
1581 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1583 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1584 unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx;
1586 JoinedCopies.count(CopyMI) == 0 &&
1587 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg,
1588 NewSrcSubIdx, NewDstSubIdx)) {
1589 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1590 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1591 isBackEdgeCopy(CopyMI, DstReg)));
1596 // Remember to delete the copy instruction.
1597 JoinedCopies.insert(CopyMI);
1599 // Some live range has been lengthened due to colaescing, eliminate the
1600 // unnecessary kills.
1601 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1602 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1603 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1608 // r1024 = implicit_def
1611 RemoveDeadImpDef(DstReg, *ResDstInt);
1612 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1614 // SrcReg is guarateed to be the register whose live interval that is
1616 li_->removeInterval(SrcReg);
1618 // Manually deleted the live interval copy.
1625 // Now the copy is being coalesced away, the val# previously defined
1626 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1627 // length interval. Remove the val#.
1628 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1629 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1630 VNInfo *ImpVal = LR->valno;
1631 assert(ImpVal->def == CopyIdx);
1632 unsigned NextDef = LR->end;
1633 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1634 ResDstInt->removeValNo(ImpVal);
1635 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1636 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1637 // Special case: vr1024 = implicit_def
1638 // vr1024 = insert_subreg vr1024, vr1025, c
1639 // The insert_subreg becomes a "copy" that defines a val# which can itself
1640 // be coalesced away.
1641 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1642 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1643 LR->valno->copy = DefMI;
1647 // If resulting interval has a preference that no longer fits because of subreg
1648 // coalescing, just clear the preference.
1649 if (ResDstInt->preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1650 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1651 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1652 if (!RC->contains(ResDstInt->preference))
1653 ResDstInt->preference = 0;
1656 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1663 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1664 /// compute what the resultant value numbers for each value in the input two
1665 /// ranges will be. This is complicated by copies between the two which can
1666 /// and will commonly cause multiple value numbers to be merged into one.
1668 /// VN is the value number that we're trying to resolve. InstDefiningValue
1669 /// keeps track of the new InstDefiningValue assignment for the result
1670 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1671 /// whether a value in this or other is a copy from the opposite set.
1672 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1673 /// already been assigned.
1675 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1676 /// contains the value number the copy is from.
1678 static unsigned ComputeUltimateVN(VNInfo *VNI,
1679 SmallVector<VNInfo*, 16> &NewVNInfo,
1680 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1681 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1682 SmallVector<int, 16> &ThisValNoAssignments,
1683 SmallVector<int, 16> &OtherValNoAssignments) {
1684 unsigned VN = VNI->id;
1686 // If the VN has already been computed, just return it.
1687 if (ThisValNoAssignments[VN] >= 0)
1688 return ThisValNoAssignments[VN];
1689 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1691 // If this val is not a copy from the other val, then it must be a new value
1692 // number in the destination.
1693 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1694 if (I == ThisFromOther.end()) {
1695 NewVNInfo.push_back(VNI);
1696 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1698 VNInfo *OtherValNo = I->second;
1700 // Otherwise, this *is* a copy from the RHS. If the other side has already
1701 // been computed, return it.
1702 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1703 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1705 // Mark this value number as currently being computed, then ask what the
1706 // ultimate value # of the other value is.
1707 ThisValNoAssignments[VN] = -2;
1708 unsigned UltimateVN =
1709 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1710 OtherValNoAssignments, ThisValNoAssignments);
1711 return ThisValNoAssignments[VN] = UltimateVN;
1714 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1715 return std::find(V.begin(), V.end(), Val) != V.end();
1718 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1719 /// the specified live interval is defined by a copy from the specified
1721 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1724 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1727 if (LR->valno->def == ~0U &&
1728 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1729 *tri_->getSuperRegisters(li.reg)) {
1730 // It's a sub-register live interval, we may not have precise information.
1732 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1733 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1735 tii_->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1736 DstReg == li.reg && SrcReg == Reg) {
1737 // Cache computed info.
1738 LR->valno->def = LR->start;
1739 LR->valno->copy = DefMI;
1746 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1747 /// caller of this method must guarantee that the RHS only contains a single
1748 /// value number and that the RHS is not defined by a copy from this
1749 /// interval. This returns false if the intervals are not joinable, or it
1750 /// joins them and returns true.
1751 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1752 assert(RHS.containsOneValue());
1754 // Some number (potentially more than one) value numbers in the current
1755 // interval may be defined as copies from the RHS. Scan the overlapping
1756 // portions of the LHS and RHS, keeping track of this and looking for
1757 // overlapping live ranges that are NOT defined as copies. If these exist, we
1760 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1761 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1763 if (LHSIt->start < RHSIt->start) {
1764 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1765 if (LHSIt != LHS.begin()) --LHSIt;
1766 } else if (RHSIt->start < LHSIt->start) {
1767 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1768 if (RHSIt != RHS.begin()) --RHSIt;
1771 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1774 // Determine if these live intervals overlap.
1775 bool Overlaps = false;
1776 if (LHSIt->start <= RHSIt->start)
1777 Overlaps = LHSIt->end > RHSIt->start;
1779 Overlaps = RHSIt->end > LHSIt->start;
1781 // If the live intervals overlap, there are two interesting cases: if the
1782 // LHS interval is defined by a copy from the RHS, it's ok and we record
1783 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1784 // coalesce these live ranges and we bail out.
1786 // If we haven't already recorded that this value # is safe, check it.
1787 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1788 // Copy from the RHS?
1789 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1790 return false; // Nope, bail out.
1792 if (LHSIt->contains(RHSIt->valno->def))
1793 // Here is an interesting situation:
1795 // vr1025 = copy vr1024
1800 // Even though vr1025 is copied from vr1024, it's not safe to
1801 // coalesce them since the live range of vr1025 intersects the
1802 // def of vr1024. This happens because vr1025 is assigned the
1803 // value of the previous iteration of vr1024.
1805 EliminatedLHSVals.push_back(LHSIt->valno);
1808 // We know this entire LHS live range is okay, so skip it now.
1809 if (++LHSIt == LHSEnd) break;
1813 if (LHSIt->end < RHSIt->end) {
1814 if (++LHSIt == LHSEnd) break;
1816 // One interesting case to check here. It's possible that we have
1817 // something like "X3 = Y" which defines a new value number in the LHS,
1818 // and is the last use of this liverange of the RHS. In this case, we
1819 // want to notice this copy (so that it gets coalesced away) even though
1820 // the live ranges don't actually overlap.
1821 if (LHSIt->start == RHSIt->end) {
1822 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1823 // We already know that this value number is going to be merged in
1824 // if coalescing succeeds. Just skip the liverange.
1825 if (++LHSIt == LHSEnd) break;
1827 // Otherwise, if this is a copy from the RHS, mark it as being merged
1829 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1830 if (LHSIt->contains(RHSIt->valno->def))
1831 // Here is an interesting situation:
1833 // vr1025 = copy vr1024
1838 // Even though vr1025 is copied from vr1024, it's not safe to
1839 // coalesced them since live range of vr1025 intersects the
1840 // def of vr1024. This happens because vr1025 is assigned the
1841 // value of the previous iteration of vr1024.
1843 EliminatedLHSVals.push_back(LHSIt->valno);
1845 // We know this entire LHS live range is okay, so skip it now.
1846 if (++LHSIt == LHSEnd) break;
1851 if (++RHSIt == RHSEnd) break;
1855 // If we got here, we know that the coalescing will be successful and that
1856 // the value numbers in EliminatedLHSVals will all be merged together. Since
1857 // the most common case is that EliminatedLHSVals has a single number, we
1858 // optimize for it: if there is more than one value, we merge them all into
1859 // the lowest numbered one, then handle the interval as if we were merging
1860 // with one value number.
1861 VNInfo *LHSValNo = NULL;
1862 if (EliminatedLHSVals.size() > 1) {
1863 // Loop through all the equal value numbers merging them into the smallest
1865 VNInfo *Smallest = EliminatedLHSVals[0];
1866 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1867 if (EliminatedLHSVals[i]->id < Smallest->id) {
1868 // Merge the current notion of the smallest into the smaller one.
1869 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1870 Smallest = EliminatedLHSVals[i];
1872 // Merge into the smallest.
1873 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1876 LHSValNo = Smallest;
1877 } else if (EliminatedLHSVals.empty()) {
1878 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1879 *tri_->getSuperRegisters(LHS.reg))
1880 // Imprecise sub-register information. Can't handle it.
1882 assert(0 && "No copies from the RHS?");
1884 LHSValNo = EliminatedLHSVals[0];
1887 // Okay, now that there is a single LHS value number that we're merging the
1888 // RHS into, update the value number info for the LHS to indicate that the
1889 // value number is defined where the RHS value number was.
1890 const VNInfo *VNI = RHS.getValNumInfo(0);
1891 LHSValNo->def = VNI->def;
1892 LHSValNo->copy = VNI->copy;
1894 // Okay, the final step is to loop over the RHS live intervals, adding them to
1896 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
1897 LHS.addKills(LHSValNo, VNI->kills);
1898 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1899 LHS.weight += RHS.weight;
1900 if (RHS.preference && !LHS.preference)
1901 LHS.preference = RHS.preference;
1903 // Update the liveintervals of sub-registers.
1904 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
1905 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
1906 li_->getOrCreateInterval(*AS).MergeInClobberRanges(LHS,
1907 li_->getVNInfoAllocator());
1912 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1913 /// returns false. Otherwise, if one of the intervals being joined is a
1914 /// physreg, this method always canonicalizes LHS to be it. The output
1915 /// "RHS" will not have been modified, so we can use this information
1916 /// below to update aliases.
1918 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
1920 // Compute the final value assignment, assuming that the live ranges can be
1922 SmallVector<int, 16> LHSValNoAssignments;
1923 SmallVector<int, 16> RHSValNoAssignments;
1924 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1925 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1926 SmallVector<VNInfo*, 16> NewVNInfo;
1928 // If a live interval is a physical register, conservatively check if any
1929 // of its sub-registers is overlapping the live interval of the virtual
1930 // register. If so, do not coalesce.
1931 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1932 *tri_->getSubRegisters(LHS.reg)) {
1933 // If it's coalescing a virtual register to a physical register, estimate
1934 // its live interval length. This is the *cost* of scanning an entire live
1935 // interval. If the cost is low, we'll do an exhaustive check instead.
1937 // If this is something like this:
1945 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
1946 // less conservative check. It's possible a sub-register is defined before
1947 // v1024 (or live in) and live out of BB1.
1948 if (RHS.containsOneValue() &&
1949 li_->intervalIsInOneMBB(RHS) &&
1950 li_->getApproximateInstructionCount(RHS) <= 10) {
1951 // Perform a more exhaustive check for some common cases.
1952 if (li_->conflictsWithPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
1955 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1956 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1957 DOUT << "Interfere with sub-register ";
1958 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1962 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1963 *tri_->getSubRegisters(RHS.reg)) {
1964 if (LHS.containsOneValue() &&
1965 li_->getApproximateInstructionCount(LHS) <= 10) {
1966 // Perform a more exhaustive check for some common cases.
1967 if (li_->conflictsWithPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
1970 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1971 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1972 DOUT << "Interfere with sub-register ";
1973 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1979 // Compute ultimate value numbers for the LHS and RHS values.
1980 if (RHS.containsOneValue()) {
1981 // Copies from a liveinterval with a single value are simple to handle and
1982 // very common, handle the special case here. This is important, because
1983 // often RHS is small and LHS is large (e.g. a physreg).
1985 // Find out if the RHS is defined as a copy from some value in the LHS.
1986 int RHSVal0DefinedFromLHS = -1;
1988 VNInfo *RHSValNoInfo = NULL;
1989 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1990 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1991 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
1992 // If RHS is not defined as a copy from the LHS, we can use simpler and
1993 // faster checks to see if the live ranges are coalescable. This joiner
1994 // can't swap the LHS/RHS intervals though.
1995 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1996 return SimpleJoin(LHS, RHS);
1998 RHSValNoInfo = RHSValNoInfo0;
2001 // It was defined as a copy from the LHS, find out what value # it is.
2002 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
2003 RHSValID = RHSValNoInfo->id;
2004 RHSVal0DefinedFromLHS = RHSValID;
2007 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2008 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2009 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2011 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2012 // should now get updated.
2013 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2016 unsigned VN = VNI->id;
2017 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2018 if (LHSSrcReg != RHS.reg) {
2019 // If this is not a copy from the RHS, its value number will be
2020 // unmodified by the coalescing.
2021 NewVNInfo[VN] = VNI;
2022 LHSValNoAssignments[VN] = VN;
2023 } else if (RHSValID == -1) {
2024 // Otherwise, it is a copy from the RHS, and we don't already have a
2025 // value# for it. Keep the current value number, but remember it.
2026 LHSValNoAssignments[VN] = RHSValID = VN;
2027 NewVNInfo[VN] = RHSValNoInfo;
2028 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2030 // Otherwise, use the specified value #.
2031 LHSValNoAssignments[VN] = RHSValID;
2032 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2033 NewVNInfo[VN] = RHSValNoInfo;
2034 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2038 NewVNInfo[VN] = VNI;
2039 LHSValNoAssignments[VN] = VN;
2043 assert(RHSValID != -1 && "Didn't find value #?");
2044 RHSValNoAssignments[0] = RHSValID;
2045 if (RHSVal0DefinedFromLHS != -1) {
2046 // This path doesn't go through ComputeUltimateVN so just set
2048 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2051 // Loop over the value numbers of the LHS, seeing if any are defined from
2053 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2056 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
2059 // DstReg is known to be a register in the LHS interval. If the src is
2060 // from the RHS interval, we can use its value #.
2061 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2064 // Figure out the value # from the RHS.
2065 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
2068 // Loop over the value numbers of the RHS, seeing if any are defined from
2070 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2073 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
2076 // DstReg is known to be a register in the RHS interval. If the src is
2077 // from the LHS interval, we can use its value #.
2078 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2081 // Figure out the value # from the LHS.
2082 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
2085 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2086 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2087 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2089 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2092 unsigned VN = VNI->id;
2093 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
2095 ComputeUltimateVN(VNI, NewVNInfo,
2096 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2097 LHSValNoAssignments, RHSValNoAssignments);
2099 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2102 unsigned VN = VNI->id;
2103 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
2105 // If this value number isn't a copy from the LHS, it's a new number.
2106 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2107 NewVNInfo.push_back(VNI);
2108 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2112 ComputeUltimateVN(VNI, NewVNInfo,
2113 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2114 RHSValNoAssignments, LHSValNoAssignments);
2118 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2119 // interval lists to see if these intervals are coalescable.
2120 LiveInterval::const_iterator I = LHS.begin();
2121 LiveInterval::const_iterator IE = LHS.end();
2122 LiveInterval::const_iterator J = RHS.begin();
2123 LiveInterval::const_iterator JE = RHS.end();
2125 // Skip ahead until the first place of potential sharing.
2126 if (I->start < J->start) {
2127 I = std::upper_bound(I, IE, J->start);
2128 if (I != LHS.begin()) --I;
2129 } else if (J->start < I->start) {
2130 J = std::upper_bound(J, JE, I->start);
2131 if (J != RHS.begin()) --J;
2135 // Determine if these two live ranges overlap.
2137 if (I->start < J->start) {
2138 Overlaps = I->end > J->start;
2140 Overlaps = J->end > I->start;
2143 // If so, check value # info to determine if they are really different.
2145 // If the live range overlap will map to the same value number in the
2146 // result liverange, we can still coalesce them. If not, we can't.
2147 if (LHSValNoAssignments[I->valno->id] !=
2148 RHSValNoAssignments[J->valno->id])
2152 if (I->end < J->end) {
2161 // Update kill info. Some live ranges are extended due to copy coalescing.
2162 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2163 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2164 VNInfo *VNI = I->first;
2165 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2166 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
2167 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
2168 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2171 // Update kill info. Some live ranges are extended due to copy coalescing.
2172 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2173 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2174 VNInfo *VNI = I->first;
2175 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2176 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
2177 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
2178 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2181 // If we get here, we know that we can coalesce the live ranges. Ask the
2182 // intervals to coalesce themselves now.
2183 if ((RHS.ranges.size() > LHS.ranges.size() &&
2184 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2185 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2186 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
2189 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
2196 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2197 // depth of the basic block (the unsigned), and then on the MBB number.
2198 struct DepthMBBCompare {
2199 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2200 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2201 if (LHS.first > RHS.first) return true; // Deeper loops first
2202 return LHS.first == RHS.first &&
2203 LHS.second->getNumber() < RHS.second->getNumber();
2208 /// getRepIntervalSize - Returns the size of the interval that represents the
2209 /// specified register.
2211 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
2212 return Rc->getRepIntervalSize(Reg);
2215 /// CopyRecSort::operator - Join priority queue sorting function.
2217 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
2218 // Inner loops first.
2219 if (left.LoopDepth > right.LoopDepth)
2221 else if (left.LoopDepth == right.LoopDepth)
2222 if (left.isBackEdge && !right.isBackEdge)
2227 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2228 std::vector<CopyRec> &TryAgain) {
2229 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
2231 std::vector<CopyRec> VirtCopies;
2232 std::vector<CopyRec> PhysCopies;
2233 std::vector<CopyRec> ImpDefCopies;
2234 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
2235 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2237 MachineInstr *Inst = MII++;
2239 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2240 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2241 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
2242 DstReg = Inst->getOperand(0).getReg();
2243 SrcReg = Inst->getOperand(1).getReg();
2244 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2245 Inst->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
2246 DstReg = Inst->getOperand(0).getReg();
2247 SrcReg = Inst->getOperand(2).getReg();
2248 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2251 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2252 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2254 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
2256 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
2257 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
2258 else if (SrcIsPhys || DstIsPhys)
2259 PhysCopies.push_back(CopyRec(Inst, 0, false));
2261 VirtCopies.push_back(CopyRec(Inst, 0, false));
2268 // Try coalescing implicit copies first, followed by copies to / from
2269 // physical registers, then finally copies from virtual registers to
2270 // virtual registers.
2271 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2272 CopyRec &TheCopy = ImpDefCopies[i];
2274 if (!JoinCopy(TheCopy, Again))
2276 TryAgain.push_back(TheCopy);
2278 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2279 CopyRec &TheCopy = PhysCopies[i];
2281 if (!JoinCopy(TheCopy, Again))
2283 TryAgain.push_back(TheCopy);
2285 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2286 CopyRec &TheCopy = VirtCopies[i];
2288 if (!JoinCopy(TheCopy, Again))
2290 TryAgain.push_back(TheCopy);
2294 void SimpleRegisterCoalescing::joinIntervals() {
2295 DOUT << "********** JOINING INTERVALS ***********\n";
2298 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
2300 std::vector<CopyRec> TryAgainList;
2301 if (loopInfo->empty()) {
2302 // If there are no loops in the function, join intervals in function order.
2303 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2305 CopyCoalesceInMBB(I, TryAgainList);
2307 // Otherwise, join intervals in inner loops before other intervals.
2308 // Unfortunately we can't just iterate over loop hierarchy here because
2309 // there may be more MBB's than BB's. Collect MBB's for sorting.
2311 // Join intervals in the function prolog first. We want to join physical
2312 // registers with virtual registers before the intervals got too long.
2313 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2314 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2315 MachineBasicBlock *MBB = I;
2316 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2319 // Sort by loop depth.
2320 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2322 // Finally, join intervals in loop nest order.
2323 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2324 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2327 // Joining intervals can allow other intervals to be joined. Iteratively join
2328 // until we make no progress.
2330 SmallVector<CopyRec, 16> TryAgain;
2331 bool ProgressMade = true;
2332 while (ProgressMade) {
2333 ProgressMade = false;
2334 while (!JoinQueue->empty()) {
2335 CopyRec R = JoinQueue->pop();
2337 bool Success = JoinCopy(R, Again);
2339 ProgressMade = true;
2341 TryAgain.push_back(R);
2345 while (!TryAgain.empty()) {
2346 JoinQueue->push(TryAgain.back());
2347 TryAgain.pop_back();
2352 bool ProgressMade = true;
2353 while (ProgressMade) {
2354 ProgressMade = false;
2356 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2357 CopyRec &TheCopy = TryAgainList[i];
2360 bool Success = JoinCopy(TheCopy, Again);
2361 if (Success || !Again) {
2362 TheCopy.MI = 0; // Mark this one as done.
2363 ProgressMade = true;
2374 /// Return true if the two specified registers belong to different register
2375 /// classes. The registers may be either phys or virt regs.
2377 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2378 unsigned RegB) const {
2379 // Get the register classes for the first reg.
2380 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2381 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2382 "Shouldn't consider two physregs!");
2383 return !mri_->getRegClass(RegB)->contains(RegA);
2386 // Compare against the regclass for the second reg.
2387 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2388 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2389 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2390 return RegClassA != RegClassB;
2392 return !RegClassA->contains(RegB);
2395 /// lastRegisterUse - Returns the last use of the specific register between
2396 /// cycles Start and End or NULL if there are no uses.
2398 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2399 unsigned Reg, unsigned &UseIdx) const{
2401 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2402 MachineOperand *LastUse = NULL;
2403 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2404 E = mri_->use_end(); I != E; ++I) {
2405 MachineOperand &Use = I.getOperand();
2406 MachineInstr *UseMI = Use.getParent();
2407 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2408 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2410 // Ignore identity copies.
2412 unsigned Idx = li_->getInstructionIndex(UseMI);
2413 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2415 UseIdx = li_->getUseIndex(Idx);
2421 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2424 // Skip deleted instructions
2425 MachineInstr *MI = li_->getInstructionFromIndex(e);
2426 while ((e - InstrSlots::NUM) >= s && !MI) {
2427 e -= InstrSlots::NUM;
2428 MI = li_->getInstructionFromIndex(e);
2430 if (e < s || MI == NULL)
2433 // Ignore identity copies.
2434 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2435 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2437 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2438 MachineOperand &Use = MI->getOperand(i);
2439 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2440 tri_->regsOverlap(Use.getReg(), Reg)) {
2441 UseIdx = li_->getUseIndex(e);
2446 e -= InstrSlots::NUM;
2453 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2454 if (TargetRegisterInfo::isPhysicalRegister(reg))
2455 cerr << tri_->getName(reg);
2457 cerr << "%reg" << reg;
2460 void SimpleRegisterCoalescing::releaseMemory() {
2461 JoinedCopies.clear();
2462 ReMatCopies.clear();
2466 static bool isZeroLengthInterval(LiveInterval *li) {
2467 for (LiveInterval::Ranges::const_iterator
2468 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2469 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
2474 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
2475 /// turn the copy into an implicit def.
2477 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
2478 MachineBasicBlock *MBB,
2479 unsigned DstReg, unsigned SrcReg) {
2480 MachineInstr *CopyMI = &*I;
2481 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
2482 if (!li_->hasInterval(SrcReg))
2484 LiveInterval &SrcInt = li_->getInterval(SrcReg);
2485 if (!SrcInt.empty())
2487 if (!li_->hasInterval(DstReg))
2489 LiveInterval &DstInt = li_->getInterval(DstReg);
2490 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
2491 DstInt.removeValNo(DstLR->valno);
2492 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
2493 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
2494 CopyMI->RemoveOperand(i);
2495 bool NoUse = mri_->use_empty(SrcReg);
2497 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
2498 E = mri_->reg_end(); I != E; ) {
2499 assert(I.getOperand().isDef());
2500 MachineInstr *DefMI = &*I;
2502 // The implicit_def source has no other uses, delete it.
2503 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2504 li_->RemoveMachineInstrFromMaps(DefMI);
2505 DefMI->eraseFromParent();
2513 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2515 mri_ = &fn.getRegInfo();
2516 tm_ = &fn.getTarget();
2517 tri_ = tm_->getRegisterInfo();
2518 tii_ = tm_->getInstrInfo();
2519 li_ = &getAnalysis<LiveIntervals>();
2520 loopInfo = &getAnalysis<MachineLoopInfo>();
2522 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2523 << "********** Function: "
2524 << ((Value*)mf_->getFunction())->getName() << '\n';
2526 allocatableRegs_ = tri_->getAllocatableSet(fn);
2527 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2528 E = tri_->regclass_end(); I != E; ++I)
2529 allocatableRCRegs_.insert(std::make_pair(*I,
2530 tri_->getAllocatableSet(fn, *I)));
2532 // Join (coalesce) intervals if requested.
2533 if (EnableJoining) {
2536 DOUT << "********** INTERVALS POST JOINING **********\n";
2537 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2538 I->second->print(DOUT, tri_);
2544 // Perform a final pass over the instructions and compute spill weights
2545 // and remove identity moves.
2546 SmallVector<unsigned, 4> DeadDefs;
2547 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2548 mbbi != mbbe; ++mbbi) {
2549 MachineBasicBlock* mbb = mbbi;
2550 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2552 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2554 MachineInstr *MI = mii;
2555 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2556 if (JoinedCopies.count(MI)) {
2557 // Delete all coalesced copies.
2558 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2559 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2560 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2561 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
2562 "Unrecognized copy instruction");
2563 DstReg = MI->getOperand(0).getReg();
2565 if (MI->registerDefIsDead(DstReg)) {
2566 LiveInterval &li = li_->getInterval(DstReg);
2567 if (!ShortenDeadCopySrcLiveRange(li, MI))
2568 ShortenDeadCopyLiveRange(li, MI);
2570 li_->RemoveMachineInstrFromMaps(MI);
2571 mii = mbbi->erase(mii);
2576 // Now check if this is a remat'ed def instruction which is now dead.
2577 if (ReMatDefs.count(MI)) {
2579 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2580 const MachineOperand &MO = MI->getOperand(i);
2583 unsigned Reg = MO.getReg();
2586 if (TargetRegisterInfo::isVirtualRegister(Reg))
2587 DeadDefs.push_back(Reg);
2590 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2591 !mri_->use_empty(Reg)) {
2597 while (!DeadDefs.empty()) {
2598 unsigned DeadDef = DeadDefs.back();
2599 DeadDefs.pop_back();
2600 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2602 li_->RemoveMachineInstrFromMaps(mii);
2603 mii = mbbi->erase(mii);
2609 // If the move will be an identity move delete it
2610 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2611 if (isMove && SrcReg == DstReg) {
2612 if (li_->hasInterval(SrcReg)) {
2613 LiveInterval &RegInt = li_->getInterval(SrcReg);
2614 // If def of this move instruction is dead, remove its live range
2615 // from the dstination register's live interval.
2616 if (MI->registerDefIsDead(DstReg)) {
2617 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2618 ShortenDeadCopyLiveRange(RegInt, MI);
2621 li_->RemoveMachineInstrFromMaps(MI);
2622 mii = mbbi->erase(mii);
2624 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2625 SmallSet<unsigned, 4> UniqueUses;
2626 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2627 const MachineOperand &mop = MI->getOperand(i);
2628 if (mop.isReg() && mop.getReg() &&
2629 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2630 unsigned reg = mop.getReg();
2631 // Multiple uses of reg by the same instruction. It should not
2632 // contribute to spill weight again.
2633 if (UniqueUses.count(reg) != 0)
2635 LiveInterval &RegInt = li_->getInterval(reg);
2637 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2638 UniqueUses.insert(reg);
2646 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2647 LiveInterval &LI = *I->second;
2648 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2649 // If the live interval length is essentially zero, i.e. in every live
2650 // range the use follows def immediately, it doesn't make sense to spill
2651 // it and hope it will be easier to allocate for this li.
2652 if (isZeroLengthInterval(&LI))
2653 LI.weight = HUGE_VALF;
2655 bool isLoad = false;
2656 SmallVector<LiveInterval*, 4> SpillIs;
2657 if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
2658 // If all of the definitions of the interval are re-materializable,
2659 // it is a preferred candidate for spilling. If non of the defs are
2660 // loads, then it's potentially very cheap to re-materialize.
2661 // FIXME: this gets much more complicated once we support non-trivial
2662 // re-materialization.
2670 // Slightly prefer live interval that has been assigned a preferred reg.
2674 // Divide the weight of the interval by its size. This encourages
2675 // spilling of intervals that are large and have few uses, and
2676 // discourages spilling of small intervals with many uses.
2677 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2685 /// print - Implement the dump method.
2686 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2690 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2691 return new SimpleRegisterCoalescing();
2694 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2695 DEFINING_FILE_FOR(SimpleRegisterCoalescing)