1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numJoins , "Number of interval joins performed");
40 STATISTIC(numCrossRCs , "Number of cross class joins performed");
41 STATISTIC(numCommutes , "Number of instruction commuting performed");
42 STATISTIC(numExtends , "Number of copies extended");
43 STATISTIC(NumReMats , "Number of instructions re-materialized");
44 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
45 STATISTIC(numAborts , "Number of times interval joining aborted");
46 STATISTIC(numDeadValNo, "Number of valno def marked dead");
48 char SimpleRegisterCoalescing::ID = 0;
50 EnableJoining("join-liveintervals",
51 cl::desc("Coalesce copies (default=true)"),
55 NewHeuristic("new-coalescer-heuristic",
56 cl::desc("Use new coalescer heuristic"),
57 cl::init(false), cl::Hidden);
60 CrossClassJoin("join-cross-class-copies",
61 cl::desc("Coalesce cross register class copies"),
62 cl::init(false), cl::Hidden);
65 PhysJoinTweak("tweak-phys-join-heuristics",
66 cl::desc("Tweak heuristics for joining phys reg with vr"),
67 cl::init(false), cl::Hidden);
69 static RegisterPass<SimpleRegisterCoalescing>
70 X("simple-register-coalescing", "Simple Register Coalescing");
72 // Declare that we implement the RegisterCoalescer interface
73 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
75 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
77 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
78 AU.addRequired<LiveIntervals>();
79 AU.addPreserved<LiveIntervals>();
80 AU.addRequired<MachineLoopInfo>();
81 AU.addPreserved<MachineLoopInfo>();
82 AU.addPreservedID(MachineDominatorsID);
84 AU.addPreservedID(StrongPHIEliminationID);
86 AU.addPreservedID(PHIEliminationID);
87 AU.addPreservedID(TwoAddressInstructionPassID);
88 MachineFunctionPass::getAnalysisUsage(AU);
91 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
92 /// being the source and IntB being the dest, thus this defines a value number
93 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
94 /// see if we can merge these two pieces of B into a single value number,
95 /// eliminating a copy. For example:
99 /// B1 = A3 <- this copy
101 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
102 /// value number to be replaced with B0 (which simplifies the B liveinterval).
104 /// This returns true if an interval was modified.
106 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
108 MachineInstr *CopyMI) {
109 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
111 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
112 // the example above.
113 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
114 assert(BLR != IntB.end() && "Live range not found!");
115 VNInfo *BValNo = BLR->valno;
117 // Get the location that B is defined at. Two options: either this value has
118 // an unknown definition point or it is defined at CopyIdx. If unknown, we
120 if (!BValNo->copy) return false;
121 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
123 // AValNo is the value number in A that defines the copy, A3 in the example.
124 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
125 assert(ALR != IntA.end() && "Live range not found!");
126 VNInfo *AValNo = ALR->valno;
127 // If it's re-defined by an early clobber somewhere in the live range, then
128 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
130 // 172 %ECX<def> = MOV32rr %reg1039<kill>
131 // 180 INLINEASM <es:subl $5,$1
132 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
133 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
134 // 188 %EAX<def> = MOV32rr %EAX<kill>
135 // 196 %ECX<def> = MOV32rr %ECX<kill>
136 // 204 %ECX<def> = MOV32rr %ECX<kill>
137 // 212 %EAX<def> = MOV32rr %EAX<kill>
138 // 220 %EAX<def> = MOV32rr %EAX
139 // 228 %reg1039<def> = MOV32rr %ECX<kill>
140 // The early clobber operand ties ECX input to the ECX def.
142 // The live interval of ECX is represented as this:
143 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
144 // The coalescer has no idea there was a def in the middle of [174,230].
145 if (AValNo->hasRedefByEC())
148 // If AValNo is defined as a copy from IntB, we can potentially process this.
149 // Get the instruction that defines this value number.
150 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
151 if (!SrcReg) return false; // Not defined by a copy.
153 // If the value number is not defined by a copy instruction, ignore it.
155 // If the source register comes from an interval other than IntB, we can't
157 if (SrcReg != IntB.reg) return false;
159 // Get the LiveRange in IntB that this value number starts with.
160 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
161 assert(ValLR != IntB.end() && "Live range not found!");
163 // Make sure that the end of the live range is inside the same block as
165 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
167 ValLREndInst->getParent() != CopyMI->getParent()) return false;
169 // Okay, we now know that ValLR ends in the same block that the CopyMI
170 // live-range starts. If there are no intervening live ranges between them in
171 // IntB, we can merge them.
172 if (ValLR+1 != BLR) return false;
174 // If a live interval is a physical register, conservatively check if any
175 // of its sub-registers is overlapping the live interval of the virtual
176 // register. If so, do not coalesce.
177 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
178 *tri_->getSubRegisters(IntB.reg)) {
179 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
180 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
181 DOUT << "Interfere with sub-register ";
182 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
187 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
189 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
190 // We are about to delete CopyMI, so need to remove it as the 'instruction
191 // that defines this value #'. Update the the valnum with the new defining
193 BValNo->def = FillerStart;
196 // Okay, we can merge them. We need to insert a new liverange:
197 // [ValLR.end, BLR.begin) of either value number, then we merge the
198 // two value numbers.
199 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
201 // If the IntB live range is assigned to a physical register, and if that
202 // physreg has sub-registers, update their live intervals as well.
203 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
204 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
205 LiveInterval &SRLI = li_->getInterval(*SR);
206 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
207 SRLI.getNextValue(FillerStart, 0, true,
208 li_->getVNInfoAllocator())));
212 // Okay, merge "B1" into the same value number as "B0".
213 if (BValNo != ValLR->valno) {
214 IntB.addKills(ValLR->valno, BValNo->kills);
215 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
217 DOUT << " result = "; IntB.print(DOUT, tri_);
220 // If the source instruction was killing the source register before the
221 // merge, unset the isKill marker given the live range has been extended.
222 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
224 ValLREndInst->getOperand(UIdx).setIsKill(false);
225 IntB.removeKill(ValLR->valno, FillerStart);
232 /// HasOtherReachingDefs - Return true if there are definitions of IntB
233 /// other than BValNo val# that can reach uses of AValno val# of IntA.
234 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
238 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
240 if (AI->valno != AValNo) continue;
241 LiveInterval::Ranges::iterator BI =
242 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
243 if (BI != IntB.ranges.begin())
245 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
246 if (BI->valno == BValNo)
248 if (BI->start <= AI->start && BI->end > AI->start)
250 if (BI->start > AI->start && BI->start < AI->end)
257 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
258 /// being the source and IntB being the dest, thus this defines a value number
259 /// in IntB. If the source value number (in IntA) is defined by a commutable
260 /// instruction and its other operand is coalesced to the copy dest register,
261 /// see if we can transform the copy into a noop by commuting the definition. For
264 /// A3 = op A2 B0<kill>
266 /// B1 = A3 <- this copy
268 /// = op A3 <- more uses
272 /// B2 = op B0 A2<kill>
274 /// B1 = B2 <- now an identify copy
276 /// = op B2 <- more uses
278 /// This returns true if an interval was modified.
280 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
282 MachineInstr *CopyMI) {
283 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
285 // FIXME: For now, only eliminate the copy by commuting its def when the
286 // source register is a virtual register. We want to guard against cases
287 // where the copy is a back edge copy and commuting the def lengthen the
288 // live interval of the source register to the entire loop.
289 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
292 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
293 // the example above.
294 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
295 assert(BLR != IntB.end() && "Live range not found!");
296 VNInfo *BValNo = BLR->valno;
298 // Get the location that B is defined at. Two options: either this value has
299 // an unknown definition point or it is defined at CopyIdx. If unknown, we
301 if (!BValNo->copy) return false;
302 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
304 // AValNo is the value number in A that defines the copy, A3 in the example.
305 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
306 assert(ALR != IntA.end() && "Live range not found!");
307 VNInfo *AValNo = ALR->valno;
308 // If other defs can reach uses of this def, then it's not safe to perform
309 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
311 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
312 AValNo->isUnused() || AValNo->hasPHIKill())
314 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
315 const TargetInstrDesc &TID = DefMI->getDesc();
316 if (!TID.isCommutable())
318 // If DefMI is a two-address instruction then commuting it will change the
319 // destination register.
320 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
321 assert(DefIdx != -1);
323 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
325 unsigned Op1, Op2, NewDstIdx;
326 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
330 else if (Op2 == UseOpIdx)
335 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
336 unsigned NewReg = NewDstMO.getReg();
337 if (NewReg != IntB.reg || !NewDstMO.isKill())
340 // Make sure there are no other definitions of IntB that would reach the
341 // uses which the new definition can reach.
342 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
345 // If some of the uses of IntA.reg is already coalesced away, return false.
346 // It's not possible to determine whether it's safe to perform the coalescing.
347 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
348 UE = mri_->use_end(); UI != UE; ++UI) {
349 MachineInstr *UseMI = &*UI;
350 unsigned UseIdx = li_->getInstructionIndex(UseMI);
351 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
352 if (ULR == IntA.end())
354 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
358 // At this point we have decided that it is legal to do this
359 // transformation. Start by commuting the instruction.
360 MachineBasicBlock *MBB = DefMI->getParent();
361 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
364 if (NewMI != DefMI) {
365 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
366 MBB->insert(DefMI, NewMI);
369 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
370 NewMI->getOperand(OpIdx).setIsKill();
372 bool BHasPHIKill = BValNo->hasPHIKill();
373 SmallVector<VNInfo*, 4> BDeadValNos;
374 VNInfo::KillSet BKills;
375 std::map<unsigned, unsigned> BExtend;
377 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
386 // then do not add kills of A to the newly created B interval.
387 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
389 BExtend[ALR->end] = BLR->end;
391 // Update uses of IntA of the specific Val# with IntB.
392 bool BHasSubRegs = false;
393 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
394 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
395 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
396 UE = mri_->use_end(); UI != UE;) {
397 MachineOperand &UseMO = UI.getOperand();
398 MachineInstr *UseMI = &*UI;
400 if (JoinedCopies.count(UseMI))
402 unsigned UseIdx = li_->getInstructionIndex(UseMI);
403 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
404 if (ULR == IntA.end() || ULR->valno != AValNo)
406 UseMO.setReg(NewReg);
409 if (UseMO.isKill()) {
411 UseMO.setIsKill(false);
413 BKills.push_back(VNInfo::KillInfo(false, li_->getUseIndex(UseIdx)+1));
415 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
416 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
418 if (DstReg == IntB.reg) {
419 // This copy will become a noop. If it's defining a new val#,
420 // remove that val# as well. However this live range is being
421 // extended to the end of the existing live range defined by the copy.
422 unsigned DefIdx = li_->getDefIndex(UseIdx);
423 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
424 BHasPHIKill |= DLR->valno->hasPHIKill();
425 assert(DLR->valno->def == DefIdx);
426 BDeadValNos.push_back(DLR->valno);
427 BExtend[DLR->start] = DLR->end;
428 JoinedCopies.insert(UseMI);
429 // If this is a kill but it's going to be removed, the last use
430 // of the same val# is the new kill.
436 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
437 // simply extend BLR if CopyMI doesn't end the range.
438 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
440 // Remove val#'s defined by copies that will be coalesced away.
441 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
442 VNInfo *DeadVNI = BDeadValNos[i];
444 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
445 LiveInterval &SRLI = li_->getInterval(*SR);
446 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
447 SRLI.removeValNo(SRLR->valno);
450 IntB.removeValNo(BDeadValNos[i]);
453 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
454 // is updated. Kills are also updated.
455 VNInfo *ValNo = BValNo;
456 ValNo->def = AValNo->def;
458 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
459 unsigned Kill = ValNo->kills[j].killIdx;
460 if (Kill != BLR->end)
461 BKills.push_back(VNInfo::KillInfo(ValNo->kills[j].isPHIKill, Kill));
463 ValNo->kills.clear();
464 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
466 if (AI->valno != AValNo) continue;
467 unsigned End = AI->end;
468 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
469 if (EI != BExtend.end())
471 IntB.addRange(LiveRange(AI->start, End, ValNo));
473 // If the IntB live range is assigned to a physical register, and if that
474 // physreg has sub-registers, update their live intervals as well.
476 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
477 LiveInterval &SRLI = li_->getInterval(*SR);
478 SRLI.MergeInClobberRange(AI->start, End, li_->getVNInfoAllocator());
482 IntB.addKills(ValNo, BKills);
483 ValNo->setHasPHIKill(BHasPHIKill);
485 DOUT << " result = "; IntB.print(DOUT, tri_);
488 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
489 IntA.removeValNo(AValNo);
490 DOUT << " result = "; IntA.print(DOUT, tri_);
497 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
498 /// fallthoughs to SuccMBB.
499 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
500 MachineBasicBlock *SuccMBB,
501 const TargetInstrInfo *tii_) {
504 MachineBasicBlock *TBB = 0, *FBB = 0;
505 SmallVector<MachineOperand, 4> Cond;
506 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
507 MBB->isSuccessor(SuccMBB);
510 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
511 /// from a physical register live interval as well as from the live intervals
512 /// of its sub-registers.
513 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
514 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
515 li.removeRange(Start, End, true);
516 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
517 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
518 if (!li_->hasInterval(*SR))
520 LiveInterval &sli = li_->getInterval(*SR);
521 unsigned RemoveEnd = Start;
522 while (RemoveEnd != End) {
523 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
526 RemoveEnd = (LR->end < End) ? LR->end : End;
527 sli.removeRange(Start, RemoveEnd, true);
534 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
535 /// as the copy instruction, trim the live interval to the last use and return
538 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
539 MachineBasicBlock *CopyMBB,
541 const LiveRange *LR) {
542 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
544 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
547 MachineInstr *LastUseMI = LastUse->getParent();
548 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
555 // r1025<dead> = r1024<kill>
556 if (MBBStart < LR->end)
557 removeRange(li, MBBStart, LR->end, li_, tri_);
561 // There are uses before the copy, just shorten the live range to the end
563 LastUse->setIsKill();
564 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
565 li.addKill(LR->valno, LastUseIdx+1, false);
566 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
567 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
569 // Last use is itself an identity code.
570 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
571 LastUseMI->getOperand(DeadIdx).setIsDead();
577 if (LR->start <= MBBStart && LR->end > MBBStart) {
578 if (LR->start == 0) {
579 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
580 // Live-in to the function but dead. Remove it from entry live-in set.
581 mf_->begin()->removeLiveIn(li.reg);
583 // FIXME: Shorten intervals in BBs that reaches this BB.
589 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
590 /// computation, replace the copy by rematerialize the definition.
591 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
593 MachineInstr *CopyMI) {
594 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
595 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
596 assert(SrcLR != SrcInt.end() && "Live range not found!");
597 VNInfo *ValNo = SrcLR->valno;
598 // If other defs can reach uses of this def, then it's not safe to perform
599 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
601 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
602 ValNo->isUnused() || ValNo->hasPHIKill())
604 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
605 const TargetInstrDesc &TID = DefMI->getDesc();
606 if (!TID.isAsCheapAsAMove())
608 if (!DefMI->getDesc().isRematerializable() ||
609 !tii_->isTriviallyReMaterializable(DefMI))
611 bool SawStore = false;
612 if (!DefMI->isSafeToMove(tii_, SawStore))
614 if (TID.getNumDefs() != 1)
616 // Make sure the copy destination register class fits the instruction
617 // definition register class. The mismatch can happen as a result of earlier
618 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
619 const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0);
620 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
621 if (mri_->getRegClass(DstReg) != RC)
623 } else if (!RC->contains(DstReg))
626 unsigned DefIdx = li_->getDefIndex(CopyIdx);
627 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
628 DLR->valno->copy = NULL;
629 // Don't forget to update sub-register intervals.
630 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
631 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
632 if (!li_->hasInterval(*SR))
634 DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
635 if (DLR && DLR->valno->copy == CopyMI)
636 DLR->valno->copy = NULL;
640 // If copy kills the source register, find the last use and propagate
642 bool checkForDeadDef = false;
643 MachineBasicBlock *MBB = CopyMI->getParent();
644 if (CopyMI->killsRegister(SrcInt.reg))
645 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
646 checkForDeadDef = true;
649 MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
650 tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
651 MachineInstr *NewMI = prior(MII);
653 if (checkForDeadDef) {
654 // PR4090 fix: Trim interval failed because there was no use of the
655 // source interval in this MBB. If the def is in this MBB too then we
656 // should mark it dead:
657 if (DefMI->getParent() == MBB) {
658 DefMI->addRegisterDead(SrcInt.reg, tri_);
659 SrcLR->end = SrcLR->start + 1;
663 // CopyMI may have implicit operands, transfer them over to the newly
664 // rematerialized instruction. And update implicit def interval valnos.
665 for (unsigned i = CopyMI->getDesc().getNumOperands(),
666 e = CopyMI->getNumOperands(); i != e; ++i) {
667 MachineOperand &MO = CopyMI->getOperand(i);
668 if (MO.isReg() && MO.isImplicit())
669 NewMI->addOperand(MO);
670 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
671 unsigned Reg = MO.getReg();
672 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
673 if (DLR && DLR->valno->copy == CopyMI)
674 DLR->valno->copy = NULL;
678 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
679 CopyMI->eraseFromParent();
680 ReMatCopies.insert(CopyMI);
681 ReMatDefs.insert(DefMI);
686 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
688 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
689 unsigned DstReg) const {
690 MachineBasicBlock *MBB = CopyMI->getParent();
691 const MachineLoop *L = loopInfo->getLoopFor(MBB);
694 if (MBB != L->getLoopLatch())
697 LiveInterval &LI = li_->getInterval(DstReg);
698 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
699 LiveInterval::const_iterator DstLR =
700 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
701 if (DstLR == LI.end())
703 if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0].isPHIKill)
708 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
709 /// update the subregister number if it is not zero. If DstReg is a
710 /// physical register and the existing subregister number of the def / use
711 /// being updated is not zero, make sure to set it to the correct physical
714 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
716 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
717 if (DstIsPhys && SubIdx) {
718 // Figure out the real physical register we are updating with.
719 DstReg = tri_->getSubReg(DstReg, SubIdx);
723 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
724 E = mri_->reg_end(); I != E; ) {
725 MachineOperand &O = I.getOperand();
726 MachineInstr *UseMI = &*I;
728 unsigned OldSubIdx = O.getSubReg();
730 unsigned UseDstReg = DstReg;
732 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
734 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
735 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
736 CopySrcSubIdx, CopyDstSubIdx) &&
737 CopySrcReg != CopyDstReg &&
738 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
739 // If the use is a copy and it won't be coalesced away, and its source
740 // is defined by a trivial computation, try to rematerialize it instead.
741 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
750 // Sub-register indexes goes from small to large. e.g.
751 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
752 // EAX: 1 -> AL, 2 -> AX
753 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
754 // sub-register 2 is also AX.
755 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
756 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
759 // Remove would-be duplicated kill marker.
760 if (O.isKill() && UseMI->killsRegister(DstReg))
764 // After updating the operand, check if the machine instruction has
765 // become a copy. If so, update its val# information.
766 if (JoinedCopies.count(UseMI))
769 const TargetInstrDesc &TID = UseMI->getDesc();
770 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
771 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
772 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
773 CopySrcSubIdx, CopyDstSubIdx) &&
774 CopySrcReg != CopyDstReg &&
775 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
776 allocatableRegs_[CopyDstReg])) {
777 LiveInterval &LI = li_->getInterval(CopyDstReg);
778 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
779 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
780 if (DLR->valno->def == DefIdx)
781 DLR->valno->copy = UseMI;
787 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
788 /// registers due to insert_subreg coalescing. e.g.
790 /// r1025 = implicit_def
791 /// r1025 = insert_subreg r1025, r1024
795 /// r1025 = implicit_def
796 /// r1025 = insert_subreg r1025, r1025
799 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
800 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
801 E = mri_->reg_end(); I != E; ) {
802 MachineOperand &O = I.getOperand();
803 MachineInstr *DefMI = &*I;
807 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
809 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
811 li_->RemoveMachineInstrFromMaps(DefMI);
812 DefMI->eraseFromParent();
816 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
817 /// due to live range lengthening as the result of coalescing.
818 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
820 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
821 UE = mri_->use_end(); UI != UE; ++UI) {
822 MachineOperand &UseMO = UI.getOperand();
823 if (UseMO.isKill()) {
824 MachineInstr *UseMI = UseMO.getParent();
825 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
826 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
827 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
828 UseMO.setIsKill(false);
833 /// removeIntervalIfEmpty - Check if the live interval of a physical register
834 /// is empty, if so remove it and also remove the empty intervals of its
835 /// sub-registers. Return true if live interval is removed.
836 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
837 const TargetRegisterInfo *tri_) {
839 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
840 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
841 if (!li_->hasInterval(*SR))
843 LiveInterval &sli = li_->getInterval(*SR);
845 li_->removeInterval(*SR);
847 li_->removeInterval(li.reg);
853 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
854 /// Return true if live interval is removed.
855 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
856 MachineInstr *CopyMI) {
857 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
858 LiveInterval::iterator MLR =
859 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
861 return false; // Already removed by ShortenDeadCopySrcLiveRange.
862 unsigned RemoveStart = MLR->start;
863 unsigned RemoveEnd = MLR->end;
864 unsigned DefIdx = li_->getDefIndex(CopyIdx);
865 // Remove the liverange that's defined by this.
866 if (RemoveStart == DefIdx && RemoveEnd == DefIdx+1) {
867 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
868 return removeIntervalIfEmpty(li, li_, tri_);
873 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
874 /// the val# it defines. If the live interval becomes empty, remove it as well.
875 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
876 MachineInstr *DefMI) {
877 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
878 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
879 if (DefIdx != MLR->valno->def)
881 li.removeValNo(MLR->valno);
882 return removeIntervalIfEmpty(li, li_, tri_);
885 /// PropagateDeadness - Propagate the dead marker to the instruction which
886 /// defines the val#.
887 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
888 unsigned &LRStart, LiveIntervals *li_,
889 const TargetRegisterInfo* tri_) {
890 MachineInstr *DefMI =
891 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
892 if (DefMI && DefMI != CopyMI) {
893 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
895 DefMI->getOperand(DeadIdx).setIsDead();
896 // A dead def should have a single cycle interval.
902 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
903 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
904 /// ends the live range there. If there isn't another use, then this live range
905 /// is dead. Return true if live interval is removed.
907 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
908 MachineInstr *CopyMI) {
909 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
911 // FIXME: special case: function live in. It can be a general case if the
912 // first instruction index starts at > 0 value.
913 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
914 // Live-in to the function but dead. Remove it from entry live-in set.
915 if (mf_->begin()->isLiveIn(li.reg))
916 mf_->begin()->removeLiveIn(li.reg);
917 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
918 removeRange(li, LR->start, LR->end, li_, tri_);
919 return removeIntervalIfEmpty(li, li_, tri_);
922 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
924 // Livein but defined by a phi.
927 unsigned RemoveStart = LR->start;
928 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
929 if (LR->end > RemoveEnd)
930 // More uses past this copy? Nothing to do.
933 // If there is a last use in the same bb, we can't remove the live range.
934 // Shorten the live interval and return.
935 MachineBasicBlock *CopyMBB = CopyMI->getParent();
936 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
939 // There are other kills of the val#. Nothing to do.
940 if (!li.isOnlyLROfValNo(LR))
943 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
944 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
945 // If the live range starts in another mbb and the copy mbb is not a fall
946 // through mbb, then we can only cut the range from the beginning of the
948 RemoveStart = li_->getMBBStartIdx(CopyMBB) + 1;
950 if (LR->valno->def == RemoveStart) {
951 // If the def MI defines the val# and this copy is the only kill of the
952 // val#, then propagate the dead marker.
953 if (li.isOnlyLROfValNo(LR)) {
954 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
957 if (li.isKill(LR->valno, RemoveEnd))
958 li.removeKill(LR->valno, RemoveEnd);
961 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
962 return removeIntervalIfEmpty(li, li_, tri_);
965 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
966 /// from an implicit def to another register can be coalesced away.
967 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
969 LiveInterval &ImpLi) const{
970 if (!CopyMI->killsRegister(ImpLi.reg))
972 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
973 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
976 if (LR->valno->hasPHIKill())
978 if (LR->valno->def != CopyIdx)
980 // Make sure all of val# uses are copies.
981 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
982 UE = mri_->use_end(); UI != UE;) {
983 MachineInstr *UseMI = &*UI;
985 if (JoinedCopies.count(UseMI))
987 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
988 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
989 if (ULR == li.end() || ULR->valno != LR->valno)
991 // If the use is not a use, then it's not safe to coalesce the move.
992 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
993 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
994 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
995 UseMI->getOperand(1).getReg() == li.reg)
1004 /// TurnCopiesFromValNoToImpDefs - The specified value# is defined by an
1005 /// implicit_def and it is being removed. Turn all copies from this value#
1006 /// into implicit_defs.
1007 void SimpleRegisterCoalescing::TurnCopiesFromValNoToImpDefs(LiveInterval &li,
1009 SmallVector<MachineInstr*, 4> ImpDefs;
1010 MachineOperand *LastUse = NULL;
1011 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
1012 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
1013 RE = mri_->reg_end(); RI != RE;) {
1014 MachineOperand *MO = &RI.getOperand();
1015 MachineInstr *MI = &*RI;
1018 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
1019 ImpDefs.push_back(MI);
1022 if (JoinedCopies.count(MI))
1024 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
1025 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
1026 if (ULR == li.end() || ULR->valno != VNI)
1028 // If the use is a copy, turn it into an identity copy.
1029 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1030 if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1032 // Change it to an implicit_def.
1033 MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
1034 for (int i = MI->getNumOperands() - 1, e = 0; i > e; --i)
1035 MI->RemoveOperand(i);
1036 // It's no longer a copy, update the valno it defines.
1037 unsigned DefIdx = li_->getDefIndex(UseIdx);
1038 LiveInterval &DstInt = li_->getInterval(DstReg);
1039 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(DefIdx);
1040 assert(DLR != DstInt.end() && "Live range not found!");
1041 assert(DLR->valno->copy == MI);
1042 DLR->valno->copy = NULL;
1043 ReMatCopies.insert(MI);
1044 } else if (UseIdx > LastUseIdx) {
1045 LastUseIdx = UseIdx;
1050 LastUse->setIsKill();
1051 li.addKill(VNI, LastUseIdx+1, false);
1053 // Remove dead implicit_def's.
1054 while (!ImpDefs.empty()) {
1055 MachineInstr *ImpDef = ImpDefs.back();
1057 li_->RemoveMachineInstrFromMaps(ImpDef);
1058 ImpDef->eraseFromParent();
1063 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
1064 /// a virtual destination register with physical source register.
1066 SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
1067 MachineBasicBlock *CopyMBB,
1068 LiveInterval &DstInt,
1069 LiveInterval &SrcInt) {
1070 // If the virtual register live interval is long but it has low use desity,
1071 // do not join them, instead mark the physical register as its allocation
1073 const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg);
1074 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1075 unsigned Length = li_->getApproximateInstructionCount(DstInt);
1076 if (Length > Threshold &&
1077 (((float)std::distance(mri_->use_begin(DstInt.reg),
1078 mri_->use_end()) / Length) < (1.0 / Threshold)))
1081 // If the virtual register live interval extends into a loop, turn down
1083 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1084 const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
1086 // Let's see if the virtual register live interval extends into the loop.
1087 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
1088 assert(DLR != DstInt.end() && "Live range not found!");
1089 DLR = DstInt.FindLiveRangeContaining(DLR->end+1);
1090 if (DLR != DstInt.end()) {
1091 CopyMBB = li_->getMBBFromIndex(DLR->start);
1092 L = loopInfo->getLoopFor(CopyMBB);
1096 if (!L || Length <= Threshold)
1099 unsigned UseIdx = li_->getUseIndex(CopyIdx);
1100 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1101 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1102 if (loopInfo->getLoopFor(SMBB) != L) {
1103 if (!loopInfo->isLoopHeader(CopyMBB))
1105 // If vr's live interval extends pass the loop header, do not join.
1106 for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(),
1107 SE = CopyMBB->succ_end(); SI != SE; ++SI) {
1108 MachineBasicBlock *SuccMBB = *SI;
1109 if (SuccMBB == CopyMBB)
1111 if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
1112 li_->getMBBEndIdx(SuccMBB)+1))
1119 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
1120 /// copy from a virtual source register to a physical destination register.
1122 SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
1123 MachineBasicBlock *CopyMBB,
1124 LiveInterval &DstInt,
1125 LiveInterval &SrcInt) {
1126 // If the virtual register live interval is long but it has low use desity,
1127 // do not join them, instead mark the physical register as its allocation
1129 const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
1130 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1131 unsigned Length = li_->getApproximateInstructionCount(SrcInt);
1132 if (Length > Threshold &&
1133 (((float)std::distance(mri_->use_begin(SrcInt.reg),
1134 mri_->use_end()) / Length) < (1.0 / Threshold)))
1138 // Must be implicit_def.
1141 // If the virtual register live interval is defined or cross a loop, turn
1142 // down aggressiveness.
1143 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1144 unsigned UseIdx = li_->getUseIndex(CopyIdx);
1145 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1146 assert(SLR != SrcInt.end() && "Live range not found!");
1147 SLR = SrcInt.FindLiveRangeContaining(SLR->start-1);
1148 if (SLR == SrcInt.end())
1150 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1151 const MachineLoop *L = loopInfo->getLoopFor(SMBB);
1153 if (!L || Length <= Threshold)
1156 if (loopInfo->getLoopFor(CopyMBB) != L) {
1157 if (SMBB != L->getLoopLatch())
1159 // If vr's live interval is extended from before the loop latch, do not
1161 for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(),
1162 PE = SMBB->pred_end(); PI != PE; ++PI) {
1163 MachineBasicBlock *PredMBB = *PI;
1164 if (PredMBB == SMBB)
1166 if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
1167 li_->getMBBEndIdx(PredMBB)+1))
1174 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1175 /// two virtual registers from different register classes.
1177 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned LargeReg,
1179 unsigned Threshold) {
1180 // Then make sure the intervals are *short*.
1181 LiveInterval &LargeInt = li_->getInterval(LargeReg);
1182 LiveInterval &SmallInt = li_->getInterval(SmallReg);
1183 unsigned LargeSize = li_->getApproximateInstructionCount(LargeInt);
1184 unsigned SmallSize = li_->getApproximateInstructionCount(SmallInt);
1185 if (SmallSize > Threshold || LargeSize > Threshold)
1186 if ((float)std::distance(mri_->use_begin(SmallReg),
1187 mri_->use_end()) / SmallSize <
1188 (float)std::distance(mri_->use_begin(LargeReg),
1189 mri_->use_end()) / LargeSize)
1194 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1195 /// register with a physical register, check if any of the virtual register
1196 /// operand is a sub-register use or def. If so, make sure it won't result
1197 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1198 /// vr1024 = extract_subreg vr1025, 1
1200 /// vr1024 = mov8rr AH
1201 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1202 /// AH does not have a super-reg whose sub-register 1 is AH.
1204 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1207 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1208 E = mri_->reg_end(); I != E; ++I) {
1209 MachineOperand &O = I.getOperand();
1210 MachineInstr *MI = &*I;
1211 if (MI == CopyMI || JoinedCopies.count(MI))
1213 unsigned SubIdx = O.getSubReg();
1214 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1216 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1217 SubIdx = MI->getOperand(2).getImm();
1218 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1221 unsigned SrcReg = MI->getOperand(1).getReg();
1222 const TargetRegisterClass *RC =
1223 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1224 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1225 : mri_->getRegClass(SrcReg);
1226 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1230 if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
1231 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
1232 SubIdx = MI->getOperand(3).getImm();
1233 if (VirtReg == MI->getOperand(0).getReg()) {
1234 if (!tri_->getSubReg(PhysReg, SubIdx))
1237 unsigned DstReg = MI->getOperand(0).getReg();
1238 const TargetRegisterClass *RC =
1239 TargetRegisterInfo::isPhysicalRegister(DstReg)
1240 ? tri_->getPhysicalRegisterRegClass(DstReg)
1241 : mri_->getRegClass(DstReg);
1242 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1251 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1252 /// an extract_subreg where dst is a physical register, e.g.
1253 /// cl = EXTRACT_SUBREG reg1024, 1
1255 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1256 unsigned SrcReg, unsigned SubIdx,
1257 unsigned &RealDstReg) {
1258 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1259 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1260 assert(RealDstReg && "Invalid extract_subreg instruction!");
1262 // For this type of EXTRACT_SUBREG, conservatively
1263 // check if the live interval of the source register interfere with the
1264 // actual super physical register we are trying to coalesce with.
1265 LiveInterval &RHS = li_->getInterval(SrcReg);
1266 if (li_->hasInterval(RealDstReg) &&
1267 RHS.overlaps(li_->getInterval(RealDstReg))) {
1268 DOUT << "Interfere with register ";
1269 DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
1270 return false; // Not coalescable
1272 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1273 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1274 DOUT << "Interfere with sub-register ";
1275 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1276 return false; // Not coalescable
1281 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1282 /// an insert_subreg where src is a physical register, e.g.
1283 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1285 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1286 unsigned SrcReg, unsigned SubIdx,
1287 unsigned &RealSrcReg) {
1288 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1289 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1290 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1292 LiveInterval &RHS = li_->getInterval(DstReg);
1293 if (li_->hasInterval(RealSrcReg) &&
1294 RHS.overlaps(li_->getInterval(RealSrcReg))) {
1295 DOUT << "Interfere with register ";
1296 DEBUG(li_->getInterval(RealSrcReg).print(DOUT, tri_));
1297 return false; // Not coalescable
1299 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1300 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1301 DOUT << "Interfere with sub-register ";
1302 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1303 return false; // Not coalescable
1308 /// getRegAllocPreference - Return register allocation preference register.
1310 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1311 MachineRegisterInfo *MRI,
1312 const TargetRegisterInfo *TRI) {
1313 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1315 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
1316 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1319 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1320 /// which are the src/dst of the copy instruction CopyMI. This returns true
1321 /// if the copy was successfully coalesced away. If it is not currently
1322 /// possible to coalesce this interval, but it may be possible if other
1323 /// things get coalesced, then it returns true by reference in 'Again'.
1324 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1325 MachineInstr *CopyMI = TheCopy.MI;
1328 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1329 return false; // Already done.
1331 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
1333 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1334 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
1335 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
1336 bool isSubRegToReg = CopyMI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG;
1337 unsigned SubIdx = 0;
1339 DstReg = CopyMI->getOperand(0).getReg();
1340 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1341 SrcReg = CopyMI->getOperand(1).getReg();
1342 SrcSubIdx = CopyMI->getOperand(2).getImm();
1343 } else if (isInsSubReg || isSubRegToReg) {
1344 if (CopyMI->getOperand(2).getSubReg()) {
1345 DOUT << "\tSource of insert_subreg is already coalesced "
1346 << "to another register.\n";
1347 return false; // Not coalescable.
1349 DstReg = CopyMI->getOperand(0).getReg();
1350 DstSubIdx = CopyMI->getOperand(3).getImm();
1351 SrcReg = CopyMI->getOperand(2).getReg();
1352 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
1353 llvm_unreachable("Unrecognized copy instruction!");
1356 // If they are already joined we continue.
1357 if (SrcReg == DstReg) {
1358 DOUT << "\tCopy already coalesced.\n";
1359 return false; // Not coalescable.
1362 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1363 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1365 // If they are both physical registers, we cannot join them.
1366 if (SrcIsPhys && DstIsPhys) {
1367 DOUT << "\tCan not coalesce physregs.\n";
1368 return false; // Not coalescable.
1371 // We only join virtual registers with allocatable physical registers.
1372 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1373 DOUT << "\tSrc reg is unallocatable physreg.\n";
1374 return false; // Not coalescable.
1376 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1377 DOUT << "\tDst reg is unallocatable physreg.\n";
1378 return false; // Not coalescable.
1381 // Check that a physical source register is compatible with dst regclass
1383 unsigned SrcSubReg = SrcSubIdx ?
1384 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1385 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1386 const TargetRegisterClass *DstSubRC = DstRC;
1388 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1389 assert(DstSubRC && "Illegal subregister index");
1390 if (!DstSubRC->contains(SrcSubReg)) {
1391 DOUT << "\tIncompatible destination regclass: "
1392 << tri_->getName(SrcSubReg) << " not in " << DstSubRC->getName()
1394 return false; // Not coalescable.
1398 // Check that a physical dst register is compatible with source regclass
1400 unsigned DstSubReg = DstSubIdx ?
1401 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1402 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1403 const TargetRegisterClass *SrcSubRC = SrcRC;
1405 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1406 assert(SrcSubRC && "Illegal subregister index");
1407 if (!SrcSubRC->contains(DstReg)) {
1408 DOUT << "\tIncompatible source regclass: "
1409 << tri_->getName(DstSubReg) << " not in " << SrcSubRC->getName()
1411 return false; // Not coalescable.
1415 // Should be non-null only when coalescing to a sub-register class.
1416 bool CrossRC = false;
1417 const TargetRegisterClass *NewRC = NULL;
1418 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1419 unsigned RealDstReg = 0;
1420 unsigned RealSrcReg = 0;
1421 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1422 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1423 if (SrcIsPhys && isExtSubReg) {
1424 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1425 // coalesced with AX.
1426 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1428 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1429 // coalesced to a larger register so the subreg indices cancel out.
1430 if (DstSubIdx != SubIdx) {
1431 DOUT << "\t Sub-register indices mismatch.\n";
1432 return false; // Not coalescable.
1435 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1437 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1438 // EAX = INSERT_SUBREG EAX, r1024, 0
1439 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1441 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1442 // coalesced to a larger register so the subreg indices cancel out.
1443 if (SrcSubIdx != SubIdx) {
1444 DOUT << "\t Sub-register indices mismatch.\n";
1445 return false; // Not coalescable.
1448 DstReg = tri_->getSubReg(DstReg, SubIdx);
1450 } else if ((DstIsPhys && isExtSubReg) ||
1451 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1452 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1453 DOUT << "\tSrc of extract_subreg already coalesced with reg"
1454 << " of a super-class.\n";
1455 return false; // Not coalescable.
1459 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1460 return false; // Not coalescable
1462 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1463 return false; // Not coalescable
1467 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1468 : CopyMI->getOperand(2).getSubReg();
1470 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1471 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1472 // coalesced to a larger register so the subreg indices cancel out.
1473 // Also check if the other larger register is of the same register
1474 // class as the would be resulting register.
1477 DOUT << "\t Sub-register indices mismatch.\n";
1478 return false; // Not coalescable.
1482 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1483 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1484 unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
1485 if (!isWinToJoinCrossClass(LargeReg, SmallReg, Limit)) {
1486 Again = true; // May be possible to coalesce later.
1491 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1492 if (!CrossClassJoin)
1496 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1497 // with another? If it's the resulting destination register, then
1498 // the subidx must be propagated to uses (but only those defined
1499 // by the EXTRACT_SUBREG). If it's being coalesced into another
1500 // register, it should be safe because register is assumed to have
1501 // the register class of the super-register.
1503 // Process moves where one of the registers have a sub-register index.
1504 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1505 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1506 SubIdx = DstMO->getSubReg();
1508 if (SrcMO->getSubReg())
1509 // FIXME: can we handle this?
1511 // This is not an insert_subreg but it looks like one.
1512 // e.g. %reg1024:4 = MOV32rr %EAX
1515 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1516 return false; // Not coalescable
1520 SubIdx = SrcMO->getSubReg();
1522 // This is not a extract_subreg but it looks like one.
1523 // e.g. %cl = MOV16rr %reg1024:1
1526 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1527 return false; // Not coalescable
1533 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1534 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1535 unsigned LargeReg = SrcReg;
1536 unsigned SmallReg = DstReg;
1539 // Now determine the register class of the joined register.
1541 if (SubIdx && DstRC && DstRC->isASubClass()) {
1542 // This is a move to a sub-register class. However, the source is a
1543 // sub-register of a larger register class. We don't know what should
1544 // the register class be. FIXME.
1548 Limit = allocatableRCRegs_[DstRC].count();
1549 } else if (!SrcIsPhys && !DstIsPhys) {
1550 NewRC = getCommonSubClass(SrcRC, DstRC);
1552 DOUT << "\tDisjoint regclasses: "
1553 << SrcRC->getName() << ", "
1554 << DstRC->getName() << ".\n";
1555 return false; // Not coalescable.
1557 if (DstRC->getSize() > SrcRC->getSize())
1558 std::swap(LargeReg, SmallReg);
1561 // If we are joining two virtual registers and the resulting register
1562 // class is more restrictive (fewer register, smaller size). Check if it's
1563 // worth doing the merge.
1564 if (!SrcIsPhys && !DstIsPhys &&
1565 (isExtSubReg || DstRC->isASubClass()) &&
1566 !isWinToJoinCrossClass(LargeReg, SmallReg,
1567 allocatableRCRegs_[NewRC].count())) {
1568 DOUT << "\tSrc/Dest are different register classes.\n";
1569 // Allow the coalescer to try again in case either side gets coalesced to
1570 // a physical register that's compatible with the other side. e.g.
1571 // r1024 = MOV32to32_ r1025
1572 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1573 Again = true; // May be possible to coalesce later.
1578 // Will it create illegal extract_subreg / insert_subreg?
1579 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1581 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1584 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1585 LiveInterval &DstInt = li_->getInterval(DstReg);
1586 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1587 "Register mapping is horribly broken!");
1589 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1590 DOUT << " and "; DstInt.print(DOUT, tri_);
1593 // Save a copy of the virtual register live interval. We'll manually
1594 // merge this into the "real" physical register live interval this is
1596 LiveInterval *SavedLI = 0;
1598 SavedLI = li_->dupInterval(&SrcInt);
1599 else if (RealSrcReg)
1600 SavedLI = li_->dupInterval(&DstInt);
1602 // Check if it is necessary to propagate "isDead" property.
1603 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1604 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1605 bool isDead = mopd->isDead();
1607 // We need to be careful about coalescing a source physical register with a
1608 // virtual register. Once the coalescing is done, it cannot be broken and
1609 // these are not spillable! If the destination interval uses are far away,
1610 // think twice about coalescing them!
1611 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1612 // If the copy is in a loop, take care not to coalesce aggressively if the
1613 // src is coming in from outside the loop (or the dst is out of the loop).
1614 // If it's not in a loop, then determine whether to join them base purely
1615 // by the length of the interval.
1616 if (PhysJoinTweak) {
1618 if (!isWinToJoinVRWithSrcPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
1619 mri_->setRegAllocationHint(DstInt.reg, 0, SrcReg);
1621 DOUT << "\tMay tie down a physical register, abort!\n";
1622 Again = true; // May be possible to coalesce later.
1626 if (!isWinToJoinVRWithDstPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
1627 mri_->setRegAllocationHint(SrcInt.reg, 0, DstReg);
1629 DOUT << "\tMay tie down a physical register, abort!\n";
1630 Again = true; // May be possible to coalesce later.
1635 // If the virtual register live interval is long but it has low use desity,
1636 // do not join them, instead mark the physical register as its allocation
1638 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1639 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1640 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1641 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1642 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1643 if (TheCopy.isBackEdge)
1644 Threshold *= 2; // Favors back edge copies.
1646 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1647 float Ratio = 1.0 / Threshold;
1648 if (Length > Threshold &&
1649 (((float)std::distance(mri_->use_begin(JoinVReg),
1650 mri_->use_end()) / Length) < Ratio)) {
1651 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1653 DOUT << "\tMay tie down a physical register, abort!\n";
1654 Again = true; // May be possible to coalesce later.
1661 // Okay, attempt to join these two intervals. On failure, this returns false.
1662 // Otherwise, if one of the intervals being joined is a physreg, this method
1663 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1664 // been modified, so we can use this information below to update aliases.
1665 bool Swapped = false;
1666 // If SrcInt is implicitly defined, it's safe to coalesce.
1667 bool isEmpty = SrcInt.empty();
1668 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1669 // Only coalesce an empty interval (defined by implicit_def) with
1670 // another interval which has a valno defined by the CopyMI and the CopyMI
1671 // is a kill of the implicit def.
1672 DOUT << "Not profitable!\n";
1676 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1677 // Coalescing failed.
1679 // If definition of source is defined by trivial computation, try
1680 // rematerializing it.
1681 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1682 ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
1685 // If we can eliminate the copy without merging the live ranges, do so now.
1686 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1687 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1688 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1689 JoinedCopies.insert(CopyMI);
1693 // Otherwise, we are unable to join the intervals.
1694 DOUT << "Interference!\n";
1695 Again = true; // May be possible to coalesce later.
1699 LiveInterval *ResSrcInt = &SrcInt;
1700 LiveInterval *ResDstInt = &DstInt;
1702 std::swap(SrcReg, DstReg);
1703 std::swap(ResSrcInt, ResDstInt);
1705 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1706 "LiveInterval::join didn't work right!");
1708 // If we're about to merge live ranges into a physical register live interval,
1709 // we have to update any aliased register's live ranges to indicate that they
1710 // have clobbered values for this range.
1711 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1712 // If this is a extract_subreg where dst is a physical register, e.g.
1713 // cl = EXTRACT_SUBREG reg1024, 1
1714 // then create and update the actual physical register allocated to RHS.
1715 if (RealDstReg || RealSrcReg) {
1716 LiveInterval &RealInt =
1717 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1718 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1719 E = SavedLI->vni_end(); I != E; ++I) {
1720 const VNInfo *ValNo = *I;
1721 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->copy,
1722 false, // updated at *
1723 li_->getVNInfoAllocator());
1724 NewValNo->setFlags(ValNo->getFlags()); // * updated here.
1725 RealInt.addKills(NewValNo, ValNo->kills);
1726 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1728 RealInt.weight += SavedLI->weight;
1729 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1732 // Update the liveintervals of sub-registers.
1733 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1734 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1735 li_->getVNInfoAllocator());
1738 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1739 // larger super-register.
1740 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1741 !SrcIsPhys && !DstIsPhys) {
1742 if ((isExtSubReg && !Swapped) ||
1743 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1744 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1745 std::swap(SrcReg, DstReg);
1746 std::swap(ResSrcInt, ResDstInt);
1750 // Coalescing to a virtual register that is of a sub-register class of the
1751 // other. Make sure the resulting register is set to the right register class.
1755 mri_->setRegClass(DstReg, NewRC);
1759 // Add all copies that define val# in the source interval into the queue.
1760 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1761 e = ResSrcInt->vni_end(); i != e; ++i) {
1762 const VNInfo *vni = *i;
1763 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1764 if (!vni->def || vni->isUnused() || vni->isPHIDef() || !vni->isDefAccurate())
1766 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1767 unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx;
1769 JoinedCopies.count(CopyMI) == 0 &&
1770 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg,
1771 NewSrcSubIdx, NewDstSubIdx)) {
1772 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1773 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1774 isBackEdgeCopy(CopyMI, DstReg)));
1779 // Remember to delete the copy instruction.
1780 JoinedCopies.insert(CopyMI);
1782 // Some live range has been lengthened due to colaescing, eliminate the
1783 // unnecessary kills.
1784 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1785 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1786 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1791 // r1024 = implicit_def
1794 RemoveDeadImpDef(DstReg, *ResDstInt);
1795 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1797 // SrcReg is guarateed to be the register whose live interval that is
1799 li_->removeInterval(SrcReg);
1801 // Update regalloc hint.
1802 tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
1804 // Manually deleted the live interval copy.
1811 // Now the copy is being coalesced away, the val# previously defined
1812 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1813 // length interval. Remove the val#.
1814 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1815 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1816 VNInfo *ImpVal = LR->valno;
1817 assert(ImpVal->def == CopyIdx);
1818 unsigned NextDef = LR->end;
1819 TurnCopiesFromValNoToImpDefs(*ResDstInt, ImpVal);
1820 ResDstInt->removeValNo(ImpVal);
1821 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1822 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1823 // Special case: vr1024 = implicit_def
1824 // vr1024 = insert_subreg vr1024, vr1025, c
1825 // The insert_subreg becomes a "copy" that defines a val# which can itself
1826 // be coalesced away.
1827 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1828 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1829 LR->valno->copy = DefMI;
1833 // If resulting interval has a preference that no longer fits because of subreg
1834 // coalescing, just clear the preference.
1835 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1836 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1837 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1838 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1839 if (!RC->contains(Preference))
1840 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1843 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1850 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1851 /// compute what the resultant value numbers for each value in the input two
1852 /// ranges will be. This is complicated by copies between the two which can
1853 /// and will commonly cause multiple value numbers to be merged into one.
1855 /// VN is the value number that we're trying to resolve. InstDefiningValue
1856 /// keeps track of the new InstDefiningValue assignment for the result
1857 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1858 /// whether a value in this or other is a copy from the opposite set.
1859 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1860 /// already been assigned.
1862 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1863 /// contains the value number the copy is from.
1865 static unsigned ComputeUltimateVN(VNInfo *VNI,
1866 SmallVector<VNInfo*, 16> &NewVNInfo,
1867 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1868 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1869 SmallVector<int, 16> &ThisValNoAssignments,
1870 SmallVector<int, 16> &OtherValNoAssignments) {
1871 unsigned VN = VNI->id;
1873 // If the VN has already been computed, just return it.
1874 if (ThisValNoAssignments[VN] >= 0)
1875 return ThisValNoAssignments[VN];
1876 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1878 // If this val is not a copy from the other val, then it must be a new value
1879 // number in the destination.
1880 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1881 if (I == ThisFromOther.end()) {
1882 NewVNInfo.push_back(VNI);
1883 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1885 VNInfo *OtherValNo = I->second;
1887 // Otherwise, this *is* a copy from the RHS. If the other side has already
1888 // been computed, return it.
1889 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1890 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1892 // Mark this value number as currently being computed, then ask what the
1893 // ultimate value # of the other value is.
1894 ThisValNoAssignments[VN] = -2;
1895 unsigned UltimateVN =
1896 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1897 OtherValNoAssignments, ThisValNoAssignments);
1898 return ThisValNoAssignments[VN] = UltimateVN;
1901 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1902 return std::find(V.begin(), V.end(), Val) != V.end();
1905 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1906 /// the specified live interval is defined by a copy from the specified
1908 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1911 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1914 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1915 if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) &&
1916 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1917 *tri_->getSuperRegisters(li.reg)) {
1918 // It's a sub-register live interval, we may not have precise information.
1920 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1921 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1923 tii_->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1924 DstReg == li.reg && SrcReg == Reg) {
1925 // Cache computed info.
1926 LR->valno->def = LR->start;
1927 LR->valno->copy = DefMI;
1934 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1935 /// caller of this method must guarantee that the RHS only contains a single
1936 /// value number and that the RHS is not defined by a copy from this
1937 /// interval. This returns false if the intervals are not joinable, or it
1938 /// joins them and returns true.
1939 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1940 assert(RHS.containsOneValue());
1942 // Some number (potentially more than one) value numbers in the current
1943 // interval may be defined as copies from the RHS. Scan the overlapping
1944 // portions of the LHS and RHS, keeping track of this and looking for
1945 // overlapping live ranges that are NOT defined as copies. If these exist, we
1948 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1949 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1951 if (LHSIt->start < RHSIt->start) {
1952 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1953 if (LHSIt != LHS.begin()) --LHSIt;
1954 } else if (RHSIt->start < LHSIt->start) {
1955 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1956 if (RHSIt != RHS.begin()) --RHSIt;
1959 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1962 // Determine if these live intervals overlap.
1963 bool Overlaps = false;
1964 if (LHSIt->start <= RHSIt->start)
1965 Overlaps = LHSIt->end > RHSIt->start;
1967 Overlaps = RHSIt->end > LHSIt->start;
1969 // If the live intervals overlap, there are two interesting cases: if the
1970 // LHS interval is defined by a copy from the RHS, it's ok and we record
1971 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1972 // coalesce these live ranges and we bail out.
1974 // If we haven't already recorded that this value # is safe, check it.
1975 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1976 // Copy from the RHS?
1977 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1978 return false; // Nope, bail out.
1980 if (LHSIt->contains(RHSIt->valno->def))
1981 // Here is an interesting situation:
1983 // vr1025 = copy vr1024
1988 // Even though vr1025 is copied from vr1024, it's not safe to
1989 // coalesce them since the live range of vr1025 intersects the
1990 // def of vr1024. This happens because vr1025 is assigned the
1991 // value of the previous iteration of vr1024.
1993 EliminatedLHSVals.push_back(LHSIt->valno);
1996 // We know this entire LHS live range is okay, so skip it now.
1997 if (++LHSIt == LHSEnd) break;
2001 if (LHSIt->end < RHSIt->end) {
2002 if (++LHSIt == LHSEnd) break;
2004 // One interesting case to check here. It's possible that we have
2005 // something like "X3 = Y" which defines a new value number in the LHS,
2006 // and is the last use of this liverange of the RHS. In this case, we
2007 // want to notice this copy (so that it gets coalesced away) even though
2008 // the live ranges don't actually overlap.
2009 if (LHSIt->start == RHSIt->end) {
2010 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
2011 // We already know that this value number is going to be merged in
2012 // if coalescing succeeds. Just skip the liverange.
2013 if (++LHSIt == LHSEnd) break;
2015 // Otherwise, if this is a copy from the RHS, mark it as being merged
2017 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
2018 if (LHSIt->contains(RHSIt->valno->def))
2019 // Here is an interesting situation:
2021 // vr1025 = copy vr1024
2026 // Even though vr1025 is copied from vr1024, it's not safe to
2027 // coalesced them since live range of vr1025 intersects the
2028 // def of vr1024. This happens because vr1025 is assigned the
2029 // value of the previous iteration of vr1024.
2031 EliminatedLHSVals.push_back(LHSIt->valno);
2033 // We know this entire LHS live range is okay, so skip it now.
2034 if (++LHSIt == LHSEnd) break;
2039 if (++RHSIt == RHSEnd) break;
2043 // If we got here, we know that the coalescing will be successful and that
2044 // the value numbers in EliminatedLHSVals will all be merged together. Since
2045 // the most common case is that EliminatedLHSVals has a single number, we
2046 // optimize for it: if there is more than one value, we merge them all into
2047 // the lowest numbered one, then handle the interval as if we were merging
2048 // with one value number.
2049 VNInfo *LHSValNo = NULL;
2050 if (EliminatedLHSVals.size() > 1) {
2051 // Loop through all the equal value numbers merging them into the smallest
2053 VNInfo *Smallest = EliminatedLHSVals[0];
2054 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
2055 if (EliminatedLHSVals[i]->id < Smallest->id) {
2056 // Merge the current notion of the smallest into the smaller one.
2057 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
2058 Smallest = EliminatedLHSVals[i];
2060 // Merge into the smallest.
2061 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
2064 LHSValNo = Smallest;
2065 } else if (EliminatedLHSVals.empty()) {
2066 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2067 *tri_->getSuperRegisters(LHS.reg))
2068 // Imprecise sub-register information. Can't handle it.
2070 llvm_unreachable("No copies from the RHS?");
2072 LHSValNo = EliminatedLHSVals[0];
2075 // Okay, now that there is a single LHS value number that we're merging the
2076 // RHS into, update the value number info for the LHS to indicate that the
2077 // value number is defined where the RHS value number was.
2078 const VNInfo *VNI = RHS.getValNumInfo(0);
2079 LHSValNo->def = VNI->def;
2080 LHSValNo->copy = VNI->copy;
2082 // Okay, the final step is to loop over the RHS live intervals, adding them to
2084 if (VNI->hasPHIKill())
2085 LHSValNo->setHasPHIKill(true);
2086 LHS.addKills(LHSValNo, VNI->kills);
2087 LHS.MergeRangesInAsValue(RHS, LHSValNo);
2088 LHS.weight += RHS.weight;
2090 // Update regalloc hint if both are virtual registers.
2091 if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
2092 TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
2093 std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
2094 std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
2095 if (RHSPref != LHSPref)
2096 mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second);
2099 // Update the liveintervals of sub-registers.
2100 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
2101 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
2102 li_->getOrCreateInterval(*AS).MergeInClobberRanges(LHS,
2103 li_->getVNInfoAllocator());
2108 /// JoinIntervals - Attempt to join these two intervals. On failure, this
2109 /// returns false. Otherwise, if one of the intervals being joined is a
2110 /// physreg, this method always canonicalizes LHS to be it. The output
2111 /// "RHS" will not have been modified, so we can use this information
2112 /// below to update aliases.
2114 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
2116 // Compute the final value assignment, assuming that the live ranges can be
2118 SmallVector<int, 16> LHSValNoAssignments;
2119 SmallVector<int, 16> RHSValNoAssignments;
2120 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
2121 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
2122 SmallVector<VNInfo*, 16> NewVNInfo;
2124 // If a live interval is a physical register, conservatively check if any
2125 // of its sub-registers is overlapping the live interval of the virtual
2126 // register. If so, do not coalesce.
2127 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2128 *tri_->getSubRegisters(LHS.reg)) {
2129 // If it's coalescing a virtual register to a physical register, estimate
2130 // its live interval length. This is the *cost* of scanning an entire live
2131 // interval. If the cost is low, we'll do an exhaustive check instead.
2133 // If this is something like this:
2141 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
2142 // less conservative check. It's possible a sub-register is defined before
2143 // v1024 (or live in) and live out of BB1.
2144 if (RHS.containsOneValue() &&
2145 li_->intervalIsInOneMBB(RHS) &&
2146 li_->getApproximateInstructionCount(RHS) <= 10) {
2147 // Perform a more exhaustive check for some common cases.
2148 if (li_->conflictsWithPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
2151 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
2152 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
2153 DOUT << "Interfere with sub-register ";
2154 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
2158 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
2159 *tri_->getSubRegisters(RHS.reg)) {
2160 if (LHS.containsOneValue() &&
2161 li_->getApproximateInstructionCount(LHS) <= 10) {
2162 // Perform a more exhaustive check for some common cases.
2163 if (li_->conflictsWithPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
2166 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
2167 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
2168 DOUT << "Interfere with sub-register ";
2169 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
2175 // Compute ultimate value numbers for the LHS and RHS values.
2176 if (RHS.containsOneValue()) {
2177 // Copies from a liveinterval with a single value are simple to handle and
2178 // very common, handle the special case here. This is important, because
2179 // often RHS is small and LHS is large (e.g. a physreg).
2181 // Find out if the RHS is defined as a copy from some value in the LHS.
2182 int RHSVal0DefinedFromLHS = -1;
2184 VNInfo *RHSValNoInfo = NULL;
2185 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
2186 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
2187 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
2188 // If RHS is not defined as a copy from the LHS, we can use simpler and
2189 // faster checks to see if the live ranges are coalescable. This joiner
2190 // can't swap the LHS/RHS intervals though.
2191 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2192 return SimpleJoin(LHS, RHS);
2194 RHSValNoInfo = RHSValNoInfo0;
2197 // It was defined as a copy from the LHS, find out what value # it is.
2198 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
2199 RHSValID = RHSValNoInfo->id;
2200 RHSVal0DefinedFromLHS = RHSValID;
2203 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2204 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2205 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2207 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2208 // should now get updated.
2209 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2212 unsigned VN = VNI->id;
2213 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2214 if (LHSSrcReg != RHS.reg) {
2215 // If this is not a copy from the RHS, its value number will be
2216 // unmodified by the coalescing.
2217 NewVNInfo[VN] = VNI;
2218 LHSValNoAssignments[VN] = VN;
2219 } else if (RHSValID == -1) {
2220 // Otherwise, it is a copy from the RHS, and we don't already have a
2221 // value# for it. Keep the current value number, but remember it.
2222 LHSValNoAssignments[VN] = RHSValID = VN;
2223 NewVNInfo[VN] = RHSValNoInfo;
2224 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2226 // Otherwise, use the specified value #.
2227 LHSValNoAssignments[VN] = RHSValID;
2228 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2229 NewVNInfo[VN] = RHSValNoInfo;
2230 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2234 NewVNInfo[VN] = VNI;
2235 LHSValNoAssignments[VN] = VN;
2239 assert(RHSValID != -1 && "Didn't find value #?");
2240 RHSValNoAssignments[0] = RHSValID;
2241 if (RHSVal0DefinedFromLHS != -1) {
2242 // This path doesn't go through ComputeUltimateVN so just set
2244 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2247 // Loop over the value numbers of the LHS, seeing if any are defined from
2249 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2252 if (VNI->isUnused() || VNI->copy == 0) // Src not defined by a copy?
2255 // DstReg is known to be a register in the LHS interval. If the src is
2256 // from the RHS interval, we can use its value #.
2257 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2260 // Figure out the value # from the RHS.
2261 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
2264 // Loop over the value numbers of the RHS, seeing if any are defined from
2266 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2269 if (VNI->isUnused() || VNI->copy == 0) // Src not defined by a copy?
2272 // DstReg is known to be a register in the RHS interval. If the src is
2273 // from the LHS interval, we can use its value #.
2274 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2277 // Figure out the value # from the LHS.
2278 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
2281 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2282 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2283 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2285 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2288 unsigned VN = VNI->id;
2289 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2291 ComputeUltimateVN(VNI, NewVNInfo,
2292 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2293 LHSValNoAssignments, RHSValNoAssignments);
2295 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2298 unsigned VN = VNI->id;
2299 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2301 // If this value number isn't a copy from the LHS, it's a new number.
2302 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2303 NewVNInfo.push_back(VNI);
2304 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2308 ComputeUltimateVN(VNI, NewVNInfo,
2309 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2310 RHSValNoAssignments, LHSValNoAssignments);
2314 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2315 // interval lists to see if these intervals are coalescable.
2316 LiveInterval::const_iterator I = LHS.begin();
2317 LiveInterval::const_iterator IE = LHS.end();
2318 LiveInterval::const_iterator J = RHS.begin();
2319 LiveInterval::const_iterator JE = RHS.end();
2321 // Skip ahead until the first place of potential sharing.
2322 if (I->start < J->start) {
2323 I = std::upper_bound(I, IE, J->start);
2324 if (I != LHS.begin()) --I;
2325 } else if (J->start < I->start) {
2326 J = std::upper_bound(J, JE, I->start);
2327 if (J != RHS.begin()) --J;
2331 // Determine if these two live ranges overlap.
2333 if (I->start < J->start) {
2334 Overlaps = I->end > J->start;
2336 Overlaps = J->end > I->start;
2339 // If so, check value # info to determine if they are really different.
2341 // If the live range overlap will map to the same value number in the
2342 // result liverange, we can still coalesce them. If not, we can't.
2343 if (LHSValNoAssignments[I->valno->id] !=
2344 RHSValNoAssignments[J->valno->id])
2348 if (I->end < J->end) {
2357 // Update kill info. Some live ranges are extended due to copy coalescing.
2358 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2359 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2360 VNInfo *VNI = I->first;
2361 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2362 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
2363 if (VNI->hasPHIKill())
2364 NewVNInfo[LHSValID]->setHasPHIKill(true);
2365 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2368 // Update kill info. Some live ranges are extended due to copy coalescing.
2369 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2370 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2371 VNInfo *VNI = I->first;
2372 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2373 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
2374 if (VNI->hasPHIKill())
2375 NewVNInfo[RHSValID]->setHasPHIKill(true);
2376 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2379 // If we get here, we know that we can coalesce the live ranges. Ask the
2380 // intervals to coalesce themselves now.
2381 if ((RHS.ranges.size() > LHS.ranges.size() &&
2382 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2383 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2384 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2388 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2396 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2397 // depth of the basic block (the unsigned), and then on the MBB number.
2398 struct DepthMBBCompare {
2399 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2400 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2401 if (LHS.first > RHS.first) return true; // Deeper loops first
2402 return LHS.first == RHS.first &&
2403 LHS.second->getNumber() < RHS.second->getNumber();
2408 /// getRepIntervalSize - Returns the size of the interval that represents the
2409 /// specified register.
2411 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
2412 return Rc->getRepIntervalSize(Reg);
2415 /// CopyRecSort::operator - Join priority queue sorting function.
2417 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
2418 // Inner loops first.
2419 if (left.LoopDepth > right.LoopDepth)
2421 else if (left.LoopDepth == right.LoopDepth)
2422 if (left.isBackEdge && !right.isBackEdge)
2427 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2428 std::vector<CopyRec> &TryAgain) {
2429 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
2431 std::vector<CopyRec> VirtCopies;
2432 std::vector<CopyRec> PhysCopies;
2433 std::vector<CopyRec> ImpDefCopies;
2434 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
2435 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2437 MachineInstr *Inst = MII++;
2439 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2440 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2441 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
2442 DstReg = Inst->getOperand(0).getReg();
2443 SrcReg = Inst->getOperand(1).getReg();
2444 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2445 Inst->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
2446 DstReg = Inst->getOperand(0).getReg();
2447 SrcReg = Inst->getOperand(2).getReg();
2448 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2451 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2452 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2454 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
2456 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
2457 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
2458 else if (SrcIsPhys || DstIsPhys)
2459 PhysCopies.push_back(CopyRec(Inst, 0, false));
2461 VirtCopies.push_back(CopyRec(Inst, 0, false));
2468 // Try coalescing implicit copies first, followed by copies to / from
2469 // physical registers, then finally copies from virtual registers to
2470 // virtual registers.
2471 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2472 CopyRec &TheCopy = ImpDefCopies[i];
2474 if (!JoinCopy(TheCopy, Again))
2476 TryAgain.push_back(TheCopy);
2478 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2479 CopyRec &TheCopy = PhysCopies[i];
2481 if (!JoinCopy(TheCopy, Again))
2483 TryAgain.push_back(TheCopy);
2485 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2486 CopyRec &TheCopy = VirtCopies[i];
2488 if (!JoinCopy(TheCopy, Again))
2490 TryAgain.push_back(TheCopy);
2494 void SimpleRegisterCoalescing::joinIntervals() {
2495 DOUT << "********** JOINING INTERVALS ***********\n";
2498 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
2500 std::vector<CopyRec> TryAgainList;
2501 if (loopInfo->empty()) {
2502 // If there are no loops in the function, join intervals in function order.
2503 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2505 CopyCoalesceInMBB(I, TryAgainList);
2507 // Otherwise, join intervals in inner loops before other intervals.
2508 // Unfortunately we can't just iterate over loop hierarchy here because
2509 // there may be more MBB's than BB's. Collect MBB's for sorting.
2511 // Join intervals in the function prolog first. We want to join physical
2512 // registers with virtual registers before the intervals got too long.
2513 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2514 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2515 MachineBasicBlock *MBB = I;
2516 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2519 // Sort by loop depth.
2520 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2522 // Finally, join intervals in loop nest order.
2523 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2524 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2527 // Joining intervals can allow other intervals to be joined. Iteratively join
2528 // until we make no progress.
2530 SmallVector<CopyRec, 16> TryAgain;
2531 bool ProgressMade = true;
2532 while (ProgressMade) {
2533 ProgressMade = false;
2534 while (!JoinQueue->empty()) {
2535 CopyRec R = JoinQueue->pop();
2537 bool Success = JoinCopy(R, Again);
2539 ProgressMade = true;
2541 TryAgain.push_back(R);
2545 while (!TryAgain.empty()) {
2546 JoinQueue->push(TryAgain.back());
2547 TryAgain.pop_back();
2552 bool ProgressMade = true;
2553 while (ProgressMade) {
2554 ProgressMade = false;
2556 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2557 CopyRec &TheCopy = TryAgainList[i];
2560 bool Success = JoinCopy(TheCopy, Again);
2561 if (Success || !Again) {
2562 TheCopy.MI = 0; // Mark this one as done.
2563 ProgressMade = true;
2574 /// Return true if the two specified registers belong to different register
2575 /// classes. The registers may be either phys or virt regs.
2577 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2578 unsigned RegB) const {
2579 // Get the register classes for the first reg.
2580 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2581 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2582 "Shouldn't consider two physregs!");
2583 return !mri_->getRegClass(RegB)->contains(RegA);
2586 // Compare against the regclass for the second reg.
2587 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2588 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2589 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2590 return RegClassA != RegClassB;
2592 return !RegClassA->contains(RegB);
2595 /// lastRegisterUse - Returns the last use of the specific register between
2596 /// cycles Start and End or NULL if there are no uses.
2598 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2599 unsigned Reg, unsigned &UseIdx) const{
2601 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2602 MachineOperand *LastUse = NULL;
2603 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2604 E = mri_->use_end(); I != E; ++I) {
2605 MachineOperand &Use = I.getOperand();
2606 MachineInstr *UseMI = Use.getParent();
2607 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2608 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2610 // Ignore identity copies.
2612 unsigned Idx = li_->getInstructionIndex(UseMI);
2613 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2615 UseIdx = li_->getUseIndex(Idx);
2621 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2624 // Skip deleted instructions
2625 MachineInstr *MI = li_->getInstructionFromIndex(e);
2626 while ((e - InstrSlots::NUM) >= s && !MI) {
2627 e -= InstrSlots::NUM;
2628 MI = li_->getInstructionFromIndex(e);
2630 if (e < s || MI == NULL)
2633 // Ignore identity copies.
2634 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2635 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2637 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2638 MachineOperand &Use = MI->getOperand(i);
2639 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2640 tri_->regsOverlap(Use.getReg(), Reg)) {
2641 UseIdx = li_->getUseIndex(e);
2646 e -= InstrSlots::NUM;
2653 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2654 if (TargetRegisterInfo::isPhysicalRegister(reg))
2655 cerr << tri_->getName(reg);
2657 cerr << "%reg" << reg;
2660 void SimpleRegisterCoalescing::releaseMemory() {
2661 JoinedCopies.clear();
2662 ReMatCopies.clear();
2666 static bool isZeroLengthInterval(LiveInterval *li) {
2667 for (LiveInterval::Ranges::const_iterator
2668 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2669 if (i->end - i->start > LiveInterval::InstrSlots::NUM)
2674 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
2675 /// turn the copy into an implicit def.
2677 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
2678 MachineBasicBlock *MBB,
2679 unsigned DstReg, unsigned SrcReg) {
2680 MachineInstr *CopyMI = &*I;
2681 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
2682 if (!li_->hasInterval(SrcReg))
2684 LiveInterval &SrcInt = li_->getInterval(SrcReg);
2685 if (!SrcInt.empty())
2687 if (!li_->hasInterval(DstReg))
2689 LiveInterval &DstInt = li_->getInterval(DstReg);
2690 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
2691 // If the valno extends beyond this basic block, then it's not safe to delete
2692 // the val# or else livein information won't be correct.
2693 MachineBasicBlock *EndMBB = li_->getMBBFromIndex(DstLR->end);
2696 DstInt.removeValNo(DstLR->valno);
2697 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
2698 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
2699 CopyMI->RemoveOperand(i);
2700 CopyMI->getOperand(0).setIsUndef();
2701 bool NoUse = mri_->use_empty(SrcReg);
2703 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
2704 RE = mri_->reg_end(); RI != RE; ) {
2705 assert(RI.getOperand().isDef());
2706 MachineInstr *DefMI = &*RI;
2708 // The implicit_def source has no other uses, delete it.
2709 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2710 li_->RemoveMachineInstrFromMaps(DefMI);
2711 DefMI->eraseFromParent();
2715 // Mark uses of implicit_def isUndef.
2716 for (MachineRegisterInfo::use_iterator RI = mri_->use_begin(DstReg),
2717 RE = mri_->use_end(); RI != RE; ++RI) {
2718 assert((*RI).getParent() == MBB);
2719 RI.getOperand().setIsUndef();
2727 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2729 mri_ = &fn.getRegInfo();
2730 tm_ = &fn.getTarget();
2731 tri_ = tm_->getRegisterInfo();
2732 tii_ = tm_->getInstrInfo();
2733 li_ = &getAnalysis<LiveIntervals>();
2734 loopInfo = &getAnalysis<MachineLoopInfo>();
2736 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2737 << "********** Function: "
2738 << ((Value*)mf_->getFunction())->getName() << '\n';
2740 allocatableRegs_ = tri_->getAllocatableSet(fn);
2741 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2742 E = tri_->regclass_end(); I != E; ++I)
2743 allocatableRCRegs_.insert(std::make_pair(*I,
2744 tri_->getAllocatableSet(fn, *I)));
2746 // Join (coalesce) intervals if requested.
2747 if (EnableJoining) {
2750 DOUT << "********** INTERVALS POST JOINING **********\n";
2751 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2752 I->second->print(DOUT, tri_);
2758 // Perform a final pass over the instructions and compute spill weights
2759 // and remove identity moves.
2760 SmallVector<unsigned, 4> DeadDefs;
2761 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2762 mbbi != mbbe; ++mbbi) {
2763 MachineBasicBlock* mbb = mbbi;
2764 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2766 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2768 MachineInstr *MI = mii;
2769 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2770 if (JoinedCopies.count(MI)) {
2771 // Delete all coalesced copies.
2772 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2773 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2774 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2775 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
2776 "Unrecognized copy instruction");
2777 DstReg = MI->getOperand(0).getReg();
2779 if (MI->registerDefIsDead(DstReg)) {
2780 LiveInterval &li = li_->getInterval(DstReg);
2781 if (!ShortenDeadCopySrcLiveRange(li, MI))
2782 ShortenDeadCopyLiveRange(li, MI);
2784 li_->RemoveMachineInstrFromMaps(MI);
2785 mii = mbbi->erase(mii);
2790 // Now check if this is a remat'ed def instruction which is now dead.
2791 if (ReMatDefs.count(MI)) {
2793 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2794 const MachineOperand &MO = MI->getOperand(i);
2797 unsigned Reg = MO.getReg();
2800 if (TargetRegisterInfo::isVirtualRegister(Reg))
2801 DeadDefs.push_back(Reg);
2804 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2805 !mri_->use_empty(Reg)) {
2811 while (!DeadDefs.empty()) {
2812 unsigned DeadDef = DeadDefs.back();
2813 DeadDefs.pop_back();
2814 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2816 li_->RemoveMachineInstrFromMaps(mii);
2817 mii = mbbi->erase(mii);
2823 // If the move will be an identity move delete it
2824 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2825 if (isMove && SrcReg == DstReg) {
2826 if (li_->hasInterval(SrcReg)) {
2827 LiveInterval &RegInt = li_->getInterval(SrcReg);
2828 // If def of this move instruction is dead, remove its live range
2829 // from the dstination register's live interval.
2830 if (MI->registerDefIsDead(DstReg)) {
2831 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2832 ShortenDeadCopyLiveRange(RegInt, MI);
2835 li_->RemoveMachineInstrFromMaps(MI);
2836 mii = mbbi->erase(mii);
2838 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2839 SmallSet<unsigned, 4> UniqueUses;
2840 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2841 const MachineOperand &mop = MI->getOperand(i);
2842 if (mop.isReg() && mop.getReg() &&
2843 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2844 unsigned reg = mop.getReg();
2845 // Multiple uses of reg by the same instruction. It should not
2846 // contribute to spill weight again.
2847 if (UniqueUses.count(reg) != 0)
2849 LiveInterval &RegInt = li_->getInterval(reg);
2851 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2852 UniqueUses.insert(reg);
2860 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2861 LiveInterval &LI = *I->second;
2862 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2863 // If the live interval length is essentially zero, i.e. in every live
2864 // range the use follows def immediately, it doesn't make sense to spill
2865 // it and hope it will be easier to allocate for this li.
2866 if (isZeroLengthInterval(&LI))
2867 LI.weight = HUGE_VALF;
2869 bool isLoad = false;
2870 SmallVector<LiveInterval*, 4> SpillIs;
2871 if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
2872 // If all of the definitions of the interval are re-materializable,
2873 // it is a preferred candidate for spilling. If non of the defs are
2874 // loads, then it's potentially very cheap to re-materialize.
2875 // FIXME: this gets much more complicated once we support non-trivial
2876 // re-materialization.
2884 // Slightly prefer live interval that has been assigned a preferred reg.
2885 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(LI.reg);
2886 if (Hint.first || Hint.second)
2889 // Divide the weight of the interval by its size. This encourages
2890 // spilling of intervals that are large and have few uses, and
2891 // discourages spilling of small intervals with many uses.
2892 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2900 /// print - Implement the dump method.
2901 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2905 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2906 return new SimpleRegisterCoalescing();
2909 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2910 DEFINING_FILE_FOR(SimpleRegisterCoalescing)