1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
33 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
34 bool isLocal = GV->hasLocalLinkage();
35 bool isDeclaration = GV->isDeclaration();
36 // FIXME: what should we do for protected and internal visibility?
37 // For variables, is internal different from hidden?
38 bool isHidden = GV->hasHiddenVisibility();
40 if (reloc == Reloc::PIC_) {
41 if (isLocal || isHidden)
42 return TLSModel::LocalDynamic;
44 return TLSModel::GeneralDynamic;
46 if (!isDeclaration || isHidden)
47 return TLSModel::LocalExec;
49 return TLSModel::InitialExec;
54 /// InitLibcallNames - Set default libcall names.
56 static void InitLibcallNames(const char **Names) {
57 Names[RTLIB::SHL_I16] = "__ashlhi3";
58 Names[RTLIB::SHL_I32] = "__ashlsi3";
59 Names[RTLIB::SHL_I64] = "__ashldi3";
60 Names[RTLIB::SHL_I128] = "__ashlti3";
61 Names[RTLIB::SRL_I16] = "__lshrhi3";
62 Names[RTLIB::SRL_I32] = "__lshrsi3";
63 Names[RTLIB::SRL_I64] = "__lshrdi3";
64 Names[RTLIB::SRL_I128] = "__lshrti3";
65 Names[RTLIB::SRA_I16] = "__ashrhi3";
66 Names[RTLIB::SRA_I32] = "__ashrsi3";
67 Names[RTLIB::SRA_I64] = "__ashrdi3";
68 Names[RTLIB::SRA_I128] = "__ashrti3";
69 Names[RTLIB::MUL_I8] = "__mulqi3";
70 Names[RTLIB::MUL_I16] = "__mulhi3";
71 Names[RTLIB::MUL_I32] = "__mulsi3";
72 Names[RTLIB::MUL_I64] = "__muldi3";
73 Names[RTLIB::MUL_I128] = "__multi3";
74 Names[RTLIB::SDIV_I8] = "__divqi3";
75 Names[RTLIB::SDIV_I16] = "__divhi3";
76 Names[RTLIB::SDIV_I32] = "__divsi3";
77 Names[RTLIB::SDIV_I64] = "__divdi3";
78 Names[RTLIB::SDIV_I128] = "__divti3";
79 Names[RTLIB::UDIV_I8] = "__udivqi3";
80 Names[RTLIB::UDIV_I16] = "__udivhi3";
81 Names[RTLIB::UDIV_I32] = "__udivsi3";
82 Names[RTLIB::UDIV_I64] = "__udivdi3";
83 Names[RTLIB::UDIV_I128] = "__udivti3";
84 Names[RTLIB::SREM_I8] = "__modqi3";
85 Names[RTLIB::SREM_I16] = "__modhi3";
86 Names[RTLIB::SREM_I32] = "__modsi3";
87 Names[RTLIB::SREM_I64] = "__moddi3";
88 Names[RTLIB::SREM_I128] = "__modti3";
89 Names[RTLIB::UREM_I8] = "__umodqi3";
90 Names[RTLIB::UREM_I16] = "__umodhi3";
91 Names[RTLIB::UREM_I32] = "__umodsi3";
92 Names[RTLIB::UREM_I64] = "__umoddi3";
93 Names[RTLIB::UREM_I128] = "__umodti3";
94 Names[RTLIB::NEG_I32] = "__negsi2";
95 Names[RTLIB::NEG_I64] = "__negdi2";
96 Names[RTLIB::ADD_F32] = "__addsf3";
97 Names[RTLIB::ADD_F64] = "__adddf3";
98 Names[RTLIB::ADD_F80] = "__addxf3";
99 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
100 Names[RTLIB::SUB_F32] = "__subsf3";
101 Names[RTLIB::SUB_F64] = "__subdf3";
102 Names[RTLIB::SUB_F80] = "__subxf3";
103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
104 Names[RTLIB::MUL_F32] = "__mulsf3";
105 Names[RTLIB::MUL_F64] = "__muldf3";
106 Names[RTLIB::MUL_F80] = "__mulxf3";
107 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
108 Names[RTLIB::DIV_F32] = "__divsf3";
109 Names[RTLIB::DIV_F64] = "__divdf3";
110 Names[RTLIB::DIV_F80] = "__divxf3";
111 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
112 Names[RTLIB::REM_F32] = "fmodf";
113 Names[RTLIB::REM_F64] = "fmod";
114 Names[RTLIB::REM_F80] = "fmodl";
115 Names[RTLIB::REM_PPCF128] = "fmodl";
116 Names[RTLIB::POWI_F32] = "__powisf2";
117 Names[RTLIB::POWI_F64] = "__powidf2";
118 Names[RTLIB::POWI_F80] = "__powixf2";
119 Names[RTLIB::POWI_PPCF128] = "__powitf2";
120 Names[RTLIB::SQRT_F32] = "sqrtf";
121 Names[RTLIB::SQRT_F64] = "sqrt";
122 Names[RTLIB::SQRT_F80] = "sqrtl";
123 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
124 Names[RTLIB::LOG_F32] = "logf";
125 Names[RTLIB::LOG_F64] = "log";
126 Names[RTLIB::LOG_F80] = "logl";
127 Names[RTLIB::LOG_PPCF128] = "logl";
128 Names[RTLIB::LOG2_F32] = "log2f";
129 Names[RTLIB::LOG2_F64] = "log2";
130 Names[RTLIB::LOG2_F80] = "log2l";
131 Names[RTLIB::LOG2_PPCF128] = "log2l";
132 Names[RTLIB::LOG10_F32] = "log10f";
133 Names[RTLIB::LOG10_F64] = "log10";
134 Names[RTLIB::LOG10_F80] = "log10l";
135 Names[RTLIB::LOG10_PPCF128] = "log10l";
136 Names[RTLIB::EXP_F32] = "expf";
137 Names[RTLIB::EXP_F64] = "exp";
138 Names[RTLIB::EXP_F80] = "expl";
139 Names[RTLIB::EXP_PPCF128] = "expl";
140 Names[RTLIB::EXP2_F32] = "exp2f";
141 Names[RTLIB::EXP2_F64] = "exp2";
142 Names[RTLIB::EXP2_F80] = "exp2l";
143 Names[RTLIB::EXP2_PPCF128] = "exp2l";
144 Names[RTLIB::SIN_F32] = "sinf";
145 Names[RTLIB::SIN_F64] = "sin";
146 Names[RTLIB::SIN_F80] = "sinl";
147 Names[RTLIB::SIN_PPCF128] = "sinl";
148 Names[RTLIB::COS_F32] = "cosf";
149 Names[RTLIB::COS_F64] = "cos";
150 Names[RTLIB::COS_F80] = "cosl";
151 Names[RTLIB::COS_PPCF128] = "cosl";
152 Names[RTLIB::POW_F32] = "powf";
153 Names[RTLIB::POW_F64] = "pow";
154 Names[RTLIB::POW_F80] = "powl";
155 Names[RTLIB::POW_PPCF128] = "powl";
156 Names[RTLIB::CEIL_F32] = "ceilf";
157 Names[RTLIB::CEIL_F64] = "ceil";
158 Names[RTLIB::CEIL_F80] = "ceill";
159 Names[RTLIB::CEIL_PPCF128] = "ceill";
160 Names[RTLIB::TRUNC_F32] = "truncf";
161 Names[RTLIB::TRUNC_F64] = "trunc";
162 Names[RTLIB::TRUNC_F80] = "truncl";
163 Names[RTLIB::TRUNC_PPCF128] = "truncl";
164 Names[RTLIB::RINT_F32] = "rintf";
165 Names[RTLIB::RINT_F64] = "rint";
166 Names[RTLIB::RINT_F80] = "rintl";
167 Names[RTLIB::RINT_PPCF128] = "rintl";
168 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
169 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
170 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
171 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
172 Names[RTLIB::FLOOR_F32] = "floorf";
173 Names[RTLIB::FLOOR_F64] = "floor";
174 Names[RTLIB::FLOOR_F80] = "floorl";
175 Names[RTLIB::FLOOR_PPCF128] = "floorl";
176 Names[RTLIB::COPYSIGN_F32] = "copysignf";
177 Names[RTLIB::COPYSIGN_F64] = "copysign";
178 Names[RTLIB::COPYSIGN_F80] = "copysignl";
179 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
180 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
181 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
182 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
183 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
184 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
185 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
186 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
187 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
188 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
189 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
190 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
191 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
192 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
193 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
194 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
195 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
196 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
197 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
198 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
199 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
200 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
201 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
202 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
203 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
204 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
205 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
206 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
207 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
208 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
209 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
210 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
211 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
212 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
213 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
214 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
215 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
216 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
217 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
218 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
219 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
220 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
221 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
222 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
223 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
224 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
225 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
226 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
227 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
228 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
229 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
230 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
231 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
232 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
233 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
234 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
235 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
236 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
237 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
238 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
239 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
240 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
241 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
242 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
243 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
244 Names[RTLIB::OEQ_F32] = "__eqsf2";
245 Names[RTLIB::OEQ_F64] = "__eqdf2";
246 Names[RTLIB::UNE_F32] = "__nesf2";
247 Names[RTLIB::UNE_F64] = "__nedf2";
248 Names[RTLIB::OGE_F32] = "__gesf2";
249 Names[RTLIB::OGE_F64] = "__gedf2";
250 Names[RTLIB::OLT_F32] = "__ltsf2";
251 Names[RTLIB::OLT_F64] = "__ltdf2";
252 Names[RTLIB::OLE_F32] = "__lesf2";
253 Names[RTLIB::OLE_F64] = "__ledf2";
254 Names[RTLIB::OGT_F32] = "__gtsf2";
255 Names[RTLIB::OGT_F64] = "__gtdf2";
256 Names[RTLIB::UO_F32] = "__unordsf2";
257 Names[RTLIB::UO_F64] = "__unorddf2";
258 Names[RTLIB::O_F32] = "__unordsf2";
259 Names[RTLIB::O_F64] = "__unorddf2";
260 Names[RTLIB::MEMCPY] = "memcpy";
261 Names[RTLIB::MEMMOVE] = "memmove";
262 Names[RTLIB::MEMSET] = "memset";
263 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
264 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
268 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
272 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
273 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
274 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
276 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
277 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
280 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
281 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
282 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
283 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
284 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
285 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
286 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
287 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
288 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
289 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
292 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
293 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
298 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
300 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
301 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
302 CCs[i] = CallingConv::C;
306 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
307 /// UNKNOWN_LIBCALL if there is none.
308 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
309 if (OpVT == MVT::f32) {
310 if (RetVT == MVT::f64)
311 return FPEXT_F32_F64;
314 return UNKNOWN_LIBCALL;
317 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
318 /// UNKNOWN_LIBCALL if there is none.
319 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
320 if (RetVT == MVT::f32) {
321 if (OpVT == MVT::f64)
322 return FPROUND_F64_F32;
323 if (OpVT == MVT::f80)
324 return FPROUND_F80_F32;
325 if (OpVT == MVT::ppcf128)
326 return FPROUND_PPCF128_F32;
327 } else if (RetVT == MVT::f64) {
328 if (OpVT == MVT::f80)
329 return FPROUND_F80_F64;
330 if (OpVT == MVT::ppcf128)
331 return FPROUND_PPCF128_F64;
334 return UNKNOWN_LIBCALL;
337 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
338 /// UNKNOWN_LIBCALL if there is none.
339 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
340 if (OpVT == MVT::f32) {
341 if (RetVT == MVT::i8)
342 return FPTOSINT_F32_I8;
343 if (RetVT == MVT::i16)
344 return FPTOSINT_F32_I16;
345 if (RetVT == MVT::i32)
346 return FPTOSINT_F32_I32;
347 if (RetVT == MVT::i64)
348 return FPTOSINT_F32_I64;
349 if (RetVT == MVT::i128)
350 return FPTOSINT_F32_I128;
351 } else if (OpVT == MVT::f64) {
352 if (RetVT == MVT::i8)
353 return FPTOSINT_F64_I8;
354 if (RetVT == MVT::i16)
355 return FPTOSINT_F64_I16;
356 if (RetVT == MVT::i32)
357 return FPTOSINT_F64_I32;
358 if (RetVT == MVT::i64)
359 return FPTOSINT_F64_I64;
360 if (RetVT == MVT::i128)
361 return FPTOSINT_F64_I128;
362 } else if (OpVT == MVT::f80) {
363 if (RetVT == MVT::i32)
364 return FPTOSINT_F80_I32;
365 if (RetVT == MVT::i64)
366 return FPTOSINT_F80_I64;
367 if (RetVT == MVT::i128)
368 return FPTOSINT_F80_I128;
369 } else if (OpVT == MVT::ppcf128) {
370 if (RetVT == MVT::i32)
371 return FPTOSINT_PPCF128_I32;
372 if (RetVT == MVT::i64)
373 return FPTOSINT_PPCF128_I64;
374 if (RetVT == MVT::i128)
375 return FPTOSINT_PPCF128_I128;
377 return UNKNOWN_LIBCALL;
380 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
381 /// UNKNOWN_LIBCALL if there is none.
382 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
383 if (OpVT == MVT::f32) {
384 if (RetVT == MVT::i8)
385 return FPTOUINT_F32_I8;
386 if (RetVT == MVT::i16)
387 return FPTOUINT_F32_I16;
388 if (RetVT == MVT::i32)
389 return FPTOUINT_F32_I32;
390 if (RetVT == MVT::i64)
391 return FPTOUINT_F32_I64;
392 if (RetVT == MVT::i128)
393 return FPTOUINT_F32_I128;
394 } else if (OpVT == MVT::f64) {
395 if (RetVT == MVT::i8)
396 return FPTOUINT_F64_I8;
397 if (RetVT == MVT::i16)
398 return FPTOUINT_F64_I16;
399 if (RetVT == MVT::i32)
400 return FPTOUINT_F64_I32;
401 if (RetVT == MVT::i64)
402 return FPTOUINT_F64_I64;
403 if (RetVT == MVT::i128)
404 return FPTOUINT_F64_I128;
405 } else if (OpVT == MVT::f80) {
406 if (RetVT == MVT::i32)
407 return FPTOUINT_F80_I32;
408 if (RetVT == MVT::i64)
409 return FPTOUINT_F80_I64;
410 if (RetVT == MVT::i128)
411 return FPTOUINT_F80_I128;
412 } else if (OpVT == MVT::ppcf128) {
413 if (RetVT == MVT::i32)
414 return FPTOUINT_PPCF128_I32;
415 if (RetVT == MVT::i64)
416 return FPTOUINT_PPCF128_I64;
417 if (RetVT == MVT::i128)
418 return FPTOUINT_PPCF128_I128;
420 return UNKNOWN_LIBCALL;
423 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
424 /// UNKNOWN_LIBCALL if there is none.
425 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
426 if (OpVT == MVT::i32) {
427 if (RetVT == MVT::f32)
428 return SINTTOFP_I32_F32;
429 else if (RetVT == MVT::f64)
430 return SINTTOFP_I32_F64;
431 else if (RetVT == MVT::f80)
432 return SINTTOFP_I32_F80;
433 else if (RetVT == MVT::ppcf128)
434 return SINTTOFP_I32_PPCF128;
435 } else if (OpVT == MVT::i64) {
436 if (RetVT == MVT::f32)
437 return SINTTOFP_I64_F32;
438 else if (RetVT == MVT::f64)
439 return SINTTOFP_I64_F64;
440 else if (RetVT == MVT::f80)
441 return SINTTOFP_I64_F80;
442 else if (RetVT == MVT::ppcf128)
443 return SINTTOFP_I64_PPCF128;
444 } else if (OpVT == MVT::i128) {
445 if (RetVT == MVT::f32)
446 return SINTTOFP_I128_F32;
447 else if (RetVT == MVT::f64)
448 return SINTTOFP_I128_F64;
449 else if (RetVT == MVT::f80)
450 return SINTTOFP_I128_F80;
451 else if (RetVT == MVT::ppcf128)
452 return SINTTOFP_I128_PPCF128;
454 return UNKNOWN_LIBCALL;
457 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
458 /// UNKNOWN_LIBCALL if there is none.
459 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
460 if (OpVT == MVT::i32) {
461 if (RetVT == MVT::f32)
462 return UINTTOFP_I32_F32;
463 else if (RetVT == MVT::f64)
464 return UINTTOFP_I32_F64;
465 else if (RetVT == MVT::f80)
466 return UINTTOFP_I32_F80;
467 else if (RetVT == MVT::ppcf128)
468 return UINTTOFP_I32_PPCF128;
469 } else if (OpVT == MVT::i64) {
470 if (RetVT == MVT::f32)
471 return UINTTOFP_I64_F32;
472 else if (RetVT == MVT::f64)
473 return UINTTOFP_I64_F64;
474 else if (RetVT == MVT::f80)
475 return UINTTOFP_I64_F80;
476 else if (RetVT == MVT::ppcf128)
477 return UINTTOFP_I64_PPCF128;
478 } else if (OpVT == MVT::i128) {
479 if (RetVT == MVT::f32)
480 return UINTTOFP_I128_F32;
481 else if (RetVT == MVT::f64)
482 return UINTTOFP_I128_F64;
483 else if (RetVT == MVT::f80)
484 return UINTTOFP_I128_F80;
485 else if (RetVT == MVT::ppcf128)
486 return UINTTOFP_I128_PPCF128;
488 return UNKNOWN_LIBCALL;
491 /// InitCmpLibcallCCs - Set default comparison libcall CC.
493 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
494 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
495 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
496 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
497 CCs[RTLIB::UNE_F32] = ISD::SETNE;
498 CCs[RTLIB::UNE_F64] = ISD::SETNE;
499 CCs[RTLIB::OGE_F32] = ISD::SETGE;
500 CCs[RTLIB::OGE_F64] = ISD::SETGE;
501 CCs[RTLIB::OLT_F32] = ISD::SETLT;
502 CCs[RTLIB::OLT_F64] = ISD::SETLT;
503 CCs[RTLIB::OLE_F32] = ISD::SETLE;
504 CCs[RTLIB::OLE_F64] = ISD::SETLE;
505 CCs[RTLIB::OGT_F32] = ISD::SETGT;
506 CCs[RTLIB::OGT_F64] = ISD::SETGT;
507 CCs[RTLIB::UO_F32] = ISD::SETNE;
508 CCs[RTLIB::UO_F64] = ISD::SETNE;
509 CCs[RTLIB::O_F32] = ISD::SETEQ;
510 CCs[RTLIB::O_F64] = ISD::SETEQ;
513 /// NOTE: The constructor takes ownership of TLOF.
514 TargetLowering::TargetLowering(const TargetMachine &tm,
515 const TargetLoweringObjectFile *tlof)
516 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
517 // All operations default to being supported.
518 memset(OpActions, 0, sizeof(OpActions));
519 memset(LoadExtActions, 0, sizeof(LoadExtActions));
520 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
521 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
522 memset(CondCodeActions, 0, sizeof(CondCodeActions));
524 // Set default actions for various operations.
525 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
526 // Default all indexed load / store to expand.
527 for (unsigned IM = (unsigned)ISD::PRE_INC;
528 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
529 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
530 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
533 // These operations default to expand.
534 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
538 // Most targets ignore the @llvm.prefetch intrinsic.
539 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
541 // ConstantFP nodes default to expand. Targets can either change this to
542 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
543 // to optimize expansions for certain constants.
544 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
545 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
546 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
548 // These library functions default to expand.
549 setOperationAction(ISD::FLOG , MVT::f64, Expand);
550 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
551 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
552 setOperationAction(ISD::FEXP , MVT::f64, Expand);
553 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
554 setOperationAction(ISD::FLOG , MVT::f32, Expand);
555 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
556 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
557 setOperationAction(ISD::FEXP , MVT::f32, Expand);
558 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
560 // Default ISD::TRAP to expand (which turns it into abort).
561 setOperationAction(ISD::TRAP, MVT::Other, Expand);
563 IsLittleEndian = TD->isLittleEndian();
564 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
565 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
566 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
567 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
568 benefitFromCodePlacementOpt = false;
569 UseUnderscoreSetJmp = false;
570 UseUnderscoreLongJmp = false;
571 SelectIsExpensive = false;
572 IntDivIsCheap = false;
573 Pow2DivIsCheap = false;
574 StackPointerRegisterToSaveRestore = 0;
575 ExceptionPointerRegister = 0;
576 ExceptionSelectorRegister = 0;
577 BooleanContents = UndefinedBooleanContent;
578 SchedPreferenceInfo = Sched::Latency;
580 JumpBufAlignment = 0;
581 PrefLoopAlignment = 0;
582 ShouldFoldAtomicFences = false;
584 InitLibcallNames(LibcallRoutineNames);
585 InitCmpLibcallCCs(CmpLibcallCCs);
586 InitLibcallCallingConvs(LibcallCallingConvs);
589 TargetLowering::~TargetLowering() {
593 /// canOpTrap - Returns true if the operation can trap for the value type.
594 /// VT must be a legal type.
595 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
596 assert(isTypeLegal(VT));
611 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
612 unsigned &NumIntermediates,
614 TargetLowering *TLI) {
615 // Figure out the right, legal destination reg to copy into.
616 unsigned NumElts = VT.getVectorNumElements();
617 MVT EltTy = VT.getVectorElementType();
619 unsigned NumVectorRegs = 1;
621 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
622 // could break down into LHS/RHS like LegalizeDAG does.
623 if (!isPowerOf2_32(NumElts)) {
624 NumVectorRegs = NumElts;
628 // Divide the input until we get to a supported size. This will always
629 // end with a scalar if the target doesn't support vectors.
630 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
635 NumIntermediates = NumVectorRegs;
637 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
638 if (!TLI->isTypeLegal(NewVT))
640 IntermediateVT = NewVT;
642 EVT DestVT = TLI->getRegisterType(NewVT);
644 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
645 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
647 // Otherwise, promotion or legal types use the same number of registers as
648 // the vector decimated to the appropriate level.
649 return NumVectorRegs;
652 /// computeRegisterProperties - Once all of the register classes are added,
653 /// this allows us to compute derived properties we expose.
654 void TargetLowering::computeRegisterProperties() {
655 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
656 "Too many value types for ValueTypeActions to hold!");
658 // Everything defaults to needing one register.
659 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
660 NumRegistersForVT[i] = 1;
661 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
663 // ...except isVoid, which doesn't need any registers.
664 NumRegistersForVT[MVT::isVoid] = 0;
666 // Find the largest integer register class.
667 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
668 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
669 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
671 // Every integer value type larger than this largest register takes twice as
672 // many registers to represent as the previous ValueType.
673 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
674 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
675 if (!ExpandedVT.isInteger())
677 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
678 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
679 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
680 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
683 // Inspect all of the ValueType's smaller than the largest integer
684 // register to see which ones need promotion.
685 unsigned LegalIntReg = LargestIntReg;
686 for (unsigned IntReg = LargestIntReg - 1;
687 IntReg >= (unsigned)MVT::i1; --IntReg) {
688 EVT IVT = (MVT::SimpleValueType)IntReg;
689 if (isTypeLegal(IVT)) {
690 LegalIntReg = IntReg;
692 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
693 (MVT::SimpleValueType)LegalIntReg;
694 ValueTypeActions.setTypeAction(IVT, Promote);
698 // ppcf128 type is really two f64's.
699 if (!isTypeLegal(MVT::ppcf128)) {
700 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
701 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
702 TransformToType[MVT::ppcf128] = MVT::f64;
703 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
706 // Decide how to handle f64. If the target does not have native f64 support,
707 // expand it to i64 and we will be generating soft float library calls.
708 if (!isTypeLegal(MVT::f64)) {
709 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
710 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
711 TransformToType[MVT::f64] = MVT::i64;
712 ValueTypeActions.setTypeAction(MVT::f64, Expand);
715 // Decide how to handle f32. If the target does not have native support for
716 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
717 if (!isTypeLegal(MVT::f32)) {
718 if (isTypeLegal(MVT::f64)) {
719 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
720 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
721 TransformToType[MVT::f32] = MVT::f64;
722 ValueTypeActions.setTypeAction(MVT::f32, Promote);
724 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
725 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
726 TransformToType[MVT::f32] = MVT::i32;
727 ValueTypeActions.setTypeAction(MVT::f32, Expand);
731 // Loop over all of the vector value types to see which need transformations.
732 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
733 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
734 MVT VT = (MVT::SimpleValueType)i;
735 if (isTypeLegal(VT)) continue;
739 unsigned NumIntermediates;
740 NumRegistersForVT[i] =
741 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
743 RegisterTypeForVT[i] = RegisterVT;
745 // Determine if there is a legal wider type.
746 bool IsLegalWiderType = false;
747 EVT EltVT = VT.getVectorElementType();
748 unsigned NElts = VT.getVectorNumElements();
749 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
750 EVT SVT = (MVT::SimpleValueType)nVT;
751 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
752 SVT.getVectorNumElements() > NElts && NElts != 1) {
753 TransformToType[i] = SVT;
754 ValueTypeActions.setTypeAction(VT, Promote);
755 IsLegalWiderType = true;
759 if (!IsLegalWiderType) {
760 EVT NVT = VT.getPow2VectorType();
762 // Type is already a power of 2. The default action is to split.
763 TransformToType[i] = MVT::Other;
764 ValueTypeActions.setTypeAction(VT, Expand);
766 TransformToType[i] = NVT;
767 ValueTypeActions.setTypeAction(VT, Promote);
773 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
778 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
779 return PointerTy.SimpleTy;
782 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
783 return MVT::i32; // return the default value
786 /// getVectorTypeBreakdown - Vector types are broken down into some number of
787 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
788 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
789 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
791 /// This method returns the number of registers needed, and the VT for each
792 /// register. It also returns the VT and quantity of the intermediate values
793 /// before they are promoted/expanded.
795 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
797 unsigned &NumIntermediates,
798 EVT &RegisterVT) const {
799 // Figure out the right, legal destination reg to copy into.
800 unsigned NumElts = VT.getVectorNumElements();
801 EVT EltTy = VT.getVectorElementType();
803 unsigned NumVectorRegs = 1;
805 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
806 // could break down into LHS/RHS like LegalizeDAG does.
807 if (!isPowerOf2_32(NumElts)) {
808 NumVectorRegs = NumElts;
812 // Divide the input until we get to a supported size. This will always
813 // end with a scalar if the target doesn't support vectors.
814 while (NumElts > 1 && !isTypeLegal(
815 EVT::getVectorVT(Context, EltTy, NumElts))) {
820 NumIntermediates = NumVectorRegs;
822 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
823 if (!isTypeLegal(NewVT))
825 IntermediateVT = NewVT;
827 EVT DestVT = getRegisterType(Context, NewVT);
829 if (DestVT.bitsLT(NewVT)) {
830 // Value is expanded, e.g. i64 -> i16.
831 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
833 // Otherwise, promotion or legal types use the same number of registers as
834 // the vector decimated to the appropriate level.
835 return NumVectorRegs;
841 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
842 /// function arguments in the caller parameter area. This is the actual
843 /// alignment, not its logarithm.
844 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
845 return TD->getCallFrameTypeAlignment(Ty);
848 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
849 /// current function. The returned value is a member of the
850 /// MachineJumpTableInfo::JTEntryKind enum.
851 unsigned TargetLowering::getJumpTableEncoding() const {
852 // In non-pic modes, just use the address of a block.
853 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
854 return MachineJumpTableInfo::EK_BlockAddress;
856 // In PIC mode, if the target supports a GPRel32 directive, use it.
857 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
858 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
860 // Otherwise, use a label difference.
861 return MachineJumpTableInfo::EK_LabelDifference32;
864 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
865 SelectionDAG &DAG) const {
866 // If our PIC model is GP relative, use the global offset table as the base.
867 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
868 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
872 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
873 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
876 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
877 unsigned JTI,MCContext &Ctx) const{
878 // The normal PIC reloc base is the label at the start of the jump table.
879 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
883 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
884 // Assume that everything is safe in static mode.
885 if (getTargetMachine().getRelocationModel() == Reloc::Static)
888 // In dynamic-no-pic mode, assume that known defined values are safe.
889 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
891 !GA->getGlobal()->isDeclaration() &&
892 !GA->getGlobal()->isWeakForLinker())
895 // Otherwise assume nothing is safe.
899 //===----------------------------------------------------------------------===//
900 // Optimization Methods
901 //===----------------------------------------------------------------------===//
903 /// ShrinkDemandedConstant - Check to see if the specified operand of the
904 /// specified instruction is a constant integer. If so, check to see if there
905 /// are any bits set in the constant that are not demanded. If so, shrink the
906 /// constant and return true.
907 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
908 const APInt &Demanded) {
909 DebugLoc dl = Op.getDebugLoc();
911 // FIXME: ISD::SELECT, ISD::SELECT_CC
912 switch (Op.getOpcode()) {
917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
918 if (!C) return false;
920 if (Op.getOpcode() == ISD::XOR &&
921 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
924 // if we can expand it to have all bits set, do it
925 if (C->getAPIntValue().intersects(~Demanded)) {
926 EVT VT = Op.getValueType();
927 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
928 DAG.getConstant(Demanded &
931 return CombineTo(Op, New);
941 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
942 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
943 /// cast, but it could be generalized for targets with other types of
944 /// implicit widening casts.
946 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
948 const APInt &Demanded,
950 assert(Op.getNumOperands() == 2 &&
951 "ShrinkDemandedOp only supports binary operators!");
952 assert(Op.getNode()->getNumValues() == 1 &&
953 "ShrinkDemandedOp only supports nodes with one result!");
955 // Don't do this if the node has another user, which may require the
957 if (!Op.getNode()->hasOneUse())
960 // Search for the smallest integer type with free casts to and from
961 // Op's type. For expedience, just check power-of-2 integer types.
962 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
963 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
964 if (!isPowerOf2_32(SmallVTBits))
965 SmallVTBits = NextPowerOf2(SmallVTBits);
966 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
967 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
968 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
969 TLI.isZExtFree(SmallVT, Op.getValueType())) {
970 // We found a type with free casts.
971 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
972 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
973 Op.getNode()->getOperand(0)),
974 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
975 Op.getNode()->getOperand(1)));
976 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
977 return CombineTo(Op, Z);
983 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
984 /// DemandedMask bits of the result of Op are ever used downstream. If we can
985 /// use this information to simplify Op, create a new simplified DAG node and
986 /// return true, returning the original and new nodes in Old and New. Otherwise,
987 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
988 /// the expression (used to simplify the caller). The KnownZero/One bits may
989 /// only be accurate for those bits in the DemandedMask.
990 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
991 const APInt &DemandedMask,
994 TargetLoweringOpt &TLO,
995 unsigned Depth) const {
996 unsigned BitWidth = DemandedMask.getBitWidth();
997 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
998 "Mask size mismatches value type size!");
999 APInt NewMask = DemandedMask;
1000 DebugLoc dl = Op.getDebugLoc();
1002 // Don't know anything.
1003 KnownZero = KnownOne = APInt(BitWidth, 0);
1005 // Other users may use these bits.
1006 if (!Op.getNode()->hasOneUse()) {
1008 // If not at the root, Just compute the KnownZero/KnownOne bits to
1009 // simplify things downstream.
1010 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
1013 // If this is the root being simplified, allow it to have multiple uses,
1014 // just set the NewMask to all bits.
1015 NewMask = APInt::getAllOnesValue(BitWidth);
1016 } else if (DemandedMask == 0) {
1017 // Not demanding any bits from Op.
1018 if (Op.getOpcode() != ISD::UNDEF)
1019 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1021 } else if (Depth == 6) { // Limit search depth.
1025 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1026 switch (Op.getOpcode()) {
1028 // We know all of the bits for a constant!
1029 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1030 KnownZero = ~KnownOne & NewMask;
1031 return false; // Don't fall through, will infinitely loop.
1033 // If the RHS is a constant, check to see if the LHS would be zero without
1034 // using the bits from the RHS. Below, we use knowledge about the RHS to
1035 // simplify the LHS, here we're using information from the LHS to simplify
1037 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1038 APInt LHSZero, LHSOne;
1039 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
1040 LHSZero, LHSOne, Depth+1);
1041 // If the LHS already has zeros where RHSC does, this and is dead.
1042 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1043 return TLO.CombineTo(Op, Op.getOperand(0));
1044 // If any of the set bits in the RHS are known zero on the LHS, shrink
1046 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1050 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1051 KnownOne, TLO, Depth+1))
1053 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1054 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1055 KnownZero2, KnownOne2, TLO, Depth+1))
1057 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1059 // If all of the demanded bits are known one on one side, return the other.
1060 // These bits cannot contribute to the result of the 'and'.
1061 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1062 return TLO.CombineTo(Op, Op.getOperand(0));
1063 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1064 return TLO.CombineTo(Op, Op.getOperand(1));
1065 // If all of the demanded bits in the inputs are known zeros, return zero.
1066 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1067 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1068 // If the RHS is a constant, see if we can simplify it.
1069 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1071 // If the operation can be done in a smaller type, do so.
1072 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1075 // Output known-1 bits are only known if set in both the LHS & RHS.
1076 KnownOne &= KnownOne2;
1077 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1078 KnownZero |= KnownZero2;
1081 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1082 KnownOne, TLO, Depth+1))
1084 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1085 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1086 KnownZero2, KnownOne2, TLO, Depth+1))
1088 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1090 // If all of the demanded bits are known zero on one side, return the other.
1091 // These bits cannot contribute to the result of the 'or'.
1092 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1093 return TLO.CombineTo(Op, Op.getOperand(0));
1094 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1095 return TLO.CombineTo(Op, Op.getOperand(1));
1096 // If all of the potentially set bits on one side are known to be set on
1097 // the other side, just use the 'other' side.
1098 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1099 return TLO.CombineTo(Op, Op.getOperand(0));
1100 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1101 return TLO.CombineTo(Op, Op.getOperand(1));
1102 // If the RHS is a constant, see if we can simplify it.
1103 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1105 // If the operation can be done in a smaller type, do so.
1106 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1109 // Output known-0 bits are only known if clear in both the LHS & RHS.
1110 KnownZero &= KnownZero2;
1111 // Output known-1 are known to be set if set in either the LHS | RHS.
1112 KnownOne |= KnownOne2;
1115 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1116 KnownOne, TLO, Depth+1))
1118 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1119 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1120 KnownOne2, TLO, Depth+1))
1122 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1124 // If all of the demanded bits are known zero on one side, return the other.
1125 // These bits cannot contribute to the result of the 'xor'.
1126 if ((KnownZero & NewMask) == NewMask)
1127 return TLO.CombineTo(Op, Op.getOperand(0));
1128 if ((KnownZero2 & NewMask) == NewMask)
1129 return TLO.CombineTo(Op, Op.getOperand(1));
1130 // If the operation can be done in a smaller type, do so.
1131 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1134 // If all of the unknown bits are known to be zero on one side or the other
1135 // (but not both) turn this into an *inclusive* or.
1136 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1137 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1138 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1142 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1143 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1144 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1145 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1147 // If all of the demanded bits on one side are known, and all of the set
1148 // bits on that side are also known to be set on the other side, turn this
1149 // into an AND, as we know the bits will be cleared.
1150 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1151 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1152 if ((KnownOne & KnownOne2) == KnownOne) {
1153 EVT VT = Op.getValueType();
1154 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1155 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1156 Op.getOperand(0), ANDC));
1160 // If the RHS is a constant, see if we can simplify it.
1161 // for XOR, we prefer to force bits to 1 if they will make a -1.
1162 // if we can't force bits, try to shrink constant
1163 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1164 APInt Expanded = C->getAPIntValue() | (~NewMask);
1165 // if we can expand it to have all bits set, do it
1166 if (Expanded.isAllOnesValue()) {
1167 if (Expanded != C->getAPIntValue()) {
1168 EVT VT = Op.getValueType();
1169 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1170 TLO.DAG.getConstant(Expanded, VT));
1171 return TLO.CombineTo(Op, New);
1173 // if it already has all the bits set, nothing to change
1174 // but don't shrink either!
1175 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1180 KnownZero = KnownZeroOut;
1181 KnownOne = KnownOneOut;
1184 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1185 KnownOne, TLO, Depth+1))
1187 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1188 KnownOne2, TLO, Depth+1))
1190 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1191 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1193 // If the operands are constants, see if we can simplify them.
1194 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1197 // Only known if known in both the LHS and RHS.
1198 KnownOne &= KnownOne2;
1199 KnownZero &= KnownZero2;
1201 case ISD::SELECT_CC:
1202 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1203 KnownOne, TLO, Depth+1))
1205 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1206 KnownOne2, TLO, Depth+1))
1208 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1209 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1211 // If the operands are constants, see if we can simplify them.
1212 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1215 // Only known if known in both the LHS and RHS.
1216 KnownOne &= KnownOne2;
1217 KnownZero &= KnownZero2;
1220 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1221 unsigned ShAmt = SA->getZExtValue();
1222 SDValue InOp = Op.getOperand(0);
1224 // If the shift count is an invalid immediate, don't do anything.
1225 if (ShAmt >= BitWidth)
1228 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1229 // single shift. We can do this if the bottom bits (which are shifted
1230 // out) are never demanded.
1231 if (InOp.getOpcode() == ISD::SRL &&
1232 isa<ConstantSDNode>(InOp.getOperand(1))) {
1233 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1234 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1235 unsigned Opc = ISD::SHL;
1236 int Diff = ShAmt-C1;
1243 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1244 EVT VT = Op.getValueType();
1245 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1246 InOp.getOperand(0), NewSA));
1250 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1251 KnownZero, KnownOne, TLO, Depth+1))
1253 KnownZero <<= SA->getZExtValue();
1254 KnownOne <<= SA->getZExtValue();
1255 // low bits known zero.
1256 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1260 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1261 EVT VT = Op.getValueType();
1262 unsigned ShAmt = SA->getZExtValue();
1263 unsigned VTSize = VT.getSizeInBits();
1264 SDValue InOp = Op.getOperand(0);
1266 // If the shift count is an invalid immediate, don't do anything.
1267 if (ShAmt >= BitWidth)
1270 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1271 // single shift. We can do this if the top bits (which are shifted out)
1272 // are never demanded.
1273 if (InOp.getOpcode() == ISD::SHL &&
1274 isa<ConstantSDNode>(InOp.getOperand(1))) {
1275 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1276 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1277 unsigned Opc = ISD::SRL;
1278 int Diff = ShAmt-C1;
1285 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1286 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1287 InOp.getOperand(0), NewSA));
1291 // Compute the new bits that are at the top now.
1292 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1293 KnownZero, KnownOne, TLO, Depth+1))
1295 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1296 KnownZero = KnownZero.lshr(ShAmt);
1297 KnownOne = KnownOne.lshr(ShAmt);
1299 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1300 KnownZero |= HighBits; // High bits known zero.
1304 // If this is an arithmetic shift right and only the low-bit is set, we can
1305 // always convert this into a logical shr, even if the shift amount is
1306 // variable. The low bit of the shift cannot be an input sign bit unless
1307 // the shift amount is >= the size of the datatype, which is undefined.
1308 if (DemandedMask == 1)
1309 return TLO.CombineTo(Op,
1310 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1311 Op.getOperand(0), Op.getOperand(1)));
1313 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1314 EVT VT = Op.getValueType();
1315 unsigned ShAmt = SA->getZExtValue();
1317 // If the shift count is an invalid immediate, don't do anything.
1318 if (ShAmt >= BitWidth)
1321 APInt InDemandedMask = (NewMask << ShAmt);
1323 // If any of the demanded bits are produced by the sign extension, we also
1324 // demand the input sign bit.
1325 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1326 if (HighBits.intersects(NewMask))
1327 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1329 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1330 KnownZero, KnownOne, TLO, Depth+1))
1332 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1333 KnownZero = KnownZero.lshr(ShAmt);
1334 KnownOne = KnownOne.lshr(ShAmt);
1336 // Handle the sign bit, adjusted to where it is now in the mask.
1337 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1339 // If the input sign bit is known to be zero, or if none of the top bits
1340 // are demanded, turn this into an unsigned shift right.
1341 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1342 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1345 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1346 KnownOne |= HighBits;
1350 case ISD::SIGN_EXTEND_INREG: {
1351 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1353 // Sign extension. Compute the demanded bits in the result that are not
1354 // present in the input.
1356 APInt::getHighBitsSet(BitWidth,
1357 BitWidth - EVT.getScalarType().getSizeInBits()) &
1360 // If none of the extended bits are demanded, eliminate the sextinreg.
1362 return TLO.CombineTo(Op, Op.getOperand(0));
1364 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
1365 InSignBit.zext(BitWidth);
1366 APInt InputDemandedBits =
1367 APInt::getLowBitsSet(BitWidth,
1368 EVT.getScalarType().getSizeInBits()) &
1371 // Since the sign extended bits are demanded, we know that the sign
1373 InputDemandedBits |= InSignBit;
1375 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1376 KnownZero, KnownOne, TLO, Depth+1))
1378 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1380 // If the sign bit of the input is known set or clear, then we know the
1381 // top bits of the result.
1383 // If the input sign bit is known zero, convert this into a zero extension.
1384 if (KnownZero.intersects(InSignBit))
1385 return TLO.CombineTo(Op,
1386 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1388 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1389 KnownOne |= NewBits;
1390 KnownZero &= ~NewBits;
1391 } else { // Input sign bit unknown
1392 KnownZero &= ~NewBits;
1393 KnownOne &= ~NewBits;
1397 case ISD::ZERO_EXTEND: {
1398 unsigned OperandBitWidth =
1399 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1400 APInt InMask = NewMask;
1401 InMask.trunc(OperandBitWidth);
1403 // If none of the top bits are demanded, convert this into an any_extend.
1405 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1406 if (!NewBits.intersects(NewMask))
1407 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1411 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1412 KnownZero, KnownOne, TLO, Depth+1))
1414 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1415 KnownZero.zext(BitWidth);
1416 KnownOne.zext(BitWidth);
1417 KnownZero |= NewBits;
1420 case ISD::SIGN_EXTEND: {
1421 EVT InVT = Op.getOperand(0).getValueType();
1422 unsigned InBits = InVT.getScalarType().getSizeInBits();
1423 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1424 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1425 APInt NewBits = ~InMask & NewMask;
1427 // If none of the top bits are demanded, convert this into an any_extend.
1429 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1433 // Since some of the sign extended bits are demanded, we know that the sign
1435 APInt InDemandedBits = InMask & NewMask;
1436 InDemandedBits |= InSignBit;
1437 InDemandedBits.trunc(InBits);
1439 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1440 KnownOne, TLO, Depth+1))
1442 KnownZero.zext(BitWidth);
1443 KnownOne.zext(BitWidth);
1445 // If the sign bit is known zero, convert this to a zero extend.
1446 if (KnownZero.intersects(InSignBit))
1447 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1451 // If the sign bit is known one, the top bits match.
1452 if (KnownOne.intersects(InSignBit)) {
1453 KnownOne |= NewBits;
1454 KnownZero &= ~NewBits;
1455 } else { // Otherwise, top bits aren't known.
1456 KnownOne &= ~NewBits;
1457 KnownZero &= ~NewBits;
1461 case ISD::ANY_EXTEND: {
1462 unsigned OperandBitWidth =
1463 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1464 APInt InMask = NewMask;
1465 InMask.trunc(OperandBitWidth);
1466 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1467 KnownZero, KnownOne, TLO, Depth+1))
1469 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1470 KnownZero.zext(BitWidth);
1471 KnownOne.zext(BitWidth);
1474 case ISD::TRUNCATE: {
1475 // Simplify the input, using demanded bit information, and compute the known
1476 // zero/one bits live out.
1477 unsigned OperandBitWidth =
1478 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1479 APInt TruncMask = NewMask;
1480 TruncMask.zext(OperandBitWidth);
1481 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1482 KnownZero, KnownOne, TLO, Depth+1))
1484 KnownZero.trunc(BitWidth);
1485 KnownOne.trunc(BitWidth);
1487 // If the input is only used by this truncate, see if we can shrink it based
1488 // on the known demanded bits.
1489 if (Op.getOperand(0).getNode()->hasOneUse()) {
1490 SDValue In = Op.getOperand(0);
1491 switch (In.getOpcode()) {
1494 // Shrink SRL by a constant if none of the high bits shifted in are
1496 if (TLO.LegalTypes() &&
1497 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1498 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1501 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1504 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1505 OperandBitWidth - BitWidth);
1506 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1507 HighBits.trunc(BitWidth);
1509 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1510 // None of the shifted in bits are needed. Add a truncate of the
1511 // shift input, then shift it.
1512 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1515 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1524 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1527 case ISD::AssertZext: {
1528 // Demand all the bits of the input that are demanded in the output.
1529 // The low bits are obvious; the high bits are demanded because we're
1530 // asserting that they're zero here.
1531 if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
1532 KnownZero, KnownOne, TLO, Depth+1))
1534 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1536 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1537 APInt InMask = APInt::getLowBitsSet(BitWidth,
1538 VT.getSizeInBits());
1539 KnownZero |= ~InMask & NewMask;
1542 case ISD::BIT_CONVERT:
1544 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1545 // is demanded, turn this into a FGETSIGN.
1546 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1547 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1548 !MVT::isVector(Op.getOperand(0).getValueType())) {
1549 // Only do this xform if FGETSIGN is valid or if before legalize.
1550 if (!TLO.AfterLegalize ||
1551 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1552 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1553 // place. We expect the SHL to be eliminated by other optimizations.
1554 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1556 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1557 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1558 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1567 // Add, Sub, and Mul don't demand any bits in positions beyond that
1568 // of the highest bit demanded of them.
1569 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1570 BitWidth - NewMask.countLeadingZeros());
1571 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1572 KnownOne2, TLO, Depth+1))
1574 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1575 KnownOne2, TLO, Depth+1))
1577 // See if the operation should be performed at a smaller bit width.
1578 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1583 // Just use ComputeMaskedBits to compute output bits.
1584 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1588 // If we know the value of all of the demanded bits, return this as a
1590 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1591 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1596 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1597 /// in Mask are known to be either zero or one and return them in the
1598 /// KnownZero/KnownOne bitsets.
1599 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1603 const SelectionDAG &DAG,
1604 unsigned Depth) const {
1605 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1606 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1607 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1608 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1609 "Should use MaskedValueIsZero if you don't know whether Op"
1610 " is a target node!");
1611 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1614 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1615 /// targets that want to expose additional information about sign bits to the
1617 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1618 unsigned Depth) const {
1619 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1620 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1621 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1622 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1623 "Should use ComputeNumSignBits if you don't know whether Op"
1624 " is a target node!");
1628 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1629 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1630 /// determine which bit is set.
1632 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1633 // A left-shift of a constant one will have exactly one bit set, because
1634 // shifting the bit off the end is undefined.
1635 if (Val.getOpcode() == ISD::SHL)
1636 if (ConstantSDNode *C =
1637 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1638 if (C->getAPIntValue() == 1)
1641 // Similarly, a right-shift of a constant sign-bit will have exactly
1643 if (Val.getOpcode() == ISD::SRL)
1644 if (ConstantSDNode *C =
1645 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1646 if (C->getAPIntValue().isSignBit())
1649 // More could be done here, though the above checks are enough
1650 // to handle some common cases.
1652 // Fall back to ComputeMaskedBits to catch other known cases.
1653 EVT OpVT = Val.getValueType();
1654 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1655 APInt Mask = APInt::getAllOnesValue(BitWidth);
1656 APInt KnownZero, KnownOne;
1657 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1658 return (KnownZero.countPopulation() == BitWidth - 1) &&
1659 (KnownOne.countPopulation() == 1);
1662 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1663 /// and cc. If it is unable to simplify it, return a null SDValue.
1665 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1666 ISD::CondCode Cond, bool foldBooleans,
1667 DAGCombinerInfo &DCI, DebugLoc dl) const {
1668 SelectionDAG &DAG = DCI.DAG;
1669 LLVMContext &Context = *DAG.getContext();
1671 // These setcc operations always fold.
1675 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1677 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1680 if (isa<ConstantSDNode>(N0.getNode())) {
1681 // Ensure that the constant occurs on the RHS, and fold constant
1683 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1686 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1687 const APInt &C1 = N1C->getAPIntValue();
1689 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1690 // equality comparison, then we're just comparing whether X itself is
1692 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1693 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1694 N0.getOperand(1).getOpcode() == ISD::Constant) {
1696 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1697 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1698 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1699 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1700 // (srl (ctlz x), 5) == 0 -> X != 0
1701 // (srl (ctlz x), 5) != 1 -> X != 0
1704 // (srl (ctlz x), 5) != 0 -> X == 0
1705 // (srl (ctlz x), 5) == 1 -> X == 0
1708 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1709 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1714 // If the LHS is '(and load, const)', the RHS is 0,
1715 // the test is for equality or unsigned, and all 1 bits of the const are
1716 // in the same partial word, see if we can shorten the load.
1717 if (DCI.isBeforeLegalize() &&
1718 N0.getOpcode() == ISD::AND && C1 == 0 &&
1719 N0.getNode()->hasOneUse() &&
1720 isa<LoadSDNode>(N0.getOperand(0)) &&
1721 N0.getOperand(0).getNode()->hasOneUse() &&
1722 isa<ConstantSDNode>(N0.getOperand(1))) {
1723 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1725 unsigned bestWidth = 0, bestOffset = 0;
1726 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1727 unsigned origWidth = N0.getValueType().getSizeInBits();
1728 unsigned maskWidth = origWidth;
1729 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1730 // 8 bits, but have to be careful...
1731 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1732 origWidth = Lod->getMemoryVT().getSizeInBits();
1734 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1735 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1736 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1737 for (unsigned offset=0; offset<origWidth/width; offset++) {
1738 if ((newMask & Mask) == Mask) {
1739 if (!TD->isLittleEndian())
1740 bestOffset = (origWidth/width - offset - 1) * (width/8);
1742 bestOffset = (uint64_t)offset * (width/8);
1743 bestMask = Mask.lshr(offset * (width/8) * 8);
1747 newMask = newMask << width;
1752 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1753 if (newVT.isRound()) {
1754 EVT PtrType = Lod->getOperand(1).getValueType();
1755 SDValue Ptr = Lod->getBasePtr();
1756 if (bestOffset != 0)
1757 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1758 DAG.getConstant(bestOffset, PtrType));
1759 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1760 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1762 Lod->getSrcValueOffset() + bestOffset,
1763 false, false, NewAlign);
1764 return DAG.getSetCC(dl, VT,
1765 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1766 DAG.getConstant(bestMask.trunc(bestWidth),
1768 DAG.getConstant(0LL, newVT), Cond);
1773 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1774 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1775 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1777 // If the comparison constant has bits in the upper part, the
1778 // zero-extended value could never match.
1779 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1780 C1.getBitWidth() - InSize))) {
1784 case ISD::SETEQ: return DAG.getConstant(0, VT);
1787 case ISD::SETNE: return DAG.getConstant(1, VT);
1790 // True if the sign bit of C1 is set.
1791 return DAG.getConstant(C1.isNegative(), VT);
1794 // True if the sign bit of C1 isn't set.
1795 return DAG.getConstant(C1.isNonNegative(), VT);
1801 // Otherwise, we can perform the comparison with the low bits.
1809 EVT newVT = N0.getOperand(0).getValueType();
1810 if (DCI.isBeforeLegalizeOps() ||
1811 (isOperationLegal(ISD::SETCC, newVT) &&
1812 getCondCodeAction(Cond, newVT)==Legal))
1813 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1814 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1819 break; // todo, be more careful with signed comparisons
1821 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1822 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1823 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1824 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1825 EVT ExtDstTy = N0.getValueType();
1826 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1828 // If the extended part has any inconsistent bits, it cannot ever
1829 // compare equal. In other words, they have to be all ones or all
1832 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1833 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1834 return DAG.getConstant(Cond == ISD::SETNE, VT);
1837 EVT Op0Ty = N0.getOperand(0).getValueType();
1838 if (Op0Ty == ExtSrcTy) {
1839 ZextOp = N0.getOperand(0);
1841 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1842 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1843 DAG.getConstant(Imm, Op0Ty));
1845 if (!DCI.isCalledByLegalizer())
1846 DCI.AddToWorklist(ZextOp.getNode());
1847 // Otherwise, make this a use of a zext.
1848 return DAG.getSetCC(dl, VT, ZextOp,
1849 DAG.getConstant(C1 & APInt::getLowBitsSet(
1854 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1855 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1856 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1857 if (N0.getOpcode() == ISD::SETCC &&
1858 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1859 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1861 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1862 // Invert the condition.
1863 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1864 CC = ISD::getSetCCInverse(CC,
1865 N0.getOperand(0).getValueType().isInteger());
1866 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1869 if ((N0.getOpcode() == ISD::XOR ||
1870 (N0.getOpcode() == ISD::AND &&
1871 N0.getOperand(0).getOpcode() == ISD::XOR &&
1872 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1873 isa<ConstantSDNode>(N0.getOperand(1)) &&
1874 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1875 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1876 // can only do this if the top bits are known zero.
1877 unsigned BitWidth = N0.getValueSizeInBits();
1878 if (DAG.MaskedValueIsZero(N0,
1879 APInt::getHighBitsSet(BitWidth,
1881 // Okay, get the un-inverted input value.
1883 if (N0.getOpcode() == ISD::XOR)
1884 Val = N0.getOperand(0);
1886 assert(N0.getOpcode() == ISD::AND &&
1887 N0.getOperand(0).getOpcode() == ISD::XOR);
1888 // ((X^1)&1)^1 -> X & 1
1889 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1890 N0.getOperand(0).getOperand(0),
1894 return DAG.getSetCC(dl, VT, Val, N1,
1895 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1897 } else if (N1C->getAPIntValue() == 1 &&
1899 getBooleanContents() == ZeroOrOneBooleanContent)) {
1901 if (Op0.getOpcode() == ISD::TRUNCATE)
1902 Op0 = Op0.getOperand(0);
1904 if ((Op0.getOpcode() == ISD::XOR) &&
1905 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1906 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1907 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1908 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1909 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1911 } else if (Op0.getOpcode() == ISD::AND &&
1912 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1913 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1914 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1915 if (Op0.getValueType().bitsGT(VT))
1916 Op0 = DAG.getNode(ISD::AND, dl, VT,
1917 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1918 DAG.getConstant(1, VT));
1919 else if (Op0.getValueType().bitsLT(VT))
1920 Op0 = DAG.getNode(ISD::AND, dl, VT,
1921 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1922 DAG.getConstant(1, VT));
1924 return DAG.getSetCC(dl, VT, Op0,
1925 DAG.getConstant(0, Op0.getValueType()),
1926 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1931 APInt MinVal, MaxVal;
1932 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1933 if (ISD::isSignedIntSetCC(Cond)) {
1934 MinVal = APInt::getSignedMinValue(OperandBitSize);
1935 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1937 MinVal = APInt::getMinValue(OperandBitSize);
1938 MaxVal = APInt::getMaxValue(OperandBitSize);
1941 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1942 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1943 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1944 // X >= C0 --> X > (C0-1)
1945 return DAG.getSetCC(dl, VT, N0,
1946 DAG.getConstant(C1-1, N1.getValueType()),
1947 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1950 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1951 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1952 // X <= C0 --> X < (C0+1)
1953 return DAG.getSetCC(dl, VT, N0,
1954 DAG.getConstant(C1+1, N1.getValueType()),
1955 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1958 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1959 return DAG.getConstant(0, VT); // X < MIN --> false
1960 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1961 return DAG.getConstant(1, VT); // X >= MIN --> true
1962 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1963 return DAG.getConstant(0, VT); // X > MAX --> false
1964 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1965 return DAG.getConstant(1, VT); // X <= MAX --> true
1967 // Canonicalize setgt X, Min --> setne X, Min
1968 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1969 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1970 // Canonicalize setlt X, Max --> setne X, Max
1971 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1972 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1974 // If we have setult X, 1, turn it into seteq X, 0
1975 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1976 return DAG.getSetCC(dl, VT, N0,
1977 DAG.getConstant(MinVal, N0.getValueType()),
1979 // If we have setugt X, Max-1, turn it into seteq X, Max
1980 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1981 return DAG.getSetCC(dl, VT, N0,
1982 DAG.getConstant(MaxVal, N0.getValueType()),
1985 // If we have "setcc X, C0", check to see if we can shrink the immediate
1988 // SETUGT X, SINTMAX -> SETLT X, 0
1989 if (Cond == ISD::SETUGT &&
1990 C1 == APInt::getSignedMaxValue(OperandBitSize))
1991 return DAG.getSetCC(dl, VT, N0,
1992 DAG.getConstant(0, N1.getValueType()),
1995 // SETULT X, SINTMIN -> SETGT X, -1
1996 if (Cond == ISD::SETULT &&
1997 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1998 SDValue ConstMinusOne =
1999 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2001 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2004 // Fold bit comparisons when we can.
2005 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2006 (VT == N0.getValueType() ||
2007 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2008 N0.getOpcode() == ISD::AND)
2009 if (ConstantSDNode *AndRHS =
2010 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2011 EVT ShiftTy = DCI.isBeforeLegalize() ?
2012 getPointerTy() : getShiftAmountTy();
2013 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2014 // Perform the xform if the AND RHS is a single bit.
2015 if (AndRHS->getAPIntValue().isPowerOf2()) {
2016 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2017 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2018 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2020 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2021 // (X & 8) == 8 --> (X & 8) >> 3
2022 // Perform the xform if C1 is a single bit.
2023 if (C1.isPowerOf2()) {
2024 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2025 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2026 DAG.getConstant(C1.logBase2(), ShiftTy)));
2032 if (isa<ConstantFPSDNode>(N0.getNode())) {
2033 // Constant fold or commute setcc.
2034 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2035 if (O.getNode()) return O;
2036 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2037 // If the RHS of an FP comparison is a constant, simplify it away in
2039 if (CFP->getValueAPF().isNaN()) {
2040 // If an operand is known to be a nan, we can fold it.
2041 switch (ISD::getUnorderedFlavor(Cond)) {
2042 default: llvm_unreachable("Unknown flavor!");
2043 case 0: // Known false.
2044 return DAG.getConstant(0, VT);
2045 case 1: // Known true.
2046 return DAG.getConstant(1, VT);
2047 case 2: // Undefined.
2048 return DAG.getUNDEF(VT);
2052 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2053 // constant if knowing that the operand is non-nan is enough. We prefer to
2054 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2056 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2057 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2059 // If the condition is not legal, see if we can find an equivalent one
2061 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2062 // If the comparison was an awkward floating-point == or != and one of
2063 // the comparison operands is infinity or negative infinity, convert the
2064 // condition to a less-awkward <= or >=.
2065 if (CFP->getValueAPF().isInfinity()) {
2066 if (CFP->getValueAPF().isNegative()) {
2067 if (Cond == ISD::SETOEQ &&
2068 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2069 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2070 if (Cond == ISD::SETUEQ &&
2071 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2072 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2073 if (Cond == ISD::SETUNE &&
2074 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2075 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2076 if (Cond == ISD::SETONE &&
2077 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2078 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2080 if (Cond == ISD::SETOEQ &&
2081 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2082 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2083 if (Cond == ISD::SETUEQ &&
2084 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2085 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2086 if (Cond == ISD::SETUNE &&
2087 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2088 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2089 if (Cond == ISD::SETONE &&
2090 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2091 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2098 // We can always fold X == X for integer setcc's.
2099 if (N0.getValueType().isInteger())
2100 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2101 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2102 if (UOF == 2) // FP operators that are undefined on NaNs.
2103 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2104 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2105 return DAG.getConstant(UOF, VT);
2106 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2107 // if it is not already.
2108 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2109 if (NewCond != Cond)
2110 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2113 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2114 N0.getValueType().isInteger()) {
2115 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2116 N0.getOpcode() == ISD::XOR) {
2117 // Simplify (X+Y) == (X+Z) --> Y == Z
2118 if (N0.getOpcode() == N1.getOpcode()) {
2119 if (N0.getOperand(0) == N1.getOperand(0))
2120 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2121 if (N0.getOperand(1) == N1.getOperand(1))
2122 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2123 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2124 // If X op Y == Y op X, try other combinations.
2125 if (N0.getOperand(0) == N1.getOperand(1))
2126 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2128 if (N0.getOperand(1) == N1.getOperand(0))
2129 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2134 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2135 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2136 // Turn (X+C1) == C2 --> X == C2-C1
2137 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2138 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2139 DAG.getConstant(RHSC->getAPIntValue()-
2140 LHSR->getAPIntValue(),
2141 N0.getValueType()), Cond);
2144 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2145 if (N0.getOpcode() == ISD::XOR)
2146 // If we know that all of the inverted bits are zero, don't bother
2147 // performing the inversion.
2148 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2150 DAG.getSetCC(dl, VT, N0.getOperand(0),
2151 DAG.getConstant(LHSR->getAPIntValue() ^
2152 RHSC->getAPIntValue(),
2157 // Turn (C1-X) == C2 --> X == C1-C2
2158 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2159 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2161 DAG.getSetCC(dl, VT, N0.getOperand(1),
2162 DAG.getConstant(SUBC->getAPIntValue() -
2163 RHSC->getAPIntValue(),
2170 // Simplify (X+Z) == X --> Z == 0
2171 if (N0.getOperand(0) == N1)
2172 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2173 DAG.getConstant(0, N0.getValueType()), Cond);
2174 if (N0.getOperand(1) == N1) {
2175 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2176 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2177 DAG.getConstant(0, N0.getValueType()), Cond);
2178 else if (N0.getNode()->hasOneUse()) {
2179 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2180 // (Z-X) == X --> Z == X<<1
2181 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2183 DAG.getConstant(1, getShiftAmountTy()));
2184 if (!DCI.isCalledByLegalizer())
2185 DCI.AddToWorklist(SH.getNode());
2186 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2191 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2192 N1.getOpcode() == ISD::XOR) {
2193 // Simplify X == (X+Z) --> Z == 0
2194 if (N1.getOperand(0) == N0) {
2195 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2196 DAG.getConstant(0, N1.getValueType()), Cond);
2197 } else if (N1.getOperand(1) == N0) {
2198 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2199 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2200 DAG.getConstant(0, N1.getValueType()), Cond);
2201 } else if (N1.getNode()->hasOneUse()) {
2202 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2203 // X == (Z-X) --> X<<1 == Z
2204 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2205 DAG.getConstant(1, getShiftAmountTy()));
2206 if (!DCI.isCalledByLegalizer())
2207 DCI.AddToWorklist(SH.getNode());
2208 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2213 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2214 // Note that where y is variable and is known to have at most
2215 // one bit set (for example, if it is z&1) we cannot do this;
2216 // the expressions are not equivalent when y==0.
2217 if (N0.getOpcode() == ISD::AND)
2218 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2219 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2220 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2221 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2222 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2225 if (N1.getOpcode() == ISD::AND)
2226 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2227 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2228 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2229 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2230 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2235 // Fold away ALL boolean setcc's.
2237 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2239 default: llvm_unreachable("Unknown integer setcc!");
2240 case ISD::SETEQ: // X == Y -> ~(X^Y)
2241 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2242 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2243 if (!DCI.isCalledByLegalizer())
2244 DCI.AddToWorklist(Temp.getNode());
2246 case ISD::SETNE: // X != Y --> (X^Y)
2247 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2249 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2250 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2251 Temp = DAG.getNOT(dl, N0, MVT::i1);
2252 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2253 if (!DCI.isCalledByLegalizer())
2254 DCI.AddToWorklist(Temp.getNode());
2256 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2257 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2258 Temp = DAG.getNOT(dl, N1, MVT::i1);
2259 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2260 if (!DCI.isCalledByLegalizer())
2261 DCI.AddToWorklist(Temp.getNode());
2263 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2264 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2265 Temp = DAG.getNOT(dl, N0, MVT::i1);
2266 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2267 if (!DCI.isCalledByLegalizer())
2268 DCI.AddToWorklist(Temp.getNode());
2270 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2271 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2272 Temp = DAG.getNOT(dl, N1, MVT::i1);
2273 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2276 if (VT != MVT::i1) {
2277 if (!DCI.isCalledByLegalizer())
2278 DCI.AddToWorklist(N0.getNode());
2279 // FIXME: If running after legalize, we probably can't do this.
2280 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2285 // Could not fold it.
2289 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2290 /// node is a GlobalAddress + offset.
2291 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
2292 int64_t &Offset) const {
2293 if (isa<GlobalAddressSDNode>(N)) {
2294 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2295 GA = GASD->getGlobal();
2296 Offset += GASD->getOffset();
2300 if (N->getOpcode() == ISD::ADD) {
2301 SDValue N1 = N->getOperand(0);
2302 SDValue N2 = N->getOperand(1);
2303 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2304 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2306 Offset += V->getSExtValue();
2309 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2310 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2312 Offset += V->getSExtValue();
2321 SDValue TargetLowering::
2322 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2323 // Default implementation: no optimization.
2327 //===----------------------------------------------------------------------===//
2328 // Inline Assembler Implementation Methods
2329 //===----------------------------------------------------------------------===//
2332 TargetLowering::ConstraintType
2333 TargetLowering::getConstraintType(const std::string &Constraint) const {
2334 // FIXME: lots more standard ones to handle.
2335 if (Constraint.size() == 1) {
2336 switch (Constraint[0]) {
2338 case 'r': return C_RegisterClass;
2340 case 'o': // offsetable
2341 case 'V': // not offsetable
2343 case 'i': // Simple Integer or Relocatable Constant
2344 case 'n': // Simple Integer
2345 case 's': // Relocatable Constant
2346 case 'X': // Allow ANY value.
2347 case 'I': // Target registers.
2359 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2360 Constraint[Constraint.size()-1] == '}')
2365 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2366 /// with another that has more specific requirements based on the type of the
2367 /// corresponding operand.
2368 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2369 if (ConstraintVT.isInteger())
2371 if (ConstraintVT.isFloatingPoint())
2372 return "f"; // works for many targets
2376 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2377 /// vector. If it is invalid, don't add anything to Ops.
2378 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2379 char ConstraintLetter,
2380 std::vector<SDValue> &Ops,
2381 SelectionDAG &DAG) const {
2382 switch (ConstraintLetter) {
2384 case 'X': // Allows any operand; labels (basic block) use this.
2385 if (Op.getOpcode() == ISD::BasicBlock) {
2390 case 'i': // Simple Integer or Relocatable Constant
2391 case 'n': // Simple Integer
2392 case 's': { // Relocatable Constant
2393 // These operands are interested in values of the form (GV+C), where C may
2394 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2395 // is possible and fine if either GV or C are missing.
2396 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2397 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2399 // If we have "(add GV, C)", pull out GV/C
2400 if (Op.getOpcode() == ISD::ADD) {
2401 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2402 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2403 if (C == 0 || GA == 0) {
2404 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2405 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2407 if (C == 0 || GA == 0)
2411 // If we find a valid operand, map to the TargetXXX version so that the
2412 // value itself doesn't get selected.
2413 if (GA) { // Either &GV or &GV+C
2414 if (ConstraintLetter != 'n') {
2415 int64_t Offs = GA->getOffset();
2416 if (C) Offs += C->getZExtValue();
2417 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2419 Op.getValueType(), Offs));
2423 if (C) { // just C, no GV.
2424 // Simple constants are not allowed for 's'.
2425 if (ConstraintLetter != 's') {
2426 // gcc prints these as sign extended. Sign extend value to 64 bits
2427 // now; without this it would get ZExt'd later in
2428 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2429 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2439 std::vector<unsigned> TargetLowering::
2440 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2442 return std::vector<unsigned>();
2446 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2447 getRegForInlineAsmConstraint(const std::string &Constraint,
2449 if (Constraint[0] != '{')
2450 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2451 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2453 // Remove the braces from around the name.
2454 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2456 // Figure out which register class contains this reg.
2457 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2458 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2459 E = RI->regclass_end(); RCI != E; ++RCI) {
2460 const TargetRegisterClass *RC = *RCI;
2462 // If none of the value types for this register class are valid, we
2463 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2464 bool isLegal = false;
2465 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2467 if (isTypeLegal(*I)) {
2473 if (!isLegal) continue;
2475 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2477 if (RegName.equals_lower(RI->getName(*I)))
2478 return std::make_pair(*I, RC);
2482 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2485 //===----------------------------------------------------------------------===//
2486 // Constraint Selection.
2488 /// isMatchingInputConstraint - Return true of this is an input operand that is
2489 /// a matching constraint like "4".
2490 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2491 assert(!ConstraintCode.empty() && "No known constraint!");
2492 return isdigit(ConstraintCode[0]);
2495 /// getMatchedOperand - If this is an input matching constraint, this method
2496 /// returns the output operand it matches.
2497 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2498 assert(!ConstraintCode.empty() && "No known constraint!");
2499 return atoi(ConstraintCode.c_str());
2503 /// getConstraintGenerality - Return an integer indicating how general CT
2505 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2507 default: llvm_unreachable("Unknown constraint type!");
2508 case TargetLowering::C_Other:
2509 case TargetLowering::C_Unknown:
2511 case TargetLowering::C_Register:
2513 case TargetLowering::C_RegisterClass:
2515 case TargetLowering::C_Memory:
2520 /// ChooseConstraint - If there are multiple different constraints that we
2521 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2522 /// This is somewhat tricky: constraints fall into four classes:
2523 /// Other -> immediates and magic values
2524 /// Register -> one specific register
2525 /// RegisterClass -> a group of regs
2526 /// Memory -> memory
2527 /// Ideally, we would pick the most specific constraint possible: if we have
2528 /// something that fits into a register, we would pick it. The problem here
2529 /// is that if we have something that could either be in a register or in
2530 /// memory that use of the register could cause selection of *other*
2531 /// operands to fail: they might only succeed if we pick memory. Because of
2532 /// this the heuristic we use is:
2534 /// 1) If there is an 'other' constraint, and if the operand is valid for
2535 /// that constraint, use it. This makes us take advantage of 'i'
2536 /// constraints when available.
2537 /// 2) Otherwise, pick the most general constraint present. This prefers
2538 /// 'm' over 'r', for example.
2540 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2541 const TargetLowering &TLI,
2542 SDValue Op, SelectionDAG *DAG) {
2543 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2544 unsigned BestIdx = 0;
2545 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2546 int BestGenerality = -1;
2548 // Loop over the options, keeping track of the most general one.
2549 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2550 TargetLowering::ConstraintType CType =
2551 TLI.getConstraintType(OpInfo.Codes[i]);
2553 // If this is an 'other' constraint, see if the operand is valid for it.
2554 // For example, on X86 we might have an 'rI' constraint. If the operand
2555 // is an integer in the range [0..31] we want to use I (saving a load
2556 // of a register), otherwise we must use 'r'.
2557 if (CType == TargetLowering::C_Other && Op.getNode()) {
2558 assert(OpInfo.Codes[i].size() == 1 &&
2559 "Unhandled multi-letter 'other' constraint");
2560 std::vector<SDValue> ResultOps;
2561 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
2563 if (!ResultOps.empty()) {
2570 // Things with matching constraints can only be registers, per gcc
2571 // documentation. This mainly affects "g" constraints.
2572 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2575 // This constraint letter is more general than the previous one, use it.
2576 int Generality = getConstraintGenerality(CType);
2577 if (Generality > BestGenerality) {
2580 BestGenerality = Generality;
2584 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2585 OpInfo.ConstraintType = BestType;
2588 /// ComputeConstraintToUse - Determines the constraint code and constraint
2589 /// type to use for the specific AsmOperandInfo, setting
2590 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2591 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2593 SelectionDAG *DAG) const {
2594 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2596 // Single-letter constraints ('r') are very common.
2597 if (OpInfo.Codes.size() == 1) {
2598 OpInfo.ConstraintCode = OpInfo.Codes[0];
2599 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2601 ChooseConstraint(OpInfo, *this, Op, DAG);
2604 // 'X' matches anything.
2605 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2606 // Labels and constants are handled elsewhere ('X' is the only thing
2607 // that matches labels). For Functions, the type here is the type of
2608 // the result, which is not what we want to look at; leave them alone.
2609 Value *v = OpInfo.CallOperandVal;
2610 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2611 OpInfo.CallOperandVal = v;
2615 // Otherwise, try to resolve it to something we know about by looking at
2616 // the actual operand type.
2617 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2618 OpInfo.ConstraintCode = Repl;
2619 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2624 //===----------------------------------------------------------------------===//
2625 // Loop Strength Reduction hooks
2626 //===----------------------------------------------------------------------===//
2628 /// isLegalAddressingMode - Return true if the addressing mode represented
2629 /// by AM is legal for this target, for a load/store of the specified type.
2630 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2631 const Type *Ty) const {
2632 // The default implementation of this implements a conservative RISCy, r+r and
2635 // Allows a sign-extended 16-bit immediate field.
2636 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2639 // No global is ever allowed as a base.
2643 // Only support r+r,
2645 case 0: // "r+i" or just "i", depending on HasBaseReg.
2648 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2650 // Otherwise we have r+r or r+i.
2653 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2655 // Allow 2*r as r+r.
2662 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2663 /// return a DAG expression to select that will generate the same value by
2664 /// multiplying by a magic number. See:
2665 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2666 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2667 std::vector<SDNode*>* Created) const {
2668 EVT VT = N->getValueType(0);
2669 DebugLoc dl= N->getDebugLoc();
2671 // Check to see if we can do this.
2672 // FIXME: We should be more aggressive here.
2673 if (!isTypeLegal(VT))
2676 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2677 APInt::ms magics = d.magic();
2679 // Multiply the numerator (operand 0) by the magic value
2680 // FIXME: We should support doing a MUL in a wider type
2682 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2683 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2684 DAG.getConstant(magics.m, VT));
2685 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2686 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2688 DAG.getConstant(magics.m, VT)).getNode(), 1);
2690 return SDValue(); // No mulhs or equvialent
2691 // If d > 0 and m < 0, add the numerator
2692 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2693 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2695 Created->push_back(Q.getNode());
2697 // If d < 0 and m > 0, subtract the numerator.
2698 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2699 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2701 Created->push_back(Q.getNode());
2703 // Shift right algebraic if shift value is nonzero
2705 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2706 DAG.getConstant(magics.s, getShiftAmountTy()));
2708 Created->push_back(Q.getNode());
2710 // Extract the sign bit and add it to the quotient
2712 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2713 getShiftAmountTy()));
2715 Created->push_back(T.getNode());
2716 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2719 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2720 /// return a DAG expression to select that will generate the same value by
2721 /// multiplying by a magic number. See:
2722 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2723 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2724 std::vector<SDNode*>* Created) const {
2725 EVT VT = N->getValueType(0);
2726 DebugLoc dl = N->getDebugLoc();
2728 // Check to see if we can do this.
2729 // FIXME: We should be more aggressive here.
2730 if (!isTypeLegal(VT))
2733 // FIXME: We should use a narrower constant when the upper
2734 // bits are known to be zero.
2735 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2736 APInt::mu magics = N1C->getAPIntValue().magicu();
2738 // Multiply the numerator (operand 0) by the magic value
2739 // FIXME: We should support doing a MUL in a wider type
2741 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2742 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2743 DAG.getConstant(magics.m, VT));
2744 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2745 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2747 DAG.getConstant(magics.m, VT)).getNode(), 1);
2749 return SDValue(); // No mulhu or equvialent
2751 Created->push_back(Q.getNode());
2753 if (magics.a == 0) {
2754 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2755 "We shouldn't generate an undefined shift!");
2756 return DAG.getNode(ISD::SRL, dl, VT, Q,
2757 DAG.getConstant(magics.s, getShiftAmountTy()));
2759 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2761 Created->push_back(NPQ.getNode());
2762 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2763 DAG.getConstant(1, getShiftAmountTy()));
2765 Created->push_back(NPQ.getNode());
2766 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2768 Created->push_back(NPQ.getNode());
2769 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2770 DAG.getConstant(magics.s-1, getShiftAmountTy()));