1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
33 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
34 bool isLocal = GV->hasLocalLinkage();
35 bool isDeclaration = GV->isDeclaration();
36 // FIXME: what should we do for protected and internal visibility?
37 // For variables, is internal different from hidden?
38 bool isHidden = GV->hasHiddenVisibility();
40 if (reloc == Reloc::PIC_) {
41 if (isLocal || isHidden)
42 return TLSModel::LocalDynamic;
44 return TLSModel::GeneralDynamic;
46 if (!isDeclaration || isHidden)
47 return TLSModel::LocalExec;
49 return TLSModel::InitialExec;
54 /// InitLibcallNames - Set default libcall names.
56 static void InitLibcallNames(const char **Names) {
57 Names[RTLIB::SHL_I16] = "__ashlhi3";
58 Names[RTLIB::SHL_I32] = "__ashlsi3";
59 Names[RTLIB::SHL_I64] = "__ashldi3";
60 Names[RTLIB::SHL_I128] = "__ashlti3";
61 Names[RTLIB::SRL_I16] = "__lshrhi3";
62 Names[RTLIB::SRL_I32] = "__lshrsi3";
63 Names[RTLIB::SRL_I64] = "__lshrdi3";
64 Names[RTLIB::SRL_I128] = "__lshrti3";
65 Names[RTLIB::SRA_I16] = "__ashrhi3";
66 Names[RTLIB::SRA_I32] = "__ashrsi3";
67 Names[RTLIB::SRA_I64] = "__ashrdi3";
68 Names[RTLIB::SRA_I128] = "__ashrti3";
69 Names[RTLIB::MUL_I8] = "__mulqi3";
70 Names[RTLIB::MUL_I16] = "__mulhi3";
71 Names[RTLIB::MUL_I32] = "__mulsi3";
72 Names[RTLIB::MUL_I64] = "__muldi3";
73 Names[RTLIB::MUL_I128] = "__multi3";
74 Names[RTLIB::SDIV_I8] = "__divqi3";
75 Names[RTLIB::SDIV_I16] = "__divhi3";
76 Names[RTLIB::SDIV_I32] = "__divsi3";
77 Names[RTLIB::SDIV_I64] = "__divdi3";
78 Names[RTLIB::SDIV_I128] = "__divti3";
79 Names[RTLIB::UDIV_I8] = "__udivqi3";
80 Names[RTLIB::UDIV_I16] = "__udivhi3";
81 Names[RTLIB::UDIV_I32] = "__udivsi3";
82 Names[RTLIB::UDIV_I64] = "__udivdi3";
83 Names[RTLIB::UDIV_I128] = "__udivti3";
84 Names[RTLIB::SREM_I8] = "__modqi3";
85 Names[RTLIB::SREM_I16] = "__modhi3";
86 Names[RTLIB::SREM_I32] = "__modsi3";
87 Names[RTLIB::SREM_I64] = "__moddi3";
88 Names[RTLIB::SREM_I128] = "__modti3";
89 Names[RTLIB::UREM_I8] = "__umodqi3";
90 Names[RTLIB::UREM_I16] = "__umodhi3";
91 Names[RTLIB::UREM_I32] = "__umodsi3";
92 Names[RTLIB::UREM_I64] = "__umoddi3";
93 Names[RTLIB::UREM_I128] = "__umodti3";
94 Names[RTLIB::NEG_I32] = "__negsi2";
95 Names[RTLIB::NEG_I64] = "__negdi2";
96 Names[RTLIB::ADD_F32] = "__addsf3";
97 Names[RTLIB::ADD_F64] = "__adddf3";
98 Names[RTLIB::ADD_F80] = "__addxf3";
99 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
100 Names[RTLIB::SUB_F32] = "__subsf3";
101 Names[RTLIB::SUB_F64] = "__subdf3";
102 Names[RTLIB::SUB_F80] = "__subxf3";
103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
104 Names[RTLIB::MUL_F32] = "__mulsf3";
105 Names[RTLIB::MUL_F64] = "__muldf3";
106 Names[RTLIB::MUL_F80] = "__mulxf3";
107 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
108 Names[RTLIB::DIV_F32] = "__divsf3";
109 Names[RTLIB::DIV_F64] = "__divdf3";
110 Names[RTLIB::DIV_F80] = "__divxf3";
111 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
112 Names[RTLIB::REM_F32] = "fmodf";
113 Names[RTLIB::REM_F64] = "fmod";
114 Names[RTLIB::REM_F80] = "fmodl";
115 Names[RTLIB::REM_PPCF128] = "fmodl";
116 Names[RTLIB::POWI_F32] = "__powisf2";
117 Names[RTLIB::POWI_F64] = "__powidf2";
118 Names[RTLIB::POWI_F80] = "__powixf2";
119 Names[RTLIB::POWI_PPCF128] = "__powitf2";
120 Names[RTLIB::SQRT_F32] = "sqrtf";
121 Names[RTLIB::SQRT_F64] = "sqrt";
122 Names[RTLIB::SQRT_F80] = "sqrtl";
123 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
124 Names[RTLIB::LOG_F32] = "logf";
125 Names[RTLIB::LOG_F64] = "log";
126 Names[RTLIB::LOG_F80] = "logl";
127 Names[RTLIB::LOG_PPCF128] = "logl";
128 Names[RTLIB::LOG2_F32] = "log2f";
129 Names[RTLIB::LOG2_F64] = "log2";
130 Names[RTLIB::LOG2_F80] = "log2l";
131 Names[RTLIB::LOG2_PPCF128] = "log2l";
132 Names[RTLIB::LOG10_F32] = "log10f";
133 Names[RTLIB::LOG10_F64] = "log10";
134 Names[RTLIB::LOG10_F80] = "log10l";
135 Names[RTLIB::LOG10_PPCF128] = "log10l";
136 Names[RTLIB::EXP_F32] = "expf";
137 Names[RTLIB::EXP_F64] = "exp";
138 Names[RTLIB::EXP_F80] = "expl";
139 Names[RTLIB::EXP_PPCF128] = "expl";
140 Names[RTLIB::EXP2_F32] = "exp2f";
141 Names[RTLIB::EXP2_F64] = "exp2";
142 Names[RTLIB::EXP2_F80] = "exp2l";
143 Names[RTLIB::EXP2_PPCF128] = "exp2l";
144 Names[RTLIB::SIN_F32] = "sinf";
145 Names[RTLIB::SIN_F64] = "sin";
146 Names[RTLIB::SIN_F80] = "sinl";
147 Names[RTLIB::SIN_PPCF128] = "sinl";
148 Names[RTLIB::COS_F32] = "cosf";
149 Names[RTLIB::COS_F64] = "cos";
150 Names[RTLIB::COS_F80] = "cosl";
151 Names[RTLIB::COS_PPCF128] = "cosl";
152 Names[RTLIB::POW_F32] = "powf";
153 Names[RTLIB::POW_F64] = "pow";
154 Names[RTLIB::POW_F80] = "powl";
155 Names[RTLIB::POW_PPCF128] = "powl";
156 Names[RTLIB::CEIL_F32] = "ceilf";
157 Names[RTLIB::CEIL_F64] = "ceil";
158 Names[RTLIB::CEIL_F80] = "ceill";
159 Names[RTLIB::CEIL_PPCF128] = "ceill";
160 Names[RTLIB::TRUNC_F32] = "truncf";
161 Names[RTLIB::TRUNC_F64] = "trunc";
162 Names[RTLIB::TRUNC_F80] = "truncl";
163 Names[RTLIB::TRUNC_PPCF128] = "truncl";
164 Names[RTLIB::RINT_F32] = "rintf";
165 Names[RTLIB::RINT_F64] = "rint";
166 Names[RTLIB::RINT_F80] = "rintl";
167 Names[RTLIB::RINT_PPCF128] = "rintl";
168 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
169 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
170 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
171 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
172 Names[RTLIB::FLOOR_F32] = "floorf";
173 Names[RTLIB::FLOOR_F64] = "floor";
174 Names[RTLIB::FLOOR_F80] = "floorl";
175 Names[RTLIB::FLOOR_PPCF128] = "floorl";
176 Names[RTLIB::COPYSIGN_F32] = "copysignf";
177 Names[RTLIB::COPYSIGN_F64] = "copysign";
178 Names[RTLIB::COPYSIGN_F80] = "copysignl";
179 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
180 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
181 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
182 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
183 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
184 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
185 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
186 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
187 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
188 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
189 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
190 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
191 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
192 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
193 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
194 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
195 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
196 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
197 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
198 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
199 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
200 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
201 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
202 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
203 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
204 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
205 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
206 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
207 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
208 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
209 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
210 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
211 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
212 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
213 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
214 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
215 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
216 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
217 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
218 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
219 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
220 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
221 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
222 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
223 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
224 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
225 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
226 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
227 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
228 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
229 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
230 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
231 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
232 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
233 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
234 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
235 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
236 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
237 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
238 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
239 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
240 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
241 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
242 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
243 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
244 Names[RTLIB::OEQ_F32] = "__eqsf2";
245 Names[RTLIB::OEQ_F64] = "__eqdf2";
246 Names[RTLIB::UNE_F32] = "__nesf2";
247 Names[RTLIB::UNE_F64] = "__nedf2";
248 Names[RTLIB::OGE_F32] = "__gesf2";
249 Names[RTLIB::OGE_F64] = "__gedf2";
250 Names[RTLIB::OLT_F32] = "__ltsf2";
251 Names[RTLIB::OLT_F64] = "__ltdf2";
252 Names[RTLIB::OLE_F32] = "__lesf2";
253 Names[RTLIB::OLE_F64] = "__ledf2";
254 Names[RTLIB::OGT_F32] = "__gtsf2";
255 Names[RTLIB::OGT_F64] = "__gtdf2";
256 Names[RTLIB::UO_F32] = "__unordsf2";
257 Names[RTLIB::UO_F64] = "__unorddf2";
258 Names[RTLIB::O_F32] = "__unordsf2";
259 Names[RTLIB::O_F64] = "__unorddf2";
260 Names[RTLIB::MEMCPY] = "memcpy";
261 Names[RTLIB::MEMMOVE] = "memmove";
262 Names[RTLIB::MEMSET] = "memset";
263 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
264 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
268 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
272 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
273 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
274 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
276 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
277 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
280 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
281 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
282 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
283 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
284 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
285 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
286 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
287 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
288 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
289 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
292 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
293 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
298 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
300 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
301 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
302 CCs[i] = CallingConv::C;
306 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
307 /// UNKNOWN_LIBCALL if there is none.
308 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
309 if (OpVT == MVT::f32) {
310 if (RetVT == MVT::f64)
311 return FPEXT_F32_F64;
314 return UNKNOWN_LIBCALL;
317 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
318 /// UNKNOWN_LIBCALL if there is none.
319 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
320 if (RetVT == MVT::f32) {
321 if (OpVT == MVT::f64)
322 return FPROUND_F64_F32;
323 if (OpVT == MVT::f80)
324 return FPROUND_F80_F32;
325 if (OpVT == MVT::ppcf128)
326 return FPROUND_PPCF128_F32;
327 } else if (RetVT == MVT::f64) {
328 if (OpVT == MVT::f80)
329 return FPROUND_F80_F64;
330 if (OpVT == MVT::ppcf128)
331 return FPROUND_PPCF128_F64;
334 return UNKNOWN_LIBCALL;
337 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
338 /// UNKNOWN_LIBCALL if there is none.
339 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
340 if (OpVT == MVT::f32) {
341 if (RetVT == MVT::i8)
342 return FPTOSINT_F32_I8;
343 if (RetVT == MVT::i16)
344 return FPTOSINT_F32_I16;
345 if (RetVT == MVT::i32)
346 return FPTOSINT_F32_I32;
347 if (RetVT == MVT::i64)
348 return FPTOSINT_F32_I64;
349 if (RetVT == MVT::i128)
350 return FPTOSINT_F32_I128;
351 } else if (OpVT == MVT::f64) {
352 if (RetVT == MVT::i8)
353 return FPTOSINT_F64_I8;
354 if (RetVT == MVT::i16)
355 return FPTOSINT_F64_I16;
356 if (RetVT == MVT::i32)
357 return FPTOSINT_F64_I32;
358 if (RetVT == MVT::i64)
359 return FPTOSINT_F64_I64;
360 if (RetVT == MVT::i128)
361 return FPTOSINT_F64_I128;
362 } else if (OpVT == MVT::f80) {
363 if (RetVT == MVT::i32)
364 return FPTOSINT_F80_I32;
365 if (RetVT == MVT::i64)
366 return FPTOSINT_F80_I64;
367 if (RetVT == MVT::i128)
368 return FPTOSINT_F80_I128;
369 } else if (OpVT == MVT::ppcf128) {
370 if (RetVT == MVT::i32)
371 return FPTOSINT_PPCF128_I32;
372 if (RetVT == MVT::i64)
373 return FPTOSINT_PPCF128_I64;
374 if (RetVT == MVT::i128)
375 return FPTOSINT_PPCF128_I128;
377 return UNKNOWN_LIBCALL;
380 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
381 /// UNKNOWN_LIBCALL if there is none.
382 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
383 if (OpVT == MVT::f32) {
384 if (RetVT == MVT::i8)
385 return FPTOUINT_F32_I8;
386 if (RetVT == MVT::i16)
387 return FPTOUINT_F32_I16;
388 if (RetVT == MVT::i32)
389 return FPTOUINT_F32_I32;
390 if (RetVT == MVT::i64)
391 return FPTOUINT_F32_I64;
392 if (RetVT == MVT::i128)
393 return FPTOUINT_F32_I128;
394 } else if (OpVT == MVT::f64) {
395 if (RetVT == MVT::i8)
396 return FPTOUINT_F64_I8;
397 if (RetVT == MVT::i16)
398 return FPTOUINT_F64_I16;
399 if (RetVT == MVT::i32)
400 return FPTOUINT_F64_I32;
401 if (RetVT == MVT::i64)
402 return FPTOUINT_F64_I64;
403 if (RetVT == MVT::i128)
404 return FPTOUINT_F64_I128;
405 } else if (OpVT == MVT::f80) {
406 if (RetVT == MVT::i32)
407 return FPTOUINT_F80_I32;
408 if (RetVT == MVT::i64)
409 return FPTOUINT_F80_I64;
410 if (RetVT == MVT::i128)
411 return FPTOUINT_F80_I128;
412 } else if (OpVT == MVT::ppcf128) {
413 if (RetVT == MVT::i32)
414 return FPTOUINT_PPCF128_I32;
415 if (RetVT == MVT::i64)
416 return FPTOUINT_PPCF128_I64;
417 if (RetVT == MVT::i128)
418 return FPTOUINT_PPCF128_I128;
420 return UNKNOWN_LIBCALL;
423 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
424 /// UNKNOWN_LIBCALL if there is none.
425 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
426 if (OpVT == MVT::i32) {
427 if (RetVT == MVT::f32)
428 return SINTTOFP_I32_F32;
429 else if (RetVT == MVT::f64)
430 return SINTTOFP_I32_F64;
431 else if (RetVT == MVT::f80)
432 return SINTTOFP_I32_F80;
433 else if (RetVT == MVT::ppcf128)
434 return SINTTOFP_I32_PPCF128;
435 } else if (OpVT == MVT::i64) {
436 if (RetVT == MVT::f32)
437 return SINTTOFP_I64_F32;
438 else if (RetVT == MVT::f64)
439 return SINTTOFP_I64_F64;
440 else if (RetVT == MVT::f80)
441 return SINTTOFP_I64_F80;
442 else if (RetVT == MVT::ppcf128)
443 return SINTTOFP_I64_PPCF128;
444 } else if (OpVT == MVT::i128) {
445 if (RetVT == MVT::f32)
446 return SINTTOFP_I128_F32;
447 else if (RetVT == MVT::f64)
448 return SINTTOFP_I128_F64;
449 else if (RetVT == MVT::f80)
450 return SINTTOFP_I128_F80;
451 else if (RetVT == MVT::ppcf128)
452 return SINTTOFP_I128_PPCF128;
454 return UNKNOWN_LIBCALL;
457 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
458 /// UNKNOWN_LIBCALL if there is none.
459 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
460 if (OpVT == MVT::i32) {
461 if (RetVT == MVT::f32)
462 return UINTTOFP_I32_F32;
463 else if (RetVT == MVT::f64)
464 return UINTTOFP_I32_F64;
465 else if (RetVT == MVT::f80)
466 return UINTTOFP_I32_F80;
467 else if (RetVT == MVT::ppcf128)
468 return UINTTOFP_I32_PPCF128;
469 } else if (OpVT == MVT::i64) {
470 if (RetVT == MVT::f32)
471 return UINTTOFP_I64_F32;
472 else if (RetVT == MVT::f64)
473 return UINTTOFP_I64_F64;
474 else if (RetVT == MVT::f80)
475 return UINTTOFP_I64_F80;
476 else if (RetVT == MVT::ppcf128)
477 return UINTTOFP_I64_PPCF128;
478 } else if (OpVT == MVT::i128) {
479 if (RetVT == MVT::f32)
480 return UINTTOFP_I128_F32;
481 else if (RetVT == MVT::f64)
482 return UINTTOFP_I128_F64;
483 else if (RetVT == MVT::f80)
484 return UINTTOFP_I128_F80;
485 else if (RetVT == MVT::ppcf128)
486 return UINTTOFP_I128_PPCF128;
488 return UNKNOWN_LIBCALL;
491 /// InitCmpLibcallCCs - Set default comparison libcall CC.
493 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
494 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
495 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
496 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
497 CCs[RTLIB::UNE_F32] = ISD::SETNE;
498 CCs[RTLIB::UNE_F64] = ISD::SETNE;
499 CCs[RTLIB::OGE_F32] = ISD::SETGE;
500 CCs[RTLIB::OGE_F64] = ISD::SETGE;
501 CCs[RTLIB::OLT_F32] = ISD::SETLT;
502 CCs[RTLIB::OLT_F64] = ISD::SETLT;
503 CCs[RTLIB::OLE_F32] = ISD::SETLE;
504 CCs[RTLIB::OLE_F64] = ISD::SETLE;
505 CCs[RTLIB::OGT_F32] = ISD::SETGT;
506 CCs[RTLIB::OGT_F64] = ISD::SETGT;
507 CCs[RTLIB::UO_F32] = ISD::SETNE;
508 CCs[RTLIB::UO_F64] = ISD::SETNE;
509 CCs[RTLIB::O_F32] = ISD::SETEQ;
510 CCs[RTLIB::O_F64] = ISD::SETEQ;
513 /// NOTE: The constructor takes ownership of TLOF.
514 TargetLowering::TargetLowering(const TargetMachine &tm,
515 const TargetLoweringObjectFile *tlof)
516 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
517 // All operations default to being supported.
518 memset(OpActions, 0, sizeof(OpActions));
519 memset(LoadExtActions, 0, sizeof(LoadExtActions));
520 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
521 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
522 memset(CondCodeActions, 0, sizeof(CondCodeActions));
524 // Set default actions for various operations.
525 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
526 // Default all indexed load / store to expand.
527 for (unsigned IM = (unsigned)ISD::PRE_INC;
528 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
529 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
530 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
533 // These operations default to expand.
534 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
538 // Most targets ignore the @llvm.prefetch intrinsic.
539 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
541 // ConstantFP nodes default to expand. Targets can either change this to
542 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
543 // to optimize expansions for certain constants.
544 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
545 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
546 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
548 // These library functions default to expand.
549 setOperationAction(ISD::FLOG , MVT::f64, Expand);
550 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
551 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
552 setOperationAction(ISD::FEXP , MVT::f64, Expand);
553 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
554 setOperationAction(ISD::FLOG , MVT::f32, Expand);
555 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
556 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
557 setOperationAction(ISD::FEXP , MVT::f32, Expand);
558 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
560 // Default ISD::TRAP to expand (which turns it into abort).
561 setOperationAction(ISD::TRAP, MVT::Other, Expand);
563 IsLittleEndian = TD->isLittleEndian();
564 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
565 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
566 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
567 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
568 benefitFromCodePlacementOpt = false;
569 UseUnderscoreSetJmp = false;
570 UseUnderscoreLongJmp = false;
571 SelectIsExpensive = false;
572 IntDivIsCheap = false;
573 Pow2DivIsCheap = false;
574 StackPointerRegisterToSaveRestore = 0;
575 ExceptionPointerRegister = 0;
576 ExceptionSelectorRegister = 0;
577 BooleanContents = UndefinedBooleanContent;
578 SchedPreferenceInfo = Sched::Latency;
580 JumpBufAlignment = 0;
581 IfCvtBlockSizeLimit = 2;
582 IfCvtDupBlockSizeLimit = 0;
583 PrefLoopAlignment = 0;
584 ShouldFoldAtomicFences = false;
586 InitLibcallNames(LibcallRoutineNames);
587 InitCmpLibcallCCs(CmpLibcallCCs);
588 InitLibcallCallingConvs(LibcallCallingConvs);
591 TargetLowering::~TargetLowering() {
595 /// canOpTrap - Returns true if the operation can trap for the value type.
596 /// VT must be a legal type.
597 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
598 assert(isTypeLegal(VT));
613 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
614 unsigned &NumIntermediates,
616 TargetLowering* TLI) {
617 // Figure out the right, legal destination reg to copy into.
618 unsigned NumElts = VT.getVectorNumElements();
619 MVT EltTy = VT.getVectorElementType();
621 unsigned NumVectorRegs = 1;
623 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
624 // could break down into LHS/RHS like LegalizeDAG does.
625 if (!isPowerOf2_32(NumElts)) {
626 NumVectorRegs = NumElts;
630 // Divide the input until we get to a supported size. This will always
631 // end with a scalar if the target doesn't support vectors.
632 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
637 NumIntermediates = NumVectorRegs;
639 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
640 if (!TLI->isTypeLegal(NewVT))
642 IntermediateVT = NewVT;
644 EVT DestVT = TLI->getRegisterType(NewVT);
646 if (EVT(DestVT).bitsLT(NewVT)) {
647 // Value is expanded, e.g. i64 -> i16.
648 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
650 // Otherwise, promotion or legal types use the same number of registers as
651 // the vector decimated to the appropriate level.
652 return NumVectorRegs;
658 /// computeRegisterProperties - Once all of the register classes are added,
659 /// this allows us to compute derived properties we expose.
660 void TargetLowering::computeRegisterProperties() {
661 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
662 "Too many value types for ValueTypeActions to hold!");
664 // Everything defaults to needing one register.
665 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
666 NumRegistersForVT[i] = 1;
667 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
669 // ...except isVoid, which doesn't need any registers.
670 NumRegistersForVT[MVT::isVoid] = 0;
672 // Find the largest integer register class.
673 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
674 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
675 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
677 // Every integer value type larger than this largest register takes twice as
678 // many registers to represent as the previous ValueType.
679 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
680 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
681 if (!ExpandedVT.isInteger())
683 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
684 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
685 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
686 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
689 // Inspect all of the ValueType's smaller than the largest integer
690 // register to see which ones need promotion.
691 unsigned LegalIntReg = LargestIntReg;
692 for (unsigned IntReg = LargestIntReg - 1;
693 IntReg >= (unsigned)MVT::i1; --IntReg) {
694 EVT IVT = (MVT::SimpleValueType)IntReg;
695 if (isTypeLegal(IVT)) {
696 LegalIntReg = IntReg;
698 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
699 (MVT::SimpleValueType)LegalIntReg;
700 ValueTypeActions.setTypeAction(IVT, Promote);
704 // ppcf128 type is really two f64's.
705 if (!isTypeLegal(MVT::ppcf128)) {
706 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
707 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
708 TransformToType[MVT::ppcf128] = MVT::f64;
709 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
712 // Decide how to handle f64. If the target does not have native f64 support,
713 // expand it to i64 and we will be generating soft float library calls.
714 if (!isTypeLegal(MVT::f64)) {
715 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
716 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
717 TransformToType[MVT::f64] = MVT::i64;
718 ValueTypeActions.setTypeAction(MVT::f64, Expand);
721 // Decide how to handle f32. If the target does not have native support for
722 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
723 if (!isTypeLegal(MVT::f32)) {
724 if (isTypeLegal(MVT::f64)) {
725 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
726 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
727 TransformToType[MVT::f32] = MVT::f64;
728 ValueTypeActions.setTypeAction(MVT::f32, Promote);
730 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
731 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
732 TransformToType[MVT::f32] = MVT::i32;
733 ValueTypeActions.setTypeAction(MVT::f32, Expand);
737 // Loop over all of the vector value types to see which need transformations.
738 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
739 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
740 MVT VT = (MVT::SimpleValueType)i;
741 if (!isTypeLegal(VT)) {
744 unsigned NumIntermediates;
745 NumRegistersForVT[i] =
746 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
748 RegisterTypeForVT[i] = RegisterVT;
750 // Determine if there is a legal wider type.
751 bool IsLegalWiderType = false;
752 EVT EltVT = VT.getVectorElementType();
753 unsigned NElts = VT.getVectorNumElements();
754 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
755 EVT SVT = (MVT::SimpleValueType)nVT;
756 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
757 SVT.getVectorNumElements() > NElts && NElts != 1) {
758 TransformToType[i] = SVT;
759 ValueTypeActions.setTypeAction(VT, Promote);
760 IsLegalWiderType = true;
764 if (!IsLegalWiderType) {
765 EVT NVT = VT.getPow2VectorType();
767 // Type is already a power of 2. The default action is to split.
768 TransformToType[i] = MVT::Other;
769 ValueTypeActions.setTypeAction(VT, Expand);
771 TransformToType[i] = NVT;
772 ValueTypeActions.setTypeAction(VT, Promote);
779 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
784 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
785 return PointerTy.SimpleTy;
788 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
789 return MVT::i32; // return the default value
792 /// getVectorTypeBreakdown - Vector types are broken down into some number of
793 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
794 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
795 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
797 /// This method returns the number of registers needed, and the VT for each
798 /// register. It also returns the VT and quantity of the intermediate values
799 /// before they are promoted/expanded.
801 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
803 unsigned &NumIntermediates,
804 EVT &RegisterVT) const {
805 // Figure out the right, legal destination reg to copy into.
806 unsigned NumElts = VT.getVectorNumElements();
807 EVT EltTy = VT.getVectorElementType();
809 unsigned NumVectorRegs = 1;
811 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
812 // could break down into LHS/RHS like LegalizeDAG does.
813 if (!isPowerOf2_32(NumElts)) {
814 NumVectorRegs = NumElts;
818 // Divide the input until we get to a supported size. This will always
819 // end with a scalar if the target doesn't support vectors.
820 while (NumElts > 1 && !isTypeLegal(
821 EVT::getVectorVT(Context, EltTy, NumElts))) {
826 NumIntermediates = NumVectorRegs;
828 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
829 if (!isTypeLegal(NewVT))
831 IntermediateVT = NewVT;
833 EVT DestVT = getRegisterType(Context, NewVT);
835 if (DestVT.bitsLT(NewVT)) {
836 // Value is expanded, e.g. i64 -> i16.
837 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
839 // Otherwise, promotion or legal types use the same number of registers as
840 // the vector decimated to the appropriate level.
841 return NumVectorRegs;
847 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
848 /// function arguments in the caller parameter area. This is the actual
849 /// alignment, not its logarithm.
850 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
851 return TD->getCallFrameTypeAlignment(Ty);
854 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
855 /// current function. The returned value is a member of the
856 /// MachineJumpTableInfo::JTEntryKind enum.
857 unsigned TargetLowering::getJumpTableEncoding() const {
858 // In non-pic modes, just use the address of a block.
859 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
860 return MachineJumpTableInfo::EK_BlockAddress;
862 // In PIC mode, if the target supports a GPRel32 directive, use it.
863 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
864 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
866 // Otherwise, use a label difference.
867 return MachineJumpTableInfo::EK_LabelDifference32;
870 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
871 SelectionDAG &DAG) const {
872 // If our PIC model is GP relative, use the global offset table as the base.
873 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
874 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
878 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
879 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
882 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
883 unsigned JTI,MCContext &Ctx) const{
884 // The normal PIC reloc base is the label at the start of the jump table.
885 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
889 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
890 // Assume that everything is safe in static mode.
891 if (getTargetMachine().getRelocationModel() == Reloc::Static)
894 // In dynamic-no-pic mode, assume that known defined values are safe.
895 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
897 !GA->getGlobal()->isDeclaration() &&
898 !GA->getGlobal()->isWeakForLinker())
901 // Otherwise assume nothing is safe.
905 //===----------------------------------------------------------------------===//
906 // Optimization Methods
907 //===----------------------------------------------------------------------===//
909 /// ShrinkDemandedConstant - Check to see if the specified operand of the
910 /// specified instruction is a constant integer. If so, check to see if there
911 /// are any bits set in the constant that are not demanded. If so, shrink the
912 /// constant and return true.
913 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
914 const APInt &Demanded) {
915 DebugLoc dl = Op.getDebugLoc();
917 // FIXME: ISD::SELECT, ISD::SELECT_CC
918 switch (Op.getOpcode()) {
923 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
924 if (!C) return false;
926 if (Op.getOpcode() == ISD::XOR &&
927 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
930 // if we can expand it to have all bits set, do it
931 if (C->getAPIntValue().intersects(~Demanded)) {
932 EVT VT = Op.getValueType();
933 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
934 DAG.getConstant(Demanded &
937 return CombineTo(Op, New);
947 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
948 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
949 /// cast, but it could be generalized for targets with other types of
950 /// implicit widening casts.
952 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
954 const APInt &Demanded,
956 assert(Op.getNumOperands() == 2 &&
957 "ShrinkDemandedOp only supports binary operators!");
958 assert(Op.getNode()->getNumValues() == 1 &&
959 "ShrinkDemandedOp only supports nodes with one result!");
961 // Don't do this if the node has another user, which may require the
963 if (!Op.getNode()->hasOneUse())
966 // Search for the smallest integer type with free casts to and from
967 // Op's type. For expedience, just check power-of-2 integer types.
968 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
969 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
970 if (!isPowerOf2_32(SmallVTBits))
971 SmallVTBits = NextPowerOf2(SmallVTBits);
972 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
973 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
974 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
975 TLI.isZExtFree(SmallVT, Op.getValueType())) {
976 // We found a type with free casts.
977 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
978 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
979 Op.getNode()->getOperand(0)),
980 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
981 Op.getNode()->getOperand(1)));
982 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
983 return CombineTo(Op, Z);
989 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
990 /// DemandedMask bits of the result of Op are ever used downstream. If we can
991 /// use this information to simplify Op, create a new simplified DAG node and
992 /// return true, returning the original and new nodes in Old and New. Otherwise,
993 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
994 /// the expression (used to simplify the caller). The KnownZero/One bits may
995 /// only be accurate for those bits in the DemandedMask.
996 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
997 const APInt &DemandedMask,
1000 TargetLoweringOpt &TLO,
1001 unsigned Depth) const {
1002 unsigned BitWidth = DemandedMask.getBitWidth();
1003 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1004 "Mask size mismatches value type size!");
1005 APInt NewMask = DemandedMask;
1006 DebugLoc dl = Op.getDebugLoc();
1008 // Don't know anything.
1009 KnownZero = KnownOne = APInt(BitWidth, 0);
1011 // Other users may use these bits.
1012 if (!Op.getNode()->hasOneUse()) {
1014 // If not at the root, Just compute the KnownZero/KnownOne bits to
1015 // simplify things downstream.
1016 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
1019 // If this is the root being simplified, allow it to have multiple uses,
1020 // just set the NewMask to all bits.
1021 NewMask = APInt::getAllOnesValue(BitWidth);
1022 } else if (DemandedMask == 0) {
1023 // Not demanding any bits from Op.
1024 if (Op.getOpcode() != ISD::UNDEF)
1025 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1027 } else if (Depth == 6) { // Limit search depth.
1031 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1032 switch (Op.getOpcode()) {
1034 // We know all of the bits for a constant!
1035 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1036 KnownZero = ~KnownOne & NewMask;
1037 return false; // Don't fall through, will infinitely loop.
1039 // If the RHS is a constant, check to see if the LHS would be zero without
1040 // using the bits from the RHS. Below, we use knowledge about the RHS to
1041 // simplify the LHS, here we're using information from the LHS to simplify
1043 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1044 APInt LHSZero, LHSOne;
1045 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
1046 LHSZero, LHSOne, Depth+1);
1047 // If the LHS already has zeros where RHSC does, this and is dead.
1048 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1049 return TLO.CombineTo(Op, Op.getOperand(0));
1050 // If any of the set bits in the RHS are known zero on the LHS, shrink
1052 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1056 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1057 KnownOne, TLO, Depth+1))
1059 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1060 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1061 KnownZero2, KnownOne2, TLO, Depth+1))
1063 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1065 // If all of the demanded bits are known one on one side, return the other.
1066 // These bits cannot contribute to the result of the 'and'.
1067 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1068 return TLO.CombineTo(Op, Op.getOperand(0));
1069 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1070 return TLO.CombineTo(Op, Op.getOperand(1));
1071 // If all of the demanded bits in the inputs are known zeros, return zero.
1072 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1073 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1074 // If the RHS is a constant, see if we can simplify it.
1075 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1077 // If the operation can be done in a smaller type, do so.
1078 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1081 // Output known-1 bits are only known if set in both the LHS & RHS.
1082 KnownOne &= KnownOne2;
1083 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1084 KnownZero |= KnownZero2;
1087 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1088 KnownOne, TLO, Depth+1))
1090 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1091 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1092 KnownZero2, KnownOne2, TLO, Depth+1))
1094 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1096 // If all of the demanded bits are known zero on one side, return the other.
1097 // These bits cannot contribute to the result of the 'or'.
1098 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1099 return TLO.CombineTo(Op, Op.getOperand(0));
1100 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1101 return TLO.CombineTo(Op, Op.getOperand(1));
1102 // If all of the potentially set bits on one side are known to be set on
1103 // the other side, just use the 'other' side.
1104 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1105 return TLO.CombineTo(Op, Op.getOperand(0));
1106 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1107 return TLO.CombineTo(Op, Op.getOperand(1));
1108 // If the RHS is a constant, see if we can simplify it.
1109 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1111 // If the operation can be done in a smaller type, do so.
1112 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1115 // Output known-0 bits are only known if clear in both the LHS & RHS.
1116 KnownZero &= KnownZero2;
1117 // Output known-1 are known to be set if set in either the LHS | RHS.
1118 KnownOne |= KnownOne2;
1121 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1122 KnownOne, TLO, Depth+1))
1124 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1125 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1126 KnownOne2, TLO, Depth+1))
1128 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1130 // If all of the demanded bits are known zero on one side, return the other.
1131 // These bits cannot contribute to the result of the 'xor'.
1132 if ((KnownZero & NewMask) == NewMask)
1133 return TLO.CombineTo(Op, Op.getOperand(0));
1134 if ((KnownZero2 & NewMask) == NewMask)
1135 return TLO.CombineTo(Op, Op.getOperand(1));
1136 // If the operation can be done in a smaller type, do so.
1137 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1140 // If all of the unknown bits are known to be zero on one side or the other
1141 // (but not both) turn this into an *inclusive* or.
1142 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1143 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1144 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1148 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1149 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1150 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1151 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1153 // If all of the demanded bits on one side are known, and all of the set
1154 // bits on that side are also known to be set on the other side, turn this
1155 // into an AND, as we know the bits will be cleared.
1156 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1157 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1158 if ((KnownOne & KnownOne2) == KnownOne) {
1159 EVT VT = Op.getValueType();
1160 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1161 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1162 Op.getOperand(0), ANDC));
1166 // If the RHS is a constant, see if we can simplify it.
1167 // for XOR, we prefer to force bits to 1 if they will make a -1.
1168 // if we can't force bits, try to shrink constant
1169 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1170 APInt Expanded = C->getAPIntValue() | (~NewMask);
1171 // if we can expand it to have all bits set, do it
1172 if (Expanded.isAllOnesValue()) {
1173 if (Expanded != C->getAPIntValue()) {
1174 EVT VT = Op.getValueType();
1175 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1176 TLO.DAG.getConstant(Expanded, VT));
1177 return TLO.CombineTo(Op, New);
1179 // if it already has all the bits set, nothing to change
1180 // but don't shrink either!
1181 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1186 KnownZero = KnownZeroOut;
1187 KnownOne = KnownOneOut;
1190 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1191 KnownOne, TLO, Depth+1))
1193 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1194 KnownOne2, TLO, Depth+1))
1196 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1197 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1199 // If the operands are constants, see if we can simplify them.
1200 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1203 // Only known if known in both the LHS and RHS.
1204 KnownOne &= KnownOne2;
1205 KnownZero &= KnownZero2;
1207 case ISD::SELECT_CC:
1208 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1209 KnownOne, TLO, Depth+1))
1211 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1212 KnownOne2, TLO, Depth+1))
1214 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1215 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1217 // If the operands are constants, see if we can simplify them.
1218 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1221 // Only known if known in both the LHS and RHS.
1222 KnownOne &= KnownOne2;
1223 KnownZero &= KnownZero2;
1226 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1227 unsigned ShAmt = SA->getZExtValue();
1228 SDValue InOp = Op.getOperand(0);
1230 // If the shift count is an invalid immediate, don't do anything.
1231 if (ShAmt >= BitWidth)
1234 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1235 // single shift. We can do this if the bottom bits (which are shifted
1236 // out) are never demanded.
1237 if (InOp.getOpcode() == ISD::SRL &&
1238 isa<ConstantSDNode>(InOp.getOperand(1))) {
1239 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1240 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1241 unsigned Opc = ISD::SHL;
1242 int Diff = ShAmt-C1;
1249 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1250 EVT VT = Op.getValueType();
1251 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1252 InOp.getOperand(0), NewSA));
1256 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1257 KnownZero, KnownOne, TLO, Depth+1))
1259 KnownZero <<= SA->getZExtValue();
1260 KnownOne <<= SA->getZExtValue();
1261 // low bits known zero.
1262 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1266 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1267 EVT VT = Op.getValueType();
1268 unsigned ShAmt = SA->getZExtValue();
1269 unsigned VTSize = VT.getSizeInBits();
1270 SDValue InOp = Op.getOperand(0);
1272 // If the shift count is an invalid immediate, don't do anything.
1273 if (ShAmt >= BitWidth)
1276 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1277 // single shift. We can do this if the top bits (which are shifted out)
1278 // are never demanded.
1279 if (InOp.getOpcode() == ISD::SHL &&
1280 isa<ConstantSDNode>(InOp.getOperand(1))) {
1281 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1282 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1283 unsigned Opc = ISD::SRL;
1284 int Diff = ShAmt-C1;
1291 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1292 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1293 InOp.getOperand(0), NewSA));
1297 // Compute the new bits that are at the top now.
1298 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1299 KnownZero, KnownOne, TLO, Depth+1))
1301 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1302 KnownZero = KnownZero.lshr(ShAmt);
1303 KnownOne = KnownOne.lshr(ShAmt);
1305 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1306 KnownZero |= HighBits; // High bits known zero.
1310 // If this is an arithmetic shift right and only the low-bit is set, we can
1311 // always convert this into a logical shr, even if the shift amount is
1312 // variable. The low bit of the shift cannot be an input sign bit unless
1313 // the shift amount is >= the size of the datatype, which is undefined.
1314 if (DemandedMask == 1)
1315 return TLO.CombineTo(Op,
1316 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1317 Op.getOperand(0), Op.getOperand(1)));
1319 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1320 EVT VT = Op.getValueType();
1321 unsigned ShAmt = SA->getZExtValue();
1323 // If the shift count is an invalid immediate, don't do anything.
1324 if (ShAmt >= BitWidth)
1327 APInt InDemandedMask = (NewMask << ShAmt);
1329 // If any of the demanded bits are produced by the sign extension, we also
1330 // demand the input sign bit.
1331 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1332 if (HighBits.intersects(NewMask))
1333 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1335 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1336 KnownZero, KnownOne, TLO, Depth+1))
1338 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1339 KnownZero = KnownZero.lshr(ShAmt);
1340 KnownOne = KnownOne.lshr(ShAmt);
1342 // Handle the sign bit, adjusted to where it is now in the mask.
1343 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1345 // If the input sign bit is known to be zero, or if none of the top bits
1346 // are demanded, turn this into an unsigned shift right.
1347 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1348 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1351 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1352 KnownOne |= HighBits;
1356 case ISD::SIGN_EXTEND_INREG: {
1357 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1359 // Sign extension. Compute the demanded bits in the result that are not
1360 // present in the input.
1362 APInt::getHighBitsSet(BitWidth,
1363 BitWidth - EVT.getScalarType().getSizeInBits()) &
1366 // If none of the extended bits are demanded, eliminate the sextinreg.
1368 return TLO.CombineTo(Op, Op.getOperand(0));
1370 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
1371 InSignBit.zext(BitWidth);
1372 APInt InputDemandedBits =
1373 APInt::getLowBitsSet(BitWidth,
1374 EVT.getScalarType().getSizeInBits()) &
1377 // Since the sign extended bits are demanded, we know that the sign
1379 InputDemandedBits |= InSignBit;
1381 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1382 KnownZero, KnownOne, TLO, Depth+1))
1384 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1386 // If the sign bit of the input is known set or clear, then we know the
1387 // top bits of the result.
1389 // If the input sign bit is known zero, convert this into a zero extension.
1390 if (KnownZero.intersects(InSignBit))
1391 return TLO.CombineTo(Op,
1392 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1394 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1395 KnownOne |= NewBits;
1396 KnownZero &= ~NewBits;
1397 } else { // Input sign bit unknown
1398 KnownZero &= ~NewBits;
1399 KnownOne &= ~NewBits;
1403 case ISD::ZERO_EXTEND: {
1404 unsigned OperandBitWidth =
1405 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1406 APInt InMask = NewMask;
1407 InMask.trunc(OperandBitWidth);
1409 // If none of the top bits are demanded, convert this into an any_extend.
1411 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1412 if (!NewBits.intersects(NewMask))
1413 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1417 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1418 KnownZero, KnownOne, TLO, Depth+1))
1420 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1421 KnownZero.zext(BitWidth);
1422 KnownOne.zext(BitWidth);
1423 KnownZero |= NewBits;
1426 case ISD::SIGN_EXTEND: {
1427 EVT InVT = Op.getOperand(0).getValueType();
1428 unsigned InBits = InVT.getScalarType().getSizeInBits();
1429 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1430 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1431 APInt NewBits = ~InMask & NewMask;
1433 // If none of the top bits are demanded, convert this into an any_extend.
1435 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1439 // Since some of the sign extended bits are demanded, we know that the sign
1441 APInt InDemandedBits = InMask & NewMask;
1442 InDemandedBits |= InSignBit;
1443 InDemandedBits.trunc(InBits);
1445 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1446 KnownOne, TLO, Depth+1))
1448 KnownZero.zext(BitWidth);
1449 KnownOne.zext(BitWidth);
1451 // If the sign bit is known zero, convert this to a zero extend.
1452 if (KnownZero.intersects(InSignBit))
1453 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1457 // If the sign bit is known one, the top bits match.
1458 if (KnownOne.intersects(InSignBit)) {
1459 KnownOne |= NewBits;
1460 KnownZero &= ~NewBits;
1461 } else { // Otherwise, top bits aren't known.
1462 KnownOne &= ~NewBits;
1463 KnownZero &= ~NewBits;
1467 case ISD::ANY_EXTEND: {
1468 unsigned OperandBitWidth =
1469 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1470 APInt InMask = NewMask;
1471 InMask.trunc(OperandBitWidth);
1472 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1473 KnownZero, KnownOne, TLO, Depth+1))
1475 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1476 KnownZero.zext(BitWidth);
1477 KnownOne.zext(BitWidth);
1480 case ISD::TRUNCATE: {
1481 // Simplify the input, using demanded bit information, and compute the known
1482 // zero/one bits live out.
1483 unsigned OperandBitWidth =
1484 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1485 APInt TruncMask = NewMask;
1486 TruncMask.zext(OperandBitWidth);
1487 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1488 KnownZero, KnownOne, TLO, Depth+1))
1490 KnownZero.trunc(BitWidth);
1491 KnownOne.trunc(BitWidth);
1493 // If the input is only used by this truncate, see if we can shrink it based
1494 // on the known demanded bits.
1495 if (Op.getOperand(0).getNode()->hasOneUse()) {
1496 SDValue In = Op.getOperand(0);
1497 switch (In.getOpcode()) {
1500 // Shrink SRL by a constant if none of the high bits shifted in are
1502 if (TLO.LegalTypes() &&
1503 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1504 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1507 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1510 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1511 OperandBitWidth - BitWidth);
1512 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1513 HighBits.trunc(BitWidth);
1515 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1516 // None of the shifted in bits are needed. Add a truncate of the
1517 // shift input, then shift it.
1518 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1521 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1530 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1533 case ISD::AssertZext: {
1534 // Demand all the bits of the input that are demanded in the output.
1535 // The low bits are obvious; the high bits are demanded because we're
1536 // asserting that they're zero here.
1537 if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
1538 KnownZero, KnownOne, TLO, Depth+1))
1540 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1542 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1543 APInt InMask = APInt::getLowBitsSet(BitWidth,
1544 VT.getSizeInBits());
1545 KnownZero |= ~InMask & NewMask;
1548 case ISD::BIT_CONVERT:
1550 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1551 // is demanded, turn this into a FGETSIGN.
1552 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1553 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1554 !MVT::isVector(Op.getOperand(0).getValueType())) {
1555 // Only do this xform if FGETSIGN is valid or if before legalize.
1556 if (!TLO.AfterLegalize ||
1557 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1558 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1559 // place. We expect the SHL to be eliminated by other optimizations.
1560 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1562 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1563 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1564 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1573 // Add, Sub, and Mul don't demand any bits in positions beyond that
1574 // of the highest bit demanded of them.
1575 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1576 BitWidth - NewMask.countLeadingZeros());
1577 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1578 KnownOne2, TLO, Depth+1))
1580 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1581 KnownOne2, TLO, Depth+1))
1583 // See if the operation should be performed at a smaller bit width.
1584 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1589 // Just use ComputeMaskedBits to compute output bits.
1590 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1594 // If we know the value of all of the demanded bits, return this as a
1596 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1597 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1602 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1603 /// in Mask are known to be either zero or one and return them in the
1604 /// KnownZero/KnownOne bitsets.
1605 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1609 const SelectionDAG &DAG,
1610 unsigned Depth) const {
1611 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1612 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1613 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1614 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1615 "Should use MaskedValueIsZero if you don't know whether Op"
1616 " is a target node!");
1617 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1620 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1621 /// targets that want to expose additional information about sign bits to the
1623 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1624 unsigned Depth) const {
1625 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1626 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1627 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1628 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1629 "Should use ComputeNumSignBits if you don't know whether Op"
1630 " is a target node!");
1634 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1635 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1636 /// determine which bit is set.
1638 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1639 // A left-shift of a constant one will have exactly one bit set, because
1640 // shifting the bit off the end is undefined.
1641 if (Val.getOpcode() == ISD::SHL)
1642 if (ConstantSDNode *C =
1643 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1644 if (C->getAPIntValue() == 1)
1647 // Similarly, a right-shift of a constant sign-bit will have exactly
1649 if (Val.getOpcode() == ISD::SRL)
1650 if (ConstantSDNode *C =
1651 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1652 if (C->getAPIntValue().isSignBit())
1655 // More could be done here, though the above checks are enough
1656 // to handle some common cases.
1658 // Fall back to ComputeMaskedBits to catch other known cases.
1659 EVT OpVT = Val.getValueType();
1660 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1661 APInt Mask = APInt::getAllOnesValue(BitWidth);
1662 APInt KnownZero, KnownOne;
1663 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1664 return (KnownZero.countPopulation() == BitWidth - 1) &&
1665 (KnownOne.countPopulation() == 1);
1668 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1669 /// and cc. If it is unable to simplify it, return a null SDValue.
1671 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1672 ISD::CondCode Cond, bool foldBooleans,
1673 DAGCombinerInfo &DCI, DebugLoc dl) const {
1674 SelectionDAG &DAG = DCI.DAG;
1675 LLVMContext &Context = *DAG.getContext();
1677 // These setcc operations always fold.
1681 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1683 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1686 if (isa<ConstantSDNode>(N0.getNode())) {
1687 // Ensure that the constant occurs on the RHS, and fold constant
1689 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1692 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1693 const APInt &C1 = N1C->getAPIntValue();
1695 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1696 // equality comparison, then we're just comparing whether X itself is
1698 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1699 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1700 N0.getOperand(1).getOpcode() == ISD::Constant) {
1702 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1703 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1704 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1705 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1706 // (srl (ctlz x), 5) == 0 -> X != 0
1707 // (srl (ctlz x), 5) != 1 -> X != 0
1710 // (srl (ctlz x), 5) != 0 -> X == 0
1711 // (srl (ctlz x), 5) == 1 -> X == 0
1714 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1715 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1720 // If the LHS is '(and load, const)', the RHS is 0,
1721 // the test is for equality or unsigned, and all 1 bits of the const are
1722 // in the same partial word, see if we can shorten the load.
1723 if (DCI.isBeforeLegalize() &&
1724 N0.getOpcode() == ISD::AND && C1 == 0 &&
1725 N0.getNode()->hasOneUse() &&
1726 isa<LoadSDNode>(N0.getOperand(0)) &&
1727 N0.getOperand(0).getNode()->hasOneUse() &&
1728 isa<ConstantSDNode>(N0.getOperand(1))) {
1729 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1731 unsigned bestWidth = 0, bestOffset = 0;
1732 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1733 unsigned origWidth = N0.getValueType().getSizeInBits();
1734 unsigned maskWidth = origWidth;
1735 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1736 // 8 bits, but have to be careful...
1737 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1738 origWidth = Lod->getMemoryVT().getSizeInBits();
1740 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1741 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1742 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1743 for (unsigned offset=0; offset<origWidth/width; offset++) {
1744 if ((newMask & Mask) == Mask) {
1745 if (!TD->isLittleEndian())
1746 bestOffset = (origWidth/width - offset - 1) * (width/8);
1748 bestOffset = (uint64_t)offset * (width/8);
1749 bestMask = Mask.lshr(offset * (width/8) * 8);
1753 newMask = newMask << width;
1758 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1759 if (newVT.isRound()) {
1760 EVT PtrType = Lod->getOperand(1).getValueType();
1761 SDValue Ptr = Lod->getBasePtr();
1762 if (bestOffset != 0)
1763 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1764 DAG.getConstant(bestOffset, PtrType));
1765 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1766 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1768 Lod->getSrcValueOffset() + bestOffset,
1769 false, false, NewAlign);
1770 return DAG.getSetCC(dl, VT,
1771 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1772 DAG.getConstant(bestMask.trunc(bestWidth),
1774 DAG.getConstant(0LL, newVT), Cond);
1779 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1780 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1781 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1783 // If the comparison constant has bits in the upper part, the
1784 // zero-extended value could never match.
1785 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1786 C1.getBitWidth() - InSize))) {
1790 case ISD::SETEQ: return DAG.getConstant(0, VT);
1793 case ISD::SETNE: return DAG.getConstant(1, VT);
1796 // True if the sign bit of C1 is set.
1797 return DAG.getConstant(C1.isNegative(), VT);
1800 // True if the sign bit of C1 isn't set.
1801 return DAG.getConstant(C1.isNonNegative(), VT);
1807 // Otherwise, we can perform the comparison with the low bits.
1815 EVT newVT = N0.getOperand(0).getValueType();
1816 if (DCI.isBeforeLegalizeOps() ||
1817 (isOperationLegal(ISD::SETCC, newVT) &&
1818 getCondCodeAction(Cond, newVT)==Legal))
1819 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1820 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1825 break; // todo, be more careful with signed comparisons
1827 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1828 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1829 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1830 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1831 EVT ExtDstTy = N0.getValueType();
1832 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1834 // If the extended part has any inconsistent bits, it cannot ever
1835 // compare equal. In other words, they have to be all ones or all
1838 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1839 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1840 return DAG.getConstant(Cond == ISD::SETNE, VT);
1843 EVT Op0Ty = N0.getOperand(0).getValueType();
1844 if (Op0Ty == ExtSrcTy) {
1845 ZextOp = N0.getOperand(0);
1847 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1848 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1849 DAG.getConstant(Imm, Op0Ty));
1851 if (!DCI.isCalledByLegalizer())
1852 DCI.AddToWorklist(ZextOp.getNode());
1853 // Otherwise, make this a use of a zext.
1854 return DAG.getSetCC(dl, VT, ZextOp,
1855 DAG.getConstant(C1 & APInt::getLowBitsSet(
1860 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1861 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1862 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1863 if (N0.getOpcode() == ISD::SETCC &&
1864 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1865 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1867 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1868 // Invert the condition.
1869 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1870 CC = ISD::getSetCCInverse(CC,
1871 N0.getOperand(0).getValueType().isInteger());
1872 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1875 if ((N0.getOpcode() == ISD::XOR ||
1876 (N0.getOpcode() == ISD::AND &&
1877 N0.getOperand(0).getOpcode() == ISD::XOR &&
1878 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1879 isa<ConstantSDNode>(N0.getOperand(1)) &&
1880 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1881 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1882 // can only do this if the top bits are known zero.
1883 unsigned BitWidth = N0.getValueSizeInBits();
1884 if (DAG.MaskedValueIsZero(N0,
1885 APInt::getHighBitsSet(BitWidth,
1887 // Okay, get the un-inverted input value.
1889 if (N0.getOpcode() == ISD::XOR)
1890 Val = N0.getOperand(0);
1892 assert(N0.getOpcode() == ISD::AND &&
1893 N0.getOperand(0).getOpcode() == ISD::XOR);
1894 // ((X^1)&1)^1 -> X & 1
1895 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1896 N0.getOperand(0).getOperand(0),
1900 return DAG.getSetCC(dl, VT, Val, N1,
1901 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1903 } else if (N1C->getAPIntValue() == 1 &&
1905 getBooleanContents() == ZeroOrOneBooleanContent)) {
1907 if (Op0.getOpcode() == ISD::TRUNCATE)
1908 Op0 = Op0.getOperand(0);
1910 if ((Op0.getOpcode() == ISD::XOR) &&
1911 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1912 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1913 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1914 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1915 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1917 } else if (Op0.getOpcode() == ISD::AND &&
1918 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1919 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1920 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1921 if (Op0.getValueType().bitsGT(VT))
1922 Op0 = DAG.getNode(ISD::AND, dl, VT,
1923 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1924 DAG.getConstant(1, VT));
1925 else if (Op0.getValueType().bitsLT(VT))
1926 Op0 = DAG.getNode(ISD::AND, dl, VT,
1927 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1928 DAG.getConstant(1, VT));
1930 return DAG.getSetCC(dl, VT, Op0,
1931 DAG.getConstant(0, Op0.getValueType()),
1932 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1937 APInt MinVal, MaxVal;
1938 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1939 if (ISD::isSignedIntSetCC(Cond)) {
1940 MinVal = APInt::getSignedMinValue(OperandBitSize);
1941 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1943 MinVal = APInt::getMinValue(OperandBitSize);
1944 MaxVal = APInt::getMaxValue(OperandBitSize);
1947 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1948 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1949 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1950 // X >= C0 --> X > (C0-1)
1951 return DAG.getSetCC(dl, VT, N0,
1952 DAG.getConstant(C1-1, N1.getValueType()),
1953 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1956 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1957 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1958 // X <= C0 --> X < (C0+1)
1959 return DAG.getSetCC(dl, VT, N0,
1960 DAG.getConstant(C1+1, N1.getValueType()),
1961 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1964 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1965 return DAG.getConstant(0, VT); // X < MIN --> false
1966 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1967 return DAG.getConstant(1, VT); // X >= MIN --> true
1968 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1969 return DAG.getConstant(0, VT); // X > MAX --> false
1970 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1971 return DAG.getConstant(1, VT); // X <= MAX --> true
1973 // Canonicalize setgt X, Min --> setne X, Min
1974 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1975 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1976 // Canonicalize setlt X, Max --> setne X, Max
1977 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1978 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1980 // If we have setult X, 1, turn it into seteq X, 0
1981 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1982 return DAG.getSetCC(dl, VT, N0,
1983 DAG.getConstant(MinVal, N0.getValueType()),
1985 // If we have setugt X, Max-1, turn it into seteq X, Max
1986 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1987 return DAG.getSetCC(dl, VT, N0,
1988 DAG.getConstant(MaxVal, N0.getValueType()),
1991 // If we have "setcc X, C0", check to see if we can shrink the immediate
1994 // SETUGT X, SINTMAX -> SETLT X, 0
1995 if (Cond == ISD::SETUGT &&
1996 C1 == APInt::getSignedMaxValue(OperandBitSize))
1997 return DAG.getSetCC(dl, VT, N0,
1998 DAG.getConstant(0, N1.getValueType()),
2001 // SETULT X, SINTMIN -> SETGT X, -1
2002 if (Cond == ISD::SETULT &&
2003 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2004 SDValue ConstMinusOne =
2005 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2007 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2010 // Fold bit comparisons when we can.
2011 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2012 (VT == N0.getValueType() ||
2013 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2014 N0.getOpcode() == ISD::AND)
2015 if (ConstantSDNode *AndRHS =
2016 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2017 EVT ShiftTy = DCI.isBeforeLegalize() ?
2018 getPointerTy() : getShiftAmountTy();
2019 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2020 // Perform the xform if the AND RHS is a single bit.
2021 if (AndRHS->getAPIntValue().isPowerOf2()) {
2022 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2023 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2024 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2026 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2027 // (X & 8) == 8 --> (X & 8) >> 3
2028 // Perform the xform if C1 is a single bit.
2029 if (C1.isPowerOf2()) {
2030 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2031 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2032 DAG.getConstant(C1.logBase2(), ShiftTy)));
2038 if (isa<ConstantFPSDNode>(N0.getNode())) {
2039 // Constant fold or commute setcc.
2040 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2041 if (O.getNode()) return O;
2042 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2043 // If the RHS of an FP comparison is a constant, simplify it away in
2045 if (CFP->getValueAPF().isNaN()) {
2046 // If an operand is known to be a nan, we can fold it.
2047 switch (ISD::getUnorderedFlavor(Cond)) {
2048 default: llvm_unreachable("Unknown flavor!");
2049 case 0: // Known false.
2050 return DAG.getConstant(0, VT);
2051 case 1: // Known true.
2052 return DAG.getConstant(1, VT);
2053 case 2: // Undefined.
2054 return DAG.getUNDEF(VT);
2058 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2059 // constant if knowing that the operand is non-nan is enough. We prefer to
2060 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2062 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2063 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2065 // If the condition is not legal, see if we can find an equivalent one
2067 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2068 // If the comparison was an awkward floating-point == or != and one of
2069 // the comparison operands is infinity or negative infinity, convert the
2070 // condition to a less-awkward <= or >=.
2071 if (CFP->getValueAPF().isInfinity()) {
2072 if (CFP->getValueAPF().isNegative()) {
2073 if (Cond == ISD::SETOEQ &&
2074 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2075 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2076 if (Cond == ISD::SETUEQ &&
2077 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2078 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2079 if (Cond == ISD::SETUNE &&
2080 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2081 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2082 if (Cond == ISD::SETONE &&
2083 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2084 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2086 if (Cond == ISD::SETOEQ &&
2087 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2088 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2089 if (Cond == ISD::SETUEQ &&
2090 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2091 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2092 if (Cond == ISD::SETUNE &&
2093 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2094 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2095 if (Cond == ISD::SETONE &&
2096 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2097 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2104 // We can always fold X == X for integer setcc's.
2105 if (N0.getValueType().isInteger())
2106 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2107 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2108 if (UOF == 2) // FP operators that are undefined on NaNs.
2109 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2110 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2111 return DAG.getConstant(UOF, VT);
2112 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2113 // if it is not already.
2114 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2115 if (NewCond != Cond)
2116 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2119 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2120 N0.getValueType().isInteger()) {
2121 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2122 N0.getOpcode() == ISD::XOR) {
2123 // Simplify (X+Y) == (X+Z) --> Y == Z
2124 if (N0.getOpcode() == N1.getOpcode()) {
2125 if (N0.getOperand(0) == N1.getOperand(0))
2126 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2127 if (N0.getOperand(1) == N1.getOperand(1))
2128 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2129 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2130 // If X op Y == Y op X, try other combinations.
2131 if (N0.getOperand(0) == N1.getOperand(1))
2132 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2134 if (N0.getOperand(1) == N1.getOperand(0))
2135 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2140 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2141 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2142 // Turn (X+C1) == C2 --> X == C2-C1
2143 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2144 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2145 DAG.getConstant(RHSC->getAPIntValue()-
2146 LHSR->getAPIntValue(),
2147 N0.getValueType()), Cond);
2150 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2151 if (N0.getOpcode() == ISD::XOR)
2152 // If we know that all of the inverted bits are zero, don't bother
2153 // performing the inversion.
2154 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2156 DAG.getSetCC(dl, VT, N0.getOperand(0),
2157 DAG.getConstant(LHSR->getAPIntValue() ^
2158 RHSC->getAPIntValue(),
2163 // Turn (C1-X) == C2 --> X == C1-C2
2164 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2165 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2167 DAG.getSetCC(dl, VT, N0.getOperand(1),
2168 DAG.getConstant(SUBC->getAPIntValue() -
2169 RHSC->getAPIntValue(),
2176 // Simplify (X+Z) == X --> Z == 0
2177 if (N0.getOperand(0) == N1)
2178 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2179 DAG.getConstant(0, N0.getValueType()), Cond);
2180 if (N0.getOperand(1) == N1) {
2181 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2182 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2183 DAG.getConstant(0, N0.getValueType()), Cond);
2184 else if (N0.getNode()->hasOneUse()) {
2185 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2186 // (Z-X) == X --> Z == X<<1
2187 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2189 DAG.getConstant(1, getShiftAmountTy()));
2190 if (!DCI.isCalledByLegalizer())
2191 DCI.AddToWorklist(SH.getNode());
2192 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2197 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2198 N1.getOpcode() == ISD::XOR) {
2199 // Simplify X == (X+Z) --> Z == 0
2200 if (N1.getOperand(0) == N0) {
2201 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2202 DAG.getConstant(0, N1.getValueType()), Cond);
2203 } else if (N1.getOperand(1) == N0) {
2204 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2205 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2206 DAG.getConstant(0, N1.getValueType()), Cond);
2207 } else if (N1.getNode()->hasOneUse()) {
2208 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2209 // X == (Z-X) --> X<<1 == Z
2210 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2211 DAG.getConstant(1, getShiftAmountTy()));
2212 if (!DCI.isCalledByLegalizer())
2213 DCI.AddToWorklist(SH.getNode());
2214 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2219 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2220 // Note that where y is variable and is known to have at most
2221 // one bit set (for example, if it is z&1) we cannot do this;
2222 // the expressions are not equivalent when y==0.
2223 if (N0.getOpcode() == ISD::AND)
2224 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2225 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2226 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2227 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2228 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2231 if (N1.getOpcode() == ISD::AND)
2232 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2233 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2234 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2235 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2236 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2241 // Fold away ALL boolean setcc's.
2243 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2245 default: llvm_unreachable("Unknown integer setcc!");
2246 case ISD::SETEQ: // X == Y -> ~(X^Y)
2247 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2248 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2249 if (!DCI.isCalledByLegalizer())
2250 DCI.AddToWorklist(Temp.getNode());
2252 case ISD::SETNE: // X != Y --> (X^Y)
2253 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2255 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2256 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2257 Temp = DAG.getNOT(dl, N0, MVT::i1);
2258 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2259 if (!DCI.isCalledByLegalizer())
2260 DCI.AddToWorklist(Temp.getNode());
2262 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2263 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2264 Temp = DAG.getNOT(dl, N1, MVT::i1);
2265 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2266 if (!DCI.isCalledByLegalizer())
2267 DCI.AddToWorklist(Temp.getNode());
2269 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2270 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2271 Temp = DAG.getNOT(dl, N0, MVT::i1);
2272 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2273 if (!DCI.isCalledByLegalizer())
2274 DCI.AddToWorklist(Temp.getNode());
2276 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2277 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2278 Temp = DAG.getNOT(dl, N1, MVT::i1);
2279 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2282 if (VT != MVT::i1) {
2283 if (!DCI.isCalledByLegalizer())
2284 DCI.AddToWorklist(N0.getNode());
2285 // FIXME: If running after legalize, we probably can't do this.
2286 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2291 // Could not fold it.
2295 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2296 /// node is a GlobalAddress + offset.
2297 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
2298 int64_t &Offset) const {
2299 if (isa<GlobalAddressSDNode>(N)) {
2300 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2301 GA = GASD->getGlobal();
2302 Offset += GASD->getOffset();
2306 if (N->getOpcode() == ISD::ADD) {
2307 SDValue N1 = N->getOperand(0);
2308 SDValue N2 = N->getOperand(1);
2309 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2310 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2312 Offset += V->getSExtValue();
2315 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2316 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2318 Offset += V->getSExtValue();
2327 SDValue TargetLowering::
2328 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2329 // Default implementation: no optimization.
2333 //===----------------------------------------------------------------------===//
2334 // Inline Assembler Implementation Methods
2335 //===----------------------------------------------------------------------===//
2338 TargetLowering::ConstraintType
2339 TargetLowering::getConstraintType(const std::string &Constraint) const {
2340 // FIXME: lots more standard ones to handle.
2341 if (Constraint.size() == 1) {
2342 switch (Constraint[0]) {
2344 case 'r': return C_RegisterClass;
2346 case 'o': // offsetable
2347 case 'V': // not offsetable
2349 case 'i': // Simple Integer or Relocatable Constant
2350 case 'n': // Simple Integer
2351 case 's': // Relocatable Constant
2352 case 'X': // Allow ANY value.
2353 case 'I': // Target registers.
2365 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2366 Constraint[Constraint.size()-1] == '}')
2371 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2372 /// with another that has more specific requirements based on the type of the
2373 /// corresponding operand.
2374 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2375 if (ConstraintVT.isInteger())
2377 if (ConstraintVT.isFloatingPoint())
2378 return "f"; // works for many targets
2382 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2383 /// vector. If it is invalid, don't add anything to Ops.
2384 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2385 char ConstraintLetter,
2387 std::vector<SDValue> &Ops,
2388 SelectionDAG &DAG) const {
2389 switch (ConstraintLetter) {
2391 case 'X': // Allows any operand; labels (basic block) use this.
2392 if (Op.getOpcode() == ISD::BasicBlock) {
2397 case 'i': // Simple Integer or Relocatable Constant
2398 case 'n': // Simple Integer
2399 case 's': { // Relocatable Constant
2400 // These operands are interested in values of the form (GV+C), where C may
2401 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2402 // is possible and fine if either GV or C are missing.
2403 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2404 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2406 // If we have "(add GV, C)", pull out GV/C
2407 if (Op.getOpcode() == ISD::ADD) {
2408 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2409 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2410 if (C == 0 || GA == 0) {
2411 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2412 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2414 if (C == 0 || GA == 0)
2418 // If we find a valid operand, map to the TargetXXX version so that the
2419 // value itself doesn't get selected.
2420 if (GA) { // Either &GV or &GV+C
2421 if (ConstraintLetter != 'n') {
2422 int64_t Offs = GA->getOffset();
2423 if (C) Offs += C->getZExtValue();
2424 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2425 Op.getValueType(), Offs));
2429 if (C) { // just C, no GV.
2430 // Simple constants are not allowed for 's'.
2431 if (ConstraintLetter != 's') {
2432 // gcc prints these as sign extended. Sign extend value to 64 bits
2433 // now; without this it would get ZExt'd later in
2434 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2435 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2445 std::vector<unsigned> TargetLowering::
2446 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2448 return std::vector<unsigned>();
2452 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2453 getRegForInlineAsmConstraint(const std::string &Constraint,
2455 if (Constraint[0] != '{')
2456 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2457 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2459 // Remove the braces from around the name.
2460 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2462 // Figure out which register class contains this reg.
2463 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2464 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2465 E = RI->regclass_end(); RCI != E; ++RCI) {
2466 const TargetRegisterClass *RC = *RCI;
2468 // If none of the value types for this register class are valid, we
2469 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2470 bool isLegal = false;
2471 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2473 if (isTypeLegal(*I)) {
2479 if (!isLegal) continue;
2481 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2483 if (RegName.equals_lower(RI->getName(*I)))
2484 return std::make_pair(*I, RC);
2488 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2491 //===----------------------------------------------------------------------===//
2492 // Constraint Selection.
2494 /// isMatchingInputConstraint - Return true of this is an input operand that is
2495 /// a matching constraint like "4".
2496 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2497 assert(!ConstraintCode.empty() && "No known constraint!");
2498 return isdigit(ConstraintCode[0]);
2501 /// getMatchedOperand - If this is an input matching constraint, this method
2502 /// returns the output operand it matches.
2503 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2504 assert(!ConstraintCode.empty() && "No known constraint!");
2505 return atoi(ConstraintCode.c_str());
2509 /// getConstraintGenerality - Return an integer indicating how general CT
2511 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2513 default: llvm_unreachable("Unknown constraint type!");
2514 case TargetLowering::C_Other:
2515 case TargetLowering::C_Unknown:
2517 case TargetLowering::C_Register:
2519 case TargetLowering::C_RegisterClass:
2521 case TargetLowering::C_Memory:
2526 /// ChooseConstraint - If there are multiple different constraints that we
2527 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2528 /// This is somewhat tricky: constraints fall into four classes:
2529 /// Other -> immediates and magic values
2530 /// Register -> one specific register
2531 /// RegisterClass -> a group of regs
2532 /// Memory -> memory
2533 /// Ideally, we would pick the most specific constraint possible: if we have
2534 /// something that fits into a register, we would pick it. The problem here
2535 /// is that if we have something that could either be in a register or in
2536 /// memory that use of the register could cause selection of *other*
2537 /// operands to fail: they might only succeed if we pick memory. Because of
2538 /// this the heuristic we use is:
2540 /// 1) If there is an 'other' constraint, and if the operand is valid for
2541 /// that constraint, use it. This makes us take advantage of 'i'
2542 /// constraints when available.
2543 /// 2) Otherwise, pick the most general constraint present. This prefers
2544 /// 'm' over 'r', for example.
2546 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2547 bool hasMemory, const TargetLowering &TLI,
2548 SDValue Op, SelectionDAG *DAG) {
2549 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2550 unsigned BestIdx = 0;
2551 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2552 int BestGenerality = -1;
2554 // Loop over the options, keeping track of the most general one.
2555 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2556 TargetLowering::ConstraintType CType =
2557 TLI.getConstraintType(OpInfo.Codes[i]);
2559 // If this is an 'other' constraint, see if the operand is valid for it.
2560 // For example, on X86 we might have an 'rI' constraint. If the operand
2561 // is an integer in the range [0..31] we want to use I (saving a load
2562 // of a register), otherwise we must use 'r'.
2563 if (CType == TargetLowering::C_Other && Op.getNode()) {
2564 assert(OpInfo.Codes[i].size() == 1 &&
2565 "Unhandled multi-letter 'other' constraint");
2566 std::vector<SDValue> ResultOps;
2567 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2569 if (!ResultOps.empty()) {
2576 // This constraint letter is more general than the previous one, use it.
2577 int Generality = getConstraintGenerality(CType);
2578 if (Generality > BestGenerality) {
2581 BestGenerality = Generality;
2585 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2586 OpInfo.ConstraintType = BestType;
2589 /// ComputeConstraintToUse - Determines the constraint code and constraint
2590 /// type to use for the specific AsmOperandInfo, setting
2591 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2592 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2595 SelectionDAG *DAG) const {
2596 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2598 // Single-letter constraints ('r') are very common.
2599 if (OpInfo.Codes.size() == 1) {
2600 OpInfo.ConstraintCode = OpInfo.Codes[0];
2601 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2603 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2606 // 'X' matches anything.
2607 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2608 // Labels and constants are handled elsewhere ('X' is the only thing
2609 // that matches labels). For Functions, the type here is the type of
2610 // the result, which is not what we want to look at; leave them alone.
2611 Value *v = OpInfo.CallOperandVal;
2612 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2613 OpInfo.CallOperandVal = v;
2617 // Otherwise, try to resolve it to something we know about by looking at
2618 // the actual operand type.
2619 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2620 OpInfo.ConstraintCode = Repl;
2621 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2626 //===----------------------------------------------------------------------===//
2627 // Loop Strength Reduction hooks
2628 //===----------------------------------------------------------------------===//
2630 /// isLegalAddressingMode - Return true if the addressing mode represented
2631 /// by AM is legal for this target, for a load/store of the specified type.
2632 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2633 const Type *Ty) const {
2634 // The default implementation of this implements a conservative RISCy, r+r and
2637 // Allows a sign-extended 16-bit immediate field.
2638 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2641 // No global is ever allowed as a base.
2645 // Only support r+r,
2647 case 0: // "r+i" or just "i", depending on HasBaseReg.
2650 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2652 // Otherwise we have r+r or r+i.
2655 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2657 // Allow 2*r as r+r.
2664 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2665 /// return a DAG expression to select that will generate the same value by
2666 /// multiplying by a magic number. See:
2667 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2668 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2669 std::vector<SDNode*>* Created) const {
2670 EVT VT = N->getValueType(0);
2671 DebugLoc dl= N->getDebugLoc();
2673 // Check to see if we can do this.
2674 // FIXME: We should be more aggressive here.
2675 if (!isTypeLegal(VT))
2678 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2679 APInt::ms magics = d.magic();
2681 // Multiply the numerator (operand 0) by the magic value
2682 // FIXME: We should support doing a MUL in a wider type
2684 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2685 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2686 DAG.getConstant(magics.m, VT));
2687 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2688 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2690 DAG.getConstant(magics.m, VT)).getNode(), 1);
2692 return SDValue(); // No mulhs or equvialent
2693 // If d > 0 and m < 0, add the numerator
2694 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2695 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2697 Created->push_back(Q.getNode());
2699 // If d < 0 and m > 0, subtract the numerator.
2700 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2701 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2703 Created->push_back(Q.getNode());
2705 // Shift right algebraic if shift value is nonzero
2707 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2708 DAG.getConstant(magics.s, getShiftAmountTy()));
2710 Created->push_back(Q.getNode());
2712 // Extract the sign bit and add it to the quotient
2714 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2715 getShiftAmountTy()));
2717 Created->push_back(T.getNode());
2718 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2721 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2722 /// return a DAG expression to select that will generate the same value by
2723 /// multiplying by a magic number. See:
2724 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2725 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2726 std::vector<SDNode*>* Created) const {
2727 EVT VT = N->getValueType(0);
2728 DebugLoc dl = N->getDebugLoc();
2730 // Check to see if we can do this.
2731 // FIXME: We should be more aggressive here.
2732 if (!isTypeLegal(VT))
2735 // FIXME: We should use a narrower constant when the upper
2736 // bits are known to be zero.
2737 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2738 APInt::mu magics = N1C->getAPIntValue().magicu();
2740 // Multiply the numerator (operand 0) by the magic value
2741 // FIXME: We should support doing a MUL in a wider type
2743 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2744 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2745 DAG.getConstant(magics.m, VT));
2746 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2747 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2749 DAG.getConstant(magics.m, VT)).getNode(), 1);
2751 return SDValue(); // No mulhu or equvialent
2753 Created->push_back(Q.getNode());
2755 if (magics.a == 0) {
2756 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2757 "We shouldn't generate an undefined shift!");
2758 return DAG.getNode(ISD::SRL, dl, VT, Q,
2759 DAG.getConstant(magics.s, getShiftAmountTy()));
2761 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2763 Created->push_back(NPQ.getNode());
2764 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2765 DAG.getConstant(1, getShiftAmountTy()));
2767 Created->push_back(NPQ.getNode());
2768 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2770 Created->push_back(NPQ.getNode());
2771 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2772 DAG.getConstant(magics.s-1, getShiftAmountTy()));