1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
35 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
36 bool isLocal = GV->hasLocalLinkage();
37 bool isDeclaration = GV->isDeclaration();
38 // FIXME: what should we do for protected and internal visibility?
39 // For variables, is internal different from hidden?
40 bool isHidden = GV->hasHiddenVisibility();
42 if (reloc == Reloc::PIC_) {
43 if (isLocal || isHidden)
44 return TLSModel::LocalDynamic;
46 return TLSModel::GeneralDynamic;
48 if (!isDeclaration || isHidden)
49 return TLSModel::LocalExec;
51 return TLSModel::InitialExec;
56 /// InitLibcallNames - Set default libcall names.
58 static void InitLibcallNames(const char **Names) {
59 Names[RTLIB::SHL_I16] = "__ashlhi3";
60 Names[RTLIB::SHL_I32] = "__ashlsi3";
61 Names[RTLIB::SHL_I64] = "__ashldi3";
62 Names[RTLIB::SHL_I128] = "__ashlti3";
63 Names[RTLIB::SRL_I16] = "__lshrhi3";
64 Names[RTLIB::SRL_I32] = "__lshrsi3";
65 Names[RTLIB::SRL_I64] = "__lshrdi3";
66 Names[RTLIB::SRL_I128] = "__lshrti3";
67 Names[RTLIB::SRA_I16] = "__ashrhi3";
68 Names[RTLIB::SRA_I32] = "__ashrsi3";
69 Names[RTLIB::SRA_I64] = "__ashrdi3";
70 Names[RTLIB::SRA_I128] = "__ashrti3";
71 Names[RTLIB::MUL_I8] = "__mulqi3";
72 Names[RTLIB::MUL_I16] = "__mulhi3";
73 Names[RTLIB::MUL_I32] = "__mulsi3";
74 Names[RTLIB::MUL_I64] = "__muldi3";
75 Names[RTLIB::MUL_I128] = "__multi3";
76 Names[RTLIB::SDIV_I8] = "__divqi3";
77 Names[RTLIB::SDIV_I16] = "__divhi3";
78 Names[RTLIB::SDIV_I32] = "__divsi3";
79 Names[RTLIB::SDIV_I64] = "__divdi3";
80 Names[RTLIB::SDIV_I128] = "__divti3";
81 Names[RTLIB::UDIV_I8] = "__udivqi3";
82 Names[RTLIB::UDIV_I16] = "__udivhi3";
83 Names[RTLIB::UDIV_I32] = "__udivsi3";
84 Names[RTLIB::UDIV_I64] = "__udivdi3";
85 Names[RTLIB::UDIV_I128] = "__udivti3";
86 Names[RTLIB::SREM_I8] = "__modqi3";
87 Names[RTLIB::SREM_I16] = "__modhi3";
88 Names[RTLIB::SREM_I32] = "__modsi3";
89 Names[RTLIB::SREM_I64] = "__moddi3";
90 Names[RTLIB::SREM_I128] = "__modti3";
91 Names[RTLIB::UREM_I8] = "__umodqi3";
92 Names[RTLIB::UREM_I16] = "__umodhi3";
93 Names[RTLIB::UREM_I32] = "__umodsi3";
94 Names[RTLIB::UREM_I64] = "__umoddi3";
95 Names[RTLIB::UREM_I128] = "__umodti3";
97 // These are generally not available.
98 Names[RTLIB::SDIVREM_I8] = 0;
99 Names[RTLIB::SDIVREM_I16] = 0;
100 Names[RTLIB::SDIVREM_I32] = 0;
101 Names[RTLIB::SDIVREM_I64] = 0;
102 Names[RTLIB::SDIVREM_I128] = 0;
103 Names[RTLIB::UDIVREM_I8] = 0;
104 Names[RTLIB::UDIVREM_I16] = 0;
105 Names[RTLIB::UDIVREM_I32] = 0;
106 Names[RTLIB::UDIVREM_I64] = 0;
107 Names[RTLIB::UDIVREM_I128] = 0;
109 Names[RTLIB::NEG_I32] = "__negsi2";
110 Names[RTLIB::NEG_I64] = "__negdi2";
111 Names[RTLIB::ADD_F32] = "__addsf3";
112 Names[RTLIB::ADD_F64] = "__adddf3";
113 Names[RTLIB::ADD_F80] = "__addxf3";
114 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
115 Names[RTLIB::SUB_F32] = "__subsf3";
116 Names[RTLIB::SUB_F64] = "__subdf3";
117 Names[RTLIB::SUB_F80] = "__subxf3";
118 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
119 Names[RTLIB::MUL_F32] = "__mulsf3";
120 Names[RTLIB::MUL_F64] = "__muldf3";
121 Names[RTLIB::MUL_F80] = "__mulxf3";
122 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
123 Names[RTLIB::DIV_F32] = "__divsf3";
124 Names[RTLIB::DIV_F64] = "__divdf3";
125 Names[RTLIB::DIV_F80] = "__divxf3";
126 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
127 Names[RTLIB::REM_F32] = "fmodf";
128 Names[RTLIB::REM_F64] = "fmod";
129 Names[RTLIB::REM_F80] = "fmodl";
130 Names[RTLIB::REM_PPCF128] = "fmodl";
131 Names[RTLIB::POWI_F32] = "__powisf2";
132 Names[RTLIB::POWI_F64] = "__powidf2";
133 Names[RTLIB::POWI_F80] = "__powixf2";
134 Names[RTLIB::POWI_PPCF128] = "__powitf2";
135 Names[RTLIB::SQRT_F32] = "sqrtf";
136 Names[RTLIB::SQRT_F64] = "sqrt";
137 Names[RTLIB::SQRT_F80] = "sqrtl";
138 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
139 Names[RTLIB::LOG_F32] = "logf";
140 Names[RTLIB::LOG_F64] = "log";
141 Names[RTLIB::LOG_F80] = "logl";
142 Names[RTLIB::LOG_PPCF128] = "logl";
143 Names[RTLIB::LOG2_F32] = "log2f";
144 Names[RTLIB::LOG2_F64] = "log2";
145 Names[RTLIB::LOG2_F80] = "log2l";
146 Names[RTLIB::LOG2_PPCF128] = "log2l";
147 Names[RTLIB::LOG10_F32] = "log10f";
148 Names[RTLIB::LOG10_F64] = "log10";
149 Names[RTLIB::LOG10_F80] = "log10l";
150 Names[RTLIB::LOG10_PPCF128] = "log10l";
151 Names[RTLIB::EXP_F32] = "expf";
152 Names[RTLIB::EXP_F64] = "exp";
153 Names[RTLIB::EXP_F80] = "expl";
154 Names[RTLIB::EXP_PPCF128] = "expl";
155 Names[RTLIB::EXP2_F32] = "exp2f";
156 Names[RTLIB::EXP2_F64] = "exp2";
157 Names[RTLIB::EXP2_F80] = "exp2l";
158 Names[RTLIB::EXP2_PPCF128] = "exp2l";
159 Names[RTLIB::SIN_F32] = "sinf";
160 Names[RTLIB::SIN_F64] = "sin";
161 Names[RTLIB::SIN_F80] = "sinl";
162 Names[RTLIB::SIN_PPCF128] = "sinl";
163 Names[RTLIB::COS_F32] = "cosf";
164 Names[RTLIB::COS_F64] = "cos";
165 Names[RTLIB::COS_F80] = "cosl";
166 Names[RTLIB::COS_PPCF128] = "cosl";
167 Names[RTLIB::POW_F32] = "powf";
168 Names[RTLIB::POW_F64] = "pow";
169 Names[RTLIB::POW_F80] = "powl";
170 Names[RTLIB::POW_PPCF128] = "powl";
171 Names[RTLIB::CEIL_F32] = "ceilf";
172 Names[RTLIB::CEIL_F64] = "ceil";
173 Names[RTLIB::CEIL_F80] = "ceill";
174 Names[RTLIB::CEIL_PPCF128] = "ceill";
175 Names[RTLIB::TRUNC_F32] = "truncf";
176 Names[RTLIB::TRUNC_F64] = "trunc";
177 Names[RTLIB::TRUNC_F80] = "truncl";
178 Names[RTLIB::TRUNC_PPCF128] = "truncl";
179 Names[RTLIB::RINT_F32] = "rintf";
180 Names[RTLIB::RINT_F64] = "rint";
181 Names[RTLIB::RINT_F80] = "rintl";
182 Names[RTLIB::RINT_PPCF128] = "rintl";
183 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
184 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
185 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
186 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
187 Names[RTLIB::FLOOR_F32] = "floorf";
188 Names[RTLIB::FLOOR_F64] = "floor";
189 Names[RTLIB::FLOOR_F80] = "floorl";
190 Names[RTLIB::FLOOR_PPCF128] = "floorl";
191 Names[RTLIB::COPYSIGN_F32] = "copysignf";
192 Names[RTLIB::COPYSIGN_F64] = "copysign";
193 Names[RTLIB::COPYSIGN_F80] = "copysignl";
194 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
195 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
196 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
197 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
198 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
199 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
200 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
201 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
202 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
203 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
204 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
205 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
206 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
207 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
208 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
209 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
210 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
211 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
212 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
213 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
214 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
215 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
216 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
217 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
218 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
219 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
220 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
221 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
222 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
223 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
224 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
225 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
226 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
227 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
228 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
229 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
230 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
231 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
232 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
233 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
234 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
235 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
236 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
237 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
238 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
239 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
240 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
241 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
242 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
243 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
244 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
245 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
246 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
247 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
248 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
249 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
250 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
251 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
252 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
253 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
254 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
255 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
256 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
257 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
258 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
259 Names[RTLIB::OEQ_F32] = "__eqsf2";
260 Names[RTLIB::OEQ_F64] = "__eqdf2";
261 Names[RTLIB::UNE_F32] = "__nesf2";
262 Names[RTLIB::UNE_F64] = "__nedf2";
263 Names[RTLIB::OGE_F32] = "__gesf2";
264 Names[RTLIB::OGE_F64] = "__gedf2";
265 Names[RTLIB::OLT_F32] = "__ltsf2";
266 Names[RTLIB::OLT_F64] = "__ltdf2";
267 Names[RTLIB::OLE_F32] = "__lesf2";
268 Names[RTLIB::OLE_F64] = "__ledf2";
269 Names[RTLIB::OGT_F32] = "__gtsf2";
270 Names[RTLIB::OGT_F64] = "__gtdf2";
271 Names[RTLIB::UO_F32] = "__unordsf2";
272 Names[RTLIB::UO_F64] = "__unorddf2";
273 Names[RTLIB::O_F32] = "__unordsf2";
274 Names[RTLIB::O_F64] = "__unorddf2";
275 Names[RTLIB::MEMCPY] = "memcpy";
276 Names[RTLIB::MEMMOVE] = "memmove";
277 Names[RTLIB::MEMSET] = "memset";
278 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
279 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
280 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
281 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
282 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
283 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
284 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
285 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
286 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
287 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
288 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
289 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
290 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
291 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
292 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
293 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
294 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
295 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
296 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
297 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
298 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
299 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
300 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
301 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
302 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
303 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
304 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
305 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
306 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
307 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
308 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
309 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
310 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
313 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
315 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
316 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
317 CCs[i] = CallingConv::C;
321 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
322 /// UNKNOWN_LIBCALL if there is none.
323 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
324 if (OpVT == MVT::f32) {
325 if (RetVT == MVT::f64)
326 return FPEXT_F32_F64;
329 return UNKNOWN_LIBCALL;
332 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
333 /// UNKNOWN_LIBCALL if there is none.
334 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
335 if (RetVT == MVT::f32) {
336 if (OpVT == MVT::f64)
337 return FPROUND_F64_F32;
338 if (OpVT == MVT::f80)
339 return FPROUND_F80_F32;
340 if (OpVT == MVT::ppcf128)
341 return FPROUND_PPCF128_F32;
342 } else if (RetVT == MVT::f64) {
343 if (OpVT == MVT::f80)
344 return FPROUND_F80_F64;
345 if (OpVT == MVT::ppcf128)
346 return FPROUND_PPCF128_F64;
349 return UNKNOWN_LIBCALL;
352 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
353 /// UNKNOWN_LIBCALL if there is none.
354 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
355 if (OpVT == MVT::f32) {
356 if (RetVT == MVT::i8)
357 return FPTOSINT_F32_I8;
358 if (RetVT == MVT::i16)
359 return FPTOSINT_F32_I16;
360 if (RetVT == MVT::i32)
361 return FPTOSINT_F32_I32;
362 if (RetVT == MVT::i64)
363 return FPTOSINT_F32_I64;
364 if (RetVT == MVT::i128)
365 return FPTOSINT_F32_I128;
366 } else if (OpVT == MVT::f64) {
367 if (RetVT == MVT::i8)
368 return FPTOSINT_F64_I8;
369 if (RetVT == MVT::i16)
370 return FPTOSINT_F64_I16;
371 if (RetVT == MVT::i32)
372 return FPTOSINT_F64_I32;
373 if (RetVT == MVT::i64)
374 return FPTOSINT_F64_I64;
375 if (RetVT == MVT::i128)
376 return FPTOSINT_F64_I128;
377 } else if (OpVT == MVT::f80) {
378 if (RetVT == MVT::i32)
379 return FPTOSINT_F80_I32;
380 if (RetVT == MVT::i64)
381 return FPTOSINT_F80_I64;
382 if (RetVT == MVT::i128)
383 return FPTOSINT_F80_I128;
384 } else if (OpVT == MVT::ppcf128) {
385 if (RetVT == MVT::i32)
386 return FPTOSINT_PPCF128_I32;
387 if (RetVT == MVT::i64)
388 return FPTOSINT_PPCF128_I64;
389 if (RetVT == MVT::i128)
390 return FPTOSINT_PPCF128_I128;
392 return UNKNOWN_LIBCALL;
395 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
396 /// UNKNOWN_LIBCALL if there is none.
397 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
398 if (OpVT == MVT::f32) {
399 if (RetVT == MVT::i8)
400 return FPTOUINT_F32_I8;
401 if (RetVT == MVT::i16)
402 return FPTOUINT_F32_I16;
403 if (RetVT == MVT::i32)
404 return FPTOUINT_F32_I32;
405 if (RetVT == MVT::i64)
406 return FPTOUINT_F32_I64;
407 if (RetVT == MVT::i128)
408 return FPTOUINT_F32_I128;
409 } else if (OpVT == MVT::f64) {
410 if (RetVT == MVT::i8)
411 return FPTOUINT_F64_I8;
412 if (RetVT == MVT::i16)
413 return FPTOUINT_F64_I16;
414 if (RetVT == MVT::i32)
415 return FPTOUINT_F64_I32;
416 if (RetVT == MVT::i64)
417 return FPTOUINT_F64_I64;
418 if (RetVT == MVT::i128)
419 return FPTOUINT_F64_I128;
420 } else if (OpVT == MVT::f80) {
421 if (RetVT == MVT::i32)
422 return FPTOUINT_F80_I32;
423 if (RetVT == MVT::i64)
424 return FPTOUINT_F80_I64;
425 if (RetVT == MVT::i128)
426 return FPTOUINT_F80_I128;
427 } else if (OpVT == MVT::ppcf128) {
428 if (RetVT == MVT::i32)
429 return FPTOUINT_PPCF128_I32;
430 if (RetVT == MVT::i64)
431 return FPTOUINT_PPCF128_I64;
432 if (RetVT == MVT::i128)
433 return FPTOUINT_PPCF128_I128;
435 return UNKNOWN_LIBCALL;
438 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
439 /// UNKNOWN_LIBCALL if there is none.
440 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
441 if (OpVT == MVT::i32) {
442 if (RetVT == MVT::f32)
443 return SINTTOFP_I32_F32;
444 else if (RetVT == MVT::f64)
445 return SINTTOFP_I32_F64;
446 else if (RetVT == MVT::f80)
447 return SINTTOFP_I32_F80;
448 else if (RetVT == MVT::ppcf128)
449 return SINTTOFP_I32_PPCF128;
450 } else if (OpVT == MVT::i64) {
451 if (RetVT == MVT::f32)
452 return SINTTOFP_I64_F32;
453 else if (RetVT == MVT::f64)
454 return SINTTOFP_I64_F64;
455 else if (RetVT == MVT::f80)
456 return SINTTOFP_I64_F80;
457 else if (RetVT == MVT::ppcf128)
458 return SINTTOFP_I64_PPCF128;
459 } else if (OpVT == MVT::i128) {
460 if (RetVT == MVT::f32)
461 return SINTTOFP_I128_F32;
462 else if (RetVT == MVT::f64)
463 return SINTTOFP_I128_F64;
464 else if (RetVT == MVT::f80)
465 return SINTTOFP_I128_F80;
466 else if (RetVT == MVT::ppcf128)
467 return SINTTOFP_I128_PPCF128;
469 return UNKNOWN_LIBCALL;
472 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
473 /// UNKNOWN_LIBCALL if there is none.
474 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
475 if (OpVT == MVT::i32) {
476 if (RetVT == MVT::f32)
477 return UINTTOFP_I32_F32;
478 else if (RetVT == MVT::f64)
479 return UINTTOFP_I32_F64;
480 else if (RetVT == MVT::f80)
481 return UINTTOFP_I32_F80;
482 else if (RetVT == MVT::ppcf128)
483 return UINTTOFP_I32_PPCF128;
484 } else if (OpVT == MVT::i64) {
485 if (RetVT == MVT::f32)
486 return UINTTOFP_I64_F32;
487 else if (RetVT == MVT::f64)
488 return UINTTOFP_I64_F64;
489 else if (RetVT == MVT::f80)
490 return UINTTOFP_I64_F80;
491 else if (RetVT == MVT::ppcf128)
492 return UINTTOFP_I64_PPCF128;
493 } else if (OpVT == MVT::i128) {
494 if (RetVT == MVT::f32)
495 return UINTTOFP_I128_F32;
496 else if (RetVT == MVT::f64)
497 return UINTTOFP_I128_F64;
498 else if (RetVT == MVT::f80)
499 return UINTTOFP_I128_F80;
500 else if (RetVT == MVT::ppcf128)
501 return UINTTOFP_I128_PPCF128;
503 return UNKNOWN_LIBCALL;
506 /// InitCmpLibcallCCs - Set default comparison libcall CC.
508 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
509 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
510 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
511 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
512 CCs[RTLIB::UNE_F32] = ISD::SETNE;
513 CCs[RTLIB::UNE_F64] = ISD::SETNE;
514 CCs[RTLIB::OGE_F32] = ISD::SETGE;
515 CCs[RTLIB::OGE_F64] = ISD::SETGE;
516 CCs[RTLIB::OLT_F32] = ISD::SETLT;
517 CCs[RTLIB::OLT_F64] = ISD::SETLT;
518 CCs[RTLIB::OLE_F32] = ISD::SETLE;
519 CCs[RTLIB::OLE_F64] = ISD::SETLE;
520 CCs[RTLIB::OGT_F32] = ISD::SETGT;
521 CCs[RTLIB::OGT_F64] = ISD::SETGT;
522 CCs[RTLIB::UO_F32] = ISD::SETNE;
523 CCs[RTLIB::UO_F64] = ISD::SETNE;
524 CCs[RTLIB::O_F32] = ISD::SETEQ;
525 CCs[RTLIB::O_F64] = ISD::SETEQ;
528 /// NOTE: The constructor takes ownership of TLOF.
529 TargetLowering::TargetLowering(const TargetMachine &tm,
530 const TargetLoweringObjectFile *tlof)
531 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
532 // All operations default to being supported.
533 memset(OpActions, 0, sizeof(OpActions));
534 memset(LoadExtActions, 0, sizeof(LoadExtActions));
535 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
536 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
537 memset(CondCodeActions, 0, sizeof(CondCodeActions));
539 // Set default actions for various operations.
540 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
541 // Default all indexed load / store to expand.
542 for (unsigned IM = (unsigned)ISD::PRE_INC;
543 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
544 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
545 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
548 // These operations default to expand.
549 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
553 // Most targets ignore the @llvm.prefetch intrinsic.
554 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
556 // ConstantFP nodes default to expand. Targets can either change this to
557 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
558 // to optimize expansions for certain constants.
559 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
560 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
561 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
563 // These library functions default to expand.
564 setOperationAction(ISD::FLOG , MVT::f64, Expand);
565 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
566 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
567 setOperationAction(ISD::FEXP , MVT::f64, Expand);
568 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
569 setOperationAction(ISD::FLOG , MVT::f32, Expand);
570 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
571 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
572 setOperationAction(ISD::FEXP , MVT::f32, Expand);
573 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
575 // Default ISD::TRAP to expand (which turns it into abort).
576 setOperationAction(ISD::TRAP, MVT::Other, Expand);
578 IsLittleEndian = TD->isLittleEndian();
579 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
580 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
581 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
582 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
583 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
584 = maxStoresPerMemmoveOptSize = 4;
585 benefitFromCodePlacementOpt = false;
586 UseUnderscoreSetJmp = false;
587 UseUnderscoreLongJmp = false;
588 SelectIsExpensive = false;
589 IntDivIsCheap = false;
590 Pow2DivIsCheap = false;
591 JumpIsExpensive = false;
592 StackPointerRegisterToSaveRestore = 0;
593 ExceptionPointerRegister = 0;
594 ExceptionSelectorRegister = 0;
595 BooleanContents = UndefinedBooleanContent;
596 SchedPreferenceInfo = Sched::Latency;
598 JumpBufAlignment = 0;
599 MinFunctionAlignment = 0;
600 PrefFunctionAlignment = 0;
601 PrefLoopAlignment = 0;
602 MinStackArgumentAlignment = 1;
603 ShouldFoldAtomicFences = false;
605 InitLibcallNames(LibcallRoutineNames);
606 InitCmpLibcallCCs(CmpLibcallCCs);
607 InitLibcallCallingConvs(LibcallCallingConvs);
610 TargetLowering::~TargetLowering() {
614 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
615 return MVT::getIntegerVT(8*TD->getPointerSize());
618 /// canOpTrap - Returns true if the operation can trap for the value type.
619 /// VT must be a legal type.
620 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
621 assert(isTypeLegal(VT));
636 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
637 unsigned &NumIntermediates,
639 TargetLowering *TLI) {
640 // Figure out the right, legal destination reg to copy into.
641 unsigned NumElts = VT.getVectorNumElements();
642 MVT EltTy = VT.getVectorElementType();
644 unsigned NumVectorRegs = 1;
646 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
647 // could break down into LHS/RHS like LegalizeDAG does.
648 if (!isPowerOf2_32(NumElts)) {
649 NumVectorRegs = NumElts;
653 // Divide the input until we get to a supported size. This will always
654 // end with a scalar if the target doesn't support vectors.
655 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
660 NumIntermediates = NumVectorRegs;
662 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
663 if (!TLI->isTypeLegal(NewVT))
665 IntermediateVT = NewVT;
667 EVT DestVT = TLI->getRegisterType(NewVT);
669 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
670 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
672 // Otherwise, promotion or legal types use the same number of registers as
673 // the vector decimated to the appropriate level.
674 return NumVectorRegs;
677 /// isLegalRC - Return true if the value types that can be represented by the
678 /// specified register class are all legal.
679 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
680 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
688 /// hasLegalSuperRegRegClasses - Return true if the specified register class
689 /// has one or more super-reg register classes that are legal.
691 TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
692 if (*RC->superregclasses_begin() == 0)
694 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
695 E = RC->superregclasses_end(); I != E; ++I) {
696 const TargetRegisterClass *RRC = *I;
703 /// findRepresentativeClass - Return the largest legal super-reg register class
704 /// of the register class for the specified type and its associated "cost".
705 std::pair<const TargetRegisterClass*, uint8_t>
706 TargetLowering::findRepresentativeClass(EVT VT) const {
707 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
709 return std::make_pair(RC, 0);
710 const TargetRegisterClass *BestRC = RC;
711 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
712 E = RC->superregclasses_end(); I != E; ++I) {
713 const TargetRegisterClass *RRC = *I;
714 if (RRC->isASubClass() || !isLegalRC(RRC))
716 if (!hasLegalSuperRegRegClasses(RRC))
717 return std::make_pair(RRC, 1);
720 return std::make_pair(BestRC, 1);
724 /// computeRegisterProperties - Once all of the register classes are added,
725 /// this allows us to compute derived properties we expose.
726 void TargetLowering::computeRegisterProperties() {
727 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
728 "Too many value types for ValueTypeActions to hold!");
730 // Everything defaults to needing one register.
731 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
732 NumRegistersForVT[i] = 1;
733 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
735 // ...except isVoid, which doesn't need any registers.
736 NumRegistersForVT[MVT::isVoid] = 0;
738 // Find the largest integer register class.
739 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
740 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
741 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
743 // Every integer value type larger than this largest register takes twice as
744 // many registers to represent as the previous ValueType.
745 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
746 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
747 if (!ExpandedVT.isInteger())
749 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
750 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
751 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
752 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
755 // Inspect all of the ValueType's smaller than the largest integer
756 // register to see which ones need promotion.
757 unsigned LegalIntReg = LargestIntReg;
758 for (unsigned IntReg = LargestIntReg - 1;
759 IntReg >= (unsigned)MVT::i1; --IntReg) {
760 EVT IVT = (MVT::SimpleValueType)IntReg;
761 if (isTypeLegal(IVT)) {
762 LegalIntReg = IntReg;
764 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
765 (MVT::SimpleValueType)LegalIntReg;
766 ValueTypeActions.setTypeAction(IVT, Promote);
770 // ppcf128 type is really two f64's.
771 if (!isTypeLegal(MVT::ppcf128)) {
772 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
773 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
774 TransformToType[MVT::ppcf128] = MVT::f64;
775 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
778 // Decide how to handle f64. If the target does not have native f64 support,
779 // expand it to i64 and we will be generating soft float library calls.
780 if (!isTypeLegal(MVT::f64)) {
781 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
782 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
783 TransformToType[MVT::f64] = MVT::i64;
784 ValueTypeActions.setTypeAction(MVT::f64, Expand);
787 // Decide how to handle f32. If the target does not have native support for
788 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
789 if (!isTypeLegal(MVT::f32)) {
790 if (isTypeLegal(MVT::f64)) {
791 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
792 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
793 TransformToType[MVT::f32] = MVT::f64;
794 ValueTypeActions.setTypeAction(MVT::f32, Promote);
796 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
797 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
798 TransformToType[MVT::f32] = MVT::i32;
799 ValueTypeActions.setTypeAction(MVT::f32, Expand);
803 // Loop over all of the vector value types to see which need transformations.
804 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 if (isTypeLegal(VT)) continue;
809 // Determine if there is a legal wider type. If so, we should promote to
810 // that wider vector type.
811 EVT EltVT = VT.getVectorElementType();
812 unsigned NElts = VT.getVectorNumElements();
814 bool IsLegalWiderType = false;
815 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
816 EVT SVT = (MVT::SimpleValueType)nVT;
817 if (SVT.getVectorElementType() == EltVT &&
818 SVT.getVectorNumElements() > NElts &&
820 TransformToType[i] = SVT;
821 RegisterTypeForVT[i] = SVT;
822 NumRegistersForVT[i] = 1;
823 ValueTypeActions.setTypeAction(VT, Promote);
824 IsLegalWiderType = true;
828 if (IsLegalWiderType) continue;
833 unsigned NumIntermediates;
834 NumRegistersForVT[i] =
835 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
837 RegisterTypeForVT[i] = RegisterVT;
839 EVT NVT = VT.getPow2VectorType();
841 // Type is already a power of 2. The default action is to split.
842 TransformToType[i] = MVT::Other;
843 ValueTypeActions.setTypeAction(VT, Expand);
845 TransformToType[i] = NVT;
846 ValueTypeActions.setTypeAction(VT, Promote);
850 // Determine the 'representative' register class for each value type.
851 // An representative register class is the largest (meaning one which is
852 // not a sub-register class / subreg register class) legal register class for
853 // a group of value types. For example, on i386, i8, i16, and i32
854 // representative would be GR32; while on x86_64 it's GR64.
855 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
856 const TargetRegisterClass* RRC;
858 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
859 RepRegClassForVT[i] = RRC;
860 RepRegClassCostForVT[i] = Cost;
864 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
869 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
870 return PointerTy.SimpleTy;
873 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
874 return MVT::i32; // return the default value
877 /// getVectorTypeBreakdown - Vector types are broken down into some number of
878 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
879 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
880 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
882 /// This method returns the number of registers needed, and the VT for each
883 /// register. It also returns the VT and quantity of the intermediate values
884 /// before they are promoted/expanded.
886 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
888 unsigned &NumIntermediates,
889 EVT &RegisterVT) const {
890 unsigned NumElts = VT.getVectorNumElements();
892 // If there is a wider vector type with the same element type as this one,
893 // we should widen to that legal vector type. This handles things like
894 // <2 x float> -> <4 x float>.
895 if (NumElts != 1 && getTypeAction(VT) == Promote) {
896 RegisterVT = getTypeToTransformTo(Context, VT);
897 if (isTypeLegal(RegisterVT)) {
898 IntermediateVT = RegisterVT;
899 NumIntermediates = 1;
904 // Figure out the right, legal destination reg to copy into.
905 EVT EltTy = VT.getVectorElementType();
907 unsigned NumVectorRegs = 1;
909 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
910 // could break down into LHS/RHS like LegalizeDAG does.
911 if (!isPowerOf2_32(NumElts)) {
912 NumVectorRegs = NumElts;
916 // Divide the input until we get to a supported size. This will always
917 // end with a scalar if the target doesn't support vectors.
918 while (NumElts > 1 && !isTypeLegal(
919 EVT::getVectorVT(Context, EltTy, NumElts))) {
924 NumIntermediates = NumVectorRegs;
926 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
927 if (!isTypeLegal(NewVT))
929 IntermediateVT = NewVT;
931 EVT DestVT = getRegisterType(Context, NewVT);
933 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
934 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
936 // Otherwise, promotion or legal types use the same number of registers as
937 // the vector decimated to the appropriate level.
938 return NumVectorRegs;
941 /// Get the EVTs and ArgFlags collections that represent the legalized return
942 /// type of the given function. This does not require a DAG or a return value,
943 /// and is suitable for use before any DAGs for the function are constructed.
944 /// TODO: Move this out of TargetLowering.cpp.
945 void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
946 SmallVectorImpl<ISD::OutputArg> &Outs,
947 const TargetLowering &TLI,
948 SmallVectorImpl<uint64_t> *Offsets) {
949 SmallVector<EVT, 4> ValueVTs;
950 ComputeValueVTs(TLI, ReturnType, ValueVTs);
951 unsigned NumValues = ValueVTs.size();
952 if (NumValues == 0) return;
955 for (unsigned j = 0, f = NumValues; j != f; ++j) {
956 EVT VT = ValueVTs[j];
957 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
959 if (attr & Attribute::SExt)
960 ExtendKind = ISD::SIGN_EXTEND;
961 else if (attr & Attribute::ZExt)
962 ExtendKind = ISD::ZERO_EXTEND;
964 // FIXME: C calling convention requires the return type to be promoted to
965 // at least 32-bit. But this is not necessary for non-C calling
966 // conventions. The frontend should mark functions whose return values
967 // require promoting with signext or zeroext attributes.
968 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
969 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
970 if (VT.bitsLT(MinVT))
974 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
975 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
976 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
977 PartVT.getTypeForEVT(ReturnType->getContext()));
979 // 'inreg' on function refers to return value
980 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
981 if (attr & Attribute::InReg)
984 // Propagate extension type if any
985 if (attr & Attribute::SExt)
987 else if (attr & Attribute::ZExt)
990 for (unsigned i = 0; i < NumParts; ++i) {
991 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
993 Offsets->push_back(Offset);
1000 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1001 /// function arguments in the caller parameter area. This is the actual
1002 /// alignment, not its logarithm.
1003 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1004 return TD->getCallFrameTypeAlignment(Ty);
1007 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1008 /// current function. The returned value is a member of the
1009 /// MachineJumpTableInfo::JTEntryKind enum.
1010 unsigned TargetLowering::getJumpTableEncoding() const {
1011 // In non-pic modes, just use the address of a block.
1012 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1013 return MachineJumpTableInfo::EK_BlockAddress;
1015 // In PIC mode, if the target supports a GPRel32 directive, use it.
1016 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1017 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1019 // Otherwise, use a label difference.
1020 return MachineJumpTableInfo::EK_LabelDifference32;
1023 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1024 SelectionDAG &DAG) const {
1025 // If our PIC model is GP relative, use the global offset table as the base.
1026 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
1027 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1031 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1032 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1035 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1036 unsigned JTI,MCContext &Ctx) const{
1037 // The normal PIC reloc base is the label at the start of the jump table.
1038 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1042 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1043 // Assume that everything is safe in static mode.
1044 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1047 // In dynamic-no-pic mode, assume that known defined values are safe.
1048 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1050 !GA->getGlobal()->isDeclaration() &&
1051 !GA->getGlobal()->isWeakForLinker())
1054 // Otherwise assume nothing is safe.
1058 //===----------------------------------------------------------------------===//
1059 // Optimization Methods
1060 //===----------------------------------------------------------------------===//
1062 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1063 /// specified instruction is a constant integer. If so, check to see if there
1064 /// are any bits set in the constant that are not demanded. If so, shrink the
1065 /// constant and return true.
1066 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1067 const APInt &Demanded) {
1068 DebugLoc dl = Op.getDebugLoc();
1070 // FIXME: ISD::SELECT, ISD::SELECT_CC
1071 switch (Op.getOpcode()) {
1076 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1077 if (!C) return false;
1079 if (Op.getOpcode() == ISD::XOR &&
1080 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1083 // if we can expand it to have all bits set, do it
1084 if (C->getAPIntValue().intersects(~Demanded)) {
1085 EVT VT = Op.getValueType();
1086 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1087 DAG.getConstant(Demanded &
1090 return CombineTo(Op, New);
1100 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1101 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1102 /// cast, but it could be generalized for targets with other types of
1103 /// implicit widening casts.
1105 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1107 const APInt &Demanded,
1109 assert(Op.getNumOperands() == 2 &&
1110 "ShrinkDemandedOp only supports binary operators!");
1111 assert(Op.getNode()->getNumValues() == 1 &&
1112 "ShrinkDemandedOp only supports nodes with one result!");
1114 // Don't do this if the node has another user, which may require the
1116 if (!Op.getNode()->hasOneUse())
1119 // Search for the smallest integer type with free casts to and from
1120 // Op's type. For expedience, just check power-of-2 integer types.
1121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1122 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1123 if (!isPowerOf2_32(SmallVTBits))
1124 SmallVTBits = NextPowerOf2(SmallVTBits);
1125 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1126 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1127 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1128 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1129 // We found a type with free casts.
1130 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1131 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1132 Op.getNode()->getOperand(0)),
1133 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1134 Op.getNode()->getOperand(1)));
1135 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1136 return CombineTo(Op, Z);
1142 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1143 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1144 /// use this information to simplify Op, create a new simplified DAG node and
1145 /// return true, returning the original and new nodes in Old and New. Otherwise,
1146 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
1147 /// the expression (used to simplify the caller). The KnownZero/One bits may
1148 /// only be accurate for those bits in the DemandedMask.
1149 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1150 const APInt &DemandedMask,
1153 TargetLoweringOpt &TLO,
1154 unsigned Depth) const {
1155 unsigned BitWidth = DemandedMask.getBitWidth();
1156 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1157 "Mask size mismatches value type size!");
1158 APInt NewMask = DemandedMask;
1159 DebugLoc dl = Op.getDebugLoc();
1161 // Don't know anything.
1162 KnownZero = KnownOne = APInt(BitWidth, 0);
1164 // Other users may use these bits.
1165 if (!Op.getNode()->hasOneUse()) {
1167 // If not at the root, Just compute the KnownZero/KnownOne bits to
1168 // simplify things downstream.
1169 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
1172 // If this is the root being simplified, allow it to have multiple uses,
1173 // just set the NewMask to all bits.
1174 NewMask = APInt::getAllOnesValue(BitWidth);
1175 } else if (DemandedMask == 0) {
1176 // Not demanding any bits from Op.
1177 if (Op.getOpcode() != ISD::UNDEF)
1178 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1180 } else if (Depth == 6) { // Limit search depth.
1184 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1185 switch (Op.getOpcode()) {
1187 // We know all of the bits for a constant!
1188 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1189 KnownZero = ~KnownOne & NewMask;
1190 return false; // Don't fall through, will infinitely loop.
1192 // If the RHS is a constant, check to see if the LHS would be zero without
1193 // using the bits from the RHS. Below, we use knowledge about the RHS to
1194 // simplify the LHS, here we're using information from the LHS to simplify
1196 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1197 APInt LHSZero, LHSOne;
1198 // Do not increment Depth here; that can cause an infinite loop.
1199 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
1200 LHSZero, LHSOne, Depth);
1201 // If the LHS already has zeros where RHSC does, this and is dead.
1202 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1203 return TLO.CombineTo(Op, Op.getOperand(0));
1204 // If any of the set bits in the RHS are known zero on the LHS, shrink
1206 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1210 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1211 KnownOne, TLO, Depth+1))
1213 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1214 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1215 KnownZero2, KnownOne2, TLO, Depth+1))
1217 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1219 // If all of the demanded bits are known one on one side, return the other.
1220 // These bits cannot contribute to the result of the 'and'.
1221 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1222 return TLO.CombineTo(Op, Op.getOperand(0));
1223 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1224 return TLO.CombineTo(Op, Op.getOperand(1));
1225 // If all of the demanded bits in the inputs are known zeros, return zero.
1226 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1227 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1228 // If the RHS is a constant, see if we can simplify it.
1229 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1231 // If the operation can be done in a smaller type, do so.
1232 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1235 // Output known-1 bits are only known if set in both the LHS & RHS.
1236 KnownOne &= KnownOne2;
1237 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1238 KnownZero |= KnownZero2;
1241 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1242 KnownOne, TLO, Depth+1))
1244 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1245 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1246 KnownZero2, KnownOne2, TLO, Depth+1))
1248 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1250 // If all of the demanded bits are known zero on one side, return the other.
1251 // These bits cannot contribute to the result of the 'or'.
1252 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1253 return TLO.CombineTo(Op, Op.getOperand(0));
1254 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1255 return TLO.CombineTo(Op, Op.getOperand(1));
1256 // If all of the potentially set bits on one side are known to be set on
1257 // the other side, just use the 'other' side.
1258 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1259 return TLO.CombineTo(Op, Op.getOperand(0));
1260 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1261 return TLO.CombineTo(Op, Op.getOperand(1));
1262 // If the RHS is a constant, see if we can simplify it.
1263 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1265 // If the operation can be done in a smaller type, do so.
1266 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1269 // Output known-0 bits are only known if clear in both the LHS & RHS.
1270 KnownZero &= KnownZero2;
1271 // Output known-1 are known to be set if set in either the LHS | RHS.
1272 KnownOne |= KnownOne2;
1275 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1276 KnownOne, TLO, Depth+1))
1278 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1279 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1280 KnownOne2, TLO, Depth+1))
1282 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1284 // If all of the demanded bits are known zero on one side, return the other.
1285 // These bits cannot contribute to the result of the 'xor'.
1286 if ((KnownZero & NewMask) == NewMask)
1287 return TLO.CombineTo(Op, Op.getOperand(0));
1288 if ((KnownZero2 & NewMask) == NewMask)
1289 return TLO.CombineTo(Op, Op.getOperand(1));
1290 // If the operation can be done in a smaller type, do so.
1291 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1294 // If all of the unknown bits are known to be zero on one side or the other
1295 // (but not both) turn this into an *inclusive* or.
1296 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1297 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1298 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1302 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1303 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1304 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1305 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1307 // If all of the demanded bits on one side are known, and all of the set
1308 // bits on that side are also known to be set on the other side, turn this
1309 // into an AND, as we know the bits will be cleared.
1310 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1311 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1312 if ((KnownOne & KnownOne2) == KnownOne) {
1313 EVT VT = Op.getValueType();
1314 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1315 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1316 Op.getOperand(0), ANDC));
1320 // If the RHS is a constant, see if we can simplify it.
1321 // for XOR, we prefer to force bits to 1 if they will make a -1.
1322 // if we can't force bits, try to shrink constant
1323 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1324 APInt Expanded = C->getAPIntValue() | (~NewMask);
1325 // if we can expand it to have all bits set, do it
1326 if (Expanded.isAllOnesValue()) {
1327 if (Expanded != C->getAPIntValue()) {
1328 EVT VT = Op.getValueType();
1329 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1330 TLO.DAG.getConstant(Expanded, VT));
1331 return TLO.CombineTo(Op, New);
1333 // if it already has all the bits set, nothing to change
1334 // but don't shrink either!
1335 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1340 KnownZero = KnownZeroOut;
1341 KnownOne = KnownOneOut;
1344 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1345 KnownOne, TLO, Depth+1))
1347 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1348 KnownOne2, TLO, Depth+1))
1350 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1351 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1353 // If the operands are constants, see if we can simplify them.
1354 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1357 // Only known if known in both the LHS and RHS.
1358 KnownOne &= KnownOne2;
1359 KnownZero &= KnownZero2;
1361 case ISD::SELECT_CC:
1362 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1363 KnownOne, TLO, Depth+1))
1365 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1366 KnownOne2, TLO, Depth+1))
1368 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1369 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1371 // If the operands are constants, see if we can simplify them.
1372 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1375 // Only known if known in both the LHS and RHS.
1376 KnownOne &= KnownOne2;
1377 KnownZero &= KnownZero2;
1380 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1381 unsigned ShAmt = SA->getZExtValue();
1382 SDValue InOp = Op.getOperand(0);
1384 // If the shift count is an invalid immediate, don't do anything.
1385 if (ShAmt >= BitWidth)
1388 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1389 // single shift. We can do this if the bottom bits (which are shifted
1390 // out) are never demanded.
1391 if (InOp.getOpcode() == ISD::SRL &&
1392 isa<ConstantSDNode>(InOp.getOperand(1))) {
1393 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1394 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1395 unsigned Opc = ISD::SHL;
1396 int Diff = ShAmt-C1;
1403 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1404 EVT VT = Op.getValueType();
1405 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1406 InOp.getOperand(0), NewSA));
1410 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1411 KnownZero, KnownOne, TLO, Depth+1))
1414 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1415 // are not demanded. This will likely allow the anyext to be folded away.
1416 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1417 SDValue InnerOp = InOp.getNode()->getOperand(0);
1418 EVT InnerVT = InnerOp.getValueType();
1419 if ((APInt::getHighBitsSet(BitWidth,
1420 BitWidth - InnerVT.getSizeInBits()) &
1421 DemandedMask) == 0 &&
1422 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1423 EVT ShTy = getShiftAmountTy(InnerVT);
1424 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1427 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1428 TLO.DAG.getConstant(ShAmt, ShTy));
1431 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1436 KnownZero <<= SA->getZExtValue();
1437 KnownOne <<= SA->getZExtValue();
1438 // low bits known zero.
1439 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1443 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1444 EVT VT = Op.getValueType();
1445 unsigned ShAmt = SA->getZExtValue();
1446 unsigned VTSize = VT.getSizeInBits();
1447 SDValue InOp = Op.getOperand(0);
1449 // If the shift count is an invalid immediate, don't do anything.
1450 if (ShAmt >= BitWidth)
1453 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1454 // single shift. We can do this if the top bits (which are shifted out)
1455 // are never demanded.
1456 if (InOp.getOpcode() == ISD::SHL &&
1457 isa<ConstantSDNode>(InOp.getOperand(1))) {
1458 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1459 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1460 unsigned Opc = ISD::SRL;
1461 int Diff = ShAmt-C1;
1468 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1469 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1470 InOp.getOperand(0), NewSA));
1474 // Compute the new bits that are at the top now.
1475 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1476 KnownZero, KnownOne, TLO, Depth+1))
1478 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1479 KnownZero = KnownZero.lshr(ShAmt);
1480 KnownOne = KnownOne.lshr(ShAmt);
1482 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1483 KnownZero |= HighBits; // High bits known zero.
1487 // If this is an arithmetic shift right and only the low-bit is set, we can
1488 // always convert this into a logical shr, even if the shift amount is
1489 // variable. The low bit of the shift cannot be an input sign bit unless
1490 // the shift amount is >= the size of the datatype, which is undefined.
1491 if (DemandedMask == 1)
1492 return TLO.CombineTo(Op,
1493 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1494 Op.getOperand(0), Op.getOperand(1)));
1496 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1497 EVT VT = Op.getValueType();
1498 unsigned ShAmt = SA->getZExtValue();
1500 // If the shift count is an invalid immediate, don't do anything.
1501 if (ShAmt >= BitWidth)
1504 APInt InDemandedMask = (NewMask << ShAmt);
1506 // If any of the demanded bits are produced by the sign extension, we also
1507 // demand the input sign bit.
1508 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1509 if (HighBits.intersects(NewMask))
1510 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1512 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1513 KnownZero, KnownOne, TLO, Depth+1))
1515 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1516 KnownZero = KnownZero.lshr(ShAmt);
1517 KnownOne = KnownOne.lshr(ShAmt);
1519 // Handle the sign bit, adjusted to where it is now in the mask.
1520 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1522 // If the input sign bit is known to be zero, or if none of the top bits
1523 // are demanded, turn this into an unsigned shift right.
1524 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1525 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1528 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1529 KnownOne |= HighBits;
1533 case ISD::SIGN_EXTEND_INREG: {
1534 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1536 // Sign extension. Compute the demanded bits in the result that are not
1537 // present in the input.
1539 APInt::getHighBitsSet(BitWidth,
1540 BitWidth - EVT.getScalarType().getSizeInBits());
1542 // If none of the extended bits are demanded, eliminate the sextinreg.
1543 if ((NewBits & NewMask) == 0)
1544 return TLO.CombineTo(Op, Op.getOperand(0));
1547 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth);
1548 APInt InputDemandedBits =
1549 APInt::getLowBitsSet(BitWidth,
1550 EVT.getScalarType().getSizeInBits()) &
1553 // Since the sign extended bits are demanded, we know that the sign
1555 InputDemandedBits |= InSignBit;
1557 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1558 KnownZero, KnownOne, TLO, Depth+1))
1560 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1562 // If the sign bit of the input is known set or clear, then we know the
1563 // top bits of the result.
1565 // If the input sign bit is known zero, convert this into a zero extension.
1566 if (KnownZero.intersects(InSignBit))
1567 return TLO.CombineTo(Op,
1568 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1570 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1571 KnownOne |= NewBits;
1572 KnownZero &= ~NewBits;
1573 } else { // Input sign bit unknown
1574 KnownZero &= ~NewBits;
1575 KnownOne &= ~NewBits;
1579 case ISD::ZERO_EXTEND: {
1580 unsigned OperandBitWidth =
1581 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1582 APInt InMask = NewMask.trunc(OperandBitWidth);
1584 // If none of the top bits are demanded, convert this into an any_extend.
1586 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1587 if (!NewBits.intersects(NewMask))
1588 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1592 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1593 KnownZero, KnownOne, TLO, Depth+1))
1595 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1596 KnownZero = KnownZero.zext(BitWidth);
1597 KnownOne = KnownOne.zext(BitWidth);
1598 KnownZero |= NewBits;
1601 case ISD::SIGN_EXTEND: {
1602 EVT InVT = Op.getOperand(0).getValueType();
1603 unsigned InBits = InVT.getScalarType().getSizeInBits();
1604 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1605 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1606 APInt NewBits = ~InMask & NewMask;
1608 // If none of the top bits are demanded, convert this into an any_extend.
1610 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1614 // Since some of the sign extended bits are demanded, we know that the sign
1616 APInt InDemandedBits = InMask & NewMask;
1617 InDemandedBits |= InSignBit;
1618 InDemandedBits = InDemandedBits.trunc(InBits);
1620 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1621 KnownOne, TLO, Depth+1))
1623 KnownZero = KnownZero.zext(BitWidth);
1624 KnownOne = KnownOne.zext(BitWidth);
1626 // If the sign bit is known zero, convert this to a zero extend.
1627 if (KnownZero.intersects(InSignBit))
1628 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1632 // If the sign bit is known one, the top bits match.
1633 if (KnownOne.intersects(InSignBit)) {
1634 KnownOne |= NewBits;
1635 KnownZero &= ~NewBits;
1636 } else { // Otherwise, top bits aren't known.
1637 KnownOne &= ~NewBits;
1638 KnownZero &= ~NewBits;
1642 case ISD::ANY_EXTEND: {
1643 unsigned OperandBitWidth =
1644 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1645 APInt InMask = NewMask.trunc(OperandBitWidth);
1646 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1647 KnownZero, KnownOne, TLO, Depth+1))
1649 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1650 KnownZero = KnownZero.zext(BitWidth);
1651 KnownOne = KnownOne.zext(BitWidth);
1654 case ISD::TRUNCATE: {
1655 // Simplify the input, using demanded bit information, and compute the known
1656 // zero/one bits live out.
1657 unsigned OperandBitWidth =
1658 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1659 APInt TruncMask = NewMask.zext(OperandBitWidth);
1660 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1661 KnownZero, KnownOne, TLO, Depth+1))
1663 KnownZero = KnownZero.trunc(BitWidth);
1664 KnownOne = KnownOne.trunc(BitWidth);
1666 // If the input is only used by this truncate, see if we can shrink it based
1667 // on the known demanded bits.
1668 if (Op.getOperand(0).getNode()->hasOneUse()) {
1669 SDValue In = Op.getOperand(0);
1670 switch (In.getOpcode()) {
1673 // Shrink SRL by a constant if none of the high bits shifted in are
1675 if (TLO.LegalTypes() &&
1676 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1677 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1680 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1683 SDValue Shift = In.getOperand(1);
1684 if (TLO.LegalTypes()) {
1685 uint64_t ShVal = ShAmt->getZExtValue();
1687 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1690 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1691 OperandBitWidth - BitWidth);
1692 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1694 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1695 // None of the shifted in bits are needed. Add a truncate of the
1696 // shift input, then shift it.
1697 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1700 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1709 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1712 case ISD::AssertZext: {
1713 // Demand all the bits of the input that are demanded in the output.
1714 // The low bits are obvious; the high bits are demanded because we're
1715 // asserting that they're zero here.
1716 if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
1717 KnownZero, KnownOne, TLO, Depth+1))
1719 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1721 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1722 APInt InMask = APInt::getLowBitsSet(BitWidth,
1723 VT.getSizeInBits());
1724 KnownZero |= ~InMask & NewMask;
1729 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1730 // is demanded, turn this into a FGETSIGN.
1731 if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1732 Op.getOperand(0).getValueType().isFloatingPoint() &&
1733 !Op.getOperand(0).getValueType().isVector()) {
1734 // Only do this xform if FGETSIGN is valid or if before legalize.
1735 if (TLO.isBeforeLegalize() ||
1736 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1737 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1738 // place. We expect the SHL to be eliminated by other optimizations.
1739 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(),
1741 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1742 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1743 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1753 // Add, Sub, and Mul don't demand any bits in positions beyond that
1754 // of the highest bit demanded of them.
1755 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1756 BitWidth - NewMask.countLeadingZeros());
1757 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1758 KnownOne2, TLO, Depth+1))
1760 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1761 KnownOne2, TLO, Depth+1))
1763 // See if the operation should be performed at a smaller bit width.
1764 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1769 // Just use ComputeMaskedBits to compute output bits.
1770 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1774 // If we know the value of all of the demanded bits, return this as a
1776 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1777 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1782 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1783 /// in Mask are known to be either zero or one and return them in the
1784 /// KnownZero/KnownOne bitsets.
1785 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1789 const SelectionDAG &DAG,
1790 unsigned Depth) const {
1791 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1792 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1793 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1794 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1795 "Should use MaskedValueIsZero if you don't know whether Op"
1796 " is a target node!");
1797 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1800 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1801 /// targets that want to expose additional information about sign bits to the
1803 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1804 unsigned Depth) const {
1805 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1806 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1807 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1808 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1809 "Should use ComputeNumSignBits if you don't know whether Op"
1810 " is a target node!");
1814 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1815 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1816 /// determine which bit is set.
1818 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1819 // A left-shift of a constant one will have exactly one bit set, because
1820 // shifting the bit off the end is undefined.
1821 if (Val.getOpcode() == ISD::SHL)
1822 if (ConstantSDNode *C =
1823 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1824 if (C->getAPIntValue() == 1)
1827 // Similarly, a right-shift of a constant sign-bit will have exactly
1829 if (Val.getOpcode() == ISD::SRL)
1830 if (ConstantSDNode *C =
1831 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1832 if (C->getAPIntValue().isSignBit())
1835 // More could be done here, though the above checks are enough
1836 // to handle some common cases.
1838 // Fall back to ComputeMaskedBits to catch other known cases.
1839 EVT OpVT = Val.getValueType();
1840 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1841 APInt Mask = APInt::getAllOnesValue(BitWidth);
1842 APInt KnownZero, KnownOne;
1843 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1844 return (KnownZero.countPopulation() == BitWidth - 1) &&
1845 (KnownOne.countPopulation() == 1);
1848 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1849 /// and cc. If it is unable to simplify it, return a null SDValue.
1851 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1852 ISD::CondCode Cond, bool foldBooleans,
1853 DAGCombinerInfo &DCI, DebugLoc dl) const {
1854 SelectionDAG &DAG = DCI.DAG;
1856 // These setcc operations always fold.
1860 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1862 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1865 // Ensure that the constant occurs on the RHS, and fold constant
1867 if (isa<ConstantSDNode>(N0.getNode()))
1868 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1870 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1871 const APInt &C1 = N1C->getAPIntValue();
1873 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1874 // equality comparison, then we're just comparing whether X itself is
1876 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1877 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1878 N0.getOperand(1).getOpcode() == ISD::Constant) {
1880 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1881 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1882 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1883 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1884 // (srl (ctlz x), 5) == 0 -> X != 0
1885 // (srl (ctlz x), 5) != 1 -> X != 0
1888 // (srl (ctlz x), 5) != 0 -> X == 0
1889 // (srl (ctlz x), 5) == 1 -> X == 0
1892 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1893 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1899 // Look through truncs that don't change the value of a ctpop.
1900 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1901 CTPOP = N0.getOperand(0);
1903 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1904 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1905 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1906 EVT CTVT = CTPOP.getValueType();
1907 SDValue CTOp = CTPOP.getOperand(0);
1909 // (ctpop x) u< 2 -> (x & x-1) == 0
1910 // (ctpop x) u> 1 -> (x & x-1) != 0
1911 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1912 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1913 DAG.getConstant(1, CTVT));
1914 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1915 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1916 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1919 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1922 // (zext x) == C --> x == (trunc C)
1923 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1924 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1925 unsigned MinBits = N0.getValueSizeInBits();
1927 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1929 MinBits = N0->getOperand(0).getValueSizeInBits();
1930 PreZExt = N0->getOperand(0);
1931 } else if (N0->getOpcode() == ISD::AND) {
1932 // DAGCombine turns costly ZExts into ANDs
1933 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1934 if ((C->getAPIntValue()+1).isPowerOf2()) {
1935 MinBits = C->getAPIntValue().countTrailingOnes();
1936 PreZExt = N0->getOperand(0);
1938 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1940 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1941 MinBits = LN0->getMemoryVT().getSizeInBits();
1946 // Make sure we're not loosing bits from the constant.
1947 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
1948 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1949 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1950 // Will get folded away.
1951 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1952 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1953 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1958 // If the LHS is '(and load, const)', the RHS is 0,
1959 // the test is for equality or unsigned, and all 1 bits of the const are
1960 // in the same partial word, see if we can shorten the load.
1961 if (DCI.isBeforeLegalize() &&
1962 N0.getOpcode() == ISD::AND && C1 == 0 &&
1963 N0.getNode()->hasOneUse() &&
1964 isa<LoadSDNode>(N0.getOperand(0)) &&
1965 N0.getOperand(0).getNode()->hasOneUse() &&
1966 isa<ConstantSDNode>(N0.getOperand(1))) {
1967 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1969 unsigned bestWidth = 0, bestOffset = 0;
1970 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1971 unsigned origWidth = N0.getValueType().getSizeInBits();
1972 unsigned maskWidth = origWidth;
1973 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1974 // 8 bits, but have to be careful...
1975 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1976 origWidth = Lod->getMemoryVT().getSizeInBits();
1978 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1979 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1980 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1981 for (unsigned offset=0; offset<origWidth/width; offset++) {
1982 if ((newMask & Mask) == Mask) {
1983 if (!TD->isLittleEndian())
1984 bestOffset = (origWidth/width - offset - 1) * (width/8);
1986 bestOffset = (uint64_t)offset * (width/8);
1987 bestMask = Mask.lshr(offset * (width/8) * 8);
1991 newMask = newMask << width;
1996 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1997 if (newVT.isRound()) {
1998 EVT PtrType = Lod->getOperand(1).getValueType();
1999 SDValue Ptr = Lod->getBasePtr();
2000 if (bestOffset != 0)
2001 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2002 DAG.getConstant(bestOffset, PtrType));
2003 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2004 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2005 Lod->getPointerInfo().getWithOffset(bestOffset),
2006 false, false, NewAlign);
2007 return DAG.getSetCC(dl, VT,
2008 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2009 DAG.getConstant(bestMask.trunc(bestWidth),
2011 DAG.getConstant(0LL, newVT), Cond);
2016 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2017 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2018 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2020 // If the comparison constant has bits in the upper part, the
2021 // zero-extended value could never match.
2022 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2023 C1.getBitWidth() - InSize))) {
2027 case ISD::SETEQ: return DAG.getConstant(0, VT);
2030 case ISD::SETNE: return DAG.getConstant(1, VT);
2033 // True if the sign bit of C1 is set.
2034 return DAG.getConstant(C1.isNegative(), VT);
2037 // True if the sign bit of C1 isn't set.
2038 return DAG.getConstant(C1.isNonNegative(), VT);
2044 // Otherwise, we can perform the comparison with the low bits.
2052 EVT newVT = N0.getOperand(0).getValueType();
2053 if (DCI.isBeforeLegalizeOps() ||
2054 (isOperationLegal(ISD::SETCC, newVT) &&
2055 getCondCodeAction(Cond, newVT)==Legal))
2056 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2057 DAG.getConstant(C1.trunc(InSize), newVT),
2062 break; // todo, be more careful with signed comparisons
2064 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2065 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2066 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2067 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2068 EVT ExtDstTy = N0.getValueType();
2069 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2071 // If the constant doesn't fit into the number of bits for the source of
2072 // the sign extension, it is impossible for both sides to be equal.
2073 if (C1.getMinSignedBits() > ExtSrcTyBits)
2074 return DAG.getConstant(Cond == ISD::SETNE, VT);
2077 EVT Op0Ty = N0.getOperand(0).getValueType();
2078 if (Op0Ty == ExtSrcTy) {
2079 ZextOp = N0.getOperand(0);
2081 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2082 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2083 DAG.getConstant(Imm, Op0Ty));
2085 if (!DCI.isCalledByLegalizer())
2086 DCI.AddToWorklist(ZextOp.getNode());
2087 // Otherwise, make this a use of a zext.
2088 return DAG.getSetCC(dl, VT, ZextOp,
2089 DAG.getConstant(C1 & APInt::getLowBitsSet(
2094 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2095 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2096 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2097 if (N0.getOpcode() == ISD::SETCC &&
2098 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2099 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2101 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2102 // Invert the condition.
2103 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2104 CC = ISD::getSetCCInverse(CC,
2105 N0.getOperand(0).getValueType().isInteger());
2106 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2109 if ((N0.getOpcode() == ISD::XOR ||
2110 (N0.getOpcode() == ISD::AND &&
2111 N0.getOperand(0).getOpcode() == ISD::XOR &&
2112 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2113 isa<ConstantSDNode>(N0.getOperand(1)) &&
2114 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2115 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2116 // can only do this if the top bits are known zero.
2117 unsigned BitWidth = N0.getValueSizeInBits();
2118 if (DAG.MaskedValueIsZero(N0,
2119 APInt::getHighBitsSet(BitWidth,
2121 // Okay, get the un-inverted input value.
2123 if (N0.getOpcode() == ISD::XOR)
2124 Val = N0.getOperand(0);
2126 assert(N0.getOpcode() == ISD::AND &&
2127 N0.getOperand(0).getOpcode() == ISD::XOR);
2128 // ((X^1)&1)^1 -> X & 1
2129 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2130 N0.getOperand(0).getOperand(0),
2134 return DAG.getSetCC(dl, VT, Val, N1,
2135 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2137 } else if (N1C->getAPIntValue() == 1 &&
2139 getBooleanContents() == ZeroOrOneBooleanContent)) {
2141 if (Op0.getOpcode() == ISD::TRUNCATE)
2142 Op0 = Op0.getOperand(0);
2144 if ((Op0.getOpcode() == ISD::XOR) &&
2145 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2146 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2147 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2148 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2149 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2151 } else if (Op0.getOpcode() == ISD::AND &&
2152 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2153 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2154 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2155 if (Op0.getValueType().bitsGT(VT))
2156 Op0 = DAG.getNode(ISD::AND, dl, VT,
2157 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2158 DAG.getConstant(1, VT));
2159 else if (Op0.getValueType().bitsLT(VT))
2160 Op0 = DAG.getNode(ISD::AND, dl, VT,
2161 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2162 DAG.getConstant(1, VT));
2164 return DAG.getSetCC(dl, VT, Op0,
2165 DAG.getConstant(0, Op0.getValueType()),
2166 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2171 APInt MinVal, MaxVal;
2172 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2173 if (ISD::isSignedIntSetCC(Cond)) {
2174 MinVal = APInt::getSignedMinValue(OperandBitSize);
2175 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2177 MinVal = APInt::getMinValue(OperandBitSize);
2178 MaxVal = APInt::getMaxValue(OperandBitSize);
2181 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2182 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2183 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2184 // X >= C0 --> X > (C0-1)
2185 return DAG.getSetCC(dl, VT, N0,
2186 DAG.getConstant(C1-1, N1.getValueType()),
2187 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2190 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2191 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2192 // X <= C0 --> X < (C0+1)
2193 return DAG.getSetCC(dl, VT, N0,
2194 DAG.getConstant(C1+1, N1.getValueType()),
2195 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2198 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2199 return DAG.getConstant(0, VT); // X < MIN --> false
2200 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2201 return DAG.getConstant(1, VT); // X >= MIN --> true
2202 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2203 return DAG.getConstant(0, VT); // X > MAX --> false
2204 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2205 return DAG.getConstant(1, VT); // X <= MAX --> true
2207 // Canonicalize setgt X, Min --> setne X, Min
2208 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2209 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2210 // Canonicalize setlt X, Max --> setne X, Max
2211 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2212 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2214 // If we have setult X, 1, turn it into seteq X, 0
2215 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2216 return DAG.getSetCC(dl, VT, N0,
2217 DAG.getConstant(MinVal, N0.getValueType()),
2219 // If we have setugt X, Max-1, turn it into seteq X, Max
2220 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2221 return DAG.getSetCC(dl, VT, N0,
2222 DAG.getConstant(MaxVal, N0.getValueType()),
2225 // If we have "setcc X, C0", check to see if we can shrink the immediate
2228 // SETUGT X, SINTMAX -> SETLT X, 0
2229 if (Cond == ISD::SETUGT &&
2230 C1 == APInt::getSignedMaxValue(OperandBitSize))
2231 return DAG.getSetCC(dl, VT, N0,
2232 DAG.getConstant(0, N1.getValueType()),
2235 // SETULT X, SINTMIN -> SETGT X, -1
2236 if (Cond == ISD::SETULT &&
2237 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2238 SDValue ConstMinusOne =
2239 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2241 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2244 // Fold bit comparisons when we can.
2245 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2246 (VT == N0.getValueType() ||
2247 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2248 N0.getOpcode() == ISD::AND)
2249 if (ConstantSDNode *AndRHS =
2250 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2251 EVT ShiftTy = DCI.isBeforeLegalize() ?
2252 getPointerTy() : getShiftAmountTy(N0.getValueType());
2253 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2254 // Perform the xform if the AND RHS is a single bit.
2255 if (AndRHS->getAPIntValue().isPowerOf2()) {
2256 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2257 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2258 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2260 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2261 // (X & 8) == 8 --> (X & 8) >> 3
2262 // Perform the xform if C1 is a single bit.
2263 if (C1.isPowerOf2()) {
2264 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2265 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2266 DAG.getConstant(C1.logBase2(), ShiftTy)));
2272 if (isa<ConstantFPSDNode>(N0.getNode())) {
2273 // Constant fold or commute setcc.
2274 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2275 if (O.getNode()) return O;
2276 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2277 // If the RHS of an FP comparison is a constant, simplify it away in
2279 if (CFP->getValueAPF().isNaN()) {
2280 // If an operand is known to be a nan, we can fold it.
2281 switch (ISD::getUnorderedFlavor(Cond)) {
2282 default: llvm_unreachable("Unknown flavor!");
2283 case 0: // Known false.
2284 return DAG.getConstant(0, VT);
2285 case 1: // Known true.
2286 return DAG.getConstant(1, VT);
2287 case 2: // Undefined.
2288 return DAG.getUNDEF(VT);
2292 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2293 // constant if knowing that the operand is non-nan is enough. We prefer to
2294 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2296 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2297 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2299 // If the condition is not legal, see if we can find an equivalent one
2301 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2302 // If the comparison was an awkward floating-point == or != and one of
2303 // the comparison operands is infinity or negative infinity, convert the
2304 // condition to a less-awkward <= or >=.
2305 if (CFP->getValueAPF().isInfinity()) {
2306 if (CFP->getValueAPF().isNegative()) {
2307 if (Cond == ISD::SETOEQ &&
2308 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2309 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2310 if (Cond == ISD::SETUEQ &&
2311 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2312 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2313 if (Cond == ISD::SETUNE &&
2314 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2315 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2316 if (Cond == ISD::SETONE &&
2317 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2318 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2320 if (Cond == ISD::SETOEQ &&
2321 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2322 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2323 if (Cond == ISD::SETUEQ &&
2324 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2325 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2326 if (Cond == ISD::SETUNE &&
2327 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2328 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2329 if (Cond == ISD::SETONE &&
2330 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2331 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2338 // We can always fold X == X for integer setcc's.
2339 if (N0.getValueType().isInteger())
2340 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2341 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2342 if (UOF == 2) // FP operators that are undefined on NaNs.
2343 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2344 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2345 return DAG.getConstant(UOF, VT);
2346 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2347 // if it is not already.
2348 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2349 if (NewCond != Cond)
2350 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2353 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2354 N0.getValueType().isInteger()) {
2355 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2356 N0.getOpcode() == ISD::XOR) {
2357 // Simplify (X+Y) == (X+Z) --> Y == Z
2358 if (N0.getOpcode() == N1.getOpcode()) {
2359 if (N0.getOperand(0) == N1.getOperand(0))
2360 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2361 if (N0.getOperand(1) == N1.getOperand(1))
2362 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2363 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2364 // If X op Y == Y op X, try other combinations.
2365 if (N0.getOperand(0) == N1.getOperand(1))
2366 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2368 if (N0.getOperand(1) == N1.getOperand(0))
2369 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2374 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2375 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2376 // Turn (X+C1) == C2 --> X == C2-C1
2377 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2378 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2379 DAG.getConstant(RHSC->getAPIntValue()-
2380 LHSR->getAPIntValue(),
2381 N0.getValueType()), Cond);
2384 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2385 if (N0.getOpcode() == ISD::XOR)
2386 // If we know that all of the inverted bits are zero, don't bother
2387 // performing the inversion.
2388 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2390 DAG.getSetCC(dl, VT, N0.getOperand(0),
2391 DAG.getConstant(LHSR->getAPIntValue() ^
2392 RHSC->getAPIntValue(),
2397 // Turn (C1-X) == C2 --> X == C1-C2
2398 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2399 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2401 DAG.getSetCC(dl, VT, N0.getOperand(1),
2402 DAG.getConstant(SUBC->getAPIntValue() -
2403 RHSC->getAPIntValue(),
2410 // Simplify (X+Z) == X --> Z == 0
2411 if (N0.getOperand(0) == N1)
2412 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2413 DAG.getConstant(0, N0.getValueType()), Cond);
2414 if (N0.getOperand(1) == N1) {
2415 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2416 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2417 DAG.getConstant(0, N0.getValueType()), Cond);
2418 else if (N0.getNode()->hasOneUse()) {
2419 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2420 // (Z-X) == X --> Z == X<<1
2421 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2423 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2424 if (!DCI.isCalledByLegalizer())
2425 DCI.AddToWorklist(SH.getNode());
2426 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2431 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2432 N1.getOpcode() == ISD::XOR) {
2433 // Simplify X == (X+Z) --> Z == 0
2434 if (N1.getOperand(0) == N0) {
2435 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2436 DAG.getConstant(0, N1.getValueType()), Cond);
2437 } else if (N1.getOperand(1) == N0) {
2438 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2439 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2440 DAG.getConstant(0, N1.getValueType()), Cond);
2441 } else if (N1.getNode()->hasOneUse()) {
2442 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2443 // X == (Z-X) --> X<<1 == Z
2444 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2445 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2446 if (!DCI.isCalledByLegalizer())
2447 DCI.AddToWorklist(SH.getNode());
2448 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2453 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2454 // Note that where y is variable and is known to have at most
2455 // one bit set (for example, if it is z&1) we cannot do this;
2456 // the expressions are not equivalent when y==0.
2457 if (N0.getOpcode() == ISD::AND)
2458 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2459 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2460 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2461 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2462 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2465 if (N1.getOpcode() == ISD::AND)
2466 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2467 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2468 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2469 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2470 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2475 // Fold away ALL boolean setcc's.
2477 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2479 default: llvm_unreachable("Unknown integer setcc!");
2480 case ISD::SETEQ: // X == Y -> ~(X^Y)
2481 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2482 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2483 if (!DCI.isCalledByLegalizer())
2484 DCI.AddToWorklist(Temp.getNode());
2486 case ISD::SETNE: // X != Y --> (X^Y)
2487 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2489 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2490 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2491 Temp = DAG.getNOT(dl, N0, MVT::i1);
2492 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2493 if (!DCI.isCalledByLegalizer())
2494 DCI.AddToWorklist(Temp.getNode());
2496 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2497 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2498 Temp = DAG.getNOT(dl, N1, MVT::i1);
2499 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2500 if (!DCI.isCalledByLegalizer())
2501 DCI.AddToWorklist(Temp.getNode());
2503 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2504 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2505 Temp = DAG.getNOT(dl, N0, MVT::i1);
2506 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2507 if (!DCI.isCalledByLegalizer())
2508 DCI.AddToWorklist(Temp.getNode());
2510 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2511 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2512 Temp = DAG.getNOT(dl, N1, MVT::i1);
2513 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2516 if (VT != MVT::i1) {
2517 if (!DCI.isCalledByLegalizer())
2518 DCI.AddToWorklist(N0.getNode());
2519 // FIXME: If running after legalize, we probably can't do this.
2520 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2525 // Could not fold it.
2529 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2530 /// node is a GlobalAddress + offset.
2531 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2532 int64_t &Offset) const {
2533 if (isa<GlobalAddressSDNode>(N)) {
2534 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2535 GA = GASD->getGlobal();
2536 Offset += GASD->getOffset();
2540 if (N->getOpcode() == ISD::ADD) {
2541 SDValue N1 = N->getOperand(0);
2542 SDValue N2 = N->getOperand(1);
2543 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2544 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2546 Offset += V->getSExtValue();
2549 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2550 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2552 Offset += V->getSExtValue();
2562 SDValue TargetLowering::
2563 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2564 // Default implementation: no optimization.
2568 //===----------------------------------------------------------------------===//
2569 // Inline Assembler Implementation Methods
2570 //===----------------------------------------------------------------------===//
2573 TargetLowering::ConstraintType
2574 TargetLowering::getConstraintType(const std::string &Constraint) const {
2575 // FIXME: lots more standard ones to handle.
2576 if (Constraint.size() == 1) {
2577 switch (Constraint[0]) {
2579 case 'r': return C_RegisterClass;
2581 case 'o': // offsetable
2582 case 'V': // not offsetable
2584 case 'i': // Simple Integer or Relocatable Constant
2585 case 'n': // Simple Integer
2586 case 'E': // Floating Point Constant
2587 case 'F': // Floating Point Constant
2588 case 's': // Relocatable Constant
2589 case 'p': // Address.
2590 case 'X': // Allow ANY value.
2591 case 'I': // Target registers.
2605 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2606 Constraint[Constraint.size()-1] == '}')
2611 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2612 /// with another that has more specific requirements based on the type of the
2613 /// corresponding operand.
2614 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2615 if (ConstraintVT.isInteger())
2617 if (ConstraintVT.isFloatingPoint())
2618 return "f"; // works for many targets
2622 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2623 /// vector. If it is invalid, don't add anything to Ops.
2624 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2625 char ConstraintLetter,
2626 std::vector<SDValue> &Ops,
2627 SelectionDAG &DAG) const {
2628 switch (ConstraintLetter) {
2630 case 'X': // Allows any operand; labels (basic block) use this.
2631 if (Op.getOpcode() == ISD::BasicBlock) {
2636 case 'i': // Simple Integer or Relocatable Constant
2637 case 'n': // Simple Integer
2638 case 's': { // Relocatable Constant
2639 // These operands are interested in values of the form (GV+C), where C may
2640 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2641 // is possible and fine if either GV or C are missing.
2642 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2643 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2645 // If we have "(add GV, C)", pull out GV/C
2646 if (Op.getOpcode() == ISD::ADD) {
2647 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2648 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2649 if (C == 0 || GA == 0) {
2650 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2651 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2653 if (C == 0 || GA == 0)
2657 // If we find a valid operand, map to the TargetXXX version so that the
2658 // value itself doesn't get selected.
2659 if (GA) { // Either &GV or &GV+C
2660 if (ConstraintLetter != 'n') {
2661 int64_t Offs = GA->getOffset();
2662 if (C) Offs += C->getZExtValue();
2663 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2664 C ? C->getDebugLoc() : DebugLoc(),
2665 Op.getValueType(), Offs));
2669 if (C) { // just C, no GV.
2670 // Simple constants are not allowed for 's'.
2671 if (ConstraintLetter != 's') {
2672 // gcc prints these as sign extended. Sign extend value to 64 bits
2673 // now; without this it would get ZExt'd later in
2674 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2675 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2685 std::vector<unsigned> TargetLowering::
2686 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2688 return std::vector<unsigned>();
2692 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2693 getRegForInlineAsmConstraint(const std::string &Constraint,
2695 if (Constraint[0] != '{')
2696 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2697 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2699 // Remove the braces from around the name.
2700 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2702 // Figure out which register class contains this reg.
2703 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2704 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2705 E = RI->regclass_end(); RCI != E; ++RCI) {
2706 const TargetRegisterClass *RC = *RCI;
2708 // If none of the value types for this register class are valid, we
2709 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2710 bool isLegal = false;
2711 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2713 if (isTypeLegal(*I)) {
2719 if (!isLegal) continue;
2721 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2723 if (RegName.equals_lower(RI->getName(*I)))
2724 return std::make_pair(*I, RC);
2728 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2731 //===----------------------------------------------------------------------===//
2732 // Constraint Selection.
2734 /// isMatchingInputConstraint - Return true of this is an input operand that is
2735 /// a matching constraint like "4".
2736 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2737 assert(!ConstraintCode.empty() && "No known constraint!");
2738 return isdigit(ConstraintCode[0]);
2741 /// getMatchedOperand - If this is an input matching constraint, this method
2742 /// returns the output operand it matches.
2743 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2744 assert(!ConstraintCode.empty() && "No known constraint!");
2745 return atoi(ConstraintCode.c_str());
2749 /// ParseConstraints - Split up the constraint string from the inline
2750 /// assembly value into the specific constraints and their prefixes,
2751 /// and also tie in the associated operand values.
2752 /// If this returns an empty vector, and if the constraint string itself
2753 /// isn't empty, there was an error parsing.
2754 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2755 ImmutableCallSite CS) const {
2756 /// ConstraintOperands - Information about all of the constraints.
2757 AsmOperandInfoVector ConstraintOperands;
2758 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2759 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2761 // Do a prepass over the constraints, canonicalizing them, and building up the
2762 // ConstraintOperands list.
2763 InlineAsm::ConstraintInfoVector
2764 ConstraintInfos = IA->ParseConstraints();
2766 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2767 unsigned ResNo = 0; // ResNo - The result number of the next output.
2769 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2770 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2771 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2773 // Update multiple alternative constraint count.
2774 if (OpInfo.multipleAlternatives.size() > maCount)
2775 maCount = OpInfo.multipleAlternatives.size();
2777 OpInfo.ConstraintVT = MVT::Other;
2779 // Compute the value type for each operand.
2780 switch (OpInfo.Type) {
2781 case InlineAsm::isOutput:
2782 // Indirect outputs just consume an argument.
2783 if (OpInfo.isIndirect) {
2784 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2788 // The return value of the call is this value. As such, there is no
2789 // corresponding argument.
2790 assert(!CS.getType()->isVoidTy() &&
2792 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
2793 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2795 assert(ResNo == 0 && "Asm only has one result!");
2796 OpInfo.ConstraintVT = getValueType(CS.getType());
2800 case InlineAsm::isInput:
2801 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2803 case InlineAsm::isClobber:
2808 if (OpInfo.CallOperandVal) {
2809 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2810 if (OpInfo.isIndirect) {
2811 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2813 report_fatal_error("Indirect operand for inline asm not a pointer!");
2814 OpTy = PtrTy->getElementType();
2817 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2818 if (const StructType *STy = dyn_cast<StructType>(OpTy))
2819 if (STy->getNumElements() == 1)
2820 OpTy = STy->getElementType(0);
2822 // If OpTy is not a single value, it may be a struct/union that we
2823 // can tile with integers.
2824 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2825 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2834 OpInfo.ConstraintVT =
2835 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2838 } else if (dyn_cast<PointerType>(OpTy)) {
2839 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2841 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2846 // If we have multiple alternative constraints, select the best alternative.
2847 if (ConstraintInfos.size()) {
2849 unsigned bestMAIndex = 0;
2850 int bestWeight = -1;
2851 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2854 // Compute the sums of the weights for each alternative, keeping track
2855 // of the best (highest weight) one so far.
2856 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2858 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2859 cIndex != eIndex; ++cIndex) {
2860 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2861 if (OpInfo.Type == InlineAsm::isClobber)
2864 // If this is an output operand with a matching input operand,
2865 // look up the matching input. If their types mismatch, e.g. one
2866 // is an integer, the other is floating point, or their sizes are
2867 // different, flag it as an maCantMatch.
2868 if (OpInfo.hasMatchingInput()) {
2869 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2870 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2871 if ((OpInfo.ConstraintVT.isInteger() !=
2872 Input.ConstraintVT.isInteger()) ||
2873 (OpInfo.ConstraintVT.getSizeInBits() !=
2874 Input.ConstraintVT.getSizeInBits())) {
2875 weightSum = -1; // Can't match.
2880 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2885 weightSum += weight;
2888 if (weightSum > bestWeight) {
2889 bestWeight = weightSum;
2890 bestMAIndex = maIndex;
2894 // Now select chosen alternative in each constraint.
2895 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2896 cIndex != eIndex; ++cIndex) {
2897 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2898 if (cInfo.Type == InlineAsm::isClobber)
2900 cInfo.selectAlternative(bestMAIndex);
2905 // Check and hook up tied operands, choose constraint code to use.
2906 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2907 cIndex != eIndex; ++cIndex) {
2908 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2910 // If this is an output operand with a matching input operand, look up the
2911 // matching input. If their types mismatch, e.g. one is an integer, the
2912 // other is floating point, or their sizes are different, flag it as an
2914 if (OpInfo.hasMatchingInput()) {
2915 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2917 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2918 if ((OpInfo.ConstraintVT.isInteger() !=
2919 Input.ConstraintVT.isInteger()) ||
2920 (OpInfo.ConstraintVT.getSizeInBits() !=
2921 Input.ConstraintVT.getSizeInBits())) {
2922 report_fatal_error("Unsupported asm: input constraint"
2923 " with a matching output constraint of"
2924 " incompatible type!");
2931 return ConstraintOperands;
2935 /// getConstraintGenerality - Return an integer indicating how general CT
2937 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2939 default: llvm_unreachable("Unknown constraint type!");
2940 case TargetLowering::C_Other:
2941 case TargetLowering::C_Unknown:
2943 case TargetLowering::C_Register:
2945 case TargetLowering::C_RegisterClass:
2947 case TargetLowering::C_Memory:
2952 /// Examine constraint type and operand type and determine a weight value.
2953 /// This object must already have been set up with the operand type
2954 /// and the current alternative constraint selected.
2955 TargetLowering::ConstraintWeight
2956 TargetLowering::getMultipleConstraintMatchWeight(
2957 AsmOperandInfo &info, int maIndex) const {
2958 InlineAsm::ConstraintCodeVector *rCodes;
2959 if (maIndex >= (int)info.multipleAlternatives.size())
2960 rCodes = &info.Codes;
2962 rCodes = &info.multipleAlternatives[maIndex].Codes;
2963 ConstraintWeight BestWeight = CW_Invalid;
2965 // Loop over the options, keeping track of the most general one.
2966 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2967 ConstraintWeight weight =
2968 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2969 if (weight > BestWeight)
2970 BestWeight = weight;
2976 /// Examine constraint type and operand type and determine a weight value.
2977 /// This object must already have been set up with the operand type
2978 /// and the current alternative constraint selected.
2979 TargetLowering::ConstraintWeight
2980 TargetLowering::getSingleConstraintMatchWeight(
2981 AsmOperandInfo &info, const char *constraint) const {
2982 ConstraintWeight weight = CW_Invalid;
2983 Value *CallOperandVal = info.CallOperandVal;
2984 // If we don't have a value, we can't do a match,
2985 // but allow it at the lowest weight.
2986 if (CallOperandVal == NULL)
2988 // Look at the constraint type.
2989 switch (*constraint) {
2990 case 'i': // immediate integer.
2991 case 'n': // immediate integer with a known value.
2992 if (isa<ConstantInt>(CallOperandVal))
2993 weight = CW_Constant;
2995 case 's': // non-explicit intregal immediate.
2996 if (isa<GlobalValue>(CallOperandVal))
2997 weight = CW_Constant;
2999 case 'E': // immediate float if host format.
3000 case 'F': // immediate float.
3001 if (isa<ConstantFP>(CallOperandVal))
3002 weight = CW_Constant;
3004 case '<': // memory operand with autodecrement.
3005 case '>': // memory operand with autoincrement.
3006 case 'm': // memory operand.
3007 case 'o': // offsettable memory operand
3008 case 'V': // non-offsettable memory operand
3011 case 'r': // general register.
3012 case 'g': // general register, memory operand or immediate integer.
3013 // note: Clang converts "g" to "imr".
3014 if (CallOperandVal->getType()->isIntegerTy())
3015 weight = CW_Register;
3017 case 'X': // any operand.
3019 weight = CW_Default;
3025 /// ChooseConstraint - If there are multiple different constraints that we
3026 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3027 /// This is somewhat tricky: constraints fall into four classes:
3028 /// Other -> immediates and magic values
3029 /// Register -> one specific register
3030 /// RegisterClass -> a group of regs
3031 /// Memory -> memory
3032 /// Ideally, we would pick the most specific constraint possible: if we have
3033 /// something that fits into a register, we would pick it. The problem here
3034 /// is that if we have something that could either be in a register or in
3035 /// memory that use of the register could cause selection of *other*
3036 /// operands to fail: they might only succeed if we pick memory. Because of
3037 /// this the heuristic we use is:
3039 /// 1) If there is an 'other' constraint, and if the operand is valid for
3040 /// that constraint, use it. This makes us take advantage of 'i'
3041 /// constraints when available.
3042 /// 2) Otherwise, pick the most general constraint present. This prefers
3043 /// 'm' over 'r', for example.
3045 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3046 const TargetLowering &TLI,
3047 SDValue Op, SelectionDAG *DAG) {
3048 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3049 unsigned BestIdx = 0;
3050 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3051 int BestGenerality = -1;
3053 // Loop over the options, keeping track of the most general one.
3054 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3055 TargetLowering::ConstraintType CType =
3056 TLI.getConstraintType(OpInfo.Codes[i]);
3058 // If this is an 'other' constraint, see if the operand is valid for it.
3059 // For example, on X86 we might have an 'rI' constraint. If the operand
3060 // is an integer in the range [0..31] we want to use I (saving a load
3061 // of a register), otherwise we must use 'r'.
3062 if (CType == TargetLowering::C_Other && Op.getNode()) {
3063 assert(OpInfo.Codes[i].size() == 1 &&
3064 "Unhandled multi-letter 'other' constraint");
3065 std::vector<SDValue> ResultOps;
3066 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
3068 if (!ResultOps.empty()) {
3075 // Things with matching constraints can only be registers, per gcc
3076 // documentation. This mainly affects "g" constraints.
3077 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3080 // This constraint letter is more general than the previous one, use it.
3081 int Generality = getConstraintGenerality(CType);
3082 if (Generality > BestGenerality) {
3085 BestGenerality = Generality;
3089 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3090 OpInfo.ConstraintType = BestType;
3093 /// ComputeConstraintToUse - Determines the constraint code and constraint
3094 /// type to use for the specific AsmOperandInfo, setting
3095 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3096 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3098 SelectionDAG *DAG) const {
3099 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3101 // Single-letter constraints ('r') are very common.
3102 if (OpInfo.Codes.size() == 1) {
3103 OpInfo.ConstraintCode = OpInfo.Codes[0];
3104 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3106 ChooseConstraint(OpInfo, *this, Op, DAG);
3109 // 'X' matches anything.
3110 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3111 // Labels and constants are handled elsewhere ('X' is the only thing
3112 // that matches labels). For Functions, the type here is the type of
3113 // the result, which is not what we want to look at; leave them alone.
3114 Value *v = OpInfo.CallOperandVal;
3115 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3116 OpInfo.CallOperandVal = v;
3120 // Otherwise, try to resolve it to something we know about by looking at
3121 // the actual operand type.
3122 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3123 OpInfo.ConstraintCode = Repl;
3124 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3129 //===----------------------------------------------------------------------===//
3130 // Loop Strength Reduction hooks
3131 //===----------------------------------------------------------------------===//
3133 /// isLegalAddressingMode - Return true if the addressing mode represented
3134 /// by AM is legal for this target, for a load/store of the specified type.
3135 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3136 const Type *Ty) const {
3137 // The default implementation of this implements a conservative RISCy, r+r and
3140 // Allows a sign-extended 16-bit immediate field.
3141 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3144 // No global is ever allowed as a base.
3148 // Only support r+r,
3150 case 0: // "r+i" or just "i", depending on HasBaseReg.
3153 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3155 // Otherwise we have r+r or r+i.
3158 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3160 // Allow 2*r as r+r.
3167 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3168 /// return a DAG expression to select that will generate the same value by
3169 /// multiplying by a magic number. See:
3170 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3171 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
3172 std::vector<SDNode*>* Created) const {
3173 EVT VT = N->getValueType(0);
3174 DebugLoc dl= N->getDebugLoc();
3176 // Check to see if we can do this.
3177 // FIXME: We should be more aggressive here.
3178 if (!isTypeLegal(VT))
3181 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3182 APInt::ms magics = d.magic();
3184 // Multiply the numerator (operand 0) by the magic value
3185 // FIXME: We should support doing a MUL in a wider type
3187 if (isOperationLegalOrCustom(ISD::MULHS, VT))
3188 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3189 DAG.getConstant(magics.m, VT));
3190 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3191 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3193 DAG.getConstant(magics.m, VT)).getNode(), 1);
3195 return SDValue(); // No mulhs or equvialent
3196 // If d > 0 and m < 0, add the numerator
3197 if (d.isStrictlyPositive() && magics.m.isNegative()) {
3198 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3200 Created->push_back(Q.getNode());
3202 // If d < 0 and m > 0, subtract the numerator.
3203 if (d.isNegative() && magics.m.isStrictlyPositive()) {
3204 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3206 Created->push_back(Q.getNode());
3208 // Shift right algebraic if shift value is nonzero
3210 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3211 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3213 Created->push_back(Q.getNode());
3215 // Extract the sign bit and add it to the quotient
3217 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3218 getShiftAmountTy(Q.getValueType())));
3220 Created->push_back(T.getNode());
3221 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3224 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3225 /// return a DAG expression to select that will generate the same value by
3226 /// multiplying by a magic number. See:
3227 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3228 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
3229 std::vector<SDNode*>* Created) const {
3230 EVT VT = N->getValueType(0);
3231 DebugLoc dl = N->getDebugLoc();
3233 // Check to see if we can do this.
3234 // FIXME: We should be more aggressive here.
3235 if (!isTypeLegal(VT))
3238 // FIXME: We should use a narrower constant when the upper
3239 // bits are known to be zero.
3240 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3241 APInt::mu magics = N1C.magicu();
3243 SDValue Q = N->getOperand(0);
3245 // If the divisor is even, we can avoid using the expensive fixup by shifting
3246 // the divided value upfront.
3247 if (magics.a != 0 && !N1C[0]) {
3248 unsigned Shift = N1C.countTrailingZeros();
3249 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3250 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3252 Created->push_back(Q.getNode());
3254 // Get magic number for the shifted divisor.
3255 magics = N1C.lshr(Shift).magicu(Shift);
3256 assert(magics.a == 0 && "Should use cheap fixup now");
3259 // Multiply the numerator (operand 0) by the magic value
3260 // FIXME: We should support doing a MUL in a wider type
3261 if (isOperationLegalOrCustom(ISD::MULHU, VT))
3262 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3263 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3264 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3265 DAG.getConstant(magics.m, VT)).getNode(), 1);
3267 return SDValue(); // No mulhu or equvialent
3269 Created->push_back(Q.getNode());
3271 if (magics.a == 0) {
3272 assert(magics.s < N1C.getBitWidth() &&
3273 "We shouldn't generate an undefined shift!");
3274 return DAG.getNode(ISD::SRL, dl, VT, Q,
3275 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3277 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3279 Created->push_back(NPQ.getNode());
3280 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3281 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3283 Created->push_back(NPQ.getNode());
3284 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3286 Created->push_back(NPQ.getNode());
3287 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3288 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));