1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
37 /// NOTE: The constructor takes ownership of TLOF.
38 TargetLowering::TargetLowering(const TargetMachine &tm,
39 const TargetLoweringObjectFile *tlof)
40 : TargetLoweringBase(tm, tlof) {}
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 SDValue &Chain) const {
50 const Function *F = DAG.getMachineFunction().getFunction();
52 // Conservatively require the attributes of the call to match those of
53 // the return. Ignore noalias because it doesn't affect the call sequence.
54 AttributeSet CallerAttrs = F->getAttributes();
55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56 .removeAttribute(Attribute::NoAlias).hasAttributes())
59 // It's not safe to eliminate the sign / zero extension of the return value.
60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
64 // Check if the only use is a function return node.
65 return isUsedByReturnOnly(Node, Chain);
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
80 Alignment = CS->getParamAlignment(AttrIdx);
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
86 TargetLowering::makeLibCall(SelectionDAG &DAG,
87 RTLIB::Libcall LC, EVT RetVT,
88 const SDValue *Ops, unsigned NumOps,
89 bool isSigned, SDLoc dl,
91 bool isReturnValueUsed) const {
92 TargetLowering::ArgListTy Args;
95 TargetLowering::ArgListEntry Entry;
96 for (unsigned i = 0; i != NumOps; ++i) {
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99 Entry.isSExt = isSigned;
100 Entry.isZExt = !isSigned;
101 Args.push_back(Entry);
103 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
105 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
107 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
108 false, 0, getLibcallCallingConv(LC),
109 /*isTailCall=*/false,
110 doesNotReturn, isReturnValueUsed, Callee, Args,
112 return LowerCallTo(CLI);
116 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
117 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
118 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
119 SDValue &NewLHS, SDValue &NewRHS,
120 ISD::CondCode &CCCode,
122 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
123 && "Unsupported setcc type!");
125 // Expand into one or more soft-fp libcall(s).
126 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
130 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
131 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
135 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
136 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
140 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
141 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
145 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
146 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
150 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
151 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
155 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
156 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
159 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
160 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
163 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
164 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
167 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
168 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
171 // SETONE = SETOLT | SETOGT
172 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
173 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
176 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
177 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
180 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
181 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
184 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
185 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
188 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
189 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
192 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
193 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
195 default: llvm_unreachable("Do not know how to soften this setcc!");
199 // Use the target specific return value for comparions lib calls.
200 EVT RetVT = getCmpLibcallReturnType();
201 SDValue Ops[2] = { NewLHS, NewRHS };
202 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
204 NewRHS = DAG.getConstant(0, RetVT);
205 CCCode = getCmpLibcallCC(LC1);
206 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
207 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
208 getSetCCResultType(*DAG.getContext(), RetVT),
209 NewLHS, NewRHS, DAG.getCondCode(CCCode));
210 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
212 NewLHS = DAG.getNode(ISD::SETCC, dl,
213 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
214 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
215 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
220 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
221 /// current function. The returned value is a member of the
222 /// MachineJumpTableInfo::JTEntryKind enum.
223 unsigned TargetLowering::getJumpTableEncoding() const {
224 // In non-pic modes, just use the address of a block.
225 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
226 return MachineJumpTableInfo::EK_BlockAddress;
228 // In PIC mode, if the target supports a GPRel32 directive, use it.
229 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
230 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
232 // Otherwise, use a label difference.
233 return MachineJumpTableInfo::EK_LabelDifference32;
236 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
237 SelectionDAG &DAG) const {
238 // If our PIC model is GP relative, use the global offset table as the base.
239 unsigned JTEncoding = getJumpTableEncoding();
241 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
242 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
243 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
248 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
249 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
252 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
253 unsigned JTI,MCContext &Ctx) const{
254 // The normal PIC reloc base is the label at the start of the jump table.
255 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
259 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
260 // Assume that everything is safe in static mode.
261 if (getTargetMachine().getRelocationModel() == Reloc::Static)
264 // In dynamic-no-pic mode, assume that known defined values are safe.
265 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
267 !GA->getGlobal()->isDeclaration() &&
268 !GA->getGlobal()->isWeakForLinker())
271 // Otherwise assume nothing is safe.
275 //===----------------------------------------------------------------------===//
276 // Optimization Methods
277 //===----------------------------------------------------------------------===//
279 /// ShrinkDemandedConstant - Check to see if the specified operand of the
280 /// specified instruction is a constant integer. If so, check to see if there
281 /// are any bits set in the constant that are not demanded. If so, shrink the
282 /// constant and return true.
283 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
284 const APInt &Demanded) {
287 // FIXME: ISD::SELECT, ISD::SELECT_CC
288 switch (Op.getOpcode()) {
293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
294 if (!C) return false;
296 if (Op.getOpcode() == ISD::XOR &&
297 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
300 // if we can expand it to have all bits set, do it
301 if (C->getAPIntValue().intersects(~Demanded)) {
302 EVT VT = Op.getValueType();
303 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
304 DAG.getConstant(Demanded &
307 return CombineTo(Op, New);
317 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
318 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
319 /// cast, but it could be generalized for targets with other types of
320 /// implicit widening casts.
322 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
324 const APInt &Demanded,
326 assert(Op.getNumOperands() == 2 &&
327 "ShrinkDemandedOp only supports binary operators!");
328 assert(Op.getNode()->getNumValues() == 1 &&
329 "ShrinkDemandedOp only supports nodes with one result!");
331 // Don't do this if the node has another user, which may require the
333 if (!Op.getNode()->hasOneUse())
336 // Search for the smallest integer type with free casts to and from
337 // Op's type. For expedience, just check power-of-2 integer types.
338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
339 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
340 unsigned SmallVTBits = DemandedSize;
341 if (!isPowerOf2_32(SmallVTBits))
342 SmallVTBits = NextPowerOf2(SmallVTBits);
343 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
344 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
345 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
346 TLI.isZExtFree(SmallVT, Op.getValueType())) {
347 // We found a type with free casts.
348 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
349 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
350 Op.getNode()->getOperand(0)),
351 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
352 Op.getNode()->getOperand(1)));
353 bool NeedZext = DemandedSize > SmallVTBits;
354 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
355 dl, Op.getValueType(), X);
356 return CombineTo(Op, Z);
362 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
363 /// DemandedMask bits of the result of Op are ever used downstream. If we can
364 /// use this information to simplify Op, create a new simplified DAG node and
365 /// return true, returning the original and new nodes in Old and New. Otherwise,
366 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
367 /// the expression (used to simplify the caller). The KnownZero/One bits may
368 /// only be accurate for those bits in the DemandedMask.
369 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
370 const APInt &DemandedMask,
373 TargetLoweringOpt &TLO,
374 unsigned Depth) const {
375 unsigned BitWidth = DemandedMask.getBitWidth();
376 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
377 "Mask size mismatches value type size!");
378 APInt NewMask = DemandedMask;
381 // Don't know anything.
382 KnownZero = KnownOne = APInt(BitWidth, 0);
384 // Other users may use these bits.
385 if (!Op.getNode()->hasOneUse()) {
387 // If not at the root, Just compute the KnownZero/KnownOne bits to
388 // simplify things downstream.
389 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
392 // If this is the root being simplified, allow it to have multiple uses,
393 // just set the NewMask to all bits.
394 NewMask = APInt::getAllOnesValue(BitWidth);
395 } else if (DemandedMask == 0) {
396 // Not demanding any bits from Op.
397 if (Op.getOpcode() != ISD::UNDEF)
398 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
400 } else if (Depth == 6) { // Limit search depth.
404 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
405 switch (Op.getOpcode()) {
407 // We know all of the bits for a constant!
408 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
409 KnownZero = ~KnownOne;
410 return false; // Don't fall through, will infinitely loop.
412 // If the RHS is a constant, check to see if the LHS would be zero without
413 // using the bits from the RHS. Below, we use knowledge about the RHS to
414 // simplify the LHS, here we're using information from the LHS to simplify
416 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
417 APInt LHSZero, LHSOne;
418 // Do not increment Depth here; that can cause an infinite loop.
419 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
420 // If the LHS already has zeros where RHSC does, this and is dead.
421 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
422 return TLO.CombineTo(Op, Op.getOperand(0));
423 // If any of the set bits in the RHS are known zero on the LHS, shrink
425 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
429 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
430 KnownOne, TLO, Depth+1))
432 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
433 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
434 KnownZero2, KnownOne2, TLO, Depth+1))
436 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
438 // If all of the demanded bits are known one on one side, return the other.
439 // These bits cannot contribute to the result of the 'and'.
440 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
441 return TLO.CombineTo(Op, Op.getOperand(0));
442 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
443 return TLO.CombineTo(Op, Op.getOperand(1));
444 // If all of the demanded bits in the inputs are known zeros, return zero.
445 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
446 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
447 // If the RHS is a constant, see if we can simplify it.
448 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
450 // If the operation can be done in a smaller type, do so.
451 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
454 // Output known-1 bits are only known if set in both the LHS & RHS.
455 KnownOne &= KnownOne2;
456 // Output known-0 are known to be clear if zero in either the LHS | RHS.
457 KnownZero |= KnownZero2;
460 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
461 KnownOne, TLO, Depth+1))
463 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
464 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
465 KnownZero2, KnownOne2, TLO, Depth+1))
467 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
469 // If all of the demanded bits are known zero on one side, return the other.
470 // These bits cannot contribute to the result of the 'or'.
471 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
472 return TLO.CombineTo(Op, Op.getOperand(0));
473 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
474 return TLO.CombineTo(Op, Op.getOperand(1));
475 // If all of the potentially set bits on one side are known to be set on
476 // the other side, just use the 'other' side.
477 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
478 return TLO.CombineTo(Op, Op.getOperand(0));
479 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
480 return TLO.CombineTo(Op, Op.getOperand(1));
481 // If the RHS is a constant, see if we can simplify it.
482 if (TLO.ShrinkDemandedConstant(Op, NewMask))
484 // If the operation can be done in a smaller type, do so.
485 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
488 // Output known-0 bits are only known if clear in both the LHS & RHS.
489 KnownZero &= KnownZero2;
490 // Output known-1 are known to be set if set in either the LHS | RHS.
491 KnownOne |= KnownOne2;
494 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
495 KnownOne, TLO, Depth+1))
497 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
498 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
499 KnownOne2, TLO, Depth+1))
501 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
503 // If all of the demanded bits are known zero on one side, return the other.
504 // These bits cannot contribute to the result of the 'xor'.
505 if ((KnownZero & NewMask) == NewMask)
506 return TLO.CombineTo(Op, Op.getOperand(0));
507 if ((KnownZero2 & NewMask) == NewMask)
508 return TLO.CombineTo(Op, Op.getOperand(1));
509 // If the operation can be done in a smaller type, do so.
510 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
513 // If all of the unknown bits are known to be zero on one side or the other
514 // (but not both) turn this into an *inclusive* or.
515 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
516 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
517 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
521 // Output known-0 bits are known if clear or set in both the LHS & RHS.
522 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
523 // Output known-1 are known to be set if set in only one of the LHS, RHS.
524 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
526 // If all of the demanded bits on one side are known, and all of the set
527 // bits on that side are also known to be set on the other side, turn this
528 // into an AND, as we know the bits will be cleared.
529 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
530 // NB: it is okay if more bits are known than are requested
531 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
532 if (KnownOne == KnownOne2) { // set bits are the same on both sides
533 EVT VT = Op.getValueType();
534 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
535 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
536 Op.getOperand(0), ANDC));
540 // If the RHS is a constant, see if we can simplify it.
541 // for XOR, we prefer to force bits to 1 if they will make a -1.
542 // if we can't force bits, try to shrink constant
543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
544 APInt Expanded = C->getAPIntValue() | (~NewMask);
545 // if we can expand it to have all bits set, do it
546 if (Expanded.isAllOnesValue()) {
547 if (Expanded != C->getAPIntValue()) {
548 EVT VT = Op.getValueType();
549 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
550 TLO.DAG.getConstant(Expanded, VT));
551 return TLO.CombineTo(Op, New);
553 // if it already has all the bits set, nothing to change
554 // but don't shrink either!
555 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
560 KnownZero = KnownZeroOut;
561 KnownOne = KnownOneOut;
564 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
565 KnownOne, TLO, Depth+1))
567 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
568 KnownOne2, TLO, Depth+1))
570 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
571 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
573 // If the operands are constants, see if we can simplify them.
574 if (TLO.ShrinkDemandedConstant(Op, NewMask))
577 // Only known if known in both the LHS and RHS.
578 KnownOne &= KnownOne2;
579 KnownZero &= KnownZero2;
582 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
583 KnownOne, TLO, Depth+1))
585 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
586 KnownOne2, TLO, Depth+1))
588 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
589 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
591 // If the operands are constants, see if we can simplify them.
592 if (TLO.ShrinkDemandedConstant(Op, NewMask))
595 // Only known if known in both the LHS and RHS.
596 KnownOne &= KnownOne2;
597 KnownZero &= KnownZero2;
600 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
601 unsigned ShAmt = SA->getZExtValue();
602 SDValue InOp = Op.getOperand(0);
604 // If the shift count is an invalid immediate, don't do anything.
605 if (ShAmt >= BitWidth)
608 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
609 // single shift. We can do this if the bottom bits (which are shifted
610 // out) are never demanded.
611 if (InOp.getOpcode() == ISD::SRL &&
612 isa<ConstantSDNode>(InOp.getOperand(1))) {
613 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
614 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
615 unsigned Opc = ISD::SHL;
623 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
624 EVT VT = Op.getValueType();
625 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
626 InOp.getOperand(0), NewSA));
630 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
631 KnownZero, KnownOne, TLO, Depth+1))
634 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
635 // are not demanded. This will likely allow the anyext to be folded away.
636 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
637 SDValue InnerOp = InOp.getNode()->getOperand(0);
638 EVT InnerVT = InnerOp.getValueType();
639 unsigned InnerBits = InnerVT.getSizeInBits();
640 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
641 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
642 EVT ShTy = getShiftAmountTy(InnerVT);
643 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
646 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
647 TLO.DAG.getConstant(ShAmt, ShTy));
650 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
653 // Repeat the SHL optimization above in cases where an extension
654 // intervenes: (shl (anyext (shr x, c1)), c2) to
655 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
656 // aren't demanded (as above) and that the shifted upper c1 bits of
657 // x aren't demanded.
658 if (InOp.hasOneUse() &&
659 InnerOp.getOpcode() == ISD::SRL &&
660 InnerOp.hasOneUse() &&
661 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
662 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
664 if (InnerShAmt < ShAmt &&
665 InnerShAmt < InnerBits &&
666 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
667 NewMask.trunc(ShAmt) == 0) {
669 TLO.DAG.getConstant(ShAmt - InnerShAmt,
670 Op.getOperand(1).getValueType());
671 EVT VT = Op.getValueType();
672 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
673 InnerOp.getOperand(0));
674 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
680 KnownZero <<= SA->getZExtValue();
681 KnownOne <<= SA->getZExtValue();
682 // low bits known zero.
683 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
687 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
688 EVT VT = Op.getValueType();
689 unsigned ShAmt = SA->getZExtValue();
690 unsigned VTSize = VT.getSizeInBits();
691 SDValue InOp = Op.getOperand(0);
693 // If the shift count is an invalid immediate, don't do anything.
694 if (ShAmt >= BitWidth)
697 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
698 // single shift. We can do this if the top bits (which are shifted out)
699 // are never demanded.
700 if (InOp.getOpcode() == ISD::SHL &&
701 isa<ConstantSDNode>(InOp.getOperand(1))) {
702 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
703 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
704 unsigned Opc = ISD::SRL;
712 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
713 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
714 InOp.getOperand(0), NewSA));
718 // Compute the new bits that are at the top now.
719 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
720 KnownZero, KnownOne, TLO, Depth+1))
722 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
723 KnownZero = KnownZero.lshr(ShAmt);
724 KnownOne = KnownOne.lshr(ShAmt);
726 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
727 KnownZero |= HighBits; // High bits known zero.
731 // If this is an arithmetic shift right and only the low-bit is set, we can
732 // always convert this into a logical shr, even if the shift amount is
733 // variable. The low bit of the shift cannot be an input sign bit unless
734 // the shift amount is >= the size of the datatype, which is undefined.
736 return TLO.CombineTo(Op,
737 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
738 Op.getOperand(0), Op.getOperand(1)));
740 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
741 EVT VT = Op.getValueType();
742 unsigned ShAmt = SA->getZExtValue();
744 // If the shift count is an invalid immediate, don't do anything.
745 if (ShAmt >= BitWidth)
748 APInt InDemandedMask = (NewMask << ShAmt);
750 // If any of the demanded bits are produced by the sign extension, we also
751 // demand the input sign bit.
752 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
753 if (HighBits.intersects(NewMask))
754 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
756 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
757 KnownZero, KnownOne, TLO, Depth+1))
759 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
760 KnownZero = KnownZero.lshr(ShAmt);
761 KnownOne = KnownOne.lshr(ShAmt);
763 // Handle the sign bit, adjusted to where it is now in the mask.
764 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
766 // If the input sign bit is known to be zero, or if none of the top bits
767 // are demanded, turn this into an unsigned shift right.
768 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
769 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
773 int Log2 = NewMask.exactLogBase2();
775 // The bit must come from the sign.
777 TLO.DAG.getConstant(BitWidth - 1 - Log2,
778 Op.getOperand(1).getValueType());
779 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
780 Op.getOperand(0), NewSA));
783 if (KnownOne.intersects(SignBit))
784 // New bits are known one.
785 KnownOne |= HighBits;
788 case ISD::SIGN_EXTEND_INREG: {
789 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
791 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
792 // If we only care about the highest bit, don't bother shifting right.
793 if (MsbMask == DemandedMask) {
794 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
795 SDValue InOp = Op.getOperand(0);
797 // Compute the correct shift amount type, which must be getShiftAmountTy
798 // for scalar types after legalization.
799 EVT ShiftAmtTy = Op.getValueType();
800 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
801 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
803 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
804 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
805 Op.getValueType(), InOp, ShiftAmt));
808 // Sign extension. Compute the demanded bits in the result that are not
809 // present in the input.
811 APInt::getHighBitsSet(BitWidth,
812 BitWidth - ExVT.getScalarType().getSizeInBits());
814 // If none of the extended bits are demanded, eliminate the sextinreg.
815 if ((NewBits & NewMask) == 0)
816 return TLO.CombineTo(Op, Op.getOperand(0));
819 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
820 APInt InputDemandedBits =
821 APInt::getLowBitsSet(BitWidth,
822 ExVT.getScalarType().getSizeInBits()) &
825 // Since the sign extended bits are demanded, we know that the sign
827 InputDemandedBits |= InSignBit;
829 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
830 KnownZero, KnownOne, TLO, Depth+1))
832 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
834 // If the sign bit of the input is known set or clear, then we know the
835 // top bits of the result.
837 // If the input sign bit is known zero, convert this into a zero extension.
838 if (KnownZero.intersects(InSignBit))
839 return TLO.CombineTo(Op,
840 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
842 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
844 KnownZero &= ~NewBits;
845 } else { // Input sign bit unknown
846 KnownZero &= ~NewBits;
847 KnownOne &= ~NewBits;
851 case ISD::ZERO_EXTEND: {
852 unsigned OperandBitWidth =
853 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
854 APInt InMask = NewMask.trunc(OperandBitWidth);
856 // If none of the top bits are demanded, convert this into an any_extend.
858 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
859 if (!NewBits.intersects(NewMask))
860 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
864 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
865 KnownZero, KnownOne, TLO, Depth+1))
867 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
868 KnownZero = KnownZero.zext(BitWidth);
869 KnownOne = KnownOne.zext(BitWidth);
870 KnownZero |= NewBits;
873 case ISD::SIGN_EXTEND: {
874 EVT InVT = Op.getOperand(0).getValueType();
875 unsigned InBits = InVT.getScalarType().getSizeInBits();
876 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
877 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
878 APInt NewBits = ~InMask & NewMask;
880 // If none of the top bits are demanded, convert this into an any_extend.
882 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
886 // Since some of the sign extended bits are demanded, we know that the sign
888 APInt InDemandedBits = InMask & NewMask;
889 InDemandedBits |= InSignBit;
890 InDemandedBits = InDemandedBits.trunc(InBits);
892 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
893 KnownOne, TLO, Depth+1))
895 KnownZero = KnownZero.zext(BitWidth);
896 KnownOne = KnownOne.zext(BitWidth);
898 // If the sign bit is known zero, convert this to a zero extend.
899 if (KnownZero.intersects(InSignBit))
900 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
904 // If the sign bit is known one, the top bits match.
905 if (KnownOne.intersects(InSignBit)) {
907 assert((KnownZero & NewBits) == 0);
908 } else { // Otherwise, top bits aren't known.
909 assert((KnownOne & NewBits) == 0);
910 assert((KnownZero & NewBits) == 0);
914 case ISD::ANY_EXTEND: {
915 unsigned OperandBitWidth =
916 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
917 APInt InMask = NewMask.trunc(OperandBitWidth);
918 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
919 KnownZero, KnownOne, TLO, Depth+1))
921 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
922 KnownZero = KnownZero.zext(BitWidth);
923 KnownOne = KnownOne.zext(BitWidth);
926 case ISD::TRUNCATE: {
927 // Simplify the input, using demanded bit information, and compute the known
928 // zero/one bits live out.
929 unsigned OperandBitWidth =
930 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
931 APInt TruncMask = NewMask.zext(OperandBitWidth);
932 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
933 KnownZero, KnownOne, TLO, Depth+1))
935 KnownZero = KnownZero.trunc(BitWidth);
936 KnownOne = KnownOne.trunc(BitWidth);
938 // If the input is only used by this truncate, see if we can shrink it based
939 // on the known demanded bits.
940 if (Op.getOperand(0).getNode()->hasOneUse()) {
941 SDValue In = Op.getOperand(0);
942 switch (In.getOpcode()) {
945 // Shrink SRL by a constant if none of the high bits shifted in are
947 if (TLO.LegalTypes() &&
948 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
949 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
952 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
955 SDValue Shift = In.getOperand(1);
956 if (TLO.LegalTypes()) {
957 uint64_t ShVal = ShAmt->getZExtValue();
959 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
962 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
963 OperandBitWidth - BitWidth);
964 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
966 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
967 // None of the shifted in bits are needed. Add a truncate of the
968 // shift input, then shift it.
969 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
972 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
981 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
984 case ISD::AssertZext: {
985 // AssertZext demands all of the high bits, plus any of the low bits
986 // demanded by its users.
987 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
988 APInt InMask = APInt::getLowBitsSet(BitWidth,
990 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
991 KnownZero, KnownOne, TLO, Depth+1))
993 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
995 KnownZero |= ~InMask & NewMask;
999 // If this is an FP->Int bitcast and if the sign bit is the only
1000 // thing demanded, turn this into a FGETSIGN.
1001 if (!TLO.LegalOperations() &&
1002 !Op.getValueType().isVector() &&
1003 !Op.getOperand(0).getValueType().isVector() &&
1004 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1005 Op.getOperand(0).getValueType().isFloatingPoint()) {
1006 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1007 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1008 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1009 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1010 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1011 // place. We expect the SHL to be eliminated by other optimizations.
1012 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1013 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1014 if (!OpVTLegal && OpVTSizeInBits > 32)
1015 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1016 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1017 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1018 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1027 // Add, Sub, and Mul don't demand any bits in positions beyond that
1028 // of the highest bit demanded of them.
1029 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1030 BitWidth - NewMask.countLeadingZeros());
1031 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1032 KnownOne2, TLO, Depth+1))
1034 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1035 KnownOne2, TLO, Depth+1))
1037 // See if the operation should be performed at a smaller bit width.
1038 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1043 // Just use ComputeMaskedBits to compute output bits.
1044 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1048 // If we know the value of all of the demanded bits, return this as a
1050 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1051 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1056 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1057 /// in Mask are known to be either zero or one and return them in the
1058 /// KnownZero/KnownOne bitsets.
1059 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1062 const SelectionDAG &DAG,
1063 unsigned Depth) const {
1064 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1065 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1066 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1067 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1068 "Should use MaskedValueIsZero if you don't know whether Op"
1069 " is a target node!");
1070 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1073 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1074 /// targets that want to expose additional information about sign bits to the
1076 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1077 unsigned Depth) const {
1078 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1079 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1080 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1081 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1082 "Should use ComputeNumSignBits if you don't know whether Op"
1083 " is a target node!");
1087 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1088 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1089 /// determine which bit is set.
1091 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1092 // A left-shift of a constant one will have exactly one bit set, because
1093 // shifting the bit off the end is undefined.
1094 if (Val.getOpcode() == ISD::SHL)
1095 if (ConstantSDNode *C =
1096 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1097 if (C->getAPIntValue() == 1)
1100 // Similarly, a right-shift of a constant sign-bit will have exactly
1102 if (Val.getOpcode() == ISD::SRL)
1103 if (ConstantSDNode *C =
1104 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1105 if (C->getAPIntValue().isSignBit())
1108 // More could be done here, though the above checks are enough
1109 // to handle some common cases.
1111 // Fall back to ComputeMaskedBits to catch other known cases.
1112 EVT OpVT = Val.getValueType();
1113 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1114 APInt KnownZero, KnownOne;
1115 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1116 return (KnownZero.countPopulation() == BitWidth - 1) &&
1117 (KnownOne.countPopulation() == 1);
1120 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1121 /// and cc. If it is unable to simplify it, return a null SDValue.
1123 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1124 ISD::CondCode Cond, bool foldBooleans,
1125 DAGCombinerInfo &DCI, SDLoc dl) const {
1126 SelectionDAG &DAG = DCI.DAG;
1128 // These setcc operations always fold.
1132 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1134 case ISD::SETTRUE2: {
1135 TargetLowering::BooleanContent Cnt = getBooleanContents(VT.isVector());
1136 return DAG.getConstant(
1137 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1141 // Ensure that the constant occurs on the RHS, and fold constant
1143 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1144 if (isa<ConstantSDNode>(N0.getNode()) &&
1145 (DCI.isBeforeLegalizeOps() ||
1146 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1147 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1149 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1150 const APInt &C1 = N1C->getAPIntValue();
1152 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1153 // equality comparison, then we're just comparing whether X itself is
1155 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1156 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1157 N0.getOperand(1).getOpcode() == ISD::Constant) {
1159 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1160 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1161 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1162 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1163 // (srl (ctlz x), 5) == 0 -> X != 0
1164 // (srl (ctlz x), 5) != 1 -> X != 0
1167 // (srl (ctlz x), 5) != 0 -> X == 0
1168 // (srl (ctlz x), 5) == 1 -> X == 0
1171 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1172 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1178 // Look through truncs that don't change the value of a ctpop.
1179 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1180 CTPOP = N0.getOperand(0);
1182 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1183 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1184 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1185 EVT CTVT = CTPOP.getValueType();
1186 SDValue CTOp = CTPOP.getOperand(0);
1188 // (ctpop x) u< 2 -> (x & x-1) == 0
1189 // (ctpop x) u> 1 -> (x & x-1) != 0
1190 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1191 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1192 DAG.getConstant(1, CTVT));
1193 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1194 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1195 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1198 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1201 // (zext x) == C --> x == (trunc C)
1202 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1203 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1204 unsigned MinBits = N0.getValueSizeInBits();
1206 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1208 MinBits = N0->getOperand(0).getValueSizeInBits();
1209 PreZExt = N0->getOperand(0);
1210 } else if (N0->getOpcode() == ISD::AND) {
1211 // DAGCombine turns costly ZExts into ANDs
1212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1213 if ((C->getAPIntValue()+1).isPowerOf2()) {
1214 MinBits = C->getAPIntValue().countTrailingOnes();
1215 PreZExt = N0->getOperand(0);
1217 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1219 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1220 MinBits = LN0->getMemoryVT().getSizeInBits();
1225 // Make sure we're not losing bits from the constant.
1227 MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
1228 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1229 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1230 // Will get folded away.
1231 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1232 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1233 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1238 // If the LHS is '(and load, const)', the RHS is 0,
1239 // the test is for equality or unsigned, and all 1 bits of the const are
1240 // in the same partial word, see if we can shorten the load.
1241 if (DCI.isBeforeLegalize() &&
1242 !ISD::isSignedIntSetCC(Cond) &&
1243 N0.getOpcode() == ISD::AND && C1 == 0 &&
1244 N0.getNode()->hasOneUse() &&
1245 isa<LoadSDNode>(N0.getOperand(0)) &&
1246 N0.getOperand(0).getNode()->hasOneUse() &&
1247 isa<ConstantSDNode>(N0.getOperand(1))) {
1248 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1250 unsigned bestWidth = 0, bestOffset = 0;
1251 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1252 unsigned origWidth = N0.getValueType().getSizeInBits();
1253 unsigned maskWidth = origWidth;
1254 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1255 // 8 bits, but have to be careful...
1256 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1257 origWidth = Lod->getMemoryVT().getSizeInBits();
1259 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1260 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1261 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1262 for (unsigned offset=0; offset<origWidth/width; offset++) {
1263 if ((newMask & Mask) == Mask) {
1264 if (!getDataLayout()->isLittleEndian())
1265 bestOffset = (origWidth/width - offset - 1) * (width/8);
1267 bestOffset = (uint64_t)offset * (width/8);
1268 bestMask = Mask.lshr(offset * (width/8) * 8);
1272 newMask = newMask << width;
1277 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1278 if (newVT.isRound()) {
1279 EVT PtrType = Lod->getOperand(1).getValueType();
1280 SDValue Ptr = Lod->getBasePtr();
1281 if (bestOffset != 0)
1282 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1283 DAG.getConstant(bestOffset, PtrType));
1284 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1285 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1286 Lod->getPointerInfo().getWithOffset(bestOffset),
1287 false, false, false, NewAlign);
1288 return DAG.getSetCC(dl, VT,
1289 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1290 DAG.getConstant(bestMask.trunc(bestWidth),
1292 DAG.getConstant(0LL, newVT), Cond);
1297 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1298 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1299 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1301 // If the comparison constant has bits in the upper part, the
1302 // zero-extended value could never match.
1303 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1304 C1.getBitWidth() - InSize))) {
1308 case ISD::SETEQ: return DAG.getConstant(0, VT);
1311 case ISD::SETNE: return DAG.getConstant(1, VT);
1314 // True if the sign bit of C1 is set.
1315 return DAG.getConstant(C1.isNegative(), VT);
1318 // True if the sign bit of C1 isn't set.
1319 return DAG.getConstant(C1.isNonNegative(), VT);
1325 // Otherwise, we can perform the comparison with the low bits.
1333 EVT newVT = N0.getOperand(0).getValueType();
1334 if (DCI.isBeforeLegalizeOps() ||
1335 (isOperationLegal(ISD::SETCC, newVT) &&
1336 getCondCodeAction(Cond, newVT.getSimpleVT())==Legal))
1337 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1338 DAG.getConstant(C1.trunc(InSize), newVT),
1343 break; // todo, be more careful with signed comparisons
1345 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1346 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1347 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1348 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1349 EVT ExtDstTy = N0.getValueType();
1350 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1352 // If the constant doesn't fit into the number of bits for the source of
1353 // the sign extension, it is impossible for both sides to be equal.
1354 if (C1.getMinSignedBits() > ExtSrcTyBits)
1355 return DAG.getConstant(Cond == ISD::SETNE, VT);
1358 EVT Op0Ty = N0.getOperand(0).getValueType();
1359 if (Op0Ty == ExtSrcTy) {
1360 ZextOp = N0.getOperand(0);
1362 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1363 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1364 DAG.getConstant(Imm, Op0Ty));
1366 if (!DCI.isCalledByLegalizer())
1367 DCI.AddToWorklist(ZextOp.getNode());
1368 // Otherwise, make this a use of a zext.
1369 return DAG.getSetCC(dl, VT, ZextOp,
1370 DAG.getConstant(C1 & APInt::getLowBitsSet(
1375 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1376 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1377 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1378 if (N0.getOpcode() == ISD::SETCC &&
1379 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1380 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1382 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1383 // Invert the condition.
1384 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1385 CC = ISD::getSetCCInverse(CC,
1386 N0.getOperand(0).getValueType().isInteger());
1387 if (DCI.isBeforeLegalizeOps() ||
1388 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1389 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1392 if ((N0.getOpcode() == ISD::XOR ||
1393 (N0.getOpcode() == ISD::AND &&
1394 N0.getOperand(0).getOpcode() == ISD::XOR &&
1395 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1396 isa<ConstantSDNode>(N0.getOperand(1)) &&
1397 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1398 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1399 // can only do this if the top bits are known zero.
1400 unsigned BitWidth = N0.getValueSizeInBits();
1401 if (DAG.MaskedValueIsZero(N0,
1402 APInt::getHighBitsSet(BitWidth,
1404 // Okay, get the un-inverted input value.
1406 if (N0.getOpcode() == ISD::XOR)
1407 Val = N0.getOperand(0);
1409 assert(N0.getOpcode() == ISD::AND &&
1410 N0.getOperand(0).getOpcode() == ISD::XOR);
1411 // ((X^1)&1)^1 -> X & 1
1412 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1413 N0.getOperand(0).getOperand(0),
1417 return DAG.getSetCC(dl, VT, Val, N1,
1418 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1420 } else if (N1C->getAPIntValue() == 1 &&
1422 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
1424 if (Op0.getOpcode() == ISD::TRUNCATE)
1425 Op0 = Op0.getOperand(0);
1427 if ((Op0.getOpcode() == ISD::XOR) &&
1428 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1429 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1430 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1431 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1432 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1435 if (Op0.getOpcode() == ISD::AND &&
1436 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1437 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1438 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1439 if (Op0.getValueType().bitsGT(VT))
1440 Op0 = DAG.getNode(ISD::AND, dl, VT,
1441 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1442 DAG.getConstant(1, VT));
1443 else if (Op0.getValueType().bitsLT(VT))
1444 Op0 = DAG.getNode(ISD::AND, dl, VT,
1445 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1446 DAG.getConstant(1, VT));
1448 return DAG.getSetCC(dl, VT, Op0,
1449 DAG.getConstant(0, Op0.getValueType()),
1450 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1452 if (Op0.getOpcode() == ISD::AssertZext &&
1453 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1454 return DAG.getSetCC(dl, VT, Op0,
1455 DAG.getConstant(0, Op0.getValueType()),
1456 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1460 APInt MinVal, MaxVal;
1461 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1462 if (ISD::isSignedIntSetCC(Cond)) {
1463 MinVal = APInt::getSignedMinValue(OperandBitSize);
1464 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1466 MinVal = APInt::getMinValue(OperandBitSize);
1467 MaxVal = APInt::getMaxValue(OperandBitSize);
1470 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1471 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1472 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1473 // X >= C0 --> X > (C0-1)
1475 if (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1476 isLegalICmpImmediate(C.getSExtValue())))
1477 return DAG.getSetCC(dl, VT, N0,
1478 DAG.getConstant(C, N1.getValueType()),
1479 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1482 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1483 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1484 // X <= C0 --> X < (C0+1)
1486 if (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1487 isLegalICmpImmediate(C.getSExtValue())))
1488 return DAG.getSetCC(dl, VT, N0,
1489 DAG.getConstant(C, N1.getValueType()),
1490 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1493 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1494 return DAG.getConstant(0, VT); // X < MIN --> false
1495 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1496 return DAG.getConstant(1, VT); // X >= MIN --> true
1497 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1498 return DAG.getConstant(0, VT); // X > MAX --> false
1499 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1500 return DAG.getConstant(1, VT); // X <= MAX --> true
1502 // Canonicalize setgt X, Min --> setne X, Min
1503 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1504 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1505 // Canonicalize setlt X, Max --> setne X, Max
1506 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1507 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1509 // If we have setult X, 1, turn it into seteq X, 0
1510 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1511 return DAG.getSetCC(dl, VT, N0,
1512 DAG.getConstant(MinVal, N0.getValueType()),
1514 // If we have setugt X, Max-1, turn it into seteq X, Max
1515 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1516 return DAG.getSetCC(dl, VT, N0,
1517 DAG.getConstant(MaxVal, N0.getValueType()),
1520 // If we have "setcc X, C0", check to see if we can shrink the immediate
1523 // SETUGT X, SINTMAX -> SETLT X, 0
1524 if (Cond == ISD::SETUGT &&
1525 C1 == APInt::getSignedMaxValue(OperandBitSize))
1526 return DAG.getSetCC(dl, VT, N0,
1527 DAG.getConstant(0, N1.getValueType()),
1530 // SETULT X, SINTMIN -> SETGT X, -1
1531 if (Cond == ISD::SETULT &&
1532 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1533 SDValue ConstMinusOne =
1534 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1536 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1539 // Fold bit comparisons when we can.
1540 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1541 (VT == N0.getValueType() ||
1542 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1543 N0.getOpcode() == ISD::AND)
1544 if (ConstantSDNode *AndRHS =
1545 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1546 EVT ShiftTy = DCI.isBeforeLegalize() ?
1547 getPointerTy() : getShiftAmountTy(N0.getValueType());
1548 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1549 // Perform the xform if the AND RHS is a single bit.
1550 if (AndRHS->getAPIntValue().isPowerOf2()) {
1551 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1552 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1553 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1555 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1556 // (X & 8) == 8 --> (X & 8) >> 3
1557 // Perform the xform if C1 is a single bit.
1558 if (C1.isPowerOf2()) {
1559 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1560 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1561 DAG.getConstant(C1.logBase2(), ShiftTy)));
1566 if (C1.getMinSignedBits() <= 64 &&
1567 !isLegalICmpImmediate(C1.getSExtValue())) {
1568 // (X & -256) == 256 -> (X >> 8) == 1
1569 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1570 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1571 if (ConstantSDNode *AndRHS =
1572 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1573 const APInt &AndRHSC = AndRHS->getAPIntValue();
1574 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1575 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1576 EVT ShiftTy = DCI.isBeforeLegalize() ?
1577 getPointerTy() : getShiftAmountTy(N0.getValueType());
1578 EVT CmpTy = N0.getValueType();
1579 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1580 DAG.getConstant(ShiftBits, ShiftTy));
1581 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1582 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1585 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1586 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1587 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1588 // X < 0x100000000 -> (X >> 32) < 1
1589 // X >= 0x100000000 -> (X >> 32) >= 1
1590 // X <= 0x0ffffffff -> (X >> 32) < 1
1591 // X > 0x0ffffffff -> (X >> 32) >= 1
1594 ISD::CondCode NewCond = Cond;
1596 ShiftBits = C1.countTrailingOnes();
1598 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1600 ShiftBits = C1.countTrailingZeros();
1602 NewC = NewC.lshr(ShiftBits);
1603 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1604 EVT ShiftTy = DCI.isBeforeLegalize() ?
1605 getPointerTy() : getShiftAmountTy(N0.getValueType());
1606 EVT CmpTy = N0.getValueType();
1607 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1608 DAG.getConstant(ShiftBits, ShiftTy));
1609 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1610 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1616 if (isa<ConstantFPSDNode>(N0.getNode())) {
1617 // Constant fold or commute setcc.
1618 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1619 if (O.getNode()) return O;
1620 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1621 // If the RHS of an FP comparison is a constant, simplify it away in
1623 if (CFP->getValueAPF().isNaN()) {
1624 // If an operand is known to be a nan, we can fold it.
1625 switch (ISD::getUnorderedFlavor(Cond)) {
1626 default: llvm_unreachable("Unknown flavor!");
1627 case 0: // Known false.
1628 return DAG.getConstant(0, VT);
1629 case 1: // Known true.
1630 return DAG.getConstant(1, VT);
1631 case 2: // Undefined.
1632 return DAG.getUNDEF(VT);
1636 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1637 // constant if knowing that the operand is non-nan is enough. We prefer to
1638 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1640 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1641 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1643 // If the condition is not legal, see if we can find an equivalent one
1645 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1646 // If the comparison was an awkward floating-point == or != and one of
1647 // the comparison operands is infinity or negative infinity, convert the
1648 // condition to a less-awkward <= or >=.
1649 if (CFP->getValueAPF().isInfinity()) {
1650 if (CFP->getValueAPF().isNegative()) {
1651 if (Cond == ISD::SETOEQ &&
1652 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1653 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1654 if (Cond == ISD::SETUEQ &&
1655 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1656 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1657 if (Cond == ISD::SETUNE &&
1658 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1659 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1660 if (Cond == ISD::SETONE &&
1661 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1662 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1664 if (Cond == ISD::SETOEQ &&
1665 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1666 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1667 if (Cond == ISD::SETUEQ &&
1668 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1669 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1670 if (Cond == ISD::SETUNE &&
1671 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1672 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1673 if (Cond == ISD::SETONE &&
1674 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1675 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1682 // The sext(setcc()) => setcc() optimization relies on the appropriate
1683 // constant being emitted.
1685 switch (getBooleanContents(N0.getValueType().isVector())) {
1686 case UndefinedBooleanContent:
1687 case ZeroOrOneBooleanContent:
1688 EqVal = ISD::isTrueWhenEqual(Cond);
1690 case ZeroOrNegativeOneBooleanContent:
1691 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1695 // We can always fold X == X for integer setcc's.
1696 if (N0.getValueType().isInteger()) {
1697 return DAG.getConstant(EqVal, VT);
1699 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1700 if (UOF == 2) // FP operators that are undefined on NaNs.
1701 return DAG.getConstant(EqVal, VT);
1702 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1703 return DAG.getConstant(EqVal, VT);
1704 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1705 // if it is not already.
1706 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1707 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1708 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1709 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1712 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1713 N0.getValueType().isInteger()) {
1714 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1715 N0.getOpcode() == ISD::XOR) {
1716 // Simplify (X+Y) == (X+Z) --> Y == Z
1717 if (N0.getOpcode() == N1.getOpcode()) {
1718 if (N0.getOperand(0) == N1.getOperand(0))
1719 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1720 if (N0.getOperand(1) == N1.getOperand(1))
1721 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1722 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1723 // If X op Y == Y op X, try other combinations.
1724 if (N0.getOperand(0) == N1.getOperand(1))
1725 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1727 if (N0.getOperand(1) == N1.getOperand(0))
1728 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1733 // If RHS is a legal immediate value for a compare instruction, we need
1734 // to be careful about increasing register pressure needlessly.
1735 bool LegalRHSImm = false;
1737 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1738 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1739 // Turn (X+C1) == C2 --> X == C2-C1
1740 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1741 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1742 DAG.getConstant(RHSC->getAPIntValue()-
1743 LHSR->getAPIntValue(),
1744 N0.getValueType()), Cond);
1747 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1748 if (N0.getOpcode() == ISD::XOR)
1749 // If we know that all of the inverted bits are zero, don't bother
1750 // performing the inversion.
1751 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1753 DAG.getSetCC(dl, VT, N0.getOperand(0),
1754 DAG.getConstant(LHSR->getAPIntValue() ^
1755 RHSC->getAPIntValue(),
1760 // Turn (C1-X) == C2 --> X == C1-C2
1761 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1762 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1764 DAG.getSetCC(dl, VT, N0.getOperand(1),
1765 DAG.getConstant(SUBC->getAPIntValue() -
1766 RHSC->getAPIntValue(),
1772 // Could RHSC fold directly into a compare?
1773 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1774 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1777 // Simplify (X+Z) == X --> Z == 0
1778 // Don't do this if X is an immediate that can fold into a cmp
1779 // instruction and X+Z has other uses. It could be an induction variable
1780 // chain, and the transform would increase register pressure.
1781 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1782 if (N0.getOperand(0) == N1)
1783 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1784 DAG.getConstant(0, N0.getValueType()), Cond);
1785 if (N0.getOperand(1) == N1) {
1786 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1787 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1788 DAG.getConstant(0, N0.getValueType()), Cond);
1789 if (N0.getNode()->hasOneUse()) {
1790 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1791 // (Z-X) == X --> Z == X<<1
1792 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1793 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1794 if (!DCI.isCalledByLegalizer())
1795 DCI.AddToWorklist(SH.getNode());
1796 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1802 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1803 N1.getOpcode() == ISD::XOR) {
1804 // Simplify X == (X+Z) --> Z == 0
1805 if (N1.getOperand(0) == N0)
1806 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1807 DAG.getConstant(0, N1.getValueType()), Cond);
1808 if (N1.getOperand(1) == N0) {
1809 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1810 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1811 DAG.getConstant(0, N1.getValueType()), Cond);
1812 if (N1.getNode()->hasOneUse()) {
1813 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1814 // X == (Z-X) --> X<<1 == Z
1815 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1816 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1817 if (!DCI.isCalledByLegalizer())
1818 DCI.AddToWorklist(SH.getNode());
1819 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1824 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1825 // Note that where y is variable and is known to have at most
1826 // one bit set (for example, if it is z&1) we cannot do this;
1827 // the expressions are not equivalent when y==0.
1828 if (N0.getOpcode() == ISD::AND)
1829 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1830 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1831 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1832 if (DCI.isBeforeLegalizeOps() ||
1833 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1834 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1835 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1839 if (N1.getOpcode() == ISD::AND)
1840 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1841 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1842 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1843 if (DCI.isBeforeLegalizeOps() ||
1844 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1845 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1846 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1852 // Fold away ALL boolean setcc's.
1854 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1856 default: llvm_unreachable("Unknown integer setcc!");
1857 case ISD::SETEQ: // X == Y -> ~(X^Y)
1858 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1859 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1860 if (!DCI.isCalledByLegalizer())
1861 DCI.AddToWorklist(Temp.getNode());
1863 case ISD::SETNE: // X != Y --> (X^Y)
1864 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1866 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1867 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1868 Temp = DAG.getNOT(dl, N0, MVT::i1);
1869 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1870 if (!DCI.isCalledByLegalizer())
1871 DCI.AddToWorklist(Temp.getNode());
1873 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1874 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1875 Temp = DAG.getNOT(dl, N1, MVT::i1);
1876 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1877 if (!DCI.isCalledByLegalizer())
1878 DCI.AddToWorklist(Temp.getNode());
1880 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1881 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1882 Temp = DAG.getNOT(dl, N0, MVT::i1);
1883 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1884 if (!DCI.isCalledByLegalizer())
1885 DCI.AddToWorklist(Temp.getNode());
1887 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1888 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1889 Temp = DAG.getNOT(dl, N1, MVT::i1);
1890 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1893 if (VT != MVT::i1) {
1894 if (!DCI.isCalledByLegalizer())
1895 DCI.AddToWorklist(N0.getNode());
1896 // FIXME: If running after legalize, we probably can't do this.
1897 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1902 // Could not fold it.
1906 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1907 /// node is a GlobalAddress + offset.
1908 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
1909 int64_t &Offset) const {
1910 if (isa<GlobalAddressSDNode>(N)) {
1911 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
1912 GA = GASD->getGlobal();
1913 Offset += GASD->getOffset();
1917 if (N->getOpcode() == ISD::ADD) {
1918 SDValue N1 = N->getOperand(0);
1919 SDValue N2 = N->getOperand(1);
1920 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
1921 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
1923 Offset += V->getSExtValue();
1926 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
1927 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
1929 Offset += V->getSExtValue();
1939 SDValue TargetLowering::
1940 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1941 // Default implementation: no optimization.
1945 //===----------------------------------------------------------------------===//
1946 // Inline Assembler Implementation Methods
1947 //===----------------------------------------------------------------------===//
1950 TargetLowering::ConstraintType
1951 TargetLowering::getConstraintType(const std::string &Constraint) const {
1952 unsigned S = Constraint.size();
1955 switch (Constraint[0]) {
1957 case 'r': return C_RegisterClass;
1959 case 'o': // offsetable
1960 case 'V': // not offsetable
1962 case 'i': // Simple Integer or Relocatable Constant
1963 case 'n': // Simple Integer
1964 case 'E': // Floating Point Constant
1965 case 'F': // Floating Point Constant
1966 case 's': // Relocatable Constant
1967 case 'p': // Address.
1968 case 'X': // Allow ANY value.
1969 case 'I': // Target registers.
1983 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
1984 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
1991 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1992 /// with another that has more specific requirements based on the type of the
1993 /// corresponding operand.
1994 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
1995 if (ConstraintVT.isInteger())
1997 if (ConstraintVT.isFloatingPoint())
1998 return "f"; // works for many targets
2002 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2003 /// vector. If it is invalid, don't add anything to Ops.
2004 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2005 std::string &Constraint,
2006 std::vector<SDValue> &Ops,
2007 SelectionDAG &DAG) const {
2009 if (Constraint.length() > 1) return;
2011 char ConstraintLetter = Constraint[0];
2012 switch (ConstraintLetter) {
2014 case 'X': // Allows any operand; labels (basic block) use this.
2015 if (Op.getOpcode() == ISD::BasicBlock) {
2020 case 'i': // Simple Integer or Relocatable Constant
2021 case 'n': // Simple Integer
2022 case 's': { // Relocatable Constant
2023 // These operands are interested in values of the form (GV+C), where C may
2024 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2025 // is possible and fine if either GV or C are missing.
2026 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2027 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2029 // If we have "(add GV, C)", pull out GV/C
2030 if (Op.getOpcode() == ISD::ADD) {
2031 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2032 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2033 if (C == 0 || GA == 0) {
2034 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2035 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2037 if (C == 0 || GA == 0)
2041 // If we find a valid operand, map to the TargetXXX version so that the
2042 // value itself doesn't get selected.
2043 if (GA) { // Either &GV or &GV+C
2044 if (ConstraintLetter != 'n') {
2045 int64_t Offs = GA->getOffset();
2046 if (C) Offs += C->getZExtValue();
2047 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2048 C ? SDLoc(C) : SDLoc(),
2049 Op.getValueType(), Offs));
2053 if (C) { // just C, no GV.
2054 // Simple constants are not allowed for 's'.
2055 if (ConstraintLetter != 's') {
2056 // gcc prints these as sign extended. Sign extend value to 64 bits
2057 // now; without this it would get ZExt'd later in
2058 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2059 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2069 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2070 getRegForInlineAsmConstraint(const std::string &Constraint,
2072 if (Constraint.empty() || Constraint[0] != '{')
2073 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2074 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2076 // Remove the braces from around the name.
2077 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2079 std::pair<unsigned, const TargetRegisterClass*> R =
2080 std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2082 // Figure out which register class contains this reg.
2083 const TargetRegisterInfo *RI = getTargetMachine().getRegisterInfo();
2084 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2085 E = RI->regclass_end(); RCI != E; ++RCI) {
2086 const TargetRegisterClass *RC = *RCI;
2088 // If none of the value types for this register class are valid, we
2089 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2093 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2095 if (RegName.equals_lower(RI->getName(*I))) {
2096 std::pair<unsigned, const TargetRegisterClass*> S =
2097 std::make_pair(*I, RC);
2099 // If this register class has the requested value type, return it,
2100 // otherwise keep searching and return the first class found
2101 // if no other is found which explicitly has the requested type.
2102 if (RC->hasType(VT))
2113 //===----------------------------------------------------------------------===//
2114 // Constraint Selection.
2116 /// isMatchingInputConstraint - Return true of this is an input operand that is
2117 /// a matching constraint like "4".
2118 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2119 assert(!ConstraintCode.empty() && "No known constraint!");
2120 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2123 /// getMatchedOperand - If this is an input matching constraint, this method
2124 /// returns the output operand it matches.
2125 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2126 assert(!ConstraintCode.empty() && "No known constraint!");
2127 return atoi(ConstraintCode.c_str());
2131 /// ParseConstraints - Split up the constraint string from the inline
2132 /// assembly value into the specific constraints and their prefixes,
2133 /// and also tie in the associated operand values.
2134 /// If this returns an empty vector, and if the constraint string itself
2135 /// isn't empty, there was an error parsing.
2136 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2137 ImmutableCallSite CS) const {
2138 /// ConstraintOperands - Information about all of the constraints.
2139 AsmOperandInfoVector ConstraintOperands;
2140 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2141 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2143 // Do a prepass over the constraints, canonicalizing them, and building up the
2144 // ConstraintOperands list.
2145 InlineAsm::ConstraintInfoVector
2146 ConstraintInfos = IA->ParseConstraints();
2148 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2149 unsigned ResNo = 0; // ResNo - The result number of the next output.
2151 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2152 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2153 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2155 // Update multiple alternative constraint count.
2156 if (OpInfo.multipleAlternatives.size() > maCount)
2157 maCount = OpInfo.multipleAlternatives.size();
2159 OpInfo.ConstraintVT = MVT::Other;
2161 // Compute the value type for each operand.
2162 switch (OpInfo.Type) {
2163 case InlineAsm::isOutput:
2164 // Indirect outputs just consume an argument.
2165 if (OpInfo.isIndirect) {
2166 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2170 // The return value of the call is this value. As such, there is no
2171 // corresponding argument.
2172 assert(!CS.getType()->isVoidTy() &&
2174 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2175 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2177 assert(ResNo == 0 && "Asm only has one result!");
2178 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2182 case InlineAsm::isInput:
2183 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2185 case InlineAsm::isClobber:
2190 if (OpInfo.CallOperandVal) {
2191 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2192 if (OpInfo.isIndirect) {
2193 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2195 report_fatal_error("Indirect operand for inline asm not a pointer!");
2196 OpTy = PtrTy->getElementType();
2199 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2200 if (StructType *STy = dyn_cast<StructType>(OpTy))
2201 if (STy->getNumElements() == 1)
2202 OpTy = STy->getElementType(0);
2204 // If OpTy is not a single value, it may be a struct/union that we
2205 // can tile with integers.
2206 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2207 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2216 OpInfo.ConstraintVT =
2217 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2220 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2222 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2223 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2225 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2230 // If we have multiple alternative constraints, select the best alternative.
2231 if (ConstraintInfos.size()) {
2233 unsigned bestMAIndex = 0;
2234 int bestWeight = -1;
2235 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2238 // Compute the sums of the weights for each alternative, keeping track
2239 // of the best (highest weight) one so far.
2240 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2242 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2243 cIndex != eIndex; ++cIndex) {
2244 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2245 if (OpInfo.Type == InlineAsm::isClobber)
2248 // If this is an output operand with a matching input operand,
2249 // look up the matching input. If their types mismatch, e.g. one
2250 // is an integer, the other is floating point, or their sizes are
2251 // different, flag it as an maCantMatch.
2252 if (OpInfo.hasMatchingInput()) {
2253 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2254 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2255 if ((OpInfo.ConstraintVT.isInteger() !=
2256 Input.ConstraintVT.isInteger()) ||
2257 (OpInfo.ConstraintVT.getSizeInBits() !=
2258 Input.ConstraintVT.getSizeInBits())) {
2259 weightSum = -1; // Can't match.
2264 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2269 weightSum += weight;
2272 if (weightSum > bestWeight) {
2273 bestWeight = weightSum;
2274 bestMAIndex = maIndex;
2278 // Now select chosen alternative in each constraint.
2279 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2280 cIndex != eIndex; ++cIndex) {
2281 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2282 if (cInfo.Type == InlineAsm::isClobber)
2284 cInfo.selectAlternative(bestMAIndex);
2289 // Check and hook up tied operands, choose constraint code to use.
2290 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2291 cIndex != eIndex; ++cIndex) {
2292 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2294 // If this is an output operand with a matching input operand, look up the
2295 // matching input. If their types mismatch, e.g. one is an integer, the
2296 // other is floating point, or their sizes are different, flag it as an
2298 if (OpInfo.hasMatchingInput()) {
2299 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2301 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2302 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2303 getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2304 OpInfo.ConstraintVT);
2305 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2306 getRegForInlineAsmConstraint(Input.ConstraintCode,
2307 Input.ConstraintVT);
2308 if ((OpInfo.ConstraintVT.isInteger() !=
2309 Input.ConstraintVT.isInteger()) ||
2310 (MatchRC.second != InputRC.second)) {
2311 report_fatal_error("Unsupported asm: input constraint"
2312 " with a matching output constraint of"
2313 " incompatible type!");
2320 return ConstraintOperands;
2324 /// getConstraintGenerality - Return an integer indicating how general CT
2326 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2328 case TargetLowering::C_Other:
2329 case TargetLowering::C_Unknown:
2331 case TargetLowering::C_Register:
2333 case TargetLowering::C_RegisterClass:
2335 case TargetLowering::C_Memory:
2338 llvm_unreachable("Invalid constraint type");
2341 /// Examine constraint type and operand type and determine a weight value.
2342 /// This object must already have been set up with the operand type
2343 /// and the current alternative constraint selected.
2344 TargetLowering::ConstraintWeight
2345 TargetLowering::getMultipleConstraintMatchWeight(
2346 AsmOperandInfo &info, int maIndex) const {
2347 InlineAsm::ConstraintCodeVector *rCodes;
2348 if (maIndex >= (int)info.multipleAlternatives.size())
2349 rCodes = &info.Codes;
2351 rCodes = &info.multipleAlternatives[maIndex].Codes;
2352 ConstraintWeight BestWeight = CW_Invalid;
2354 // Loop over the options, keeping track of the most general one.
2355 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2356 ConstraintWeight weight =
2357 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2358 if (weight > BestWeight)
2359 BestWeight = weight;
2365 /// Examine constraint type and operand type and determine a weight value.
2366 /// This object must already have been set up with the operand type
2367 /// and the current alternative constraint selected.
2368 TargetLowering::ConstraintWeight
2369 TargetLowering::getSingleConstraintMatchWeight(
2370 AsmOperandInfo &info, const char *constraint) const {
2371 ConstraintWeight weight = CW_Invalid;
2372 Value *CallOperandVal = info.CallOperandVal;
2373 // If we don't have a value, we can't do a match,
2374 // but allow it at the lowest weight.
2375 if (CallOperandVal == NULL)
2377 // Look at the constraint type.
2378 switch (*constraint) {
2379 case 'i': // immediate integer.
2380 case 'n': // immediate integer with a known value.
2381 if (isa<ConstantInt>(CallOperandVal))
2382 weight = CW_Constant;
2384 case 's': // non-explicit intregal immediate.
2385 if (isa<GlobalValue>(CallOperandVal))
2386 weight = CW_Constant;
2388 case 'E': // immediate float if host format.
2389 case 'F': // immediate float.
2390 if (isa<ConstantFP>(CallOperandVal))
2391 weight = CW_Constant;
2393 case '<': // memory operand with autodecrement.
2394 case '>': // memory operand with autoincrement.
2395 case 'm': // memory operand.
2396 case 'o': // offsettable memory operand
2397 case 'V': // non-offsettable memory operand
2400 case 'r': // general register.
2401 case 'g': // general register, memory operand or immediate integer.
2402 // note: Clang converts "g" to "imr".
2403 if (CallOperandVal->getType()->isIntegerTy())
2404 weight = CW_Register;
2406 case 'X': // any operand.
2408 weight = CW_Default;
2414 /// ChooseConstraint - If there are multiple different constraints that we
2415 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2416 /// This is somewhat tricky: constraints fall into four classes:
2417 /// Other -> immediates and magic values
2418 /// Register -> one specific register
2419 /// RegisterClass -> a group of regs
2420 /// Memory -> memory
2421 /// Ideally, we would pick the most specific constraint possible: if we have
2422 /// something that fits into a register, we would pick it. The problem here
2423 /// is that if we have something that could either be in a register or in
2424 /// memory that use of the register could cause selection of *other*
2425 /// operands to fail: they might only succeed if we pick memory. Because of
2426 /// this the heuristic we use is:
2428 /// 1) If there is an 'other' constraint, and if the operand is valid for
2429 /// that constraint, use it. This makes us take advantage of 'i'
2430 /// constraints when available.
2431 /// 2) Otherwise, pick the most general constraint present. This prefers
2432 /// 'm' over 'r', for example.
2434 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2435 const TargetLowering &TLI,
2436 SDValue Op, SelectionDAG *DAG) {
2437 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2438 unsigned BestIdx = 0;
2439 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2440 int BestGenerality = -1;
2442 // Loop over the options, keeping track of the most general one.
2443 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2444 TargetLowering::ConstraintType CType =
2445 TLI.getConstraintType(OpInfo.Codes[i]);
2447 // If this is an 'other' constraint, see if the operand is valid for it.
2448 // For example, on X86 we might have an 'rI' constraint. If the operand
2449 // is an integer in the range [0..31] we want to use I (saving a load
2450 // of a register), otherwise we must use 'r'.
2451 if (CType == TargetLowering::C_Other && Op.getNode()) {
2452 assert(OpInfo.Codes[i].size() == 1 &&
2453 "Unhandled multi-letter 'other' constraint");
2454 std::vector<SDValue> ResultOps;
2455 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2457 if (!ResultOps.empty()) {
2464 // Things with matching constraints can only be registers, per gcc
2465 // documentation. This mainly affects "g" constraints.
2466 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2469 // This constraint letter is more general than the previous one, use it.
2470 int Generality = getConstraintGenerality(CType);
2471 if (Generality > BestGenerality) {
2474 BestGenerality = Generality;
2478 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2479 OpInfo.ConstraintType = BestType;
2482 /// ComputeConstraintToUse - Determines the constraint code and constraint
2483 /// type to use for the specific AsmOperandInfo, setting
2484 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2485 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2487 SelectionDAG *DAG) const {
2488 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2490 // Single-letter constraints ('r') are very common.
2491 if (OpInfo.Codes.size() == 1) {
2492 OpInfo.ConstraintCode = OpInfo.Codes[0];
2493 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2495 ChooseConstraint(OpInfo, *this, Op, DAG);
2498 // 'X' matches anything.
2499 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2500 // Labels and constants are handled elsewhere ('X' is the only thing
2501 // that matches labels). For Functions, the type here is the type of
2502 // the result, which is not what we want to look at; leave them alone.
2503 Value *v = OpInfo.CallOperandVal;
2504 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2505 OpInfo.CallOperandVal = v;
2509 // Otherwise, try to resolve it to something we know about by looking at
2510 // the actual operand type.
2511 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2512 OpInfo.ConstraintCode = Repl;
2513 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2518 /// \brief Given an exact SDIV by a constant, create a multiplication
2519 /// with the multiplicative inverse of the constant.
2520 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2521 SelectionDAG &DAG) const {
2522 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2523 APInt d = C->getAPIntValue();
2524 assert(d != 0 && "Division by zero!");
2526 // Shift the value upfront if it is even, so the LSB is one.
2527 unsigned ShAmt = d.countTrailingZeros();
2529 // TODO: For UDIV use SRL instead of SRA.
2530 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2531 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
2535 // Calculate the multiplicative inverse, using Newton's method.
2537 while ((t = d*xn) != 1)
2538 xn *= APInt(d.getBitWidth(), 2) - t;
2540 Op2 = DAG.getConstant(xn, Op1.getValueType());
2541 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2544 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2545 /// return a DAG expression to select that will generate the same value by
2546 /// multiplying by a magic number. See:
2547 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2548 SDValue TargetLowering::
2549 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2550 std::vector<SDNode*> *Created) const {
2551 EVT VT = N->getValueType(0);
2554 // Check to see if we can do this.
2555 // FIXME: We should be more aggressive here.
2556 if (!isTypeLegal(VT))
2559 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2560 APInt::ms magics = d.magic();
2562 // Multiply the numerator (operand 0) by the magic value
2563 // FIXME: We should support doing a MUL in a wider type
2565 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2566 isOperationLegalOrCustom(ISD::MULHS, VT))
2567 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2568 DAG.getConstant(magics.m, VT));
2569 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2570 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2571 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2573 DAG.getConstant(magics.m, VT)).getNode(), 1);
2575 return SDValue(); // No mulhs or equvialent
2576 // If d > 0 and m < 0, add the numerator
2577 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2578 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2580 Created->push_back(Q.getNode());
2582 // If d < 0 and m > 0, subtract the numerator.
2583 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2584 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2586 Created->push_back(Q.getNode());
2588 // Shift right algebraic if shift value is nonzero
2590 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2591 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2593 Created->push_back(Q.getNode());
2595 // Extract the sign bit and add it to the quotient
2597 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2598 getShiftAmountTy(Q.getValueType())));
2600 Created->push_back(T.getNode());
2601 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2604 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2605 /// return a DAG expression to select that will generate the same value by
2606 /// multiplying by a magic number. See:
2607 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2608 SDValue TargetLowering::
2609 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2610 std::vector<SDNode*> *Created) const {
2611 EVT VT = N->getValueType(0);
2614 // Check to see if we can do this.
2615 // FIXME: We should be more aggressive here.
2616 if (!isTypeLegal(VT))
2619 // FIXME: We should use a narrower constant when the upper
2620 // bits are known to be zero.
2621 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2622 APInt::mu magics = N1C.magicu();
2624 SDValue Q = N->getOperand(0);
2626 // If the divisor is even, we can avoid using the expensive fixup by shifting
2627 // the divided value upfront.
2628 if (magics.a != 0 && !N1C[0]) {
2629 unsigned Shift = N1C.countTrailingZeros();
2630 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2631 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2633 Created->push_back(Q.getNode());
2635 // Get magic number for the shifted divisor.
2636 magics = N1C.lshr(Shift).magicu(Shift);
2637 assert(magics.a == 0 && "Should use cheap fixup now");
2640 // Multiply the numerator (operand 0) by the magic value
2641 // FIXME: We should support doing a MUL in a wider type
2642 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2643 isOperationLegalOrCustom(ISD::MULHU, VT))
2644 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2645 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2646 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2647 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2648 DAG.getConstant(magics.m, VT)).getNode(), 1);
2650 return SDValue(); // No mulhu or equvialent
2652 Created->push_back(Q.getNode());
2654 if (magics.a == 0) {
2655 assert(magics.s < N1C.getBitWidth() &&
2656 "We shouldn't generate an undefined shift!");
2657 return DAG.getNode(ISD::SRL, dl, VT, Q,
2658 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2660 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2662 Created->push_back(NPQ.getNode());
2663 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2664 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2666 Created->push_back(NPQ.getNode());
2667 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2669 Created->push_back(NPQ.getNode());
2670 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2671 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2675 bool TargetLowering::
2676 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2677 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2678 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2679 "be a constant integer");