1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
35 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
36 bool isLocal = GV->hasLocalLinkage();
37 bool isDeclaration = GV->isDeclaration();
38 // FIXME: what should we do for protected and internal visibility?
39 // For variables, is internal different from hidden?
40 bool isHidden = GV->hasHiddenVisibility();
42 if (reloc == Reloc::PIC_) {
43 if (isLocal || isHidden)
44 return TLSModel::LocalDynamic;
46 return TLSModel::GeneralDynamic;
48 if (!isDeclaration || isHidden)
49 return TLSModel::LocalExec;
51 return TLSModel::InitialExec;
56 /// InitLibcallNames - Set default libcall names.
58 static void InitLibcallNames(const char **Names) {
59 Names[RTLIB::SHL_I16] = "__ashlhi3";
60 Names[RTLIB::SHL_I32] = "__ashlsi3";
61 Names[RTLIB::SHL_I64] = "__ashldi3";
62 Names[RTLIB::SHL_I128] = "__ashlti3";
63 Names[RTLIB::SRL_I16] = "__lshrhi3";
64 Names[RTLIB::SRL_I32] = "__lshrsi3";
65 Names[RTLIB::SRL_I64] = "__lshrdi3";
66 Names[RTLIB::SRL_I128] = "__lshrti3";
67 Names[RTLIB::SRA_I16] = "__ashrhi3";
68 Names[RTLIB::SRA_I32] = "__ashrsi3";
69 Names[RTLIB::SRA_I64] = "__ashrdi3";
70 Names[RTLIB::SRA_I128] = "__ashrti3";
71 Names[RTLIB::MUL_I8] = "__mulqi3";
72 Names[RTLIB::MUL_I16] = "__mulhi3";
73 Names[RTLIB::MUL_I32] = "__mulsi3";
74 Names[RTLIB::MUL_I64] = "__muldi3";
75 Names[RTLIB::MUL_I128] = "__multi3";
76 Names[RTLIB::SDIV_I8] = "__divqi3";
77 Names[RTLIB::SDIV_I16] = "__divhi3";
78 Names[RTLIB::SDIV_I32] = "__divsi3";
79 Names[RTLIB::SDIV_I64] = "__divdi3";
80 Names[RTLIB::SDIV_I128] = "__divti3";
81 Names[RTLIB::UDIV_I8] = "__udivqi3";
82 Names[RTLIB::UDIV_I16] = "__udivhi3";
83 Names[RTLIB::UDIV_I32] = "__udivsi3";
84 Names[RTLIB::UDIV_I64] = "__udivdi3";
85 Names[RTLIB::UDIV_I128] = "__udivti3";
86 Names[RTLIB::SREM_I8] = "__modqi3";
87 Names[RTLIB::SREM_I16] = "__modhi3";
88 Names[RTLIB::SREM_I32] = "__modsi3";
89 Names[RTLIB::SREM_I64] = "__moddi3";
90 Names[RTLIB::SREM_I128] = "__modti3";
91 Names[RTLIB::UREM_I8] = "__umodqi3";
92 Names[RTLIB::UREM_I16] = "__umodhi3";
93 Names[RTLIB::UREM_I32] = "__umodsi3";
94 Names[RTLIB::UREM_I64] = "__umoddi3";
95 Names[RTLIB::UREM_I128] = "__umodti3";
96 Names[RTLIB::NEG_I32] = "__negsi2";
97 Names[RTLIB::NEG_I64] = "__negdi2";
98 Names[RTLIB::ADD_F32] = "__addsf3";
99 Names[RTLIB::ADD_F64] = "__adddf3";
100 Names[RTLIB::ADD_F80] = "__addxf3";
101 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
102 Names[RTLIB::SUB_F32] = "__subsf3";
103 Names[RTLIB::SUB_F64] = "__subdf3";
104 Names[RTLIB::SUB_F80] = "__subxf3";
105 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
106 Names[RTLIB::MUL_F32] = "__mulsf3";
107 Names[RTLIB::MUL_F64] = "__muldf3";
108 Names[RTLIB::MUL_F80] = "__mulxf3";
109 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
110 Names[RTLIB::DIV_F32] = "__divsf3";
111 Names[RTLIB::DIV_F64] = "__divdf3";
112 Names[RTLIB::DIV_F80] = "__divxf3";
113 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
114 Names[RTLIB::REM_F32] = "fmodf";
115 Names[RTLIB::REM_F64] = "fmod";
116 Names[RTLIB::REM_F80] = "fmodl";
117 Names[RTLIB::REM_PPCF128] = "fmodl";
118 Names[RTLIB::POWI_F32] = "__powisf2";
119 Names[RTLIB::POWI_F64] = "__powidf2";
120 Names[RTLIB::POWI_F80] = "__powixf2";
121 Names[RTLIB::POWI_PPCF128] = "__powitf2";
122 Names[RTLIB::SQRT_F32] = "sqrtf";
123 Names[RTLIB::SQRT_F64] = "sqrt";
124 Names[RTLIB::SQRT_F80] = "sqrtl";
125 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
126 Names[RTLIB::LOG_F32] = "logf";
127 Names[RTLIB::LOG_F64] = "log";
128 Names[RTLIB::LOG_F80] = "logl";
129 Names[RTLIB::LOG_PPCF128] = "logl";
130 Names[RTLIB::LOG2_F32] = "log2f";
131 Names[RTLIB::LOG2_F64] = "log2";
132 Names[RTLIB::LOG2_F80] = "log2l";
133 Names[RTLIB::LOG2_PPCF128] = "log2l";
134 Names[RTLIB::LOG10_F32] = "log10f";
135 Names[RTLIB::LOG10_F64] = "log10";
136 Names[RTLIB::LOG10_F80] = "log10l";
137 Names[RTLIB::LOG10_PPCF128] = "log10l";
138 Names[RTLIB::EXP_F32] = "expf";
139 Names[RTLIB::EXP_F64] = "exp";
140 Names[RTLIB::EXP_F80] = "expl";
141 Names[RTLIB::EXP_PPCF128] = "expl";
142 Names[RTLIB::EXP2_F32] = "exp2f";
143 Names[RTLIB::EXP2_F64] = "exp2";
144 Names[RTLIB::EXP2_F80] = "exp2l";
145 Names[RTLIB::EXP2_PPCF128] = "exp2l";
146 Names[RTLIB::SIN_F32] = "sinf";
147 Names[RTLIB::SIN_F64] = "sin";
148 Names[RTLIB::SIN_F80] = "sinl";
149 Names[RTLIB::SIN_PPCF128] = "sinl";
150 Names[RTLIB::COS_F32] = "cosf";
151 Names[RTLIB::COS_F64] = "cos";
152 Names[RTLIB::COS_F80] = "cosl";
153 Names[RTLIB::COS_PPCF128] = "cosl";
154 Names[RTLIB::POW_F32] = "powf";
155 Names[RTLIB::POW_F64] = "pow";
156 Names[RTLIB::POW_F80] = "powl";
157 Names[RTLIB::POW_PPCF128] = "powl";
158 Names[RTLIB::CEIL_F32] = "ceilf";
159 Names[RTLIB::CEIL_F64] = "ceil";
160 Names[RTLIB::CEIL_F80] = "ceill";
161 Names[RTLIB::CEIL_PPCF128] = "ceill";
162 Names[RTLIB::TRUNC_F32] = "truncf";
163 Names[RTLIB::TRUNC_F64] = "trunc";
164 Names[RTLIB::TRUNC_F80] = "truncl";
165 Names[RTLIB::TRUNC_PPCF128] = "truncl";
166 Names[RTLIB::RINT_F32] = "rintf";
167 Names[RTLIB::RINT_F64] = "rint";
168 Names[RTLIB::RINT_F80] = "rintl";
169 Names[RTLIB::RINT_PPCF128] = "rintl";
170 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
171 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
172 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
173 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
174 Names[RTLIB::FLOOR_F32] = "floorf";
175 Names[RTLIB::FLOOR_F64] = "floor";
176 Names[RTLIB::FLOOR_F80] = "floorl";
177 Names[RTLIB::FLOOR_PPCF128] = "floorl";
178 Names[RTLIB::COPYSIGN_F32] = "copysignf";
179 Names[RTLIB::COPYSIGN_F64] = "copysign";
180 Names[RTLIB::COPYSIGN_F80] = "copysignl";
181 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
182 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
183 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
184 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
185 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
186 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
187 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
188 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
189 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
190 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
191 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
192 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
193 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
194 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
195 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
196 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
197 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
198 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
199 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
200 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
201 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
202 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
203 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
204 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
205 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
206 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
207 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
208 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
209 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
210 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
211 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
212 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
213 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
214 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
215 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
216 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
217 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
218 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
219 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
220 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
221 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
222 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
223 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
224 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
225 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
226 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
227 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
228 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
229 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
230 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
231 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
232 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
233 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
234 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
235 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
236 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
237 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
238 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
239 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
240 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
241 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
242 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
243 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
244 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
245 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
246 Names[RTLIB::OEQ_F32] = "__eqsf2";
247 Names[RTLIB::OEQ_F64] = "__eqdf2";
248 Names[RTLIB::UNE_F32] = "__nesf2";
249 Names[RTLIB::UNE_F64] = "__nedf2";
250 Names[RTLIB::OGE_F32] = "__gesf2";
251 Names[RTLIB::OGE_F64] = "__gedf2";
252 Names[RTLIB::OLT_F32] = "__ltsf2";
253 Names[RTLIB::OLT_F64] = "__ltdf2";
254 Names[RTLIB::OLE_F32] = "__lesf2";
255 Names[RTLIB::OLE_F64] = "__ledf2";
256 Names[RTLIB::OGT_F32] = "__gtsf2";
257 Names[RTLIB::OGT_F64] = "__gtdf2";
258 Names[RTLIB::UO_F32] = "__unordsf2";
259 Names[RTLIB::UO_F64] = "__unorddf2";
260 Names[RTLIB::O_F32] = "__unordsf2";
261 Names[RTLIB::O_F64] = "__unorddf2";
262 Names[RTLIB::MEMCPY] = "memcpy";
263 Names[RTLIB::MEMMOVE] = "memmove";
264 Names[RTLIB::MEMSET] = "memset";
265 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
269 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
273 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
274 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
276 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
277 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
280 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
281 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
282 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
283 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
284 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
285 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
286 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
287 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
288 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
289 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
292 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
293 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
296 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
297 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
300 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
302 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
303 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
304 CCs[i] = CallingConv::C;
308 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
309 /// UNKNOWN_LIBCALL if there is none.
310 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
311 if (OpVT == MVT::f32) {
312 if (RetVT == MVT::f64)
313 return FPEXT_F32_F64;
316 return UNKNOWN_LIBCALL;
319 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
320 /// UNKNOWN_LIBCALL if there is none.
321 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
322 if (RetVT == MVT::f32) {
323 if (OpVT == MVT::f64)
324 return FPROUND_F64_F32;
325 if (OpVT == MVT::f80)
326 return FPROUND_F80_F32;
327 if (OpVT == MVT::ppcf128)
328 return FPROUND_PPCF128_F32;
329 } else if (RetVT == MVT::f64) {
330 if (OpVT == MVT::f80)
331 return FPROUND_F80_F64;
332 if (OpVT == MVT::ppcf128)
333 return FPROUND_PPCF128_F64;
336 return UNKNOWN_LIBCALL;
339 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
340 /// UNKNOWN_LIBCALL if there is none.
341 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
342 if (OpVT == MVT::f32) {
343 if (RetVT == MVT::i8)
344 return FPTOSINT_F32_I8;
345 if (RetVT == MVT::i16)
346 return FPTOSINT_F32_I16;
347 if (RetVT == MVT::i32)
348 return FPTOSINT_F32_I32;
349 if (RetVT == MVT::i64)
350 return FPTOSINT_F32_I64;
351 if (RetVT == MVT::i128)
352 return FPTOSINT_F32_I128;
353 } else if (OpVT == MVT::f64) {
354 if (RetVT == MVT::i8)
355 return FPTOSINT_F64_I8;
356 if (RetVT == MVT::i16)
357 return FPTOSINT_F64_I16;
358 if (RetVT == MVT::i32)
359 return FPTOSINT_F64_I32;
360 if (RetVT == MVT::i64)
361 return FPTOSINT_F64_I64;
362 if (RetVT == MVT::i128)
363 return FPTOSINT_F64_I128;
364 } else if (OpVT == MVT::f80) {
365 if (RetVT == MVT::i32)
366 return FPTOSINT_F80_I32;
367 if (RetVT == MVT::i64)
368 return FPTOSINT_F80_I64;
369 if (RetVT == MVT::i128)
370 return FPTOSINT_F80_I128;
371 } else if (OpVT == MVT::ppcf128) {
372 if (RetVT == MVT::i32)
373 return FPTOSINT_PPCF128_I32;
374 if (RetVT == MVT::i64)
375 return FPTOSINT_PPCF128_I64;
376 if (RetVT == MVT::i128)
377 return FPTOSINT_PPCF128_I128;
379 return UNKNOWN_LIBCALL;
382 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
383 /// UNKNOWN_LIBCALL if there is none.
384 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
385 if (OpVT == MVT::f32) {
386 if (RetVT == MVT::i8)
387 return FPTOUINT_F32_I8;
388 if (RetVT == MVT::i16)
389 return FPTOUINT_F32_I16;
390 if (RetVT == MVT::i32)
391 return FPTOUINT_F32_I32;
392 if (RetVT == MVT::i64)
393 return FPTOUINT_F32_I64;
394 if (RetVT == MVT::i128)
395 return FPTOUINT_F32_I128;
396 } else if (OpVT == MVT::f64) {
397 if (RetVT == MVT::i8)
398 return FPTOUINT_F64_I8;
399 if (RetVT == MVT::i16)
400 return FPTOUINT_F64_I16;
401 if (RetVT == MVT::i32)
402 return FPTOUINT_F64_I32;
403 if (RetVT == MVT::i64)
404 return FPTOUINT_F64_I64;
405 if (RetVT == MVT::i128)
406 return FPTOUINT_F64_I128;
407 } else if (OpVT == MVT::f80) {
408 if (RetVT == MVT::i32)
409 return FPTOUINT_F80_I32;
410 if (RetVT == MVT::i64)
411 return FPTOUINT_F80_I64;
412 if (RetVT == MVT::i128)
413 return FPTOUINT_F80_I128;
414 } else if (OpVT == MVT::ppcf128) {
415 if (RetVT == MVT::i32)
416 return FPTOUINT_PPCF128_I32;
417 if (RetVT == MVT::i64)
418 return FPTOUINT_PPCF128_I64;
419 if (RetVT == MVT::i128)
420 return FPTOUINT_PPCF128_I128;
422 return UNKNOWN_LIBCALL;
425 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
426 /// UNKNOWN_LIBCALL if there is none.
427 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
428 if (OpVT == MVT::i32) {
429 if (RetVT == MVT::f32)
430 return SINTTOFP_I32_F32;
431 else if (RetVT == MVT::f64)
432 return SINTTOFP_I32_F64;
433 else if (RetVT == MVT::f80)
434 return SINTTOFP_I32_F80;
435 else if (RetVT == MVT::ppcf128)
436 return SINTTOFP_I32_PPCF128;
437 } else if (OpVT == MVT::i64) {
438 if (RetVT == MVT::f32)
439 return SINTTOFP_I64_F32;
440 else if (RetVT == MVT::f64)
441 return SINTTOFP_I64_F64;
442 else if (RetVT == MVT::f80)
443 return SINTTOFP_I64_F80;
444 else if (RetVT == MVT::ppcf128)
445 return SINTTOFP_I64_PPCF128;
446 } else if (OpVT == MVT::i128) {
447 if (RetVT == MVT::f32)
448 return SINTTOFP_I128_F32;
449 else if (RetVT == MVT::f64)
450 return SINTTOFP_I128_F64;
451 else if (RetVT == MVT::f80)
452 return SINTTOFP_I128_F80;
453 else if (RetVT == MVT::ppcf128)
454 return SINTTOFP_I128_PPCF128;
456 return UNKNOWN_LIBCALL;
459 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
460 /// UNKNOWN_LIBCALL if there is none.
461 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
462 if (OpVT == MVT::i32) {
463 if (RetVT == MVT::f32)
464 return UINTTOFP_I32_F32;
465 else if (RetVT == MVT::f64)
466 return UINTTOFP_I32_F64;
467 else if (RetVT == MVT::f80)
468 return UINTTOFP_I32_F80;
469 else if (RetVT == MVT::ppcf128)
470 return UINTTOFP_I32_PPCF128;
471 } else if (OpVT == MVT::i64) {
472 if (RetVT == MVT::f32)
473 return UINTTOFP_I64_F32;
474 else if (RetVT == MVT::f64)
475 return UINTTOFP_I64_F64;
476 else if (RetVT == MVT::f80)
477 return UINTTOFP_I64_F80;
478 else if (RetVT == MVT::ppcf128)
479 return UINTTOFP_I64_PPCF128;
480 } else if (OpVT == MVT::i128) {
481 if (RetVT == MVT::f32)
482 return UINTTOFP_I128_F32;
483 else if (RetVT == MVT::f64)
484 return UINTTOFP_I128_F64;
485 else if (RetVT == MVT::f80)
486 return UINTTOFP_I128_F80;
487 else if (RetVT == MVT::ppcf128)
488 return UINTTOFP_I128_PPCF128;
490 return UNKNOWN_LIBCALL;
493 /// InitCmpLibcallCCs - Set default comparison libcall CC.
495 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
499 CCs[RTLIB::UNE_F32] = ISD::SETNE;
500 CCs[RTLIB::UNE_F64] = ISD::SETNE;
501 CCs[RTLIB::OGE_F32] = ISD::SETGE;
502 CCs[RTLIB::OGE_F64] = ISD::SETGE;
503 CCs[RTLIB::OLT_F32] = ISD::SETLT;
504 CCs[RTLIB::OLT_F64] = ISD::SETLT;
505 CCs[RTLIB::OLE_F32] = ISD::SETLE;
506 CCs[RTLIB::OLE_F64] = ISD::SETLE;
507 CCs[RTLIB::OGT_F32] = ISD::SETGT;
508 CCs[RTLIB::OGT_F64] = ISD::SETGT;
509 CCs[RTLIB::UO_F32] = ISD::SETNE;
510 CCs[RTLIB::UO_F64] = ISD::SETNE;
511 CCs[RTLIB::O_F32] = ISD::SETEQ;
512 CCs[RTLIB::O_F64] = ISD::SETEQ;
515 /// NOTE: The constructor takes ownership of TLOF.
516 TargetLowering::TargetLowering(const TargetMachine &tm,
517 const TargetLoweringObjectFile *tlof)
518 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
519 // All operations default to being supported.
520 memset(OpActions, 0, sizeof(OpActions));
521 memset(LoadExtActions, 0, sizeof(LoadExtActions));
522 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
523 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
524 memset(CondCodeActions, 0, sizeof(CondCodeActions));
526 // Set default actions for various operations.
527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
528 // Default all indexed load / store to expand.
529 for (unsigned IM = (unsigned)ISD::PRE_INC;
530 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
535 // These operations default to expand.
536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
540 // Most targets ignore the @llvm.prefetch intrinsic.
541 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
543 // ConstantFP nodes default to expand. Targets can either change this to
544 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
545 // to optimize expansions for certain constants.
546 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
547 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
548 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
550 // These library functions default to expand.
551 setOperationAction(ISD::FLOG , MVT::f64, Expand);
552 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
553 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
554 setOperationAction(ISD::FEXP , MVT::f64, Expand);
555 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
556 setOperationAction(ISD::FLOG , MVT::f32, Expand);
557 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
558 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
559 setOperationAction(ISD::FEXP , MVT::f32, Expand);
560 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
562 // Default ISD::TRAP to expand (which turns it into abort).
563 setOperationAction(ISD::TRAP, MVT::Other, Expand);
565 IsLittleEndian = TD->isLittleEndian();
566 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
567 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
568 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
569 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
570 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
571 = maxStoresPerMemmoveOptSize = 4;
572 benefitFromCodePlacementOpt = false;
573 UseUnderscoreSetJmp = false;
574 UseUnderscoreLongJmp = false;
575 SelectIsExpensive = false;
576 IntDivIsCheap = false;
577 Pow2DivIsCheap = false;
578 JumpIsExpensive = false;
579 StackPointerRegisterToSaveRestore = 0;
580 ExceptionPointerRegister = 0;
581 ExceptionSelectorRegister = 0;
582 BooleanContents = UndefinedBooleanContent;
583 SchedPreferenceInfo = Sched::Latency;
585 JumpBufAlignment = 0;
586 PrefLoopAlignment = 0;
587 MinStackArgumentAlignment = 1;
588 ShouldFoldAtomicFences = false;
590 InitLibcallNames(LibcallRoutineNames);
591 InitCmpLibcallCCs(CmpLibcallCCs);
592 InitLibcallCallingConvs(LibcallCallingConvs);
595 TargetLowering::~TargetLowering() {
599 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
600 return MVT::getIntegerVT(8*TD->getPointerSize());
603 /// canOpTrap - Returns true if the operation can trap for the value type.
604 /// VT must be a legal type.
605 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
606 assert(isTypeLegal(VT));
621 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
622 unsigned &NumIntermediates,
624 TargetLowering *TLI) {
625 // Figure out the right, legal destination reg to copy into.
626 unsigned NumElts = VT.getVectorNumElements();
627 MVT EltTy = VT.getVectorElementType();
629 unsigned NumVectorRegs = 1;
631 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
632 // could break down into LHS/RHS like LegalizeDAG does.
633 if (!isPowerOf2_32(NumElts)) {
634 NumVectorRegs = NumElts;
638 // Divide the input until we get to a supported size. This will always
639 // end with a scalar if the target doesn't support vectors.
640 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
645 NumIntermediates = NumVectorRegs;
647 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
648 if (!TLI->isTypeLegal(NewVT))
650 IntermediateVT = NewVT;
652 EVT DestVT = TLI->getRegisterType(NewVT);
654 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
655 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
657 // Otherwise, promotion or legal types use the same number of registers as
658 // the vector decimated to the appropriate level.
659 return NumVectorRegs;
662 /// isLegalRC - Return true if the value types that can be represented by the
663 /// specified register class are all legal.
664 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
665 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
673 /// hasLegalSuperRegRegClasses - Return true if the specified register class
674 /// has one or more super-reg register classes that are legal.
676 TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
677 if (*RC->superregclasses_begin() == 0)
679 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
680 E = RC->superregclasses_end(); I != E; ++I) {
681 const TargetRegisterClass *RRC = *I;
688 /// findRepresentativeClass - Return the largest legal super-reg register class
689 /// of the register class for the specified type and its associated "cost".
690 std::pair<const TargetRegisterClass*, uint8_t>
691 TargetLowering::findRepresentativeClass(EVT VT) const {
692 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
694 return std::make_pair(RC, 0);
695 const TargetRegisterClass *BestRC = RC;
696 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
697 E = RC->superregclasses_end(); I != E; ++I) {
698 const TargetRegisterClass *RRC = *I;
699 if (RRC->isASubClass() || !isLegalRC(RRC))
701 if (!hasLegalSuperRegRegClasses(RRC))
702 return std::make_pair(RRC, 1);
705 return std::make_pair(BestRC, 1);
709 /// computeRegisterProperties - Once all of the register classes are added,
710 /// this allows us to compute derived properties we expose.
711 void TargetLowering::computeRegisterProperties() {
712 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
713 "Too many value types for ValueTypeActions to hold!");
715 // Everything defaults to needing one register.
716 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
717 NumRegistersForVT[i] = 1;
718 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
720 // ...except isVoid, which doesn't need any registers.
721 NumRegistersForVT[MVT::isVoid] = 0;
723 // Find the largest integer register class.
724 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
725 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
726 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
728 // Every integer value type larger than this largest register takes twice as
729 // many registers to represent as the previous ValueType.
730 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
731 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
732 if (!ExpandedVT.isInteger())
734 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
735 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
736 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
737 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
740 // Inspect all of the ValueType's smaller than the largest integer
741 // register to see which ones need promotion.
742 unsigned LegalIntReg = LargestIntReg;
743 for (unsigned IntReg = LargestIntReg - 1;
744 IntReg >= (unsigned)MVT::i1; --IntReg) {
745 EVT IVT = (MVT::SimpleValueType)IntReg;
746 if (isTypeLegal(IVT)) {
747 LegalIntReg = IntReg;
749 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
750 (MVT::SimpleValueType)LegalIntReg;
751 ValueTypeActions.setTypeAction(IVT, Promote);
755 // ppcf128 type is really two f64's.
756 if (!isTypeLegal(MVT::ppcf128)) {
757 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
758 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
759 TransformToType[MVT::ppcf128] = MVT::f64;
760 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
763 // Decide how to handle f64. If the target does not have native f64 support,
764 // expand it to i64 and we will be generating soft float library calls.
765 if (!isTypeLegal(MVT::f64)) {
766 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
767 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
768 TransformToType[MVT::f64] = MVT::i64;
769 ValueTypeActions.setTypeAction(MVT::f64, Expand);
772 // Decide how to handle f32. If the target does not have native support for
773 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
774 if (!isTypeLegal(MVT::f32)) {
775 if (isTypeLegal(MVT::f64)) {
776 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
777 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
778 TransformToType[MVT::f32] = MVT::f64;
779 ValueTypeActions.setTypeAction(MVT::f32, Promote);
781 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
782 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
783 TransformToType[MVT::f32] = MVT::i32;
784 ValueTypeActions.setTypeAction(MVT::f32, Expand);
788 // Loop over all of the vector value types to see which need transformations.
789 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
790 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
791 MVT VT = (MVT::SimpleValueType)i;
792 if (isTypeLegal(VT)) continue;
794 // Determine if there is a legal wider type. If so, we should promote to
795 // that wider vector type.
796 EVT EltVT = VT.getVectorElementType();
797 unsigned NElts = VT.getVectorNumElements();
799 bool IsLegalWiderType = false;
800 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
801 EVT SVT = (MVT::SimpleValueType)nVT;
802 if (SVT.getVectorElementType() == EltVT &&
803 SVT.getVectorNumElements() > NElts &&
805 TransformToType[i] = SVT;
806 RegisterTypeForVT[i] = SVT;
807 NumRegistersForVT[i] = 1;
808 ValueTypeActions.setTypeAction(VT, Promote);
809 IsLegalWiderType = true;
813 if (IsLegalWiderType) continue;
818 unsigned NumIntermediates;
819 NumRegistersForVT[i] =
820 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
822 RegisterTypeForVT[i] = RegisterVT;
824 EVT NVT = VT.getPow2VectorType();
826 // Type is already a power of 2. The default action is to split.
827 TransformToType[i] = MVT::Other;
828 ValueTypeActions.setTypeAction(VT, Expand);
830 TransformToType[i] = NVT;
831 ValueTypeActions.setTypeAction(VT, Promote);
835 // Determine the 'representative' register class for each value type.
836 // An representative register class is the largest (meaning one which is
837 // not a sub-register class / subreg register class) legal register class for
838 // a group of value types. For example, on i386, i8, i16, and i32
839 // representative would be GR32; while on x86_64 it's GR64.
840 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
841 const TargetRegisterClass* RRC;
843 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
844 RepRegClassForVT[i] = RRC;
845 RepRegClassCostForVT[i] = Cost;
849 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
854 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
855 return PointerTy.SimpleTy;
858 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
859 return MVT::i32; // return the default value
862 /// getVectorTypeBreakdown - Vector types are broken down into some number of
863 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
864 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
865 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
867 /// This method returns the number of registers needed, and the VT for each
868 /// register. It also returns the VT and quantity of the intermediate values
869 /// before they are promoted/expanded.
871 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
873 unsigned &NumIntermediates,
874 EVT &RegisterVT) const {
875 unsigned NumElts = VT.getVectorNumElements();
877 // If there is a wider vector type with the same element type as this one,
878 // we should widen to that legal vector type. This handles things like
879 // <2 x float> -> <4 x float>.
880 if (NumElts != 1 && getTypeAction(VT) == Promote) {
881 RegisterVT = getTypeToTransformTo(Context, VT);
882 if (isTypeLegal(RegisterVT)) {
883 IntermediateVT = RegisterVT;
884 NumIntermediates = 1;
889 // Figure out the right, legal destination reg to copy into.
890 EVT EltTy = VT.getVectorElementType();
892 unsigned NumVectorRegs = 1;
894 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
895 // could break down into LHS/RHS like LegalizeDAG does.
896 if (!isPowerOf2_32(NumElts)) {
897 NumVectorRegs = NumElts;
901 // Divide the input until we get to a supported size. This will always
902 // end with a scalar if the target doesn't support vectors.
903 while (NumElts > 1 && !isTypeLegal(
904 EVT::getVectorVT(Context, EltTy, NumElts))) {
909 NumIntermediates = NumVectorRegs;
911 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
912 if (!isTypeLegal(NewVT))
914 IntermediateVT = NewVT;
916 EVT DestVT = getRegisterType(Context, NewVT);
918 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
919 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
921 // Otherwise, promotion or legal types use the same number of registers as
922 // the vector decimated to the appropriate level.
923 return NumVectorRegs;
926 /// Get the EVTs and ArgFlags collections that represent the legalized return
927 /// type of the given function. This does not require a DAG or a return value,
928 /// and is suitable for use before any DAGs for the function are constructed.
929 /// TODO: Move this out of TargetLowering.cpp.
930 void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
931 SmallVectorImpl<ISD::OutputArg> &Outs,
932 const TargetLowering &TLI,
933 SmallVectorImpl<uint64_t> *Offsets) {
934 SmallVector<EVT, 4> ValueVTs;
935 ComputeValueVTs(TLI, ReturnType, ValueVTs);
936 unsigned NumValues = ValueVTs.size();
937 if (NumValues == 0) return;
940 for (unsigned j = 0, f = NumValues; j != f; ++j) {
941 EVT VT = ValueVTs[j];
942 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
944 if (attr & Attribute::SExt)
945 ExtendKind = ISD::SIGN_EXTEND;
946 else if (attr & Attribute::ZExt)
947 ExtendKind = ISD::ZERO_EXTEND;
949 // FIXME: C calling convention requires the return type to be promoted to
950 // at least 32-bit. But this is not necessary for non-C calling
951 // conventions. The frontend should mark functions whose return values
952 // require promoting with signext or zeroext attributes.
953 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
954 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
955 if (VT.bitsLT(MinVT))
959 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
960 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
961 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
962 PartVT.getTypeForEVT(ReturnType->getContext()));
964 // 'inreg' on function refers to return value
965 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
966 if (attr & Attribute::InReg)
969 // Propagate extension type if any
970 if (attr & Attribute::SExt)
972 else if (attr & Attribute::ZExt)
975 for (unsigned i = 0; i < NumParts; ++i) {
976 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
978 Offsets->push_back(Offset);
985 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
986 /// function arguments in the caller parameter area. This is the actual
987 /// alignment, not its logarithm.
988 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
989 return TD->getCallFrameTypeAlignment(Ty);
992 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
993 /// current function. The returned value is a member of the
994 /// MachineJumpTableInfo::JTEntryKind enum.
995 unsigned TargetLowering::getJumpTableEncoding() const {
996 // In non-pic modes, just use the address of a block.
997 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
998 return MachineJumpTableInfo::EK_BlockAddress;
1000 // In PIC mode, if the target supports a GPRel32 directive, use it.
1001 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1002 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1004 // Otherwise, use a label difference.
1005 return MachineJumpTableInfo::EK_LabelDifference32;
1008 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1009 SelectionDAG &DAG) const {
1010 // If our PIC model is GP relative, use the global offset table as the base.
1011 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
1012 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1016 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1017 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1020 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1021 unsigned JTI,MCContext &Ctx) const{
1022 // The normal PIC reloc base is the label at the start of the jump table.
1023 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1027 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1028 // Assume that everything is safe in static mode.
1029 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1032 // In dynamic-no-pic mode, assume that known defined values are safe.
1033 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1035 !GA->getGlobal()->isDeclaration() &&
1036 !GA->getGlobal()->isWeakForLinker())
1039 // Otherwise assume nothing is safe.
1043 //===----------------------------------------------------------------------===//
1044 // Optimization Methods
1045 //===----------------------------------------------------------------------===//
1047 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1048 /// specified instruction is a constant integer. If so, check to see if there
1049 /// are any bits set in the constant that are not demanded. If so, shrink the
1050 /// constant and return true.
1051 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1052 const APInt &Demanded) {
1053 DebugLoc dl = Op.getDebugLoc();
1055 // FIXME: ISD::SELECT, ISD::SELECT_CC
1056 switch (Op.getOpcode()) {
1061 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1062 if (!C) return false;
1064 if (Op.getOpcode() == ISD::XOR &&
1065 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1068 // if we can expand it to have all bits set, do it
1069 if (C->getAPIntValue().intersects(~Demanded)) {
1070 EVT VT = Op.getValueType();
1071 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1072 DAG.getConstant(Demanded &
1075 return CombineTo(Op, New);
1085 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1086 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1087 /// cast, but it could be generalized for targets with other types of
1088 /// implicit widening casts.
1090 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1092 const APInt &Demanded,
1094 assert(Op.getNumOperands() == 2 &&
1095 "ShrinkDemandedOp only supports binary operators!");
1096 assert(Op.getNode()->getNumValues() == 1 &&
1097 "ShrinkDemandedOp only supports nodes with one result!");
1099 // Don't do this if the node has another user, which may require the
1101 if (!Op.getNode()->hasOneUse())
1104 // Search for the smallest integer type with free casts to and from
1105 // Op's type. For expedience, just check power-of-2 integer types.
1106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1107 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1108 if (!isPowerOf2_32(SmallVTBits))
1109 SmallVTBits = NextPowerOf2(SmallVTBits);
1110 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1111 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1112 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1113 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1114 // We found a type with free casts.
1115 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1116 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1117 Op.getNode()->getOperand(0)),
1118 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1119 Op.getNode()->getOperand(1)));
1120 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1121 return CombineTo(Op, Z);
1127 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1128 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1129 /// use this information to simplify Op, create a new simplified DAG node and
1130 /// return true, returning the original and new nodes in Old and New. Otherwise,
1131 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
1132 /// the expression (used to simplify the caller). The KnownZero/One bits may
1133 /// only be accurate for those bits in the DemandedMask.
1134 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1135 const APInt &DemandedMask,
1138 TargetLoweringOpt &TLO,
1139 unsigned Depth) const {
1140 unsigned BitWidth = DemandedMask.getBitWidth();
1141 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1142 "Mask size mismatches value type size!");
1143 APInt NewMask = DemandedMask;
1144 DebugLoc dl = Op.getDebugLoc();
1146 // Don't know anything.
1147 KnownZero = KnownOne = APInt(BitWidth, 0);
1149 // Other users may use these bits.
1150 if (!Op.getNode()->hasOneUse()) {
1152 // If not at the root, Just compute the KnownZero/KnownOne bits to
1153 // simplify things downstream.
1154 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
1157 // If this is the root being simplified, allow it to have multiple uses,
1158 // just set the NewMask to all bits.
1159 NewMask = APInt::getAllOnesValue(BitWidth);
1160 } else if (DemandedMask == 0) {
1161 // Not demanding any bits from Op.
1162 if (Op.getOpcode() != ISD::UNDEF)
1163 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1165 } else if (Depth == 6) { // Limit search depth.
1169 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1170 switch (Op.getOpcode()) {
1172 // We know all of the bits for a constant!
1173 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1174 KnownZero = ~KnownOne & NewMask;
1175 return false; // Don't fall through, will infinitely loop.
1177 // If the RHS is a constant, check to see if the LHS would be zero without
1178 // using the bits from the RHS. Below, we use knowledge about the RHS to
1179 // simplify the LHS, here we're using information from the LHS to simplify
1181 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1182 APInt LHSZero, LHSOne;
1183 // Do not increment Depth here; that can cause an infinite loop.
1184 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
1185 LHSZero, LHSOne, Depth);
1186 // If the LHS already has zeros where RHSC does, this and is dead.
1187 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1188 return TLO.CombineTo(Op, Op.getOperand(0));
1189 // If any of the set bits in the RHS are known zero on the LHS, shrink
1191 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1195 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1196 KnownOne, TLO, Depth+1))
1198 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1199 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1200 KnownZero2, KnownOne2, TLO, Depth+1))
1202 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1204 // If all of the demanded bits are known one on one side, return the other.
1205 // These bits cannot contribute to the result of the 'and'.
1206 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1207 return TLO.CombineTo(Op, Op.getOperand(0));
1208 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1209 return TLO.CombineTo(Op, Op.getOperand(1));
1210 // If all of the demanded bits in the inputs are known zeros, return zero.
1211 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1212 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1213 // If the RHS is a constant, see if we can simplify it.
1214 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1216 // If the operation can be done in a smaller type, do so.
1217 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1220 // Output known-1 bits are only known if set in both the LHS & RHS.
1221 KnownOne &= KnownOne2;
1222 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1223 KnownZero |= KnownZero2;
1226 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1227 KnownOne, TLO, Depth+1))
1229 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1230 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1231 KnownZero2, KnownOne2, TLO, Depth+1))
1233 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1235 // If all of the demanded bits are known zero on one side, return the other.
1236 // These bits cannot contribute to the result of the 'or'.
1237 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1238 return TLO.CombineTo(Op, Op.getOperand(0));
1239 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1240 return TLO.CombineTo(Op, Op.getOperand(1));
1241 // If all of the potentially set bits on one side are known to be set on
1242 // the other side, just use the 'other' side.
1243 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1244 return TLO.CombineTo(Op, Op.getOperand(0));
1245 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1246 return TLO.CombineTo(Op, Op.getOperand(1));
1247 // If the RHS is a constant, see if we can simplify it.
1248 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1250 // If the operation can be done in a smaller type, do so.
1251 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1254 // Output known-0 bits are only known if clear in both the LHS & RHS.
1255 KnownZero &= KnownZero2;
1256 // Output known-1 are known to be set if set in either the LHS | RHS.
1257 KnownOne |= KnownOne2;
1260 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1261 KnownOne, TLO, Depth+1))
1263 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1264 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1265 KnownOne2, TLO, Depth+1))
1267 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1269 // If all of the demanded bits are known zero on one side, return the other.
1270 // These bits cannot contribute to the result of the 'xor'.
1271 if ((KnownZero & NewMask) == NewMask)
1272 return TLO.CombineTo(Op, Op.getOperand(0));
1273 if ((KnownZero2 & NewMask) == NewMask)
1274 return TLO.CombineTo(Op, Op.getOperand(1));
1275 // If the operation can be done in a smaller type, do so.
1276 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1279 // If all of the unknown bits are known to be zero on one side or the other
1280 // (but not both) turn this into an *inclusive* or.
1281 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1282 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1283 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1287 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1288 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1289 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1290 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1292 // If all of the demanded bits on one side are known, and all of the set
1293 // bits on that side are also known to be set on the other side, turn this
1294 // into an AND, as we know the bits will be cleared.
1295 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1296 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1297 if ((KnownOne & KnownOne2) == KnownOne) {
1298 EVT VT = Op.getValueType();
1299 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1300 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1301 Op.getOperand(0), ANDC));
1305 // If the RHS is a constant, see if we can simplify it.
1306 // for XOR, we prefer to force bits to 1 if they will make a -1.
1307 // if we can't force bits, try to shrink constant
1308 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1309 APInt Expanded = C->getAPIntValue() | (~NewMask);
1310 // if we can expand it to have all bits set, do it
1311 if (Expanded.isAllOnesValue()) {
1312 if (Expanded != C->getAPIntValue()) {
1313 EVT VT = Op.getValueType();
1314 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1315 TLO.DAG.getConstant(Expanded, VT));
1316 return TLO.CombineTo(Op, New);
1318 // if it already has all the bits set, nothing to change
1319 // but don't shrink either!
1320 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1325 KnownZero = KnownZeroOut;
1326 KnownOne = KnownOneOut;
1329 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1330 KnownOne, TLO, Depth+1))
1332 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1333 KnownOne2, TLO, Depth+1))
1335 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1336 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1338 // If the operands are constants, see if we can simplify them.
1339 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1342 // Only known if known in both the LHS and RHS.
1343 KnownOne &= KnownOne2;
1344 KnownZero &= KnownZero2;
1346 case ISD::SELECT_CC:
1347 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1348 KnownOne, TLO, Depth+1))
1350 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1351 KnownOne2, TLO, Depth+1))
1353 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1354 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1356 // If the operands are constants, see if we can simplify them.
1357 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1360 // Only known if known in both the LHS and RHS.
1361 KnownOne &= KnownOne2;
1362 KnownZero &= KnownZero2;
1365 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1366 unsigned ShAmt = SA->getZExtValue();
1367 SDValue InOp = Op.getOperand(0);
1369 // If the shift count is an invalid immediate, don't do anything.
1370 if (ShAmt >= BitWidth)
1373 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1374 // single shift. We can do this if the bottom bits (which are shifted
1375 // out) are never demanded.
1376 if (InOp.getOpcode() == ISD::SRL &&
1377 isa<ConstantSDNode>(InOp.getOperand(1))) {
1378 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1379 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1380 unsigned Opc = ISD::SHL;
1381 int Diff = ShAmt-C1;
1388 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1389 EVT VT = Op.getValueType();
1390 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1391 InOp.getOperand(0), NewSA));
1395 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1396 KnownZero, KnownOne, TLO, Depth+1))
1399 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1400 // are not demanded. This will likely allow the anyext to be folded away.
1401 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1402 SDValue InnerOp = InOp.getNode()->getOperand(0);
1403 EVT InnerVT = InnerOp.getValueType();
1404 if ((APInt::getHighBitsSet(BitWidth,
1405 BitWidth - InnerVT.getSizeInBits()) &
1406 DemandedMask) == 0 &&
1407 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1408 EVT ShTy = getShiftAmountTy(InnerVT);
1409 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1412 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1413 TLO.DAG.getConstant(ShAmt, ShTy));
1416 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1421 KnownZero <<= SA->getZExtValue();
1422 KnownOne <<= SA->getZExtValue();
1423 // low bits known zero.
1424 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1428 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1429 EVT VT = Op.getValueType();
1430 unsigned ShAmt = SA->getZExtValue();
1431 unsigned VTSize = VT.getSizeInBits();
1432 SDValue InOp = Op.getOperand(0);
1434 // If the shift count is an invalid immediate, don't do anything.
1435 if (ShAmt >= BitWidth)
1438 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1439 // single shift. We can do this if the top bits (which are shifted out)
1440 // are never demanded.
1441 if (InOp.getOpcode() == ISD::SHL &&
1442 isa<ConstantSDNode>(InOp.getOperand(1))) {
1443 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1444 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1445 unsigned Opc = ISD::SRL;
1446 int Diff = ShAmt-C1;
1453 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1454 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1455 InOp.getOperand(0), NewSA));
1459 // Compute the new bits that are at the top now.
1460 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1461 KnownZero, KnownOne, TLO, Depth+1))
1463 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1464 KnownZero = KnownZero.lshr(ShAmt);
1465 KnownOne = KnownOne.lshr(ShAmt);
1467 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1468 KnownZero |= HighBits; // High bits known zero.
1472 // If this is an arithmetic shift right and only the low-bit is set, we can
1473 // always convert this into a logical shr, even if the shift amount is
1474 // variable. The low bit of the shift cannot be an input sign bit unless
1475 // the shift amount is >= the size of the datatype, which is undefined.
1476 if (DemandedMask == 1)
1477 return TLO.CombineTo(Op,
1478 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1479 Op.getOperand(0), Op.getOperand(1)));
1481 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1482 EVT VT = Op.getValueType();
1483 unsigned ShAmt = SA->getZExtValue();
1485 // If the shift count is an invalid immediate, don't do anything.
1486 if (ShAmt >= BitWidth)
1489 APInt InDemandedMask = (NewMask << ShAmt);
1491 // If any of the demanded bits are produced by the sign extension, we also
1492 // demand the input sign bit.
1493 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1494 if (HighBits.intersects(NewMask))
1495 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1497 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1498 KnownZero, KnownOne, TLO, Depth+1))
1500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1501 KnownZero = KnownZero.lshr(ShAmt);
1502 KnownOne = KnownOne.lshr(ShAmt);
1504 // Handle the sign bit, adjusted to where it is now in the mask.
1505 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1507 // If the input sign bit is known to be zero, or if none of the top bits
1508 // are demanded, turn this into an unsigned shift right.
1509 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1510 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1513 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1514 KnownOne |= HighBits;
1518 case ISD::SIGN_EXTEND_INREG: {
1519 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1521 // Sign extension. Compute the demanded bits in the result that are not
1522 // present in the input.
1524 APInt::getHighBitsSet(BitWidth,
1525 BitWidth - EVT.getScalarType().getSizeInBits());
1527 // If none of the extended bits are demanded, eliminate the sextinreg.
1528 if ((NewBits & NewMask) == 0)
1529 return TLO.CombineTo(Op, Op.getOperand(0));
1532 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth);
1533 APInt InputDemandedBits =
1534 APInt::getLowBitsSet(BitWidth,
1535 EVT.getScalarType().getSizeInBits()) &
1538 // Since the sign extended bits are demanded, we know that the sign
1540 InputDemandedBits |= InSignBit;
1542 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1543 KnownZero, KnownOne, TLO, Depth+1))
1545 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1547 // If the sign bit of the input is known set or clear, then we know the
1548 // top bits of the result.
1550 // If the input sign bit is known zero, convert this into a zero extension.
1551 if (KnownZero.intersects(InSignBit))
1552 return TLO.CombineTo(Op,
1553 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1555 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1556 KnownOne |= NewBits;
1557 KnownZero &= ~NewBits;
1558 } else { // Input sign bit unknown
1559 KnownZero &= ~NewBits;
1560 KnownOne &= ~NewBits;
1564 case ISD::ZERO_EXTEND: {
1565 unsigned OperandBitWidth =
1566 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1567 APInt InMask = NewMask.trunc(OperandBitWidth);
1569 // If none of the top bits are demanded, convert this into an any_extend.
1571 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1572 if (!NewBits.intersects(NewMask))
1573 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1577 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1578 KnownZero, KnownOne, TLO, Depth+1))
1580 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1581 KnownZero = KnownZero.zext(BitWidth);
1582 KnownOne = KnownOne.zext(BitWidth);
1583 KnownZero |= NewBits;
1586 case ISD::SIGN_EXTEND: {
1587 EVT InVT = Op.getOperand(0).getValueType();
1588 unsigned InBits = InVT.getScalarType().getSizeInBits();
1589 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1590 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1591 APInt NewBits = ~InMask & NewMask;
1593 // If none of the top bits are demanded, convert this into an any_extend.
1595 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1599 // Since some of the sign extended bits are demanded, we know that the sign
1601 APInt InDemandedBits = InMask & NewMask;
1602 InDemandedBits |= InSignBit;
1603 InDemandedBits = InDemandedBits.trunc(InBits);
1605 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1606 KnownOne, TLO, Depth+1))
1608 KnownZero = KnownZero.zext(BitWidth);
1609 KnownOne = KnownOne.zext(BitWidth);
1611 // If the sign bit is known zero, convert this to a zero extend.
1612 if (KnownZero.intersects(InSignBit))
1613 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1617 // If the sign bit is known one, the top bits match.
1618 if (KnownOne.intersects(InSignBit)) {
1619 KnownOne |= NewBits;
1620 KnownZero &= ~NewBits;
1621 } else { // Otherwise, top bits aren't known.
1622 KnownOne &= ~NewBits;
1623 KnownZero &= ~NewBits;
1627 case ISD::ANY_EXTEND: {
1628 unsigned OperandBitWidth =
1629 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1630 APInt InMask = NewMask.trunc(OperandBitWidth);
1631 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1632 KnownZero, KnownOne, TLO, Depth+1))
1634 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1635 KnownZero = KnownZero.zext(BitWidth);
1636 KnownOne = KnownOne.zext(BitWidth);
1639 case ISD::TRUNCATE: {
1640 // Simplify the input, using demanded bit information, and compute the known
1641 // zero/one bits live out.
1642 unsigned OperandBitWidth =
1643 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1644 APInt TruncMask = NewMask.zext(OperandBitWidth);
1645 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1646 KnownZero, KnownOne, TLO, Depth+1))
1648 KnownZero = KnownZero.trunc(BitWidth);
1649 KnownOne = KnownOne.trunc(BitWidth);
1651 // If the input is only used by this truncate, see if we can shrink it based
1652 // on the known demanded bits.
1653 if (Op.getOperand(0).getNode()->hasOneUse()) {
1654 SDValue In = Op.getOperand(0);
1655 switch (In.getOpcode()) {
1658 // Shrink SRL by a constant if none of the high bits shifted in are
1660 if (TLO.LegalTypes() &&
1661 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1662 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1665 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1668 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1669 OperandBitWidth - BitWidth);
1670 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1672 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1673 // None of the shifted in bits are needed. Add a truncate of the
1674 // shift input, then shift it.
1675 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1678 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1687 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1690 case ISD::AssertZext: {
1691 // Demand all the bits of the input that are demanded in the output.
1692 // The low bits are obvious; the high bits are demanded because we're
1693 // asserting that they're zero here.
1694 if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
1695 KnownZero, KnownOne, TLO, Depth+1))
1697 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1699 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1700 APInt InMask = APInt::getLowBitsSet(BitWidth,
1701 VT.getSizeInBits());
1702 KnownZero |= ~InMask & NewMask;
1707 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1708 // is demanded, turn this into a FGETSIGN.
1709 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1710 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1711 !MVT::isVector(Op.getOperand(0).getValueType())) {
1712 // Only do this xform if FGETSIGN is valid or if before legalize.
1713 if (!TLO.AfterLegalize ||
1714 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1715 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1716 // place. We expect the SHL to be eliminated by other optimizations.
1717 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1719 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1720 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1721 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1730 // Add, Sub, and Mul don't demand any bits in positions beyond that
1731 // of the highest bit demanded of them.
1732 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1733 BitWidth - NewMask.countLeadingZeros());
1734 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1735 KnownOne2, TLO, Depth+1))
1737 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1738 KnownOne2, TLO, Depth+1))
1740 // See if the operation should be performed at a smaller bit width.
1741 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1746 // Just use ComputeMaskedBits to compute output bits.
1747 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1751 // If we know the value of all of the demanded bits, return this as a
1753 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1754 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1759 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1760 /// in Mask are known to be either zero or one and return them in the
1761 /// KnownZero/KnownOne bitsets.
1762 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1766 const SelectionDAG &DAG,
1767 unsigned Depth) const {
1768 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1769 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1770 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1771 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1772 "Should use MaskedValueIsZero if you don't know whether Op"
1773 " is a target node!");
1774 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1777 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1778 /// targets that want to expose additional information about sign bits to the
1780 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1781 unsigned Depth) const {
1782 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1783 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1784 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1785 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1786 "Should use ComputeNumSignBits if you don't know whether Op"
1787 " is a target node!");
1791 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1792 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1793 /// determine which bit is set.
1795 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1796 // A left-shift of a constant one will have exactly one bit set, because
1797 // shifting the bit off the end is undefined.
1798 if (Val.getOpcode() == ISD::SHL)
1799 if (ConstantSDNode *C =
1800 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1801 if (C->getAPIntValue() == 1)
1804 // Similarly, a right-shift of a constant sign-bit will have exactly
1806 if (Val.getOpcode() == ISD::SRL)
1807 if (ConstantSDNode *C =
1808 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1809 if (C->getAPIntValue().isSignBit())
1812 // More could be done here, though the above checks are enough
1813 // to handle some common cases.
1815 // Fall back to ComputeMaskedBits to catch other known cases.
1816 EVT OpVT = Val.getValueType();
1817 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1818 APInt Mask = APInt::getAllOnesValue(BitWidth);
1819 APInt KnownZero, KnownOne;
1820 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1821 return (KnownZero.countPopulation() == BitWidth - 1) &&
1822 (KnownOne.countPopulation() == 1);
1825 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1826 /// and cc. If it is unable to simplify it, return a null SDValue.
1828 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1829 ISD::CondCode Cond, bool foldBooleans,
1830 DAGCombinerInfo &DCI, DebugLoc dl) const {
1831 SelectionDAG &DAG = DCI.DAG;
1832 LLVMContext &Context = *DAG.getContext();
1834 // These setcc operations always fold.
1838 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1840 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1843 if (isa<ConstantSDNode>(N0.getNode())) {
1844 // Ensure that the constant occurs on the RHS, and fold constant
1846 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1849 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1850 const APInt &C1 = N1C->getAPIntValue();
1852 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1853 // equality comparison, then we're just comparing whether X itself is
1855 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1856 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1857 N0.getOperand(1).getOpcode() == ISD::Constant) {
1859 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1860 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1861 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1862 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1863 // (srl (ctlz x), 5) == 0 -> X != 0
1864 // (srl (ctlz x), 5) != 1 -> X != 0
1867 // (srl (ctlz x), 5) != 0 -> X == 0
1868 // (srl (ctlz x), 5) == 1 -> X == 0
1871 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1872 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1878 // Look through truncs that don't change the value of a ctpop.
1879 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1880 CTPOP = N0.getOperand(0);
1882 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1883 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1884 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1885 EVT CTVT = CTPOP.getValueType();
1886 SDValue CTOp = CTPOP.getOperand(0);
1888 // (ctpop x) u< 2 -> (x & x-1) == 0
1889 // (ctpop x) u> 1 -> (x & x-1) != 0
1890 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1891 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1892 DAG.getConstant(1, CTVT));
1893 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1894 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1895 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1898 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1901 // If the LHS is '(and load, const)', the RHS is 0,
1902 // the test is for equality or unsigned, and all 1 bits of the const are
1903 // in the same partial word, see if we can shorten the load.
1904 if (DCI.isBeforeLegalize() &&
1905 N0.getOpcode() == ISD::AND && C1 == 0 &&
1906 N0.getNode()->hasOneUse() &&
1907 isa<LoadSDNode>(N0.getOperand(0)) &&
1908 N0.getOperand(0).getNode()->hasOneUse() &&
1909 isa<ConstantSDNode>(N0.getOperand(1))) {
1910 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1912 unsigned bestWidth = 0, bestOffset = 0;
1913 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1914 unsigned origWidth = N0.getValueType().getSizeInBits();
1915 unsigned maskWidth = origWidth;
1916 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1917 // 8 bits, but have to be careful...
1918 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1919 origWidth = Lod->getMemoryVT().getSizeInBits();
1921 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1922 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1923 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1924 for (unsigned offset=0; offset<origWidth/width; offset++) {
1925 if ((newMask & Mask) == Mask) {
1926 if (!TD->isLittleEndian())
1927 bestOffset = (origWidth/width - offset - 1) * (width/8);
1929 bestOffset = (uint64_t)offset * (width/8);
1930 bestMask = Mask.lshr(offset * (width/8) * 8);
1934 newMask = newMask << width;
1939 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1940 if (newVT.isRound()) {
1941 EVT PtrType = Lod->getOperand(1).getValueType();
1942 SDValue Ptr = Lod->getBasePtr();
1943 if (bestOffset != 0)
1944 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1945 DAG.getConstant(bestOffset, PtrType));
1946 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1947 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1948 Lod->getPointerInfo().getWithOffset(bestOffset),
1949 false, false, NewAlign);
1950 return DAG.getSetCC(dl, VT,
1951 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1952 DAG.getConstant(bestMask.trunc(bestWidth),
1954 DAG.getConstant(0LL, newVT), Cond);
1959 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1960 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1961 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1963 // If the comparison constant has bits in the upper part, the
1964 // zero-extended value could never match.
1965 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1966 C1.getBitWidth() - InSize))) {
1970 case ISD::SETEQ: return DAG.getConstant(0, VT);
1973 case ISD::SETNE: return DAG.getConstant(1, VT);
1976 // True if the sign bit of C1 is set.
1977 return DAG.getConstant(C1.isNegative(), VT);
1980 // True if the sign bit of C1 isn't set.
1981 return DAG.getConstant(C1.isNonNegative(), VT);
1987 // Otherwise, we can perform the comparison with the low bits.
1995 EVT newVT = N0.getOperand(0).getValueType();
1996 if (DCI.isBeforeLegalizeOps() ||
1997 (isOperationLegal(ISD::SETCC, newVT) &&
1998 getCondCodeAction(Cond, newVT)==Legal))
1999 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2000 DAG.getConstant(C1.trunc(InSize), newVT),
2005 break; // todo, be more careful with signed comparisons
2007 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2008 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2009 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2010 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2011 EVT ExtDstTy = N0.getValueType();
2012 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2014 // If the constant doesn't fit into the number of bits for the source of
2015 // the sign extension, it is impossible for both sides to be equal.
2016 if (C1.getMinSignedBits() > ExtSrcTyBits)
2017 return DAG.getConstant(Cond == ISD::SETNE, VT);
2020 EVT Op0Ty = N0.getOperand(0).getValueType();
2021 if (Op0Ty == ExtSrcTy) {
2022 ZextOp = N0.getOperand(0);
2024 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2025 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2026 DAG.getConstant(Imm, Op0Ty));
2028 if (!DCI.isCalledByLegalizer())
2029 DCI.AddToWorklist(ZextOp.getNode());
2030 // Otherwise, make this a use of a zext.
2031 return DAG.getSetCC(dl, VT, ZextOp,
2032 DAG.getConstant(C1 & APInt::getLowBitsSet(
2037 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2038 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2039 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2040 if (N0.getOpcode() == ISD::SETCC &&
2041 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2042 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2044 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2045 // Invert the condition.
2046 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2047 CC = ISD::getSetCCInverse(CC,
2048 N0.getOperand(0).getValueType().isInteger());
2049 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2052 if ((N0.getOpcode() == ISD::XOR ||
2053 (N0.getOpcode() == ISD::AND &&
2054 N0.getOperand(0).getOpcode() == ISD::XOR &&
2055 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2056 isa<ConstantSDNode>(N0.getOperand(1)) &&
2057 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2058 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2059 // can only do this if the top bits are known zero.
2060 unsigned BitWidth = N0.getValueSizeInBits();
2061 if (DAG.MaskedValueIsZero(N0,
2062 APInt::getHighBitsSet(BitWidth,
2064 // Okay, get the un-inverted input value.
2066 if (N0.getOpcode() == ISD::XOR)
2067 Val = N0.getOperand(0);
2069 assert(N0.getOpcode() == ISD::AND &&
2070 N0.getOperand(0).getOpcode() == ISD::XOR);
2071 // ((X^1)&1)^1 -> X & 1
2072 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2073 N0.getOperand(0).getOperand(0),
2077 return DAG.getSetCC(dl, VT, Val, N1,
2078 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2080 } else if (N1C->getAPIntValue() == 1 &&
2082 getBooleanContents() == ZeroOrOneBooleanContent)) {
2084 if (Op0.getOpcode() == ISD::TRUNCATE)
2085 Op0 = Op0.getOperand(0);
2087 if ((Op0.getOpcode() == ISD::XOR) &&
2088 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2089 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2090 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2091 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2092 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2094 } else if (Op0.getOpcode() == ISD::AND &&
2095 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2096 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2097 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2098 if (Op0.getValueType().bitsGT(VT))
2099 Op0 = DAG.getNode(ISD::AND, dl, VT,
2100 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2101 DAG.getConstant(1, VT));
2102 else if (Op0.getValueType().bitsLT(VT))
2103 Op0 = DAG.getNode(ISD::AND, dl, VT,
2104 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2105 DAG.getConstant(1, VT));
2107 return DAG.getSetCC(dl, VT, Op0,
2108 DAG.getConstant(0, Op0.getValueType()),
2109 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2114 APInt MinVal, MaxVal;
2115 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2116 if (ISD::isSignedIntSetCC(Cond)) {
2117 MinVal = APInt::getSignedMinValue(OperandBitSize);
2118 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2120 MinVal = APInt::getMinValue(OperandBitSize);
2121 MaxVal = APInt::getMaxValue(OperandBitSize);
2124 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2125 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2126 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2127 // X >= C0 --> X > (C0-1)
2128 return DAG.getSetCC(dl, VT, N0,
2129 DAG.getConstant(C1-1, N1.getValueType()),
2130 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2133 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2134 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2135 // X <= C0 --> X < (C0+1)
2136 return DAG.getSetCC(dl, VT, N0,
2137 DAG.getConstant(C1+1, N1.getValueType()),
2138 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2141 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2142 return DAG.getConstant(0, VT); // X < MIN --> false
2143 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2144 return DAG.getConstant(1, VT); // X >= MIN --> true
2145 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2146 return DAG.getConstant(0, VT); // X > MAX --> false
2147 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2148 return DAG.getConstant(1, VT); // X <= MAX --> true
2150 // Canonicalize setgt X, Min --> setne X, Min
2151 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2152 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2153 // Canonicalize setlt X, Max --> setne X, Max
2154 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2155 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2157 // If we have setult X, 1, turn it into seteq X, 0
2158 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2159 return DAG.getSetCC(dl, VT, N0,
2160 DAG.getConstant(MinVal, N0.getValueType()),
2162 // If we have setugt X, Max-1, turn it into seteq X, Max
2163 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2164 return DAG.getSetCC(dl, VT, N0,
2165 DAG.getConstant(MaxVal, N0.getValueType()),
2168 // If we have "setcc X, C0", check to see if we can shrink the immediate
2171 // SETUGT X, SINTMAX -> SETLT X, 0
2172 if (Cond == ISD::SETUGT &&
2173 C1 == APInt::getSignedMaxValue(OperandBitSize))
2174 return DAG.getSetCC(dl, VT, N0,
2175 DAG.getConstant(0, N1.getValueType()),
2178 // SETULT X, SINTMIN -> SETGT X, -1
2179 if (Cond == ISD::SETULT &&
2180 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2181 SDValue ConstMinusOne =
2182 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2184 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2187 // Fold bit comparisons when we can.
2188 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2189 (VT == N0.getValueType() ||
2190 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2191 N0.getOpcode() == ISD::AND)
2192 if (ConstantSDNode *AndRHS =
2193 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2194 EVT ShiftTy = DCI.isBeforeLegalize() ?
2195 getPointerTy() : getShiftAmountTy(N0.getValueType());
2196 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2197 // Perform the xform if the AND RHS is a single bit.
2198 if (AndRHS->getAPIntValue().isPowerOf2()) {
2199 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2200 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2201 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2203 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2204 // (X & 8) == 8 --> (X & 8) >> 3
2205 // Perform the xform if C1 is a single bit.
2206 if (C1.isPowerOf2()) {
2207 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2208 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2209 DAG.getConstant(C1.logBase2(), ShiftTy)));
2215 if (isa<ConstantFPSDNode>(N0.getNode())) {
2216 // Constant fold or commute setcc.
2217 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2218 if (O.getNode()) return O;
2219 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2220 // If the RHS of an FP comparison is a constant, simplify it away in
2222 if (CFP->getValueAPF().isNaN()) {
2223 // If an operand is known to be a nan, we can fold it.
2224 switch (ISD::getUnorderedFlavor(Cond)) {
2225 default: llvm_unreachable("Unknown flavor!");
2226 case 0: // Known false.
2227 return DAG.getConstant(0, VT);
2228 case 1: // Known true.
2229 return DAG.getConstant(1, VT);
2230 case 2: // Undefined.
2231 return DAG.getUNDEF(VT);
2235 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2236 // constant if knowing that the operand is non-nan is enough. We prefer to
2237 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2239 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2240 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2242 // If the condition is not legal, see if we can find an equivalent one
2244 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2245 // If the comparison was an awkward floating-point == or != and one of
2246 // the comparison operands is infinity or negative infinity, convert the
2247 // condition to a less-awkward <= or >=.
2248 if (CFP->getValueAPF().isInfinity()) {
2249 if (CFP->getValueAPF().isNegative()) {
2250 if (Cond == ISD::SETOEQ &&
2251 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2252 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2253 if (Cond == ISD::SETUEQ &&
2254 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2255 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2256 if (Cond == ISD::SETUNE &&
2257 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2258 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2259 if (Cond == ISD::SETONE &&
2260 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2261 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2263 if (Cond == ISD::SETOEQ &&
2264 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2265 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2266 if (Cond == ISD::SETUEQ &&
2267 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2268 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2269 if (Cond == ISD::SETUNE &&
2270 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2271 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2272 if (Cond == ISD::SETONE &&
2273 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2274 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2281 // We can always fold X == X for integer setcc's.
2282 if (N0.getValueType().isInteger())
2283 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2284 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2285 if (UOF == 2) // FP operators that are undefined on NaNs.
2286 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2287 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2288 return DAG.getConstant(UOF, VT);
2289 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2290 // if it is not already.
2291 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2292 if (NewCond != Cond)
2293 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2296 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2297 N0.getValueType().isInteger()) {
2298 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2299 N0.getOpcode() == ISD::XOR) {
2300 // Simplify (X+Y) == (X+Z) --> Y == Z
2301 if (N0.getOpcode() == N1.getOpcode()) {
2302 if (N0.getOperand(0) == N1.getOperand(0))
2303 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2304 if (N0.getOperand(1) == N1.getOperand(1))
2305 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2306 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2307 // If X op Y == Y op X, try other combinations.
2308 if (N0.getOperand(0) == N1.getOperand(1))
2309 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2311 if (N0.getOperand(1) == N1.getOperand(0))
2312 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2317 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2318 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2319 // Turn (X+C1) == C2 --> X == C2-C1
2320 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2321 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2322 DAG.getConstant(RHSC->getAPIntValue()-
2323 LHSR->getAPIntValue(),
2324 N0.getValueType()), Cond);
2327 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2328 if (N0.getOpcode() == ISD::XOR)
2329 // If we know that all of the inverted bits are zero, don't bother
2330 // performing the inversion.
2331 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2333 DAG.getSetCC(dl, VT, N0.getOperand(0),
2334 DAG.getConstant(LHSR->getAPIntValue() ^
2335 RHSC->getAPIntValue(),
2340 // Turn (C1-X) == C2 --> X == C1-C2
2341 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2342 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2344 DAG.getSetCC(dl, VT, N0.getOperand(1),
2345 DAG.getConstant(SUBC->getAPIntValue() -
2346 RHSC->getAPIntValue(),
2353 // Simplify (X+Z) == X --> Z == 0
2354 if (N0.getOperand(0) == N1)
2355 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2356 DAG.getConstant(0, N0.getValueType()), Cond);
2357 if (N0.getOperand(1) == N1) {
2358 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2359 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2360 DAG.getConstant(0, N0.getValueType()), Cond);
2361 else if (N0.getNode()->hasOneUse()) {
2362 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2363 // (Z-X) == X --> Z == X<<1
2364 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2366 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2367 if (!DCI.isCalledByLegalizer())
2368 DCI.AddToWorklist(SH.getNode());
2369 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2374 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2375 N1.getOpcode() == ISD::XOR) {
2376 // Simplify X == (X+Z) --> Z == 0
2377 if (N1.getOperand(0) == N0) {
2378 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2379 DAG.getConstant(0, N1.getValueType()), Cond);
2380 } else if (N1.getOperand(1) == N0) {
2381 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2382 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2383 DAG.getConstant(0, N1.getValueType()), Cond);
2384 } else if (N1.getNode()->hasOneUse()) {
2385 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2386 // X == (Z-X) --> X<<1 == Z
2387 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2388 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2389 if (!DCI.isCalledByLegalizer())
2390 DCI.AddToWorklist(SH.getNode());
2391 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2396 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2397 // Note that where y is variable and is known to have at most
2398 // one bit set (for example, if it is z&1) we cannot do this;
2399 // the expressions are not equivalent when y==0.
2400 if (N0.getOpcode() == ISD::AND)
2401 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2402 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2403 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2404 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2405 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2408 if (N1.getOpcode() == ISD::AND)
2409 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2410 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2411 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2412 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2413 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2418 // Fold away ALL boolean setcc's.
2420 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2422 default: llvm_unreachable("Unknown integer setcc!");
2423 case ISD::SETEQ: // X == Y -> ~(X^Y)
2424 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2425 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2426 if (!DCI.isCalledByLegalizer())
2427 DCI.AddToWorklist(Temp.getNode());
2429 case ISD::SETNE: // X != Y --> (X^Y)
2430 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2432 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2433 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2434 Temp = DAG.getNOT(dl, N0, MVT::i1);
2435 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2436 if (!DCI.isCalledByLegalizer())
2437 DCI.AddToWorklist(Temp.getNode());
2439 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2440 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2441 Temp = DAG.getNOT(dl, N1, MVT::i1);
2442 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2443 if (!DCI.isCalledByLegalizer())
2444 DCI.AddToWorklist(Temp.getNode());
2446 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2447 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2448 Temp = DAG.getNOT(dl, N0, MVT::i1);
2449 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2450 if (!DCI.isCalledByLegalizer())
2451 DCI.AddToWorklist(Temp.getNode());
2453 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2454 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2455 Temp = DAG.getNOT(dl, N1, MVT::i1);
2456 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2459 if (VT != MVT::i1) {
2460 if (!DCI.isCalledByLegalizer())
2461 DCI.AddToWorklist(N0.getNode());
2462 // FIXME: If running after legalize, we probably can't do this.
2463 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2468 // Could not fold it.
2472 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2473 /// node is a GlobalAddress + offset.
2474 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2475 int64_t &Offset) const {
2476 if (isa<GlobalAddressSDNode>(N)) {
2477 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2478 GA = GASD->getGlobal();
2479 Offset += GASD->getOffset();
2483 if (N->getOpcode() == ISD::ADD) {
2484 SDValue N1 = N->getOperand(0);
2485 SDValue N2 = N->getOperand(1);
2486 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2487 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2489 Offset += V->getSExtValue();
2492 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2493 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2495 Offset += V->getSExtValue();
2505 SDValue TargetLowering::
2506 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2507 // Default implementation: no optimization.
2511 //===----------------------------------------------------------------------===//
2512 // Inline Assembler Implementation Methods
2513 //===----------------------------------------------------------------------===//
2516 TargetLowering::ConstraintType
2517 TargetLowering::getConstraintType(const std::string &Constraint) const {
2518 // FIXME: lots more standard ones to handle.
2519 if (Constraint.size() == 1) {
2520 switch (Constraint[0]) {
2522 case 'r': return C_RegisterClass;
2524 case 'o': // offsetable
2525 case 'V': // not offsetable
2527 case 'i': // Simple Integer or Relocatable Constant
2528 case 'n': // Simple Integer
2529 case 'E': // Floating Point Constant
2530 case 'F': // Floating Point Constant
2531 case 's': // Relocatable Constant
2532 case 'p': // Address.
2533 case 'X': // Allow ANY value.
2534 case 'I': // Target registers.
2548 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2549 Constraint[Constraint.size()-1] == '}')
2554 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2555 /// with another that has more specific requirements based on the type of the
2556 /// corresponding operand.
2557 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2558 if (ConstraintVT.isInteger())
2560 if (ConstraintVT.isFloatingPoint())
2561 return "f"; // works for many targets
2565 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2566 /// vector. If it is invalid, don't add anything to Ops.
2567 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2568 char ConstraintLetter,
2569 std::vector<SDValue> &Ops,
2570 SelectionDAG &DAG) const {
2571 switch (ConstraintLetter) {
2573 case 'X': // Allows any operand; labels (basic block) use this.
2574 if (Op.getOpcode() == ISD::BasicBlock) {
2579 case 'i': // Simple Integer or Relocatable Constant
2580 case 'n': // Simple Integer
2581 case 's': { // Relocatable Constant
2582 // These operands are interested in values of the form (GV+C), where C may
2583 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2584 // is possible and fine if either GV or C are missing.
2585 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2586 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2588 // If we have "(add GV, C)", pull out GV/C
2589 if (Op.getOpcode() == ISD::ADD) {
2590 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2591 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2592 if (C == 0 || GA == 0) {
2593 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2594 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2596 if (C == 0 || GA == 0)
2600 // If we find a valid operand, map to the TargetXXX version so that the
2601 // value itself doesn't get selected.
2602 if (GA) { // Either &GV or &GV+C
2603 if (ConstraintLetter != 'n') {
2604 int64_t Offs = GA->getOffset();
2605 if (C) Offs += C->getZExtValue();
2606 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2607 C ? C->getDebugLoc() : DebugLoc(),
2608 Op.getValueType(), Offs));
2612 if (C) { // just C, no GV.
2613 // Simple constants are not allowed for 's'.
2614 if (ConstraintLetter != 's') {
2615 // gcc prints these as sign extended. Sign extend value to 64 bits
2616 // now; without this it would get ZExt'd later in
2617 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2618 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2628 std::vector<unsigned> TargetLowering::
2629 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2631 return std::vector<unsigned>();
2635 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2636 getRegForInlineAsmConstraint(const std::string &Constraint,
2638 if (Constraint[0] != '{')
2639 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2640 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2642 // Remove the braces from around the name.
2643 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2645 // Figure out which register class contains this reg.
2646 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2647 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2648 E = RI->regclass_end(); RCI != E; ++RCI) {
2649 const TargetRegisterClass *RC = *RCI;
2651 // If none of the value types for this register class are valid, we
2652 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2653 bool isLegal = false;
2654 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2656 if (isTypeLegal(*I)) {
2662 if (!isLegal) continue;
2664 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2666 if (RegName.equals_lower(RI->getName(*I)))
2667 return std::make_pair(*I, RC);
2671 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2674 //===----------------------------------------------------------------------===//
2675 // Constraint Selection.
2677 /// isMatchingInputConstraint - Return true of this is an input operand that is
2678 /// a matching constraint like "4".
2679 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2680 assert(!ConstraintCode.empty() && "No known constraint!");
2681 return isdigit(ConstraintCode[0]);
2684 /// getMatchedOperand - If this is an input matching constraint, this method
2685 /// returns the output operand it matches.
2686 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2687 assert(!ConstraintCode.empty() && "No known constraint!");
2688 return atoi(ConstraintCode.c_str());
2692 /// ParseConstraints - Split up the constraint string from the inline
2693 /// assembly value into the specific constraints and their prefixes,
2694 /// and also tie in the associated operand values.
2695 /// If this returns an empty vector, and if the constraint string itself
2696 /// isn't empty, there was an error parsing.
2697 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2698 ImmutableCallSite CS) const {
2699 /// ConstraintOperands - Information about all of the constraints.
2700 AsmOperandInfoVector ConstraintOperands;
2701 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2702 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2704 // Do a prepass over the constraints, canonicalizing them, and building up the
2705 // ConstraintOperands list.
2706 InlineAsm::ConstraintInfoVector
2707 ConstraintInfos = IA->ParseConstraints();
2709 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2710 unsigned ResNo = 0; // ResNo - The result number of the next output.
2712 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2713 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2714 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2716 // Update multiple alternative constraint count.
2717 if (OpInfo.multipleAlternatives.size() > maCount)
2718 maCount = OpInfo.multipleAlternatives.size();
2720 OpInfo.ConstraintVT = MVT::Other;
2722 // Compute the value type for each operand.
2723 switch (OpInfo.Type) {
2724 case InlineAsm::isOutput:
2725 // Indirect outputs just consume an argument.
2726 if (OpInfo.isIndirect) {
2727 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2731 // The return value of the call is this value. As such, there is no
2732 // corresponding argument.
2733 assert(!CS.getType()->isVoidTy() &&
2735 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
2736 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2738 assert(ResNo == 0 && "Asm only has one result!");
2739 OpInfo.ConstraintVT = getValueType(CS.getType());
2743 case InlineAsm::isInput:
2744 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2746 case InlineAsm::isClobber:
2751 if (OpInfo.CallOperandVal) {
2752 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2753 if (OpInfo.isIndirect) {
2754 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2756 report_fatal_error("Indirect operand for inline asm not a pointer!");
2757 OpTy = PtrTy->getElementType();
2759 // If OpTy is not a single value, it may be a struct/union that we
2760 // can tile with integers.
2761 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2762 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2771 OpInfo.ConstraintVT =
2772 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2775 } else if (dyn_cast<PointerType>(OpTy)) {
2776 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2778 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2783 // If we have multiple alternative constraints, select the best alternative.
2784 if (ConstraintInfos.size()) {
2786 unsigned bestMAIndex = 0;
2787 int bestWeight = -1;
2788 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2791 // Compute the sums of the weights for each alternative, keeping track
2792 // of the best (highest weight) one so far.
2793 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2795 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2796 cIndex != eIndex; ++cIndex) {
2797 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2798 if (OpInfo.Type == InlineAsm::isClobber)
2801 // If this is an output operand with a matching input operand,
2802 // look up the matching input. If their types mismatch, e.g. one
2803 // is an integer, the other is floating point, or their sizes are
2804 // different, flag it as an maCantMatch.
2805 if (OpInfo.hasMatchingInput()) {
2806 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2807 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2808 if ((OpInfo.ConstraintVT.isInteger() !=
2809 Input.ConstraintVT.isInteger()) ||
2810 (OpInfo.ConstraintVT.getSizeInBits() !=
2811 Input.ConstraintVT.getSizeInBits())) {
2812 weightSum = -1; // Can't match.
2817 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2822 weightSum += weight;
2825 if (weightSum > bestWeight) {
2826 bestWeight = weightSum;
2827 bestMAIndex = maIndex;
2831 // Now select chosen alternative in each constraint.
2832 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2833 cIndex != eIndex; ++cIndex) {
2834 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2835 if (cInfo.Type == InlineAsm::isClobber)
2837 cInfo.selectAlternative(bestMAIndex);
2842 // Check and hook up tied operands, choose constraint code to use.
2843 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2844 cIndex != eIndex; ++cIndex) {
2845 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2847 // If this is an output operand with a matching input operand, look up the
2848 // matching input. If their types mismatch, e.g. one is an integer, the
2849 // other is floating point, or their sizes are different, flag it as an
2851 if (OpInfo.hasMatchingInput()) {
2852 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2854 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2855 if ((OpInfo.ConstraintVT.isInteger() !=
2856 Input.ConstraintVT.isInteger()) ||
2857 (OpInfo.ConstraintVT.getSizeInBits() !=
2858 Input.ConstraintVT.getSizeInBits())) {
2859 report_fatal_error("Unsupported asm: input constraint"
2860 " with a matching output constraint of"
2861 " incompatible type!");
2868 return ConstraintOperands;
2872 /// getConstraintGenerality - Return an integer indicating how general CT
2874 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2876 default: llvm_unreachable("Unknown constraint type!");
2877 case TargetLowering::C_Other:
2878 case TargetLowering::C_Unknown:
2880 case TargetLowering::C_Register:
2882 case TargetLowering::C_RegisterClass:
2884 case TargetLowering::C_Memory:
2889 /// Examine constraint type and operand type and determine a weight value.
2890 /// This object must already have been set up with the operand type
2891 /// and the current alternative constraint selected.
2892 TargetLowering::ConstraintWeight
2893 TargetLowering::getMultipleConstraintMatchWeight(
2894 AsmOperandInfo &info, int maIndex) const {
2895 InlineAsm::ConstraintCodeVector *rCodes;
2896 if (maIndex >= (int)info.multipleAlternatives.size())
2897 rCodes = &info.Codes;
2899 rCodes = &info.multipleAlternatives[maIndex].Codes;
2900 ConstraintWeight BestWeight = CW_Invalid;
2902 // Loop over the options, keeping track of the most general one.
2903 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2904 ConstraintWeight weight =
2905 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2906 if (weight > BestWeight)
2907 BestWeight = weight;
2913 /// Examine constraint type and operand type and determine a weight value.
2914 /// This object must already have been set up with the operand type
2915 /// and the current alternative constraint selected.
2916 TargetLowering::ConstraintWeight
2917 TargetLowering::getSingleConstraintMatchWeight(
2918 AsmOperandInfo &info, const char *constraint) const {
2919 ConstraintWeight weight = CW_Invalid;
2920 Value *CallOperandVal = info.CallOperandVal;
2921 // If we don't have a value, we can't do a match,
2922 // but allow it at the lowest weight.
2923 if (CallOperandVal == NULL)
2925 // Look at the constraint type.
2926 switch (*constraint) {
2927 case 'i': // immediate integer.
2928 case 'n': // immediate integer with a known value.
2929 if (isa<ConstantInt>(CallOperandVal))
2930 weight = CW_Constant;
2932 case 's': // non-explicit intregal immediate.
2933 if (isa<GlobalValue>(CallOperandVal))
2934 weight = CW_Constant;
2936 case 'E': // immediate float if host format.
2937 case 'F': // immediate float.
2938 if (isa<ConstantFP>(CallOperandVal))
2939 weight = CW_Constant;
2941 case '<': // memory operand with autodecrement.
2942 case '>': // memory operand with autoincrement.
2943 case 'm': // memory operand.
2944 case 'o': // offsettable memory operand
2945 case 'V': // non-offsettable memory operand
2948 case 'r': // general register.
2949 case 'g': // general register, memory operand or immediate integer.
2950 // note: Clang converts "g" to "imr".
2951 if (CallOperandVal->getType()->isIntegerTy())
2952 weight = CW_Register;
2954 case 'X': // any operand.
2956 weight = CW_Default;
2962 /// ChooseConstraint - If there are multiple different constraints that we
2963 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2964 /// This is somewhat tricky: constraints fall into four classes:
2965 /// Other -> immediates and magic values
2966 /// Register -> one specific register
2967 /// RegisterClass -> a group of regs
2968 /// Memory -> memory
2969 /// Ideally, we would pick the most specific constraint possible: if we have
2970 /// something that fits into a register, we would pick it. The problem here
2971 /// is that if we have something that could either be in a register or in
2972 /// memory that use of the register could cause selection of *other*
2973 /// operands to fail: they might only succeed if we pick memory. Because of
2974 /// this the heuristic we use is:
2976 /// 1) If there is an 'other' constraint, and if the operand is valid for
2977 /// that constraint, use it. This makes us take advantage of 'i'
2978 /// constraints when available.
2979 /// 2) Otherwise, pick the most general constraint present. This prefers
2980 /// 'm' over 'r', for example.
2982 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2983 const TargetLowering &TLI,
2984 SDValue Op, SelectionDAG *DAG) {
2985 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2986 unsigned BestIdx = 0;
2987 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2988 int BestGenerality = -1;
2990 // Loop over the options, keeping track of the most general one.
2991 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2992 TargetLowering::ConstraintType CType =
2993 TLI.getConstraintType(OpInfo.Codes[i]);
2995 // If this is an 'other' constraint, see if the operand is valid for it.
2996 // For example, on X86 we might have an 'rI' constraint. If the operand
2997 // is an integer in the range [0..31] we want to use I (saving a load
2998 // of a register), otherwise we must use 'r'.
2999 if (CType == TargetLowering::C_Other && Op.getNode()) {
3000 assert(OpInfo.Codes[i].size() == 1 &&
3001 "Unhandled multi-letter 'other' constraint");
3002 std::vector<SDValue> ResultOps;
3003 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
3005 if (!ResultOps.empty()) {
3012 // Things with matching constraints can only be registers, per gcc
3013 // documentation. This mainly affects "g" constraints.
3014 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3017 // This constraint letter is more general than the previous one, use it.
3018 int Generality = getConstraintGenerality(CType);
3019 if (Generality > BestGenerality) {
3022 BestGenerality = Generality;
3026 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3027 OpInfo.ConstraintType = BestType;
3030 /// ComputeConstraintToUse - Determines the constraint code and constraint
3031 /// type to use for the specific AsmOperandInfo, setting
3032 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3033 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3035 SelectionDAG *DAG) const {
3036 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3038 // Single-letter constraints ('r') are very common.
3039 if (OpInfo.Codes.size() == 1) {
3040 OpInfo.ConstraintCode = OpInfo.Codes[0];
3041 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3043 ChooseConstraint(OpInfo, *this, Op, DAG);
3046 // 'X' matches anything.
3047 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3048 // Labels and constants are handled elsewhere ('X' is the only thing
3049 // that matches labels). For Functions, the type here is the type of
3050 // the result, which is not what we want to look at; leave them alone.
3051 Value *v = OpInfo.CallOperandVal;
3052 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3053 OpInfo.CallOperandVal = v;
3057 // Otherwise, try to resolve it to something we know about by looking at
3058 // the actual operand type.
3059 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3060 OpInfo.ConstraintCode = Repl;
3061 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3066 //===----------------------------------------------------------------------===//
3067 // Loop Strength Reduction hooks
3068 //===----------------------------------------------------------------------===//
3070 /// isLegalAddressingMode - Return true if the addressing mode represented
3071 /// by AM is legal for this target, for a load/store of the specified type.
3072 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3073 const Type *Ty) const {
3074 // The default implementation of this implements a conservative RISCy, r+r and
3077 // Allows a sign-extended 16-bit immediate field.
3078 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3081 // No global is ever allowed as a base.
3085 // Only support r+r,
3087 case 0: // "r+i" or just "i", depending on HasBaseReg.
3090 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3092 // Otherwise we have r+r or r+i.
3095 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3097 // Allow 2*r as r+r.
3104 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3105 /// return a DAG expression to select that will generate the same value by
3106 /// multiplying by a magic number. See:
3107 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3108 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
3109 std::vector<SDNode*>* Created) const {
3110 EVT VT = N->getValueType(0);
3111 DebugLoc dl= N->getDebugLoc();
3113 // Check to see if we can do this.
3114 // FIXME: We should be more aggressive here.
3115 if (!isTypeLegal(VT))
3118 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3119 APInt::ms magics = d.magic();
3121 // Multiply the numerator (operand 0) by the magic value
3122 // FIXME: We should support doing a MUL in a wider type
3124 if (isOperationLegalOrCustom(ISD::MULHS, VT))
3125 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3126 DAG.getConstant(magics.m, VT));
3127 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3128 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3130 DAG.getConstant(magics.m, VT)).getNode(), 1);
3132 return SDValue(); // No mulhs or equvialent
3133 // If d > 0 and m < 0, add the numerator
3134 if (d.isStrictlyPositive() && magics.m.isNegative()) {
3135 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3137 Created->push_back(Q.getNode());
3139 // If d < 0 and m > 0, subtract the numerator.
3140 if (d.isNegative() && magics.m.isStrictlyPositive()) {
3141 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3143 Created->push_back(Q.getNode());
3145 // Shift right algebraic if shift value is nonzero
3147 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3148 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3150 Created->push_back(Q.getNode());
3152 // Extract the sign bit and add it to the quotient
3154 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3155 getShiftAmountTy(Q.getValueType())));
3157 Created->push_back(T.getNode());
3158 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3161 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3162 /// return a DAG expression to select that will generate the same value by
3163 /// multiplying by a magic number. See:
3164 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3165 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
3166 std::vector<SDNode*>* Created) const {
3167 EVT VT = N->getValueType(0);
3168 DebugLoc dl = N->getDebugLoc();
3170 // Check to see if we can do this.
3171 // FIXME: We should be more aggressive here.
3172 if (!isTypeLegal(VT))
3175 // FIXME: We should use a narrower constant when the upper
3176 // bits are known to be zero.
3177 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
3178 APInt::mu magics = N1C->getAPIntValue().magicu();
3180 // Multiply the numerator (operand 0) by the magic value
3181 // FIXME: We should support doing a MUL in a wider type
3183 if (isOperationLegalOrCustom(ISD::MULHU, VT))
3184 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
3185 DAG.getConstant(magics.m, VT));
3186 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3187 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
3189 DAG.getConstant(magics.m, VT)).getNode(), 1);
3191 return SDValue(); // No mulhu or equvialent
3193 Created->push_back(Q.getNode());
3195 if (magics.a == 0) {
3196 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
3197 "We shouldn't generate an undefined shift!");
3198 return DAG.getNode(ISD::SRL, dl, VT, Q,
3199 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3201 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3203 Created->push_back(NPQ.getNode());
3204 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3205 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3207 Created->push_back(NPQ.getNode());
3208 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3210 Created->push_back(NPQ.getNode());
3211 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3212 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));