1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
38 /// NOTE: The TargetMachine owns TLOF.
39 TargetLowering::TargetLowering(const TargetMachine &tm)
40 : TargetLoweringBase(tm) {}
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 SDValue &Chain) const {
50 const Function *F = DAG.getMachineFunction().getFunction();
52 // Conservatively require the attributes of the call to match those of
53 // the return. Ignore noalias because it doesn't affect the call sequence.
54 AttributeSet CallerAttrs = F->getAttributes();
55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56 .removeAttribute(Attribute::NoAlias).hasAttributes())
59 // It's not safe to eliminate the sign / zero extension of the return value.
60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
64 // Check if the only use is a function return node.
65 return isUsedByReturnOnly(Node, Chain);
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
80 Alignment = CS->getParamAlignment(AttrIdx);
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
86 TargetLowering::makeLibCall(SelectionDAG &DAG,
87 RTLIB::Libcall LC, EVT RetVT,
88 ArrayRef<SDValue> Ops,
89 bool isSigned, SDLoc dl,
91 bool isReturnValueUsed) const {
92 TargetLowering::ArgListTy Args;
93 Args.reserve(Ops.size());
95 TargetLowering::ArgListEntry Entry;
96 for (SDValue Op : Ops) {
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99 Entry.isSExt = shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
100 Entry.isZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
101 Args.push_back(Entry);
104 markInRegArguments(DAG, Args);
106 if (LC == RTLIB::UNKNOWN_LIBCALL)
107 report_fatal_error("Unsupported library call operation!");
108 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
109 getPointerTy(DAG.getDataLayout()));
111 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
112 TargetLowering::CallLoweringInfo CLI(DAG);
113 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
114 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
115 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
116 .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
117 .setSExtResult(signExtend).setZExtResult(!signExtend);
118 return LowerCallTo(CLI);
121 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
122 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
123 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
124 SDValue &NewLHS, SDValue &NewRHS,
125 ISD::CondCode &CCCode,
127 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
128 && "Unsupported setcc type!");
130 // Expand into one or more soft-fp libcall(s).
131 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
132 bool ShouldInvertCC = false;
136 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
137 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
141 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
142 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
146 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
147 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
151 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
152 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
156 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
157 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
161 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
162 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
165 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
166 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
169 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
170 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
173 // SETONE = SETOLT | SETOGT
174 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
175 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
176 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
177 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
180 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
181 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
182 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
183 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
186 // Invert CC for unordered comparisons
187 ShouldInvertCC = true;
190 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
191 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
194 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
195 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
198 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
199 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
202 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
203 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
205 default: llvm_unreachable("Do not know how to soften this setcc!");
209 // Use the target specific return value for comparions lib calls.
210 EVT RetVT = getCmpLibcallReturnType();
211 SDValue Ops[2] = {NewLHS, NewRHS};
212 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, false /*sign irrelevant*/,
214 NewRHS = DAG.getConstant(0, dl, RetVT);
216 CCCode = getCmpLibcallCC(LC1);
218 CCCode = getSetCCInverse(CCCode, /*isInteger=*/true);
220 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
221 SDValue Tmp = DAG.getNode(
223 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
224 NewLHS, NewRHS, DAG.getCondCode(CCCode));
225 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, false/*sign irrelevant*/,
227 NewLHS = DAG.getNode(
229 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
230 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
231 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
236 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
237 /// current function. The returned value is a member of the
238 /// MachineJumpTableInfo::JTEntryKind enum.
239 unsigned TargetLowering::getJumpTableEncoding() const {
240 // In non-pic modes, just use the address of a block.
241 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
242 return MachineJumpTableInfo::EK_BlockAddress;
244 // In PIC mode, if the target supports a GPRel32 directive, use it.
245 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
246 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
248 // Otherwise, use a label difference.
249 return MachineJumpTableInfo::EK_LabelDifference32;
252 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
253 SelectionDAG &DAG) const {
254 // If our PIC model is GP relative, use the global offset table as the base.
255 unsigned JTEncoding = getJumpTableEncoding();
257 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
258 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
259 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout()));
264 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
265 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
268 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
269 unsigned JTI,MCContext &Ctx) const{
270 // The normal PIC reloc base is the label at the start of the jump table.
271 return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
275 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
276 // Assume that everything is safe in static mode.
277 if (getTargetMachine().getRelocationModel() == Reloc::Static)
280 // In dynamic-no-pic mode, assume that known defined values are safe.
281 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
282 GA && GA->getGlobal()->isStrongDefinitionForLinker())
285 // Otherwise assume nothing is safe.
289 //===----------------------------------------------------------------------===//
290 // Optimization Methods
291 //===----------------------------------------------------------------------===//
293 /// ShrinkDemandedConstant - Check to see if the specified operand of the
294 /// specified instruction is a constant integer. If so, check to see if there
295 /// are any bits set in the constant that are not demanded. If so, shrink the
296 /// constant and return true.
297 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
298 const APInt &Demanded) {
301 // FIXME: ISD::SELECT, ISD::SELECT_CC
302 switch (Op.getOpcode()) {
307 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
308 if (!C) return false;
310 if (Op.getOpcode() == ISD::XOR &&
311 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
314 // if we can expand it to have all bits set, do it
315 if (C->getAPIntValue().intersects(~Demanded)) {
316 EVT VT = Op.getValueType();
317 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
318 DAG.getConstant(Demanded &
321 return CombineTo(Op, New);
331 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
332 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
333 /// cast, but it could be generalized for targets with other types of
334 /// implicit widening casts.
336 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
338 const APInt &Demanded,
340 assert(Op.getNumOperands() == 2 &&
341 "ShrinkDemandedOp only supports binary operators!");
342 assert(Op.getNode()->getNumValues() == 1 &&
343 "ShrinkDemandedOp only supports nodes with one result!");
345 // Early return, as this function cannot handle vector types.
346 if (Op.getValueType().isVector())
349 // Don't do this if the node has another user, which may require the
351 if (!Op.getNode()->hasOneUse())
354 // Search for the smallest integer type with free casts to and from
355 // Op's type. For expedience, just check power-of-2 integer types.
356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
357 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
358 unsigned SmallVTBits = DemandedSize;
359 if (!isPowerOf2_32(SmallVTBits))
360 SmallVTBits = NextPowerOf2(SmallVTBits);
361 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
362 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
363 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
364 TLI.isZExtFree(SmallVT, Op.getValueType())) {
365 // We found a type with free casts.
366 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
367 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
368 Op.getNode()->getOperand(0)),
369 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
370 Op.getNode()->getOperand(1)));
371 bool NeedZext = DemandedSize > SmallVTBits;
372 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
373 dl, Op.getValueType(), X);
374 return CombineTo(Op, Z);
380 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
381 /// DemandedMask bits of the result of Op are ever used downstream. If we can
382 /// use this information to simplify Op, create a new simplified DAG node and
383 /// return true, returning the original and new nodes in Old and New. Otherwise,
384 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
385 /// the expression (used to simplify the caller). The KnownZero/One bits may
386 /// only be accurate for those bits in the DemandedMask.
387 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
388 const APInt &DemandedMask,
391 TargetLoweringOpt &TLO,
392 unsigned Depth) const {
393 unsigned BitWidth = DemandedMask.getBitWidth();
394 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
395 "Mask size mismatches value type size!");
396 APInt NewMask = DemandedMask;
398 auto &DL = TLO.DAG.getDataLayout();
400 // Don't know anything.
401 KnownZero = KnownOne = APInt(BitWidth, 0);
403 // Other users may use these bits.
404 if (!Op.getNode()->hasOneUse()) {
406 // If not at the root, Just compute the KnownZero/KnownOne bits to
407 // simplify things downstream.
408 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
411 // If this is the root being simplified, allow it to have multiple uses,
412 // just set the NewMask to all bits.
413 NewMask = APInt::getAllOnesValue(BitWidth);
414 } else if (DemandedMask == 0) {
415 // Not demanding any bits from Op.
416 if (Op.getOpcode() != ISD::UNDEF)
417 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
419 } else if (Depth == 6) { // Limit search depth.
423 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
424 switch (Op.getOpcode()) {
426 // We know all of the bits for a constant!
427 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
428 KnownZero = ~KnownOne;
429 return false; // Don't fall through, will infinitely loop.
431 // If the RHS is a constant, check to see if the LHS would be zero without
432 // using the bits from the RHS. Below, we use knowledge about the RHS to
433 // simplify the LHS, here we're using information from the LHS to simplify
435 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
436 APInt LHSZero, LHSOne;
437 // Do not increment Depth here; that can cause an infinite loop.
438 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
439 // If the LHS already has zeros where RHSC does, this and is dead.
440 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
441 return TLO.CombineTo(Op, Op.getOperand(0));
442 // If any of the set bits in the RHS are known zero on the LHS, shrink
444 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
448 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
449 KnownOne, TLO, Depth+1))
451 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
452 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
453 KnownZero2, KnownOne2, TLO, Depth+1))
455 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
457 // If all of the demanded bits are known one on one side, return the other.
458 // These bits cannot contribute to the result of the 'and'.
459 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
460 return TLO.CombineTo(Op, Op.getOperand(0));
461 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
462 return TLO.CombineTo(Op, Op.getOperand(1));
463 // If all of the demanded bits in the inputs are known zeros, return zero.
464 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
465 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType()));
466 // If the RHS is a constant, see if we can simplify it.
467 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
469 // If the operation can be done in a smaller type, do so.
470 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
473 // Output known-1 bits are only known if set in both the LHS & RHS.
474 KnownOne &= KnownOne2;
475 // Output known-0 are known to be clear if zero in either the LHS | RHS.
476 KnownZero |= KnownZero2;
479 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
480 KnownOne, TLO, Depth+1))
482 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
483 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
484 KnownZero2, KnownOne2, TLO, Depth+1))
486 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
488 // If all of the demanded bits are known zero on one side, return the other.
489 // These bits cannot contribute to the result of the 'or'.
490 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
491 return TLO.CombineTo(Op, Op.getOperand(0));
492 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
493 return TLO.CombineTo(Op, Op.getOperand(1));
494 // If all of the potentially set bits on one side are known to be set on
495 // the other side, just use the 'other' side.
496 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
497 return TLO.CombineTo(Op, Op.getOperand(0));
498 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
499 return TLO.CombineTo(Op, Op.getOperand(1));
500 // If the RHS is a constant, see if we can simplify it.
501 if (TLO.ShrinkDemandedConstant(Op, NewMask))
503 // If the operation can be done in a smaller type, do so.
504 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
507 // Output known-0 bits are only known if clear in both the LHS & RHS.
508 KnownZero &= KnownZero2;
509 // Output known-1 are known to be set if set in either the LHS | RHS.
510 KnownOne |= KnownOne2;
513 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
514 KnownOne, TLO, Depth+1))
516 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
517 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
518 KnownOne2, TLO, Depth+1))
520 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
522 // If all of the demanded bits are known zero on one side, return the other.
523 // These bits cannot contribute to the result of the 'xor'.
524 if ((KnownZero & NewMask) == NewMask)
525 return TLO.CombineTo(Op, Op.getOperand(0));
526 if ((KnownZero2 & NewMask) == NewMask)
527 return TLO.CombineTo(Op, Op.getOperand(1));
528 // If the operation can be done in a smaller type, do so.
529 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
532 // If all of the unknown bits are known to be zero on one side or the other
533 // (but not both) turn this into an *inclusive* or.
534 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
535 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
536 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
540 // Output known-0 bits are known if clear or set in both the LHS & RHS.
541 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
542 // Output known-1 are known to be set if set in only one of the LHS, RHS.
543 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
545 // If all of the demanded bits on one side are known, and all of the set
546 // bits on that side are also known to be set on the other side, turn this
547 // into an AND, as we know the bits will be cleared.
548 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
549 // NB: it is okay if more bits are known than are requested
550 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
551 if (KnownOne == KnownOne2) { // set bits are the same on both sides
552 EVT VT = Op.getValueType();
553 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
554 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
555 Op.getOperand(0), ANDC));
559 // If the RHS is a constant, see if we can simplify it.
560 // for XOR, we prefer to force bits to 1 if they will make a -1.
561 // if we can't force bits, try to shrink constant
562 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
563 APInt Expanded = C->getAPIntValue() | (~NewMask);
564 // if we can expand it to have all bits set, do it
565 if (Expanded.isAllOnesValue()) {
566 if (Expanded != C->getAPIntValue()) {
567 EVT VT = Op.getValueType();
568 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
569 TLO.DAG.getConstant(Expanded, dl, VT));
570 return TLO.CombineTo(Op, New);
572 // if it already has all the bits set, nothing to change
573 // but don't shrink either!
574 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
579 KnownZero = KnownZeroOut;
580 KnownOne = KnownOneOut;
583 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
584 KnownOne, TLO, Depth+1))
586 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
587 KnownOne2, TLO, Depth+1))
589 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
590 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
592 // If the operands are constants, see if we can simplify them.
593 if (TLO.ShrinkDemandedConstant(Op, NewMask))
596 // Only known if known in both the LHS and RHS.
597 KnownOne &= KnownOne2;
598 KnownZero &= KnownZero2;
601 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
602 KnownOne, TLO, Depth+1))
604 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
605 KnownOne2, TLO, Depth+1))
607 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
608 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
610 // If the operands are constants, see if we can simplify them.
611 if (TLO.ShrinkDemandedConstant(Op, NewMask))
614 // Only known if known in both the LHS and RHS.
615 KnownOne &= KnownOne2;
616 KnownZero &= KnownZero2;
619 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
620 unsigned ShAmt = SA->getZExtValue();
621 SDValue InOp = Op.getOperand(0);
623 // If the shift count is an invalid immediate, don't do anything.
624 if (ShAmt >= BitWidth)
627 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
628 // single shift. We can do this if the bottom bits (which are shifted
629 // out) are never demanded.
630 if (InOp.getOpcode() == ISD::SRL &&
631 isa<ConstantSDNode>(InOp.getOperand(1))) {
632 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
633 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
634 unsigned Opc = ISD::SHL;
642 TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
643 EVT VT = Op.getValueType();
644 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
645 InOp.getOperand(0), NewSA));
649 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
650 KnownZero, KnownOne, TLO, Depth+1))
653 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
654 // are not demanded. This will likely allow the anyext to be folded away.
655 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
656 SDValue InnerOp = InOp.getNode()->getOperand(0);
657 EVT InnerVT = InnerOp.getValueType();
658 unsigned InnerBits = InnerVT.getSizeInBits();
659 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
660 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
661 EVT ShTy = getShiftAmountTy(InnerVT, DL);
662 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
665 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
666 TLO.DAG.getConstant(ShAmt, dl, ShTy));
669 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
672 // Repeat the SHL optimization above in cases where an extension
673 // intervenes: (shl (anyext (shr x, c1)), c2) to
674 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
675 // aren't demanded (as above) and that the shifted upper c1 bits of
676 // x aren't demanded.
677 if (InOp.hasOneUse() &&
678 InnerOp.getOpcode() == ISD::SRL &&
679 InnerOp.hasOneUse() &&
680 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
681 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
683 if (InnerShAmt < ShAmt &&
684 InnerShAmt < InnerBits &&
685 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
686 NewMask.trunc(ShAmt) == 0) {
688 TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
689 Op.getOperand(1).getValueType());
690 EVT VT = Op.getValueType();
691 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
692 InnerOp.getOperand(0));
693 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
699 KnownZero <<= SA->getZExtValue();
700 KnownOne <<= SA->getZExtValue();
701 // low bits known zero.
702 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
706 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
707 EVT VT = Op.getValueType();
708 unsigned ShAmt = SA->getZExtValue();
709 unsigned VTSize = VT.getSizeInBits();
710 SDValue InOp = Op.getOperand(0);
712 // If the shift count is an invalid immediate, don't do anything.
713 if (ShAmt >= BitWidth)
716 APInt InDemandedMask = (NewMask << ShAmt);
718 // If the shift is exact, then it does demand the low bits (and knows that
720 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
721 InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
723 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
724 // single shift. We can do this if the top bits (which are shifted out)
725 // are never demanded.
726 if (InOp.getOpcode() == ISD::SHL &&
727 isa<ConstantSDNode>(InOp.getOperand(1))) {
728 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
729 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
730 unsigned Opc = ISD::SRL;
738 TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
739 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
740 InOp.getOperand(0), NewSA));
744 // Compute the new bits that are at the top now.
745 if (SimplifyDemandedBits(InOp, InDemandedMask,
746 KnownZero, KnownOne, TLO, Depth+1))
748 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
749 KnownZero = KnownZero.lshr(ShAmt);
750 KnownOne = KnownOne.lshr(ShAmt);
752 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
753 KnownZero |= HighBits; // High bits known zero.
757 // If this is an arithmetic shift right and only the low-bit is set, we can
758 // always convert this into a logical shr, even if the shift amount is
759 // variable. The low bit of the shift cannot be an input sign bit unless
760 // the shift amount is >= the size of the datatype, which is undefined.
762 return TLO.CombineTo(Op,
763 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
764 Op.getOperand(0), Op.getOperand(1)));
766 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
767 EVT VT = Op.getValueType();
768 unsigned ShAmt = SA->getZExtValue();
770 // If the shift count is an invalid immediate, don't do anything.
771 if (ShAmt >= BitWidth)
774 APInt InDemandedMask = (NewMask << ShAmt);
776 // If the shift is exact, then it does demand the low bits (and knows that
778 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
779 InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
781 // If any of the demanded bits are produced by the sign extension, we also
782 // demand the input sign bit.
783 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
784 if (HighBits.intersects(NewMask))
785 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
787 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
788 KnownZero, KnownOne, TLO, Depth+1))
790 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
791 KnownZero = KnownZero.lshr(ShAmt);
792 KnownOne = KnownOne.lshr(ShAmt);
794 // Handle the sign bit, adjusted to where it is now in the mask.
795 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
797 // If the input sign bit is known to be zero, or if none of the top bits
798 // are demanded, turn this into an unsigned shift right.
799 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
801 Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact());
802 return TLO.CombineTo(Op,
803 TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0),
804 Op.getOperand(1), &Flags));
807 int Log2 = NewMask.exactLogBase2();
809 // The bit must come from the sign.
811 TLO.DAG.getConstant(BitWidth - 1 - Log2, dl,
812 Op.getOperand(1).getValueType());
813 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
814 Op.getOperand(0), NewSA));
817 if (KnownOne.intersects(SignBit))
818 // New bits are known one.
819 KnownOne |= HighBits;
822 case ISD::SIGN_EXTEND_INREG: {
823 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
825 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
826 // If we only care about the highest bit, don't bother shifting right.
827 if (MsbMask == NewMask) {
828 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
829 SDValue InOp = Op.getOperand(0);
830 unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits();
831 bool AlreadySignExtended =
832 TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
833 // However if the input is already sign extended we expect the sign
834 // extension to be dropped altogether later and do not simplify.
835 if (!AlreadySignExtended) {
836 // Compute the correct shift amount type, which must be getShiftAmountTy
837 // for scalar types after legalization.
838 EVT ShiftAmtTy = Op.getValueType();
839 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
840 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
842 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl,
844 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
845 Op.getValueType(), InOp,
850 // Sign extension. Compute the demanded bits in the result that are not
851 // present in the input.
853 APInt::getHighBitsSet(BitWidth,
854 BitWidth - ExVT.getScalarType().getSizeInBits());
856 // If none of the extended bits are demanded, eliminate the sextinreg.
857 if ((NewBits & NewMask) == 0)
858 return TLO.CombineTo(Op, Op.getOperand(0));
861 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
862 APInt InputDemandedBits =
863 APInt::getLowBitsSet(BitWidth,
864 ExVT.getScalarType().getSizeInBits()) &
867 // Since the sign extended bits are demanded, we know that the sign
869 InputDemandedBits |= InSignBit;
871 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
872 KnownZero, KnownOne, TLO, Depth+1))
874 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
876 // If the sign bit of the input is known set or clear, then we know the
877 // top bits of the result.
879 // If the input sign bit is known zero, convert this into a zero extension.
880 if (KnownZero.intersects(InSignBit))
881 return TLO.CombineTo(Op,
882 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
884 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
886 KnownZero &= ~NewBits;
887 } else { // Input sign bit unknown
888 KnownZero &= ~NewBits;
889 KnownOne &= ~NewBits;
893 case ISD::BUILD_PAIR: {
894 EVT HalfVT = Op.getOperand(0).getValueType();
895 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
897 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
898 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
900 APInt KnownZeroLo, KnownOneLo;
901 APInt KnownZeroHi, KnownOneHi;
903 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
904 KnownOneLo, TLO, Depth + 1))
907 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
908 KnownOneHi, TLO, Depth + 1))
911 KnownZero = KnownZeroLo.zext(BitWidth) |
912 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
914 KnownOne = KnownOneLo.zext(BitWidth) |
915 KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
918 case ISD::ZERO_EXTEND: {
919 unsigned OperandBitWidth =
920 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
921 APInt InMask = NewMask.trunc(OperandBitWidth);
923 // If none of the top bits are demanded, convert this into an any_extend.
925 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
926 if (!NewBits.intersects(NewMask))
927 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
931 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
932 KnownZero, KnownOne, TLO, Depth+1))
934 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
935 KnownZero = KnownZero.zext(BitWidth);
936 KnownOne = KnownOne.zext(BitWidth);
937 KnownZero |= NewBits;
940 case ISD::SIGN_EXTEND: {
941 EVT InVT = Op.getOperand(0).getValueType();
942 unsigned InBits = InVT.getScalarType().getSizeInBits();
943 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
944 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
945 APInt NewBits = ~InMask & NewMask;
947 // If none of the top bits are demanded, convert this into an any_extend.
949 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
953 // Since some of the sign extended bits are demanded, we know that the sign
955 APInt InDemandedBits = InMask & NewMask;
956 InDemandedBits |= InSignBit;
957 InDemandedBits = InDemandedBits.trunc(InBits);
959 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
960 KnownOne, TLO, Depth+1))
962 KnownZero = KnownZero.zext(BitWidth);
963 KnownOne = KnownOne.zext(BitWidth);
965 // If the sign bit is known zero, convert this to a zero extend.
966 if (KnownZero.intersects(InSignBit))
967 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
971 // If the sign bit is known one, the top bits match.
972 if (KnownOne.intersects(InSignBit)) {
974 assert((KnownZero & NewBits) == 0);
975 } else { // Otherwise, top bits aren't known.
976 assert((KnownOne & NewBits) == 0);
977 assert((KnownZero & NewBits) == 0);
981 case ISD::ANY_EXTEND: {
982 unsigned OperandBitWidth =
983 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
984 APInt InMask = NewMask.trunc(OperandBitWidth);
985 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
986 KnownZero, KnownOne, TLO, Depth+1))
988 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
989 KnownZero = KnownZero.zext(BitWidth);
990 KnownOne = KnownOne.zext(BitWidth);
993 case ISD::TRUNCATE: {
994 // Simplify the input, using demanded bit information, and compute the known
995 // zero/one bits live out.
996 unsigned OperandBitWidth =
997 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
998 APInt TruncMask = NewMask.zext(OperandBitWidth);
999 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1000 KnownZero, KnownOne, TLO, Depth+1))
1002 KnownZero = KnownZero.trunc(BitWidth);
1003 KnownOne = KnownOne.trunc(BitWidth);
1005 // If the input is only used by this truncate, see if we can shrink it based
1006 // on the known demanded bits.
1007 if (Op.getOperand(0).getNode()->hasOneUse()) {
1008 SDValue In = Op.getOperand(0);
1009 switch (In.getOpcode()) {
1012 // Shrink SRL by a constant if none of the high bits shifted in are
1014 if (TLO.LegalTypes() &&
1015 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1016 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1019 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1022 SDValue Shift = In.getOperand(1);
1023 if (TLO.LegalTypes()) {
1024 uint64_t ShVal = ShAmt->getZExtValue();
1025 Shift = TLO.DAG.getConstant(ShVal, dl,
1026 getShiftAmountTy(Op.getValueType(), DL));
1029 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1030 OperandBitWidth - BitWidth);
1031 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1033 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1034 // None of the shifted in bits are needed. Add a truncate of the
1035 // shift input, then shift it.
1036 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1039 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1048 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1051 case ISD::AssertZext: {
1052 // AssertZext demands all of the high bits, plus any of the low bits
1053 // demanded by its users.
1054 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1055 APInt InMask = APInt::getLowBitsSet(BitWidth,
1056 VT.getSizeInBits());
1057 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1058 KnownZero, KnownOne, TLO, Depth+1))
1060 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1062 KnownZero |= ~InMask & NewMask;
1066 // If this is an FP->Int bitcast and if the sign bit is the only
1067 // thing demanded, turn this into a FGETSIGN.
1068 if (!TLO.LegalOperations() &&
1069 !Op.getValueType().isVector() &&
1070 !Op.getOperand(0).getValueType().isVector() &&
1071 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1072 Op.getOperand(0).getValueType().isFloatingPoint()) {
1073 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1074 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1075 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1076 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1077 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1078 // place. We expect the SHL to be eliminated by other optimizations.
1079 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1080 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1081 if (!OpVTLegal && OpVTSizeInBits > 32)
1082 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1083 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1084 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, Op.getValueType());
1085 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1094 // Add, Sub, and Mul don't demand any bits in positions beyond that
1095 // of the highest bit demanded of them.
1096 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1097 BitWidth - NewMask.countLeadingZeros());
1098 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1099 KnownOne2, TLO, Depth+1))
1101 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1102 KnownOne2, TLO, Depth+1))
1104 // See if the operation should be performed at a smaller bit width.
1105 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1110 // Just use computeKnownBits to compute output bits.
1111 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1115 // If we know the value of all of the demanded bits, return this as a
1117 if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
1118 // Avoid folding to a constant if any OpaqueConstant is involved.
1119 const SDNode *N = Op.getNode();
1120 for (SDNodeIterator I = SDNodeIterator::begin(N),
1121 E = SDNodeIterator::end(N); I != E; ++I) {
1123 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
1127 return TLO.CombineTo(Op,
1128 TLO.DAG.getConstant(KnownOne, dl, Op.getValueType()));
1134 /// computeKnownBitsForTargetNode - Determine which of the bits specified
1135 /// in Mask are known to be either zero or one and return them in the
1136 /// KnownZero/KnownOne bitsets.
1137 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1140 const SelectionDAG &DAG,
1141 unsigned Depth) const {
1142 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1143 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1144 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1145 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1146 "Should use MaskedValueIsZero if you don't know whether Op"
1147 " is a target node!");
1148 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1151 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1152 /// targets that want to expose additional information about sign bits to the
1154 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1155 const SelectionDAG &,
1156 unsigned Depth) const {
1157 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1158 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1159 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1160 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1161 "Should use ComputeNumSignBits if you don't know whether Op"
1162 " is a target node!");
1166 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1167 /// one bit set. This differs from computeKnownBits in that it doesn't need to
1168 /// determine which bit is set.
1170 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1171 // A left-shift of a constant one will have exactly one bit set, because
1172 // shifting the bit off the end is undefined.
1173 if (Val.getOpcode() == ISD::SHL)
1174 if (ConstantSDNode *C =
1175 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1176 if (C->getAPIntValue() == 1)
1179 // Similarly, a right-shift of a constant sign-bit will have exactly
1181 if (Val.getOpcode() == ISD::SRL)
1182 if (ConstantSDNode *C =
1183 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1184 if (C->getAPIntValue().isSignBit())
1187 // More could be done here, though the above checks are enough
1188 // to handle some common cases.
1190 // Fall back to computeKnownBits to catch other known cases.
1191 EVT OpVT = Val.getValueType();
1192 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1193 APInt KnownZero, KnownOne;
1194 DAG.computeKnownBits(Val, KnownZero, KnownOne);
1195 return (KnownZero.countPopulation() == BitWidth - 1) &&
1196 (KnownOne.countPopulation() == 1);
1199 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1203 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1205 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1209 BitVector UndefElements;
1210 CN = BV->getConstantSplatNode(&UndefElements);
1211 // Only interested in constant splats, and we don't try to handle undef
1212 // elements in identifying boolean constants.
1213 if (!CN || UndefElements.none())
1217 switch (getBooleanContents(N->getValueType(0))) {
1218 case UndefinedBooleanContent:
1219 return CN->getAPIntValue()[0];
1220 case ZeroOrOneBooleanContent:
1222 case ZeroOrNegativeOneBooleanContent:
1223 return CN->isAllOnesValue();
1226 llvm_unreachable("Invalid boolean contents");
1229 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1233 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1235 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1239 BitVector UndefElements;
1240 CN = BV->getConstantSplatNode(&UndefElements);
1241 // Only interested in constant splats, and we don't try to handle undef
1242 // elements in identifying boolean constants.
1243 if (!CN || UndefElements.none())
1247 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
1248 return !CN->getAPIntValue()[0];
1250 return CN->isNullValue();
1253 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1254 /// and cc. If it is unable to simplify it, return a null SDValue.
1256 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1257 ISD::CondCode Cond, bool foldBooleans,
1258 DAGCombinerInfo &DCI, SDLoc dl) const {
1259 SelectionDAG &DAG = DCI.DAG;
1261 // These setcc operations always fold.
1265 case ISD::SETFALSE2: return DAG.getConstant(0, dl, VT);
1267 case ISD::SETTRUE2: {
1268 TargetLowering::BooleanContent Cnt =
1269 getBooleanContents(N0->getValueType(0));
1270 return DAG.getConstant(
1271 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, dl,
1276 // Ensure that the constant occurs on the RHS, and fold constant
1278 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1279 if (isa<ConstantSDNode>(N0.getNode()) &&
1280 (DCI.isBeforeLegalizeOps() ||
1281 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1282 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1284 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1285 const APInt &C1 = N1C->getAPIntValue();
1287 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1288 // equality comparison, then we're just comparing whether X itself is
1290 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1291 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1292 N0.getOperand(1).getOpcode() == ISD::Constant) {
1294 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1295 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1296 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1297 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1298 // (srl (ctlz x), 5) == 0 -> X != 0
1299 // (srl (ctlz x), 5) != 1 -> X != 0
1302 // (srl (ctlz x), 5) != 0 -> X == 0
1303 // (srl (ctlz x), 5) == 1 -> X == 0
1306 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
1307 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1313 // Look through truncs that don't change the value of a ctpop.
1314 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1315 CTPOP = N0.getOperand(0);
1317 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1318 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1319 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1320 EVT CTVT = CTPOP.getValueType();
1321 SDValue CTOp = CTPOP.getOperand(0);
1323 // (ctpop x) u< 2 -> (x & x-1) == 0
1324 // (ctpop x) u> 1 -> (x & x-1) != 0
1325 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1326 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1327 DAG.getConstant(1, dl, CTVT));
1328 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1329 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1330 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
1333 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1336 // (zext x) == C --> x == (trunc C)
1337 // (sext x) == C --> x == (trunc C)
1338 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1339 DCI.isBeforeLegalize() && N0->hasOneUse()) {
1340 unsigned MinBits = N0.getValueSizeInBits();
1342 bool Signed = false;
1343 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1345 MinBits = N0->getOperand(0).getValueSizeInBits();
1346 PreExt = N0->getOperand(0);
1347 } else if (N0->getOpcode() == ISD::AND) {
1348 // DAGCombine turns costly ZExts into ANDs
1349 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1350 if ((C->getAPIntValue()+1).isPowerOf2()) {
1351 MinBits = C->getAPIntValue().countTrailingOnes();
1352 PreExt = N0->getOperand(0);
1354 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
1356 MinBits = N0->getOperand(0).getValueSizeInBits();
1357 PreExt = N0->getOperand(0);
1359 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1360 // ZEXTLOAD / SEXTLOAD
1361 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1362 MinBits = LN0->getMemoryVT().getSizeInBits();
1364 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
1366 MinBits = LN0->getMemoryVT().getSizeInBits();
1371 // Figure out how many bits we need to preserve this constant.
1372 unsigned ReqdBits = Signed ?
1373 C1.getBitWidth() - C1.getNumSignBits() + 1 :
1376 // Make sure we're not losing bits from the constant.
1378 MinBits < C1.getBitWidth() &&
1379 MinBits >= ReqdBits) {
1380 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1381 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1382 // Will get folded away.
1383 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
1384 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
1385 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1390 // If the LHS is '(and load, const)', the RHS is 0,
1391 // the test is for equality or unsigned, and all 1 bits of the const are
1392 // in the same partial word, see if we can shorten the load.
1393 if (DCI.isBeforeLegalize() &&
1394 !ISD::isSignedIntSetCC(Cond) &&
1395 N0.getOpcode() == ISD::AND && C1 == 0 &&
1396 N0.getNode()->hasOneUse() &&
1397 isa<LoadSDNode>(N0.getOperand(0)) &&
1398 N0.getOperand(0).getNode()->hasOneUse() &&
1399 isa<ConstantSDNode>(N0.getOperand(1))) {
1400 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1402 unsigned bestWidth = 0, bestOffset = 0;
1403 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1404 unsigned origWidth = N0.getValueType().getSizeInBits();
1405 unsigned maskWidth = origWidth;
1406 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1407 // 8 bits, but have to be careful...
1408 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1409 origWidth = Lod->getMemoryVT().getSizeInBits();
1411 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1412 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1413 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1414 for (unsigned offset=0; offset<origWidth/width; offset++) {
1415 if ((newMask & Mask) == Mask) {
1416 if (!DAG.getDataLayout().isLittleEndian())
1417 bestOffset = (origWidth/width - offset - 1) * (width/8);
1419 bestOffset = (uint64_t)offset * (width/8);
1420 bestMask = Mask.lshr(offset * (width/8) * 8);
1424 newMask = newMask << width;
1429 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1430 if (newVT.isRound()) {
1431 EVT PtrType = Lod->getOperand(1).getValueType();
1432 SDValue Ptr = Lod->getBasePtr();
1433 if (bestOffset != 0)
1434 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1435 DAG.getConstant(bestOffset, dl, PtrType));
1436 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1437 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1438 Lod->getPointerInfo().getWithOffset(bestOffset),
1439 false, false, false, NewAlign);
1440 return DAG.getSetCC(dl, VT,
1441 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1442 DAG.getConstant(bestMask.trunc(bestWidth),
1444 DAG.getConstant(0LL, dl, newVT), Cond);
1449 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1450 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1451 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1453 // If the comparison constant has bits in the upper part, the
1454 // zero-extended value could never match.
1455 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1456 C1.getBitWidth() - InSize))) {
1460 case ISD::SETEQ: return DAG.getConstant(0, dl, VT);
1463 case ISD::SETNE: return DAG.getConstant(1, dl, VT);
1466 // True if the sign bit of C1 is set.
1467 return DAG.getConstant(C1.isNegative(), dl, VT);
1470 // True if the sign bit of C1 isn't set.
1471 return DAG.getConstant(C1.isNonNegative(), dl, VT);
1477 // Otherwise, we can perform the comparison with the low bits.
1485 EVT newVT = N0.getOperand(0).getValueType();
1486 if (DCI.isBeforeLegalizeOps() ||
1487 (isOperationLegal(ISD::SETCC, newVT) &&
1488 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1490 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), newVT);
1491 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
1493 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1495 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1500 break; // todo, be more careful with signed comparisons
1502 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1503 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1504 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1505 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1506 EVT ExtDstTy = N0.getValueType();
1507 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1509 // If the constant doesn't fit into the number of bits for the source of
1510 // the sign extension, it is impossible for both sides to be equal.
1511 if (C1.getMinSignedBits() > ExtSrcTyBits)
1512 return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
1515 EVT Op0Ty = N0.getOperand(0).getValueType();
1516 if (Op0Ty == ExtSrcTy) {
1517 ZextOp = N0.getOperand(0);
1519 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1520 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1521 DAG.getConstant(Imm, dl, Op0Ty));
1523 if (!DCI.isCalledByLegalizer())
1524 DCI.AddToWorklist(ZextOp.getNode());
1525 // Otherwise, make this a use of a zext.
1526 return DAG.getSetCC(dl, VT, ZextOp,
1527 DAG.getConstant(C1 & APInt::getLowBitsSet(
1532 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1533 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1534 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1535 if (N0.getOpcode() == ISD::SETCC &&
1536 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1537 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1539 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1540 // Invert the condition.
1541 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1542 CC = ISD::getSetCCInverse(CC,
1543 N0.getOperand(0).getValueType().isInteger());
1544 if (DCI.isBeforeLegalizeOps() ||
1545 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1546 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1549 if ((N0.getOpcode() == ISD::XOR ||
1550 (N0.getOpcode() == ISD::AND &&
1551 N0.getOperand(0).getOpcode() == ISD::XOR &&
1552 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1553 isa<ConstantSDNode>(N0.getOperand(1)) &&
1554 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1555 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1556 // can only do this if the top bits are known zero.
1557 unsigned BitWidth = N0.getValueSizeInBits();
1558 if (DAG.MaskedValueIsZero(N0,
1559 APInt::getHighBitsSet(BitWidth,
1561 // Okay, get the un-inverted input value.
1563 if (N0.getOpcode() == ISD::XOR)
1564 Val = N0.getOperand(0);
1566 assert(N0.getOpcode() == ISD::AND &&
1567 N0.getOperand(0).getOpcode() == ISD::XOR);
1568 // ((X^1)&1)^1 -> X & 1
1569 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1570 N0.getOperand(0).getOperand(0),
1574 return DAG.getSetCC(dl, VT, Val, N1,
1575 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1577 } else if (N1C->getAPIntValue() == 1 &&
1579 getBooleanContents(N0->getValueType(0)) ==
1580 ZeroOrOneBooleanContent)) {
1582 if (Op0.getOpcode() == ISD::TRUNCATE)
1583 Op0 = Op0.getOperand(0);
1585 if ((Op0.getOpcode() == ISD::XOR) &&
1586 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1587 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1588 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1589 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1590 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1593 if (Op0.getOpcode() == ISD::AND &&
1594 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1595 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1596 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1597 if (Op0.getValueType().bitsGT(VT))
1598 Op0 = DAG.getNode(ISD::AND, dl, VT,
1599 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1600 DAG.getConstant(1, dl, VT));
1601 else if (Op0.getValueType().bitsLT(VT))
1602 Op0 = DAG.getNode(ISD::AND, dl, VT,
1603 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1604 DAG.getConstant(1, dl, VT));
1606 return DAG.getSetCC(dl, VT, Op0,
1607 DAG.getConstant(0, dl, Op0.getValueType()),
1608 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1610 if (Op0.getOpcode() == ISD::AssertZext &&
1611 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1612 return DAG.getSetCC(dl, VT, Op0,
1613 DAG.getConstant(0, dl, Op0.getValueType()),
1614 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1618 APInt MinVal, MaxVal;
1619 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1620 if (ISD::isSignedIntSetCC(Cond)) {
1621 MinVal = APInt::getSignedMinValue(OperandBitSize);
1622 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1624 MinVal = APInt::getMinValue(OperandBitSize);
1625 MaxVal = APInt::getMaxValue(OperandBitSize);
1628 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1629 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1630 if (C1 == MinVal) return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1631 // X >= C0 --> X > (C0 - 1)
1633 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1634 if ((DCI.isBeforeLegalizeOps() ||
1635 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1636 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1637 isLegalICmpImmediate(C.getSExtValue())))) {
1638 return DAG.getSetCC(dl, VT, N0,
1639 DAG.getConstant(C, dl, N1.getValueType()),
1644 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1645 if (C1 == MaxVal) return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1646 // X <= C0 --> X < (C0 + 1)
1648 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1649 if ((DCI.isBeforeLegalizeOps() ||
1650 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1651 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1652 isLegalICmpImmediate(C.getSExtValue())))) {
1653 return DAG.getSetCC(dl, VT, N0,
1654 DAG.getConstant(C, dl, N1.getValueType()),
1659 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1660 return DAG.getConstant(0, dl, VT); // X < MIN --> false
1661 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1662 return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1663 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1664 return DAG.getConstant(0, dl, VT); // X > MAX --> false
1665 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1666 return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1668 // Canonicalize setgt X, Min --> setne X, Min
1669 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1670 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1671 // Canonicalize setlt X, Max --> setne X, Max
1672 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1673 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1675 // If we have setult X, 1, turn it into seteq X, 0
1676 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1677 return DAG.getSetCC(dl, VT, N0,
1678 DAG.getConstant(MinVal, dl, N0.getValueType()),
1680 // If we have setugt X, Max-1, turn it into seteq X, Max
1681 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1682 return DAG.getSetCC(dl, VT, N0,
1683 DAG.getConstant(MaxVal, dl, N0.getValueType()),
1686 // If we have "setcc X, C0", check to see if we can shrink the immediate
1689 // SETUGT X, SINTMAX -> SETLT X, 0
1690 if (Cond == ISD::SETUGT &&
1691 C1 == APInt::getSignedMaxValue(OperandBitSize))
1692 return DAG.getSetCC(dl, VT, N0,
1693 DAG.getConstant(0, dl, N1.getValueType()),
1696 // SETULT X, SINTMIN -> SETGT X, -1
1697 if (Cond == ISD::SETULT &&
1698 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1699 SDValue ConstMinusOne =
1700 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
1702 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1705 // Fold bit comparisons when we can.
1706 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1707 (VT == N0.getValueType() ||
1708 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1709 N0.getOpcode() == ISD::AND) {
1710 auto &DL = DAG.getDataLayout();
1711 if (ConstantSDNode *AndRHS =
1712 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1713 EVT ShiftTy = DCI.isBeforeLegalize()
1715 : getShiftAmountTy(N0.getValueType(), DL);
1716 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1717 // Perform the xform if the AND RHS is a single bit.
1718 if (AndRHS->getAPIntValue().isPowerOf2()) {
1719 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1720 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1721 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
1724 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1725 // (X & 8) == 8 --> (X & 8) >> 3
1726 // Perform the xform if C1 is a single bit.
1727 if (C1.isPowerOf2()) {
1728 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1729 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1730 DAG.getConstant(C1.logBase2(), dl,
1737 if (C1.getMinSignedBits() <= 64 &&
1738 !isLegalICmpImmediate(C1.getSExtValue())) {
1739 // (X & -256) == 256 -> (X >> 8) == 1
1740 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1741 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1742 if (ConstantSDNode *AndRHS =
1743 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1744 const APInt &AndRHSC = AndRHS->getAPIntValue();
1745 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1746 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1747 auto &DL = DAG.getDataLayout();
1748 EVT ShiftTy = DCI.isBeforeLegalize()
1750 : getShiftAmountTy(N0.getValueType(), DL);
1751 EVT CmpTy = N0.getValueType();
1752 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1753 DAG.getConstant(ShiftBits, dl,
1755 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
1756 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1759 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1760 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1761 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1762 // X < 0x100000000 -> (X >> 32) < 1
1763 // X >= 0x100000000 -> (X >> 32) >= 1
1764 // X <= 0x0ffffffff -> (X >> 32) < 1
1765 // X > 0x0ffffffff -> (X >> 32) >= 1
1768 ISD::CondCode NewCond = Cond;
1770 ShiftBits = C1.countTrailingOnes();
1772 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1774 ShiftBits = C1.countTrailingZeros();
1776 NewC = NewC.lshr(ShiftBits);
1777 if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
1778 isLegalICmpImmediate(NewC.getSExtValue())) {
1779 auto &DL = DAG.getDataLayout();
1780 EVT ShiftTy = DCI.isBeforeLegalize()
1782 : getShiftAmountTy(N0.getValueType(), DL);
1783 EVT CmpTy = N0.getValueType();
1784 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1785 DAG.getConstant(ShiftBits, dl, ShiftTy));
1786 SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
1787 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1793 if (isa<ConstantFPSDNode>(N0.getNode())) {
1794 // Constant fold or commute setcc.
1795 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1796 if (O.getNode()) return O;
1797 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1798 // If the RHS of an FP comparison is a constant, simplify it away in
1800 if (CFP->getValueAPF().isNaN()) {
1801 // If an operand is known to be a nan, we can fold it.
1802 switch (ISD::getUnorderedFlavor(Cond)) {
1803 default: llvm_unreachable("Unknown flavor!");
1804 case 0: // Known false.
1805 return DAG.getConstant(0, dl, VT);
1806 case 1: // Known true.
1807 return DAG.getConstant(1, dl, VT);
1808 case 2: // Undefined.
1809 return DAG.getUNDEF(VT);
1813 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1814 // constant if knowing that the operand is non-nan is enough. We prefer to
1815 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1817 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1818 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1820 // If the condition is not legal, see if we can find an equivalent one
1822 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1823 // If the comparison was an awkward floating-point == or != and one of
1824 // the comparison operands is infinity or negative infinity, convert the
1825 // condition to a less-awkward <= or >=.
1826 if (CFP->getValueAPF().isInfinity()) {
1827 if (CFP->getValueAPF().isNegative()) {
1828 if (Cond == ISD::SETOEQ &&
1829 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1830 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1831 if (Cond == ISD::SETUEQ &&
1832 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1833 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1834 if (Cond == ISD::SETUNE &&
1835 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1836 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1837 if (Cond == ISD::SETONE &&
1838 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1839 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1841 if (Cond == ISD::SETOEQ &&
1842 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1843 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1844 if (Cond == ISD::SETUEQ &&
1845 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1846 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1847 if (Cond == ISD::SETUNE &&
1848 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1849 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1850 if (Cond == ISD::SETONE &&
1851 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1852 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1859 // The sext(setcc()) => setcc() optimization relies on the appropriate
1860 // constant being emitted.
1862 switch (getBooleanContents(N0.getValueType())) {
1863 case UndefinedBooleanContent:
1864 case ZeroOrOneBooleanContent:
1865 EqVal = ISD::isTrueWhenEqual(Cond);
1867 case ZeroOrNegativeOneBooleanContent:
1868 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1872 // We can always fold X == X for integer setcc's.
1873 if (N0.getValueType().isInteger()) {
1874 return DAG.getConstant(EqVal, dl, VT);
1876 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1877 if (UOF == 2) // FP operators that are undefined on NaNs.
1878 return DAG.getConstant(EqVal, dl, VT);
1879 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1880 return DAG.getConstant(EqVal, dl, VT);
1881 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1882 // if it is not already.
1883 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1884 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1885 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1886 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1889 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1890 N0.getValueType().isInteger()) {
1891 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1892 N0.getOpcode() == ISD::XOR) {
1893 // Simplify (X+Y) == (X+Z) --> Y == Z
1894 if (N0.getOpcode() == N1.getOpcode()) {
1895 if (N0.getOperand(0) == N1.getOperand(0))
1896 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1897 if (N0.getOperand(1) == N1.getOperand(1))
1898 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1899 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1900 // If X op Y == Y op X, try other combinations.
1901 if (N0.getOperand(0) == N1.getOperand(1))
1902 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1904 if (N0.getOperand(1) == N1.getOperand(0))
1905 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1910 // If RHS is a legal immediate value for a compare instruction, we need
1911 // to be careful about increasing register pressure needlessly.
1912 bool LegalRHSImm = false;
1914 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1915 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1916 // Turn (X+C1) == C2 --> X == C2-C1
1917 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1918 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1919 DAG.getConstant(RHSC->getAPIntValue()-
1920 LHSR->getAPIntValue(),
1921 dl, N0.getValueType()), Cond);
1924 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1925 if (N0.getOpcode() == ISD::XOR)
1926 // If we know that all of the inverted bits are zero, don't bother
1927 // performing the inversion.
1928 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1930 DAG.getSetCC(dl, VT, N0.getOperand(0),
1931 DAG.getConstant(LHSR->getAPIntValue() ^
1932 RHSC->getAPIntValue(),
1933 dl, N0.getValueType()),
1937 // Turn (C1-X) == C2 --> X == C1-C2
1938 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1939 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1941 DAG.getSetCC(dl, VT, N0.getOperand(1),
1942 DAG.getConstant(SUBC->getAPIntValue() -
1943 RHSC->getAPIntValue(),
1944 dl, N0.getValueType()),
1949 // Could RHSC fold directly into a compare?
1950 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1951 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1954 // Simplify (X+Z) == X --> Z == 0
1955 // Don't do this if X is an immediate that can fold into a cmp
1956 // instruction and X+Z has other uses. It could be an induction variable
1957 // chain, and the transform would increase register pressure.
1958 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1959 if (N0.getOperand(0) == N1)
1960 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1961 DAG.getConstant(0, dl, N0.getValueType()), Cond);
1962 if (N0.getOperand(1) == N1) {
1963 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1964 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1965 DAG.getConstant(0, dl, N0.getValueType()),
1967 if (N0.getNode()->hasOneUse()) {
1968 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1969 auto &DL = DAG.getDataLayout();
1970 // (Z-X) == X --> Z == X<<1
1971 SDValue SH = DAG.getNode(
1972 ISD::SHL, dl, N1.getValueType(), N1,
1973 DAG.getConstant(1, dl,
1974 getShiftAmountTy(N1.getValueType(), DL)));
1975 if (!DCI.isCalledByLegalizer())
1976 DCI.AddToWorklist(SH.getNode());
1977 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1983 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1984 N1.getOpcode() == ISD::XOR) {
1985 // Simplify X == (X+Z) --> Z == 0
1986 if (N1.getOperand(0) == N0)
1987 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1988 DAG.getConstant(0, dl, N1.getValueType()), Cond);
1989 if (N1.getOperand(1) == N0) {
1990 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1991 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1992 DAG.getConstant(0, dl, N1.getValueType()), Cond);
1993 if (N1.getNode()->hasOneUse()) {
1994 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1995 auto &DL = DAG.getDataLayout();
1996 // X == (Z-X) --> X<<1 == Z
1997 SDValue SH = DAG.getNode(
1998 ISD::SHL, dl, N1.getValueType(), N0,
1999 DAG.getConstant(1, dl, getShiftAmountTy(N0.getValueType(), DL)));
2000 if (!DCI.isCalledByLegalizer())
2001 DCI.AddToWorklist(SH.getNode());
2002 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2007 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2008 // Note that where y is variable and is known to have at most
2009 // one bit set (for example, if it is z&1) we cannot do this;
2010 // the expressions are not equivalent when y==0.
2011 if (N0.getOpcode() == ISD::AND)
2012 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2013 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2014 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2015 if (DCI.isBeforeLegalizeOps() ||
2016 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
2017 SDValue Zero = DAG.getConstant(0, dl, N1.getValueType());
2018 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2022 if (N1.getOpcode() == ISD::AND)
2023 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2024 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2025 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2026 if (DCI.isBeforeLegalizeOps() ||
2027 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
2028 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
2029 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2035 // Fold away ALL boolean setcc's.
2037 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2039 default: llvm_unreachable("Unknown integer setcc!");
2040 case ISD::SETEQ: // X == Y -> ~(X^Y)
2041 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2042 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2043 if (!DCI.isCalledByLegalizer())
2044 DCI.AddToWorklist(Temp.getNode());
2046 case ISD::SETNE: // X != Y --> (X^Y)
2047 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2049 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2050 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2051 Temp = DAG.getNOT(dl, N0, MVT::i1);
2052 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2053 if (!DCI.isCalledByLegalizer())
2054 DCI.AddToWorklist(Temp.getNode());
2056 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2057 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2058 Temp = DAG.getNOT(dl, N1, MVT::i1);
2059 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2060 if (!DCI.isCalledByLegalizer())
2061 DCI.AddToWorklist(Temp.getNode());
2063 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2064 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2065 Temp = DAG.getNOT(dl, N0, MVT::i1);
2066 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2067 if (!DCI.isCalledByLegalizer())
2068 DCI.AddToWorklist(Temp.getNode());
2070 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2071 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2072 Temp = DAG.getNOT(dl, N1, MVT::i1);
2073 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2076 if (VT != MVT::i1) {
2077 if (!DCI.isCalledByLegalizer())
2078 DCI.AddToWorklist(N0.getNode());
2079 // FIXME: If running after legalize, we probably can't do this.
2080 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2085 // Could not fold it.
2089 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2090 /// node is a GlobalAddress + offset.
2091 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2092 int64_t &Offset) const {
2093 if (isa<GlobalAddressSDNode>(N)) {
2094 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2095 GA = GASD->getGlobal();
2096 Offset += GASD->getOffset();
2100 if (N->getOpcode() == ISD::ADD) {
2101 SDValue N1 = N->getOperand(0);
2102 SDValue N2 = N->getOperand(1);
2103 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2104 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2106 Offset += V->getSExtValue();
2109 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2110 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2112 Offset += V->getSExtValue();
2121 SDValue TargetLowering::PerformDAGCombine(SDNode *N,
2122 DAGCombinerInfo &DCI) const {
2123 // Default implementation: no optimization.
2127 //===----------------------------------------------------------------------===//
2128 // Inline Assembler Implementation Methods
2129 //===----------------------------------------------------------------------===//
2131 TargetLowering::ConstraintType
2132 TargetLowering::getConstraintType(StringRef Constraint) const {
2133 unsigned S = Constraint.size();
2136 switch (Constraint[0]) {
2138 case 'r': return C_RegisterClass;
2140 case 'o': // offsetable
2141 case 'V': // not offsetable
2143 case 'i': // Simple Integer or Relocatable Constant
2144 case 'n': // Simple Integer
2145 case 'E': // Floating Point Constant
2146 case 'F': // Floating Point Constant
2147 case 's': // Relocatable Constant
2148 case 'p': // Address.
2149 case 'X': // Allow ANY value.
2150 case 'I': // Target registers.
2164 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2165 if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
2172 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2173 /// with another that has more specific requirements based on the type of the
2174 /// corresponding operand.
2175 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2176 if (ConstraintVT.isInteger())
2178 if (ConstraintVT.isFloatingPoint())
2179 return "f"; // works for many targets
2183 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2184 /// vector. If it is invalid, don't add anything to Ops.
2185 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2186 std::string &Constraint,
2187 std::vector<SDValue> &Ops,
2188 SelectionDAG &DAG) const {
2190 if (Constraint.length() > 1) return;
2192 char ConstraintLetter = Constraint[0];
2193 switch (ConstraintLetter) {
2195 case 'X': // Allows any operand; labels (basic block) use this.
2196 if (Op.getOpcode() == ISD::BasicBlock) {
2201 case 'i': // Simple Integer or Relocatable Constant
2202 case 'n': // Simple Integer
2203 case 's': { // Relocatable Constant
2204 // These operands are interested in values of the form (GV+C), where C may
2205 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2206 // is possible and fine if either GV or C are missing.
2207 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2208 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2210 // If we have "(add GV, C)", pull out GV/C
2211 if (Op.getOpcode() == ISD::ADD) {
2212 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2213 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2215 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2216 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2219 C = nullptr, GA = nullptr;
2222 // If we find a valid operand, map to the TargetXXX version so that the
2223 // value itself doesn't get selected.
2224 if (GA) { // Either &GV or &GV+C
2225 if (ConstraintLetter != 'n') {
2226 int64_t Offs = GA->getOffset();
2227 if (C) Offs += C->getZExtValue();
2228 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2229 C ? SDLoc(C) : SDLoc(),
2230 Op.getValueType(), Offs));
2234 if (C) { // just C, no GV.
2235 // Simple constants are not allowed for 's'.
2236 if (ConstraintLetter != 's') {
2237 // gcc prints these as sign extended. Sign extend value to 64 bits
2238 // now; without this it would get ZExt'd later in
2239 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2240 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2241 SDLoc(C), MVT::i64));
2250 std::pair<unsigned, const TargetRegisterClass *>
2251 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
2252 StringRef Constraint,
2254 if (Constraint.empty() || Constraint[0] != '{')
2255 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2256 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2258 // Remove the braces from around the name.
2259 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2261 std::pair<unsigned, const TargetRegisterClass*> R =
2262 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2264 // Figure out which register class contains this reg.
2265 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2266 E = RI->regclass_end(); RCI != E; ++RCI) {
2267 const TargetRegisterClass *RC = *RCI;
2269 // If none of the value types for this register class are valid, we
2270 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2274 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2276 if (RegName.equals_lower(RI->getName(*I))) {
2277 std::pair<unsigned, const TargetRegisterClass*> S =
2278 std::make_pair(*I, RC);
2280 // If this register class has the requested value type, return it,
2281 // otherwise keep searching and return the first class found
2282 // if no other is found which explicitly has the requested type.
2283 if (RC->hasType(VT))
2294 //===----------------------------------------------------------------------===//
2295 // Constraint Selection.
2297 /// isMatchingInputConstraint - Return true of this is an input operand that is
2298 /// a matching constraint like "4".
2299 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2300 assert(!ConstraintCode.empty() && "No known constraint!");
2301 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2304 /// getMatchedOperand - If this is an input matching constraint, this method
2305 /// returns the output operand it matches.
2306 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2307 assert(!ConstraintCode.empty() && "No known constraint!");
2308 return atoi(ConstraintCode.c_str());
2311 /// ParseConstraints - Split up the constraint string from the inline
2312 /// assembly value into the specific constraints and their prefixes,
2313 /// and also tie in the associated operand values.
2314 /// If this returns an empty vector, and if the constraint string itself
2315 /// isn't empty, there was an error parsing.
2316 TargetLowering::AsmOperandInfoVector
2317 TargetLowering::ParseConstraints(const DataLayout &DL,
2318 const TargetRegisterInfo *TRI,
2319 ImmutableCallSite CS) const {
2320 /// ConstraintOperands - Information about all of the constraints.
2321 AsmOperandInfoVector ConstraintOperands;
2322 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2323 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2325 // Do a prepass over the constraints, canonicalizing them, and building up the
2326 // ConstraintOperands list.
2327 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2328 unsigned ResNo = 0; // ResNo - The result number of the next output.
2330 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
2331 ConstraintOperands.emplace_back(std::move(CI));
2332 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2334 // Update multiple alternative constraint count.
2335 if (OpInfo.multipleAlternatives.size() > maCount)
2336 maCount = OpInfo.multipleAlternatives.size();
2338 OpInfo.ConstraintVT = MVT::Other;
2340 // Compute the value type for each operand.
2341 switch (OpInfo.Type) {
2342 case InlineAsm::isOutput:
2343 // Indirect outputs just consume an argument.
2344 if (OpInfo.isIndirect) {
2345 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2349 // The return value of the call is this value. As such, there is no
2350 // corresponding argument.
2351 assert(!CS.getType()->isVoidTy() &&
2353 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2354 OpInfo.ConstraintVT =
2355 getSimpleValueType(DL, STy->getElementType(ResNo));
2357 assert(ResNo == 0 && "Asm only has one result!");
2358 OpInfo.ConstraintVT = getSimpleValueType(DL, CS.getType());
2362 case InlineAsm::isInput:
2363 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2365 case InlineAsm::isClobber:
2370 if (OpInfo.CallOperandVal) {
2371 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2372 if (OpInfo.isIndirect) {
2373 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2375 report_fatal_error("Indirect operand for inline asm not a pointer!");
2376 OpTy = PtrTy->getElementType();
2379 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2380 if (StructType *STy = dyn_cast<StructType>(OpTy))
2381 if (STy->getNumElements() == 1)
2382 OpTy = STy->getElementType(0);
2384 // If OpTy is not a single value, it may be a struct/union that we
2385 // can tile with integers.
2386 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2387 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
2396 OpInfo.ConstraintVT =
2397 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2400 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2401 unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace());
2402 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2404 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2409 // If we have multiple alternative constraints, select the best alternative.
2410 if (!ConstraintOperands.empty()) {
2412 unsigned bestMAIndex = 0;
2413 int bestWeight = -1;
2414 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2417 // Compute the sums of the weights for each alternative, keeping track
2418 // of the best (highest weight) one so far.
2419 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2421 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2422 cIndex != eIndex; ++cIndex) {
2423 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2424 if (OpInfo.Type == InlineAsm::isClobber)
2427 // If this is an output operand with a matching input operand,
2428 // look up the matching input. If their types mismatch, e.g. one
2429 // is an integer, the other is floating point, or their sizes are
2430 // different, flag it as an maCantMatch.
2431 if (OpInfo.hasMatchingInput()) {
2432 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2433 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2434 if ((OpInfo.ConstraintVT.isInteger() !=
2435 Input.ConstraintVT.isInteger()) ||
2436 (OpInfo.ConstraintVT.getSizeInBits() !=
2437 Input.ConstraintVT.getSizeInBits())) {
2438 weightSum = -1; // Can't match.
2443 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2448 weightSum += weight;
2451 if (weightSum > bestWeight) {
2452 bestWeight = weightSum;
2453 bestMAIndex = maIndex;
2457 // Now select chosen alternative in each constraint.
2458 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2459 cIndex != eIndex; ++cIndex) {
2460 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2461 if (cInfo.Type == InlineAsm::isClobber)
2463 cInfo.selectAlternative(bestMAIndex);
2468 // Check and hook up tied operands, choose constraint code to use.
2469 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2470 cIndex != eIndex; ++cIndex) {
2471 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2473 // If this is an output operand with a matching input operand, look up the
2474 // matching input. If their types mismatch, e.g. one is an integer, the
2475 // other is floating point, or their sizes are different, flag it as an
2477 if (OpInfo.hasMatchingInput()) {
2478 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2480 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2481 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2482 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
2483 OpInfo.ConstraintVT);
2484 std::pair<unsigned, const TargetRegisterClass *> InputRC =
2485 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
2486 Input.ConstraintVT);
2487 if ((OpInfo.ConstraintVT.isInteger() !=
2488 Input.ConstraintVT.isInteger()) ||
2489 (MatchRC.second != InputRC.second)) {
2490 report_fatal_error("Unsupported asm: input constraint"
2491 " with a matching output constraint of"
2492 " incompatible type!");
2498 return ConstraintOperands;
2501 /// getConstraintGenerality - Return an integer indicating how general CT
2503 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2505 case TargetLowering::C_Other:
2506 case TargetLowering::C_Unknown:
2508 case TargetLowering::C_Register:
2510 case TargetLowering::C_RegisterClass:
2512 case TargetLowering::C_Memory:
2515 llvm_unreachable("Invalid constraint type");
2518 /// Examine constraint type and operand type and determine a weight value.
2519 /// This object must already have been set up with the operand type
2520 /// and the current alternative constraint selected.
2521 TargetLowering::ConstraintWeight
2522 TargetLowering::getMultipleConstraintMatchWeight(
2523 AsmOperandInfo &info, int maIndex) const {
2524 InlineAsm::ConstraintCodeVector *rCodes;
2525 if (maIndex >= (int)info.multipleAlternatives.size())
2526 rCodes = &info.Codes;
2528 rCodes = &info.multipleAlternatives[maIndex].Codes;
2529 ConstraintWeight BestWeight = CW_Invalid;
2531 // Loop over the options, keeping track of the most general one.
2532 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2533 ConstraintWeight weight =
2534 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2535 if (weight > BestWeight)
2536 BestWeight = weight;
2542 /// Examine constraint type and operand type and determine a weight value.
2543 /// This object must already have been set up with the operand type
2544 /// and the current alternative constraint selected.
2545 TargetLowering::ConstraintWeight
2546 TargetLowering::getSingleConstraintMatchWeight(
2547 AsmOperandInfo &info, const char *constraint) const {
2548 ConstraintWeight weight = CW_Invalid;
2549 Value *CallOperandVal = info.CallOperandVal;
2550 // If we don't have a value, we can't do a match,
2551 // but allow it at the lowest weight.
2552 if (!CallOperandVal)
2554 // Look at the constraint type.
2555 switch (*constraint) {
2556 case 'i': // immediate integer.
2557 case 'n': // immediate integer with a known value.
2558 if (isa<ConstantInt>(CallOperandVal))
2559 weight = CW_Constant;
2561 case 's': // non-explicit intregal immediate.
2562 if (isa<GlobalValue>(CallOperandVal))
2563 weight = CW_Constant;
2565 case 'E': // immediate float if host format.
2566 case 'F': // immediate float.
2567 if (isa<ConstantFP>(CallOperandVal))
2568 weight = CW_Constant;
2570 case '<': // memory operand with autodecrement.
2571 case '>': // memory operand with autoincrement.
2572 case 'm': // memory operand.
2573 case 'o': // offsettable memory operand
2574 case 'V': // non-offsettable memory operand
2577 case 'r': // general register.
2578 case 'g': // general register, memory operand or immediate integer.
2579 // note: Clang converts "g" to "imr".
2580 if (CallOperandVal->getType()->isIntegerTy())
2581 weight = CW_Register;
2583 case 'X': // any operand.
2585 weight = CW_Default;
2591 /// ChooseConstraint - If there are multiple different constraints that we
2592 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2593 /// This is somewhat tricky: constraints fall into four classes:
2594 /// Other -> immediates and magic values
2595 /// Register -> one specific register
2596 /// RegisterClass -> a group of regs
2597 /// Memory -> memory
2598 /// Ideally, we would pick the most specific constraint possible: if we have
2599 /// something that fits into a register, we would pick it. The problem here
2600 /// is that if we have something that could either be in a register or in
2601 /// memory that use of the register could cause selection of *other*
2602 /// operands to fail: they might only succeed if we pick memory. Because of
2603 /// this the heuristic we use is:
2605 /// 1) If there is an 'other' constraint, and if the operand is valid for
2606 /// that constraint, use it. This makes us take advantage of 'i'
2607 /// constraints when available.
2608 /// 2) Otherwise, pick the most general constraint present. This prefers
2609 /// 'm' over 'r', for example.
2611 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2612 const TargetLowering &TLI,
2613 SDValue Op, SelectionDAG *DAG) {
2614 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2615 unsigned BestIdx = 0;
2616 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2617 int BestGenerality = -1;
2619 // Loop over the options, keeping track of the most general one.
2620 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2621 TargetLowering::ConstraintType CType =
2622 TLI.getConstraintType(OpInfo.Codes[i]);
2624 // If this is an 'other' constraint, see if the operand is valid for it.
2625 // For example, on X86 we might have an 'rI' constraint. If the operand
2626 // is an integer in the range [0..31] we want to use I (saving a load
2627 // of a register), otherwise we must use 'r'.
2628 if (CType == TargetLowering::C_Other && Op.getNode()) {
2629 assert(OpInfo.Codes[i].size() == 1 &&
2630 "Unhandled multi-letter 'other' constraint");
2631 std::vector<SDValue> ResultOps;
2632 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2634 if (!ResultOps.empty()) {
2641 // Things with matching constraints can only be registers, per gcc
2642 // documentation. This mainly affects "g" constraints.
2643 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2646 // This constraint letter is more general than the previous one, use it.
2647 int Generality = getConstraintGenerality(CType);
2648 if (Generality > BestGenerality) {
2651 BestGenerality = Generality;
2655 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2656 OpInfo.ConstraintType = BestType;
2659 /// ComputeConstraintToUse - Determines the constraint code and constraint
2660 /// type to use for the specific AsmOperandInfo, setting
2661 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2662 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2664 SelectionDAG *DAG) const {
2665 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2667 // Single-letter constraints ('r') are very common.
2668 if (OpInfo.Codes.size() == 1) {
2669 OpInfo.ConstraintCode = OpInfo.Codes[0];
2670 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2672 ChooseConstraint(OpInfo, *this, Op, DAG);
2675 // 'X' matches anything.
2676 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2677 // Labels and constants are handled elsewhere ('X' is the only thing
2678 // that matches labels). For Functions, the type here is the type of
2679 // the result, which is not what we want to look at; leave them alone.
2680 Value *v = OpInfo.CallOperandVal;
2681 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2682 OpInfo.CallOperandVal = v;
2686 // Otherwise, try to resolve it to something we know about by looking at
2687 // the actual operand type.
2688 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2689 OpInfo.ConstraintCode = Repl;
2690 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2695 /// \brief Given an exact SDIV by a constant, create a multiplication
2696 /// with the multiplicative inverse of the constant.
2697 static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d,
2698 SDLoc dl, SelectionDAG &DAG,
2699 std::vector<SDNode *> &Created) {
2700 assert(d != 0 && "Division by zero!");
2702 // Shift the value upfront if it is even, so the LSB is one.
2703 unsigned ShAmt = d.countTrailingZeros();
2705 // TODO: For UDIV use SRL instead of SRA.
2707 DAG.getConstant(ShAmt, dl, TLI.getShiftAmountTy(Op1.getValueType(),
2708 DAG.getDataLayout()));
2710 Flags.setExact(true);
2711 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags);
2712 Created.push_back(Op1.getNode());
2716 // Calculate the multiplicative inverse, using Newton's method.
2718 while ((t = d*xn) != 1)
2719 xn *= APInt(d.getBitWidth(), 2) - t;
2721 SDValue Op2 = DAG.getConstant(xn, dl, Op1.getValueType());
2722 SDValue Mul = DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2723 Created.push_back(Mul.getNode());
2727 SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2729 std::vector<SDNode *> *Created) const {
2730 AttributeSet Attr = DAG.getMachineFunction().getFunction()->getAttributes();
2731 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2732 if (TLI.isIntDivCheap(N->getValueType(0), Attr))
2733 return SDValue(N,0); // Lower SDIV as SDIV
2737 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2738 /// return a DAG expression to select that will generate the same value by
2739 /// multiplying by a magic number.
2740 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2741 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2742 SelectionDAG &DAG, bool IsAfterLegalization,
2743 std::vector<SDNode *> *Created) const {
2744 assert(Created && "No vector to hold sdiv ops.");
2746 EVT VT = N->getValueType(0);
2749 // Check to see if we can do this.
2750 // FIXME: We should be more aggressive here.
2751 if (!isTypeLegal(VT))
2754 // If the sdiv has an 'exact' bit we can use a simpler lowering.
2755 if (cast<BinaryWithFlagsSDNode>(N)->Flags.hasExact())
2756 return BuildExactSDIV(*this, N->getOperand(0), Divisor, dl, DAG, *Created);
2758 APInt::ms magics = Divisor.magic();
2760 // Multiply the numerator (operand 0) by the magic value
2761 // FIXME: We should support doing a MUL in a wider type
2763 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2764 isOperationLegalOrCustom(ISD::MULHS, VT))
2765 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2766 DAG.getConstant(magics.m, dl, VT));
2767 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2768 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2769 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2771 DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2773 return SDValue(); // No mulhs or equvialent
2774 // If d > 0 and m < 0, add the numerator
2775 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2776 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2777 Created->push_back(Q.getNode());
2779 // If d < 0 and m > 0, subtract the numerator.
2780 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2781 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2782 Created->push_back(Q.getNode());
2784 auto &DL = DAG.getDataLayout();
2785 // Shift right algebraic if shift value is nonzero
2788 ISD::SRA, dl, VT, Q,
2789 DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
2790 Created->push_back(Q.getNode());
2792 // Extract the sign bit and add it to the quotient
2794 DAG.getNode(ISD::SRL, dl, VT, Q,
2795 DAG.getConstant(VT.getScalarSizeInBits() - 1, dl,
2796 getShiftAmountTy(Q.getValueType(), DL)));
2797 Created->push_back(T.getNode());
2798 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2801 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2802 /// return a DAG expression to select that will generate the same value by
2803 /// multiplying by a magic number.
2804 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2805 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2806 SelectionDAG &DAG, bool IsAfterLegalization,
2807 std::vector<SDNode *> *Created) const {
2808 assert(Created && "No vector to hold udiv ops.");
2810 EVT VT = N->getValueType(0);
2812 auto &DL = DAG.getDataLayout();
2814 // Check to see if we can do this.
2815 // FIXME: We should be more aggressive here.
2816 if (!isTypeLegal(VT))
2819 // FIXME: We should use a narrower constant when the upper
2820 // bits are known to be zero.
2821 APInt::mu magics = Divisor.magicu();
2823 SDValue Q = N->getOperand(0);
2825 // If the divisor is even, we can avoid using the expensive fixup by shifting
2826 // the divided value upfront.
2827 if (magics.a != 0 && !Divisor[0]) {
2828 unsigned Shift = Divisor.countTrailingZeros();
2830 ISD::SRL, dl, VT, Q,
2831 DAG.getConstant(Shift, dl, getShiftAmountTy(Q.getValueType(), DL)));
2832 Created->push_back(Q.getNode());
2834 // Get magic number for the shifted divisor.
2835 magics = Divisor.lshr(Shift).magicu(Shift);
2836 assert(magics.a == 0 && "Should use cheap fixup now");
2839 // Multiply the numerator (operand 0) by the magic value
2840 // FIXME: We should support doing a MUL in a wider type
2841 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2842 isOperationLegalOrCustom(ISD::MULHU, VT))
2843 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT));
2844 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2845 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2846 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2847 DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2849 return SDValue(); // No mulhu or equvialent
2851 Created->push_back(Q.getNode());
2853 if (magics.a == 0) {
2854 assert(magics.s < Divisor.getBitWidth() &&
2855 "We shouldn't generate an undefined shift!");
2857 ISD::SRL, dl, VT, Q,
2858 DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
2860 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2861 Created->push_back(NPQ.getNode());
2863 ISD::SRL, dl, VT, NPQ,
2864 DAG.getConstant(1, dl, getShiftAmountTy(NPQ.getValueType(), DL)));
2865 Created->push_back(NPQ.getNode());
2866 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2867 Created->push_back(NPQ.getNode());
2869 ISD::SRL, dl, VT, NPQ,
2870 DAG.getConstant(magics.s - 1, dl,
2871 getShiftAmountTy(NPQ.getValueType(), DL)));
2875 bool TargetLowering::
2876 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2877 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2878 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2879 "be a constant integer");
2886 //===----------------------------------------------------------------------===//
2887 // Legalization Utilities
2888 //===----------------------------------------------------------------------===//
2890 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2891 SelectionDAG &DAG, SDValue LL, SDValue LH,
2892 SDValue RL, SDValue RH) const {
2893 EVT VT = N->getValueType(0);
2896 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2897 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2898 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2899 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2900 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2901 unsigned OuterBitSize = VT.getSizeInBits();
2902 unsigned InnerBitSize = HiLoVT.getSizeInBits();
2903 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2904 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2906 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2907 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2908 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2910 if (!LL.getNode() && !RL.getNode() &&
2911 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2912 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2913 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2919 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2920 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2921 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2922 // The inputs are both zero-extended.
2924 // We can emit a umul_lohi.
2925 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2927 Hi = SDValue(Lo.getNode(), 1);
2931 // We can emit a mulhu+mul.
2932 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2933 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2937 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2938 // The input values are both sign-extended.
2940 // We can emit a smul_lohi.
2941 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2943 Hi = SDValue(Lo.getNode(), 1);
2947 // We can emit a mulhs+mul.
2948 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2949 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2954 if (!LH.getNode() && !RH.getNode() &&
2955 isOperationLegalOrCustom(ISD::SRL, VT) &&
2956 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2957 auto &DL = DAG.getDataLayout();
2958 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2959 SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT, DL));
2960 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2961 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2962 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2963 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2970 // Lo,Hi = umul LHS, RHS.
2971 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2972 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2974 Hi = UMulLOHI.getValue(1);
2975 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2976 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2977 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2978 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2982 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2983 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2984 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2985 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2986 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2987 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2994 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
2995 SelectionDAG &DAG) const {
2996 EVT VT = Node->getOperand(0).getValueType();
2997 EVT NVT = Node->getValueType(0);
2998 SDLoc dl(SDValue(Node, 0));
3000 // FIXME: Only f32 to i64 conversions are supported.
3001 if (VT != MVT::f32 || NVT != MVT::i64)
3004 // Expand f32 -> i64 conversion
3005 // This algorithm comes from compiler-rt's implementation of fixsfdi:
3006 // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
3007 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
3008 VT.getSizeInBits());
3009 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
3010 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
3011 SDValue Bias = DAG.getConstant(127, dl, IntVT);
3012 SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl,
3014 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT);
3015 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
3017 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
3019 auto &DL = DAG.getDataLayout();
3020 SDValue ExponentBits = DAG.getNode(
3021 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
3022 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT, DL)));
3023 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
3025 SDValue Sign = DAG.getNode(
3026 ISD::SRA, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
3027 DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT, DL)));
3028 Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
3030 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
3031 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
3032 DAG.getConstant(0x00800000, dl, IntVT));
3034 R = DAG.getZExtOrTrunc(R, dl, NVT);
3036 R = DAG.getSelectCC(
3037 dl, Exponent, ExponentLoBit,
3038 DAG.getNode(ISD::SHL, dl, NVT, R,
3040 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
3041 dl, getShiftAmountTy(IntVT, DL))),
3042 DAG.getNode(ISD::SRL, dl, NVT, R,
3044 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
3045 dl, getShiftAmountTy(IntVT, DL))),
3048 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
3049 DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
3052 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
3053 DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT);
3057 //===----------------------------------------------------------------------===//
3058 // Implementation of Emulated TLS Model
3059 //===----------------------------------------------------------------------===//
3061 SDValue TargetLowering::LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3062 SelectionDAG &DAG) const {
3063 // Access to address of TLS varialbe xyz is lowered to a function call:
3064 // __emutls_get_address( address of global variable named "__emutls_v.xyz" )
3065 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3066 PointerType *VoidPtrType = Type::getInt8PtrTy(*DAG.getContext());
3071 std::string NameString = ("__emutls_v." + GA->getGlobal()->getName()).str();
3072 Module *VariableModule = const_cast<Module*>(GA->getGlobal()->getParent());
3073 StringRef EmuTlsVarName(NameString);
3074 GlobalVariable *EmuTlsVar = VariableModule->getNamedGlobal(EmuTlsVarName);
3076 EmuTlsVar = dyn_cast_or_null<GlobalVariable>(
3077 VariableModule->getOrInsertGlobal(EmuTlsVarName, VoidPtrType));
3078 Entry.Node = DAG.getGlobalAddress(EmuTlsVar, dl, PtrVT);
3079 Entry.Ty = VoidPtrType;
3080 Args.push_back(Entry);
3082 SDValue EmuTlsGetAddr = DAG.getExternalSymbol("__emutls_get_address", PtrVT);
3084 TargetLowering::CallLoweringInfo CLI(DAG);
3085 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode());
3086 CLI.setCallee(CallingConv::C, VoidPtrType, EmuTlsGetAddr, std::move(Args), 0);
3087 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3089 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
3090 // At last for X86 targets, maybe good for other targets too?
3091 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3092 MFI->setAdjustsStack(true); // Is this only for X86 target?
3093 MFI->setHasCalls(true);
3095 assert((GA->getOffset() == 0) &&
3096 "Emulated TLS must have zero offset in GlobalAddressSDNode");
3097 return CallResult.first;