1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
38 /// NOTE: The TargetMachine owns TLOF.
39 TargetLowering::TargetLowering(const TargetMachine &tm)
40 : TargetLoweringBase(tm) {}
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 SDValue &Chain) const {
50 const Function *F = DAG.getMachineFunction().getFunction();
52 // Conservatively require the attributes of the call to match those of
53 // the return. Ignore noalias because it doesn't affect the call sequence.
54 AttributeSet CallerAttrs = F->getAttributes();
55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56 .removeAttribute(Attribute::NoAlias).hasAttributes())
59 // It's not safe to eliminate the sign / zero extension of the return value.
60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
64 // Check if the only use is a function return node.
65 return isUsedByReturnOnly(Node, Chain);
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
80 Alignment = CS->getParamAlignment(AttrIdx);
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
86 TargetLowering::makeLibCall(SelectionDAG &DAG,
87 RTLIB::Libcall LC, EVT RetVT,
88 const SDValue *Ops, unsigned NumOps,
89 bool isSigned, SDLoc dl,
91 bool isReturnValueUsed) const {
92 TargetLowering::ArgListTy Args;
95 TargetLowering::ArgListEntry Entry;
96 for (unsigned i = 0; i != NumOps; ++i) {
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99 Entry.isSExt = isSigned;
100 Entry.isZExt = !isSigned;
101 Args.push_back(Entry);
103 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
105 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
106 TargetLowering::CallLoweringInfo CLI(DAG);
107 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
108 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
109 .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
110 .setSExtResult(isSigned).setZExtResult(!isSigned);
111 return LowerCallTo(CLI);
115 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
116 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
117 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
118 SDValue &NewLHS, SDValue &NewRHS,
119 ISD::CondCode &CCCode,
121 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
122 && "Unsupported setcc type!");
124 // Expand into one or more soft-fp libcall(s).
125 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
129 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
130 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
134 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
135 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
139 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
140 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
144 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
145 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
149 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
150 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
154 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
155 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
158 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
159 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
162 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
163 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
166 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
167 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
170 // SETONE = SETOLT | SETOGT
171 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
172 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
175 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
176 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
179 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
180 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
183 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
184 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
187 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
188 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
191 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
192 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
194 default: llvm_unreachable("Do not know how to soften this setcc!");
198 // Use the target specific return value for comparions lib calls.
199 EVT RetVT = getCmpLibcallReturnType();
200 SDValue Ops[2] = { NewLHS, NewRHS };
201 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
203 NewRHS = DAG.getConstant(0, RetVT);
204 CCCode = getCmpLibcallCC(LC1);
205 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
206 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
207 getSetCCResultType(*DAG.getContext(), RetVT),
208 NewLHS, NewRHS, DAG.getCondCode(CCCode));
209 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
211 NewLHS = DAG.getNode(ISD::SETCC, dl,
212 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
213 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
214 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
219 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
220 /// current function. The returned value is a member of the
221 /// MachineJumpTableInfo::JTEntryKind enum.
222 unsigned TargetLowering::getJumpTableEncoding() const {
223 // In non-pic modes, just use the address of a block.
224 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
225 return MachineJumpTableInfo::EK_BlockAddress;
227 // In PIC mode, if the target supports a GPRel32 directive, use it.
228 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
229 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
231 // Otherwise, use a label difference.
232 return MachineJumpTableInfo::EK_LabelDifference32;
235 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
236 SelectionDAG &DAG) const {
237 // If our PIC model is GP relative, use the global offset table as the base.
238 unsigned JTEncoding = getJumpTableEncoding();
240 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
241 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
242 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
247 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
248 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
251 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
252 unsigned JTI,MCContext &Ctx) const{
253 // The normal PIC reloc base is the label at the start of the jump table.
254 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
258 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
259 // Assume that everything is safe in static mode.
260 if (getTargetMachine().getRelocationModel() == Reloc::Static)
263 // In dynamic-no-pic mode, assume that known defined values are safe.
264 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
266 !GA->getGlobal()->isDeclaration() &&
267 !GA->getGlobal()->isWeakForLinker())
270 // Otherwise assume nothing is safe.
274 //===----------------------------------------------------------------------===//
275 // Optimization Methods
276 //===----------------------------------------------------------------------===//
278 /// ShrinkDemandedConstant - Check to see if the specified operand of the
279 /// specified instruction is a constant integer. If so, check to see if there
280 /// are any bits set in the constant that are not demanded. If so, shrink the
281 /// constant and return true.
282 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
283 const APInt &Demanded) {
286 // FIXME: ISD::SELECT, ISD::SELECT_CC
287 switch (Op.getOpcode()) {
292 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
293 if (!C) return false;
295 if (Op.getOpcode() == ISD::XOR &&
296 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
299 // if we can expand it to have all bits set, do it
300 if (C->getAPIntValue().intersects(~Demanded)) {
301 EVT VT = Op.getValueType();
302 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
303 DAG.getConstant(Demanded &
306 return CombineTo(Op, New);
316 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
317 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
318 /// cast, but it could be generalized for targets with other types of
319 /// implicit widening casts.
321 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
323 const APInt &Demanded,
325 assert(Op.getNumOperands() == 2 &&
326 "ShrinkDemandedOp only supports binary operators!");
327 assert(Op.getNode()->getNumValues() == 1 &&
328 "ShrinkDemandedOp only supports nodes with one result!");
330 // Early return, as this function cannot handle vector types.
331 if (Op.getValueType().isVector())
334 // Don't do this if the node has another user, which may require the
336 if (!Op.getNode()->hasOneUse())
339 // Search for the smallest integer type with free casts to and from
340 // Op's type. For expedience, just check power-of-2 integer types.
341 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
342 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
343 unsigned SmallVTBits = DemandedSize;
344 if (!isPowerOf2_32(SmallVTBits))
345 SmallVTBits = NextPowerOf2(SmallVTBits);
346 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
347 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
348 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
349 TLI.isZExtFree(SmallVT, Op.getValueType())) {
350 // We found a type with free casts.
351 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
352 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
353 Op.getNode()->getOperand(0)),
354 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
355 Op.getNode()->getOperand(1)));
356 bool NeedZext = DemandedSize > SmallVTBits;
357 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
358 dl, Op.getValueType(), X);
359 return CombineTo(Op, Z);
365 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
366 /// DemandedMask bits of the result of Op are ever used downstream. If we can
367 /// use this information to simplify Op, create a new simplified DAG node and
368 /// return true, returning the original and new nodes in Old and New. Otherwise,
369 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
370 /// the expression (used to simplify the caller). The KnownZero/One bits may
371 /// only be accurate for those bits in the DemandedMask.
372 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
373 const APInt &DemandedMask,
376 TargetLoweringOpt &TLO,
377 unsigned Depth) const {
378 unsigned BitWidth = DemandedMask.getBitWidth();
379 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
380 "Mask size mismatches value type size!");
381 APInt NewMask = DemandedMask;
384 // Don't know anything.
385 KnownZero = KnownOne = APInt(BitWidth, 0);
387 // Other users may use these bits.
388 if (!Op.getNode()->hasOneUse()) {
390 // If not at the root, Just compute the KnownZero/KnownOne bits to
391 // simplify things downstream.
392 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
395 // If this is the root being simplified, allow it to have multiple uses,
396 // just set the NewMask to all bits.
397 NewMask = APInt::getAllOnesValue(BitWidth);
398 } else if (DemandedMask == 0) {
399 // Not demanding any bits from Op.
400 if (Op.getOpcode() != ISD::UNDEF)
401 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
403 } else if (Depth == 6) { // Limit search depth.
407 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
408 switch (Op.getOpcode()) {
410 // We know all of the bits for a constant!
411 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
412 KnownZero = ~KnownOne;
413 return false; // Don't fall through, will infinitely loop.
415 // If the RHS is a constant, check to see if the LHS would be zero without
416 // using the bits from the RHS. Below, we use knowledge about the RHS to
417 // simplify the LHS, here we're using information from the LHS to simplify
419 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
420 APInt LHSZero, LHSOne;
421 // Do not increment Depth here; that can cause an infinite loop.
422 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
423 // If the LHS already has zeros where RHSC does, this and is dead.
424 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
425 return TLO.CombineTo(Op, Op.getOperand(0));
426 // If any of the set bits in the RHS are known zero on the LHS, shrink
428 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
432 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
433 KnownOne, TLO, Depth+1))
435 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
436 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
437 KnownZero2, KnownOne2, TLO, Depth+1))
439 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
441 // If all of the demanded bits are known one on one side, return the other.
442 // These bits cannot contribute to the result of the 'and'.
443 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
444 return TLO.CombineTo(Op, Op.getOperand(0));
445 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
446 return TLO.CombineTo(Op, Op.getOperand(1));
447 // If all of the demanded bits in the inputs are known zeros, return zero.
448 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
449 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
450 // If the RHS is a constant, see if we can simplify it.
451 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
453 // If the operation can be done in a smaller type, do so.
454 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
457 // Output known-1 bits are only known if set in both the LHS & RHS.
458 KnownOne &= KnownOne2;
459 // Output known-0 are known to be clear if zero in either the LHS | RHS.
460 KnownZero |= KnownZero2;
463 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
464 KnownOne, TLO, Depth+1))
466 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
467 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
468 KnownZero2, KnownOne2, TLO, Depth+1))
470 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
472 // If all of the demanded bits are known zero on one side, return the other.
473 // These bits cannot contribute to the result of the 'or'.
474 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
475 return TLO.CombineTo(Op, Op.getOperand(0));
476 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
477 return TLO.CombineTo(Op, Op.getOperand(1));
478 // If all of the potentially set bits on one side are known to be set on
479 // the other side, just use the 'other' side.
480 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
481 return TLO.CombineTo(Op, Op.getOperand(0));
482 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
483 return TLO.CombineTo(Op, Op.getOperand(1));
484 // If the RHS is a constant, see if we can simplify it.
485 if (TLO.ShrinkDemandedConstant(Op, NewMask))
487 // If the operation can be done in a smaller type, do so.
488 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
491 // Output known-0 bits are only known if clear in both the LHS & RHS.
492 KnownZero &= KnownZero2;
493 // Output known-1 are known to be set if set in either the LHS | RHS.
494 KnownOne |= KnownOne2;
497 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
498 KnownOne, TLO, Depth+1))
500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
501 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
502 KnownOne2, TLO, Depth+1))
504 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
506 // If all of the demanded bits are known zero on one side, return the other.
507 // These bits cannot contribute to the result of the 'xor'.
508 if ((KnownZero & NewMask) == NewMask)
509 return TLO.CombineTo(Op, Op.getOperand(0));
510 if ((KnownZero2 & NewMask) == NewMask)
511 return TLO.CombineTo(Op, Op.getOperand(1));
512 // If the operation can be done in a smaller type, do so.
513 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
516 // If all of the unknown bits are known to be zero on one side or the other
517 // (but not both) turn this into an *inclusive* or.
518 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
519 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
524 // Output known-0 bits are known if clear or set in both the LHS & RHS.
525 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
526 // Output known-1 are known to be set if set in only one of the LHS, RHS.
527 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
529 // If all of the demanded bits on one side are known, and all of the set
530 // bits on that side are also known to be set on the other side, turn this
531 // into an AND, as we know the bits will be cleared.
532 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
533 // NB: it is okay if more bits are known than are requested
534 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
535 if (KnownOne == KnownOne2) { // set bits are the same on both sides
536 EVT VT = Op.getValueType();
537 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
538 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
539 Op.getOperand(0), ANDC));
543 // If the RHS is a constant, see if we can simplify it.
544 // for XOR, we prefer to force bits to 1 if they will make a -1.
545 // if we can't force bits, try to shrink constant
546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
547 APInt Expanded = C->getAPIntValue() | (~NewMask);
548 // if we can expand it to have all bits set, do it
549 if (Expanded.isAllOnesValue()) {
550 if (Expanded != C->getAPIntValue()) {
551 EVT VT = Op.getValueType();
552 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
553 TLO.DAG.getConstant(Expanded, VT));
554 return TLO.CombineTo(Op, New);
556 // if it already has all the bits set, nothing to change
557 // but don't shrink either!
558 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
563 KnownZero = KnownZeroOut;
564 KnownOne = KnownOneOut;
567 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
568 KnownOne, TLO, Depth+1))
570 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
571 KnownOne2, TLO, Depth+1))
573 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
574 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
576 // If the operands are constants, see if we can simplify them.
577 if (TLO.ShrinkDemandedConstant(Op, NewMask))
580 // Only known if known in both the LHS and RHS.
581 KnownOne &= KnownOne2;
582 KnownZero &= KnownZero2;
585 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
586 KnownOne, TLO, Depth+1))
588 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
589 KnownOne2, TLO, Depth+1))
591 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
592 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
594 // If the operands are constants, see if we can simplify them.
595 if (TLO.ShrinkDemandedConstant(Op, NewMask))
598 // Only known if known in both the LHS and RHS.
599 KnownOne &= KnownOne2;
600 KnownZero &= KnownZero2;
603 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
604 unsigned ShAmt = SA->getZExtValue();
605 SDValue InOp = Op.getOperand(0);
607 // If the shift count is an invalid immediate, don't do anything.
608 if (ShAmt >= BitWidth)
611 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
612 // single shift. We can do this if the bottom bits (which are shifted
613 // out) are never demanded.
614 if (InOp.getOpcode() == ISD::SRL &&
615 isa<ConstantSDNode>(InOp.getOperand(1))) {
616 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
617 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
618 unsigned Opc = ISD::SHL;
626 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
627 EVT VT = Op.getValueType();
628 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
629 InOp.getOperand(0), NewSA));
633 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
634 KnownZero, KnownOne, TLO, Depth+1))
637 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
638 // are not demanded. This will likely allow the anyext to be folded away.
639 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
640 SDValue InnerOp = InOp.getNode()->getOperand(0);
641 EVT InnerVT = InnerOp.getValueType();
642 unsigned InnerBits = InnerVT.getSizeInBits();
643 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
644 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
645 EVT ShTy = getShiftAmountTy(InnerVT);
646 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
649 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
650 TLO.DAG.getConstant(ShAmt, ShTy));
653 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
656 // Repeat the SHL optimization above in cases where an extension
657 // intervenes: (shl (anyext (shr x, c1)), c2) to
658 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
659 // aren't demanded (as above) and that the shifted upper c1 bits of
660 // x aren't demanded.
661 if (InOp.hasOneUse() &&
662 InnerOp.getOpcode() == ISD::SRL &&
663 InnerOp.hasOneUse() &&
664 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
665 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
667 if (InnerShAmt < ShAmt &&
668 InnerShAmt < InnerBits &&
669 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
670 NewMask.trunc(ShAmt) == 0) {
672 TLO.DAG.getConstant(ShAmt - InnerShAmt,
673 Op.getOperand(1).getValueType());
674 EVT VT = Op.getValueType();
675 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
676 InnerOp.getOperand(0));
677 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
683 KnownZero <<= SA->getZExtValue();
684 KnownOne <<= SA->getZExtValue();
685 // low bits known zero.
686 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
690 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
691 EVT VT = Op.getValueType();
692 unsigned ShAmt = SA->getZExtValue();
693 unsigned VTSize = VT.getSizeInBits();
694 SDValue InOp = Op.getOperand(0);
696 // If the shift count is an invalid immediate, don't do anything.
697 if (ShAmt >= BitWidth)
700 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
701 // single shift. We can do this if the top bits (which are shifted out)
702 // are never demanded.
703 if (InOp.getOpcode() == ISD::SHL &&
704 isa<ConstantSDNode>(InOp.getOperand(1))) {
705 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
706 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
707 unsigned Opc = ISD::SRL;
715 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
716 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
717 InOp.getOperand(0), NewSA));
721 // Compute the new bits that are at the top now.
722 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
723 KnownZero, KnownOne, TLO, Depth+1))
725 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
726 KnownZero = KnownZero.lshr(ShAmt);
727 KnownOne = KnownOne.lshr(ShAmt);
729 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
730 KnownZero |= HighBits; // High bits known zero.
734 // If this is an arithmetic shift right and only the low-bit is set, we can
735 // always convert this into a logical shr, even if the shift amount is
736 // variable. The low bit of the shift cannot be an input sign bit unless
737 // the shift amount is >= the size of the datatype, which is undefined.
739 return TLO.CombineTo(Op,
740 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
741 Op.getOperand(0), Op.getOperand(1)));
743 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
744 EVT VT = Op.getValueType();
745 unsigned ShAmt = SA->getZExtValue();
747 // If the shift count is an invalid immediate, don't do anything.
748 if (ShAmt >= BitWidth)
751 APInt InDemandedMask = (NewMask << ShAmt);
753 // If any of the demanded bits are produced by the sign extension, we also
754 // demand the input sign bit.
755 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
756 if (HighBits.intersects(NewMask))
757 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
759 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
760 KnownZero, KnownOne, TLO, Depth+1))
762 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
763 KnownZero = KnownZero.lshr(ShAmt);
764 KnownOne = KnownOne.lshr(ShAmt);
766 // Handle the sign bit, adjusted to where it is now in the mask.
767 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
769 // If the input sign bit is known to be zero, or if none of the top bits
770 // are demanded, turn this into an unsigned shift right.
771 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
772 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
776 int Log2 = NewMask.exactLogBase2();
778 // The bit must come from the sign.
780 TLO.DAG.getConstant(BitWidth - 1 - Log2,
781 Op.getOperand(1).getValueType());
782 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
783 Op.getOperand(0), NewSA));
786 if (KnownOne.intersects(SignBit))
787 // New bits are known one.
788 KnownOne |= HighBits;
791 case ISD::SIGN_EXTEND_INREG: {
792 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
794 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
795 // If we only care about the highest bit, don't bother shifting right.
796 if (MsbMask == NewMask) {
797 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
798 SDValue InOp = Op.getOperand(0);
799 unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits();
800 bool AlreadySignExtended =
801 TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
802 // However if the input is already sign extended we expect the sign
803 // extension to be dropped altogether later and do not simplify.
804 if (!AlreadySignExtended) {
805 // Compute the correct shift amount type, which must be getShiftAmountTy
806 // for scalar types after legalization.
807 EVT ShiftAmtTy = Op.getValueType();
808 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
809 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
811 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
812 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
813 Op.getValueType(), InOp,
818 // Sign extension. Compute the demanded bits in the result that are not
819 // present in the input.
821 APInt::getHighBitsSet(BitWidth,
822 BitWidth - ExVT.getScalarType().getSizeInBits());
824 // If none of the extended bits are demanded, eliminate the sextinreg.
825 if ((NewBits & NewMask) == 0)
826 return TLO.CombineTo(Op, Op.getOperand(0));
829 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
830 APInt InputDemandedBits =
831 APInt::getLowBitsSet(BitWidth,
832 ExVT.getScalarType().getSizeInBits()) &
835 // Since the sign extended bits are demanded, we know that the sign
837 InputDemandedBits |= InSignBit;
839 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
840 KnownZero, KnownOne, TLO, Depth+1))
842 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
844 // If the sign bit of the input is known set or clear, then we know the
845 // top bits of the result.
847 // If the input sign bit is known zero, convert this into a zero extension.
848 if (KnownZero.intersects(InSignBit))
849 return TLO.CombineTo(Op,
850 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
852 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
854 KnownZero &= ~NewBits;
855 } else { // Input sign bit unknown
856 KnownZero &= ~NewBits;
857 KnownOne &= ~NewBits;
861 case ISD::BUILD_PAIR: {
862 EVT HalfVT = Op.getOperand(0).getValueType();
863 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
865 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
866 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
868 APInt KnownZeroLo, KnownOneLo;
869 APInt KnownZeroHi, KnownOneHi;
871 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
872 KnownOneLo, TLO, Depth + 1))
875 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
876 KnownOneHi, TLO, Depth + 1))
879 KnownZero = KnownZeroLo.zext(BitWidth) |
880 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
882 KnownOne = KnownOneLo.zext(BitWidth) |
883 KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
886 case ISD::ZERO_EXTEND: {
887 unsigned OperandBitWidth =
888 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
889 APInt InMask = NewMask.trunc(OperandBitWidth);
891 // If none of the top bits are demanded, convert this into an any_extend.
893 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
894 if (!NewBits.intersects(NewMask))
895 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
899 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
900 KnownZero, KnownOne, TLO, Depth+1))
902 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
903 KnownZero = KnownZero.zext(BitWidth);
904 KnownOne = KnownOne.zext(BitWidth);
905 KnownZero |= NewBits;
908 case ISD::SIGN_EXTEND: {
909 EVT InVT = Op.getOperand(0).getValueType();
910 unsigned InBits = InVT.getScalarType().getSizeInBits();
911 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
912 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
913 APInt NewBits = ~InMask & NewMask;
915 // If none of the top bits are demanded, convert this into an any_extend.
917 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
921 // Since some of the sign extended bits are demanded, we know that the sign
923 APInt InDemandedBits = InMask & NewMask;
924 InDemandedBits |= InSignBit;
925 InDemandedBits = InDemandedBits.trunc(InBits);
927 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
928 KnownOne, TLO, Depth+1))
930 KnownZero = KnownZero.zext(BitWidth);
931 KnownOne = KnownOne.zext(BitWidth);
933 // If the sign bit is known zero, convert this to a zero extend.
934 if (KnownZero.intersects(InSignBit))
935 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
939 // If the sign bit is known one, the top bits match.
940 if (KnownOne.intersects(InSignBit)) {
942 assert((KnownZero & NewBits) == 0);
943 } else { // Otherwise, top bits aren't known.
944 assert((KnownOne & NewBits) == 0);
945 assert((KnownZero & NewBits) == 0);
949 case ISD::ANY_EXTEND: {
950 unsigned OperandBitWidth =
951 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
952 APInt InMask = NewMask.trunc(OperandBitWidth);
953 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
954 KnownZero, KnownOne, TLO, Depth+1))
956 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
957 KnownZero = KnownZero.zext(BitWidth);
958 KnownOne = KnownOne.zext(BitWidth);
961 case ISD::TRUNCATE: {
962 // Simplify the input, using demanded bit information, and compute the known
963 // zero/one bits live out.
964 unsigned OperandBitWidth =
965 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
966 APInt TruncMask = NewMask.zext(OperandBitWidth);
967 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
968 KnownZero, KnownOne, TLO, Depth+1))
970 KnownZero = KnownZero.trunc(BitWidth);
971 KnownOne = KnownOne.trunc(BitWidth);
973 // If the input is only used by this truncate, see if we can shrink it based
974 // on the known demanded bits.
975 if (Op.getOperand(0).getNode()->hasOneUse()) {
976 SDValue In = Op.getOperand(0);
977 switch (In.getOpcode()) {
980 // Shrink SRL by a constant if none of the high bits shifted in are
982 if (TLO.LegalTypes() &&
983 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
984 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
987 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
990 SDValue Shift = In.getOperand(1);
991 if (TLO.LegalTypes()) {
992 uint64_t ShVal = ShAmt->getZExtValue();
994 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
997 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
998 OperandBitWidth - BitWidth);
999 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1001 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1002 // None of the shifted in bits are needed. Add a truncate of the
1003 // shift input, then shift it.
1004 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1007 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1016 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1019 case ISD::AssertZext: {
1020 // AssertZext demands all of the high bits, plus any of the low bits
1021 // demanded by its users.
1022 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1023 APInt InMask = APInt::getLowBitsSet(BitWidth,
1024 VT.getSizeInBits());
1025 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1026 KnownZero, KnownOne, TLO, Depth+1))
1028 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1030 KnownZero |= ~InMask & NewMask;
1034 // If this is an FP->Int bitcast and if the sign bit is the only
1035 // thing demanded, turn this into a FGETSIGN.
1036 if (!TLO.LegalOperations() &&
1037 !Op.getValueType().isVector() &&
1038 !Op.getOperand(0).getValueType().isVector() &&
1039 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1040 Op.getOperand(0).getValueType().isFloatingPoint()) {
1041 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1042 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1043 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1044 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1045 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1046 // place. We expect the SHL to be eliminated by other optimizations.
1047 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1048 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1049 if (!OpVTLegal && OpVTSizeInBits > 32)
1050 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1051 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1052 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1053 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1062 // Add, Sub, and Mul don't demand any bits in positions beyond that
1063 // of the highest bit demanded of them.
1064 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1065 BitWidth - NewMask.countLeadingZeros());
1066 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1067 KnownOne2, TLO, Depth+1))
1069 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1070 KnownOne2, TLO, Depth+1))
1072 // See if the operation should be performed at a smaller bit width.
1073 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1078 // Just use computeKnownBits to compute output bits.
1079 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1083 // If we know the value of all of the demanded bits, return this as a
1085 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1086 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1091 /// computeKnownBitsForTargetNode - Determine which of the bits specified
1092 /// in Mask are known to be either zero or one and return them in the
1093 /// KnownZero/KnownOne bitsets.
1094 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1097 const SelectionDAG &DAG,
1098 unsigned Depth) const {
1099 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1100 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1101 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1102 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1103 "Should use MaskedValueIsZero if you don't know whether Op"
1104 " is a target node!");
1105 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1108 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1109 /// targets that want to expose additional information about sign bits to the
1111 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1112 const SelectionDAG &,
1113 unsigned Depth) const {
1114 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1115 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1116 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1117 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1118 "Should use ComputeNumSignBits if you don't know whether Op"
1119 " is a target node!");
1123 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1124 /// one bit set. This differs from computeKnownBits in that it doesn't need to
1125 /// determine which bit is set.
1127 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1128 // A left-shift of a constant one will have exactly one bit set, because
1129 // shifting the bit off the end is undefined.
1130 if (Val.getOpcode() == ISD::SHL)
1131 if (ConstantSDNode *C =
1132 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1133 if (C->getAPIntValue() == 1)
1136 // Similarly, a right-shift of a constant sign-bit will have exactly
1138 if (Val.getOpcode() == ISD::SRL)
1139 if (ConstantSDNode *C =
1140 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1141 if (C->getAPIntValue().isSignBit())
1144 // More could be done here, though the above checks are enough
1145 // to handle some common cases.
1147 // Fall back to computeKnownBits to catch other known cases.
1148 EVT OpVT = Val.getValueType();
1149 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1150 APInt KnownZero, KnownOne;
1151 DAG.computeKnownBits(Val, KnownZero, KnownOne);
1152 return (KnownZero.countPopulation() == BitWidth - 1) &&
1153 (KnownOne.countPopulation() == 1);
1156 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1160 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1162 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1166 BitVector UndefElements;
1167 CN = BV->getConstantSplatNode(&UndefElements);
1168 // Only interested in constant splats, and we don't try to handle undef
1169 // elements in identifying boolean constants.
1170 if (!CN || UndefElements.none())
1174 switch (getBooleanContents(N->getValueType(0))) {
1175 case UndefinedBooleanContent:
1176 return CN->getAPIntValue()[0];
1177 case ZeroOrOneBooleanContent:
1179 case ZeroOrNegativeOneBooleanContent:
1180 return CN->isAllOnesValue();
1183 llvm_unreachable("Invalid boolean contents");
1186 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1190 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1192 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1196 BitVector UndefElements;
1197 CN = BV->getConstantSplatNode(&UndefElements);
1198 // Only interested in constant splats, and we don't try to handle undef
1199 // elements in identifying boolean constants.
1200 if (!CN || UndefElements.none())
1204 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
1205 return !CN->getAPIntValue()[0];
1207 return CN->isNullValue();
1210 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1211 /// and cc. If it is unable to simplify it, return a null SDValue.
1213 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1214 ISD::CondCode Cond, bool foldBooleans,
1215 DAGCombinerInfo &DCI, SDLoc dl) const {
1216 SelectionDAG &DAG = DCI.DAG;
1218 // These setcc operations always fold.
1222 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1224 case ISD::SETTRUE2: {
1225 TargetLowering::BooleanContent Cnt =
1226 getBooleanContents(N0->getValueType(0));
1227 return DAG.getConstant(
1228 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1232 // Ensure that the constant occurs on the RHS, and fold constant
1234 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1235 if (isa<ConstantSDNode>(N0.getNode()) &&
1236 (DCI.isBeforeLegalizeOps() ||
1237 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1238 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1240 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1241 const APInt &C1 = N1C->getAPIntValue();
1243 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1244 // equality comparison, then we're just comparing whether X itself is
1246 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1247 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1248 N0.getOperand(1).getOpcode() == ISD::Constant) {
1250 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1251 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1252 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1253 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1254 // (srl (ctlz x), 5) == 0 -> X != 0
1255 // (srl (ctlz x), 5) != 1 -> X != 0
1258 // (srl (ctlz x), 5) != 0 -> X == 0
1259 // (srl (ctlz x), 5) == 1 -> X == 0
1262 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1263 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1269 // Look through truncs that don't change the value of a ctpop.
1270 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1271 CTPOP = N0.getOperand(0);
1273 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1274 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1275 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1276 EVT CTVT = CTPOP.getValueType();
1277 SDValue CTOp = CTPOP.getOperand(0);
1279 // (ctpop x) u< 2 -> (x & x-1) == 0
1280 // (ctpop x) u> 1 -> (x & x-1) != 0
1281 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1282 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1283 DAG.getConstant(1, CTVT));
1284 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1285 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1286 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1289 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1292 // (zext x) == C --> x == (trunc C)
1293 // (sext x) == C --> x == (trunc C)
1294 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1295 DCI.isBeforeLegalize() && N0->hasOneUse()) {
1296 unsigned MinBits = N0.getValueSizeInBits();
1298 bool Signed = false;
1299 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1301 MinBits = N0->getOperand(0).getValueSizeInBits();
1302 PreExt = N0->getOperand(0);
1303 } else if (N0->getOpcode() == ISD::AND) {
1304 // DAGCombine turns costly ZExts into ANDs
1305 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1306 if ((C->getAPIntValue()+1).isPowerOf2()) {
1307 MinBits = C->getAPIntValue().countTrailingOnes();
1308 PreExt = N0->getOperand(0);
1310 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
1312 MinBits = N0->getOperand(0).getValueSizeInBits();
1313 PreExt = N0->getOperand(0);
1315 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1316 // ZEXTLOAD / SEXTLOAD
1317 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1318 MinBits = LN0->getMemoryVT().getSizeInBits();
1320 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
1322 MinBits = LN0->getMemoryVT().getSizeInBits();
1327 // Figure out how many bits we need to preserve this constant.
1328 unsigned ReqdBits = Signed ?
1329 C1.getBitWidth() - C1.getNumSignBits() + 1 :
1332 // Make sure we're not losing bits from the constant.
1334 MinBits < C1.getBitWidth() &&
1335 MinBits >= ReqdBits) {
1336 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1337 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1338 // Will get folded away.
1339 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
1340 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1341 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1346 // If the LHS is '(and load, const)', the RHS is 0,
1347 // the test is for equality or unsigned, and all 1 bits of the const are
1348 // in the same partial word, see if we can shorten the load.
1349 if (DCI.isBeforeLegalize() &&
1350 !ISD::isSignedIntSetCC(Cond) &&
1351 N0.getOpcode() == ISD::AND && C1 == 0 &&
1352 N0.getNode()->hasOneUse() &&
1353 isa<LoadSDNode>(N0.getOperand(0)) &&
1354 N0.getOperand(0).getNode()->hasOneUse() &&
1355 isa<ConstantSDNode>(N0.getOperand(1))) {
1356 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1358 unsigned bestWidth = 0, bestOffset = 0;
1359 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1360 unsigned origWidth = N0.getValueType().getSizeInBits();
1361 unsigned maskWidth = origWidth;
1362 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1363 // 8 bits, but have to be careful...
1364 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1365 origWidth = Lod->getMemoryVT().getSizeInBits();
1367 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1368 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1369 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1370 for (unsigned offset=0; offset<origWidth/width; offset++) {
1371 if ((newMask & Mask) == Mask) {
1372 if (!getDataLayout()->isLittleEndian())
1373 bestOffset = (origWidth/width - offset - 1) * (width/8);
1375 bestOffset = (uint64_t)offset * (width/8);
1376 bestMask = Mask.lshr(offset * (width/8) * 8);
1380 newMask = newMask << width;
1385 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1386 if (newVT.isRound()) {
1387 EVT PtrType = Lod->getOperand(1).getValueType();
1388 SDValue Ptr = Lod->getBasePtr();
1389 if (bestOffset != 0)
1390 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1391 DAG.getConstant(bestOffset, PtrType));
1392 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1393 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1394 Lod->getPointerInfo().getWithOffset(bestOffset),
1395 false, false, false, NewAlign);
1396 return DAG.getSetCC(dl, VT,
1397 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1398 DAG.getConstant(bestMask.trunc(bestWidth),
1400 DAG.getConstant(0LL, newVT), Cond);
1405 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1406 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1407 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1409 // If the comparison constant has bits in the upper part, the
1410 // zero-extended value could never match.
1411 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1412 C1.getBitWidth() - InSize))) {
1416 case ISD::SETEQ: return DAG.getConstant(0, VT);
1419 case ISD::SETNE: return DAG.getConstant(1, VT);
1422 // True if the sign bit of C1 is set.
1423 return DAG.getConstant(C1.isNegative(), VT);
1426 // True if the sign bit of C1 isn't set.
1427 return DAG.getConstant(C1.isNonNegative(), VT);
1433 // Otherwise, we can perform the comparison with the low bits.
1441 EVT newVT = N0.getOperand(0).getValueType();
1442 if (DCI.isBeforeLegalizeOps() ||
1443 (isOperationLegal(ISD::SETCC, newVT) &&
1444 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1445 EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1446 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
1448 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1450 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1455 break; // todo, be more careful with signed comparisons
1457 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1458 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1459 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1460 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1461 EVT ExtDstTy = N0.getValueType();
1462 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1464 // If the constant doesn't fit into the number of bits for the source of
1465 // the sign extension, it is impossible for both sides to be equal.
1466 if (C1.getMinSignedBits() > ExtSrcTyBits)
1467 return DAG.getConstant(Cond == ISD::SETNE, VT);
1470 EVT Op0Ty = N0.getOperand(0).getValueType();
1471 if (Op0Ty == ExtSrcTy) {
1472 ZextOp = N0.getOperand(0);
1474 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1475 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1476 DAG.getConstant(Imm, Op0Ty));
1478 if (!DCI.isCalledByLegalizer())
1479 DCI.AddToWorklist(ZextOp.getNode());
1480 // Otherwise, make this a use of a zext.
1481 return DAG.getSetCC(dl, VT, ZextOp,
1482 DAG.getConstant(C1 & APInt::getLowBitsSet(
1487 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1488 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1489 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1490 if (N0.getOpcode() == ISD::SETCC &&
1491 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1492 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1494 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1495 // Invert the condition.
1496 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1497 CC = ISD::getSetCCInverse(CC,
1498 N0.getOperand(0).getValueType().isInteger());
1499 if (DCI.isBeforeLegalizeOps() ||
1500 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1501 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1504 if ((N0.getOpcode() == ISD::XOR ||
1505 (N0.getOpcode() == ISD::AND &&
1506 N0.getOperand(0).getOpcode() == ISD::XOR &&
1507 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1508 isa<ConstantSDNode>(N0.getOperand(1)) &&
1509 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1510 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1511 // can only do this if the top bits are known zero.
1512 unsigned BitWidth = N0.getValueSizeInBits();
1513 if (DAG.MaskedValueIsZero(N0,
1514 APInt::getHighBitsSet(BitWidth,
1516 // Okay, get the un-inverted input value.
1518 if (N0.getOpcode() == ISD::XOR)
1519 Val = N0.getOperand(0);
1521 assert(N0.getOpcode() == ISD::AND &&
1522 N0.getOperand(0).getOpcode() == ISD::XOR);
1523 // ((X^1)&1)^1 -> X & 1
1524 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1525 N0.getOperand(0).getOperand(0),
1529 return DAG.getSetCC(dl, VT, Val, N1,
1530 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1532 } else if (N1C->getAPIntValue() == 1 &&
1534 getBooleanContents(N0->getValueType(0)) ==
1535 ZeroOrOneBooleanContent)) {
1537 if (Op0.getOpcode() == ISD::TRUNCATE)
1538 Op0 = Op0.getOperand(0);
1540 if ((Op0.getOpcode() == ISD::XOR) &&
1541 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1542 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1543 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1544 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1545 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1548 if (Op0.getOpcode() == ISD::AND &&
1549 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1550 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1551 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1552 if (Op0.getValueType().bitsGT(VT))
1553 Op0 = DAG.getNode(ISD::AND, dl, VT,
1554 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1555 DAG.getConstant(1, VT));
1556 else if (Op0.getValueType().bitsLT(VT))
1557 Op0 = DAG.getNode(ISD::AND, dl, VT,
1558 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1559 DAG.getConstant(1, VT));
1561 return DAG.getSetCC(dl, VT, Op0,
1562 DAG.getConstant(0, Op0.getValueType()),
1563 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1565 if (Op0.getOpcode() == ISD::AssertZext &&
1566 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1567 return DAG.getSetCC(dl, VT, Op0,
1568 DAG.getConstant(0, Op0.getValueType()),
1569 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1573 APInt MinVal, MaxVal;
1574 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1575 if (ISD::isSignedIntSetCC(Cond)) {
1576 MinVal = APInt::getSignedMinValue(OperandBitSize);
1577 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1579 MinVal = APInt::getMinValue(OperandBitSize);
1580 MaxVal = APInt::getMaxValue(OperandBitSize);
1583 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1584 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1585 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1586 // X >= C0 --> X > (C0 - 1)
1588 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1589 if ((DCI.isBeforeLegalizeOps() ||
1590 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1591 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1592 isLegalICmpImmediate(C.getSExtValue())))) {
1593 return DAG.getSetCC(dl, VT, N0,
1594 DAG.getConstant(C, N1.getValueType()),
1599 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1600 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1601 // X <= C0 --> X < (C0 + 1)
1603 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1604 if ((DCI.isBeforeLegalizeOps() ||
1605 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1606 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1607 isLegalICmpImmediate(C.getSExtValue())))) {
1608 return DAG.getSetCC(dl, VT, N0,
1609 DAG.getConstant(C, N1.getValueType()),
1614 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1615 return DAG.getConstant(0, VT); // X < MIN --> false
1616 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1617 return DAG.getConstant(1, VT); // X >= MIN --> true
1618 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1619 return DAG.getConstant(0, VT); // X > MAX --> false
1620 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1621 return DAG.getConstant(1, VT); // X <= MAX --> true
1623 // Canonicalize setgt X, Min --> setne X, Min
1624 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1625 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1626 // Canonicalize setlt X, Max --> setne X, Max
1627 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1628 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1630 // If we have setult X, 1, turn it into seteq X, 0
1631 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1632 return DAG.getSetCC(dl, VT, N0,
1633 DAG.getConstant(MinVal, N0.getValueType()),
1635 // If we have setugt X, Max-1, turn it into seteq X, Max
1636 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1637 return DAG.getSetCC(dl, VT, N0,
1638 DAG.getConstant(MaxVal, N0.getValueType()),
1641 // If we have "setcc X, C0", check to see if we can shrink the immediate
1644 // SETUGT X, SINTMAX -> SETLT X, 0
1645 if (Cond == ISD::SETUGT &&
1646 C1 == APInt::getSignedMaxValue(OperandBitSize))
1647 return DAG.getSetCC(dl, VT, N0,
1648 DAG.getConstant(0, N1.getValueType()),
1651 // SETULT X, SINTMIN -> SETGT X, -1
1652 if (Cond == ISD::SETULT &&
1653 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1654 SDValue ConstMinusOne =
1655 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1657 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1660 // Fold bit comparisons when we can.
1661 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1662 (VT == N0.getValueType() ||
1663 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1664 N0.getOpcode() == ISD::AND)
1665 if (ConstantSDNode *AndRHS =
1666 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1667 EVT ShiftTy = DCI.isBeforeLegalize() ?
1668 getPointerTy() : getShiftAmountTy(N0.getValueType());
1669 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1670 // Perform the xform if the AND RHS is a single bit.
1671 if (AndRHS->getAPIntValue().isPowerOf2()) {
1672 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1673 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1674 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1676 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1677 // (X & 8) == 8 --> (X & 8) >> 3
1678 // Perform the xform if C1 is a single bit.
1679 if (C1.isPowerOf2()) {
1680 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1681 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1682 DAG.getConstant(C1.logBase2(), ShiftTy)));
1687 if (C1.getMinSignedBits() <= 64 &&
1688 !isLegalICmpImmediate(C1.getSExtValue())) {
1689 // (X & -256) == 256 -> (X >> 8) == 1
1690 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1691 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1692 if (ConstantSDNode *AndRHS =
1693 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1694 const APInt &AndRHSC = AndRHS->getAPIntValue();
1695 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1696 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1697 EVT ShiftTy = DCI.isBeforeLegalize() ?
1698 getPointerTy() : getShiftAmountTy(N0.getValueType());
1699 EVT CmpTy = N0.getValueType();
1700 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1701 DAG.getConstant(ShiftBits, ShiftTy));
1702 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1703 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1706 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1707 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1708 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1709 // X < 0x100000000 -> (X >> 32) < 1
1710 // X >= 0x100000000 -> (X >> 32) >= 1
1711 // X <= 0x0ffffffff -> (X >> 32) < 1
1712 // X > 0x0ffffffff -> (X >> 32) >= 1
1715 ISD::CondCode NewCond = Cond;
1717 ShiftBits = C1.countTrailingOnes();
1719 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1721 ShiftBits = C1.countTrailingZeros();
1723 NewC = NewC.lshr(ShiftBits);
1724 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1725 EVT ShiftTy = DCI.isBeforeLegalize() ?
1726 getPointerTy() : getShiftAmountTy(N0.getValueType());
1727 EVT CmpTy = N0.getValueType();
1728 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1729 DAG.getConstant(ShiftBits, ShiftTy));
1730 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1731 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1737 if (isa<ConstantFPSDNode>(N0.getNode())) {
1738 // Constant fold or commute setcc.
1739 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1740 if (O.getNode()) return O;
1741 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1742 // If the RHS of an FP comparison is a constant, simplify it away in
1744 if (CFP->getValueAPF().isNaN()) {
1745 // If an operand is known to be a nan, we can fold it.
1746 switch (ISD::getUnorderedFlavor(Cond)) {
1747 default: llvm_unreachable("Unknown flavor!");
1748 case 0: // Known false.
1749 return DAG.getConstant(0, VT);
1750 case 1: // Known true.
1751 return DAG.getConstant(1, VT);
1752 case 2: // Undefined.
1753 return DAG.getUNDEF(VT);
1757 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1758 // constant if knowing that the operand is non-nan is enough. We prefer to
1759 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1761 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1762 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1764 // If the condition is not legal, see if we can find an equivalent one
1766 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1767 // If the comparison was an awkward floating-point == or != and one of
1768 // the comparison operands is infinity or negative infinity, convert the
1769 // condition to a less-awkward <= or >=.
1770 if (CFP->getValueAPF().isInfinity()) {
1771 if (CFP->getValueAPF().isNegative()) {
1772 if (Cond == ISD::SETOEQ &&
1773 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1774 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1775 if (Cond == ISD::SETUEQ &&
1776 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1777 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1778 if (Cond == ISD::SETUNE &&
1779 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1780 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1781 if (Cond == ISD::SETONE &&
1782 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1783 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1785 if (Cond == ISD::SETOEQ &&
1786 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1787 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1788 if (Cond == ISD::SETUEQ &&
1789 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1790 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1791 if (Cond == ISD::SETUNE &&
1792 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1793 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1794 if (Cond == ISD::SETONE &&
1795 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1796 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1803 // The sext(setcc()) => setcc() optimization relies on the appropriate
1804 // constant being emitted.
1806 switch (getBooleanContents(N0.getValueType())) {
1807 case UndefinedBooleanContent:
1808 case ZeroOrOneBooleanContent:
1809 EqVal = ISD::isTrueWhenEqual(Cond);
1811 case ZeroOrNegativeOneBooleanContent:
1812 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1816 // We can always fold X == X for integer setcc's.
1817 if (N0.getValueType().isInteger()) {
1818 return DAG.getConstant(EqVal, VT);
1820 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1821 if (UOF == 2) // FP operators that are undefined on NaNs.
1822 return DAG.getConstant(EqVal, VT);
1823 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1824 return DAG.getConstant(EqVal, VT);
1825 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1826 // if it is not already.
1827 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1828 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1829 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1830 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1833 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1834 N0.getValueType().isInteger()) {
1835 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1836 N0.getOpcode() == ISD::XOR) {
1837 // Simplify (X+Y) == (X+Z) --> Y == Z
1838 if (N0.getOpcode() == N1.getOpcode()) {
1839 if (N0.getOperand(0) == N1.getOperand(0))
1840 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1841 if (N0.getOperand(1) == N1.getOperand(1))
1842 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1843 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1844 // If X op Y == Y op X, try other combinations.
1845 if (N0.getOperand(0) == N1.getOperand(1))
1846 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1848 if (N0.getOperand(1) == N1.getOperand(0))
1849 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1854 // If RHS is a legal immediate value for a compare instruction, we need
1855 // to be careful about increasing register pressure needlessly.
1856 bool LegalRHSImm = false;
1858 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1859 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1860 // Turn (X+C1) == C2 --> X == C2-C1
1861 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1862 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1863 DAG.getConstant(RHSC->getAPIntValue()-
1864 LHSR->getAPIntValue(),
1865 N0.getValueType()), Cond);
1868 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1869 if (N0.getOpcode() == ISD::XOR)
1870 // If we know that all of the inverted bits are zero, don't bother
1871 // performing the inversion.
1872 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1874 DAG.getSetCC(dl, VT, N0.getOperand(0),
1875 DAG.getConstant(LHSR->getAPIntValue() ^
1876 RHSC->getAPIntValue(),
1881 // Turn (C1-X) == C2 --> X == C1-C2
1882 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1883 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1885 DAG.getSetCC(dl, VT, N0.getOperand(1),
1886 DAG.getConstant(SUBC->getAPIntValue() -
1887 RHSC->getAPIntValue(),
1893 // Could RHSC fold directly into a compare?
1894 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1895 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1898 // Simplify (X+Z) == X --> Z == 0
1899 // Don't do this if X is an immediate that can fold into a cmp
1900 // instruction and X+Z has other uses. It could be an induction variable
1901 // chain, and the transform would increase register pressure.
1902 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1903 if (N0.getOperand(0) == N1)
1904 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1905 DAG.getConstant(0, N0.getValueType()), Cond);
1906 if (N0.getOperand(1) == N1) {
1907 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1908 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1909 DAG.getConstant(0, N0.getValueType()), Cond);
1910 if (N0.getNode()->hasOneUse()) {
1911 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1912 // (Z-X) == X --> Z == X<<1
1913 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1914 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1915 if (!DCI.isCalledByLegalizer())
1916 DCI.AddToWorklist(SH.getNode());
1917 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1923 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1924 N1.getOpcode() == ISD::XOR) {
1925 // Simplify X == (X+Z) --> Z == 0
1926 if (N1.getOperand(0) == N0)
1927 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1928 DAG.getConstant(0, N1.getValueType()), Cond);
1929 if (N1.getOperand(1) == N0) {
1930 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1931 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1932 DAG.getConstant(0, N1.getValueType()), Cond);
1933 if (N1.getNode()->hasOneUse()) {
1934 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1935 // X == (Z-X) --> X<<1 == Z
1936 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1937 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1938 if (!DCI.isCalledByLegalizer())
1939 DCI.AddToWorklist(SH.getNode());
1940 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1945 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1946 // Note that where y is variable and is known to have at most
1947 // one bit set (for example, if it is z&1) we cannot do this;
1948 // the expressions are not equivalent when y==0.
1949 if (N0.getOpcode() == ISD::AND)
1950 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1951 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1952 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1953 if (DCI.isBeforeLegalizeOps() ||
1954 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1955 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1956 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1960 if (N1.getOpcode() == ISD::AND)
1961 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1962 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1963 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1964 if (DCI.isBeforeLegalizeOps() ||
1965 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1966 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1967 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1973 // Fold away ALL boolean setcc's.
1975 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1977 default: llvm_unreachable("Unknown integer setcc!");
1978 case ISD::SETEQ: // X == Y -> ~(X^Y)
1979 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1980 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1981 if (!DCI.isCalledByLegalizer())
1982 DCI.AddToWorklist(Temp.getNode());
1984 case ISD::SETNE: // X != Y --> (X^Y)
1985 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1987 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1988 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1989 Temp = DAG.getNOT(dl, N0, MVT::i1);
1990 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1991 if (!DCI.isCalledByLegalizer())
1992 DCI.AddToWorklist(Temp.getNode());
1994 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1995 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1996 Temp = DAG.getNOT(dl, N1, MVT::i1);
1997 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1998 if (!DCI.isCalledByLegalizer())
1999 DCI.AddToWorklist(Temp.getNode());
2001 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2002 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2003 Temp = DAG.getNOT(dl, N0, MVT::i1);
2004 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2005 if (!DCI.isCalledByLegalizer())
2006 DCI.AddToWorklist(Temp.getNode());
2008 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2009 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2010 Temp = DAG.getNOT(dl, N1, MVT::i1);
2011 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2014 if (VT != MVT::i1) {
2015 if (!DCI.isCalledByLegalizer())
2016 DCI.AddToWorklist(N0.getNode());
2017 // FIXME: If running after legalize, we probably can't do this.
2018 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2023 // Could not fold it.
2027 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2028 /// node is a GlobalAddress + offset.
2029 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2030 int64_t &Offset) const {
2031 if (isa<GlobalAddressSDNode>(N)) {
2032 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2033 GA = GASD->getGlobal();
2034 Offset += GASD->getOffset();
2038 if (N->getOpcode() == ISD::ADD) {
2039 SDValue N1 = N->getOperand(0);
2040 SDValue N2 = N->getOperand(1);
2041 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2042 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2044 Offset += V->getSExtValue();
2047 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2048 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2050 Offset += V->getSExtValue();
2060 SDValue TargetLowering::
2061 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2062 // Default implementation: no optimization.
2066 //===----------------------------------------------------------------------===//
2067 // Inline Assembler Implementation Methods
2068 //===----------------------------------------------------------------------===//
2071 TargetLowering::ConstraintType
2072 TargetLowering::getConstraintType(const std::string &Constraint) const {
2073 unsigned S = Constraint.size();
2076 switch (Constraint[0]) {
2078 case 'r': return C_RegisterClass;
2080 case 'o': // offsetable
2081 case 'V': // not offsetable
2083 case 'i': // Simple Integer or Relocatable Constant
2084 case 'n': // Simple Integer
2085 case 'E': // Floating Point Constant
2086 case 'F': // Floating Point Constant
2087 case 's': // Relocatable Constant
2088 case 'p': // Address.
2089 case 'X': // Allow ANY value.
2090 case 'I': // Target registers.
2104 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2105 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
2112 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2113 /// with another that has more specific requirements based on the type of the
2114 /// corresponding operand.
2115 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2116 if (ConstraintVT.isInteger())
2118 if (ConstraintVT.isFloatingPoint())
2119 return "f"; // works for many targets
2123 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2124 /// vector. If it is invalid, don't add anything to Ops.
2125 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2126 std::string &Constraint,
2127 std::vector<SDValue> &Ops,
2128 SelectionDAG &DAG) const {
2130 if (Constraint.length() > 1) return;
2132 char ConstraintLetter = Constraint[0];
2133 switch (ConstraintLetter) {
2135 case 'X': // Allows any operand; labels (basic block) use this.
2136 if (Op.getOpcode() == ISD::BasicBlock) {
2141 case 'i': // Simple Integer or Relocatable Constant
2142 case 'n': // Simple Integer
2143 case 's': { // Relocatable Constant
2144 // These operands are interested in values of the form (GV+C), where C may
2145 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2146 // is possible and fine if either GV or C are missing.
2147 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2148 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2150 // If we have "(add GV, C)", pull out GV/C
2151 if (Op.getOpcode() == ISD::ADD) {
2152 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2153 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2155 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2156 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2159 C = nullptr, GA = nullptr;
2162 // If we find a valid operand, map to the TargetXXX version so that the
2163 // value itself doesn't get selected.
2164 if (GA) { // Either &GV or &GV+C
2165 if (ConstraintLetter != 'n') {
2166 int64_t Offs = GA->getOffset();
2167 if (C) Offs += C->getZExtValue();
2168 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2169 C ? SDLoc(C) : SDLoc(),
2170 Op.getValueType(), Offs));
2174 if (C) { // just C, no GV.
2175 // Simple constants are not allowed for 's'.
2176 if (ConstraintLetter != 's') {
2177 // gcc prints these as sign extended. Sign extend value to 64 bits
2178 // now; without this it would get ZExt'd later in
2179 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2180 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2190 std::pair<unsigned, const TargetRegisterClass *>
2191 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
2192 const std::string &Constraint,
2194 if (Constraint.empty() || Constraint[0] != '{')
2195 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2196 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2198 // Remove the braces from around the name.
2199 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2201 std::pair<unsigned, const TargetRegisterClass*> R =
2202 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2204 // Figure out which register class contains this reg.
2205 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2206 E = RI->regclass_end(); RCI != E; ++RCI) {
2207 const TargetRegisterClass *RC = *RCI;
2209 // If none of the value types for this register class are valid, we
2210 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2214 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2216 if (RegName.equals_lower(RI->getName(*I))) {
2217 std::pair<unsigned, const TargetRegisterClass*> S =
2218 std::make_pair(*I, RC);
2220 // If this register class has the requested value type, return it,
2221 // otherwise keep searching and return the first class found
2222 // if no other is found which explicitly has the requested type.
2223 if (RC->hasType(VT))
2234 //===----------------------------------------------------------------------===//
2235 // Constraint Selection.
2237 /// isMatchingInputConstraint - Return true of this is an input operand that is
2238 /// a matching constraint like "4".
2239 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2240 assert(!ConstraintCode.empty() && "No known constraint!");
2241 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2244 /// getMatchedOperand - If this is an input matching constraint, this method
2245 /// returns the output operand it matches.
2246 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2247 assert(!ConstraintCode.empty() && "No known constraint!");
2248 return atoi(ConstraintCode.c_str());
2252 /// ParseConstraints - Split up the constraint string from the inline
2253 /// assembly value into the specific constraints and their prefixes,
2254 /// and also tie in the associated operand values.
2255 /// If this returns an empty vector, and if the constraint string itself
2256 /// isn't empty, there was an error parsing.
2257 TargetLowering::AsmOperandInfoVector
2258 TargetLowering::ParseConstraints(const TargetRegisterInfo *TRI,
2259 ImmutableCallSite CS) const {
2260 /// ConstraintOperands - Information about all of the constraints.
2261 AsmOperandInfoVector ConstraintOperands;
2262 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2263 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2265 // Do a prepass over the constraints, canonicalizing them, and building up the
2266 // ConstraintOperands list.
2267 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2268 unsigned ResNo = 0; // ResNo - The result number of the next output.
2270 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
2271 ConstraintOperands.emplace_back(std::move(CI));
2272 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2274 // Update multiple alternative constraint count.
2275 if (OpInfo.multipleAlternatives.size() > maCount)
2276 maCount = OpInfo.multipleAlternatives.size();
2278 OpInfo.ConstraintVT = MVT::Other;
2280 // Compute the value type for each operand.
2281 switch (OpInfo.Type) {
2282 case InlineAsm::isOutput:
2283 // Indirect outputs just consume an argument.
2284 if (OpInfo.isIndirect) {
2285 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2289 // The return value of the call is this value. As such, there is no
2290 // corresponding argument.
2291 assert(!CS.getType()->isVoidTy() &&
2293 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2294 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2296 assert(ResNo == 0 && "Asm only has one result!");
2297 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2301 case InlineAsm::isInput:
2302 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2304 case InlineAsm::isClobber:
2309 if (OpInfo.CallOperandVal) {
2310 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2311 if (OpInfo.isIndirect) {
2312 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2314 report_fatal_error("Indirect operand for inline asm not a pointer!");
2315 OpTy = PtrTy->getElementType();
2318 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2319 if (StructType *STy = dyn_cast<StructType>(OpTy))
2320 if (STy->getNumElements() == 1)
2321 OpTy = STy->getElementType(0);
2323 // If OpTy is not a single value, it may be a struct/union that we
2324 // can tile with integers.
2325 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2326 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2335 OpInfo.ConstraintVT =
2336 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2339 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2341 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2342 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2344 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2349 // If we have multiple alternative constraints, select the best alternative.
2350 if (!ConstraintOperands.empty()) {
2352 unsigned bestMAIndex = 0;
2353 int bestWeight = -1;
2354 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2357 // Compute the sums of the weights for each alternative, keeping track
2358 // of the best (highest weight) one so far.
2359 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2361 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2362 cIndex != eIndex; ++cIndex) {
2363 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2364 if (OpInfo.Type == InlineAsm::isClobber)
2367 // If this is an output operand with a matching input operand,
2368 // look up the matching input. If their types mismatch, e.g. one
2369 // is an integer, the other is floating point, or their sizes are
2370 // different, flag it as an maCantMatch.
2371 if (OpInfo.hasMatchingInput()) {
2372 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2373 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2374 if ((OpInfo.ConstraintVT.isInteger() !=
2375 Input.ConstraintVT.isInteger()) ||
2376 (OpInfo.ConstraintVT.getSizeInBits() !=
2377 Input.ConstraintVT.getSizeInBits())) {
2378 weightSum = -1; // Can't match.
2383 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2388 weightSum += weight;
2391 if (weightSum > bestWeight) {
2392 bestWeight = weightSum;
2393 bestMAIndex = maIndex;
2397 // Now select chosen alternative in each constraint.
2398 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2399 cIndex != eIndex; ++cIndex) {
2400 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2401 if (cInfo.Type == InlineAsm::isClobber)
2403 cInfo.selectAlternative(bestMAIndex);
2408 // Check and hook up tied operands, choose constraint code to use.
2409 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2410 cIndex != eIndex; ++cIndex) {
2411 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2413 // If this is an output operand with a matching input operand, look up the
2414 // matching input. If their types mismatch, e.g. one is an integer, the
2415 // other is floating point, or their sizes are different, flag it as an
2417 if (OpInfo.hasMatchingInput()) {
2418 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2420 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2421 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2422 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
2423 OpInfo.ConstraintVT);
2424 std::pair<unsigned, const TargetRegisterClass *> InputRC =
2425 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
2426 Input.ConstraintVT);
2427 if ((OpInfo.ConstraintVT.isInteger() !=
2428 Input.ConstraintVT.isInteger()) ||
2429 (MatchRC.second != InputRC.second)) {
2430 report_fatal_error("Unsupported asm: input constraint"
2431 " with a matching output constraint of"
2432 " incompatible type!");
2439 return ConstraintOperands;
2443 /// getConstraintGenerality - Return an integer indicating how general CT
2445 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2447 case TargetLowering::C_Other:
2448 case TargetLowering::C_Unknown:
2450 case TargetLowering::C_Register:
2452 case TargetLowering::C_RegisterClass:
2454 case TargetLowering::C_Memory:
2457 llvm_unreachable("Invalid constraint type");
2460 /// Examine constraint type and operand type and determine a weight value.
2461 /// This object must already have been set up with the operand type
2462 /// and the current alternative constraint selected.
2463 TargetLowering::ConstraintWeight
2464 TargetLowering::getMultipleConstraintMatchWeight(
2465 AsmOperandInfo &info, int maIndex) const {
2466 InlineAsm::ConstraintCodeVector *rCodes;
2467 if (maIndex >= (int)info.multipleAlternatives.size())
2468 rCodes = &info.Codes;
2470 rCodes = &info.multipleAlternatives[maIndex].Codes;
2471 ConstraintWeight BestWeight = CW_Invalid;
2473 // Loop over the options, keeping track of the most general one.
2474 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2475 ConstraintWeight weight =
2476 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2477 if (weight > BestWeight)
2478 BestWeight = weight;
2484 /// Examine constraint type and operand type and determine a weight value.
2485 /// This object must already have been set up with the operand type
2486 /// and the current alternative constraint selected.
2487 TargetLowering::ConstraintWeight
2488 TargetLowering::getSingleConstraintMatchWeight(
2489 AsmOperandInfo &info, const char *constraint) const {
2490 ConstraintWeight weight = CW_Invalid;
2491 Value *CallOperandVal = info.CallOperandVal;
2492 // If we don't have a value, we can't do a match,
2493 // but allow it at the lowest weight.
2494 if (!CallOperandVal)
2496 // Look at the constraint type.
2497 switch (*constraint) {
2498 case 'i': // immediate integer.
2499 case 'n': // immediate integer with a known value.
2500 if (isa<ConstantInt>(CallOperandVal))
2501 weight = CW_Constant;
2503 case 's': // non-explicit intregal immediate.
2504 if (isa<GlobalValue>(CallOperandVal))
2505 weight = CW_Constant;
2507 case 'E': // immediate float if host format.
2508 case 'F': // immediate float.
2509 if (isa<ConstantFP>(CallOperandVal))
2510 weight = CW_Constant;
2512 case '<': // memory operand with autodecrement.
2513 case '>': // memory operand with autoincrement.
2514 case 'm': // memory operand.
2515 case 'o': // offsettable memory operand
2516 case 'V': // non-offsettable memory operand
2519 case 'r': // general register.
2520 case 'g': // general register, memory operand or immediate integer.
2521 // note: Clang converts "g" to "imr".
2522 if (CallOperandVal->getType()->isIntegerTy())
2523 weight = CW_Register;
2525 case 'X': // any operand.
2527 weight = CW_Default;
2533 /// ChooseConstraint - If there are multiple different constraints that we
2534 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2535 /// This is somewhat tricky: constraints fall into four classes:
2536 /// Other -> immediates and magic values
2537 /// Register -> one specific register
2538 /// RegisterClass -> a group of regs
2539 /// Memory -> memory
2540 /// Ideally, we would pick the most specific constraint possible: if we have
2541 /// something that fits into a register, we would pick it. The problem here
2542 /// is that if we have something that could either be in a register or in
2543 /// memory that use of the register could cause selection of *other*
2544 /// operands to fail: they might only succeed if we pick memory. Because of
2545 /// this the heuristic we use is:
2547 /// 1) If there is an 'other' constraint, and if the operand is valid for
2548 /// that constraint, use it. This makes us take advantage of 'i'
2549 /// constraints when available.
2550 /// 2) Otherwise, pick the most general constraint present. This prefers
2551 /// 'm' over 'r', for example.
2553 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2554 const TargetLowering &TLI,
2555 SDValue Op, SelectionDAG *DAG) {
2556 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2557 unsigned BestIdx = 0;
2558 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2559 int BestGenerality = -1;
2561 // Loop over the options, keeping track of the most general one.
2562 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2563 TargetLowering::ConstraintType CType =
2564 TLI.getConstraintType(OpInfo.Codes[i]);
2566 // If this is an 'other' constraint, see if the operand is valid for it.
2567 // For example, on X86 we might have an 'rI' constraint. If the operand
2568 // is an integer in the range [0..31] we want to use I (saving a load
2569 // of a register), otherwise we must use 'r'.
2570 if (CType == TargetLowering::C_Other && Op.getNode()) {
2571 assert(OpInfo.Codes[i].size() == 1 &&
2572 "Unhandled multi-letter 'other' constraint");
2573 std::vector<SDValue> ResultOps;
2574 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2576 if (!ResultOps.empty()) {
2583 // Things with matching constraints can only be registers, per gcc
2584 // documentation. This mainly affects "g" constraints.
2585 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2588 // This constraint letter is more general than the previous one, use it.
2589 int Generality = getConstraintGenerality(CType);
2590 if (Generality > BestGenerality) {
2593 BestGenerality = Generality;
2597 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2598 OpInfo.ConstraintType = BestType;
2601 /// ComputeConstraintToUse - Determines the constraint code and constraint
2602 /// type to use for the specific AsmOperandInfo, setting
2603 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2604 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2606 SelectionDAG *DAG) const {
2607 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2609 // Single-letter constraints ('r') are very common.
2610 if (OpInfo.Codes.size() == 1) {
2611 OpInfo.ConstraintCode = OpInfo.Codes[0];
2612 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2614 ChooseConstraint(OpInfo, *this, Op, DAG);
2617 // 'X' matches anything.
2618 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2619 // Labels and constants are handled elsewhere ('X' is the only thing
2620 // that matches labels). For Functions, the type here is the type of
2621 // the result, which is not what we want to look at; leave them alone.
2622 Value *v = OpInfo.CallOperandVal;
2623 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2624 OpInfo.CallOperandVal = v;
2628 // Otherwise, try to resolve it to something we know about by looking at
2629 // the actual operand type.
2630 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2631 OpInfo.ConstraintCode = Repl;
2632 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2637 /// \brief Given an exact SDIV by a constant, create a multiplication
2638 /// with the multiplicative inverse of the constant.
2639 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2640 SelectionDAG &DAG) const {
2641 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2642 APInt d = C->getAPIntValue();
2643 assert(d != 0 && "Division by zero!");
2645 // Shift the value upfront if it is even, so the LSB is one.
2646 unsigned ShAmt = d.countTrailingZeros();
2648 // TODO: For UDIV use SRL instead of SRA.
2649 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2650 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2655 // Calculate the multiplicative inverse, using Newton's method.
2657 while ((t = d*xn) != 1)
2658 xn *= APInt(d.getBitWidth(), 2) - t;
2660 Op2 = DAG.getConstant(xn, Op1.getValueType());
2661 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2664 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2665 /// return a DAG expression to select that will generate the same value by
2666 /// multiplying by a magic number.
2667 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2668 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2669 SelectionDAG &DAG, bool IsAfterLegalization,
2670 std::vector<SDNode *> *Created) const {
2671 assert(Created && "No vector to hold sdiv ops.");
2673 EVT VT = N->getValueType(0);
2676 // Check to see if we can do this.
2677 // FIXME: We should be more aggressive here.
2678 if (!isTypeLegal(VT))
2681 APInt::ms magics = Divisor.magic();
2683 // Multiply the numerator (operand 0) by the magic value
2684 // FIXME: We should support doing a MUL in a wider type
2686 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2687 isOperationLegalOrCustom(ISD::MULHS, VT))
2688 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2689 DAG.getConstant(magics.m, VT));
2690 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2691 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2692 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2694 DAG.getConstant(magics.m, VT)).getNode(), 1);
2696 return SDValue(); // No mulhs or equvialent
2697 // If d > 0 and m < 0, add the numerator
2698 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2699 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2700 Created->push_back(Q.getNode());
2702 // If d < 0 and m > 0, subtract the numerator.
2703 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2704 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2705 Created->push_back(Q.getNode());
2707 // Shift right algebraic if shift value is nonzero
2709 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2710 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2711 Created->push_back(Q.getNode());
2713 // Extract the sign bit and add it to the quotient
2714 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2715 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2716 getShiftAmountTy(Q.getValueType())));
2717 Created->push_back(T.getNode());
2718 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2721 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2722 /// return a DAG expression to select that will generate the same value by
2723 /// multiplying by a magic number.
2724 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2725 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2726 SelectionDAG &DAG, bool IsAfterLegalization,
2727 std::vector<SDNode *> *Created) const {
2728 assert(Created && "No vector to hold udiv ops.");
2730 EVT VT = N->getValueType(0);
2733 // Check to see if we can do this.
2734 // FIXME: We should be more aggressive here.
2735 if (!isTypeLegal(VT))
2738 // FIXME: We should use a narrower constant when the upper
2739 // bits are known to be zero.
2740 APInt::mu magics = Divisor.magicu();
2742 SDValue Q = N->getOperand(0);
2744 // If the divisor is even, we can avoid using the expensive fixup by shifting
2745 // the divided value upfront.
2746 if (magics.a != 0 && !Divisor[0]) {
2747 unsigned Shift = Divisor.countTrailingZeros();
2748 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2749 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2750 Created->push_back(Q.getNode());
2752 // Get magic number for the shifted divisor.
2753 magics = Divisor.lshr(Shift).magicu(Shift);
2754 assert(magics.a == 0 && "Should use cheap fixup now");
2757 // Multiply the numerator (operand 0) by the magic value
2758 // FIXME: We should support doing a MUL in a wider type
2759 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2760 isOperationLegalOrCustom(ISD::MULHU, VT))
2761 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2762 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2763 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2764 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2765 DAG.getConstant(magics.m, VT)).getNode(), 1);
2767 return SDValue(); // No mulhu or equvialent
2769 Created->push_back(Q.getNode());
2771 if (magics.a == 0) {
2772 assert(magics.s < Divisor.getBitWidth() &&
2773 "We shouldn't generate an undefined shift!");
2774 return DAG.getNode(ISD::SRL, dl, VT, Q,
2775 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2777 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2778 Created->push_back(NPQ.getNode());
2779 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2780 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2781 Created->push_back(NPQ.getNode());
2782 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2783 Created->push_back(NPQ.getNode());
2784 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2785 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2789 bool TargetLowering::
2790 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2791 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2792 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2793 "be a constant integer");
2800 //===----------------------------------------------------------------------===//
2801 // Legalization Utilities
2802 //===----------------------------------------------------------------------===//
2804 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2805 SelectionDAG &DAG, SDValue LL, SDValue LH,
2806 SDValue RL, SDValue RH) const {
2807 EVT VT = N->getValueType(0);
2810 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2811 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2812 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2813 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2814 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2815 unsigned OuterBitSize = VT.getSizeInBits();
2816 unsigned InnerBitSize = HiLoVT.getSizeInBits();
2817 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2818 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2820 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2821 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2822 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2824 if (!LL.getNode() && !RL.getNode() &&
2825 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2826 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2827 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2833 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2834 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2835 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2836 // The inputs are both zero-extended.
2838 // We can emit a umul_lohi.
2839 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2841 Hi = SDValue(Lo.getNode(), 1);
2845 // We can emit a mulhu+mul.
2846 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2847 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2851 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2852 // The input values are both sign-extended.
2854 // We can emit a smul_lohi.
2855 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2857 Hi = SDValue(Lo.getNode(), 1);
2861 // We can emit a mulhs+mul.
2862 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2863 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2868 if (!LH.getNode() && !RH.getNode() &&
2869 isOperationLegalOrCustom(ISD::SRL, VT) &&
2870 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2871 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2872 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
2873 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2874 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2875 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2876 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2883 // Lo,Hi = umul LHS, RHS.
2884 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2885 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2887 Hi = UMulLOHI.getValue(1);
2888 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2889 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2890 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2891 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2895 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2896 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2897 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2898 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2899 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2900 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2907 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
2908 SelectionDAG &DAG) const {
2909 EVT VT = Node->getOperand(0).getValueType();
2910 EVT NVT = Node->getValueType(0);
2911 SDLoc dl(SDValue(Node, 0));
2913 // FIXME: Only f32 to i64 conversions are supported.
2914 if (VT != MVT::f32 || NVT != MVT::i64)
2917 // Expand f32 -> i64 conversion
2918 // This algorithm comes from compiler-rt's implementation of fixsfdi:
2919 // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2920 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2921 VT.getSizeInBits());
2922 SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
2923 SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
2924 SDValue Bias = DAG.getConstant(127, IntVT);
2925 SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
2927 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
2928 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
2930 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2932 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2933 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2934 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2935 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2937 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2938 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2939 DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2940 Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2942 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2943 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2944 DAG.getConstant(0x00800000, IntVT));
2946 R = DAG.getZExtOrTrunc(R, dl, NVT);
2949 R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2950 DAG.getNode(ISD::SHL, dl, NVT, R,
2952 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
2953 dl, getShiftAmountTy(IntVT))),
2954 DAG.getNode(ISD::SRL, dl, NVT, R,
2956 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
2957 dl, getShiftAmountTy(IntVT))),
2960 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
2961 DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
2964 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
2965 DAG.getConstant(0, NVT), Ret, ISD::SETLT);